TLE7241E

Data Sheet, Rev. 1.1, Jan. 2009 TLE 7241E Dual Channel Constant Current Control Solenoid Driver Automotive Power TLE 7241E Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 1.1 1.2 1.3 2 3 4 4.1 5 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.6 5.6.1 5.6.2 6 6.1 7 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 4 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Description and Electrical Characteristics . . . . . . . . . . . . Supply and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Sensing and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent / Short to VBAT Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load / Short to Ground Detection . . . . . . . . . . . . . . . . . . . . . . . . Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hysteretic Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dither Control and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Command Out of Range / Dither Clipping . . . . . . . . . . . . . . . . . . Error Correction Registers / Average Switch Threshold Trimming . . . . SPI Command and Diagnosis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 16 16 17 21 28 30 30 37 43 44 46 46 52 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Layout Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Data Sheet 2 Rev. 1.1, 2009-01-19 Dual Channel Constant Current Control Solenoid Driver TLE 7241E 1 1.1 • • • Overview Features PG-DSO-20-27 • • • • • • Two Fully Independent Channels Integrated N-channel DMOS transistors Programmable Average Current with 10-bit resolution via SPI – Iavg range = 0 to 1000 mA (typical) Programmable Superimposed Dither – Programmable Frequency (41 Hz to 1 kHz typ) – Programmable Amplitude (12.5 to 390 mVpp typ) – Programmable Hysteresis (40 to 110 mVpp typ) Interface and Control – 16-bit SPI (Serial Peripheral Interface) daisy chainable – A single “Default” pin to disable both channels and reset the programmable registers of both channels – 5.0 V and 3.3 V logic compatible I/O – The contents of all registers can be verified via SPI – Operation with or without external reference possible Protection – Overcurrent – Overvoltage – Overtemperature Diagnostics – Overcurrent / shorted solenoid – Overtemperature – Open load – Short to GND Green Product (RoHS compliant) AEC Qualified Type TLE 7241E Data Sheet Ordering Code on request 3 Package PG-DSO-20-27 Rev. 1.1, 2009-01-19 TLE 7241E Overview 1.2 • • Applications Variable force solenoids (e.g. automatic transmission solenoids) Constant current controlled solenoids like – Idle Speed Control – Exhaust Gas Recirculation – Valve control – Suspension Control 1.3 General Description The TLE 7241E is a dual channel constant current control solenoid driver with integrated DMOS power transistors. The average load current can be programmed to a value in the range of 0 mA to 1000 mA (with a 1 Ω external sense resistor) with 10 bits of resolution. Load current is controlled using a hysteretic control scheme with a programmable hysteresis value. A triangular “dither” waveform can be superimposed on the switching current waveform in order to improve the transfer function of the solenoid. The amplitude and frequency of the dither waveform are programmable by the SPI interface. The device is protected from damage due to overcurrent, overvoltage and overtemperature conditions, and is able to diagnose and report open loads, shorted loads, and loads shorted to ground. Note: An external free-wheeling diode must be provided when using the TLE 7241E in constant current control mode, otherwise the IC will be damaged. For best accuracy, an external 2.5 V reference voltage should be supplied at the REF pin. The TLE 7241E also includes an internal 2.5 V reference voltage, which can be selected by connecting the REF pin to ground. The reference voltage selection (internal or external) can be verified via the SPI interface. Data Sheet 4 Rev. 1.1, 2009-01-19 TLE 7241E Overview Application Block Diagram VBAT VBAT VDD BAT REF OUT1 DEFAULT TEST Solenoid VBAT Logic Channel 1 NEG1 POS1 VSO SI SO BAT REF PGND1 VBAT SPI SCK CSB OUT2 Channel 2 NEG2 POS2 GND PGND2 Figure 1 Basic Application Diagram Data Sheet 5 Rev. 1.1, 2009-01-19 Solenoid TLE 7241E Overview Detailed Block Diagram REF 14 Vdd 6 BAT 16 Diagnostics & Protection * * * * * * Over t em p Open load while on Open load while of f shorted load load short ed t o ground Overvolt age (Vpwr) Int Vref Vcal detect Vref Register bank Status Fault type bit Dither Register Vbat Vdd Tem p Diff Amp + Vdd 4 3 POS1 NEG1 SPI Decoder VSO Average Current Control Circuit Logic and gate drive with overload protection 2 OUT1 DEFAULT TEST 7 Switching Hysteresis Slew Rate Error Cor Reg 200mv Error Cor Reg 400mv Error Cor Reg 600mv Error Cor Reg 800mv Error Cor Reg 1000mv Revision Code 1 PGND1 13 VSO CSB SCK SI 11 Dither Osc 9 8 CHANNEL #1 10 SPI Interface 17 18 POS2 NEG2 OUT2 PGND2 SO 12 19 CHANNEL #2 15 20 GND Figure 2 Detailed Block Diagram Data Sheet 6 Rev. 1.1, 2009-01-19 TLE 7241E Pin Configuration 2 Pin Configuration Pin Assignment PGND1 OUT1 NEG1 POS1 N.C. VDD DEFAULT SCK CSB SI 1 2 3 20 19 18 PGND2 OUT2 NEG2 POS2 BAT GND REF TEST SO VSO TLE 7241E EPGND 4 5 6 7 8 9 10 17 16 15 14 13 12 11 PINOUT.VSD Figure 3 Pin-Out Pin Definitions and Functions Pin 1 2 3 4 5 6 7 Pin Name PGND1 OUT1 NEG1 POS1 NC Pin Description Power Ground Channel 1; internally connected to PGND2 Output Channel 1; Drain of Output DMOS; connect to negative terminal of external sense resistor Negative Sense Pin Channel 1; connect to negative terminal of external sense resistor with dedicated trace Positive Sense Pin Channel 1; connect to positive terminal of external sense resistor with dedicated trace Not Connected; not bonded internally Logic Supply Voltage; connect a ceramic capacitor to GND near the device Control Input; Active high digital input. 3.3V and 5.0V logic compatible. In case of not used, connect to ground 7 Rev. 1.1, 2009-01-19 VDD DEFAULT Data Sheet TLE 7241E Pin Configuration Pin Definitions and Functions (cont’d) Pin 8 9 10 11 12 13 14 15 16 Pin Name SCK CSB SI Pin Description SPI Clock; Digital input pin. 3.3V and 5.0V logic compatible Chip Select Bar; Active low digital input pin. 3.3V and 5.0V logic compatible Serial Data Input; 3.3V and 5.0V logic compatible SPI Supply Voltage; connect a ceramic capacitor to GND near the device Serial Data Output; Supplied by Vso pin Test Pin; connect to GND Voltage Reference; connect to external 2.5 V reference, or connect to GND to enable internal reference. Ground; signal ground BAT Input; connect to the solenoid supply voltage through a series resistor. Connect a ceramic capacitor to GND near the device Positive Sense Pin Channel 2; connect to positive terminal of external sense resistor with dedicated trace Negative Sense Pin Channel 2; connect to negative terminal of external sense resistor with dedicated trace Output Channel 2; Drain of Output DMOS; connect to negative terminal of external sense resistor Power Ground Channel 2; internally connected to PGND1 GND; Should be connected to GND, PGND1 and PGND2 and to the ground plane of the ECU VSO SO TEST REF GND BAT 17 18 19 20 POS2 NEG2 OUT2 PGND2 Expose EPGND d Lead Frame Note: If a channel is unused, the OUTx, NEGx, and POSx pins should be connected together. Data Sheet 8 Rev. 1.1, 2009-01-19 TLE 7241E Maximum Ratings 3 Maximum Ratings Absolute Maximum Ratings1) Tj = -40 to 150 °C Pos. Parameter Voltages M.1 Supply Voltage BAT Symbol Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1.5 -1.5 -1.5 -1.5 -0.3 -0.3 Limit Values Max. 50 6.0 6.0 50 50 20 50 min. (6.0, VDD + 0.3) 6.0 6.0 6.0 min. (6.0, VSO + 0.3) min. (6.0, VSO + 0.3) Vdc – Vdc Vdc Vdc – Vdc Vdc Vdc – Vdc – Vdc Vdc Vdc Vdc Vdc Unit Notes VDD VSO M.2 Analog Input Voltage POSx NEGx POSx-NEGx M.3 M.4 Output Voltage Digital Input Voltage OUTx REF TEST SI SCK CSB DEFAULT SO BAT POSx NEGx OUTx GND PGNDx M.5 M.6 Digital Output Pin Voltage Dynamic Clamp Voltage Tclamp < 2.0 ms Ground Pin Voltage (GND) Difference between PGND1 and PGND2 Biased Junction Temperature min. (6.0, VSO + 0.3) Vdc – – – – – 0.3 0.3 V V V V – M.7 M.8 Vdc – Vdc – Others M.9 Tj Tst Emax -40 -55 – 150 150 30 °C °C mJ – – – M.10 Storage Temperature M.11 Single Clamp Energy (OUTx) I=1.0A Tj=150 °C Data Sheet 9 Rev. 1.1, 2009-01-19 TLE 7241E Maximum Ratings Absolute Maximum Ratings1) (cont’d) Tj = -40 to 150 °C Pos. Parameter M.12 ESD HBM all pins EIA/JESD22-A 114B (1.5 K Ω, 100 pF) M.13 ESD MM all pins EIA/JESD22-A115A (0 Ω, 200 pF) Symbol Min. – -2 Limit Values Max. +2 kV – Unit Notes – -200 200 V – 1) Not subject to production test, specified by design All voltages are with respect to PGND1 & 2. Positive current flows into the pin unless otherwise specified. Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data Sheet 10 Rev. 1.1, 2009-01-19 TLE 7241E Functional Range 4 Functional Range Functional Range Tj = -40 to 150 °C; VREF = 2.5V Pos. Parameter F.1 F.2 F.3 F.4 F.5 F.6 Voltage at BAT Voltage at VDD Voltage at VSO Voltage at SI, SCK Voltage at CSB, DEFAULT, SO Voltage at POS1, POS2, NEG1, NEG2, OUT1, OUT2 Voltage Difference POS1-NEG1, POS2-NEG2 Voltage at PGND1, PGND2, GND SPI Clock Frequency Symbol VBAT VDD VVSO VIN1 VIN2 VOUT, VPOS, VNEG VPOS VNEG VGND Limit Values Min. 9 4.75 3.1 -0.3 -0.3 -0.3 Max. 18 5.25 or 5.25V Unit V V Remarks – – – – – – VDD + 0.3 V VDD + 0.3 V VSO + 0.3 V 50 V F.7 0 1.23 V – F.8 F.9 -0.3 0.3 3.2 V – fclk -40 MHz CSO = 200 pF max; VVSO = 5 V °C – F.10 Junction Temperature Tj 150 Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Thermal Resistance 4.1 Pos. Parameter G.1 G.2 Junction to Case1) Junction to Ambient1) Symbol Min. Limit Values Typ. Max. Unit Conditions 2) 2) 3) RthjC RthjA 11 5.2 26 K/W K/W Data Sheet Rev. 1.1, 2009-01-19 TLE 7241E Functional Range 1) Not subject to production test, specified by design. 2) Both channels on with 1W power dissipation per channel 3) Specified RthJA value is according to Jedec JESD51-2, -5, -7 at natural convection on FR4 2s2p board. The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70mm Cu, 2 x 35 mm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner layer. Data Sheet 12 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5 Functional Description and Electrical Characteristics Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. 5.1 Supply and Reference The device has incorporated a power-on reset circuit. This feature will reset the commanded average current to 0 mA (device off), and will reset the programmable registers to their default values. The fault register bits are reset during power on reset. The device will remain off until a valid command is received. The device will also be reset in the case of an undervoltage condition on the pin VDD. Note that if the voltage on the pin REF pin is greater than the voltage on the pin VDD, a current will flow from the REF pin to the VDD pin. Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter 5.1.1 REF Bias Current 5.1.2 VDD 5 V Supply Current 5.1.3 VSO I/O Supply Current 5.1.4 BAT Supply Current Symbol Limit Values Min. Typ. – – 2) Max. 20 15 Unit Test Conditions and Instructions μA mA IREF IDD ISO IBAT -20 – VREF = 2.5 V (includes leakage current and a small current sink) VDD = 5.25 V; CSB = 5.0 V; DAC = 3FF – – 1 mA VSO = 5.25 V; CSB = 5.0 V – 2.5 – – 1 3.5 mA V VDD = 5.25 V; CSB = 5.0 V Power-On Reset Threshold Tested at wafer test. 5.1.5 VDD VPOR Power-On Reset Threshold 5.1.6 Internal Reference Voltage 2) Target @TJ = 25 °C VIREF 2.45 2.5 2.55 V 1) Positive current flow is into the device. Data Sheet 13 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.2 Input/Output The DEFAULT pin is an active high input. A weak pull-up current (typical 15 μA) on this pin ensures a defined level when this pin is not connected (e.g. open pin). An active high signal on the DEFAULT pin sets the commanded current for both channels to 0 mA, and resets all programmable registers to their default values. Any SPI commands that are received while the DEFAULT pin is high will be ignored, and the SO pin will remain in a high impedance state. The fault register bits are not cleared when the Default pin is asserted. Upon coming out of default mode, the commanded current will remain at 0 mA, device off, and the programmable registers will remain at their default values. The DEFAULT pin must be asserted high whenever the voltage on the pin VDD is less than the minimum VDD operating voltage (4.75 V), otherwise the electrical characteristic specifications (see table below) may not be met. The diagnostic functions are not operational when the VDD voltage is less than 4.75V. The TEST pin is an active high pin. This pin must be connected directly to ground in the application, as it is only used for IC test purposes. A passive pull-down resistor in the device ensures a logic low value when the pin is not connected. Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol Limit Values Min. Typ.2) Max. -10 20 – -5 – – Unit Test Conditions and Instructions μA kΩ V IDEFAULT -25 5.2.1 DEFAULT Input Bias Current 5.2.2 TEST RTEST Pull-down Resistor 5.2.3 SI, SCK, CSB, DEFAULT Input Threshold 5.2.4 SI, SCK, CSB, DEFAULT Input Threshold 5.2.5 SO Output High Voltage 5.2.6 SO Output Low Voltage 2) Target @TJ = 25 °C VDEFAULT = 0 V; – Pull-up source is pin VSO – 2.0 VIH VIL VOH VOL SCK is specified by design, not subject to production test. SCK is specified by design, not subject to production test. SO Io = -1 mA SO Io = 1 mA – – 0.8 V 0.8 – – – 0.4 V V VSO – 1) Positive current flow is into the device. Data Sheet 14 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.3 Power Output The slew rate of the voltage on the pins OUT1 and OUT2 are programmable via the SPI interface. The fast settings are intended for fast switching solenoids (low inductance) to minimize power dissipation within the TLE 7241E, and to minimize DC current error due to overshooting the switch points. The slower slew rates can be used with slower switching solenoids (high inductance) to improve radiated emissions from the wiring harness. Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol Limit Values Min. 5.3.1 OUTx rise and OUTx fall times Slew tR and tF Rate reg = 0 5.3.2 OUTx rise and OUTx fall times Slew tR and tF Rate reg = 1 5.3.3 OUTx rise and OUTx fall times Slew tR and tF Rate reg = 2 5.3.4 OUTx rise and OUTx fall times Slew tR and tF Rate reg = 3 5.3.5 OUTx Output Off Leakage (00H) 5.3.6 OUTx Output Off Leakage (00H) 0.25 Typ.2) Max. 0.5 1 Unit Test Conditions and Instructions μs Threshold: 4 V to 10 V VBAT = 14 V; Rload = 5 Ω Threshold: 4 V to 10 V VBAT = 14 V; Rload = 5 Ω Threshold: 4 V to 10 V VBAT = 14 V; Rload = 5 Ω Threshold: 4 V to 10 V VBAT = 14 V; Rload = 5 Ω 0.5 1 2 μs 1 2 4 μs 2.5 5 10 μs IDSS IDSS – – 10 μA VDS = 24 V VDS = VCLAMP - 1V VCLAMP is the measured – – 3 mA clamp voltage (Item 5.4.1.3) – 240 450 mΩ 5.3.7 OUTx3) Driver RDS(ON) on Resistance 1) Positive current flow is into the device. 2) TJ = 25 °C Driver on Resistance @TJ = 150 °C 3) Electrical Distributions must be performed on this parameter as defined in the AEC-Q100 Specification Table 2 test 27. Data Sheet 15 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.4 Protection and Control Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol 5.4.1 POS/NEG IBIAS 5.4.2 POS/NEG LEAKAGE Limit Values Min. POS/NEG -500 IBIAS POS/NEG 20 LEAKAGE -20 Typ. – 2) Max. 500 Unit Test Conditions and Instructions μA DAC command =3FF POS=NEG=0V & POS=NEG=17V Fault typing bit = 0, Zero Current, POS = NEG = 14 V Fault typing bit = 1, Zero Current, POS = NEG = 14 V 40 60 μA μA 0 20 1) Positive current flow is into the device. 2) TJ = 25 °C Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside normal operating range. Protections functions are not designed for continuous repetitive operation. 5.4.1 Overvoltage Sensing and Protection When the voltage on the BAT pin exceeds the Overvoltage Shutdown Threshold (see table below, Item 5.4.1.1), the output channel will shut off to protect the IC from excessive power dissipation. A short filter with a typical value of 6.5 μs is included to prevent undesired shutdown due to short transient voltage spikes. Although SPI communication will remain functional, the output will remain off. The device will resume normal operation when the BAT voltage has dropped below the overvoltage hysteresis level. Note that the programmable registers are not reset, and the dither counter continues to operate during an overvoltage event. Both channels are disabled when an overvoltage condition is detected. Data Sheet 16 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics OVER-VOLTAGE FAULT V POSx - VNEGx on LS-Switch state off t < tov Vov Vov-ovhyst Vpwr 14 V Figure 4 Overvoltage Shutdown Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol 30 – 50 Limit Values Min. 5.4.1.1 BAT Overvoltage OV Shutdown 5.4.1.2 BAT Overvoltage OVHYST hysteresis 5.4.1.3 OUTx Active Clamp Voltage 2) TJ = 25 °C 3) Not subject to production test, specified by design. Typ. 35 1.0 53 2) Max. 40 – 60 Unit Test Conditions and Instructions Vdc Ramp up BAT until outputs Off Vdc Ramp BAT down until outputs On3) V Vclamp Id = 20 mA, output off 1) Positive current flow is into the device. 5.4.2 Overcurrent / Short to VBAT Sensing An overcurrent fault is detected by sensing the voltage at the POS input pin. A comparator is used to detect the voltage while the gate drive is on. When the voltage at the POS input pin exceeds the short circuit / overcurrent threshold (see table below, Item 5.4.2.3) for a time greater than the short sense time (see table below, Item 5.4.2.1) Data Sheet 17 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics the driver will be turned off and the Overcurrent / Short to VBAT (VSHT) fault bit will be latched until the fault register is read via SPI. The driver will remain in the off condition for the short circuit refresh time (see table below, Item 5.4.2.2). After the refresh time, the driver will automatically turn on again. If the short condition is no longer present, the channel will operate normally. If the short circuit condition persists, the driver will be cycled off after the short sense time once again. The refresh time has been chosen for minimal increase in power dissipation during a continuous fault condition. In order to prevent false detection of an overcurrent / short to VBAT fault during an “off to on” transition of the low-side output transistor, the detection circuit is disabled for a blanking time (see “Electrical Characteristics” on Page 31, Item 5.5.1.1 and Item 5.5.1.2) after the transistor is enabled (see Figure 16 and Figure 17). The output transistor control circuit includes a current limit feature that will limit the transistor current to a maximum value (see table below, Item 5.4.2.4) in order to protect the device from excessive current flow. If a new average current command or configuration command is received for a shorted channel while that channel is within the short circuit refresh time, the new data will be stored but the channel will remain in the off state until the refresh time expires. The new data will become active when the short circuit condition is released. The Overcurrent / Short to VBAT detection is channel specific. Note: An Overcurrent / Short to VBAT fault is not detected if the average current command is 50ma G.C. cmd G.C. cmd G.C. cmd MOSI MISO G.C. response VSHT=0 A.C. G.C. response response EDG=0 VSHT=1 G.C. response VSHT=1 “. G.C. response VSHT=0 The Latched Fault State is sampled and stored in the SPI transmit register at the points marked with “ Figure 7 Short to VBAT - Channel Off Then Turned On Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol Limit Values Min. 5.4.2.1 OUTx Short Sense Time 5.4.2.2 OUTx Short Refresh Time 5.4.2.3 OUTx Short circuit/ Overcurrent Fault Threshold 5.4.2.4 OUTx Current Limit Typ.2) Max. 60 14 2.5 90 24 3.0 30 3 Unit Test Conditions and Instructions μs ms Vdc 50 - 50 Threshold 50 - 50 Threshold tss tref VVSHTOCT 2.0 VREF = 2.5 V Idlim 3.0 5.0 6.0 A VBAT = 14 V; VDD = 5V; output on 1) Positive current flow is into the device. 2) TJ = 25 °C Data Sheet 20 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.4.3 Open Load / Short to Ground Detection The OLSG fault bit is set under the following conditions. Operating Condition #1 The average current command is > 50 mA (with 1 Ω sense resistor) and the low-side driver is ON (solenoid current is increasing). The OLSG (open load/short to ground) fault bit will be set if the low-side transistor remains on for a time greater than the on state open sense time (“Electrical Characteristics” on Page 23, Item 5.4.3.3). Operating Condition #2 The average current command is > 50 mA (with 1 Ω sense resistor) and the low-side driver is OFF. The OLSG fault bit is set if the voltage on the NEGx pin is less than the NEG pin OLSG threshold voltage (“Electrical Characteristics” on Page 23, Item 5.4.3.6) for a time greater than the NEG pin OLSG delay time (“Electrical Characteristics” on Page 23, Item 5.4.3.5). Operating Condition #3 The average current command is < 50 mA (with a 1 Ω sense resistor) and the fault typing bit = 0. The OLSG (open load/short to ground) fault bit will be set if the POS pin voltage is less than the off state open load threshold (“Electrical Characteristics” on Page 20, Item 5.4.2.3) for longer than the off state open load sense time (“Electrical Characteristics” on Page 23, Item 5.4.3.4) or the NEG pin is less than the NEG pin OLSG threshold voltage (“Electrical Characteristics” on Page 23, Item 5.4.3.6) for a time greater than the NEG pin OLSG delay time (“Electrical Characteristics” on Page 23, Item 5.4.3.5). A pull-down current (“Electrical Characteristics” on Page 23, Item 5.4.3.1) will be activated between the POS pin and ground when the Fault Typing bit = 0. Operating Condition #4 The average current command is < 50 mA (with a 1 Ω sense resistor) and the fault typing bit = 1. The OLSG fault bit will be set when the voltage on the pin POSx is below the off state open load threshold (“Electrical Characteristics” on Page 20, Item 5.4.2.3) for the a time greater than tos(off) (“Electrical Characteristics” on Page 23, Item 5.4.3.4) or the NEG pin is less than the NEG pin OLSG threshold voltage (“Electrical Characteristics” on Page 23, Item 5.4.3.6) for a time greater than the NEG pin OLSG delay time Data Sheet 21 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics (“Electrical Characteristics” on Page 23, Item 5.4.3.5). A pull-up current (“Electrical Characteristics” on Page 23, Item 5.4.3.2) will be activated between VDD and the POS pin when the Fault Typing bit = 1. Distinguishing between Open Load and Short to Ground Faults When an Open Load/Short to Ground is flagged, to distinguish between Open Load and Short-To-Ground, a general configuration command word must be sent three times to the appropriate channel with the fault typing bit set, and the average current must be programmed to zero. Check the OL/SG fault bit from the third write. A ‘0’ signifies Open Load, ‘1’ signifies Short-To-Ground. A short to ground will still be flagged for 0 mA command current. Note that setting the fault typing bit under both normal & fault conditions does not change the status of the output or the current flowing. The fault typing bit enables a 40 μA pull-up current on the POS pin when high, and enables a 40 μA pull-down current on the POS pin when low. Data Sheet 22 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol 20 -60 Limit Values Min. 5.4.3.1 POS Open detect IOL current 5.4.3.2 POS Load short to ISG ground detect tos(on) 5.4.3.3 OUTx On-State open sense time – POS pin tos(off) 5.4.3.4 OUTx Off-State open sense time – POS pin Typ. 40 -40 2) Max. 60 -20 Unit Test Conditions and Instructions μA μA Fault typing bit = 0, Zero Current Fault typing bit = 1, Zero Current, POS = NEG = 2 V 50 - 50 Threshold3) 6 12 24 ms 30 60 90 μs 50 - 50 Threshold3) 5.4.3.5 NEGx Open load / TOLSG_N (off) short to ground filter time – NEG pin 5.4.3.6 NEGx Open load / VOLSG_N short to ground detection threshold – NEG pin 1) Positive current flow is into the device. 2) TJ = 25 °C 30 60 90 μs – 2.0 2.8 3.6 V – 3) Not subject to production test, tested by scanpath. Data Sheet 23 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Diagnostics Timing Diagrams OPEN CIRCUIT / SHORT TO GROUND FAULT - OCCURS & CLEARS WHILE ON VPOS - VNEG on Output transistor state Load State OL/SGx fault state OL/SGx latched fault state CSB off open ok t < tos (on) tos(on) MOSI MISO G.C. cmd G.C. response G.C. cmd G.C. response G.C. cmd G.C. response G.C. cmd G.C. response G.C. cmd G.C. response OLSG=0 OLSG=0 OLSG=1 OLSG=1 OLSG=0 The Latched Fault State is sampled and stored in the SPI transmit register at the points marked with “ “. Figure 8 Open Load / Short to Ground Fault - Channel On OPEN LOAD / LOAD SHORTED TO GROUND FAULT - OCCURS WHILE ON THEN CHANNEL IS TURNED OFF V POSx -VNEGx on LS-Switchx state Load State OL/SGx fault state off open ok tos(on) = 12ms tos(off)=60µs OL/SGx latched fault state CSB G.C. cmd G.C. cmd G.C. response G.C. response OLSG=1 “. A.C. cmd Iav=0ma G.C. cmd A.C. G.C. response response EDG=1 OLSG=1 MOSI MISO OLSG=0 The Latched Fault State is sampled and stored in the SPI transmit register at the points marked with “ Figure 9 Data Sheet Open Load / Short to Ground - Channel On Then Turned Off 24 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics OPEN CIRCUIT FAULT - OCCURS & CLEARS WHILE OFF 14V V POSx dVPOS/dt 2.5V open t < tos (off) Load State ok tos (off) OL/SGx fault state OL/SGx latched fault state CSB G.C. cmd G.C. cmd G.C. response G.C. cmd G.C. response MOSI G.C. response MISO OLSG=0 The Latched Fault State is sampled and stored in the SPI transmit register at the points marked with “ “. OLSG=1 OLSG=0 Figure 10 Open Load Short to Ground - Channel Off (1) d V POS – ( i OL – i Rrecirc ) ---------------- = ---------------------------------------------------------dt ( C POS + C NEG + C OUT ) iOL = open load detection pull down current (5.4.3.1) iRrecirc = reverse leakage current of recirculation diode CPOS = external capacitance on the POS pin CNEG = external capacitance of the NEG pin COUT = external capacitance on the OUT pin Data Sheet 25 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics OPEN CIRCUIT FAULT - OCCURS WHILE OFF THEN TURNED ON 14V VPOSx 2.5V open Load State ok tos (off) tos(on) = 12ms OL/SGx fault state OL/SGx latched fault state CSB G. C. cmd G. C. cmd A.C. cmd Iav>50ma G. C. cmd MOSI G. C. response G.C. response A.C. response G. C. response MISO OLSG=0 OLSG=1 EDG=1 “. OLSG=1 The Latched Faul t State i s sampl ed and stored in the SPI transmit regi ster at the points marked with “ Figure 11 Open Load / Short to Ground - Channel Off Then Turned On Data Sheet 26 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics OPEN CIRCUIT FAULT - OCCURS WHILE OFF THEN OPEN LOAD / SHORT TO GROUN D TEST IS PERFORMED 14V V POSx 2.5V dV POS/dt open Load State ok tos(off) tos (off) tos(off) OL/SGx fault state OL/SGx latched fault state CSB G.C. cmd G.C. cmd G.C. cmd FT=1 G.C. cmd FT=1 G.C. cmd FT=1 MOSI MISO G.C. response OLSG=0 G.C. response OLSG=1 “. G.C. G.C. G.C. response response response OLSG=1 OLSG=1 OLSG=0 The Latched Fault State is sampled and stored in the SPI transmit register at the points marked with “ Figure 12 Open Load - Fault Type Bit = 1 Test (2) d V POS – ( i SG – i Rrecirc ) ---------------- = ---------------------------------------------------------dt ( C POS + C NEG + C OUT ) iSG = short to ground detection pull up current (5.4.3.2) iRrecirc = reverse leakage current of recirculation diode CPOS = external capacitance on the POS pin CNEG = external capacitance of the NEG pin COUT = external capacitance on the OUT pin Data Sheet 27 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics SHORT TO GROUND FAULT - OCCURS & CLEARS WHILE OFF 14V VPOSx 2.5V Load State Short to GND t < tos (off) ok tos(off) tos(off) OL/SGx fault state OL/SGx latched fault state CSB G.C. cmd G.C. cmd G.C. cmd FT=1 G.C. cmd FT=1 G.C. cmd FT=1 G.C. cmd G.C. cmd MOSI G.C. response G.C. response OLSG=1 G.C. G.C. G.C. response response response OLSG=1 OLSG=1 OLS G=1 “. G.C. G.C. response response OLSG=1 OLSG=0 MISO OLSG=0 The Latched Fault State is sampled and stored in the SPI transmit register at the points marked with “ Figure 13 Short to Ground Fault Type Bit = 1 Test 5.4.4 Thermal Shutdown Each output transistor includes an independent thermal shutdown circuit. When the temperature of the output transistor exceeds a threshold value (see table below, Item 5.4.4.1), the output transistor will be turned off and a fault bit will be set for the failed channel. The transistor will remain off until the local transistor temperature has decreased by the thermal hysteresis value (see table below, Item 5.4.4.2), the output transistor will then turn on again. Thermal shutdown faults are channel specific. Note: A thermal fault is latched until read via the MISO return word. Data Sheet 28 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics ^ OVER-TEMPERATURE FAULT VP OSx - VNEGx on LS-Switchx state off OT shutdown Sensor x temp OT shutdown OT hyst OTMPx fault state OTMPx latched fault state CSB G.C. cmd G.C. cmd G.C. cmd G.C. cmd MOSI MISO G.C. response OTMP=0 G.C. response OTMP=1 G.C. response OTMP=1 “. G.C. response OTMP=0 The Latched Fault State is sampled and stored in the SPI transmit register at the points marked with “ Figure 14 Overtemperature Shutdown with Restart Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol OTsd Limit Values Min. Typ.2) Max. 5.4.4.1 OUTx Overtemperature shutdown threshold 5.4.4.2 OUTx Overtemperature hysteresis 2) TJ = 25 °C 3) Not subject to production test, specified by design. Unit Test Conditions and Instructions °C 3) 160 – 190 OThys – 10 – °C 3) 1) Positive current flow is into the device. Data Sheet 29 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.5 5.5.1 Current Control Hysteretic Current Control The TLE 7241E device uses a hysteretic control method to regulate the solenoid current. The output transistor is toggled on and off based on the measured value of the solenoid current. The solenoid current is measured at the pins POSx and NEGx which are connected to an external current sense resistor. The device calculates an upper and lower switch point based on the input commands from the microprocessor. The output transistor is turned on until the upper threshold is reached, and then turned off until the lower threshold is reached. See Figure 15 for an example of the solenoid current waveform. In this example, the dither is disabled. The average switch point Upper switch pt + Lower switch pt SP AVG = ---------------------------------------------------------------------------------------2 is determined by the contents of the average current command register. The relationship is: register value SP AVG = ----------------------------------- × 1230 mV 10 2 (4) (3) The hysteresis value can be programmed to a value from 40 mVpp to 110 mVpp in steps of 10 mVpp. Upper Switch Point Hysteresis Lower Switch Point Figure 15 Output Current Waveform - No Dither Data Sheet 30 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Note that the switching frequency and duty cycle of the output transistor are not directly controlled by the TLE 7241E device and are dependent on the characteristics of the solenoid (inductance, resistance, etc.) and the solenoid supply voltage. Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. 5.5.1.1 Parameter OUTx Blanking time 1 (see Figure 16, Figure 17) OUTx3) Blanking time 2 (see Figure 16, Figure 17) OUTx4)5) dVOUT = 200 mV Iavg register = 0A6H OUTx4)5) dVOUT = 400 mV Iavg register = 14DH OUTx4)5) dVOUT = 600 mV Iavg register = 1F3H OUTx4)5) dVOUT = 800 mV Iavg register = 29AH 3) Symbol Tblank1 – Limit Values Min. Typ. 5 2) Unit Test Conditions and Instructions Max. – μs Slew Rate Register = 0 or 1. From enable/disable of lowside output transistor to enabling of Vpos comparator. Slew Rate Register = 2 or 3. From enable/disable of output transistor to enabling of Vpos comparator. Output current IOUT = 200 mA with Rsense = 1.0 Ω REF = 2.5V Output current IOUT = 400 mA with Rsense = 1.0 Ω REF = 2.5V Output current IOUT = 600 mA with Rsense = 1.0 Ω REF = 2.5V Output current IOUT = 800 mA with Rsense = 1.0 Ω REF = 2.5V 5.5.1.2 Tblank2 – 15 – μs 5.5.1.3 dVOUT 200 -5% 200 +5% mV 5.5.1.4 dVOUT 400 -2.5 % 400 2.5% mV 5.5.1.5 dVOUT 600 -2% 600 2% mV 5.5.1.6 dVOUT 800 -2% 800 2% mV Data Sheet 31 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics (cont’d)1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. 5.5.1.7 Parameter OUTx4)5) dVOUT = 1000 mV Iavg register = 340H OUTx3)5) Switching hysteresis 40 Sw Hyst. register = 0 DAC counts = ±17 OUTx3)5) Switching hysteresis 50 Sw Hyst. register = 1 DAC counts = ±21 Symbol dVOUT1000 -3% Limit Values Min. Typ. 2) Unit Test Conditions and Instructions Max. 3% mV Output current IOUT = 1000 mA with Rsense = 1.0 Ω REF = 2.5V 40 mV programmed setting Input Command > 200 mV REF = 2.5V 1000 5.5.1.8 dVhyst40 29.6 39.6 49.6 mVpp 5.5.1.9 dVhyst50 40.4 50.4 60.4 mVpp 50 mV programmed setting Input Command > 200 mV REF = 2.5V 5.5.1.10 OUTx3)5) Switching hysteresis 60 Sw Hyst. register = 2 DAC counts = ±25 dVhyst60 50.1 60.1 70.1 mVpp 60 mV programmed setting Input Command > 200 mV REF = 2.5V Data Sheet 32 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics (cont’d)1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol dVhyst70 Limit Values Min. 5.5.1.11 OUTx3)5) Switching hysteresis 70 Sw Hyst. register = 3 DAC counts = ±29 5.5.1.12 OUTx3)5) Switching hysteresis 80 Sw Hyst. register = 4 DAC counts = ±33 5.5.1.13 OUTx3)5) Switching hysteresis 90 Sw Hyst. register = 5 DAC counts = ±37 59.7 Typ. 69.7 2) Unit Test Conditions and Instructions Max. 79.7 mVpp 70 mV programmed setting Input Command > 200 mV REF = 2.5V dVhyst80 70.5 80.5 90.5 mVpp 80 mV programmed setting Input Command > 200 mV REF = 2.5V dVhyst90 80.1 90.1 101.1 mVpp 90 mV programmed setting Input Command > 200 mV REF = 2.5V Data Sheet 33 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics (cont’d)1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol dVhyst100 Limit Values Min. 5.5.1.14 OUTx3)5) Switching hysteresis 100 Sw Hyst. register = 6 DAC counts = ±42 5.5.1.15 OUTx3)5) Switching hysteresis 110 Sw Hyst. register = 7 DAC counts = ±46 2) TJ = 25 °C 3) Not subject to production test, specified by design. 4) Electrical Distributions must be performed on this parameter as defined in the AEC-Q100 Specification Table 2 test 27. 5) When the internal reference is used (REF pin grounded), the minimum and maximum limits must be increased by +/- 2% Typ. 99.7 2) Unit Test Conditions and Instructions Max. 109.7 mVpp 88.7 100 mV programmed setting Input Command > 200 mV REF = 2.5V dVhyst110 100.5 110.5 120.5 mVpp 110 mV programmed setting Input Command > 200 mV REF = 2.5V 1) Positive current flow is into the device. Data Sheet 34 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Figure 16 Blanking Time (output transistor turning off) Data Sheet 35 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Figure 17 Blanking Time (output transistor turning on) Data Sheet 36 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.5.2 Dither Control and Operation The dither waveform is generated digitally within the TLE 7241E by periodically adding or subtracting from the average current command register contents. Figure 18 is an illustration of the Dither Waveform. Dither Amplitude Dither Period Figure 18 Dither Waveform The Dither Frequency can be programmed over a range of 41 Hz to 1 kHz. The Dither Amplitude can be programmed over a range from 12.5 mVpp to 390 mVpp. The Dither waveform can be disabled by clearing both the dither amplitude and dither frequency fields in the Dither Configuration Register. Note: Programming the Dither Frequency field to zero when the Dither Amplitude is programmed to a non-zero value will result in incorrect current regulation. In some applications, an enhanced dither waveform is required. The enhanced dither waveform will hold the lower switch point at the minimum value (lowest lower switch point within the dither period) until the solenoid current crosses the lower switch point. This mode may be useful when the decay time of the solenoid current is slower than the slope of the dither waveform. See Figure 19 for an illustration of the enhanced dither waveform. Enhanced Dither can be enabled by setting a bit in the SPI Dither Configuration word. Data Sheet 37 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Figure 19 Enhanced Dither Waveform When the enhanced dither bit is selected, the dither period will only be extended if the lower switch threshold is not crossed during the entire negative slope portion of the dither waveform. Example see Figure 20. The first dither period is not extended since the lower threshold was crossed during the negative slope portion of the dither waveform, the following two dither periods are extended since the low switch point was not crossed during the negative slope portion of the waveform. Data Sheet 38 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Figure 20 Enhanced Dither Waveform The extension of the dither period will be terminated when the lower switch threshold is crossed or when the extension time has exceeded the enhanced dither time out period (minimum 15 ms) - see Figure 21. Data Sheet 39 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Enhanced Dither Time Out Figure 21 Enhanced Dither Time-out Data Sheet 40 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. 5.5.2.1 Parameter OUTx3) Enhanced Dither time out Symbol Tout(eD) 15 Limit Values Min. Typ. – 2) Max. 25 Unit Test Conditions and Instructions ms – 5.5.2.2 OUTx Dither3)4) IDAP-P Amplitude Reg = 04H OUTx Dither3)4) IDAP-P Amplitude Reg = 08H OUTx Dither3)4) IDAP-P Amplitude Reg = 0CH OUTx Dither3)4) IDAP-P Amplitude Reg = 10H OUTx Dither3)4) IDAP-P Amplitude Reg = 14H OUTx Dither3)4) IDAP-P Amplitude Reg = 18H OUTx Dither3)4) IDAP-P Amplitude Reg = 1CH OUTx Dither fdither Frequency Reg = 34H 40.5 50 60.5 mVpp 50 mV setting programmed REF = 2.5V 100 mV setting programmed REF = 2.5V 150 mV setting programmed REF = 2.5V 200 mV setting programmed REF = 2.5V 250 mV setting programmed REF = 2.5V 300 mV setting programmed REF = 2.5V 350 mV setting programmed REF = 2.5V 100 Hz setting programmed3) 150 Hz setting programmed3) 200 Hz setting programmed3) 5.5.2.3 90.9 101 110.9 mVpp 5.5.2.4 141.4 151 161.4 mVpp 5.5.2.5 191.8 202 211.8 mVpp 5.5.2.6 242.3 252 262.3 mVpp 5.5.2.7 292.7 303 312.7 mVpp 5.5.2.8 343.2 353 363.2 mVpp 5.5.2.9 -15% 100 +15% Hz 5.5.2.10 OUTx Dither fdither Frequency Reg = 23H 5.5.2.11 OUTx Dither fdither Frequency Reg = 1AH -15% 150 +15% Hz -15% 200 +15% Hz Data Sheet 41 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics (cont’d)1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol Limit Values Min. 5.5.2.12 OUTx Dither fdither Frequency Reg = 15H 5.5.2.13 OUTx Dither fdither Frequency Reg = 11H 5.5.2.14 OUTx Dither fdither Frequency Reg = 0FH 5.5.2.15 OUTx Dither fdither Frequency Reg = 0DH 5.5.2.16 OUTx Dither fdither Frequency Reg = 0CH 5.5.2.17 OUTx Dither fdither Frequency Reg = 0AH 1) Positive current flow is into the device. 2) TJ = 25 °C 3) Not subject to production test, specified by design 4) When the internal reference is used (REF pin grounded), the minimum and maximum limits must be increased by +/- 2% Typ. 2) Max. +15% Unit Test Conditions and Instructions Hz 250 Hz setting programmed3) 300 Hz setting programmed3) 350 Hz setting programmed3) 400 Hz setting programmed3) 450 Hz setting programmed3) 500 Hz setting programmed3) -15% 250 -15% 308 +15% Hz -15% 350 +15% Hz -15% 403 +15% Hz -15% 437 +15% Hz -15% 524 +15% Hz Data Sheet 42 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.5.3 Input Command Out of Range / Dither Clipping If an average current command between 000H and 029H inclusive (0 mA and 50 mA with a 1 Ω sense resistor) is received, then the average current will be set to 000 (channel disabled) and the COR (command out of range) error bit will be set. The average current set point verification reported in the MISO word, however, will be the actual average current command, not 000H. If an average current command greater than 3D6H (1.18 A with a 1 Ω sense resistor) is received, then the average current will be set to 3D6H, and the COR error bit will be set. The average current set point verification reported in the MISO word, however, will be the actual commanded current, not 3D6H. The minimum limit for the lower switch point is 19H (30 mA with a 1 Ω sense resistor) and the maximum limit for the upper switch point is 3FFH (1.23 A with a 1 Ω sense resistor). If the microprocessor sets the average current command and the switching hysteresis setting to values that result in switch points beyond these limits, the TLE 7241E will clip the switch point to 19H or 3FFH and the COR error bit will be set. If the average current set point and the switching hysteresis setting do not result in switch points outside the usable range (19H to 3FFH), but dither is enabled and the dither amplitude setting results in an out of range switch point, then the DCLP fault bit will be set. The fault bit is set when the calculated switch point (average current + hysteresis + dither) exceeds the upper or lower limit, not when the registers are programmed. When the DCLP fault bit is set, the TLE 7241E will enter “symmetrical dither clipping” mode within one dither cycle after the clipping occurs. During symmetrical dither clipping mode, the device maintains the average current set-point by reducing the amplitude of the dither waveform. Up to one full dither cycle may be required to exit the “symmetrical dither clipping mode” and resume normal operation when the registers are reprogrammed. See Figure 22 for an example of the dither clipping waveform. Data Sheet 43 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Figure 22 Symmetrical Dither Clipping 5.5.4 Error Correction Registers / Average Switch Threshold Trimming The average switch threshold of each channel is trimmed at wafer test under the following operating conditions: Tamb = 25 °C, VBAT = 14 V, Vcc = 5.0 V, VREF = 2.5 V, average current command = 299H (800 mA with 1 Ω sense resistor), dither = off, hysteresis = 80 mVpp. The TLE 7241E includes 5 error correction registers for each channel. The registers are written during room temperature wafer testing. After the device has been trimmed, the average of the upper and lower switch thresholds is measured at 5 average current operating points. The difference in the measured value and the ideal value is permanently stored in the 5 error registers. The contents of the error correction register are an 8 bit signed value that must be added to the ideal current command to minimize the average current error. Data Sheet 44 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Error Correction Register # 0 1 2 3 4 For example: • • • • Measured average switch threshold at 0A6H during Infineon production test = 207 mV Ideal average switch threshold at 0A6H = 199.6 mV Error Correction = -7.4 mV / (1.2 mV/count) = -6 counts The contents of the error correction register are -6 or FAH Corresponding Average Current Register Setting (Hex) 0A6 14D 1F3 29A 340 Corresponding Ideal Average Current with a 1 Ω ext. Sense Resistor 200 mA 400 mA 600 mA 800 mA 1000 mA The contents of the error correction registers can be used by the application microcontroller to improve the accuracy of the average switch points. In the above example, when the microcontroller requests an average current of 200 mA (assuming a 1 Ω sense resistor), the command sent should be 0A6 (ideal) - 6 (error correction) = 0A0. For current commands between the 5 measured operating points, the microprocessor can use linear (or more complex) interpolation to calculate the appropriate error correction values. Data Sheet 45 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.6 5.6.1 • • • • SPI Command and Diagnosis Structure SPI Signal Description The SPI serial interface has the following features: Full duplex, 4-wire synchronous communication Slave mode operation only Fixed SCK polarity and phase requirements Fixed 16-bit command word SCK operation up to 5.0 MHz (the maximum clock frequency may be limited to a value less than 5.0 MHz by the minimum required SO setup time of the SPI master device and by the total capacitive load on the SO bus node. With a SO load capacitance of 200 pF the maximum SPI frequency is 3.2 MHz). The TLE 7241E IC Serial Peripheral Interface (SPI) is used to transmit and receive data synchronously with the master SPI device. Communication occurs over a full-duplex, four wire SPI bus. The TLE 7241E IC will operate only as a slave device to the master, and requires four external pins; SI, SO, SCK, and CSB. All words are 16 bits long and sent MSB first. The device is selected when the CSB signal is asserted (low). The master will then send 16 (or a multiple of 16) clock pulses over the SCK pin. The TLE 7241E will simultaneously turn on the serial output SO and return the MISO return bits. When receiving, valid data is latched on the rising edge of each SCK pulse. The serial output data is available on the rising edge of SCK, and transitions on the falling edge of SCK. See Figure 23 for SPI timing diagram. The number of clock cycles occurring on the pin SCK while the CSB pin is asserted low must be 16 or an integer multiple of 16, otherwise the SPI MOSI data will be ignored. The fault registers are double buffered. The first buffer layer will latch a fault at the time the fault is detected. This inner layer buffer is cleared when the fault condition is no longer present and the fault bit has been communicated to the microprocessor by a MISO response. The second layer buffer will latch the output of the inner layer buffer whenever the CSB pin transitions from low to high. The output of this buffer layer is transferred to the MISO shift register one SPI frame after the corresponding MOSI command has been received from the microcontroller. The MISO data word value of FFFFH is never generated by the TLE 7241E, and will indicate a Hi-Z state on the SO pin when an external pull-up resistor to VDD is used. This feature can be used to detect an open connection between the SO pin of the TLE 7241 E and the microcontroller. All undefined MOSI command words will be ignored by the TLE 7241E, and the MISO response during the next SPI frame will be undefined (but not FFFFH). Note: The OL/SG fault bit is latched into the MISO register, and then updated within tdly (≤ 1.7 μs) after the rising edge of the CSB signal when the received MOSI word is an General Configuration command. Data Sheet 46 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Figure 23 Data Sheet SPI Timing Diagram 47 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics 1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. 5.6.1.1 Parameter Symbol -25 Limit Values Min. Typ. CSB Input Bias ICSB Current SI Input Pulldown Current -10 2) Max. -5 Unit Test Conditions and Instructions μA VCSB = 0 V VSI = VVSO Pull-up source is from pin VSO 5 5 -10 10 10 0 25 25 10 μA μA μA 5.6.1.2 5.6.1.3 5.6.1.4 ISI SCK Input Pull- ISCK down Current SO Tri-state Leakage Current VSCK = VVSO CSB = 0.7 VDD 0 V < VSO < VVSO 0 V < VSO < 5.25 V 3) ISOT 5.6.1.5 SI, SCK, CSB, CIN DEFAULT Input Capacitance SO Tri-state Output Capacitance SCK Serial Clock Frequency – – 20 pF 5.6.1.6 CSOT fSCK – – 20 pF 0 V < VSO < 5.25 V 3) 5.6.1.7 – – 3.2 MHz SPI clock SPI communications tested at CL = 200 pF on the SO pin, Tsu1 = 40 ns ns 5.6.1.8 SCK Clock Pulse High Time SCK Clock Pulse Low Time Twh 85 – – fSCK = 3.2 MHz, fSCK = 3.2 MHz, SCK = 2 V to 2 V (see Figure 23) 85 – – ns SCK = 0.8 V to 0.8 V (see Figure 23) 5.6.1.9 Twl Data Sheet 48 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics (cont’d)1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol Tsoen, Tsodis – Limit Values Min. Typ. 5.6.1.10 SO, CSB SO Pin Enable/ Disable – 2) Max. 80 Unit Test Conditions and Instructions ns CSB = 2.0 V to SO = 0.8 V/2.0 V, 10K ext. SO pull-up (see Figure 23) - enable CSB = 0.8 V to SO hi-Z, 10K ext. SO pull-up (see Figure 23) - disable Required setup time by microprocessor equivalent to Twl Tvalid SO = 0.8 V/2.0 V to SCK = 0.8 V (see Figure 23) Required hold time by microprocessor equivalent to Twh + Tvalid - Trso/Tfso SCK = 2.0 V to SO = 0.8 V/2.0 V (see Figure 23) SI = 0.8 V/2.0 V to SCK = 2.0 V at 3.2 MHz (see Figure 23) SCK = 2.0 V to SI = 0.8 V/2.0 V at 3.2 MHz (see Figure 23) 5.6.1.11 SO, SCK3) Output Data Setup Time, SO to SCK Rising Edge Tsu1 80 – – ns 5.6.1.12 SO, SCK3) Th1 Output Data Hold Time, SO Hold After SCK Rising Edge 150 – – ns 5.6.1.13 SI, SCK Input Data Setup Time, SI to SCK Rising Edge 5.6.1.14 SI, SCK Input Data Hold Time, SI Hold after SCK Rising Edge 5.6.1.15 SO Serial Output Rise/Fall Time Tsu2 20 – – ns Th2 30 – – ns Trso/Tfso – – 50 ns Cld = 200 pF (see Figure 23) Data Sheet 49 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics (cont’d)1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol Trsi/Tfsi – Limit Values Min. Typ. 5.6.1.16 SI, CSB, SCK Serial Inputs Rise/Fall Time 5.6.1.17 CSB, SCK CSB Falling Edge to SCK Rising Edge 5.6.1.18 CSB, SCK SCK Falling Edge to CSB Rising Edge 5.6.1.19 SCK, SO Falling Edge SCK to SO Data Valid 5.6.1.20 CSB3) Sequential Transfers – 2) Max. 25 Unit Test Conditions and Instructions ns 3) Tlead 100 – – ns CSB = 0.8 V to SCK = 0.8 V (see Figure 23) SCK = 0.8 V to CSB = 0.8 V (see Figure 23) SCK = 0.8 V to SO Data Valid, Cld = 200 pF at 3.2 MHz (see Figure 23) CSB = 2.0 V (increasing) to CSB = 2.0 V (decreasing). IC will not require more than maximum time stated between communications. SCK = 0.8 V to CSB = 2.0 V (see Figure 23) CSB = 2.0 V to SCK = 0.8 V (see Figure 23) Tlag 50 – – ns Data Valid – – 80 ns Xfer Delay 1 – – μs 5.6.1.21 SCK, CSB Tsck1 Falling edge of SCK to falling edge of CSB 5.6.1.22 SCK, CSB Rising edge of CSB to rising edge of SCK Tsck2 20 – – ns 10 – – ns Data Sheet 50 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Electrical Characteristics (cont’d)1) Tj = -40 to 150 °C; VBAT = 9 V to 18 V; VDD = 4.75 V to 5.25 V Pos. Parameter Symbol nSCK 16 Limit Values Min. Typ. 5.6.1.23 SCK Number of SCK pulses while CSB low (n is a positive integer) 5.6.1.24 CSB3) MISO shift register load delay time 2) Max. Unit Test Conditions and Instructions Pulses – n × 16 – tdly – 1.7 – μs CSB = 2.0 V (increasing) to MISO data loaded into shift register (see Figure 24) 1) Positive current flow is into the device. 2) TJ = 25 °C. 3) Not subject to production test, specified by design. Tdly Latched Fault Bit CSB Figure 24 Fault Bit Refresh Delay Time (tdly) Data Sheet 51 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics 5.6.2 Table 1 B15 0 0 0 0 1 1 1 1 SPI Command Structure SPI Command Summary B14 0 0 1 1 0 0 1 1 B13 0 1 0 1 0 1 0 1 Average Current Set Point CH#1 Dither Configuration - CH#1 General Configuration CH#1 Read Register - CH#1 Average Current Set Point CH#2 Dither Configuration - CH#2 General Configuration CH#2 Read Register - CH#2 MISO Response - Next CSB Assertion Average Current Verification and Status - CH#1 Dither Config Verification CH#1 General Config Verification CH#1 Register Contents - CH#1 Average Current Verification and Status - CH#2 Dither Config Verification CH#2 General Config Verification CH#2 Register Contents - CH#2 Channel Instruction ID Command Type B15 Channel B14 I average B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MOSI MISO CH CH 0 0 0 0 X EDG Diagnostic Error X COR Command out of Range X DCLP Dither clipping D9 D9 D8 D8 D7 D7 D6 D6 Average Current Setpoint D5 D4 D5 D4 D3 D3 D2 D2 D1 D1 D0 D0 Channel I average Average Current Setpoint Figure 25 MOSI • • Average Current Set Point B12 - B10 NU: Not used, Default = 0 (40 mVpp) B9 - B0: Average Current Set point, Average Current Set point setting (see Table 2), Default = 0 (0 mA) Data Sheet 52 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics MISO • • • • B12 Diagnostic Error: = 1 if OL/SG = 1 or VSHT = 1 or OTMP = 1 (channel specific) B11 Command out of Range: = 1 if the average current set point + the hysteresis setting result in a switch point > 1.23 V or < 0.03 V B10 Dither Clipping: = 1 if the dither setting, average current set point, and hysteresis setting result in a switch point > 1.23 V or < 0.03 V B9 - B0 Average Current Set point: Contents of the average current set point command (non-clipped) Average Output Current Key (typical) - Partial Table Load Current with 1 Ω Sense Resistor [mA] 0.00 0.00 0.00 0.00 0.00 0.00 50.45 51.65 52.85 199.39 399.99 599.38 799.98 Load Current with 0.68 Ω Sense Resistor [mA] 0.00 0.00 0.00 0.00 0.00 0.00 74.19 75.96 77.72 293.23 588.22 881.45 1176.44 Table 2 COR Hex d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Average Switch Point [mV] 0 1 1 1 … 1 1 1) 1) 1) 000 0 001 0 002 0 003 0 028 0 029 0 02A 0 02B 0 02C 0 0A6 0 14D 0 1F3 0 29A 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0.00 0.00 0.00 0.00 0.00 0.00 50.45 51.65 52.85 199.39 399.99 599.38 799.98 … 0 … 0 … 0 … 0 … Data Sheet 53 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Table 2 Average Output Current Key (typical) - Partial Table (cont’d) Load Current with 1 Ω Sense Resistor [mA] 999.38 1175.95 1177.15 1178.35 1178.35 1178.35 1178.35 1178.35 1178.35 1178.35 Load Current with 0.68 Ω Sense Resistor [mA] 1469.67 1729.33 1731.10 1732.87 1732.87 1732.87 1732.87 1732.87 1732.87 1732.87 COR Hex d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Average Switch Point [mV] 0 … 1) 1) 1) 1) 340 1 3D3 1 3D4 1 3D5 1 3D6 1 3D7 1 3FC 1 3FD 1 3FE 1 3FF 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 999.38 1175.95 1177.15 1178.35 1178.35 1178.35 1178.35 1178.35 1178.35 1178.35 1 … 1 1 1 1 1) COR state dependent on the switching hysteresis value. register value SP AVG = ----------------------------------- × 1230 mV 10 2 register value 1230 I AVG = ----------------------------------- × --------------- mA 10 R sense 2 (5) (6) Note: When a new average current command or hysteresis setting is received, the new data is loaded immediately with the rising edge of CSB (not synchronized with the dither waveform). The dither waveform is not reset when the new average current command or hysteresis setting is received. Data Sheet 54 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics B15 B14 B13 B12 Enhanced Dither B11 B10 B9 Dither Amplitude B8 B7 B6 B5 B4 B3 Dither Frequency B2 B1 B0 MOSI MISO CH CH Channel 0 0 Dither Configuration Dither Configuration 1 1 ED ED DA4 DA4 DA3 DA3 DA2 DA2 Dither Amplitude DA1 DA1 DA0 DA0 DF6 DF6 DF5 DF5 DF4 DF4 DF3 DF3 Dither Frequency DF2 DF2 DF1 DF1 DF0 DF0 Figure 26 MOSI • • • Dither Programming B12 Enhanced Dither: Enables the enhanced dither feature when ED = 1, Default = 0 (disabled) B11 - B7 Dither Amplitude: Setting for the amplitude of the dither waveform (see Table 3), Default = 00H (Dither Disabled) B6 - B0 Dither Frequency: Setting for the frequency of the dither waveform (see Table 4), Default = 00H (Dither Disabled) Note: To disable the dither waveform, both the amplitude and frequency fields must be set to zero. These fields must both be cleared in the same SPI communication frame. Programming the frequency to zero when the amplitude is set to a non-zero value will result in incorrect current regulation. MISO • • • B12 Enhanced Dither: Contents of the ED bit of the dither configuration register B11 - B7 Dither Amplitude: Contents of the dither amplitude register (shadow register) B6 - B0 Dither Frequency: Contents of the dither frequency register (shadow register) Note: When a Dither Configuration command is received which changes either the dither frequency or the dither amplitude settings, the new dither waveform characteristics will take effect at the beginning of the next dither period. Data Sheet Enhanced Dither Channel 55 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Figure 27 Start of Dither Cycle Data Sheet 56 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Table 3 Ideal Dither Amplitude Key (typical) Dither Amplitude with 0.68 Ω sense resistor [mApp] 0.00 18.5 37.1 55.6 74.19 92.74 111.29 129.84 148.38 166.93 185.48 204.03 222.58 241.12 259.67 278.22 296.77 315.32 333.86 352.41 370.96 389.51 408.05 426.60 445.15 463.70 482.25 500.79 Rev. 1.1, 2009-01-19 Hex DA4 DA3 DA2 DA1 DA0 Dither Dither Amplitude Amplitude with [mVpp] 1 Ω sense resistor [mApp] 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.0 12.6 25.2 37.8 50.5 63.1 75.7 88.3 100.9 113.5 126.1 138.7 151.4 164.0 176.6 189.2 201.8 214.4 227.0 239.6 252.3 264.9 277.5 290.1 302.7 315.3 327.9 340.5 57 0.00 12.6 25.2 37.8 50.45 63.06 75.68 88.29 100.90 113.51 126.13 138.74 151.35 163.96 176.58 189.19 201.80 214.41 227.03 239.64 252.25 264.86 277.48 290.09 302.70 315.32 327.93 340.54 Data Sheet TLE 7241E Functional Description and Electrical Characteristics Table 3 Ideal Dither Amplitude Key (typical) Dither Amplitude with 0.68 Ω sense resistor [mApp] 519.34 537.89 556.44 574.99 Hex DA4 DA3 DA2 DA1 DA0 Dither Dither Amplitude Amplitude with [mVpp] 1 Ω sense resistor [mApp] 1C 1D 1E 1F 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 353.2 365.8 378.4 391.0 353.15 365.77 378.38 390.99 register value × 10.5 V dithamp = ----------------------------------------------------- × 1230 mVpp 10 2 register value × 10.5 1230I dithamp = ----------------------------------------------------- × --------------- mApp 10 R sense 2 Table 4 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DF6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ideal Dither Frequency Key (typical)- Partial Table DF5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DF4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DF3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 58 (7) (8) DF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Dither Frequency 0.0 Hz 5238.1 Hz 2619.0 Hz 1746.0 Hz 1309.5 Hz 1047.6 Hz 873.0 Hz 748.3 Hz 654.8 Hz 582.0 Hz 523.8 Hz 476.2 Hz 436.5 Hz 402.9 Hz 374.2 Hz 349.2 Hz Rev. 1.1, 2009-01-19 Data Sheet TLE 7241E Functional Description and Electrical Characteristics Table 4 Hex 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D DF6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ideal Dither Frequency Key (typical)- Partial Table (cont’d) DF5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DF4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DF3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 DF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 DF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 DF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Dither Frequency 327.4 Hz 308.1 Hz 291.0 Hz 275.7 Hz 261.9 Hz 249.4 Hz 238.1 Hz 227.7 Hz 218.3 Hz 209.5 Hz 201.5 Hz 194.0 Hz 187.1 Hz 180.6 Hz 174.6 Hz 169.0 Hz 163.7 Hz 158.7 Hz 154.1 Hz 149.7 Hz 145.5 Hz 141.6 Hz 137.8 Hz 134.3 Hz 131.0 Hz 127.8 Hz 124.7 Hz 121.8 Hz 119.0 Hz 116.4 Hz Data Sheet 59 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Table 4 Hex 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B DF6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Ideal Dither Frequency Key (typical)- Partial Table (cont’d) DF5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 DF4 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 DF3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 DF2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 DF1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Dither Frequency 113.9 Hz 111.4 Hz 109.1 Hz 106.9 Hz 104.8 Hz 102.7 Hz 100.7 Hz 98.8 Hz 97.0 Hz 95.2 Hz 93.5 Hz 91.9 Hz 90.3 Hz 88.8 Hz 87.3 Hz 85.9 Hz 84.5 Hz 83.1 Hz 81.8 Hz 80.6 Hz 79.4 Hz 78.2 Hz 77.0 Hz 75.9 Hz 74.8 Hz 73.8 Hz 72.8 Hz 71.8 Hz 70.8 Hz 69.8 Hz Data Sheet 60 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Table 4 Hex 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 DF6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Ideal Dither Frequency Key (typical)- Partial Table (cont’d) DF5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 DF4 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 DF3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 DF2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 DF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 DF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Dither Frequency 68.9 Hz 68.0 Hz 67.2 Hz 66.3 Hz 65.5 Hz 64.7 Hz 63.9 Hz 63.1 Hz 62.4 Hz 61.6 Hz 60.9 Hz 60.2 Hz 59.5 Hz 58.9 Hz 58.2 Hz 57.6 Hz 56.9 Hz 56.3 Hz 55.7 Hz 55.1 Hz 54.6 Hz 54.0 Hz 53.5 Hz 52.9 Hz 52.4 Hz 51.9 Hz 51.4 Hz 50.9 Hz 50.4 Hz 49.9 Hz Data Sheet 61 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics Table 4 Hex 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F DF6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Ideal Dither Frequency Key (typical)- Partial Table (cont’d) DF5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DF4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DF3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DF2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DF1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Dither Frequency 49.4 Hz 49.0 Hz 48.5 Hz 48.1 Hz 47.6 Hz 47.2 Hz 46.8 Hz 46.4 Hz 45.9 Hz 45.5 Hz 45.2 Hz 44.8 Hz 44.4 Hz 44.0 Hz 43.7 Hz 43.3 Hz 42.9 Hz 42.6 Hz 42.2 Hz 41.9 Hz 41.6 Hz 41.2 Hz 1.76 × 10 f dith = --------------------------------------------------- Hz register value × 336 6 (9) Data Sheet 62 Rev. 1.1, 2009-01-19 TLE 7241E Functional Description and Electrical Characteristics B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 Fault Typing Current Source B4 B3 B2 B1 B0 General Configuration MOSI MISO CH CH Channel 1 1 General Configuration 0 0 X X X OL/SG VSHT OTMP Open Load or Short to GND Short to Vpwr Over Temperature X 0 X 0 X 0 X REF Ext./Int. Reference Volt. FT FT Fault Typing Current Source SR1 SR1 SR0 SR0 SW2 SW2 Switching Hysteresis SW1 SW1 SW0 SW0 Slew Rate Figure 28 MOSI • • • • Channel General Configuration Register B12 - B6: Not used, Ignored - Don’t Care B5 Fault Typing Bit: Activates a 40 μA pull-up current on POSx pin for SG/OL differentiation. Default = 0 (disabled) B4 - B3 Slew Rate: Setting for the slew rate (see Table 5). Default = 3 (1.2 V/μs) B2 - B0 Switching Hysteresis: Setting for the hysteresis value (see Table 6), Default = 0 (40 mVpp) MISO • • • • • • • • B12 OL/SG: Open Load / Short to Ground fault flag B11 VSHT: Short to BAT (Shorted Load) fault flag B10 OTMP: Overtemperature fault flag B9 - B7: Not used, always 0 B6 REF: = 0 when an external reference is detected on the REF pin, B6 REF: = 1 when the REF pin is grounded and the internal 2.5 V reference is active B5 FT: Contents of the FT-bit in the general configuration register B4 - B3 Slew Rate: Contents of the Slew Rate settings in the general configuration register B2 - B0 SW: Contents of the switching hysteresis setting in the general configuration register Data Sheet 63 Rev. 1.1, 2009-01-19 Switching Hysteresis Slew Rate TLE 7241E Functional Description and Electrical Characteristics Table 5 SR1 0 0 1 1 Table 6 SH2 0 0 0 0 1 1 1 1 Slew Rate Control Key SR0 0 1 0 1 Tf/Tr (4 V - 10 V) 0.5 μs 1 μs 2 μs 5 μs Slew Rate 12 V/μs 6 V/μs 3 V/μs 1.2 V/μs Switching Hysteresis Key SH1 0 0 1 1 0 0 1 1 SH0 0 1 0 1 0 1 0 1 Hysteresis 40 mVpp 50 mVpp 60 mVpp 70 mVpp 80 mVpp 90 mVpp 100 mVpp 110 mVpp B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MOSI MISO CH CH Channel 1 1 1 1 0 0 0 0 RID2 RID2 RID1 RID1 Register ID RID0 RID0 Read Error Registers Command Extension X RV7 X RV6 X RV5 X RV4 Register Value X RV3 X RV2 X RV1 X RV0 Figure 29 MOSI • • • Channel Read Error Register B12 - B11 Command Extension: Always send as 00 B10 - B8 Register ID: Selects Register to be transmitted to μP during next SPI frame (see Table 7) B7 - B0: Not used, Ignored / Don't Care 64 Rev. 1.1, 2009-01-19 Data Sheet Register ID Read Error Registers Command Extension TLE 7241E Functional Description and Electrical Characteristics MISO • • • B12 - 11 Command Extension: Always 00 B10 - B8 RID0-2: Register ID of the register contents in B7 - B0 B7 - B0 RV: Register contents Error Register Values per Channel RID1 0 0 1 1 0 0 1 1 RID0 0 1 0 1 0 1 0 1 Register Name Error Correction - 200 mV Error Correction - 400 mV Error Correction - 600 mV Error Correction - 800 mV Error Correction - 1000 mV Chip Revision Code 00H 00H Table 7 RID2 0 0 0 0 1 1 1 1 The MOSI Commands “X1101XXX XXXXXXXX”, “X1110XXX XXXXXXXX”, and “X1111XXX XXXXXXXX” are not valid commands for the TLE7241 E. The MISO return words associated with these commands are undefined, but exclude the word “FFFFH”. Data Sheet 65 Rev. 1.1, 2009-01-19 TLE 7241E Application 6 Application VPWR (4) Rbat (2) Cref 2.5V ref +5V Cvdd Cbat VPWR/ RECIRC VDD +5V or 3.3V BAT REF OUT1 Cout1(3) Rsns1 SOL1 Csol1 VSO Cso Rso (5) NEG1 POS1 PGND1 Cng1 (3) Cps1 (3) VPWR/ RECIRC SO TLE7241 OUT2 NEG2 POS2 PGND2 TEST GND Cng2 (3) Cps2 (3) Cout2 (3) μController Tri-Core TC17XX Rdft (1). DEFAULT SI SCK CSB Rsns2 SOL2 Csol2 Figure 30 Application Circuit Note: This is a very simplified example of an application circuit. The function must be verified in the real application 1. Recommended for applications with microcontroller I/O voltage levels less than 5.0 V. The resistor will limit the microcontroller input current when the adjacent pins DEFAULT and VDD are shorted together. 2. Required for applications that do not provide a reverse battery protected BAT supply. RBAT may also be required to limit the BAT pin current during BAT voltage transient events (e. g. ISO pulses). 3. May be required for module level compliance with EMC specifications, but they are not required for TLE7241 functionality or stability. 4. Connect to the REF pin directly to GND to enable the internal 2.5 V voltage reference. 5. Optional. Defines SO signal voltage when the SO pin has failed as an open circuit. Note: In case of an unused channel, the OUTx, NEGx, and POSx pins should be connected together. Data Sheet 66 Rev. 1.1, 2009-01-19 TLE 7241E Application 6.1 • • • Layout Notes • • • • • • • The POS pin should be connected directly to the external sense resistor with a dedicated trace. The NEG pin should be connected directly to the external sense resistor with a dedicated trace. The POS pin trace should be routed near the NEG pin trace and both traces should not be routed near noise inducing signal lines and/or components (SPI clock signals, switching power supply inductors, etc.). For best accuracy, the external sense resistor should be placed near the IC. A capacitor should be connected between the VDD pin and ground near the IC. A capacitor should be connected between the VSO pin and ground near the IC. A capacitor should be connected between the BAT pin and ground near the IC. A capacitor should be connected between the REF pin and ground near the IC. The exposed lead frame should be connected to a large area ground plane and to the pins PGND1, PGND2. The GND pin should be connected directly to the ground plane. Data Sheet 67 Rev. 1.1, 2009-01-19 TLE 7241E Package Outlines 7 Package Outlines 2.6 MAX. 0.35 x 45° 7.6 -0.2 1) 0...0.10 2.45 -0.2 0.23 +0.09 0.7 ±0.2 10.3 ±0.3 D 20 1.27 0.4 ±0.08 2) 0.25 M A 20 11 0.1 C 20x C A-B C D 20x Ejector Mark Ejector Mark Bottom View 11 Exposed Diepad Index Marking 4.6 1 10 10 B 12.8 -0.2 1) 5.2 1 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side PG-DSO-20-27-PO V14 Figure 31 PG-DSO-20-27 EDP(Plastic Dual Small Outline Exposed Die Pad) Green Product (RoHS-compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC JSTD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 68 Dimensions in mm Rev. 1.1, 2009-01-19 8° MAX. TLE 7241E Revision History 8 Version Rev. 1.1 Revision History Date Changes 2009-01-19 Page 68: Updated Package drawing (Stand-off) Page 69-70: added Revision History, updated Legal Disclaimer Data Sheet 69 Rev. 1.1, 2009-01-19 Edition 2009-01-19 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.infineon.com Published by Infineon Technologies AG