TLE7278-2EV50

Data Sheet, Rev. 1.2, April 2009 TLE7278-2 Low Dropout Voltage Regulator Automotive Power Low Dropout Voltage Regulator TLE7278-2 1 Features • • • • • • • • • • • • • • Overview Output Voltage 5 V, 3.3 V or 2.6 V Output Voltage Tolerance ±2% Output Current Up To 180 mA Ultra Low Quiescent Current Consumption < 36 µA Enable Function Very Low Dropout voltage Reset With Adjustable Power-On Delay Standard Watchdog With Current Dependent Deactivation Output Current Limitation Wide Operation Range Up To 45 V Wide Temperature Range From -40 °C To 150 °C Overtemperature Shutdown Green Product (RoHS compliant) AEC Qualified PG-DSO-14 Description PG-SSOP-14 Exposed Pad The TLE7278-2 is a monolithic integrated voltage regulator with integrated standard watchdog and reset dedicated for microcontroller supplies under harsh automotive environment conditions. The watchdog circuit is deactivated for very low loads at the device’s output (e.g. microcontroller in standby mode). Due to its ultra low quiescent current the TLE7278-2 is perfectly suited for applications that are permanently connected to battery. In addition, the regulator can be shut down via the Enable input causing the current consumption to drop below 3 µA. The TLE7278-2 is equipped with an overtemperature shutdown and an output current limitation protecting the device against overload, short circuit and overtemperature. It operates in the wide junction temperature range from -40 °C to 150 °C. Type TLE7278-2GV50 TLE7278-2GV33 TLE7278-2GV26 TLE7278-2EV50 Data Sheet Package PG-DSO-14 PG-DSO-14 PG-DSO-14 PG-SSOP-14 Exposed Pad 2 Marking TLE7278-2GV50 TLE7278-2GV33 TLE7278-2GV26 7278 V50 Rev. 1.2, 2009-04-28 TLE7278-2 Block Diagram 2 Block Diagram I TLE7278-2 Q Overtemperature shutdown RO Bandgap Reference 1 Reset Generator and Watchdog WDI Charge Pump WM1 WM2 EN Enable GND Figure 1 Block Diagram Data Sheet 3 Rev. 1.2, 2009-04-28 TLE7278-2 Pin Configuration 3 3.1 Pin Configuration Pin Assignment (PG-DSO-14) RO GND GND GND GND WM2 WM1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 EN I GND GND GND Q WDI AEP02113_7278 Figure 2 Pin Configuration 3.2 Pin 1 Pin Definitions and Functions (PG-DSO-14) Symbol RO Function Reset Output TLE7278-2GV33, TLE7278-2GV26: open drain output; TLE7278-2GV50: integrated 20 kΩ pull-up resistor Ground connect pin 2 and 3 to GND; connect pin 4-5, 10-12 to PCB heat sink area with GND potential Watchdog Mode Bit 1 watchdog and Reset mode selection, see Figure 5; connect to Q or GND Watchdog Mode Bit 2 watchdog and reset mode selection, see Figure 5; connect to Q or GND Watchdog Input trigger input for watchdog pulses; pull down to GND if not needed and turn off the watchdog with WM1 and WM2 pin Output Voltage block to GND with a ceramic capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in “Functional Range” on Page 7 Input Voltage block to ground directly at the IC with a 100 nF ceramic capacitor Enable Input low level disables the IC; integrated pull-down resistor to GND 2-5, 10-12 7 GND WM1 6 WM2 8 WDI 9 Q 13 14 I EN Data Sheet 4 Rev. 1.2, 2009-04-28 TLE7278-2 Pin Configuration 3.3 Pin Assignments (PG-SSOP-14 Exposed Pad) Figure 3 Pin Assignment PG-SSOP-14 Exposed Pad (top view) 3.4 Table 1 Pin No. 1 Pin Definitions and Functions (PG-SSOP-14 Exposed Pad) Pin Definitions and Functions Symbol RO Function Reset Output integrated 20 kΩ pull-up resistor; leave open if not needed Ground connect to GND not connected leave open or connect to GND Watchdog Mode Bit 2 watchdog and reset mode selection, see Figure 5; connect to Q or GND Watchdog Mode Bit 1 watchdog and Reset mode selection, see Figure 5; connect to Q or GND Watchdog Input trigger input for watchdog pulses; pull down to GND if not needed and turn off the watchdog with WM1 and WM2 pin Output Voltage block to GND with a ceramic capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in “Functional Range” on Page 7 Input Voltage block to ground directly at the IC with a 100 nF ceramic capacitor Enable Input low level disables the IC; integrated pull-down resistor Exposed Pad connect to heatsink area; connect to GND on PCB 5 Rev. 1.2, 2009-04-28 2, 5 3, 4, 10, 11, 12 6 GND n.c. WM2 7 WM1 8 WDI 9 Q 13 14 I EN Pad – Data Sheet TLE7278-2 General Product Characteristics 4 4.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Input I 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 1) 2) 3) 4) Parameter Symbol Limit Values Min. Max. 45 5.5 6.2 45 1 7 5.5 6.2 5 3 1.5 150 150 Unit Conditions Voltage Voltage Voltage Voltage Current Voltage Voltage Voltage Current Human Body Model (HBM)3) Charge Device Model (CDM) Junction temperature Storage temperature 4) VI VQ VQ VEN IEN VRO VWM1 VWM1 IWM1 Voltage Voltage -0.3 -0.3 -0.3 -1 -1 -1 -0.3 -0.3 -5 – – -40 -50 V V V V mA V V V mA kV kV °C °C – permanent Output Q, Reset Output RO, Watchdog Mode 2 t < 10 s2) – – permanent permanent Enable Input EN Watchdog Input WDI Watchdog Mode 1 t < 10 s2) – – – – – ESD Susceptibility Temperatures Tj Tstg not subject to production test, specified by design exposure to these absolute maximum ratings for extended periods (t > 10 s) may affect device reliability ESD HBM Test according to JEDEC JESD22-A114 ESD CDM Test according AEC/ESDA ESD-STM5.3.1-1999 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 6 Rev. 1.2, 2009-04-28 TLE7278-2 General Product Characteristics 4.2 Pos. 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 Functional Range Parameter Input voltage Symbol Min. Limit Values Max. 45 45 45 – 3 150 V V V nF Ω °C TLE7278-2GV50, TLE7278-2EV50 TLE7278-2GV33 TLE7278-2GV26 –1) –2) – 5.5 4.2 4.5 Output Capacitor’s Requirements for Stability Junction Temperature Unit Conditions VI CQ 470 ESR(CQ) – Tj -40 1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Pos. Thermal Resistance Parameter Symbol Min. Limit Values Typ. 30 Max. – K/W measured to group of pins 3, 4, 5, 10, 11, 12 2) Unit Conditions Package PG-DSO-14 4.3.1 Junction to Soldering Point1) RthJSP – 4.3.2 4.3.3 4.3.4 4.3.5 Junction to Ambient1) RthJA – – – – 53 105 74 65 – – – – K/W K/W K/W K/W footprint only3) 300 mm2 heatsink area on PCB3) 600 mm2 heatsink area on PCB3) measured to exposed pad 2) Package PG-SSOP-14 Exposed Pad 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 Junction to Case1) Junction to Ambient1) RthJC RthJA – – – – – 14 47 141 66 56 – – – – – K/W K/W K/W K/W K/W footprint only3) 300 mm2 heatsink area on PCB3) 600 mm2 heatsink area on PCB3) 1) not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 7 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics 5 5.1 Block Description and Electrical Characteristics Circuit Description 5.1.1 Power On Reset and Reset Output For an output voltage level VQ ≥ 1 V the reset output is hold low. When the level of VQ reaches the reset threshold VRT, the signal at RO remains low for the power-up reset delay time tRD. The reset function and timing is illustrated in Figure 4. The reset reaction time tRR avoids wrong triggering caused by short “glitches” on the VQ-line. In case of VQ power down (VQ < VRT for t > tRR) a logic low signal is generated at the pin RO to reset an external micro controller. The TLE7278-2GV50 and TLE7278-2EV50 feature an integrated pull-up resistor on the reset output while the TLE7278-2GV33 and TLE7278-2GV26 have an open drain output requiring an external pull-up resistor. When connected to a voltage level of Vext = 5 V, a recommended value for this external resistor is ≥ 5.6 kΩ. But it’s also possible calculating its value by using the following formula, based on the reset sink current (Example: external pull-up resistor connected to Vext = 5 V): Rextmin = ∆V / IRO = (Vext - VROmin) / IRO = (5 V - 0.25 V) / 1.0 mA = 4.75 kΩ At low output voltage levels VQ < 1 V the integrated pull-up resistor of the TLE7278-2GV50 is switched off setting the reset output high ohmic. VI VRTI t VQ < tRR VRT VRO VROH VROL tRD t RR tRR t t AET03526NEW.VSD Figure 4 Data Sheet Reset Function and Timing Diagram 8 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics 5.1.2 Watchdog Operation The watchdog uses a fraction of the charge pump oscillator’s clock signal as timebase. The watchdog timebase can be adjusted using the pins WM1 and WM2 (see Figure 5). The watchdog can be turned off setting WM1 and WM2 to high level. The timing values used this text refer to typ. values with WM1 and WM2 connected to GND (fast watchdog and reset timing). If the timebase is switched by changing the condition on the WM pins, the new timing is valid from the beginning of the new period on. From this time on, the frequency on the WDI pin must be adapted. Figure 5 shows the state diagram of the watchdog (WD) and the mode selection. After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time TRD of typ. 16 ms. With the LOW to HIGH transition of the signal at RO the device starts the ignore window time tCW (32 ms). Next the WD starts the Watchdog Period (time frame within a trigger at WDI must occur). From now on the timing of the signal on WDI from the micro controller must correspond the WD-Period tWD,p correspondent the electrical characteristics and based on the setting on the WM pins. A Re-Trigger of the WD-Period is done with a HIGH-to-LOW Transient at the WDI-pin within the set tWD,p. A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken as a trigger. To avoid wrong triggering due to parasitic glitches two HIGH samples followed by two LOW samples (sample period tsam typ. 0.5 ms) are decoded as a valid trigger. A reset is generated (RO goes LOW) if there is no trigger pulse during the Watchdog Period. VI t VQ VRT t IQ IQ, WD_OFF TRD TRD Normal operation IQ, WD_ON t No Reset during Current shut down Power Fail V RO trr tsam trr t Trigger Window Ingnore Wnd Don’t care WDI during IW 1. Correct Trigger t WDI tWD,p No Trigger causing reset Current Controlled WD-turn off t WM1 WM2 Watchdog Mode Reset Mode L L Fast Fast L H Slow Slow H L Fast Slow H H Off Slow 7278 Timing Figure 5 Watchdog Timing Diagram, Watchdog and Reset Modes Data Sheet 9 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics 5.2 Electrical Characteristics Electrical Characteristics VI = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Output Q 5.2.1 Output voltage Limit Values Typ. 5.00 Max. 5.10 V TLE7278-2GV50, TLE7278-2EV50 1 mA < IQ < 180 mA 6 V < VI < 1 6 V TLE7278-2GV50, TLE7278-2EV50 IQ = 10 mA 6 V < VI < 4 5 V TLE7278-2GV33 1 mA < IQ < 180 mA 4.5 V < VI < 16 V TLE7278-2GV33 IQ = 10 mA 4.5 V < VI < 45 V TLE7278-2GV26 1 mA < IQ < 180 mA 4.5 V < VI < 16 V TLE7278-2GV26 IQ = 10 mA 4.5 V < VI < 45 V Unit Conditions VQ 4.90 5.2.2 Output voltage VQ 4.90 5.00 5.10 V 5.2.3 Output voltage VQ 3.234 3.30 3.366 V 5.2.4 Output voltage VQ 3.234 3.30 3.366 V 5.2.5 Output voltage VQ 2.548 2.60 2.652 V 5.2.6 Output voltage VQ 2.548 2.60 2.652 V 5.2.7 5.2.8 Output current limitation Dropout Voltage; IQ VDR 200 200 – – – 250 500 600 500 mA mA mV VDR = VI - VQ 5.2.9 5.2.10 5.2.11 5.2.12 Load regulation Line regulation Power-Supply-Ripple-Rejection Reverse Output Current Clamping Quiescent current; Iq = II - IQ Quiescent current; Disabled High Level Input Voltage VQ = 2.0 V VQ = 0 V IQ = 180 mA1) TLE7278-2GV50, TLE7278-2EV50 ∆VQ,Lo ∆VQ,Li – – – – 50 10 60 – 90 50 – 5.5 mV mV dB V 1 mA < IQ < 180 mA IQ = 1 mA; 10 V < VI < 32 V fr = 100 Hz; Vr = 0.5 Vpp IQ,REV = -1 mA; VEN = 0 V IQ = 100 µA; Tj < 80 °C VEN = 0 V; Tj < 80 °C VQ on Rev. 1.2, 2009-04-28 PSRR VQ,REV Current Consumption 5.2.13 5.2.14 Iq Iq – – 28 1 36 3 µA µA Enable Input EN 5.2.15 VEN,H 3.0 10 – – V Data Sheet TLE7278-2 Block Description and Electrical Characteristics Electrical Characteristics (cont’d) VI = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.2.16 5.2.17 5.2.18 5.2.19 5.2.20 5.2.21 5.2.22 5.2.23 5.2.24 5.2.25 5.2.26 5.2.27 5.2.28 5.2.29 5.2.30 5.2.31 5.2.32 5.2.33 5.2.34 5.2.35 5.2.36 Low Level Input Voltage High Level Input Current Low Level Input Current Watchdog sampling time Ignore window time Watchdog Period Watchdog deactivation current threshold Low Level Input Voltage High Level Input Voltage Low Level Input Voltage High Level Input Voltage High Level Input Current High Level Input Voltage Parameter Low Level Input Voltage Symbol Min. Limit Values Typ. – – 3 – – – – – – – – – – – – 3 0.5 0.50 1.00 32.0 64.0 32 64 – Max. 0.5 0.3 4 – – – 0.80 – – – 0.80 – – – 0.80 4 1 0.60 1.20 38.4 76.8 38.4 76.8 – V V µA V V V V V V V V V V V V µA µA ms ms ms ms ms ms mA – – Unit Conditions VEN,L IEN,H VWM1,H – 4.00 2.65 2.30 VQ = 0.02 V; IQ = 5 mA; Tj < 125 °C VQ = 0.02 V IQ = 5 mA VEN = 5 V TLE7278-2GV50, TLE7278-2EV50 TLE7278-2GV33 TLE7278-2GV26 – TLE7278-2GV50, TLE7278-2EV50 TLE7278-2GV33 TLE7278-2GV26 – TLE7278-2GV50, TLE7278-2EV50 TLE7278-2GV33 TLE7278-2GV26 – Watchdog Mode Bit 1 VWM1,L VWM2,H – 4.00 2.65 2.30 Watchdog Mode Bit 2 VWM2,L VWDI,H – 4.0 2.65 2.30 Watchdog Input WDI VWDI,L IWDI,H IWDI,L tsam tOW tWD,p IQ,WD_off – – – 0.40 0.80 25.6 51.2 25.6 51.2 0.5 VWDI = 5 V VWDI = 0 V; Tj < 80 °C fast watchdog timing slow watchdog timing fast watchdog timing slow watchdog timing fast watchdog timing slow watchdog timing IQ decreasing VI > VI, WD_on > 6.0 V for TLE7278-2GV50, TLE7278-2EV50 VI > VI,WD_on > 4.5 V for TLE7278-2GV33, TLE7278-2GV26 Data Sheet 11 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics Electrical Characteristics (cont’d) VI = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.2.37 Parameter Watchdog activation current threshold Symbol Min. Limit Values Typ. – Max. 5 mA – Unit Conditions IQ,WD_on IQ increasing VI > VI,WD_on > 6.0 V for TLE7278-2GV50, TLE7278-2EV50 VI > VI,WD_on > 4.5 V for TLE7278-2GV33, TLE7278-2GV26 Reset Output RO 5.2.38 Output Voltage Reset Switching Threshold VRT 4.50 4.60 4.70 V TLE7278-2GV50, TLE7278-2EV50 VQ decreasing TLE7278-2GV332) VQ decreasing TLE7278-2GV262) VQ decreasing TLE7278-2GV262) TLE7278-2GV332) VQ > VRT, VI decreasing TLE7278-2GV26 TLE7278-2GV33 TLE7278-2GV50, TLE7278-2EV50 TLE7278-2GV50, TLE7278-2EV50 VQ = 4.5 V, VRO = 0.25 V TLE7278-2GV33 5.2.39 5.2.40 5.2.41 Input Voltage Reset Switching Threshold 3.00 2.35 3.07 2.38 3.9 3.13 2.45 4.0 V V V VRT_VI – 5.2.42 5.2.43 5.2.44 5.2.45 Reset Hysteresis VRH – – – 45 60 90 – – – – – mV mV mV mA Maximum Reset Sink Current IRO 1.75 5.2.46 1.3 – – mA VQ = 3.0 V, VRO = 0.25 V 5.2.47 1.0 – – mA TLE7278-2GV26 5.2.48 5.2.49 5.2.50 Reset output low voltage Reset high voltage Reset high leakage current VROL VROH IROLK – 4.5 – 0.15 – – 0.25 – 1 V V µA VQ = 2.35 V, VRO = 0.25 V VQ ≥ 1 V ; IRO < 200 µA TLE7278-2GV50, TLE7278-2EV50 TLE7278-2GV33 TLE7278-2GV26 Data Sheet 12 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics Electrical Characteristics (cont’d) VI = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.2.51 Parameter Integrated reset pull-up resistor Symbol Min. Limit Values Typ. 20 Max. 40 kΩ TLE7278-2GV50, TLE7278-2EV50 internally connected to VQ fast reset timing slow reset timing – 10 Unit Conditions RRO 5.2.52 5.2.53 Power-on Reset delay time Reset Reaction Time TRD TRR 12.8 25.6 – 16.0 32.0 4 19.2 38.4 12 ms ms µs 1) measured when the output voltage has dropped 100 mV from the nominal Value obtained at VI = 13.5 V 2) reset output triggered when output voltage VQ is lower than output voltage reset switching threshold VRT or is also triggered, when input voltage is decreasing to VI < 4.0 V and VQ > VRT Data Sheet 13 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics Current Consumption Iq versus Junction Temperature Tj (EN=ON) 1_Iq-Tj.vsd Current Consumption Iq versus Output Current IQ (EN=ON) 2 _ IQ -IQ .V S D Iq [µA] VI = 13.5V 100 45 T j = 2 5 °C 40 35 T j = - 4 0 °C IQ = 100 µA 30 10 I q [µA] 25 20 15 1 10 5 0 0.01 -40 -20 0 20 40 60 80 100 120 140 0 ,1 1 10 100 1000 Tj [°C] I Q [m A ] Current Consumption Iq versus Input Voltage VI at Tj=-40°C (EN=ON) Current Consumption Iq versus Input Voltage VI at Tj=25°C (EN=ON) 200 3A_IQ-VI_25.VSD 200 3A_IQ-VI_-40.VSD Iq [µA] 150 Tj = 2 5 °C Iq [µA] 150 Tj = - 40°C 100 100 IQ = 1 00mA I Q = 1 0mA 50 IQ = 1 00mA I Q = 1 0mA 50 IQ = 0 .2mA IQ = 0 .2mA 0 10 20 30 40 0 10 20 30 40 VI [V] VI [V] Data Sheet 14 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Load Regulation dVQ versus Output Current Change dIQ 0 18b_dVQ-dIQ_Vi135V.vsd Load Regulation dVQ versus Output Current Change dIQ 0 18a_dVQ-dIQ_Vi6V.vsd ∆VQ [mV] VI = 13.5V ∆VQ [mV] VI = 6V -2 Tj = 25 °C Tj = -40 °C Tj = 150 °C -2 Tj = 150 °C Tj = -40 °C Tj = 25 °C -3 -3 -4 -4 -5 -5 -6 0 100 200 -6 0 100 200 IQ [mA] IQ [mA] Power Supply Ripple Rejection PSRR 80 13_PSRR.VSD Load Regulation dVQ versus Output Current Change dIQ 0 18c_dVQ-dIQ_Vi28V.vsd PSRR [dB] IQ = 0.1 mA IQ = 10 mA IQ = 100 mA ∆VQ [mV] Tj = 25 °C VI = 28 60 -2 Tj = -40 °C Tj = 150 °C 50 -3 40 -4 30 VRIPPLE = 1 V VIN = 13.5 V CQ = 470nF Ceramics Tj = 25 °C 100 1k 10k 100k -5 10 -6 0 100 200 f [Hz] IQ [mA] Data Sheet 15 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Line Regulation dVQ versus Input Voltage Change dVI 6 19_dVQ-dVI__150C.vsd Line Regulation dVQ versus Input Voltage Change dVI Tj = 150 °C 6 19_dVQ-dVI_25C_.vsd ∆ VQ [mV] IQ = 10mA ∆ VQ [mV] Tj = 25 °C IQ = 1mA IQ = 10mA 2 IQ = 1mA 2 IQ = 100mA 0 0 -2 -2 -4 -4 -6 0 5 10 15 20 25 30 35 40 45 -6 0 5 10 15 20 25 30 35 40 45 VI [V] VI [V] Line Regulation dVQ versus Input Voltage Change dVI 6 19_dVQ-dVI_-40C.vsd Enable Input Current IEN versus Enable Input Voltage VEN 24_IINH vs VINH.vsd ∆VQ [mV] Tj = -40 °C [µA] 50 IEN Tj = 150°C Tj = 25°C Tj = -40°C 2 40 IQ = 100mA 0 IQ = 10mA IQ = 1mA 30 -2 20 -4 10 -6 0 5 10 15 20 25 30 35 40 45 10 20 30 40 VI [V] VEN [V] Data Sheet 16 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Enable Input Current IEN versus Input Voltage VI, EN=Off 25_IINH vs VIN INH_off.vsd Enable High Level / Low Level Input Voltage VEN,H / VEN,L versus Junction Temperature Tj 25a_VINH_Tj_ INH_on.vsd [µA] 1.0 IEN VEN EN = OFF [V] 2.5 VI = 13.5V 0.8 2.0 VEN increasing 0.6 1.5 Tj = 150°C 0.4 1.0 VEN decreasing 0.2 Tj = 25°C Tj = -40°C 10 20 30 40 0.5 -40 -20 0 20 40 60 80 100 120 140 VIN [V] Tj [°C] Reset Threshold VRT versus Junction Temperature Tj (5V-Version) 26_VRT_VS_TEMP_5V.VSD Reset Hysteresis versus Junction Temperature Tj (5V-Version) 120 [mV] 29_VRT_HYSTERESIS-_VS_TEMP_5V.VSD VQ [V] VI = 13.5 V ∆V VI = 13.5 V 4.90 80 4.80 Reset Release Threshold 4.70 60 40 4.60 Reset Trigger Threshold -40 -20 0 20 40 60 80 100 120 140 20 -40 -20 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Data Sheet 17 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Reset Threshold VRT versus Junction Temperature Tj (3.3V-Version) 26_VRT_VS_TEMP_33V.VSD Reset Hysteresis versus Junction Temperature Tj (3.3V-Version) 120 [mV] 29_VRT_HYSTERESIS-_VS_TEMP_33V.VSD VQ [V] VI = 13.5 V ∆V VI = 13.5 V 3.20 Reset Release Threshold 3.10 80 60 3.00 Reset Trigger Threshold 40 2.90 20 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Reset Threshold VRT versus Junction Temperature Tj (2.6V-Version) 26_VRT_VS_TEMP_26V.VSD Reset Hysteresis versus Junction Temperature Tj (2.6V-Version) 120 [mV] 29_VRT_HYSTERESIS-_VS_TEMP_26V.VS D VQ [V] VI = 13.5 V ∆V VI = 13.5 V 2.50 Reset Release Threshold 80 2.40 Reset Trigger Threshold 60 2.30 40 2.20 20 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Data Sheet 18 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Reset Delay tRD Time versus Junction Temperature Tj 60 [ms] 27_RESETDELAY VS TEMP.VSD Reset Reaction Time trr versus Junction Temperature Tj 12 [µs] 28_RESETREACTION_VS_TEMP.VSD tRD VI = 13.5 V tRR VI = 13.5 V 40 SLOW Timing 8 30 6 20 4 FAST Timing 2 10 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Reset Output Sink Current IRO versus Junction Temperature Tj 4,40 [mA] 30_IRO_VS_TEMP.VSD Watchdog Timing tWD versus Junction Temperature Tj 80 [ms] 44_TWD_VS_TEMP.VSD IRO VI = 13.5 V tWD Timing for Ignore-, Open- Closed- Window VI = 13.5 V 3,60 60 SLOW Timing 3,20 50 2,80 40 2,40 30 FAST Timing -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Data Sheet 19 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Region of Stability ESR(CQ) versus Output Current IQ 100 12_ESR-IQ.VSD ESRCQ [Ω] CQ = 470nF Tj = -40...150 °C 10 1 Stable Region 0.1 0.01 0 100 200 IQ [mA] Data Sheet 20 Rev. 1.2, 2009-04-28 TLE7278-2 Package Outlines 6 Package Outlines 0.35 x 45˚ 1.75 MAX. 0.175 ±0.07 (1.47) C 4 -0.2 1.27 0.41+0.10 2) -0.06 14 B 0.1 0.2 M A B 14x 8 6±0.2 0.64 ±0.25 0.2 M C 1 7 1) 8.75 -0.2 A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01230 Figure 6 PG-DSO-14 (Plastic/Plastic Green - Dual Small Outline Package) Data Sheet 21 Rev. 1.2, 2009-04-28 8˚MAX. 1) 0.19 +0.06 TLE7278-2 Package Outlines 0.35 x 45˚ Stand Off (1.45) 1.7 MAX. 3.9 ±0.11) 0.1 C D 0 ... 0.1 0.19 +0.06 0.08 C 6 ±0.2 0.65 0.25 ±0.05 2) C 0.64 ±0.25 D 0.2 8˚ MAX. M 0.15 M C A-B D 14x D 8x A 14 8 Bottom View 3 ±0.2 1 7 1 7 B 0.1 C A-B 2x Exposed Diepad 14 8 4.9 ±0.11) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion PG-SSOP-14-1,-2,-3-PO V02 Figure 7 PG-SSOP-14 Exposed Pad Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 22 2.65 ±0.2 Dimensions in mm Rev. 1.2, 2009-04-28 TLE7278-2 Revision History 7 Revision 1.2 Revision History Date 2009-04-28 Changes 2.6V version, 5V version in PG-SSOP-14 package and all related description added: In “Features” on Page 2 “or 2.6V” added In “Features” on Page 2 package drawing for PG-DSO-14 updated, package drawing for PG-SSOP-14 added In “Overview” on Page 2 in table at the bottom types “TLE7278-2GV26” and TLE7278-2EV50” added In Table 3.2 “Pin Definitions and Functions (PG-DSO-14)” on Page 4 in description for Pin 1 “, TLE7273-2GV26” added In “Pin Assignment (PG-DSO-14)” on Page 4 “(PG-DSO-14)” added; In “Pin Definitions and Functions (PG-DSO-14)” on Page 4 “(PG-DSO-14)” added; In Table 3.2 “Pin Definitions and Functions (PG-DSO-14)” on Page 4 in description for pin 8 “; pull down to GND if not needed and turn off the watchdog with WM1 and WM2 pin” added “Pin Assignments (PG-SSOP-14 Exposed Pad)” on Page 5 and “Pin Definitions and Functions (PG-SSOP-14 Exposed Pad)” on Page 5 added In “Functional Range” on Page 7 Item 4.2.3 added, in Item 4.2.1 “, TLE72782EV50” added In Table 4.3 “Thermal Resistance” on Page 7 above Item 4.3.1 line with “Package PG-DSO-14” and values for PG-SSOP-14 package added: Item 4.3.6, Item 4.3.7, Item 4.3.8, Item 4.3.9 and Item 4.3.10 added In “Power On Reset and Reset Output” on Page 8 “and TLE7278-2EV50” in description added In “Electrical Characteristics” on Page 10 all specific items for 2.6V version added: Item 5.2.5, Item 5.2.6, Item 5.2.21, Item 5.2.25, Item 5.2.29, Item 5.2.40, Item 5.2.42 and Item 5.2.47 added; In Item 5.2.36, Item 5.2.37, Item 5.2.41 and Item 5.2.50 conditions for 2.6V version added; In Item 5.2.1, Item 5.2.2, Item 5.2.8, Item 5.2.19, Item 5.2.23, Item 5.2.27, Item 5.2.36, Item 5.2.37, Item 5.2.38, Item 5.2.44, Item 5.2.45, Item 5.2.49 and Item 5.2.51 in conditions “, TLE7278-2EV50” added In “Typical Performance Characteristics” on Page 14 Graphs “Reset Threshold VRT versus Junction Temperature Tj (3.3V-Version)” on Page 18, “Reset Hysteresis versus Junction Temperature Tj (3.3V-Version)” on Page 18, “Reset Threshold VRT versus Junction Temperature Tj (2.6VVersion)” on Page 18 and “Reset Hysteresis versus Junction Temperature Tj (2.6V-Version)” on Page 18 added In “Package Outlines” on Page 21 Outlines for PG-SSOP-14 package added: Figure 7 Data Sheet 23 Rev. 1.2, 2009-04-28 TLE7278-2 Revision History Revision 1.1 Date 2008-07-25 Changes 3.3V version and all related description added: In “Features” on Page 2“ 3.3V” added In “Overview” on Page 2 in table at the bottom type “TLE7273-2GV33” added In “Pin Definitions and Functions (PG-DSO-14)” on Page 4 in description for Pin 1 “TLE7273-2GV33: open drain output;” added In “Functional Range” on Page 7 Item 4.2.2 added In “Power On Reset and Reset Output” on Page 8 description for dimensioning external pull-up resistor at RO added; In “Electrical Characteristics” on Page 10 all specific Items for 3.3V version added: Item 5.2.3, Item 5.2.4, Item 5.2.20, Item 5.2.24, Item 5.2.28, Item 5.2.39, Item 5.2.41, Item 5.2.43, Item 5.2.46 and Item 5.2.50 added; In Item 5.2.36 and Item 5.2.37 Conditions for 3.3V version added; 1.0 2008-04-10 final version data sheet Data Sheet 24 Rev. 1.2, 2009-04-28 Edition 2009-04-28 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.