TLE8102SG

D a t a S h e e t , V 1. 4 , M ay 2 00 8 TLE8102SG S m a r t D ua l C h a n n e l P o w e r t r a in S w i t c h coreFLEX A u to m o t i v e P o w e r TLE8102SG Smart Dual Channel Powertrain Switch Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 2 2.1 3 3.1 3.2 4 4.1 4.2 5 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.4 5.3.5 5.4 5.5 5.6 5.6.1 5.6.2 5.7 6 7 8 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical and Functional Description of Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reverse Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Data Sheet 2 V1.4, 2008-05-08 Smart Dual Channel Powertrain Switch coreFLEX TLE8102SG 1 Features • • • • • • • • • Overview Overload Protection DMOS Overtemperature protection Open load detection Current limitation Low quiescent current mode 3.3 V µC compatible input Electrostatic discharge (ESD) protection Green Product (RoHS compliant) AEC Qualified PG-DSO-12-11 Description • • • • • • Proportional load current sense with improved Precision: +/- 6% at ID=3A and +/-3% Current Sense Temperature Deviation refering to TJ=25°C Two Low-Side Channels with RON(max. @ 150°C) = 360mOhm. IC Overtemperature warning 8-Bit SPI (for diagnosis and control) Short to GND detection Programmable overload behaviour Dual Current Sense Low-Side Switch in Smart Power Technology (SPT) with two open drain DMOS output stages. The TLE8102SG is protected by embedded protection functions and designed for automotive applications. The output stages can be controlled directly by parallel inputs for PWM applications (e.g. Oxygen Probe Heater) or by SPI. All output stages can provide a load current proportional sense signal. Diagnosis can be read from an 8-bit SPI or by the external fault pin. Type TLE8102SG Data Sheet Package PG-DSO-12-11 3 Marking TLE8102SG V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Overview Parameter Summary Parameter Supply voltage Drain source voltage On resistance Symbol Value 4.5 … 5.5 48 … 60 0.36 Unit V V Ω VDD VDS(CL) RON(max. @ 150°C) VDD IN1 IN2 input control proportional current sense temperature sensor short circuit detection open load detection selectable current limit gate control OUT1 OUT2 reset sleep mode SPI CS SCLK SI CO2 [SO / ST2] CO1 [IS1 / IS2 / ST1 / FAULT] current sense / diagnosis hardware configuration control, diagnostic and protective functions under current detection GND Overview .emf Figure 1 Block Diagram Data Sheet 4 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Overview 2 2.1 Overview Terms Figure 2 shows all terms used in this Target Data Sheet. Vbat IVDD VDD V DD V IN1 V IN2 VCS V SCLK V SI I SO IIN1 IN1 I IN2 IN2 I CS CS ISCLK SCLK I SI I ST2 SI CO2 [SO / ST2] V SO / ST2 I IS1 / IS2 / ST1 / FAULT V IS1 / IS2 / ST1 / FAULT CO1 [IS1 / IS2 / ST1 / FAULT] GND I GND OUT1 I D1 I D2 OUT2 VDS2 VDS1 Figure 2 Terms In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS1 and VDS2). Data Sheet 5 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Pin Configuration 3 3.1 Pin Configuration Pin Assignment P-DSO-12 IN2 SI OUT2 CO1 SCLK GND 1 2 3 4 5 6 12 11 10 9 8 7 P-DSO-12_TLE8102.vsd GND CO2 VDD OUT1 CS IN1 Figure 3 Pin Configuration (top view) Both GND pins and the heat sink must be connected to GND externally. 3.2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 Pin Definitions and Functions Symbol IN2 SI OUT2 CO1 SCLK GND IN1 CS OUT1 VDD CO2 GND Function Input Channel 2 SPI Signal In Power Output Channel 2 Current Sense 1/2/Fault/Status Ch1 SPI Clock Ground Input Channel 1 SPI Chip Select Power Output Channel 1 Supply Voltage SPI Signal Out/Status Ch2 Ground Data Sheet 6 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Maximum Ratings and Operating Conditions 4 4.1 Maximum Ratings and Operating Conditions Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 Parameter Supply Voltage Continuous Drain Source Voltage (OUT1 to OUT2) Input Voltage, All Inputs and Data outputs, Sense Lines Output Current per Channel2) Maximum Voltage for short circuit Protection (single event)3) Symbol Limit Values Min. Max. 7 48 7 V V V – – – Output ON Current Limit 2, slew rate 1 (default setting) Current Limit 2, slew rate 2 Current Limit 1, slew rate 1 or 2 Output Pins All other Pins – – -0.3 -0.3 -0.3 -3 – – – 4.1.6 Electrostatic Discharge Voltage (human body model) according to EIA/JESD22-A114-E DIN Humidity Category, DIN 40 040 IEC Climatic Category, DIN IEC 68-1 Unit Conditions VDD VDS VIN ID VSC, single ID(lim1,2) min. A 48 32 18 4000 2000 V V V V V VESD -4000 -2000 E 40/150/ 56 4.1.7 4.1.8 1) Not subject to production test, specified by design. 2) Output current rating as long as maximum junction temperature is not exceeded. The maximum output current in the application has to be calculated using RthJA depending onmounting conditions. 3) Device mounted on PCB (50 mm × 50 mm × 1.5 mm epoxy, FR4) with 6 cm2 copper heatsink area (one layer, 70 µm thick); PCB in test chamber with blown air. Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 7 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Maximum Ratings and Operating Conditions 4.2 Pos. 4.2.1 Operating Conditions Parameter Symbol Min. Output Clamping Energy (single EAS event), linearly decreasing current1) – Limit Values Typ. – Max. 75 mJ Unit Conditions ID(0) = 2 A, TJ(0) = 150 °C, max. 100 cycles over lifetime Thermal Resistance 4.2.2 4.2.3 4.2.4 4.2.5 RthJSP Junction to ambient (see Figure 4) RthJA Junction to case Operating Temperature Range Storage Temperature Range – – -40 -55 1.3 25 – – 2 – 150 150 K/W K/W °C °C Pv = 2W Pv = 2W – – Temperature Range Tj Tstg 1) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given by the related electrical characteristics table. PCB Dimensions: 76.2 x 114.3 x 1.5 mm³, FR4 Thermal Vias: diameter = 0.3 mm; plating 25 µm; 14 pcs. Metallisation according JEDEC 2s2p (JESD 51-7) + (JESD 51-5) 70µm modeled (traces) 1,5 mm 35µm, 90% metalization 35µm, 90% metalization 70µm, 5% metalization T hermal_Setup.vsd Figure 4 Thermal Simulation - PCB set-up Data Sheet 8 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks 5 5.1 Electrical and Functional Description of Blocks Power Supply The TLE8102SG is supplied by power supply line VDD, used for the digital as well as the analog functions of the device including the gate control of the power stages. A capacitor between pins VDD to GND is recommended. The TLE8102SG can be programmed via SPI to enter sleep mode. In sleep mode, all outputs are turned off and all diagnosis and biasing circuits are disabled. These actions reduce the quiescent current consumption from the power supply. However, the SPI configuration registers (except for the channel on/off register) are not reset when the TLE8102SG enters sleep mode. To exit sleep mode, a wake up command must be sent via SPI. Electrical Characteristics: Power Supply VDD = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.1.1 5.1.2 5.1.3 5.1.4 Parameter Supply Voltage Supply Current Supply Current in Sleep Mode Wake up Time (after sleep mode) 1) Symbol Min. Limit Values Typ. – – – – Max. 5.5 5 10 100 4.5 – – – Unit V mA µA µs Conditions – – – – VDD IVDD IVDD(sleep) twake 1) Not subject to production test, specified by design. 5.2 Parallel Inputs There are two input pins available on the TLE8102SG to control the output stages. Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1 and IN2 controls OUT2. Please refer to Figure 5 for details. The input pins are active high and each have an integrated pull-down current source. A comparator with hysteresis determines the state of the signal on INn. The zener diode protects the input circuit against ESD pulses. The BOL bit can be set via SPI. This bit determines if the output is exclusively controlled by the INn signals, exclusively controlled by the corresponding data bits CHnIN or by a Boolean OR or AND operation of the two inputs. The default setting of the BOL bits programs the outputs to be controlled exclusively by the INn signals. The SLEn bit can be set via SPI. This bit sets the slew rate of its assigned channel by selecting either slew rate 1 or slew rate 2. The slew rate also changes the over load switch off delay time (only for current limit 2). channel 2 channel 1 IN IN1 I IN1 CH1IN OR & SPI gate control BOL SLE1 Figure 5 Input Control and Boolean Operator Data Sheet 9 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Electrical Characteristics: Parallel Inputs VDD = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.2.1 5.2.2 5.2.3 5.2.4 Parameter Input Low Voltage Input High Voltage Input Voltage Hysteresis Input Pull-down Current (IN1 to IN2) 1) Symbol Min. Limit Values Typ. – – 200 50 Max. 1.0 – 400 100 – 2.0 100 20 Unit V V mV µA Conditions – – – – VINL VINH VINHys IIN(1 … 2) 1) Not subject to production test, specified by design. 5.3 5.3.1 Power Outputs Timing Diagrams The power transistors are switched on and off with a dedicated slope either via the parallel inputs or by the CHnIN bits of the serial peripheral interface SPI. The switching times tON and tOFF are designed equally. The switching time of each channel can be selected via SPI by programming the SLEn bit of the desired output. See Figure 6 for details CS SPI: O N tON SPI: O FF tOFF t VDS 80% 20% t Figure 6 Switching a Resistive Load 5.3.2 Inductive Output Clamp When switching off inductive loads, the potential at pin OUT rises to VDS(CL), as the inductance continues to drive current. The inductive output clamp is necessary to prevent destruction of the device. See Figure 7 for details. The maximum allowed load inductance and current, however, are limited. V bat ID VDS L, RL OUT VDS(CL) GND Figure 7 Data Sheet Inductive Output Clamp 10 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the TLE8102SG. This energy can be calculated with following equation: V bat – V DS(CL)   R L ⋅ ID L E = V DS(CL) ⋅ ------------------------------------ ⋅ ln 1 – ------------------------------------  + I D ⋅ -----RL RL V bat – V DS(CL)   The equation simplifies under the assumption of RL = 0:  V bat 2 1 E = -- LI D ⋅ 1 – ------------------------------------  2 V bat – V DS(CL)   The energy, which is converted into heat, is limited by the thermal design of the component. 5.3.3 Protection Functions The TLE8102SG provides embedded protective functions. Integrated protection functions are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered “outside” the normal operating range. Protection functions are not designed for continuous repetitive operation. Over load and over temperature protections are implemented in the TLE8102SG. Figure 8 gives an overview pf the protective functions. INn Input Control Tn temperature monitor gate control T OUTn CS SCLK SI SO FAULT CLn ST Status SPI current limitation / shutdown GND Figure 8 Protection Functions 5.3.3.1 Over Load Protection The TLE8102SG is protected in case of over load or short circuit of the load. If the device is programmed for current limitation (current limit 1), the current is limited to IDS(lim1). After time td(fault), the corresponding over load flag CLn is set. If using the status outputs for diagnosis, the over load flag is cleared immediately after the over load condition is no longer present. If using the SPI interface and fault pin for diagnosis, the over load flag of the affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission. If the TLE8102SG is programmed for current shutdown (current limit 2), the current threshold is IDS(lim2). However, unlike in current limit 1, after time td(fault), the affected channel is turned off and the according over load flag CLn is set. To turn on the channel again, this overload latch has to be reset by turning off the affected channel with either the parallel input or SPI. In addition, the switch off delay time can be programmed by changing the slew rate setting. If using the SPI interface and fault pin for diagnosis in case of current limit 2, the over load flag of the affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission when the IN pin is low. A valid SPI cycle would not lead to a reset of the OVL flag of the affected channel during the IN-Pin is high. In both cases, the channel may shut down due to over temperature. Data Sheet 11 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks For timing information, please refer to Figure 9 and Figure 10 for details. NO OVL O VL OVL Condition ON O FF IN ID (lim 1) I O UT V B at Inom Inom t d(fault) t d(fault) t d(fault) td(fault) t 125 °C1) – Sleep mode active 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 Reverse Current per channel1)2) Output Leakage Current Turn-On Time 1 Turn-On Time 2 Turn-Off Time 1 Turn-Off Time 2 Turn On slew rate Slew rate 1 Slew rate 2 Turn Off slew rate Slew rate 1 Slew rate 2 IC Overtemperature Warning1) Hysteresis1) Channel Overtemp. Shutdown1) Hysteresis1) Irev ID(lkg) tON tOFF sON – – – – – – 1 – ID = 2 A, resistive load ID = 2 A, resistive load Vbat = 14 V, ID = 2 A, resistive load, UDS = 80% to 30% 5.3.10 sOFF 1 – 20 5 185 – 200 – V/µs Vbat = 14 V, ID = 2 A, resistive load, UDS = 30% to 80% – – – – 5.3.11 5.3.12 Tw T(w) hys Tth(sd) T(sd)hys 155 – 170 – °C K °C K 1) Not subject to production test, specified by design. 2) Device functions normally, but supply current IVDD can be greater than 5 mA. Data Sheet 16 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks 5.4 Diagnostic Functions The TLE8102SG provides diagnosis information about the device and about the load. The following diagnosis functions are implemented: • • • • The protective functions (flags CLn and Tn) of channel n are registered in the diagnosis flag Pn. The open load diagnosis of channel n is registered in the diagnosis flag OLn. The under current diagnosis of channel n is registered in the diagnosis flag UCn. The short to ground monitor information of channel n is registered in the diagnosis flag SGn The diagnosis information of the TLE8102SG can either be accessed by status (ST) pins or the SPI interface and/or fault pin. With the exception of over temperature, a fault is only recognized if it lasts longer than the fault delay time td(fault). If using the status pins for diagnosis, the status pins change state in normal operation to match the input signal of the corresponding channel. If a fault condition appears and the fault delay time elapses, the status pin for the channel shows the inverted input signal. This diagnosis flag is not latched. Therefore, if the fault condition is removed, the status pins will indicate normal operation. Unlike the status pins, when using the SPI interface and/or fault pin, diagnosis flags are latched in the diagnosis register of the SPI interface. In this case, diagnosis flags are cleared by the rising edge of the CS signal after a successful SPI transmission. Please see Table 1 and Figure 13 for details. Table 1 Diagnostic Information Control Input Power Output Filter Time Status Output Fault Output Channel Channel Diagnosis Overtemp. Bits Flag MSB, LSB –– H, H H, H L, L L, H L, H L, H H, L H, L H, L H, L – L L L L L L L L H H Operating Condition Sleep Mode Normal Operation Short to ground Open load, Under current.1) x L H L H L H off off on off on off on on off off3) off 4) – – td(fault) td(fault) td(fault) td(fault) td(fault) td(off) L L H H L H L L L L L H H H L L L L L L L L Over load (current limit 1, H current limitation)1) Over load (current limit 2, H latching shutdown)2) Overtemp. (autorestart) Overtemp. (latching shutdown) H H – – 1) Short to ground/open load/ under current /overload/short-to-supply - events shorter than min. time td(fault) will not be latched and not reported at the diagnosis pins. 2) Overload/short-to-supply - events shorter than min. time td(off) will not be latched and not reported at the diagnosis pins. 3) Off as long as overtemperature occurs, restart after cooling down. 4) Shutdown latch reset by falling input edge. Data Sheet 17 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks VDD VDS (S G) SPI CHn MUX 00 01 10 SGn VDS (OL) OLn I DS (S G) OUTn IDS (P D) STn / FAULT ISn OR OR gate control under current detection UCn CLn Pn IIS n current sense OR protective functions Tn GND diagnosis.emf Figure 13 Block Diagram of Diagnostic Functions Electrical Characteristics: Diagnostic Functions VDD = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 Parameter Open Load Detection Voltage (Channel OFF) Output Pull-down Current (Channel OFF) Fault Filtering Time Overload switch off delay time (only current limit 2) Symbol Min. Limit Values Typ. 0.6 × Max. 0.7 × V µA µs µs V µA mA – – – Slew rate 1 Slew rate 2 – – – 0.5 × Unit Conditions VDS(OL) IPD(OL) td(fault) Td(off) VDD 25 50 10 10 0.3 × VDD 50 100 – – 0.4 × VDD 100 200 50 150 0.5 × Short to Ground Detection Voltage VDS(SHG) Output Pull-up Current (Channel OFF) VDD IPU(SHG) -50 100 VDD -100 170 VDD -150 300 Under Current Detection Threshold ID(OL) (Channel ON) Data Sheet 18 V1.4, 2008-05-08 TLE8102SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Figure 14 Open load (off) and Short to GND Diagnostics OL/ UC IN Inom O L(“O FF”)/U C (“O N ”) C ondition NO O L/U C ON O FF I OUT V Bat ID(UC) td(fault) t d(fault) td(fault) V DS(O L) set reset reset td(fault) t d(fault) td(fault) t d(fault) t