TLE8209-2SA

Data Sheet, Rev. 1.0, Feb. 2010 TLE8209-2SA SPI Programmable H-Bridge Automotive Power TLE8209-2SA Table of Contents Table of Contents 1 2 2.1 2.2 2.3 3 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.4 6 7 7.1 7.2 7.3 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 9.1 9.2 9.3 10 11 12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 5 7 7 8 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Basic Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDD Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDDIO - Digital Output Supply and Diagnostic Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics Power Supply and VDD-Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel or SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-Bridge or Single Switch Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis in Status Flag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Dependent Current Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit to Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit across the Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15 18 18 18 19 19 20 20 20 20 20 22 24 24 25 33 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Package Outlines TLE8209-2SA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data Sheet 2 Rev. 1.0, 2010-02-16 SPI Programmable H-Bridge TLE8209-2SA 1 Features • • • • • • • • • • • • • • • • • • • • • • Overview Programmable current limitation from 1.5 to 8.6 A typ. Full path RDSon of 240 mΩ (typ. at Tj=25°C) Operating battery supply voltage 4.5 V to 28 V Operating logic supply voltage 4.4 to 5.25 V Low standby current (8 µA typ.) Logic inputs TTL/CMOS-compatible All I/O pins overvoltage tolerant up to 18 V Enable and disable input Short circuit and overtemperature protection VS undervoltage protection VDD over and undervoltage protection Open load detection in off condition Temperature dependent current reduction Extensive diagnosis capabilities via SPI interface Status Flag for basic diagnosis without SPI Configurable as H-bridge or two independent half bridges Control of power stages by parallel inputs or via SPI Output switching frequency up to 11 kHz Slewrate programmable through SPI Excellent EMC performance AEC qualified Green product (RoHS compliant) PG-DSO-20-65 Functional Description The TLE8209-2SA is a SPI programmable H-bridge, designed for the control of DC motors in safety critical automotive applications. It features four selectable current ranges, two selectable slew rate settings and extensive diagnosis via SPI. The device monitors the digital supply voltage VDD and shuts down the output stages in case of VDD over- or undervoltage, thus providing a safe switch off path in case of malfunction of the digital control circuitry. In order to reduce power dissipation in extreme thermal conditions the current limitation threshold is reduced linearly for junction temperatures over 165°C. A thermal warning bit is set in the SPI. The two half bridges can also be used independently to drive two separate loads like solenoids or unidirectional DC motors. Type TLE8209-2SA Package PG-DSO-20-65 Body Width 430 mil Marking TLE8209-2SA Data Sheet 3 Rev. 1.0, 2010-02-16 TLE8209-2SA Pin Configuration 2 2.1 Pin Configuration Pin Assignment GND SO VDDIO SS/SF CP 1 2 3 4 5 6 7 8 9 10 21 GND 20 19 18 17 16 15 14 13 12 11 GND GNDABE VDD SCK SI VS IN1 OUT1 DIS GND VS IN2 OUT2 ABE GND Figure 1 Pinout TLE8209-2SA 2.2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Definitions and Functions Symbol GND SO Function in SPI Mode Ground SPI Serial Data Out Supply Voltage for Logic Output Buffer Slave Select (low active) Pin for external Charge Pump Capacitor Function in Status Flag Mode Ground no function - connect to GND Switches to SF-mode if connected to GND Status Flag (low active) Pin for external Charge Pump Capacitor VDDIO SS/SF CP VS IN1 OUT1 DIS GND GND ABE OUT2 IN2 Battery Supply Voltage, has to be connected to Battery Supply Voltage, has to be pin 15 connected to pin 15 Input 1 Output 1 Disable Ground Ground Bidirectional Enable Pin Output 2 Input 2 Input battery supply voltage, has to be connected to pin 6 SPI Serial Data Input 4 Input 1 Output 1 Disable Ground Ground Bidirectional Enable Pin Output 2 Input 2 Input battery supply voltage, has to be connected to pin 6 no function - connect to GND Rev. 1.0, 2010-02-16 VS SI Data Sheet TLE8209-2SA Pin Configuration Pin 17 18 19 20 21 Symbol SCK Function in SPI Mode SPI Clock Function in Status Flag Mode no function - connect to GND VDD GNDABE GND GND VDD supply Sense ground for VDD monitoring Ground Heatslug - connect to GND VDD supply Sense ground for VDD monitoring Ground Heatslug - connect to GND 2.3 Terms I CP IS I DD VDD IGNDS VGNDS CP VS VCP VS VDD GNDS IIN 1 IIN 2 VIN1 VIN2 VDIS VEN I DIS IEN IN1 IN2 DIS EN VOUT1 OUT2 IOUT2 VOUT2 OUT1 I OUT1 I SO ISI VSO VSI I SCK ICSN/ SF IDDIO VCSN/SF VDDIO VSCK SO SI SCK CSN/SF VDDIO GND Figure 2 Terms TLE8209-2SA Data Sheet 5 Rev. 1.0, 2010-02-16 TLE8209-2SA Block Diagram 3 Block Diagram CP VDD GNDABE VDDMonitoring internal Supply VS IN1 IN2 DIS ABE SO SI SCK SS/SF VDDIO SPI/Flag Logic VS Undervoltage Gate Control OUT1 OUT2 Diagnostics GND Figure 3 Block Diagram TLE8209-2SA Data Sheet 6 Rev. 1.0, 2010-02-16 TLE8209-2SA General Product Characteristics 4 4.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 °C to 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 4.1.1 4.1.2 4.1.3 4.1.4 Parameter Junction temperature Storage temperature Ambient temperature Battery supply voltage Symbol Limit Values Min. Max. 150 175 150 125 40 40 °C °C °C V V – 100h cumulative – – Static destruction proof Dynamic destruction proof t < 0.5 s (single pulse, Tjstart < 85 °C) – – – -40 150 -55 -40 -0.5 -2 Unit Test Conditions / Comment Tj Ts Ta VS 4.1.5 4.1.6 4.1.7 Logic supply voltage Supply for logic out Voltage at logic pins ABE, IN1, IN2, DIS, SCK, SS/SF, SI Voltage at SO Voltage at CP Voltage at GNDABE ESD Resistivity to GND VDD VDDIO VIN -0.5 -0.5 -0.5 18 18 18 V V V 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 VSO -0.5 VDDIO +0.3 V – 0V < VS < 40V VCP VS-0.3 VS+5.0 V VGNDABE VGND-0.3 VGND+0.3 V VESD -2 -8 -500 -750 2 8 500 750 kV kV V V ESD Susceptibility HBM2) HBM2), Pins OUT1 and OUT2 CDM3) CDM3), Pins 1, 10, 11, 20 1) Not subject to production test, specified by design. 2) ESD susceptibility HBM according to EIA/JESD22-A114-B (1.5kΩ, 100pF) 3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 7 Rev. 1.0, 2010-02-16 TLE8209-2SA General Product Characteristics 4.2 Pos. 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 Operating Range Parameter Symbol Limit Values Min. Max. 28 5.25 5.5 11 150 V V V kHz °C – – – – – 4.5 4.4 0 – -40 Unit Remark VS supply voltage range VDD supply voltage VDDIO supply voltage PWM frequency Junction temperature VS VDD VDDIO f TJ Note: Within the operating range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Pos. 4.3.6 4.3.7 Thermal Resistance Parameter Junction to Case1) Junction to Ambient 1) Symbol Min. Limit Values Typ. – 17 Max. 1.6 – – – Unit K/W K/W Remark – 2) RthJC RthJA 1) Not subject to production test, specified by design. 2) Simulation according to Jedec JESD51-2,-5,-7; natural convection; FR4 2s2p board 76.2 x 114.3 x 1.5 mm (2 x 70µm Cu, 2 x 35µm Cu) Data Sheet 8 Rev. 1.0, 2010-02-16 TLE8209-2SA Power Supply 5 5.1 Power Supply Basic Supply Characteristics The TLE8209-2SA has three different supply pins: VDD, VS and VDDIO. VDD is used to supply the internal logic circuitry. VS connects to battery voltage and supplies the output stages. The voltage at pin VDDIO defines the high level output voltage at the pin SO of the SPI interface. VDDIO is also used as a mode select pin. If VDDIO is connected to ground, the device is set to status flag mode (SPI inactive). On power up the device will enter a functional state when VDD rises above the functional reset threshold VDD_RES. In this state all output stages are inactive and internal registers are cleared. When VDD rises further above the power on reset threshold VDD_POR the device starts operation with a delay time of tPOR. 5.2 VDD Monitoring The logic supply voltage level at the pin VDD is monitored. If the voltage at pin VDD is out of the permissible range of VDD_L … VDD_H the power stages of TLE8209-2SA are switched off and pin ABE is pulled to ground. To suppress glitches in the VDD monitoring, a glitch filter is implemented.VDD is measured with reference to pin GNDABE. The state of VDD monitoring is stored in STATCON_REG and can be read out via SPI. The output stages can also be turned off by pulling the ABE pin to ground externally. In case of VDD failure, the output stages are switched off, even if the pin ABE should be connected to a high level signal because of external short circuit to VDD or battery voltage (up to 18V). OUT1 and OUT2 cannot be switched on in over- or undervoltage condition, switching off is always possible. A power on reset (VDD < VDD_POR) switches off all stages without delay. Control of VDD-monitoring is possible in SPI mode only. Detailed information (differentiation of over and undervoltage detection) is only possible by SPI interface. Behavior of VDD monitoring in SF mode: - monitoring is present with the specified values for over- and undervoltage - any test of over- and undervoltage threshold is not possible - the latch for overvoltage is disabled VDD Undervoltage If the VDD voltage is lower than the supply voltage supervisory lower threshold (VDD_THL), output stages are shut off after a filtering time (tFIL_OFF) and the bi-directional pin ABE is pulled low. At the transition from undervoltage to normal voltage the signal at pin ABE goes high and the output stages will return to normal operation after a filtering time (tFIL_ON) has expired. For output control via SPI the bits MUX and SINx in the config register have to be reprogrammed. New failures are not stored to diagnostic registers during undervoltage, register content remains valid, writing new information to configuration registers is possible as far as they are not reset by ABE. If VDD falls below the power-on-reset supply voltage (VDD_POR) all stages are shut off and ABE is switched active low. When VDD is rising above the power-on-reset supply voltage threshold (VDD_POR) a power-on-reset is generated (tPOR), setting all registers to its default state. VDD Overvoltage If the VDD voltage is higher than the supply voltage supervisory upper threshold (VDD_THH), all output stages are shut off after a filtering time (tFIL_OFF) and the bi-directional pin ABE is pulled low. The behavior of the ABE level and output stages on the return of VDD from overvoltage to the correct range is configured in STATCON_REG, bit CONFIG0) CONFIG0=’1’: ABE is latched and outputs remain off after overvoltage. Return to normal operation is only possible with power-on reset or by changing this bit via SPI. Data Sheet 9 Rev. 1.0, 2010-02-16 TLE8209-2SA Power Supply CONFIG0=’0’: ABE is inactive after VDD returned to normal operating voltage and filtering time has expired. At the transition from overvoltage to normal condition, the output stages will return to normal operation. For output control via SPI the bits MUX and SINx in the config register have to be re-programmed. New failures are not stored to diagnostic registers during overvoltage, register content remains valid, writing new information to configure registers is possible as far as they are not reset by ABE. VDD Monitoring Test Mode Testing of VDD monitoring is possible in SPI mode only. The latch function for over voltage at VDD has to be switched of (CONFIG0=0 in STATCON_REG) Testing upper threshold: By writing 00xxxxxxb into STATCON_REG, the overvoltage threshold is reduced to VDD_TEST_H. STATCON_REG bit 2 and 0 have to be LOW then. After writing 1xxxxxxxb to STATCON_REG, bit 2 and 0 in STATCON_REG must be HIGH again Testing lower threshold: By writing 01xxxxxxb into STATCON_REG, the undervoltage threshold is increased to VDD_TEST_L. STATCON_REG bit 2 and 1 have to be LOW then. After writing 1xxxxxxxb to STATCON_REG, bit 2 and 1 in STATCON_REG must be HIGH again. 5.3 VDDIO - Digital Output Supply and Diagnostic Mode Selection The voltage at VDDIO is used to supply the output buffer at the SO pin (serial output of SPI-interface). The VDDIO pin is also used to select SPI- or in status flag (SF) diagnostic mode. As soon as VDDIO is lower than VDDIO_L, the device is put into status flag mode. . VDDIO to internal logic (SF-mode / SPI-mode) + SF/SPI - mode threshold VDDIO_L from internal logic SO Figure 4 VDDIO and SO-Pin Data Sheet 10 Rev. 1.0, 2010-02-16 TLE8209-2SA Power Supply 5.4 Electrical Characteristics Power Supply and VDD-Monitoring Electrical Characteristics: Power Supply and VDD-Monitoring VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 °C to 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Supply 5.4.1 Supply Current Parameter Symbol Min. Limit Values Typ. 8 2.1 Max. 20 4 µA mA Unit Test Conditions IVS – – – – – 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 Functional Reset Threshold VDD_RES Power On Reset Threshold VDD_POR Power On Reset Delay Time VDD Input current VDDIO Input current – 3.5 – – – 2.5 4 4.8 1.4 3.75 0.22 7 30 5 9 13 2.5 4.0 0.5 9 100 mA mA mA V V ms mA µA IOUT = 0 A, VDD = 0V, VS < 18 V, Tj < 125°C bridge disabled, IOUT = 0 A, 5 V < VS < 18 V f = 2 kHz, IOUT = 0 A, 5 V < VS < 18 V f = 10 kHz, IOUT = 0 A, 5 V < VS < 18 V f = 10 kHz, IOUT = 0 A, 5 V < VS < 28 V – – tPOR IDD IDDIO VDD = on --> output stage active, no load 4.5V < VDD < 5.5V SPI-mode no load at SO no SPI communication – – – Voltage referred to GNDABE 5.4.7 5.4.8 5.4.9 5.4.10 5.4.11 5.4.12 5.4.13 5.4.14 5.4.15 SF-mode Threshold SPI-mode Threshold Mode selection hysteresis Overvoltage threshold Undervoltage threshold Test mode reduced Overvoltage threshold Test mode increased Undervoltage threshold Filter time for glitch suppression Maximum Slew Rate on VDD1) VDDIO_L VDDIO_H VDDIO_HYS VDD_THH VDD_THL VDD_TEST_H VDD_TEST_L tFIL VDD_slew – 2.0 0.2 5.25 4.2 4.2 5.25 60 – – – 0.5 5.4 4.3 4.3 5.4 100 – 1.0 – 1.0 5.5 4.4 4.4 5.5 135 0.5 V V V V V V V µs V/µs VDD-Monitoring – – 1) Not subject to production test; specified by design Data Sheet 11 Rev. 1.0, 2010-02-16 TLE8209-2SA Logic Inputs and Outputs 6 Logic Inputs and Outputs The threshold specifications for the logic inputs are compatible to both 5 and 3.3 V standard CMOS microcontroller ports. All inputs (except ABE) feature internal pull-up current sources. The logic output SO is supplied by VDDIO. VDDIO can be supplied with either 5 or 3.3 V, so the output thresholds of SO can be configured to the required I/O voltage. Electrical Characteristics: Control Inputs VS = 5 V to 28 V; VDD = 5.0 V; Tj = -40 °C to 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. IN1, IN2 6.0.1 6.0.2 6.0.3 6.0.4 6.0.5 6.0.6 DIS 6.0.7 6.0.8 6.0.9 6.0.10 6.0.11 6.0.12 6.0.13 ABE 6.0.14 6.0.15 6.0.16 6.0.17 6.0.18 6.0.19 6.0.20 6.0.21 SI 6.0.22 6.0.23 6.0.24 6.0.25 6.0.26 Low level High level Hysteresis Input Current (Pull Up) Input Capacity 1) Parameter Symbol Min. Limit Values Typ. – – – -20 2 – – – – -125 2 – 0.8 – – – – – 0.8 40 – – – – -20 Max. 1.0 Unit Test Conditions Low level High level Hysteresis Input Current (Pull Up) VINx_L VINx_H VINx_HYS IINx -0.3 2.0 0.2 -30 0 V V V µA µA pF V V V µA µA pF µs V V V V V µs µA µA V V V µA pF – – – 0 V < VINx < 2.1 V VDD+0.3 1.0 -10 5 20 1.0 VINx > 3.0 V 2) Input Capacity1) Low level High level Hysteresis Input Current (Pull Up) CINx – -0.3 2.0 0.2 -200 0 VDIS_L VDIS_H VDIS_HYS IDIS – – – 0 V < VDIS< 2.1 V VDD+0.3 1.0 -50 5 20 1.5 1.2 1.0 – 0.3*VDD 1.0 1.5 120 60 1.0 VDIS > 3.0 V 2) Input Capacity1) Minimum Pulse Width 1) CDIS tDIS – 0.4 – Output low-level voltage VABE_OUTL – – Input threshold high VDD_THH < VDD < 18 V IABE < 5 mA 2.5 V < VDD < VDD_THL IABE < 1 mA – – – – 1.5 V < VABE < 18 V 0 V < VABE < 1.5 V – – – 0 V < VSI < 2.1 V 2) VABE_INH Input threshold low VABE_INL Hysteresis VABE_INHY 1) Minimum pulse width tABE ABE Input current (Pull -IABE_L Down) 0.7*VDD – 0.2 0.4 20 0 VSI_L VSI_H VSI_HYS ISI CSI -0.3 2.0 0.2 -30 VDD+0.3 1.0 -10 14 Data Sheet 12 Rev. 1.0, 2010-02-16 TLE8209-2SA Logic Inputs and Outputs Electrical Characteristics: Control Inputs (cont’d) VS = 5 V to 28 V; VDD = 5.0 V; Tj = -40 °C to 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. SCK 6.0.27 6.0.28 6.0.29 6.0.30 6.0.31 SS/SF 6.0.32 6.0.33 6.0.34 6.0.35 6.0.36 6.0.37 6.0.38 6.0.39 6.0.40 SO 6.0.41 6.0.42 6.0.43 6.0.44 Low level High level Output capacitance1) Leakage current Input Current in SF mode (Open Drain) Input Capacity 1) Parameter Symbol Min. Limit Values Typ. – – – -20 – – – – -20 – 2 2 – – – Max. 1.0 Unit Test Conditions Low level High level Hysteresis Input Current (Pull Up) Input Capacity Low level High level Hysteresis Input Current in SPI mode (Pull Up) 1) VSCK_L VSCK_H VSCK_HYS ISCK CSCK -0.3 2.0 0.2 -30 – -0.3 2.0 0.2 -30 -30 0 V V V µA pF V V V µA µA µA µA µA pF V V pF µA – – – 0 V < VSCK < 2.1 V 2) VDD+0.3 1.0 -10 14 1.0 VSS_L VSS_H VSS_HYS ISS – – – 0 V < VSS < 2.1 V VDD+0.3 1.0 -10 5 5 5 – 15 0.4 ISF CSS 0 300 – 0.0 2.1 V < VSS < 3.0 V VSS > 3.0 V VSF = 5.0 V, SF inactive VSF = 1.0 V, SF active 2) VSO_L VSO_H CSO ISO VDDIO-0.75 – – -2 – – VDDIO 19 2 ISO = 2 mA ISO = -2 mA 2.9 V < VDDIO < 5.5 V In tristate2) In tristate 0 < VSO < VDDIO 1) Not subject to production test; specified by design 2) Vbias = 2 V; Vtest = 20 mVpp; f = 1 MHz Data Sheet 13 Rev. 1.0, 2010-02-16 TLE8209-2SA Power Stages 7 Power Stages The TLE8209-2SA contains four n-channel power-DMOS transistors that can be used in an H-bridge or in dual half bridge configuration. Integrated circuits protect the outputs against overcurrent and over-temperature, in case of short-circuit to ground, to the supply voltage or across the load. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes (body diodes of power-DMOS). 7.1 Parallel or SPI Control By default the setting of the power switches is controlled by the Inputs IN1, IN2 (parallel control). The outputs OUT1 and OUT2 are set to High (high-side switch ON, low-side switch OFF) or Low (high-side switch OFF, lowside switch ON) by the parallel inputs IN1 and IN2, respectively. In SPI mode there is also the option to control the outputs via the SPI bits SIN1 and SIN2 of the SPI configuration register. To switch to SPI control the bit MUX has to be set to ’0’. In addition, the outputs can be disabled (set to tristate, high- and low-side switch OFF) by the disable input DIS and the bidirectional reset pin ABE. Disabling sets the device to parallel control Table 1 shows the different options for the output control. 7.2 H-Bridge or Single Switch Usage The IC can be set to H-bridge mode or single-switch mode by SPI. This setting changes the behavior of the device in the following features: • • • current limiting overcurrent shut-down open load diagnosis Functional Truth Table DIS L L ABE H H H H H H H H X L IN1 H L L H X X X X X X IN2 L H L H X X X X X X SPI MUX 1 1 1 1 0 0 0 0 X X SPI SIN1 X X X X 1 0 0 1 X X SPI SIN2 X X X X 0 1 0 1 X X OUT1 H L L H H L L H Z Z OUT2 L H L H L H L H Z Z Table 1 Pos. Forward, parallel ctrl. Reverse, parallel ctrl. Free-wheeling low, parallel ctrl. L Free-wheeling high, parallel ctrl. L Forward, SPI ctrl. Reverse, SPI ctrl. Free-wheeling low, SPI ctrl. Free-wheeling high, SPI ctrl. Disabled by DIS Disabled by ABE Table 2 OUT H L Z OUT States L L L L H X High-Side DMOS ON OFF OFF Low-Side DMOS OFF ON OFF Data Sheet 14 Rev. 1.0, 2010-02-16 TLE8209-2SA Power Stages 7.3 Electrical Characteristics Power Stages Electrical Characteristics: Power Stage VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 °C to 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Power Outputs OUT1, OUT2 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 Switch on resistance low side Switch on resistance high side Leakage current Free-wheel diode forward voltage Free-wheel diode reverse recovery time1) Rise time HS Fall time HS Rise time LS Fall time LS Rise time HS Fall time HS Rise time LS Fall time LS Output on-delay Output off-delay Output on-delay Output off-delay Output on-delay Output off-delay Output on-delay Output off-delay Limit Values Typ. 125 215 115 200 – 0.9 – Max. – 250 – 240 200 1.1 100 µA V ns mΩ mΩ Unit Test Conditions ROUT1L ROUT2L ROUT1H ROUT2H IOUT1(off) IOUT2(off) UD trr – – – – -200 – – IOUTx = 3 A; Tj = 25°C IOUTx = 3 A; Tj = 150°C IOUTx = 3 A; Tj = 25°C IOUTx = 3 A; Tj = 150°C Output stage switched off VS = 13 V ID = 3 A – Output Switching Times - Fast Slew Rate 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 7.3.15 7.3.16 7.3.17 7.3.18 7.3.19 7.3.20 7.3.21 tr (HS) tf (HS) tr (LS) tf (LS) tr (HS) tf (HS) tr (LS) tf (LS) tdon tdoff tdon tdoff tdon tdoff tdon tdoff 3.5 3.5 3.5 3.5 15 15 18 18 – – – – – – – – 6.0 6.0 6.0 6.0 30 30 30 30 – – – – – – – – 10 10 8.5 8.5 48 48 48 48 12 7 13 12 41 25 42 26 µs SPI bit SL=’0’ VS = 8..18 V; IOUT = 3 A Output Switching Times - Slow Slew Rate µs SPI bit SL=’1’ VS = 8..18 V; IOUT = 3 A Output Delay - Parallel Control, Fast Slew Rate µs µs µs VS = 8..18 V; IOUT = 3 A VS = 8..18 V; IOUT = 3 A Output Delay - SPI Control, Fast Slew Rate Output Delay - Parallel Control, Slow Slew Rate µs VS = 8..18 V; IOUT = 3 A Output Delay - SPI Control, Slow Slew Rate µs VS = 8..18 V; IOUT = 3 A Data Sheet 15 Rev. 1.0, 2010-02-16 TLE8209-2SA Power Stages Electrical Characteristics: Power Stage VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 °C to 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Enable and Disable Delay Times 7.3.22 7.3.23 7.3.24 7.3.25 7.3.26 Disable delay time, fast slew rate Disable delay time, slow slew rate Enable delay time, fast slew rate Enable delay time, slow slew rate Power on delay time Limit Values Typ. 8 38 8 38 0.1 Max. 20 75 20 75 0.4 ms µs VS = 8..18 V; IOUT = 3 A Unit Test Conditions tddis tddis tdel tdel tdel – – – – – VS = on --> output stage active, no load 1) Not subject to production test - specified by design tRISE 90% OUTx 10% tFALL 90% 10% Figure 5 Output Switching Time V 5 INx 0 30% 30% 90% OUTx 10% tdon tdoff Figure 6 Data Sheet Output Delay Time – Low-Side FETs 16 Rev. 1.0, 2010-02-16 TLE8209-2SA Power Stages V 5 ABE 0 50% 50% t 3A 90% IOUT 10% 0 tddis tden t Figure 7 ABE pin - Enable and Disable Delay Time V 5 DIS 30% 0 30% t 3A 90% IOUT 10% 0 tddis tden t Figure 8 DIS pin - Enable and Disable Delay Time Data Sheet 17 Rev. 1.0, 2010-02-16 TLE8209-2SA Protection and Monitoring 8 • • • • • • Protection and Monitoring Short to battery voltage (SCB). Can be detected when low side-switches are turned on Short to ground (SCG). Can be detected when high side-switches are turned on Open load (OL). Can be detected in inactive mode Over-temperature (OT). Can be detected in active and inactive mode VDD over- and under voltage (Chapter 5.2) Battery under voltage detection. Can be detected in active and inactive mode Both output stages of the TLE8209-2SA are equipped with fault diagnostic functions: Individual detection for each output in single switch operation mode (SCB, SCG, OL) is possible. The corresponding diagnostics bits for each failure will be set in the SPI according to Table 8 “Failure Encoding” on Page 29. 8.1 Diagnosis in Status Flag Mode Instead of using the SPI interface for control and diagnosis of the TLE8209-2SA, the device can also be set into status flag mode by connecting pin VDDIO to GND as described in Chapter 5.3. In status flag mode the pin SF will be pulled low in the following cases: • • • • • undervoltage at VS bridge disabled by ABE or DIS bridge disabled by VDD monitoring bridge disabled by short circuit detection overtemperature shut down SF will not be pulled low if VDD is below the power on reset threshold (VDD_POR). 8.2 Current Limitation To limit the output current at low power loss, a chopper current limitation is integrated. Current measurement for current limitation is done in the high side path. This requires high side freewheeling in case of active current limitation. ttrans tb IL Ihys IOUT HS1 LS1 time Figure 9 Chopper Current Limitation HS2 LS2 Figure 9 shows the behavior of the current limitation for over current detection in HS1. It applies accordingly also for HS2: When the current in high-side switch of OUT1 (HS1) exceeds the limit IL longer than the blanking time tb, OUT2 is switched to high (e.g. LS2->OFF, HS2->ON), independent of the input signal at IN2. This leads to a slow-decay current decrease in the load and in HS1. As soon as the current falls below IL-Ihys, OUT2 is switched back to normal Data Sheet 18 Rev. 1.0, 2010-02-16 TLE8209-2SA Protection and Monitoring operation, i.e. the outputs follow the inputs according to the truth table. The current limit IL can be programmed to four different values by setting the SPI bits CL1 and CL2 in the SPI configuration register. To avoid high chopper frequencies the time between two transients ttrans is limited. Current limitation is available in H-bridge operation mode, not in single switch operation mode. This means, that the current limit, current limit hysteresis and blanking time has no effect in single switch operation mode. 8.3 Temperature Dependent Current Reduction For TILR < Tj < TSD the current limit decreases from IL as set by the SPI to IL_TSD = 2.5 A typ. as shown in Figure 10. A IL tolerance of temperature dependent current reduction range of overtemperature shut-down (typ. 2.5A) IL_TSD TSD TILR (typ. 165°C) (min. 175°C) Tj [°C] Figure 10 Temperature Dependent Current Reduction 8.4 Short Circuit to Ground current IOUK IL short circuit detected current limitation active output off current tracking I hys tb t< tb tDF_H tDF_OFF time tristate I OUT Short IN1 OUT1 IN2 OUT2 tristate Figure 11 Data Sheet Short to Ground Detection 19 Rev. 1.0, 2010-02-16 TLE8209-2SA Protection and Monitoring The short circuit to ground detection is activated when the current through one of the high side switches rises over the threshold IOUK and remains higher than IOUK for at least the filter time tDF_H within the blanking time tb. The output stage in which the short circuit was detected will be switched off within tDF_OFF. In H-bridge mode also the other output will be switched off after a short delay of tDF_del . In single switch mode only the affected output will be switched off. 8.5 Short Circuit to Battery A short circuit to battery is detected in the same way as a short circuit to ground, only in the low side switch instead of the high side switch. 8.6 Short Circuit across the Load Short circuit over load is indicated by two failures - short circuit to ground on one output and short circuit to battery on the other output. Both failure bits will be set in the SPI diagnostics register. Both output stages will be turned off. 8.7 Overtemperature In case of high DC-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above the thermal shut-down temperature TSD (see Figure 10). In that case, all output transistors are turned off. 8.8 Undervoltage Shut-Down If the supply voltage at the VS pins falls below the undervoltage detection threshold VUV_OFF, the outputs switches are turned off. As soon as VS rises above VUV_ON again, the device is returning to normal operation. 8.9 Open Load Diagnosis Open load diagnosis is only possible if outputs are switched off by DIS or ABE. The diagnostic current sources are deactivated in status flag mode. Diagnostic current sources are disconnected if outputs are active. That means that the diagnostic current sources are also disconnected if the outputs are deactivated due to short circuit. The open load detection in H-bridge mode is different from the open load detection in single switch mode. Open Load Detection in H-Bridge mode VDD OUT1 OUT2 Vref_L + - OUT1_L Vref_L + - OUT2_L Figure 12 Open Load Detection in H-Bridge Mode Data Sheet 20 Rev. 1.0, 2010-02-16 TLE8209-2SA Protection and Monitoring Table 3 < Vref_L < Vref_L > Vref_L > Vref_L H H L L Open Load Detection in H-Bridge Mode VOUT2 < Vref_L > Vref_L < Vref_L > Vref_L OUT2_L H L H L Diagnostic Load o.k. Load o.k. Open Load Load o.k. transient area Comment pull down current is stronger transient area VOUT1 OUT1_L Open Load Detection in Single Switch Mode VDD Vref_M Vref_H VDD OUTx Vref_M V ref_H V ref_L + Vref_L + - OUTx_H + - OUTx_L Figure 13 Table 4 Open Load Detection in Single Switch Mode Open Load Detection in Single Switch Mode OUTx_H L L H OUTx_L H L L Diagnostic o.k. Open Load o.k. Comment Load to ground Output open Load to VS VOUTx (OFF State) VOUTx < Vref_L Vref_L Vref_H Data Sheet 21 Rev. 1.0, 2010-02-16 TLE8209-2SA Protection and Monitoring 8.10 Electrical Characteristics Electrical Characteristics: Protection and Monitoring VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 °C to 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Chopper Current Limitation 8.10.1 8.10.2 8.10.3 8.10.4 8.10.5 8.10.6 8.10.7 8.10.8 8.10.9 8.10.10 8.10.11 Current Limit Hysteresis Blanking time Time between transients Current Limit at TSD Start of current limit reduction Thermal shut-down Range of temperature dependent current reduction Short circuit detection current (HS) Current Limit |IL1| |IL2| |IL3| |IL4| 1.0 3.3 5.5 7.7 0 8 90 1) Limit Values Typ. 1.5 4.0 6.6 8.6 0.25 11 – 2.5 165 – 25 Max. 2.0 4.7 7.7 10.5 0.40 15 130 3.6 – – 30 Unit Test Conditions A -40 °C < Tj < TILR Dependent on SPI setting; Default = IL3 -40 °C < Tj < TILR – – – – – – Ihys tb ttrans IL_TSD A µs µs A °C °C °C Temperature Dependent Current Limitation 1.4 150 175 20 TILR TSD TSD - TILR Short Circuit Detection to GND 8.10.12 8.10.13 8.10.14 8.10.15 8.10.16 8.10.17 8.10.18 8.10.19 Short Circuit Detection to VS 8.10.20 8.10.21 8.10.22 8.10.23 8.10.24 8.10.25 8.10.26 8.10.27 Current tracking Short circuit detection current (LS) |IOUKL1| |IOUKL2| |IOUKL3| |IOUKL4| 2.5 5.0 7.5 9.5 4.6 7.9 9.8 14 3.0 4.0 3.5 5.1 6.5 10 11.5 17.4 5.0 5.5 5.5 8.0 A A -40 °C < Tj < TILR Dependent on SPIsetting for |IL|; Default = Current tracking |IOUKH1| |IOUKH2| |IOUKH3| |IOUKH4| 2.5 5.0 7.5 9.5 5.0 7.3 9.5 11.8 3.5 3.3 3.2 3.0 6.5 10 11.5 17.4 5.0 5.0 5.0 5.0 A A -40 °C < Tj < TILR Dependent on SPIsetting for |IL|; Default = IOUKH3 |IOUKH1| - |IL1| 2.0 |IOUKH2| - |IL2| 2.0 |IOUKH3| - |IL3| 2.0 |IOUKH4| - |IL4| 1.8 IOUKL3 |IOUKL1| - |IL1| 1.5 |IOUKL2| - |IL2| 2.0 |IOUKL3| - |IL3| 1.8 |IOUKL4| - |IL4| 2.0 Data Sheet 22 Rev. 1.0, 2010-02-16 TLE8209-2SA Protection and Monitoring Electrical Characteristics: Protection and Monitoring VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 °C to 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Short Circuit Detection Timing 8.10.28 8.10.29 8.10.30 Delay time for fault detection Limit Values Typ. 2 – 17 Max. 5 4 40 µs µs µs – – – Unit Test Conditions tDF_H, tDF_L 1 – 5 Time from detected fault to tDF_OFF high impedance of output1) Delay time between switching off of the output stages in short circuit Open Load Diagnostic Filter Time1) Low Diagnosis Threshold tDF_del Open Load 8.10.31 8.10.32 tOL_DIAG Vref_L 60 0.4 * VDD 0.2 0.8 * VDD 0.2 0.6 * VDD 0.2 300 270 -350 -350 2 – 0.4 * VDD 0.8 * VDD 0.6 * VDD 620 610 -240 -210 2.9 135 µs – – 0.4 * VDD V + 0.2 0.8 * VDD V + 0.2 0.6 * VDD V + 0.2 980 980 -100 -80 4 µA µA µA µA – 8.10.33 High Diagnosis Threshold Vref_H – 8.10.34 Diagnosis Bias Voltage Vref_M – 8.10.35 8.10.36 8.10.37 8.10.38 8.10.39 Positive Diagnostic Current IDIA_P (pull down current source) Negative Diagnostic Current Ratio of current sources (Pos/Neg) Undervoltage at VS IDIA_N RatioI_DIA VOUTx = 14 V VOUTx = Vref_H VOUTx = 0 V VOUTx = Vref_L – Undervoltage VUV OFF VUV ON VUV HY 8.10.41 VS Undervoltage Detection tUV 8.10.40 Filter Time1) 1) Not subject to production test; specified by design. 3.1 3.3 100 – 3.7 3.9 200 – 4.4 4.6 400 1.5 V V mV µs Switch off threshold Switch on threshold Hysteresis Data Sheet 23 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface 9 SPI Interface The serial SPI interface establishes a communication link between TLE8209-2SA and the systems microcontroller. The TLE8209-2SA always operates in slave mode whereas the controller provides the master function. The maximum baud rate is 2 MBaud. By applying an active slave select signal at SS the TLE8209-2SA is selected by the SPI-master. SI is the data input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI-clock is provided by the master. In case of inactive slave select signal (High) the data output SO goes into tristate. The first two bits of an instruction may be used to establish an extended device-addressing. This gives the opportunity to operate up to 4 Slave-devices sharing one common SS signal from the Master-Unit (see Figure 16). SS SCK SPI-Control: -> state machine -> clock counter -> instruction recognition shift-register 8 SI SO DIA_REG Reset 8 Diagnostics DIS OR ABE Figure 14 SPI Block Diagram 9.1 General SPI Characteristics 1. During active reset conditions the SPI is driven into its default state. The output SO is set to high impedance (tristate). When reset becomes inactive, the state machine enters into a wait state for the next instruction. 2. If the slave select signal at SS is inactive (high), the state machine is forced to wait for the following instruction. 3. During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used to latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the data according to the instruction (i.e. modification of internal registers) will be triggered by the rising edge of the SS signal. 4. In order to establish the option of extended addressing the upper two bits of the instruction byte (i.e. the first two SI bits of a frame) are reserved to send a chip address. To avoid a bus conflict the output SO will remain tristate during the addressing phase of a frame (i.e. until the address bits are recognized as a valid chip Data Sheet 24 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface address). If the chip address does not match, the according frame will be ignored and SO remains tristate for the complete frame. 5. Verification byte: Simultaneously to the receipt of an SPI instruction the TLE8209-2SA transmits a verification byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial bit pattern and a flag indicating an invalid instruction of the previous access. 6. On a read access the data bits at the SPI input SI are rejected. During a valid write access the SPI will transmit the data byte "00hex" at the output SO after having sent the verification byte. 7. An instruction is invalid if one of the following conditions is fulfilled: - an unused instruction code is detected (see tables with SPI instructions). - the previous transmission is not completed in terms of internal data processing. - the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses. If an unused instruction code occurres, the data byte “FFhex” (no error) will be transmitted after having sent the verification byte. This transmission takes place within the same SPI-frame that contained the unused instruction byte. If an invalid instruction is detected, bit TRANS_F in the following verification byte (next SPI-transmission) is set to HIGH. The TRANS_F bit must not be cleared before it has been sent to the microcontroller. 9.2 SPI Communication The 16 input bits consist of the SPI instruction byte and an input data byte. The 16 output bits consist of the verification byte and the output data byte (see also Figure 15). The definition of these bytes is given in the subsequent sections. The access mode of the registers is described in the column “Type” (r = read, w = write). SS SCK SI SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB SPI Instruction Verification byte LSB LSB MSB input data-byte output data-byte LSB Figure 15 SPI Communication 9.2.1 Instruction Byte The upper 2 bit of the instruction byte contain the chip address. The chip address of the TLE8209-2SA is ’00’. During read access, the output data according to the register requested in the instruction byte are applied to SO within the same SPI frame. That means, the output data corresponding to an instruction byte sent during one SPI frame are transmitted to SO during the same SPI-frame Data Sheet 25 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface Table 5 7 CPAD1 SPI Instruction Format 6 CPAD0 5 INSTR5 4 INSTR4 3 INSTR3 2 INSTR2 1 INSTR1 0 INSTR0 Field CPAD1:0 INSTR5:0 Bits 7:6 5:0 Type w w Description Chip Address (00B) SPI Instruction (encoding) SO remains tristated after SS active Address sent by master is "00 B " Correct addres is recognized, data transmitted to SO SS SCK 7 7 Z 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 0 0 0 7 6 5 4 3 2 1 0 SI SO 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 SO remains tristated after SS active Address sent by master is different from "00 B" Correct addres is not recognized, SO remains tristated and SI data are ignored SS SCK 7 7 6 5 5 4 4 3 3 2 1 1 0 0 7 6 6 5 5 4 3 3 2 2 1 1 0 0 SI SO 6 2 7 4 Z Figure 16 Bus Arbitration by Chip Address Data Sheet 26 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface Table 6 Command RD_ID RD_REV RD_DIA SPI Instruction Set SPI Instruction Byte 0000 0000 0000 0011 0000 1001 0011 0000 0011 1100 0010 1000 0001 1000 00xx xxxx xxxx xxxx Description Read identifier Read version Read diagnostics register Read power stage configuration Read VDD monitoring status Write power stage configuration Write VDD monitoring status Unused - TRANS_F is set to high, ff_hex is sent as data bit. Invalid address - SO remains tristate during entire SPI-frame. RD_CONFIG RD_STATCON WR_CONFIG WR_STATCON all other instructions all other chip addr. 9.2.2 Table 7 7 VER6 Verification Byte Verification Byte Format 6 VER5 5 VER4 4 VER3 3 VER2 2 VER1 1 VER0 0 TRANS_F Field VER6 VER5 VER4 VER3 VER2 VER1 VER0 TRANS_F Bits 7 6 5 4 3 2 1 0 Type r r r r r r r r Description Fixed to tristate (Z) Fixed to tristate (Z) Fixed to high (1) Fixed to low (0) Fixed to high (1) Fixed to low (0) Fixed to high (1) Transfer failure: 1B Error detected during previous transfer 0B Previous transfer was recognized as valid 9.2.3 Device Identifier and Revision The IC’s identifier (device ID) and revision number are used for production test purposes and features plug & play functionality depending on the systems software release. The two numbers are read-only accessible via the SPIinstructions RD_ID and RD_REV as described in Section 9.2.1. The device ID is defined to allow identification of different IC-types by software and is fixed for the TLE8209-2SA. The revision number may be utilized to distinguish different states of hardware and is updated with each redesign of the TLE8209-2SA. It is divided into an upper 4 bit field reserved to define revisions (SWR) corresponding to specific software releases and a lower 4 bit field utilized to identify the actual mask set revision (MSR). Both (SWR and MSR) will start with 0000B and are increased by 1 every time an according modification of the hardware is introduced. Data Sheet 27 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface ID_REG Device Identifier 7 ID7 6 ID6 5 ID5 4 ID4 3 ID3 2 ID2 1 ID1 0 ID0 Field ID7:0 Bits 7:0 Type r Description Device-ID TLE8209-2SA: DE hex REV_REG Device Revision 7 SWR3 6 SWR2 5 SWR1 4 SWR0 3 MSR3 2 MSR2 1 MSR1 0 MSR0 Field SWR3:0 MSR3:0 Bits 7:4 3:0 Type r r Description Revision corresponding to software release Revision corresponding to mask set 9.2.4 Diagnostics Register Reset Value: x111 1111B 5 CurrRed 4 CurrLim 3 DIA21 2 DIA20 1 DIA11 0 DIA10 DIA_REG Diagnostics Register 7 ABE/DIS 6 OT Field ABE/DIS OT CurrRed CurrLim DIA21 DIA20 DIA11 DIA10 Bits 7 6 5 4 3 2 1 0 Type r r r r r r r r Description Is set to “0” in case of ABE = L or DIS = H Is set to “0” in case of over temperature Is set to “0” in case of temperature dependent current limitation Is set to “0” in case of current limitation Diagnosis-Bit2 of OUT2 Diagnosis-Bit1 of OUT2 Diagnosis-Bit2 of OUT1 Diagnosis-Bit1 of OUT1 Data Sheet 28 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface Table 8 ABE/DIS X 1 1 1 1 1 1 1 1 X 0 0 0 Note: Failure Encoding DIA21 DIA20 DIA11 1 X X X 0 1 1 0 1 0 1 1 1 1 X X X 1 0 1 1 0 0 1 1 1 1 0 1 1 X X X 1 0 0 0 X 0 DIA10 Description 1 1 0 1 X X X 0 1 0 0 0 X no failure short circuit to battery at OUT1 (SCB1) short circuit to ground at OUT1 (SCG1) no error detected at OUT1 short circuit to battery at OUT2 (SCB2) short circuit to ground at OUT2 (SCG2) no error detected at OUT2 short circuit accross load (HS1+LS2 active) short circuit accross load (HS2+LS1 active) Undervoltage at pin VS open load (H-Bridge) open load at OUT1 (single switch operation) open load at OUT2 (single switch operation) latched latched not latched latched latched latched latched latched latched latched Comment The bit ABE/DIS shows directly the status of inputs ABE and DIS. It is set to ‘0’ if the power stages are disabled by ABE or DIS. The bits OT, CurrRed and CurrLim are latched. They will be reset with each read access. If the failure condition is still present the according bits are set again. Undervoltage at VS is reported and the outputs are switched off as long as the undervoltage condition is present. The previous setting of the DIAx bits is masked but not reset. Once the supply voltage is back in the operating range the diagnostic bits DIAxx will return to their setting before VS undervoltage. The outputs will return to normal operation. Detection of short circuit will switch of the output stages. In single half bridge operation only the affected output is switched off. In H-Bridge mode both outputs are shut down. The outputs remain off until the failure condition is removed and the diagnosis register is reset. A short across the load may also be reported as SCG at one output and SCB at the other. The diagnostic information DIAxx in the SPI interface is reset in the following cases: • • • • Read out of DIA_REG: only bit 4, 5 and 6 will be reset Enabling or disabling of the bridge via ABE or DIS Undervoltage at VDD Reset command via SPI Data Sheet 29 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface 9.2.5 Configuration Register Reset Value: 1111 1010B 5 SIN1 4 SIN2 3 CL1 2 CL2 1 RESET 0 SL CONFIG_REG Configuration Register 7 MODE 6 MUX Field MODE MUX SIN1 SIN2 CL1 CL2 RESET SL Bits 7 6 5 4 3 2 1 0 Type wr wr wr wr wr wr wr wr Description ’1’: H-bridge mode ’0’: single output stages (for current levels 1 to 3 only) ’1’: control by parallel inputs IN1 and IN2 ’0’: control by SPI bits SIN1 and SIN2 control of OUT1 if MUX=’0’ control of OUT2 if MUX=’0’ current limitation level (see table below) current limitation level (see table below) ’0’: reset of digital logic slew rate setting ’1’: slow ’0’: fast Table 9 CL1 0 0 1 1 Current Limitation Levels CL2 0 1 0 1 Current Level 1 2 3 (default) 4 Typical Current 1.5A 4.0A 6.6A 8.6A 9.2.6 STATCON Register Reset Value: 1101 1xxxB 5 CONFIG0 4 DIACLR2 3 DIACLR1 2 STATUS2 1 STATUS1 0 STATUS0 STATCON_REG STATCON Register 7 CONFIG2 6 CONFIG1 Field CONFIG2 Bits 7 Type wr Description VDD threshold test mode ’1’: VDD monitoring in normal operation ’0’: VDD thresholds are changed according to CONFIG1 Data Sheet 30 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface Field CONFIG1 Bits 6 Type wr Description changes thresholds in VDD threshold test mode (CONFIG2=’0’) ’1’: increase lower threshold of VDD monitoring to test switch off path ’0’: decrease upper threshold of VDD monitoring to test switch off path latch function for overvoltage at VDD ’1’: overvoltage at VDD latched ’0’: overvoltage at VDD not latched ’0’: clears diagnosis of OUT2 always returns ’1’ at read access ’0’: clears diagnosis of OUT1 always returns ’1’ at read access returns level at ABE ’0’: under voltage at VDD ’1’: VDD voltage above lower limit 0’: over voltage at VDD ’1’: VDD voltage below upper limit CONFIG0 5 wr DIACLR2 DIACLR1 STATUS2 STATUS1 STATUS0 4 3 2 1 0 wr wr r r r Data Sheet 31 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface 9.2.7 Contents of the SPI registers after a reset condition Note: The registers for device identifier and revision (ID_REG and REV_REG) are not affected by reset. DIA_REG 7 ABEDIS POR SPIR ABEDISR RDR DIACLR1 DIACLR2 CONFIG_REG 7 MODE POR SPIR DISR SFMODE STATCON_REG 7 POR SPIR SFMODE 1 1 1 6 1 1 1 5 0 0 0 4 1 1 1 3 1 1 1 2 x x x 1 x x x 0 x x x CONFIG2 CONFIG1 CONFIG0 DIACLR2 DIACLR1 STATUS2 STATUS1 STATUS0 1 1 x 1 6 MUX 1 1 1 1 5 SIN1 1 1 1 1 4 SIN2 1 1 1 1 3 CL1 1 1 x 1 2 CL2 0 0 x 0 1 RESET 1 1 1 1 0 SL 0 0 x 0 x x x x x x 6 OT 1 1 1 1 x x 5 CurrRed 1 1 1 1 x x 4 CurLim 1 1 1 1 x x 3 DIA21 1 1 1 x x 1 2 DIA20 1 1 1 x x 1 1 DIA11 1 1 1 x 1 x 0 DIA10 1 1 1 x 1 x POR: Reset due to VDD power up SPIR: Reset via SPI by writing 0 into the RESET of CONFIG_REG ABEDISR: Reset due to enabling or disabling the power stages via DIS or ABE (edge triggered) DISR: Reset due to a disabled power stage by DIS or ABE (level triggered) RDR: Reset due to a read access to DIA_REG DIACLR1: Reset via SPI by writing 0 into the DIACLR1 of STATCON_REG DIACLR2: Reset via SPI by writing 0 into the DIACLR2 of STATCON_REG SFMODE: Reset by setting the TLE8209-2SA into the Status Flag Mode (VDDIO = 0V) x: No change Note: If a reset condition is not listed for a particular register it has no effect on the contents of this register. Data Sheet 32 Rev. 1.0, 2010-02-16 TLE8209-2SA SPI Interface 9.3 Electrical Characteristics SPI Electrical Characteristics: SPI Interface VS = 5 V to 28 V; VDD = 5.0 V; VDDIO = 2.9 V to 5.5 V, Tj = -40 °C to 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. SPI-Timing (see Figure 17)1) 9.3.1 9.3.2 9.3.3 9.3.4 Cycle-time (1) Enable Lead Time (2) Enable Lag Time (3) Data Valid (4) H->L: VSCK=2V -> VSO=0.2 VDDIO L->H: VSCK=2V -> VSO=0.8 VDDIO if VDDIO < 4.5V: L->H: VSCK=2V -> VSO=0.7 VDDIO Data Setup Time (5) Data Hold Time (6) Disable Time (7) Transfer Delay (8) Disable Lead Time (9) Disable Lag Time (10) Access time (11) Typ. Max. – – – – – – – – 150 230 ns ns ns ns referred to master referred to master referred to master Unit Test Conditions tcyc tlead tlag tv 490 50 150 – – CL = 200 pF CL = 350 pF referred to TLE8209-2 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 tsu th tdis tdt tdld tdlg tacc 40 40 – 250 250 250 8.35 – – – – – – – – – 100 – – – – ns ns ns ns ns ns µs referred to master referred to master referred to TLE8209-2 referred to master referred to master referred to master referred to master 1) All timing parameters specified by design - not subject to production test 11 SS 3 9 2 1 10 8 SCK 4 7 SO 5 6 tristate Bit (n-3) Bit (n-4)…1 Bit 0; LSB SI MSB IN Bit (n-2) Bit (n-3) Bit (n-4)…1 LSB IN n=16 Figure 17 Data Sheet SPI Timing 33 Rev. 1.0, 2010-02-16 TLE8209-2SA Application Information 10 Application Information Note: The following simplified application examples are given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. The function of the described circuits must be verified in the real application Vbat Vs < 40V 100 uF 100nF VS 10 nF CP TLE8209-2SA 5V ECU supply 8.2k Enable input (s) ABE V DD open -drain output (s) IN1 IN2 DIS µC SO SI SCK SS/ SF OUT1 M OUT2