TLE8261-2E

D a t a S h e e t , R e v. 1 . 0 , M ay 2 00 9 TLE8261-2E U ni v e r s a l S y s t e m B as i s C h i p H ER M ES R ev . 1 . 0 A u to m o t i v e P o w e r TLE8261-2E Table of Contents Table of Contents 1 2 3 3.1 3.2 4 4.1 4.2 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 9.3 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 HERMES Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 State Machine Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Regulator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Regulator Modes with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Voltage Regulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Voltage Regulator State by SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-speed CAN Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Cell Mode with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPLIT Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Modes with SBC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 16 16 17 18 19 21 21 21 21 22 23 24 24 24 24 25 27 29 29 29 32 33 34 36 40 40 40 42 43 43 44 48 49 49 53 53 53 Data Sheet Rev. 1.0, 2009-05-26 TLE8261-2E Table of Contents 11.5 12 12.1 12.2 12.3 12.4 12.5 12.6 13 13.1 13.2 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 15 15.1 15.2 15.3 16 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Limp Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp Home output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activation of the Limp Home Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of the Limp Home Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vcc1µC undervoltage time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 55 55 57 57 57 59 Configuration Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Configuration select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Config Hardware Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Corrupted data in the SPI data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Input Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZthJA Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hints for SBC Factory Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 61 62 63 63 71 73 75 78 79 80 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Data Sheet 3 Rev. 1.0, 2009-05-26 Universal System Basis Chip HERMES Rev. 1.0 TLE8261-2E 1 • • • • • • • • • • • • • • • • • HERMES Overview Eight products for complete scalable application coverage Complete compatibility (hardware and software) across the family TLE8264-2E (3LIN), TLE8263-2E (2LIN) - 3 Limp Home outputs TLE8264E (3LIN), TLE8263E (2LIN) - 1 Limp Home output TLE8262-2E (1LIN), TLE8261-2E (no LIN) - 3 Limp Home outputs TLE8262E (1LIN), TLE8261E (no LIN) - 1 Limp Home output Very low quiescent current in Stop and Sleep Modes Reset input, output Power on and scalable undervoltage reset generator Standard 16-bit SPI interface Overtemperature and short circuit protection Short circuit proof to GND and battery One universal wake-up input Wide input voltage and temperature range Cyclic wake in Stop Mode Green Product (RoHS compliant) AEC Qualified Scalable System Basis Chip Family Basic Features PG-DSO-36-38 Description The devices of the SBC family are monolithic integrated circuits in an enhanced power package with identical software functionality and hardware features except for the number of LIN cells. The devices are designed for CAN-LIN automotive applications e.g. body controller, gateway applications. To support these applications, the System Basis Chip (SBC) provides the main functions, such as HS-CAN transceiver for data transmission, low dropout voltage regulators (LDO) for an external 5 V supply, and a 16-bit Serial Peripheral Interface (SPI) to control and monitor the device. Also implemented are a Time-out or a Window Watchdog circuit with a reset feature, Limp Home circuitry output, and an undervoltage reset feature. The devices offer low power modes in order to support application that are connected permanent to the battery. A wake-up from the low power mode is possible via a message on the buses or via the bi-level sensitive monitoring/wake-up input as well as from the SPI command. Each wake-up source can be inhibited. The device is designed to withstand the severe conditions of automotive applications. Type TLE8261-2E Package PG-DSO-36-38 Marking TLE8261-2E Data Sheet 4 Rev. 1.0, 2009-05-26 TLE8261-2E HERMES Overview HS CAN Transceiver • • • • • • • • • • • • • • • • • • • • • • • • • • • Compliant to ISO 11898-2 and 11898-5 as well as SAE J2284 CAN data transmission rate up to 1 MBaud Supplied by dedicated input VccHSCAN Low power mode management Bus wake-up capability via CAN message Excellent EMC performance (very high immunity and very low emission) Bus pins are short circuit proof to ground and battery voltage 8 kV ESD gun test on CANH / CANL / SPLIT Bus failure detection Low-dropout voltage regulator Vcc1µC, 200 mA, 5 V ±2% for external devices, such as microcontroller and RF receiver Vcc2, 200 mA, 5 V ±2% for external devices or the internal HS CAN cell Vcc3, current limitation by shunt resistor (up to 400 mA with 220 mΩ shunt resistor), 5 V ±4% with external PNP transistor; for example: to supply additional external CAN transceivers Vcc1µC, undervoltage Time-out Reset output with integrated pull-up resistor Time-out or Window Watchdog, SPI configured Watchdog Timer from 16 ms to 1024 ms Check sum bit for Watchdog configuration Reset due to Watchdog failure can be inhibited with Test pin (SBC SW Development Mode) Complete enabling / disabling of interrupt sources Timing filter mechanism to avoid multiple / infinite Interrupt signals Open drain Limp Home outputs Dedicated internal logic supply Maximum safety architecture for Safety Operation Mode Configurable Fail-Safe behavior Dedicated side indicators signal 1.25Hz 50% duty cycle Dedicated PWM signal 100Hz 20% duty cycle Voltage Regulators Supervision Interrupt Management Limp Home Data Sheet 5 Rev. 1.0, 2009-05-26 TLE8261-2E Block Diagram 2 Block Diagram The simplified block diagram illustrates only the basic elements of the SBC devices. Please refer to the information for each device in the product family for more specific hardware configurations. VCC3S HUNT VCC3B AS E V CC3ref VCC1µC VS VS VS VS Vcc1µC Vcc2 V CC2 GND Vcc3 Vint. Vint. SDI SDO CLK CSN SPI SBC STATE MACHINE Limp Home LH_PL/ test Limp home LHO_SI INT Interrupt Control RESET GENERATOR WK RO WK Vs VCCHSCAN TxD CAN RxD CAN CAN_H SPLIT CAN_L WAKE REGISTER CAN cell GND Block diagram_TLE8261-2E.vsd Figure 1 Simplified Block Diagram Data Sheet 6 Rev. 1.0, 2009-05-26 TLE8261-2E Pin Configuration 3 3.1 Pin Configuration Pin Assignments RO CSN CLK SDI SDO GND n.c. Vs Vs n.c. Vcc3shunt Vcc3base GND Vcc3REF INT Vcc1µC Vcc2 VccHSCAN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 LH_PL/Test Limp home WK LH_SI n.c. GND n.c. n.c. n.c. n.c. n.c. n.c. RxDCAN TxDCAN GND CANL SPLIT CANH TLE8261-2E DSO 36 - Exposed Pad 34 33 32 31 30 29 Exposed Die Pad 28 27 26 25 24 23 22 21 20 19 Pinout_8261_2E.vsd Figure 2 Pin Configuration Data Sheet 7 Rev. 1.0, 2009-05-26 TLE8261-2E Pin Configuration 3.2 Pin 1 2 Pin Definitions and Functions Symbol RO CSN Function Reset Input/Output; open drain output, integrated pull-up resistor; active low. SPI Chip Select Not Input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should be set to low only when CLK is low; CSN has an internal pull-up resistor and requires CMOS logic level inputs. SPI Clock Input; clock input for shift register; CLK has an internal pull-down resistor and requires CMOS logic level inputs. SPI Data Input; receives serial data from the control device; serial data transmitted to SDI is a 16-bit control word with the Least Significant Bit (LSB) transferred first: the input has a pull-down resistor and requires CMOS logic level inputs; SDI will accept data on the falling edge of the CLK signal. SPI Data Output; this tri-state output transfers diagnostic data to the control device; the output will remain tri-stated unless the device is selected by a low on Chip Select Not (CSN). Ground Not connected Power Supply Input; block to GND directly at the IC with ceramic capacitor. Ensure to have no current flow from PIN8 to PIN9. PIN8 and PIN9 can be directly connected. Power Supply Input; block to GND directly at the IC with ceramic capacitor. Ensure to have no current flow from PIN8 to PIN9. PIN8 and PIN9 can be directly connected. Not connected PNP Shunt; External PNP emitter voltage. PNP Base; External PNP base voltage. Ground External PNP Output Voltage Interrupt Output, configuration Input; used as wake-up flag from SBC Stop Mode and indicating failures. Active low. Integrated pull up. During start-up used to set the SBC configuration. External Pull-up sets config 1/3, no external Pull-up sets config 2/4. Voltage Regulator Output; 5 V supply; to stabilize block to GND with an external capacitor. Voltage Regulator Output; 5 V supply; to stabilize block to GND with an external capacitor. Supply Input; for the internal HS CAN cell. CAN High Line; High in dominant state. Termination Output; to support recessive voltage level of the bus lines. CAN Low Line; Low in dominant state. Ground CAN Transmit Data Input; integrated pull-up resistor. CAN Receive Data Output Not connected Not connected 3 4 CLK SDI 5 SDO 6 7 8 9 10 11 12 13 14 15 GND n.c. Vs Vs n.c. Vcc3 shunt Vcc3 base GND Vcc3REF INT 16 17 18 19 20 21 22 23 24 25 26 Vcc1 µc Vcc2 VccHSCAN CANH SPLIT CANL GND TxDCAN RxDCAN n.c. n.c. Data Sheet 8 Rev. 1.0, 2009-05-26 TLE8261-2E Pin Configuration Pin 27 28 29 30 31 32 33 34 35 36 Symbol n.c. n.c. n.c. n.c. GND n.c. Function Not connected Not connected Not connected Not connected Ground Not connected Limp Home side indicator; Side indicators 1.25Hz 50% duty cycle output; Open drain. Active LOW. Monitoring / Wake-Up Input; bi-level sensitive input used to monitor signals coming from, for example, an external switch panel; also used as wake-up input; Fail-Safe Function Output; Open drain. Active LOW. SBC SW Development Mode entry; Connect to GND for activation; Integrated pullup resistor. Connect to VS or leave open for normal operation. Limp Home Pulsed Light output: Brake/rear light 100Hz 20% duty cycle output; Open drain. Active LOW. Exposed Die Pad; For cooling purposes only, do not use it as an electrical ground.1) LH_SI WK Limp Home LH_PL/Test EDP - 1) The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the PCB. The exposed die pad is not connected to any active part of the IC and can be left floating or it can be connected to GND for the best EMC performance. Data Sheet 9 Rev. 1.0, 2009-05-26 TLE8261-2E State Machine 4 4.1 State Machine Block Description First battery connection (POR) AND config0 not active Condition / event SBC Init mode ( 256ms max after reset relaxation) SBC action Vcc1 on SPI cmd Vcc2/3 off CAN inact SPI cmd WD conf SPI cmd L.H. inact SBC SW Flash mode WD trig reset (initiated by SBC ) SBC Normal mode Vcc1 on L.H. act/inact Vcc1 on L.H. act/inact Vcc2/3 on/off CAN Tx/Rx WD fixed Vcc2/3 on/off CAN conf WD conf WD trig SPI cmd OR WD failed NOT reset clamped (high or low) OR NOT undervoltage at Vcc1 WK event stored LH entry condition stored OR Restart entry condition stored SPI cmd SPI cmd SPI cmd SBC Sleep mode Vcc1 off L .H. act/inact SBC Stop mode Vcc1 on L.H. act/inact Detection of falling edge at reset pin (any mode) OR undervoltage reset at VCC1µC (any mode) Vcc2/3 off CAN Wakable/ off Wake up event WD off SPI cmd Vcc2/3 on/off CAN wakable/ off WD fixed/off WD trig SBC Restart mode 1st (config1) or 2nd (config3) WD trig failure in Normal / Stop / SW Flash mode Config 1/3: Reset clamped LOW (any mode) Vcc1 on L.H. act/inact Vcc2/3 on/off CAN waked or off Reset act. Init mode not successful Config 1/3: Reset clamped HIGH during restart / init First battery connection (POR) AND config 0 SBC SW Development mode Vcc1 Vcc2/3 WD mode set mode set mode set L.H. CAN mode set mode set CAN, WK Wake-up OR Release of over temperature at Vcc1 (Wake-up event stored) (LH entry condition stored) SBC Fail-Safe mode 1st (config2) or 2nd (config4) WD trig failure in Normal / Stop / SW Flash mode Config 2/4: Reset clamped LOW (any mode) SBC Factory Flash mode Config 2/4: Reset clamped HIGH during Restart or Init mode Vcc1 off L.H. act Vcc2/3 off CAN sleep WD off Vcc1 ext. L.H. inact. Vcc2/3 off CAN off WD off Vcc1 over temperature shutdown OR V S > VUV_ON & Undervoltage time out on VCC1 Power mode managment 8261.vsd Figure 3 Power Mode Management Data Sheet 10 Rev. 1.0, 2009-05-26 TLE8261-2E State Machine 4.2 State Machine Description The System Basis Chip (SBC) offers ten operating modes: Power On Reset, Init, Normal, Restart, Software Flash, Sleep, Stop, Fail-Safe, Software Development, and Factory Flash Mode. The modes are controlled with one test pin and via three mode select bits MS2..0, within the SPI. Additionally, the SBC allows five configurations, accessed via two external pins and one SPI bit. 4.2.1 Table 1 Configuration Description SBC Configuration Description Software Development Mode Test pin 0V INT Pin n.a WD to LH bit n.a Table 1 provides descriptions and conditions for entry to the different configurations of the SBC. Configuration config 0 config 1 config 2 config 3 After missing the WD trigger for the first time, the state of Vcc1µC Open / VS External 0 remain unchanged, LH pin is active, SBC in Restart Mode pull-up After missing the WD trigger for the first time, Vcc1µC turns OFF, LH pin is active, SBC in Fail-Safe Mode After missing the WD trigger for the second time, the state of Vcc1µC remain unchanged, LH pin is active, SBC in Restart Mode After missing the WD trigger for the second time, Vcc1µC turns OFF, LH pin is active, SBC in Fail-Safe Mode No ext. pull-up 0 External 1 pull-up No ext. pull-up 1 config 4 In SBC SW Development Mode, Config 1 to 4 are accessible. 4.2.2 SBC Power ON Reset (POR) At VS > VUVON, the SBC starts to operate, by reading the test pin and then by turning ON Vcc1µC. When Vcc1µC reaches the reset threshold VRT1, the reset output remains activated for tRD1 and the SBC enters then the Init Mode. In the event that Vs decreases below VUVOFF, the device is completely disabled. For more details on the disable behavior of the SBC blocks, please refer to the chapter specific to each block. 4.2.3 SBC Init Mode At entering the SBC Init Mode, the SBC starts to read the Test pin. The SBC starts-up in SBC Init Mode, and, after powering-up, waits for the microcontroller to finish its startup and initialization sequences. Vcc2/3 are OFF and the Watchdog is configurable but not active. CAN is inactive and Limp Home output is inactive. From this transition mode, the SBC can be switched via SPI command to the desired operating mode, SBC Normal or Software Flash Mode. If the SBC does not receive any SPI command, or receive wrong SPI command (i.e. not send the device to SBC Normal or SBC SW Flash Mode) within a 256 ms time frame after the reset relaxation, it will enter into SBC Restart Mode and activate the Limp Home output. Note: In Init Mode it is recommended to send one SPI command that sets the device to Normal Mode, triggers the watchdog the first time and sets the required watchdog settings. Data Sheet 11 Rev. 1.0, 2009-05-26 TLE8261-2E State Machine 4.2.4 SBC Normal Mode SBC Normal Mode is used to transmit and receive CAN messages. In this mode, Vcc1µC is always “ON” Vcc2 and Vcc3 can be turned-on or off by SPI command. In Normal Mode the watchdog needs to be triggered. It can be configured via SPI, window watchdog and time-out watchdog is possible (default value is time-out 256 ms). All the wake-up sources can be inhibited in this mode. The Limp Home output can be enabled or disabled via SPI command. Via SPI command, the SBC can enter Sleep, Stop or Software Flash Mode. A reset is triggered by the SBC when entering the Software Flash Mode. It is recommended to send at first SPI command the watchdog setting. Please refer to Chapter 12.4. 4.2.5 SBC Sleep Mode During SBC Sleep Mode, the lowest power consumption is achieved by having the main and external voltage regulators switched-off. As the microcontroller is not supplied, the integrated Watchdog is disabled in Sleep Mode. The last Watchdog configuration is not stored. The CAN module is in Wake-capable or OFF modes and the Limp Home output is unchanged, as before entering the Sleep Mode. If a wake-up appears in this mode, the SBC goes into Restart Mode automatically. In Sleep Mode, not all wake-up sources should be inhibited, this is required to not program the device in a mode where it can not wake up. If all wake sources are inhibited when sending the SBC to Sleep Mode, the SBC does not go to Sleep Mode, the microcontroller is informed via the INT output, and the SPI bit “Fail SPI” is set. The first SPI output data when going to SBC Normal Mode will always indicate the wake up source, as well as the SBC Sleep Mode to indicate where the device comes from and why it left the state. Note: Do not change the transceiver settings in the same SPI command that sends the SBC to Sleep Mode. 4.2.6 SBC Stop Mode The Stop Mode is used as low power mode where the µC is supplied. In this mode the voltage regulator Vcc1µC remains active. The other voltage regulator (Vcc2/3) can be switched on or off. The watchdog can be used or switched off. If the watchdog is used the settings made in Normal Mode are also valid in Stop Mode and can not be changed. The CAN is not active. It can be selected to be off or used as wake-up source. If all wake up sources are disabled, (CAN, WK, cyclic wake) the watchdog can not be disabled, the SBC stays in Normal Mode and the watchdog continues with the old settings. If a wake-up event occurs the INT pin is set to low. The µC can react on the interrupt and set the device into Normal Mode via SPI. There is no automatic transition to SBC Normal Mode. There are 4 Options for SBC Stop Mode • • • • WD on (the watchdog needs to be served as in Normal Mode WD off (special sequence required see Chapter 10.2.4) Cyclic Wake up with acknowledge (interrupt is sent after set time and needs to be acknowledged by SPI read) Cyclic Wake-up, Watchdog off (interrupt is sent after set time) Cyclic Wake-Up Feature SBC Stop Mode supports the cyclic wake-up feature. By default, the function is OFF. It is possible to activate the cyclic wake-up via “Cyclic WK on/off” SPI bit. This feature is useful to monitor battery voltage, for example, during parking of the vehicle or for tracking RF data coming via the RF receiver. The Cyclic Wake-up feature sends an interrupt via the pin INT to the µC after the set time. The cyclic wake-up feature shares the same clock as the Watchdog. The time base set in the SPI for the Watchdog will be used for the cyclic wake-up. The timer has to be set before activating the function. With the cyclic wake-up feature the watchdog is not working as known from the other modes. In the case that both functions (Watchdog and cyclic wake-up) are selected, the cyclic wake-up is activated and each interrupt has to be acknowledged by reading the SPI Wake register before the next Cyclic Wake-Up comes. Otherwise, the SBC goes to SBC Restart Mode. Data Sheet 12 Rev. 1.0, 2009-05-26 TLE8261-2E State Machine 4.2.7 SBC Software Flash Mode SBC Software Flash Mode is similar to SBC Normal Mode regarding voltage regulators. In this mode, the Limp Home output can be set to active LOW via SPI and the communication on CAN is activated to receive flash data. The Watchdog configuration is fixed to the settings used before entering the SBC SW Flash Mode. When the device comes from SBC Normal Mode, a reset is generated at the transition. From the SBC Software Flash Mode, the SBC goes into SBC Restart Mode, the config setting has no influence on the behavior. A mode change to SBC Restart Mode can be caused by a SPI command, a time-out or Window Watchdog failure or an undervoltage reset. When leaving the SBC Software Flash Mode a reset is generated. 4.2.8 SBC Restart Mode They are multiple reasons to enter the SBC Restart Mode and multiple SBC behaviors described in Table 2. In any case, the purpose of the SBC Restart Mode is to reset the microcontroller. • • • • • From SBC SW Flash Mode, it is used to start the new downloaded code. From SBC Normal, SBC Stop Mode and SBC SW Flash Mode it is reached in case of undervoltage on Vcc1µC, or due to incorrect Watchdog triggering. From SBC Sleep Mode it is used to ramp up Vcc1µC after wake From SBC Init Mode, it is used to avoid the system to remain undefined. From SBC Fail-safe Mode it is used to ramp up Vcc1µC after wake or cool down of Vcc1µC. From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode. The delay time tRDx is programmable by the “Reset delay” SPI bit. The Reset output (RO) is released at the transition. SBC Restart Mode is left automatically by the SBC without any microcontroller influence. The first SPI output data will provide information about the reason for entering Restart Mode. The reason for entering Restart Mode is stored and kept until the microcontroller reads the corresponding “LH0..2” or “RM0..1” SPI bits. In case of a wake up from Sleep Mode the wake source is seen at the interrupt bits (Configuration select 000), an interrupt is not generated. Entering or leaving the SBC Restart Mode will not result in deactivation of the Limp Home output (if activated). The first SPI output data when going to SBC Normal Mode will always indicate the reason for the SBC Restart event. Data Sheet 13 Rev. 1.0, 2009-05-26 TLE8261-2E State Machine Table 2 Mode SBC Restart Mode Entry Reasons and Actions Actions LH output Init Mode time-out Reset low from outside Reset clamped undervoltage reset ON Unchanged ON unchanged ON WD trigger failure OFF after 1st remains ON LOW ON after 2nd OFF after 1st Reset low from outside Reset clamped undervoltage reset SPI cmd WD trigger failure Reset low from outside Reset clamped Wake-up event undervoltage reset Unchanged ON unchanged unchanged unchanged Unchanged ON unchanged unchanged ON WD trigger failure OFF after 1st remains ON LOW ON after 2nd OFF after 1st Reset low from outside Reset clamped Wake-up event undervoltage reset Reset low from outside Reset clamped Unchanged ON ON unchanged Unchanged ON remains ON LOW remains ON LOW ramping up ramping up LOW LOW remains ON LOW remains ON LOW remains ON LOW remains ON LOW remains ON LOW remains ON LOW remains ON LOW ramping up ramping up LOW LOW Config n.a SBC Mode and Configuration Entering reason Vcc1µC RO SPI Out Bits LH 0..2 RM 0..1 LH 0..2 RM 0..1 LH 0..2 RM 0..1 after 1st LH 0..2 after 2nd RM 0..1 after 1st2) RM 0..1 LH 0..2 RM 0..1 RM 0..1 RM 0..1 RM 0..1 LH 0..2 WK bits register RM 0..1 LH 0..2 RM 0..1 after 1st LH 0..2 after 2nd RM 0..1 after 1st2) RM 0..1 LH 0..2 LH 0..2 RM 0..1 RM 0..1 LH 0..2 remains ON LOW remains ON LOW remains ON LOW ramping up LOW Init Mode n.a. config 1/3 n.a config 1 config 3 Normal1) config 4 n.a. config 1/3 n.a n.a Software Flash n.a n.a. config 1/3 Sleep n.a n.a config 1 config 3 Stop1) config 4 n.a. config 1/3 Fail-Safe Software Development Mode n.a. n.a n.a. config 1/3 remains ON LOW remains ON LOW 1) Config 2 will never enter Restart Mode in case of WD failure but directly Fail-Safe Mode 2) Goes to Fail-Safe Mode after the second consecutive failure Data Sheet 14 Rev. 1.0, 2009-05-26 TLE8261-2E State Machine 4.2.9 SBC Fail-Safe Mode In SBC Fail-Safe Mode, all voltage regulators are OFF and the transceivers are in Wake-Capable Mode. The Limp Home output is active. Conditions to enter the SBC Fail-Safe Mode are: • • • • Watchdog trigger failure in configuration 2 or 4 Vcc1µC undervoltage time-out in any configuration if VS is above VLHUV range. Temperature shutdown of Vcc1µC in any configuration. Reset clamped in Config. 2/4 In case of Vcc1µC overtemperature shutdown, the SBC will latch and wait to cool down below the thermal hysteresis, and will go back to SBC Restart Mode. In case of a wake-up event, the SBC will go to SBC Restart Mode (not in case of Vcc1µC overtemperature shutdown), storing the wake-up event and resetting the Watchdog trigger failure counter. The first SPI output data when going to SBC Normal Mode will always indicate the reason for the SBC Fail-Safe Mode. 4.2.10 SBC Software Development Mode If the Test pin is connected to GND (Config 0 active) during powering-up, the SBC enters SBC Software Development Mode. SBC Software Development Mode is a super set of the other modes so it is possible to use all the modes of the SBC with the following difference. In SBC Software Development Mode, no reset is generated and VCC1µC is not switched off due to Watchdog trigger failure. If a Watchdog trigger failure occurs, it will be indicated by the INT output (reset bit). The SBC Fail-Safe Mode or SBC Restart Mode are not reached in case of wrong Watchdog trigger but the other reasons to enter these modes are still valid. 4.2.11 SBC Factory Flash Mode In this mode, the SBC is completely powered OFF and the microcontroller is supplied externally. The mode is detected when VCC1µC is powered from external and the voltage on Vs is not powered from external. The current flow out of Vs must be limited to the maximum rating. The external supply voltage should be below the absolute maximum rating stated in Chapter 5.1. The reset can be driven by an external circuit, or pulled high with a pull-up resistor. Note: Please respect the absolute maximum ratings when the device is in SBC Factory Flash Mode. Data Sheet 15 Rev. 1.0, 2009-05-26 TLE8261-2E General Product Characteristics 5 5.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Voltages 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Supply Voltage Max. 40 5 5.5 40 40 V V V V – – – CANH-CANL VUV OFF; – -1) -1) Pull up to VS RLHO = 40kΩ 3) 1) In the case Vs < VUVOFF, the SBC is switched OFF and will restart in INIT Mode at next Vs rising. 2) During load dump, the others pins remains in their absolute maximum ratings 3) Not subject to production test, specified by design Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Data Sheet 17 Rev. 1.0, 2009-05-26 TLE8261-2E General Product Characteristics 5.3 Pos. 5.3.1 Thermal Characteristics Parameter Junction Ambient Junction Ambient Symbol Min. Limit Values Typ. 40 25 5 145 25 185 35 1.20 – 10 – 170 – 200 – – 200 – Max. K/W K/W K/W °C K °C K – °C K 1) 3) Unit Test Conditions 300 mm2 cooling area 2) 3) RthJA_1L RthJA_4L RthJSP TjPW ∆TPW – – – 120 – 150 – – 150 – 2s2p + 600 mm2 cooling area 3) 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 Junction to Soldering Point Thermal Prewarning and Shutdown Junction Temperatures; VCC1µC, Thermal Pre-warning ON Temperature -3) 3) VCC1µC, Thermal Prewarning Hysteresis VCC1µC, VCC2 Thermal Shutdown Temperature VCC1µC, VCC2 Thermal Shutdown Hysteresis VCC1µC, Ratio of SD to PW Temperature TjSDVcc ∆TSDVcc 3) 3) TjSDVcc/ TjPW 3) CAN Transmitter Thermal Shutdown Temperature CAN Transmitter Thermal Shutdown Hysteresis TjSDCAN ∆TCAN 3) 3) 1) Specified Rthja value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 single layer. The product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board. 2) According to Jedec JESD51-2,-5,-7 at natural convection on 2s2p board for 2W. Board: 76.2x114.3x1.5mm³ with 2 inner copper layers (35µm thick)., with thermal via array under the exposed pad contacted the first inner copper layer and 600mm2 cooling are on the top layer (70µm) 3) Not subject to production test; specified by design; Data Sheet 18 Rev. 1.0, 2009-05-26 TLE8261-2E General Product Characteristics 5.4 Current Consumption VS = 5.5 V to 28 V; all outputs open; Without VCC3; Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Min. Normal Mode; 5.4.1 Current Consumption for Internal Logic Limit Values Typ. – Max. 2 mA SBC Normal Mode ICC1µC = ICC2 = 0mA; CAN OFF mode; CAN Normal Mode; Recessive state; VCC2 connected to VCCHSCAN VTxD = Vcc1µC; without RL CAN Normal Mode; dominant state; VCC2 connected to VCCHSCAN VTxD = low; without RL; SBC Stop Mode; Vs = 13.5 V; VCC1µC“ON”; VCC2/3“OFF” CAN wake capable; Tj = 25°C Unit Test Condition IVS_logic – 5.4.2 IVS_CAN Additional current Consumption for CAN Cell – – 10 mA – – 12 mA Stop Mode 5.4.3 Current Consumption IVS – 58 75 µA 65 – 70 85 90 µA Tj = 85°C1) SBC Stop Mode; Vs = 13.5 V; VCC1µC/2“ON”; VCC3“OFF” CAN wake capable; Tj = 25°C – 78 100 Tj = 85°C1) Data Sheet 19 Rev. 1.0, 2009-05-26 TLE8261-2E General Product Characteristics 5.4 Current Consumption (cont’d) VS = 5.5 V to 28 V; all outputs open; Without VCC3; Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Min. Sleep Mode 5.4.4 Current consumption, all Wake Up Sources available. Limit Values Typ. 28 Max. 40 µA SBC Sleep Mode; Tj = 25°C Vs = 13.5 V; VCC1µC/2/3“OFF” CAN wake capable; Tj = 85°C1) µA 1) Unit Test Condition IVS_sleep_ – SBC 32 5.4.5 Quiescent Current Reduction when Wake Capable CAN Cell Disabled 50 – IVS_sleep_ 5 CAN 12 SBC Sleep Mode; Tj = 25°C; VS = 13.,5 V; VCC1µC/2/3“OFF” CAN OFF 1) Not subject to production test; specified by design Data Sheet 20 Rev. 1.0, 2009-05-26 TLE8261-2E Internal Voltage Regulator 6 6.1 Internal Voltage Regulator Block Description V CC 1µC Vs Vref V CC2 1 Overtemperature Shutdown State Machine Bandgap Reference INH Vref 1 Charge Pump GND INTE RNA L RE GULA TOR DIA GRA M V S D . Figure 4 Functional Block Diagram The internal voltage regulators are dual low-drop voltage regulators that can supply loads up to ICC1µC/2_max. An input voltage up to VSMAX is regulated to Vcc1µC/2_nom = 5.0 V with a precision of ±2%. Due to its integrated reset circuitry, featuring two SPI configurable power-on timing (tRDx) and three SPI configurable output voltages (VRTx) monitoring, the device is well suited for microcontroller supply. The design enables stable operation even with ceramic output capacitors down to 470nF, with ESR < 1 Ω @ f = 10 kHz. The device is designed for automotive applications, therefore it is protected against overload, short circuit, and overtemperature conditions. Figure 4 shows the functional block diagram. If the VS voltage is lower than VUV_OFF, the DMOS of the voltage regulator is switched to high impedance. The body diodes of the DMOS might go into conduction when VCC1µC or VCC2 > VS (no reverse protection). 6.2 Internal Voltage Regulator Modes It is possible to turn Vcc1µC via SBC Modes and Vcc2 activity ON or OFF via SPI command or by entering SBC modes. The limiting current for the both regulators is ICC1µC_max/ICC2. 6.3 Internal Voltage Regulator Modes with SBC Mode Depending on the SBC Mode in use, Vcc1µC and Vcc2 can be either ON or OFF by definition, Vcc2 can be also turned ON or OFF, via SPI. Table 3 identifies the possible states of the voltage regulators, based on the various SBC modes. Data Sheet 21 Rev. 1.0, 2009-05-26 TLE8261-2E Internal Voltage Regulator Table 3 SBC Mode INIT Mode Internal Voltage Regulators States Vcc1µC ON ON OFF ON ON ON OFF OFF ON OFF unchanged ON ON OFF OFF OFF OFF Vcc2 Normal Mode Sleep Mode Restart Mode Software Flash Mode Stop Mode Fail-Safe Mode 6.4 6.4.1 Application information Timing Diagram Figure 5 shows the ramp up and down of the VS, and the dependency of Vcc1µC. At the first ramp up from SBC Init Mode, the reset threshold VRT and time tRO are set to the default value. See Chapter 10.1 Vs VUV ON V UV OFF t Vcc1µC VRTx,r VRTx,f GND t RO SBC OFF SBC Init Any mode SBC OFF t Figure 5 Ramp up / Down of Main Voltage Regulator An undervoltage time-out on Vcc1µC is implemented. Refer to Chapter 12 for more information on this function. 6.4.2 Under voltage detection at Vcc2 The Vcc2 voltage regulator integrates an under voltage detection. When Vcc2 voltage goes below VUV_VCC2, the failure is indicated by an interrupt and the failure is reported into the diagnosis frame of the SPI. Data Sheet 22 Rev. 1.0, 2009-05-26 TLE8261-2E Internal Voltage Regulator 6.5 Electrical Characteristics Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Min. Voltage Regulator; Pin Vcc1 µC 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 Output Voltage Line Regulation Load Regulation Power Supply Ripple Rejection Output Current Limit Typ. 5.0 – – 40 – Max. 5.1 20 50 – 500 V mV mV dB mA 0 mA ICC3max UV Vcc3 UV VCC2 OT VCC2 OT HS CAN OTP Vcc1µC 001 001 Res. Res. Res. Res. Res. Res. CAN Bus CAN CAN failure failure 1 0 010 010 R eserved WD to LH Cyclic L.H. VCC2 WK PIN VCC3 Reset WK On/off On/Off On /off On/off Delay On/off CAN 1 CAN 0 Ti. Out / Win. 011 011 RT1 RT0 100 100 Res. Res. Res. Res. Res. Res. Res. 101 101 R EGISTER CHK WD SUM On/Off Set to 1 Window /Time out Watchdog Timing Bit Position: 10 .. 6 LH 1 LH 0 Test 2 Test 1 Test 0 110 110 Res. RM1 RM0 LH 2 111 111 SPI_Settings_out_TLE8261.vsd 14.5 14.5.1 SPI Data Encoding WD Refresh bit / WK state The WD Refresh bit is used to trigger the Watchdog. The first trigger should be a 1, and then a 0. For more details, please refer to Chapter 10.2. The WK state bit gives the voltage level at the WK pin. A 1 indicates a high level, a 0 a low level. Data Sheet 63 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface 14.5.2 14.5.2.1 SBC Configuration Setting and Read Out Mode selection bits and configuration select Table 12 lists the encoding of the possible SBC mode. Except SBC Restart and Init Mode which are most of time entered automatically, all others SBC mode are accessible on request of the microcontroller. The microcontroller should send the correct mode selection bits to set the SBC in the respective mode. The output indicates the SBC mode where the SBC currently is or was, depending on the situation. Table 12 MS2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Mode Selection Bits Data Input Set the SBC to SBC Restart Mode. (In SW Flash mode only) Set the SBC to Software Flash Mode Set the SBC to SBC Normal Mode Set the SBC to SBC Sleep Mode Set the SBC to SBC Stop Mode Data Output Show the device was in Restart previous SPI data Show the device is SBC Software Flash Mode Show the device is in SBC Normal Mode Show the device was in SBC Sleep Mode Show the device is in SBC Stop Mode 0 1 0 1 0 1 0 1 Not valid (the complete SPI word is ignored) Show the device was in Init previous SPI data MS1 MS0 Set the SBC to SBC Fail-Safe Mode Show the device was in SBC Fail-Safe Mode (In SBC Software Development mode only) Set the SBC to Read Only SPI access. The Reserved configuration register needs to be selected. The SPI information on SDO is provided in the same SPI frame. No write access is done in this mode. Bit 15 (Watchdog) has to be served correctly. Table 13 lists the eight possible configuration selection. Some are related to event or state of the different part of the SBC, others are used to configure the SBC in the application specific set up. Table 13 CS2 0 0 0 0 1 1 1 1 CS1 0 0 1 1 0 0 1 1 Configuration Select Encoder (for Data Input and Output) CS0 0 1 0 1 0 1 0 1 Configuration Register Select Wake Register Interrupt SBC Failure Interrupt Communication Failure Interrupt Reserved SBC Configuration Register Communication Setup Register Watchdog Configuration Register Limp Home / Diagnosis Register Data Sheet 64 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface 14.5.2.2 Interrupt Register Encoder Table 14 lists all interrupts the SBC can generates. The microcontroller should read the correct register to release the INT pin. By default, all interrupt sources are enabled. The microcontroller can decide to inhibit a specific interrupt source. Table 14 CS Interrupt Register encoder 1) Default Value (INPUT) 1 11 Default Value (OUT) Bit Name Data Input Data Output Configuration select 000 (Wake register interrupt) 000 WK CAN WK 1 WK pin WK 0 WK pin 0 00 Interrupt enabled (1) disabled (0) for wake event on CAN Interrupt enabled (1) disabled (0) for wake pin event. 00 No interrupt 10 Interrupt for a LOW to HIGH transition on WK 01 Interrupt for HIGH to LOW transition on WK 11 Interrupt for both HIGH to LOW and LOW to HIGH on WK n.a n.a Wake on CAN (1) Wake on WK pin 00 No wake 10 Interrupt for a LOW to HIGH transition on WK 01 Interrupt for HIGH to LOW transition on WK 11 Interrupt for both HIGH to LOW and LOW to HIGH on WK Cyclic WK (1) Indicates that there is a status bit or uncleared event in configuration select 001 and/or 010. If set read the two register Cyclic WK INT n.a n.a 0 0 Data Sheet 65 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface Table 14 CS Interrupt Register encoder (cont’d)1) Default Value (INPUT) 1 1 1 1 Default Value (OUT) Bit Name Data Input Data Output Configuration select 001 (SBC Failure interrupt) 001 OTP_Vcc1µC OT_HSCAN OT_Vcc2 UV_Vcc3 0 0 0 0 Interrupt enabled (1) disabled Vcc1µC temperature pre warning (0) for temperature pre-warning (1) Interrupt enabled (1) disabled (0) for temperature shutdown Interrupt enabled (1) disabled (0) for temperature shutdown HS CAN temperature shutdown (1) Vcc2 temperature shutdown (1) Interrupt enabled (1) disabled Undervoltage detection on Vcc3 (0) for undervoltage detection (1) or due to back to normal voltage Interrupt enabled (1) disabled (0) for SPI corrupted data. Interrupt enabled (1) disabled (0) for reset information (only in SBC Software Development Mode) Interrupt enabled (1) disabled (0) for incorrect Watchdog setting SPI input corrupted data (1) Reset (1) (only in SBC Software Development Mode) Incorrect WD programming for data output SPI Fail Reset 1 1 0 0 Wrong WD set 1 0 UV Vcc2 1 0 Interrupt enabled (1) disabled Under voltage detected at Vcc2 (0) for undervoltage detection at Vcc2 ICC3 > ICC3max 1 0 Interrupt enable (1) disabled (0) Over current detected at Vcc3 for over current at Vcc3 Interrupt enabled (1) disabled (0) for CAN failure Interrupt enabled (1) disabled (0) for CAN bus failure CAN failure Refer to Table 15 CAN bus failure detected (1) Configuration select 010 (Communication failure interrupt) 010 CAN failure 1 CAN failure 0 CAN Bus n.a 1 1 0 0 0 1) A value of 0 will set the SBC into the opposite state. Data Sheet 66 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface 14.5.2.3 Table 15 0 0 1 1 CAN failure encoder CAN Failure Encoder CAN 0 Failure 0 1 0 1 Fault No failure TxD shorted to GND or bus dominant clamped RxD shorted to Vcc TxD shorted to RxD Table 15 describes the encoding of the possible internal CAN failures. CAN 1 Failure 14.5.2.4 Configuration encoder Table 16 lists the configuration register of the SBC. The microcontroller can change the settings. If no settings are changed the default values are used. The current value can be read on the SPI Data Out. Table 16 Configuration Encoder Default Default Value Value (INPUT) (OUT) 01 1 0 0 0 0 01 1 0 1 0 0 0 State Configuration Bit Name Select Configuration select 100 (SBC Configuration Register) 100 RT10 Reset delay Reset threshold setting. Please refer to Table 17 Long reset window Vcc3 ON /OFF Vcc2 On / Off LH ON / OFF Cyclic WK On / Off WD to LH Vcc3 is activated (1) The wake pin will wake the SBC WK pin ON / OFF 1 Vcc2 is activated (1) Limp Home output state. Activated (1) when entry condition is met. Activation (1) of the cyclic wake 1 1 Watchdog failure to Limp Home active. 0 = only one Watchdog failure brings to Limp Home activated. 1 = two consecutive Watchdog failures bring to Limp Home activated. Data Sheet 67 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface Table 16 Configuration Encoder Default Default Value Value (INPUT) (OUT) 00 00 State Configuration Bit Name Select Configuration select 101 (SBC communication set up register) CAN 1.0 The CAN cell is in: 00 = CAN OFF 01 = CAN is Wake Capable 10 = CAN Receive Only Mode 11 = CAN Normal Mode Time-out Watchdog is activated Bit is reserved and fix set to “1”. Set to 1 in SW. Watchdog is activated Check sum of the bit 13...6 In case the CHK SUM is wrong, the device remains in previous valid state. CHKSUM = Bit13 ⊕ … ⊕ Bit6 Configuration select 110 (SBC Watchdog register) 110 Ti. Out / Win. Set to 1 WD ON / OFF CHK SUM 1 1 1 1 1 1 1 1 Configuration select 111 (Limp Home / Diagnosis register) 111 Reserved for input For output, refer to Table 19, Table 20 and Table 21 14.5.2.5 Reset encoder Table 17 lists the three possible reset thresholds. Please also refer to Chapter 10.3 to get the exact voltage threshold. Table 17 RT1 0 0 1 1 0 1 0 1 Reset Encoder RT0 Threshold Selected Not Valid. Device remains at previous threshold VRT1 (default setting at SBC Init), VRT2 VRT3 14.5.2.6 SBC Watchdog encoder Table 18 list the 32 possible watchdog timer. Table 18 Bit 10...6 00000 00001 00010 ... 01111 Data Sheet Watchdog Encoder Decimal calculation (ms) 0 1 2 ... 15 (n+1) × 16 n = decimal value of setting Timer (ms) 16 32 48 ... 256 (default setting) 68 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface Table 18 Bit 10...6 10000 10001 ... 11110 11111 Watchdog Encoder Decimal calculation (ms) 16 17 ... 30 31 n × 48 - 464 Timer (ms) 304 352 ... 976 1024 14.5.3 SBC Diagnostic encoder The SBC offers diagnostics information. The encoding of the different possible failures are listed in the following table. The description apply only to data output. 14.5.3.1 Reason for restart and reset Reason for reset, without activation of the Limp Home and the way it is encoded are summed up in Table 19. The bits are cleared by reading the register with Read-Only command. When coming from Sleep Mode or Fail Safe Mode the bits are cleared. Table 19 RM1 0 0 1 1 Reason to Enter SBC Restart Mode without Limp HomeLimp Home activation RM0 0 1 0 1 Cause for entering SBC Restart Mode No reset has occurred or Limp Home activated Undervoltage on Vcc1µC First Watchdog failure (config 3 and 4) or no acknowledge of the Cyclic Wake-up SPI command in SBC Software Flash Mode or reset low from outside Data Sheet 69 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface 14.5.3.2 Limp Home failure encoder Table 20 describes the encoding of all possible reason to activate automatically the Limp Home output. Bits are set back to “000” when switching Limp Home off via SPI. Table 20 LH2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Limp Home Failure Diagnosis LH1 LH0 0 1 0 1 0 1 0 1 Failure1) No failure Vcc1µC undervoltage Time-out One Watchdog failure (config 1 and 2) Two consecutive Watchdog failures (config 3 and 4) INIT Mode Time-out Temperature shutdown at Vcc1µC Reset clamped Reserved 14.5.3.3 Test pin and failure to Limp Home configuration read out The SBC allows to read the hardware setting of the configuration that is done via the INT pin, as well as the test pin and the WD to LH bit. Table 21 describes the encoding of these informations. Table 21 Test2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Test pin and SBC Configuration Test1 Test0 0 1 0 1 0 1 0 1 Test Read Out1) Vcc1µC remains ON in SBC Restart Mode after one Watchdog failure (config 1) Vcc1µC is OFF in SBC Fail-Safe Mode after one Watchdog failure (config 2) Vcc1µC remains ON in SBC Restart Mode after two Watchdog failures (config 3) Vcc1µC is OFF in SBC Fail-Safe Mode after two Watchdog failures (config 4) Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no reset is generated and Restart Mode or Fail-Safe Mode are not entered. Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no reset is generated and Restart Mode or Fail-Safe Mode are not entered. Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no reset is generated and Restart Mode or Fail-Safe Mode are not entered. Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no reset is generated and Restart Mode or Fail-Safe Mode are not entered. 1) Refer also to Chapter 4.2.1 Data Sheet 70 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface 14.6 14.6.1 SPI Output Data First SPI output data Since the SPI output data is sent when the SBC is receiving data, the output data are dependent of the previous SPI command, if no Read Only command is used. Under some conditions there is no “previous command”. Table 22 gives the first SPI output data that is sent to the microcontroller when entering SBC Normal Mode, depending on the mode where the SBC was before receiving the first SPI command. . Table 22 Sleep mode First SPI output data frame Mode selection bits (MS2...0) Configuration select (CS 2..0) Sleep mode Fail-Safe mode Restart mode Restart mode Init mode Wake Register interrupt1) Limp Home register1) Limp Home register1) SBC Configuration Register SBC Configuration Register Previous SBC mode Fail-Safe mode Restart mode when failure and config 1 / 3 Restart mode when microcontroller has sent to Restart mode SBC Init mode 1) This does not clear the bits. It will be reset when the microcontroller requests the read out Data Sheet 71 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface 14.6.2 Read Only command In the Mode Selection Bits a Read Only can be selected. The Read Only access clears the INT bits that are selected in the Configuration Select (some interrupt bits show a state, and can not be cleared with a SPI read). With this SPI command no write access is done to the SBC, and the mode of the SBC is not changed. The watchdog can also be triggered with a Read Only command. The Read Only command delivers the information requested with the Configuration Select in the same SPI command on the SDO pin. As all other SPI commands deliver the requested information with the next SPI command. Figure 34 shows an example of a Read Only access. The bits are shown with LSB first, on the left side in difference to the register description. DI DI 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WD refresh Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WD refresh 1 1 1 0 0 0 x 1 1 0 1 1 1 x DO 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 DO 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WK state Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WK state 1 1 0 0 0 0 x 1 1 0 1 0 0 x TIME Figure 34 Read Only Command Figure 35 shows an example of an SPI write access in normal mode for comparison. The requested information is sent out with the next SPI command. DI DI 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WD refresh Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WD refresh 1 1 0 0 0 0 x 1 1 0 1 1 1 x DO 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 DO 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WK state Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WK state 1 1 0 1 0 0 x 1 1 0 0 0 0 x TIME Figure 35 Write Command Data Sheet 72 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface 14.7 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Min. SPI Interface; Logic Inputs SDI, CLK and CSN 14.7.1 14.7.2 14.7.3 14.7.4 14.7.5 14.7.6 H-input Voltage Threshold VIH L-input Voltage Threshold VIL Hysteresis of input Voltage Pull-up Resistance at pin CSN Pull-down Resistance at pin SDI and CLK Input Capacitance at pin CSN, SDI or CLK H-output Voltage Level L-output Voltage Level – 0.3 x – – 0.12 x 0.7 x V V V 80 80 kΩ kΩ pF – – –1) Limit Values Typ. Max. Unit Test Condition VCC1µC – VCC1µC VCC1µC 20 40 40 10 VIHY RICSN VCSN = 0.7 × VCC1µC VSDI/CLK = 0.2 × VCC1µC -1) RICLK/SDI 20 CI – Logic Output SDO 14.7.7 14.7.8 14.7.9 14.7.10 VSDOH VSDOL VCC1µC - VCC1µC - – 0.4 – -10 – 0.2 0.2 – 10 0.4 10 15 V V µA pF IDOH = -1.6 mA IDOL = 1.6 mA VCSN = VCC1µC; 0 V < VDO < VCC1 1) Tri-state Leakage Current ISDOLK Tri-state Input Capacitance Clock Period Clock High Time Clock Low Time Clock Low before CSN Low CSN Setup Time CLK Setup Time CSDO Data Input Timing1) 14.7.11 14.7.12 14.7.13 14.7.14 14.7.15 14.7.16 14.7.17 14.7.18 14.7.19 tpCLK tCLKH tCLKL tbef tlead tlag 250 125 125 125 250 250 125 100 50 – – – – – – – – – – – – – – – – – – ns ns ns ns ns ns ns ns ns – – – – – – – – – Clock Low after CSN High tbeh SDI Set-up Time SDI Hold Time tDISU tDIHO Data Sheet 73 Rev. 1.0, 2009-05-26 TLE8261-2E Serial Peripheral Interface 14.7 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. 14.7.20 14.7.21 14.7.22 Parameter Input Signal Rise Time at pin SDI, CLK and CSN Input Signal Fall Time at pin SDI, CLK and CSN Delay Time for Mode Change from Normal Mode to Sleep Mode CSN High Time SDO Rise Time SDO Fall Time SDO Enable Time SDO Disable Time SDO Valid Time Symbol Min. Limit Values Typ. – – – Max. 50 50 10 ns ns µs – – – – – – Unit Test Condition trIN tfIN tfIN 14.7.23 14.7.24 14.7.25 14.7.26 14.7.27 14.7.28 tCSN(high) 10 trSDO tfSDO tENSDO tDISSDO tVASDO – – – – – – 30 30 – – – – 80 80 50 50 60 µs ns ns ns ns ns CL = 100 pF CL = 100 pF low impedance high impedance CL = 100 pF Data Output Timing 1) 1) Not subject to production test; specified by design 23 CSN 14 CLK 18 DI not defined 26 DO Flag 28 LSB MSB LSB 19 MSB 27 15 12 13 16 17 Figure 36 SPI Timing Diagram Note: Numbers in drawing correlate to the last 2 digits of the Pos. number in the Electrical Characteristics table. Data Sheet 74 Rev. 1.0, 2009-05-26 TLE8261-2E Application Information 15 Application Information Note: The following information is given only as a hint for the implementation of the device and should not be regarded as a description or warranty of a certain functionality, condition or quality of the device. V DD VBAT VBAT C1 C2 C3 C 12 VS T1 V IO V CC GND IC2 D1 R1 VCC IC3 C13 GND VS VCC3shunt VS VCC3base VCC3ref VDD Vcc1µC C9 R 12 C10 TLE8261-2 CSN CLK SDO SDI TxD LIN 1 RxD LIN 1 CSN VDD CLK SDI µC SDO TxD LIN 1 RxD LIN1 LOGIC State Machine TxD CAN RxD CAN INT S1 WK R9 R5 C7 CAN cell VBAT TxD CAN RxD CAN INT Reset VSS VDD RO VS WK VCC2 R 10 VCCHSCAN C 11 CANH R7 C8 R8 CANL SPLIT CANH Limp Home T2 CANL LH_SI LH_PL/Test T3 DEVICE GROUND VBAT C14 VDD VBB VS VS CS SCLK SI SO LHI IN0 IN1 IN2 IN3 IN4 IN5 IC1 GND D5 GND S2 VS T4 Application _information _TLE8261 -2E.vsd Figure 37 Application Example for a Body Controller Module Data Sheet 75 Rev. 1.0, 2009-05-26 TLE8261-2E Application Information Note: This is a very simplified example of an application circuit and bill of material. The function must be verified in the actual application. Table 23 Ref. C1 C2 C3 C7 C8 C9 C10 C11 C12 C13 C14 R1 R5 R7 R8 R9 R10 R12 Bills of material Option Vendor Y Kemet Y N Y Y Y N N Y Y Y N Y Y Y Y Y Y Murata Value 68µF optional depending on application 100nF 10µF ceramic cap low ESR 22nF 50V 47nF OEM dependent 10µF 100nF 10µF CAN transceiver dependent 100nF 100nF 100nF 220mΩ 1kΩ 60Ω / OEM dependent 60Ω / OEM dependent 10kΩ 500Ω 47kΩ Purpose Cut off battery spike EMC Stability of the VCC3 EMC Improve SPLIT pin stability Buffer of the VCC1µC depending on load. (µC) Stability of the VCC1µC Buffering of the VCC2 for CAN Transceiver Improve stability of the logic Improve stability of the logic Improve stability of the logic Capacitance Resistance VCC3 current measurement for ICC3 400mA max Wetting current of the switch CAN bus termination CAN bus termination Limit the WK pin current in ISO pulses Insulation of the VDD supply Set config 1/3. If not connected config 2/4 is selected Data Sheet 76 Rev. 1.0, 2009-05-26 TLE8261-2E Application Information Table 23 Ref. T1 Bills of material Option Vendor N ON Semi Infineon T2 T3 T4 D1 µC IC1 IC2 IC3 N N N N N Y Y Y Infineon Infineon Infineon Infineon Infineon Infineon Infineon Infineon Value MJD253 BCP52-16 BCR191W BCR191W BCR191W BAS 3010A XC2xxx SPOC - BTS5672E TLE 6254-3G TLE 6251DS Purpose Power element of VCC3 Alternative power element of VCC3, current limit to be adapted R1 to be changed. High active Limp Home High active Limp Home High active Limp Home Reverse polarity protection micro-controller high side switches Low speed CAN High speed CAN Active components Data Sheet 77 Rev. 1.0, 2009-05-26 TLE8261-2E Application Information 15.1 ZthJA Curve 60 Zth-JA(Ch4; 600) Zth-JA(Ch4; 300) Zth-JA(Ch4; 100) 40 Zth-JA [K/W] 50 Zth-JA(Ch4; footprint) 30 20 10 0 0,00001 0,0001 0,001 0,01 0,1 tim e (s) 1 10 100 1000 10000 Zthja curves.vsd Figure 38 ZthJA Curve, Function of Cooling Area 600mm² cooling area 300mm² cooling area 100mm² cooling area minimum footprint PCB set up.vsd Figure 39 Board Set-up Board set-up is done according to JESD 51-3, single layer FR4 PCB 70 µm. Data Sheet 78 Rev. 1.0, 2009-05-26 TLE8261-2E Application Information 15.2 Hints for SBC Factory Flash Mode The mode is used during production of the module to flash the µC. The idea is that the µC is not supplied from the SBC but from an external 5V power supply. The reset of the µC that is connected to the RO pin of the SBC can be driven from an external source and the SBC does not give a reset signal. Also no interrupt at the pin INT and no signal on the SPI SDO pin is generated by the SBC. The SPI pins can be driven externally. The mode is reached by applying 5V to the VCC1µC pin and no voltage to the Vs pin. The Vs pin will show a voltage of about 4.5V because of the internal diode from VCC1µC to Vs. The current drawn at Vs must not exceed the maximum rating of Ivs,max = -500mA. The function is designed for ambient temperature. In case the Vs was supplied before going to FF Mode, the voltage on pin Vs must be set below 3 V before applying 5V to VCC1µC (discharging the C) Not supplied Not supplied 5V Reset signal VBAT C Vs IVS Internal supply VCC1µC The current flowing to other devices from Vs should be limited to not exceed the maximum ratings. Other Devices CSN CLK SDO SDI TxD LIN1 RxD LIN1 TxD LIN2 RxD LIN2 TxD LIN3 RxD LIN3 TxD CAN RxD CAN INT RO CSN V DD CLK SDI µC SDO TxD LIN1 RxD LIN1 TxD LIN2 RxD LIN2 TxD LIN3 RxD LIN3 TxD CAN RxD CAN INT Reset V SS Application_ FF_Mode _2.vsd Figure 40 Application Hint for Factor Flash Mode Data Sheet 79 Rev. 1.0, 2009-05-26 TLE8261-2E Application Information Table 24 Pin Vs Vcc1µC RO INT LH SDO CLK, SDI CSN PIN in Factory Flash Mode Level typ. 4.5V 5V ± 2% Pull-up resistor Pull-up resistor High impedance High impedance Pull-down resistor Pull-up resistor Pull-up resistor High impedance Comment Voltage output from SBC. No voltage applied from external. To be applied from external Can be driven from external Can be driven from external if required Can be driven from external if required Can be driven from external if required Can be driven from external if required Can be driven from external if required Can be driven from external if required Can be driven from external if required TxDCAN, TxDLIN1, TxDLIN2, TxDLIN3 RxDCAN, RxDLIN1, RxDLIN2, RxDLIN3 15.3 ESD Tests Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) have been performed. The results and test condition is available in a test report. The values for the test are listed in Table 25 below. Table 25 ESD “Gun test” Result >8 < -8 Unit Remarks positive pulse1) Performed Test ESD at pin CANH, CANL, BUSx, Vs versus GND ESD at pin CANH, CANL, BUSx, Vs versus GND kV kV negative pulse 1) ESD susceptibility “ESD GUN” contact discharge (R=330Ohm C=150pF) (DIN EN 61000-4-2) tested according LIN EMC 1.3 Test Specification and ICT EMC Evaluation of CAN Transceiver. Tested by external test house (IBEE Zwickau, EMC Test report Nr. 06-02-09a) Data Sheet 80 Rev. 1.0, 2009-05-26 TLE8261-2E Package Outline 16 Package Outline 0...0.10 STAND OFF 2.45 -0.2 2.55 MAX. 0.35 x 45˚ 3) 0.65 C 17 x 0.65 = 11.05 0.33 ±0.08 2) 0.1 C 36x SEATING PLANE 1.1 0.7 ±0.2 10.3 ±0.3 D 0.17 M A-B C D 36x A 19 Bottom View 19 36 36 Ejector Mark Exposed Diepad Ey 1 18 18 B 12.8 -0.21) Index Marking Ex 1 Index Marking Exposed Diepad Dimensions 4) Ex Leadframe Package PG-DSO-36-24, -41, -42 A6901-C001 7 A6901-C003 7 PG-DSO-36-38 A6901-C007 5.2 PG-DSO-36-38 PG-DSO-36-50 A6901-C008 6.0 Ey 5.1 5.1 4.6 5.4 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side 3) Distance from leads bottom (= seating plane) to exposed diepad 4) Excluding the mold flash allowance of 0.3 max per side PG-DSO-36-24, -38, -41, -42, -50-PO V09 Figure 41 PG-DSO-36-38 (Leadframe A6901-003);) Note: For the SBC product family the package PG-DSO-36-38 with the leadframe A6901-C003 is used. Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations, the Universal System Basis Chip is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD020). For information about packages and types of packing, refer to the Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 81 8˚ MAX. 7.6 -0.2 1) 0.23 +0.09 Dimensions in mm Rev. 1.0, 2009-05-26 TLE8261-2E Revision History 17 Version 1.0 Revision History Date 2009-05-25 Parameter Changes First Rev. of Data Sheet Data Sheet 82 Rev. 1.0, 2009-05-26 Edition 2009-05-26 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.