TLE8263-2E

D a t a S h e e t , R e v. 1 . 0 , M ar c h 2 00 9 U ni v e r s a l S y s t e m B as i s C h i p H ER M ES R ev . 1 . 0 A u to m o t i v e P o w e r C on fi de nt ia TLE8263-2E l TLE8263-2E Confidential Table of Contents Table of Contents 1 2 3 3.1 3.2 4 4.1 4.2 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 9.3 10 10.1 10.2 10.3 10.4 10.5 10.6 11 11.1 HERMES Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Voltage Regulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Voltage Regulator State by SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-speed CAN Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Cell Mode with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPLIT Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIN Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIN Cell Mode with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . de Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Regulator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Regulator Modes with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nt General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ia State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 State Machine Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 16 16 17 18 19 21 21 21 21 22 23 24 24 24 24 25 27 29 29 29 32 33 34 36 40 40 40 42 43 43 43 45 46 47 49 Data Sheet C Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2 Rev. 1.0, 2009-03-31 on fi l TLE8263-2E Confidential 11.2 11.3 12 12.1 12.2 12.3 12.4 12.5 13 13.1 13.2 13.3 13.4 13.5 13.6 14 14.1 14.2 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 16 16.1 16.2 16.3 17 18 Table of Contents Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Modes with SBC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp Home output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activation of the Limp Home Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of the Limp Home Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vcc1µC undervoltage time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 60 64 64 64 65 66 66 66 68 68 68 70 Configuration Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Configuration select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Config Hardware Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Corrupted data in the SPI data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Input Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZthJA Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hints for SBC Factory Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . de nt ia l fi 72 72 72 73 74 74 82 84 86 89 90 91 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Data Sheet C on 3 Rev. 1.0, 2009-03-31 Confidential Universal System Basis Chip HERMES Rev. 1.0 TLE8263-2E Scalable System Basis Chip Family • • • • • • • • • • • • • • • • Basic Features Description The devices of the SBC family are monolithic integrated circuits in an enhanced power package with identical software functionality and hardware features except for the number of LIN cells. The devices are designed for CAN-LIN automotive applications e.g. body controller, gateway applications. To support these applications, the System Basis Chip (SBC) provides the main functions, such as HS-CAN transceiver and LIN transceivers for data transmission, low dropout voltage regulators (LDO) for an external 5 V supply, and a 16-bit Serial Peripheral Interface (SPI) to control and monitor the device. Also implemented are a Time-out or a Window Watchdog circuit with a reset feature, Limp Home circuitry output, and an undervoltage reset feature. The devices offer low power modes in order to support application that are connected permanent to the battery. A wake-up from the low power mode is possible via a message on the buses or via the bi-level sensitive monitoring/wake-up input as well as from the SPI command. Each wake-up source can be inhibited. The device is designed to withstand the severe conditions of automotive applications. Type TLE8263-2E C on fi Very low quiescent current in Stop and Sleep Modes Reset input, output Power on and scalable undervoltage reset generator Standard 16-bit SPI interface Overtemperature and short circuit protection Short circuit proof to GND and battery One universal wake-up input Wide input voltage and temperature range Cyclic wake in Stop Mode Green Product (RoHS compliant) AEC Qualified nt 4 Six products for complete scalable application coverage Complete compatibility (hardware and software) across the family TLE8264-2E (3LIN), TLE8263-2E (2LIN) - 3 Limp Home outputs TLE8264E (3LIN), TLE8263E (2LIN) - 1 Limp Home output TLE8262E (1LIN), TLE8261E (no LIN) - 1 Limp Home output ia PG-DSO-36-38 Marking TLE8263-2E Rev. 1.0, 2009-03-31 1 HERMES Overview Data Sheet de Package PG-DSO-36-38 l TLE8263-2E Confidential HERMES Overview HS CAN Transceiver • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Compliant to ISO 11898-2 and 11898-5 as well as SAE J2284 CAN data transmission rate up to 1 MBaud Supplied by dedicated input VccHSCAN Low power mode management Bus wake-up capability via CAN message Excellent EMC performance (very high immunity and very low emission) Bus pins are short circuit proof to ground and battery voltage 8 kV ESD gun test on CANH / CANL / SPLIT Bus failure detection LIN2.1 conformance, LIN2.1 is back compatible to LIN1.3 and LIN2.0 SAE J2602-2 conformance Compatible to ISO 9141 (K-L-Line) Transmission rate up to 20 kBaud, LIN Flash Mode 115kBaud 8 kV ESD gun test on Bus pins Low-dropout voltage regulator Vcc1µC, 200 mA, 5 V ±2% for external devices, such as microcontroller and RF receiver Vcc2, 200 mA, 5 V ±2% for external devices or the internal HS CAN cell Vcc3, current limitation by shunt resistor (up to 400 mA with 220 mΩ shunt resistor), 5 V ±4% with external PNP transistor; for example: to supply additional external CAN transceivers Vcc1µC, undervoltage Time-out Reset output with integrated pull-up resistor Time-out or Window Watchdog, SPI configured Watchdog Timer from 16 ms to 1024 ms Check sum bit for Watchdog configuration Reset due to Watchdog failure can be inhibited with Test pin (SBC SW Development Mode) Complete enabling / disabling of interrupt sources Timing filter mechanism to avoid multiple / infinite Interrupt signals Open drain Limp Home outputs Dedicated internal logic supply Maximum safety architecture for Safety Operation Mode Configurable Fail-Safe behavior Dedicated side indicators signal 1.25Hz 50% duty cycle Dedicated PWM signal 100Hz 20% duty cycle LIN Transceiver Voltage Regulators Supervision Interrupt Management Limp Home Data Sheet 5 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Block Diagram 2 Block Diagram The simplified block diagram illustrates only the basic elements of the SBC devices. Please refer to the information for each device in the product family for more specific hardware configurations. VCC3S HUNT l V cc2 V CC2 GND VCC3B ASE V CC3ref VS VS Vcc1µC ia VCC1µC VS VS Vcc3 Vint. nt Vint. SDI SDO CLK CSN SPI de SBC STATE MACHINE Limp Home LH_PL/test Limp home LHO_SI INT Interrupt Control fi RESET GENERATOR Vs RO WK WK VCCH SCAN TxD CAN RxD CAN CAN_H SPLIT CAN_L on WAKE REGISTER CAN cell TxD1 RxD1 BUS1 LIN1 cell BUS2 TxD2 RxD2 LIN2 cell C GND Block diagram_TLE8263-2E.vsd Figure 1 Simplified Block Diagram Data Sheet 6 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Pin Configuration 3 3.1 Pin Configuration Pin Assignments RO CSN CLK SDI SDO GND n.c. Vs Vs Bus1 Vcc3shunt Vcc3base GND Vcc3REF ia l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 LH_PL/Test Limp home WK LH_SI Bus2 GND n.c. n.c. RxD LIN2 TxDLIN2 RxD LIN TxDLIN RxD CAN TxDCAN GND CANL SPLIT CANH INT Vcc1µC C VccHSCAN Vcc2 on fi de nt Exposed Die Pad 7 TLE8263-2E DSO 36 - Exposed Pad Pinout_8263_2E.vsd Figure 2 Pin Configuration Data Sheet Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Pin Configuration 3.2 Pin 1 2 Pin Definitions and Functions Symbol RO CSN Function Reset Input/Output; open drain output, integrated pull-up resistor; active low. SPI Chip Select Not Input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should be set to low only when CLK is low; CSN has an internal pull-up resistor and requires CMOS logic level inputs. SPI Clock Input; clock input for shift register; CLK has an internal pull-down resistor and requires CMOS logic level inputs. SPI Data Input; receives serial data from the control device; serial data transmitted to SDI is a 16-bit control word with the Least Significant Bit (LSB) transferred first: the input has a pull-down resistor and requires CMOS logic level inputs; SDI will accept data on the falling edge of the CLK signal. SPI Data Output; this tri-state output transfers diagnostic data to the control device; the output will remain tri-stated unless the device is selected by a low on Chip Select Not (CSN). Not connected 3 4 CLK SDI 5 SDO 7 8 9 10 11 12 13 14 15 n.c. Vs Vs Bus1 Power Supply Input; block to GND directly at the IC with ceramic capacitor. Ensure to have no current flow from PIN8 to PIN9. PIN8 and PIN9 can be directly connected. Power Supply Input; block to GND directly at the IC with ceramic capacitor. Ensure to have no current flow from PIN8 to PIN9. PIN8 and PIN9 can be directly connected. Vcc3 shunt Vcc3 base GND INT Vcc3REF C 16 17 18 19 20 21 22 23 24 25 Vcc1 µc Vcc2 VccHSCAN CANH SPLIT CANL GND TxDCAN RxDCAN TxDLIN Data Sheet on fi Ground Ground LIN Bus 1; Bus line for the LIN interface, according to ISO. 9141 and LIN specification 2.1 as well as SAE J2602-2. PNP Shunt; External PNP emitter voltage. PNP Base; External PNP base voltage. External PNP Output Voltage Interrupt Output, configuration Input; used as wake-up flag from SBC Stop Mode and indicating failures. Active low. Integrated pull up. During start-up used to set the SBC configuration. External Pull-up sets config 1/3, no external Pull-up sets config 2/4. Voltage Regulator Output; 5 V supply; to stabilize block to GND with an external capacitor. Voltage Regulator Output; 5 V supply; to stabilize block to GND with an external capacitor. Supply Input; for the internal HS CAN cell. CAN High Line; High in dominant state. Termination Output; to support recessive voltage level of the bus lines. CAN Low Line; Low in dominant state. CAN Transmit Data Input; integrated pull-up resistor. CAN Receive Data Output LIN Transceiver Data input; according to ISO 9141 and LIN specification 2.1 as well as SAE J2602-2. integrated pull-up resistor. 8 Rev. 1.0, 2009-03-31 de 6 GND Ground nt ia l TLE8263-2E Confidential Pin 26 27 28 29 30 31 32 33 34 35 36 Symbol RxDLIN TxDLIN2 RxDLIN2 n.c. n.c. GND Bus2 Function LIN Transceiver Data Output; according to the ISO 9141 and LIN specification 2.1 as well as SAE J2602-2; push-pull output; LOW in dominant state. LIN Transceiver Data Input; according to ISO 9141 and LIN specification 2.1 as well as SAE J2602-2. integrated pull-up resistor. LIN Transceiver Data Output; according to the ISO 9141 and LIN specification 2.1 as well as SAE J2602-2; push-pull output; LOW in dominant state. Not connected Ground Pin Configuration LIN Bus 2; Bus line for the LIN interface, according to ISO 9141 and LIN specification 2.1 as well as SAE J2602-2. WK Limp Home LH_PL/Test Monitoring / Wake-Up Input; bi-level sensitive input used to monitor signals coming from, for example, an external switch panel; also used as wake-up input; Fail-Safe Function Output; Open drain. Active LOW. SBC SW Development Mode entry; Connect to GND for activation; Integrated pullup resistor. Connect to VS or leave open for normal operation. Limp Home Pulsed Light output: Brake/rear light 100Hz 20% duty cycle output; Open drain. Active LOW. Exposed Die Pad; For cooling purposes only, do not use it as an electrical ground.1) EDP - Data Sheet C on fi 1) The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the PCB. The exposed die pad is not connected to any active part of the IC and can be left floating or it can be connected to GND for the best EMC performance. de nt 9 LH_SI Limp Home side indicator; Side indicators 1.25Hz 50% duty cycle output; Open drain. Active LOW. ia Not connected l Rev. 1.0, 2009-03-31 TLE8263-2E Confidential State Machine 4 4.1 State Machine Block Description First battery connection (POR) AND config0 not active l Condition / event SBC action WD conf SPI cmd SBC Init mode Vcc1 on SPI cmd (256ms max after reset relaxation) Vcc2/3 off CAN inact L.H. inact SBC SW Flash mode WD trig nt SPI cmd reset (initiated by SBC ) SPI cmd Vcc1 on L.H. act/inact Vcc2/3 on/off CAN Tx/Rx WD fixed LIN Flash mode ia LIN inact Vcc1 on L.H. act/inact SBC Normal mode Vcc2/3 on/off CAN conf WD conf LIN conf WD trig SPI cmd OR WD failed de SPI cmd SPI cmd Detection of falling edge at reset pin (any mode) OR undervoltage reset at VCC1µC (any mode) fi NOT reset clamped (high or low) OR NOT undervoltage at Vcc1 WK event stored LH entry condition stored OR Restart entry condition stored SBC Sleep mode Vcc1 off L .H. act/inact SBC Stop mode Vcc1 on L.H. act/inact Vcc2/3 off CAN Wakable/ off Wake up event WD off LIN Wakable/ off SPI cmd Vcc2/3 on/off CAN wakable/ off WD fixed/off WD trig LIN wakable/ off on SBC Restart mode Vcc2/3 on/off CAN 1st (config1) or 2nd (config3) WD trig failure in Normal / Stop / SW Flash mode Config 1/3: Reset clamped LOW (any mode) Vcc1 on Reset act. LIN waked or off Init mode not successful Config 1/3: Reset clamped HIGH during restart / init First battery connection (POR) AND config0 L.H. act/inact waked or off C SBC SW Development mode Vcc1 Vcc2/3 WD mode set mode set mode set L.H. CAN LIN mode set mode set mode set CAN, LIN, WK Wake-up OR Release of over temperature at Vcc1 (Wake-up event stored) (LH entry condition stored) SBC Fail-Safe mode 1st (config2) or 2nd (config4) WD trig failure in Normal / Stop / SW Flash mode Config 2/4: Reset clamped LOW (any mode) SBC Factory Flash mode Config 2/4: Reset clamped HIGH during Restart or Init mode Vcc1 off L.H. act Vcc2/3 off CAN sleep WD off LIN sleep Vcc1 ext. L.H. inact. Vcc2/3 off CAN off WD off LIN off Vcc1 over temperature shutdown OR V S > VUV_ON & Undervoltage time out on VCC1 Power mode managment.vsd Figure 3 Power Mode Management Data Sheet 10 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential State Machine 4.2 State Machine Description The System Basis Chip (SBC) offers ten operating modes: Power On Reset, Init, Normal, Restart, Software Flash, Sleep, Stop, Fail-Safe, Software Development, and Factory Flash Mode. The modes are controlled with one test pin and via three mode select bits MS2..0, within the SPI. Additionally, the SBC allows five configurations, accessed via two external pins and one SPI bit. 4.2.1 Table 1 Configuration Description SBC Configuration Description Software Development Mode Configuration config 0 config 1 config 2 config 3 ia Table 1 provides descriptions and conditions for entry to the different configurations of the SBC. Test pin 0V INT Pin n.a WD to LH bit n.a After missing the WD trigger for the first time, Vcc1µC turns OFF, LH pin is active, SBC in Fail-Safe Mode nt After missing the WD trigger for the first time, the state of Vcc1µC Open / VS External 0 remain unchanged, LH pin is active, SBC in Restart Mode pull-up No ext. pull-up 0 l External 1 pull-up No ext. pull-up 1 11 Rev. 1.0, 2009-03-31 config 4 After missing the WD trigger for the second time, Vcc1µC turns OFF, LH pin is active, SBC in Fail-Safe Mode In SBC SW Development Mode, Config 1 to 4 are accessible. 4.2.2 SBC Power ON Reset (POR) At VS > VUVON, the SBC starts to operate, by reading the test pin and then by turning ON Vcc1µC. When Vcc1µC reaches the reset threshold VRT1, the reset output remains activated for tRD1 and the SBC enters then the Init Mode. In the event that Vs decreases below VUVOFF, the device is completely disabled. For more details on the disable behavior of the SBC blocks, please refer to the chapter specific to each block. 4.2.3 SBC Init Mode At entering the SBC Init Mode, the SBC starts to read the Test pin. The SBC starts-up in SBC Init Mode, and, after powering-up, waits for the microcontroller to finish its startup and initialization sequences. Vcc2/3 are OFF and the Watchdog is configurable but not active. CAN and LIN modules are inactive and Limp Home output is inactive. From this transition mode, the SBC can be switched via SPI command to the desired operating mode, SBC Normal or Software Flash Mode. If the SBC does not receive any SPI command, or receive wrong SPI command (i.e. not send the device to SBC Normal or SBC SW Flash Mode) within a 256 ms time frame after the reset relaxation, it will enter into SBC Restart Mode and activate the Limp Home output. Note: In Init Mode it is recommended to send one SPI command that sets the device to Normal Mode, triggers the watchdog the first time and sets the required watchdog settings. Data Sheet C on fi de After missing the WD trigger for the second time, the state of Vcc1µC remain unchanged, LH pin is active, SBC in Restart Mode TLE8263-2E Confidential State Machine 4.2.4 SBC Normal Mode SBC Normal Mode is used to transmit and receive CAN and LIN messages. In this mode, Vcc1µC is always “ON” Vcc2 and Vcc3 can be turned-on or off by SPI command. In Normal Mode the watchdog needs to be triggered. It can be configured via SPI, window watchdog and time-out watchdog is possible (default value is time-out 256 ms). All the wake-up sources can be inhibited in this mode. The Limp Home output can be enabled or disabled via SPI command. Via SPI command, the SBC can enter Sleep, Stop or Software Flash Mode. A reset is triggered by the SBC when entering the Software Flash Mode. It is recommended to send at first SPI command the watchdog setting. Please refer to Chapter 13.4. 4.2.5 SBC Sleep Mode Note: Do not change the transceiver settings in the same SPI command that sends the SBC to Sleep Mode. 4.2.6 SBC Stop Mode The watchdog can be used or switched off. If the watchdog is used the settings made in Normal Mode are also valid in Stop Mode and can not be changed. If a wake-up event occurs the INT pin is set to low. The µC can react on the interrupt and set the device into Normal Mode via SPI. There is no automatic transition to SBC Normal Mode. There are 4 Options for SBC Stop Mode • • • • WD on (the watchdog needs to be served as in Normal Mode WD off (special sequence required see Chapter 11.2.4) Cyclic Wake up with acknowledge (interrupt is sent after set time and needs to be acknowledged by SPI read) Cyclic Wake-up, Watchdog off (interrupt is sent after set time) Cyclic Wake-Up Feature SBC Stop Mode supports the cyclic wake-up feature. By default, the function is OFF. It is possible to activate the cyclic wake-up via “Cyclic WK on/off” SPI bit. This feature is useful to monitor battery voltage, for example, during parking of the vehicle or for tracking RF data coming via the RF receiver. The Cyclic Wake-up feature sends an interrupt via the pin INT to the µC after the set time. The cyclic wake-up feature shares the same clock as the Watchdog. The time base set in the SPI for the Watchdog will be used for the cyclic wake-up. The timer has to be set before activating the function. With the cyclic wake-up feature the watchdog is not working as known from the other modes. In the case that both functions (Watchdog and cyclic wake-up) are selected, the cyclic wake-up is activated and each interrupt has to be acknowledged by reading the SPI Wake register before the next Cyclic Wake-Up comes. Otherwise, the SBC goes to SBC Restart Mode. Data Sheet 12 Rev. 1.0, 2009-03-31 C on The CAN and LIN modules are not active. They can be selected to be off or used as wake-up source. If all wake up sources are disabled, (CAN, LIN, WK, cyclic wake) the watchdog can not be disabled, the SBC stays in Normal Mode and the watchdog continues with the old settings. fi The Stop Mode is used as low power mode where the µC is supplied. In this mode the voltage regulator Vcc1µC remains active. The other voltage regulator (Vcc2/3) can be switched on or off. de During SBC Sleep Mode, the lowest power consumption is achieved by having the main and external voltage regulators switched-off. As the microcontroller is not supplied, the integrated Watchdog is disabled in Sleep Mode. The last Watchdog configuration is not stored. The CAN and LIN modules are in their respective Wake-capable or OFF modes and the Limp Home output is unchanged, as before entering the Sleep Mode. If a wake-up appears in this mode, the SBC goes into Restart Mode automatically. In Sleep Mode, not all wake-up sources should be inhibited, this is required to not program the device in a mode where it can not wake up. If all wake sources are inhibited when sending the SBC to Sleep Mode, the SBC does not go to Sleep Mode, the microcontroller is informed via the INT output, and the SPI bit “Fail SPI” is set. The first SPI output data when going to SBC Normal Mode will always indicate the wake up source, as well as the SBC Sleep Mode to indicate where the device comes from and why it left the state. nt ia l TLE8263-2E Confidential State Machine 4.2.7 SBC Software Flash Mode SBC Software Flash Mode is similar to SBC Normal Mode regarding voltage regulators. In this mode, the Limp Home output can be set to active LOW via SPI and the communication on CAN and LIN modules is activated to receive flash data. In the LIN module the slope control mechanism is switched off. The Watchdog configuration is fixed to the settings used before entering the SBC SW Flash Mode. When the device comes from SBC Normal Mode, a reset is generated at the transition. From the SBC Software Flash Mode, the SBC goes into SBC Restart Mode, the config setting has no influence on the behavior. A mode change to SBC Restart Mode can be caused by a SPI command, a time-out or Window Watchdog failure or an undervoltage reset. When leaving the SBC Software Flash Mode a reset is generated. 4.2.8 SBC Restart Mode They are multiple reasons to enter the SBC Restart Mode and multiple SBC behaviors described in Table 2. • • • • • From SBC SW Flash Mode, it is used to start the new downloaded code. From SBC Normal, SBC Stop Mode and SBC SW Flash Mode it is reached in case of undervoltage on Vcc1µC, or due to incorrect Watchdog triggering. From SBC Sleep Mode it is used to ramp up Vcc1µC after wake From SBC Init Mode, it is used to avoid the system to remain undefined. From SBC Fail-safe Mode it is used to ramp up Vcc1µC after wake or cool down of Vcc1µC. Entering or leaving the SBC Restart Mode will not result in deactivation of the Limp Home output (if activated). The first SPI output data when going to SBC Normal Mode will always indicate the reason for the SBC Restart event. Data Sheet C on fi From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode. The delay time tRDx is programmable by the “Reset delay” SPI bit. The Reset output (RO) is released at the transition. SBC Restart Mode is left automatically by the SBC without any microcontroller influence. The first SPI output data will provide information about the reason for entering Restart Mode. The reason for entering Restart Mode is stored and kept until the microcontroller reads the corresponding “LH0..2” or “RM0..1” SPI bits. In case of a wake up from Sleep Mode the wake source is seen at the interrupt bits (Configuration select 000), an interrupt is not generated. de nt 13 In any case, the purpose of the SBC Restart Mode is to reset the microcontroller. ia l Rev. 1.0, 2009-03-31 TLE8263-2E Confidential State Machine Table 2 Mode SBC Restart Mode Entry Reasons and Actions Actions LH output Init Mode time-out Reset low from outside Reset clamped undervoltage reset ON Unchanged ON unchanged ON WD trigger failure Config n.a SBC Mode and Configuration Entering reason Vcc1µC RO SPI Out Bits LH 0..2 RM 0..1 LH 0..2 RM 0..1 LH 0..2 RM 0..1 after 1st LH 0..2 after 2nd RM 0..1 after 1st2) remains ON LOW config 1/3 n.a config 1 config 3 Normal1) config 4 n.a. config 1/3 n.a n.a Software Flash n.a n.a. config 1/3 Sleep n.a n.a config 1 config 3 Stop1) config 4 ia l Init Mode n.a. remains ON LOW remains ON LOW ramping up LOW OFF after 1st remains ON LOW ON after 2nd OFF after 1st remains ON LOW remains ON LOW remains ON LOW remains ON LOW remains ON LOW remains ON LOW remains ON LOW ramping up ramping up LOW LOW Reset low from outside Reset clamped SPI cmd nt ON ON ON ON ON ON 14 Unchanged RM 0..1 LH 0..2 RM 0..1 RM 0..1 RM 0..1 RM 0..1 LH 0..2 WK bits register RM 0..1 LH 0..2 RM 0..1 after 1st LH 0..2 after 2nd RM 0..1 after 1st2) undervoltage reset WD trigger failure Reset low from outside Reset clamped unchanged unchanged de unchanged Unchanged Wake-up event unchanged unchanged fi undervoltage reset WD trigger failure on n.a. OFF after 1st remains ON LOW ON after 2nd OFF after 1st Unchanged remains ON LOW remains ON LOW ramping up ramping up LOW LOW Reset low from outside RM 0..1 LH 0..2 LH 0..2 RM 0..1 RM 0..1 LH 0..2 config 1/3 n.a n.a. Reset clamped Wake-up event Reset low from outside Fail-Safe Software Development Mode n.a. C undervoltage reset unchanged Unchanged remains ON LOW remains ON LOW config 1/3 Reset clamped 1) Config 2 will never enter Restart Mode in case of WD failure but directly Fail-Safe Mode 2) Goes to Fail-Safe Mode after the second consecutive failure Data Sheet Rev. 1.0, 2009-03-31 TLE8263-2E Confidential State Machine 4.2.9 SBC Fail-Safe Mode In SBC Fail-Safe Mode, all voltage regulators are OFF and the transceivers are in Wake-Capable Mode. The Limp Home output is active. Conditions to enter the SBC Fail-Safe Mode are: • • • • Watchdog trigger failure in configuration 2 or 4 Vcc1µC undervoltage time-out in any configuration if VS is above VLHUV range. Temperature shutdown of Vcc1µC in any configuration. Reset clamped in Config. 2/4 In case of Vcc1µC overtemperature shutdown, the SBC will latch and wait to cool down below the thermal hysteresis, and will go back to SBC Restart Mode. In case of a wake-up event, the SBC will go to SBC Restart Mode (not in case of Vcc1µC overtemperature shutdown), storing the wake-up event and resetting the Watchdog trigger failure counter. The first SPI output data when going to SBC Normal Mode will always indicate the reason for the SBC Fail-Safe Mode. 4.2.10 SBC Software Development Mode 4.2.11 SBC Factory Flash Mode Note: Please respect the absolute maximum ratings when the device is in SBC Factory Flash Mode. Data Sheet C on In this mode, the SBC is completely powered OFF and the microcontroller is supplied externally. The mode is detected when VCC1µC is powered from external and the voltage on Vs is not powered from external. The current flow out of Vs must be limited to the maximum rating. The external supply voltage should be below the absolute maximum rating stated in Chapter 5.1. The reset can be driven by an external circuit, or pulled high with a pull-up resistor. fi de If the Test pin is connected to GND (Config 0 active) during powering-up, the SBC enters SBC Software Development Mode. SBC Software Development Mode is a super set of the other modes so it is possible to use all the modes of the SBC with the following difference. In SBC Software Development Mode, no reset is generated and VCC1µC is not switched off due to Watchdog trigger failure. If a Watchdog trigger failure occurs, it will be indicated by the INT output (reset bit). The SBC Fail-Safe Mode or SBC Restart Mode are not reached in case of wrong Watchdog trigger but the other reasons to enter these modes are still valid. nt 15 ia l Rev. 1.0, 2009-03-31 TLE8263-2E Confidential General Product Characteristics 5 5.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Voltages 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Supply Voltage nt -0.3 -27 -40 VS dVS/dt Supply Voltage Slew Rate Regulator Output Voltage Vcc1µC/2/3 CAN Bus Voltage (CANH, CANL) VCANH/L Differential Voltage CANH, CANL, SPLIT VdiffESD ia Min. -0.3 -0.5 5 -0.3 -27 -0.3 -0.3 -0.3 -0.3 -0.3 -27 -500 -40 -55 -6 -2 – 6 2 Pos. Parameter Symbol Limit Values Max. 40 5.5 40 40 l 5.5 40 40 40 40 0.3V 0.3V 40 150 150 750 500 Unit Test Conditions V V V V – – – CANH-CANL VUV OFF; – -1) -1) Pull up to VS RLHO = 40kΩ 3) Data Sheet C on Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. fi 1) In the case Vs < VUVOFF, the SBC is switched OFF and will restart in INIT Mode at next Vs rising. 2) During load dump, the others pins remains in their absolute maximum ratings 3) Not subject to production test, specified by design Rev. 1.0, 2009-03-31 TLE8263-2E Confidential General Product Characteristics 5.3 Pos. 5.3.1 Thermal Characteristics Parameter Junction Ambient Junction Ambient Symbol Min. Limit Values Typ. 40 Max. K/W K/W K/W °C K °C K – °C K °C K 1) 3) Unit Test Conditions 300 mm2 cooling area 2) 3) RthJA_1L RthJA_4L RthJSP TjPW ∆TPW – – – l – 170 – 200 – – 200 – 200 – 25 5 ia 145 25 185 35 1.20 – 10 – 10 2s2p + 600 mm2 cooling area 3) 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 Junction to Soldering Point Thermal Prewarning and Shutdown Junction Temperatures; VCC1µC, Thermal Pre-warning ON Temperature Hysteresis 120 – -3) 3) nt 150 – – 150 – 150 – 18 VCC1µC, Thermal Prewarning VCC1µC, VCC2 Thermal Shutdown Temperature VCC1µC, VCC2 Thermal Shutdown Hysteresis VCC1µC, Ratio of SD to PW Temperature TjSDVcc 3) ∆TSDVcc 3) de TjSDVcc/ TjPW 3) CAN Transmitter Thermal Shutdown Temperature CAN Transmitter Thermal Shutdown Hysteresis TjSDCAN 3) ∆TCAN 3) fi LIN Transmitter Thermal Shutdown TjSDLIN Temperature 3) 1) Specified Rthja value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 single layer. The product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board. 2) According to Jedec JESD51-2,-5,-7 at natural convection on 2s2p board for 2W. Board: 76.2x114.3x1.5mm³ with 2 inner copper layers (35µm thick)., with thermal via array under the exposed pad contacted the first inner copper layer and 600mm2 cooling are on the top layer (70µm) 3) Not subject to production test; specified by design; Data Sheet C on LIN Transmitter Thermal Shutdown ∆TLIN Hysteresis 3) Rev. 1.0, 2009-03-31 TLE8263-2E Confidential General Product Characteristics 5.4 Current Consumption VS = 5.5 V to 28 V; all outputs open; Without VCC3; Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Min. Normal Mode; 5.4.1 Current Consumption for Internal Logic Limit Values Typ. – Max. Unit Test Condition IVS_logic – l 2 mA 10 mA 12 mA 3.0 mA 5.0 mA 75 µA 85 90 µA 100 5.4.2 IVS_CAN Additional current Consumption for CAN Cell – ia – – – – 58 65 70 78 19 SBC Normal Mode ICC1µC = ICC2 = 0mA; CAN OFF mode; LIN OFF mode CAN Normal Mode; Recessive state; VCC2 connected to VCCHSCAN VTxD = Vcc1µC; without RL CAN Normal Mode; dominant state; VCC2 connected to VCCHSCAN VTxD = low; without RL; LIN Normal Mode; recessive state; without RL; VTxD = Vcc1µC LIN Normal Mode; dominant state; without RL; VTxD = low SBC Stop Mode; Vs = 13.5 V; VCC1µC“ON”; VCC2/3“OFF” CAN/LIN wake capable; Tj = 25°C 5.4.3 Additional Current IVS_LIN Consumption per LIN Cell fi on Stop Mode 5.4.4 Current Consumption IVS C de – – – – – nt – Data Sheet Tj = 85°C1) SBC Stop Mode; Vs = 13.5 V; VCC1µC/2“ON”; VCC3“OFF” CAN/LIN wake capable; Tj = 25°C Tj = 85°C1) Rev. 1.0, 2009-03-31 TLE8263-2E Confidential General Product Characteristics 5.4 Current Consumption (cont’d) VS = 5.5 V to 28 V; all outputs open; Without VCC3; Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Min. Sleep Mode 5.4.5 Current consumption, all Wake Up Sources available. Limit Values Typ. 28 Max. Unit Test Condition IVS_sleep_ – SBC l 40 µA 50 – µA – µA ia 32 SBC Sleep Mode; Tj = 25°C Vs = 13.5 V; VCC1µC/2/3“OFF” CAN/LIN wake capable; Tj = 85°C1) 1) LIN de IVS_sleep_ 5 CAN nt 12 20 5.4.6 Quiescent Current Reduction when one Wake Capable LIN Cell Disabled IVS_sleep_ 0.5 1 SBC Sleep Mode; Tj = 25°C; VS = 13.5 V; VCC1µC/2/3“OFF” CAN/LIN 1_2 wake capable; LIN3 OFF 1) 5.4.7 Quiescent Current Reduction when Wake Capable CAN Cell Disabled SBC Sleep Mode; Tj = 25°C; VS = 13.,5 V; VCC1µC/2/3“OFF” LIN 1..3 wake capable; CAN OFF 1) Not subject to production test; specified by design Data Sheet C on fi Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Internal Voltage Regulator 6 6.1 Internal Voltage Regulator Block Description Vref 1 Overtemperature Shutdown ia 1 21 Vs l State Machine Bandgap Reference V CC 1µC V CC2 nt INH Vref Charge Pump fi de GND INTE RNA L RE GULA TOR DIA GRA M V S D . Figure 4 Functional Block Diagram 6.2 It is possible to turn Vcc1µC via SBC Modes and Vcc2 activity ON or OFF via SPI command or by entering SBC modes. The limiting current for the both regulators is ICC1µC_max/ICC2. 6.3 Depending on the SBC Mode in use, Vcc1µC and Vcc2 can be either ON or OFF by definition, Vcc2 can be also turned ON or OFF, via SPI. Table 3 identifies the possible states of the voltage regulators, based on the various SBC modes. Data Sheet C The internal voltage regulators are dual low-drop voltage regulators that can supply loads up to ICC1µC/2_max. An input voltage up to VSMAX is regulated to Vcc1µC/2_nom = 5.0 V with a precision of ±2%. Due to its integrated reset circuitry, featuring two SPI configurable power-on timing (tRDx) and three SPI configurable output voltages (VRTx) monitoring, the device is well suited for microcontroller supply. The design enables stable operation even with ceramic output capacitors down to 470nF, with ESR < 1 Ω @ f = 10 kHz. The device is designed for automotive applications, therefore it is protected against overload, short circuit, and overtemperature conditions. Figure 4 shows the functional block diagram. If the VS voltage is lower than VUV_OFF, the DMOS of the voltage regulator is switched to high impedance. The body diodes of the DMOS might go into conduction when VCC1µC or VCC2 > VS (no reverse protection). Internal Voltage Regulator Modes Internal Voltage Regulator Modes with SBC Mode on Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Internal Voltage Regulator Table 3 SBC Mode INIT Mode Internal Voltage Regulators States Vcc1µC ON ON OFF ON ON ON OFF OFF ON OFF OFF Vcc2 Normal Mode Sleep Mode Restart Mode Software Flash Mode Stop Mode Fail-Safe Mode l unchanged ON ON ia OFF V UV OFF VRTx,f Any mode SBC OFF OFF OFF 6.4 6.4.1 Application information Timing Diagram Figure 5 shows the ramp up and down of the VS, and the dependency of Vcc1µC. At the first ramp up from SBC Init Mode, the reset threshold VRT and time tRO are set to the default value. See Chapter 11.1 VUV ON de Vs nt t Vcc1µC VRTx,r fi GND t on RO SBC OFF SBC Init t An undervoltage time-out on Vcc1µC is implemented. Refer to Chapter 13 for more information on this function. 6.4.2 The Vcc2 voltage regulator integrates an under voltage detection. When Vcc2 voltage goes below VUV_VCC2, the failure is indicated by an interrupt and the failure is reported into the diagnosis frame of the SPI. Data Sheet C Figure 5 Ramp up / Down of Main Voltage Regulator Under voltage detection at Vcc2 22 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Internal Voltage Regulator 6.5 Electrical Characteristics Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Min. Voltage Regulator; Pin Vcc1 µC 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 Output Voltage Line Regulation Load Regulation Power Supply Ripple Rejection Output Current Limit Typ. 5.0 Max. Unit Test Condition VS = 5.5 V to 28 V; CCC1µC = CCC2 = 470 nF; all outputs open; SBC Normal Mode; ∆VCC1µC,Li ∆VCC1µC,Lo PSRR ia – – 20 50 – 500 40 – – 5.0 – – 40 – 0.5 5.1 20 50 – 500 – 4.65 0.5 4.8 23 VCC1µC l 5.1 V mV mV dB mA 0 mA VUVON until Init Mode is left). If the pin is low for the Init Mode time, Software Development Mode is reached. The mode is stored during the complete time where VS is above VUVOFF. It means to leave Software Development Mode, the SBC must go back to SBC OFF mode. Data Sheet C on fi de ia Limp home LH_P L_test. vsd l Rev. 1.0, 2009-03-31 R LH_ PL TLE8263-2E Confidential Limp Home 13.3 Activation of the Limp Home Output The reason to activate the Limp Home pins and the consequences are listed in Table 12 and Table 13. Table 12 SBC Mode INIT Mode Normal Mode Stop Mode Sleep Mode Restart Mode Fail-Safe Mode SW Flash Mode Table 13 SBC Mode INIT Mode Normal Mode Restart Mode Limp Home, Function of the SBC Mode Limp Home Outputs OFF Unchanged Unchanged Unchanged ON Unchanged ON via SPI ON if it was ON until the successful Watchdog setting and deactivation via SPI. OFF Automatic Activation of Limp Home Output Reason 1st Watchdog failure (config 1/2) 2nd Watchdog failure (config 3/4) Reset output permanent short circuit to Vcc1µC Reset output permanent short circuit to GND Vcc1µC undervoltage time-out Any mode When Limp Home is activated via SPI command, then it is released via SPI command. This is useful for diagnosis purpose for example. Otherwise, the Limp Home outputs are released only in SBC Normal Mode with the following conditions: After the device has been set to SBC Restart Mode, automatically entering SBC Normal Mode, a successful Watchdog trigger must be sent via SPI. At this point, the Limp Home outputs remain active. Then the microcontroller needs to send by SPI command the deactivation of the Limp Home. 13.5 A Vcc1µC undervoltage time-out condition is given, when 1) the Vcc1µC output voltage is below the reset threshold (VRT1, VRT2, VRT3), 2) VS is higher then the threshold (VSthUV1, VSthUV2, VSthUV3) and 3) the condition is valid longer then the Vcc1µC under voltage time-out (tVcc1UVTO). A Vcc1µC undervoltage time-out will sent the device into Fail-Safe Mode. Limp Home output stag will be activated (for Vs > VLHUV) Figure 34 gives an example of the Limp Home output activation, due to a Vcc1µC undervoltage time-out. Data Sheet C Vcc1µC undervoltage time-out on 13.4 Release of the Limp Home Output fi If previously turned ON in SBC Normal Mode, via SPI command Vcc1µC thermal shutdown de INIT time-out (tINITTO) nt 68 Rev. 1.0, 2009-03-31 ia l TLE8263-2E Confidential Limp Home Vs VSthUVx Vcc1µC t VRTx VRTx GND RO tVcc1UVTO ia SBC Restart l t SBC Fail safe SBC Sleep SBC Restart SBC Normal nt Limp home Wake Up tRDx tRR t GND de t undervoltage time out.vsd Figure 34 Vcc1µC undervoltage time-out timing Data Sheet C on 69 fi Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Limp Home 13.6 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin unless otherwise specified. Pos. Parameter Symbol Limit Values Min. Limp Home; 13.6.1 Watchdog edge count difference to set Limp Home activated Limp Home low output voltage (active) Limp Home high output current (inactive) INIT Time-out Vcc1µC under voltage Time-out Typ. 1 2 Max. Unit Test Condition nLH – l – – 0.4 2 V µA ms ms V V V V V – 1150 6.3 5.3 5.0 5.5 – 1,375 – Hz % 3 700 – 80 110 V mV V kΩ Hz % With SPI set. Default Setting ILH = 1mA VLH = 28V 1) 13.6.2 13.6.3 13.6.4 13.6.5 13.6.6 VLHLO ILHHI – 0 tINITTO – tVcc1UVTO 900 VSthUV1 5.3 4.3 4.0 4.5 Vs threshold for Vcc1µC nt 256 1024 – – – – 0.2 1.125 – 1.25 50 – 100 1 20 90 – 300 – 40 100 20 70 ia 0.2 – VRT1 default setting VRT2 SPI option VRT3 SPI option – – 13.6.7 13.6.8 ; 13.6.9 13.6.10 Threshold for Limp Home VLHUV minimum Vs Limp Home Vs voltage hysteresis Limp Home side indicator dSI duty cycle HIGH Level Input Voltage VTest,HI Threshold on Limp Home side indicator fLHSI frequency fi de VLHUVhys – VTest,hys VTest,LO RTest fLH_PL dPL under voltage Time-out (Vs needs to be above, to V SthUV2 activate Vcc1µC under VSthUV3 voltage Time-out) – – LH_PL/Test 13.6.11 13.6.12 13.6.13 13.6.14 13.6.15 13.6.16 – – – C Input Hysteresis LOW Level Input Voltage Threshold Pull-up Resistor Limp Home pulsed light frequency Limp Home pulsed light duty cycle VLH_PL/Test = 0V SBC Init Mode – – 1) Not subject to production test, specified by design. Data Sheet Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Configuration Select 14 14.1 Configuration Select Configuration select 14.2 Config Hardware Descriptions Figure 35 gives the electrical equivalents to the configuration function of the INT pin. de Time out R CFG nt 71 In Init Mode before the RO pin goes high the INT pin is pulled to low with a weak pull down resistor RCFG, the pull up resistor RINT is switched off. When Vcc1µC is high, above the reset threshold VRT1 and before the RO pin goes high the level on the INT pin is monitored to select the configuration. With RO going high in Init Mode the pull up resistor RINT is switched on. Configuration logic ia The Configuration select is used to set the device for two different SBC behaviors; please refer to Chapter 4.2.1 for detailed information. Depending on the requirements of the application, the Vcc1µC is switched off and the device goes to Fail-Safe Mode in case of watchdog fail (1 or 2 fail) or reset clamped. To turn Vcc1µC OFF (Config 2/4), the INT pin is not connected to a pull up resistor externally. In case the Vcc1µC is not switched off (Config 1/3) the INT pin is connected to Vcc1µC with a pull up resistor. The configuration is only read during Init Mode, after that the configuration is stored. fi l Vc c 1µC R INT INT Interrupt logic on Electrical characteristics are listed in chapter Chapter 12.5 Data Sheet INTERRUPT BLOCK_CONFIG.VSD C Figure 35 Config Logic Diagram Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15 15.1 Serial Peripheral Interface SPI Description The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK supplied by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 36). The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After the CSN input returns from LOW to HIGH, the word that has been read in becomes the new control word. The SDO output switches to tri-state status (high impedance) at this point, thereby releasing the SDO bus for other use. The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted out of the output register after every rising edge on CLK. The number of received input clocks is supervised by a modulo-16 operation and the Input / Control Word is discarded in case of a mismatch. This error is flagged in the following SPI output by a “HIGH” at the data output (SDO pin, bit FO) before the first rising edge of the clock is received. The SPI of the SBC is not daisy chain capable. CSN high to low: SDO is enabled. Status information transferred to output shift register CSN de nt ia l time CSN low to high: data from shift register is transferred to output functions CLK fi time Actual data New data FI 01 ++ time SDI FI - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDI: will accept data on the falling edge of CLK signal Actual status on New status FO 0 + 1 + time SDO FO - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDO: will change state on the rising edge of CLK signal Figure 36 15.2 When the microcontroller send a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI command can be either a number of bits different of 16, the mode selection (MS2..0) = 000 or requesting to go to an SBC mode which is not allowed by the state machine, for example from SBC Stop Mode to SBC SW Flash Mode. In that case, an interrupt is generated (if not inhibited) and the bit SPI Fail is set. Since the SPI data is corrupted, the next SPI output data will remain the former one (the information is then repeated). Data Sheet C SPI Data Transfer Timing Corrupted data in the SPI data input 72 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15.3 SPI Input Data MSB LSB WD refresh l CS2 CS1 Input Data 15 14 13 12 11 10 9 8 7 6 5 4 3 CS0 2 MS2 1 MS1 0 MS0 ia WK LIN1 WK CAN OT HS CAN Configuration Registers Res. Res. Res. WK 1 WK 0 Res. WK pin WK pin WK LIN2 Configuration Select Mode Selection Bits not valid Restart SW Flash Normal Sleep Stop Fail safe Read Only 000 000 INTERRUPT MASK Res. Res. LIN 2 LIN2 LIN1 LIN1 failure failure failure failure 1 0 1 0 nt Wrong Reset WD set Fail SPI ICC3 > ICC3max UV Vcc3 UV VCC2 OT VCC2 OTP Vcc 1µC 001 001 CAN Bus CAN CAN failure failure 1 0 010 010 R eserved WD to LH 011 011 de Cyclic L.H. VCC2 WK PIN VCC3 Reset WK On/off On/Off On/off On/off Delay On /off CAN 1 CAN 0 LIN2 1 LIN 2 0 RT1 RT0 100 100 REGISTER LIN 10.4k Res. Res. LIN1 1 LIN 1 0 101 101 fi Ti. CHK WD Out / SUM On/Off Win. Set to 1 Window /Time out Watchdog Timing Bit Position: 10 .. 6 Test 2 Test 1 Test 0 110 110 LH Reserved 0 2 LH 1 LH 111 111 on SPI data input TLE8263.vsd Figure 37 16-Bit SPI Input Data / Control Word Data Sheet C 73 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15.4 SPI Output Data MSB LSB Output 15 14 13 12 11 10 Data WK state 9 8 7 6 5 CS2 4 CS1 3 CS0 2 MS2 1 MS1 0 MS0 l ia WK LIN1 WK CAN OT HS CAN Configuration Registers INT Res. Cyclic WK 1 WK 0 Res. WK WK pin WK pin WK LIN2 Configuration Select Mode Selection Bits Init Restart SW Flash Normal Sleep Stop Fail Safe Reserved 000 000 Res. Res. LIN 2 LIN2 LIN1 LIN1 failure failure failure failure 1 0 1 0 nt Status or INTERRUPT event Wrong Reset WD set Fail SPI ICC3 > ICC3max UV Vcc3 UV VCC2 OT VCC2 OTP Vcc1µC 001 001 CAN Bus CAN CAN failure failure 1 0 010 010 R eserved WD to LH 011 011 de Cyclic L.H. VCC2 WK PIN VCC3 Reset WK On/off On/Off On /off On/off Delay On/off CAN 1 CAN 0 LIN2 1 LIN 2 0 RT1 RT0 100 100 LIN 10.4k Res. Res. LIN1 1 LIN 1 0 101 101 R EGISTER CHK WD SUM On/Off fi Ti. Out / Win. Set to 1 Window /Time out Watchdog Timing Bit Position: 10 .. 6 LH 1 LH 0 Test 2 Test 1 Test 0 110 110 Res. RM1 RM0 LH 2 111 111 Figure 38 16-bit SPI Output Data / Control Word 15.5 15.5.1 SPI Data Encoding The WD Refresh bit is used to trigger the Watchdog. The first trigger should be a 1, and then a 0. For more details, please refer to Chapter 11.2. The WK state bit gives the voltage level at the WK pin. A 1 indicates a high level, a 0 a low level. Data Sheet C WD Refresh bit / WK state on SPI_Settings_out_TLE8263.vsd 74 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15.5.2 15.5.2.1 SBC Configuration Setting and Read Out Mode selection bits and configuration select Table 14 lists the encoding of the possible SBC mode. Except SBC Restart and Init Mode which are most of time entered automatically, all others SBC mode are accessible on request of the microcontroller. The microcontroller should send the correct mode selection bits to set the SBC in the respective mode. The output indicates the SBC mode where the SBC currently is or was, depending on the situation. Table 14 MS2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Mode Selection Bits Data Input Set the SBC to SBC Restart Mode. (In SW Flash mode only) Set the SBC to SBC Normal Mode Set the SBC to SBC Sleep Mode Set the SBC to SBC Stop Mode 0 1 0 1 0 1 0 1 MS1 MS0 Not valid (the complete SPI word is ignored) Show the device was in Init previous SPI data Set the SBC to Software Flash Mode Table 15 CS2 0 0 0 0 1 1 1 1 CS1 0 0 1 1 0 0 1 1 Configuration Select Encoder (for Data Input and Output) CS0 0 1 0 1 0 1 0 1 Configuration Register Select Wake Register Interrupt SBC Failure Interrupt Communication Failure Interrupt Reserved SBC Configuration Register Communication Setup Register Watchdog Configuration Register Limp Home / Diagnosis Register Data Sheet C on Table 15 lists the eight possible configuration selection. Some are related to event or state of the different part of the SBC, others are used to configure the SBC in the application specific set up. fi Set the SBC to Read Only SPI access. The Reserved configuration register needs to be selected. The SPI information on SDO is provided in the same SPI frame. No write access is done in this mode. Bit 15 (Watchdog) has to be served correctly. de Set the SBC to SBC Fail-Safe Mode Show the device was in SBC Fail-Safe Mode (In SBC Software Development mode only) nt 75 ia Data Output Show the device was in Restart previous SPI data Show the device is SBC Software Flash Mode Show the device is in SBC Normal Mode Show the device was in SBC Sleep Mode Show the device is in SBC Stop Mode l Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15.5.2.2 Interrupt Register Encoder Table 16 lists all interrupts the SBC can generates. The microcontroller should read the correct register to release the INT pin. By default, all interrupt sources are enabled. The microcontroller can decide to inhibit a specific interrupt source. Table 16 CS Interrupt Register encoder 1) Default Value (INPUT) 1 1 11 Default Value (OUT) Bit Name Data Input Configuration select 000 (Wake register interrupt) 000 WK CAN WKLINx WK 1 WK pin WK 0 WK pin 0 0 00 Interrupt enabled (1) disabled (0) for wake event on CAN ia nt n.a n.a 76 Interrupt enabled (1) disabled (0) for wake event on LIN Interrupt enabled (1) disabled (0) for wake pin event. 00 No interrupt 10 Interrupt for a LOW to HIGH transition on WK 01 Interrupt for HIGH to LOW transition on WK 11 Interrupt for both HIGH to LOW and LOW to HIGH on WK Cyclic WK INT n.a n.a de 0 0 fi Data Sheet C on l Data Output Wake on CAN (1) Wake on LINx (1) Wake on WK pin 00 No wake 10 Interrupt for a LOW to HIGH transition on WK 01 Interrupt for HIGH to LOW transition on WK 11 Interrupt for both HIGH to LOW and LOW to HIGH on WK Cyclic WK (1) Indicates that there is a status bit or uncleared event in configuration select 001 and/or 010. If set read the two register Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Table 16 CS Interrupt Register encoder (cont’d)1) Default Value (INPUT) 1 1 1 1 Default Value (OUT) Serial Peripheral Interface Bit Name Data Input Data Output Configuration select 001 (SBC Failure interrupt) 001 OT_Vcc2 UV_Vcc3 0 0 Interrupt enabled (1) disabled (0) for temperature shutdown ia OT_HSCAN 0 Interrupt enabled (1) disabled (0) for temperature shutdown SPI Fail Reset 1 1 0 0 nt Vcc2 77 Interrupt enabled (1) disabled Undervoltage detection on Vcc3 (0) for undervoltage detection (1) or due to back to normal voltage Interrupt enabled (1) disabled (0) for SPI corrupted data. SPI input corrupted data (1) Reset (1) (only in SBC Software Development Mode) Incorrect WD programming for data output Wrong WD set 1 ICC3 > ICC3max 1 fi UV Vcc2 1 Configuration select 010 (Communication failure interrupt) 010 CAN failure 1 CAN failure 0 CAN Bus n.a 1 0 0 0 0 0 Interrupt enabled (1) disabled (0) for CAN failure Interrupt enabled (1) disabled (0) for CAN bus failure Interrupt enabled (1) disabled (0) for LIN failure CAN failure Refer to Table 17 CAN bus failure detected (1) LIN failure. Refer to Table 17 1) A value of 0 will set the SBC into the opposite state. Data Sheet C LINx failure 1 LINx failure 0 on 1 n.a 1 de 0 0 0 Interrupt enabled (1) disabled (0) for reset information (only in SBC Software Development Mode) Interrupt enabled (1) disabled (0) for incorrect Watchdog setting Interrupt enabled (1) disabled Under voltage detected at Vcc2 (0) for undervoltage detection at Interrupt enable (1) disabled (0) Over current detected at Vcc3 for over current at Vcc3 l OTP_Vcc1µC 0 Interrupt enabled (1) disabled Vcc1µC temperature pre warning (0) for temperature pre-warning (1) HS CAN temperature shutdown (1) Vcc2 temperature shutdown (1) Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15.5.2.3 Table 17 0 0 1 1 CAN / LIN failure encoder CAN / LIN Failure Encoder 0 1 0 1 No failure RxD shorted to Vcc TxD shorted to RxD Table 17 describes the encoding of the possible internal CAN and LIN failures. CAN / LINx 1 Failure CAN / LINx 0 Failure Fault 15.5.2.4 Configuration encoder Table 18 Configuration Encoder Configuration Bit Name Select Default Default Value Value (INPUT) (OUT) 01 0 01 0 100 RT10 Reset delay de 1 1 1 0 0 0 0 0 0 1 1 Configuration select 100 (SBC Configuration Register) Reset threshold setting. Please refer to Table 19 Long reset window Vcc3 ON /OFF Vcc2 On / Off LH ON / OFF WK pin ON / OFF 1 fi Cyclic WK On / Off WD to LH on Data Sheet C nt State 78 Table 18 lists the configuration register of the SBC. The microcontroller can change the settings. If no settings are changed the default values are used. The current value can be read on the SPI Data Out. ia Vcc3 is activated (1) The wake pin will wake the SBC Vcc2 is activated (1) Limp Home output state. Activated (1) when entry condition is met. Activation (1) of the cyclic wake Watchdog failure to Limp Home active. 0 = only one Watchdog failure brings to Limp Home activated. 1 = two consecutive Watchdog failures bring to Limp Home activated. l TxD shorted to GND or bus dominant clamped Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Table 18 Configuration Encoder Default Default Value Value (INPUT) (OUT) 1 00 1 00 State Serial Peripheral Interface Configuration Bit Name Select Configuration select 101 (SBC communication set up register) 101 LIN 10.4k CAN 1.0 LIN cells are in LIN Low slope Mode (1) The CAN cell is in: 00 = CAN OFF 01 = CAN is Wake Capable 10 = CAN Receive Only Mode 11 = CAN Normal Mode LINx 1.0 00 00 Configuration select 110 (SBC Watchdog register) 110 Ti. Out / Win. Set to 1 WD ON / OFF CHK SUM 1 1 1 1 1 1 de 1 1 nt 79 Configuration select 111 (Limp Home / Diagnosis register) 111 Reserved for input For output, refer to Table 21, Table 22 and Table 23 15.5.2.5 Reset encoder Table 19 lists the three possible reset thresholds. Please also refer to Chapter 11.3 to get the exact voltage threshold. Table 19 RT1 0 0 1 1 15.5.2.6 Table 20 list the 32 possible watchdog timer. Data Sheet C Reset Encoder Threshold Selected Not Valid. Device remains at previous threshold VRT1 (default setting at SBC Init), VRT2 VRT3 RT0 0 1 0 1 SBC Watchdog encoder on fi ia The LIN cell is in: 00 = LIN OFF 01 = LIN is Wake Capable 10 = LIN Receive Only Mode 11 = LIN Normal Mode Time-out Watchdog is activated Bit is reserved and fix set to “1”. Set to 1 in SW. Watchdog is activated Check sum of the bit 13...6 In case the CHK SUM is wrong, the device remains in previous valid state. CHKSUM = Bit13 ⊕ … ⊕ Bit6 l Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface Table 20 Bit 10...6 00000 00001 00010 ... 01111 10000 10001 ... 11110 11111 Watchdog Encoder Decimal calculation (ms) 0 1 2 ... 15 16 17 ... 30 31 n × 48 - 464 (n+1) × 16 n = decimal value of setting Timer (ms) 16 32 48 ... 304 352 ... 976 1024 256 (default setting) 15.5.3 SBC Diagnostic encoder The SBC offers diagnostics information. The encoding of the different possible failures are listed in the following table. The description apply only to data output. 15.5.3.1 Reason for restart and reset Reason for reset, without activation of the Limp Home and the way it is encoded are summed up in Table 21. The bits are cleared by reading the register with Read-Only command. When coming from Sleep Mode or Fail Safe Mode the bits are cleared. Table 21 RM1 0 0 1 1 Reason to Enter SBC Restart Mode without Limp HomeLimp Home activation RM0 0 1 0 1 Cause for entering SBC Restart Mode No reset has occurred or Limp Home activated Undervoltage on Vcc1µC First Watchdog failure (config 3 and 4) or no acknowledge of the Cyclic Wake-up SPI command in SBC Software Flash Mode or reset low from outside Data Sheet C on fi de nt 80 ia Rev. 1.0, 2009-03-31 l TLE8263-2E Confidential Serial Peripheral Interface 15.5.3.2 Limp Home failure encoder Table 22 describes the encoding of all possible reason to activate automatically the Limp Home output. Bits are set back to “000” when switching Limp Home off via SPI. Table 22 LH2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Limp Home Failure Diagnosis 0 1 0 1 0 1 0 1 No failure One Watchdog failure (config 1 and 2) INIT Mode Time-out Reset clamped Reserved Two consecutive Watchdog failures (config 3 and 4) Temperature shutdown at Vcc1µC 15.5.3.3 Test pin and failure to Limp Home configuration read out Table 23 Test2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Test pin and SBC Configuration Test1 Test0 0 1 0 1 0 1 0 1 Test Read Out1) Vcc1µC remains ON in SBC Restart Mode after one Watchdog failure (config 1) Vcc1µC is OFF in SBC Fail-Safe Mode after one Watchdog failure (config 2) Vcc1µC remains ON in SBC Restart Mode after two Watchdog failures (config 3) Vcc1µC is OFF in SBC Fail-Safe Mode after two Watchdog failures (config 4) Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no reset is generated and Restart Mode or Fail-Safe Mode are not entered. Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no reset is generated and Restart Mode or Fail-Safe Mode are not entered. Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no reset is generated and Restart Mode or Fail-Safe Mode are not entered. Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no reset is generated and Restart Mode or Fail-Safe Mode are not entered. 1) Refer also to Chapter 4.2.1 Data Sheet C on fi de The SBC allows to read the hardware setting of the configuration that is done via the INT pin, as well as the test pin and the WD to LH bit. Table 23 describes the encoding of these informations. nt 81 ia Vcc1µC undervoltage Time-out l Rev. 1.0, 2009-03-31 LH1 LH0 Failure1) TLE8263-2E Confidential Serial Peripheral Interface 15.6 15.6.1 SPI Output Data First SPI output data Since the SPI output data is sent when the SBC is receiving data, the output data are dependent of the previous SPI command, if no Read Only command is used. Under some conditions there is no “previous command”. Table 24 gives the first SPI output data that is sent to the microcontroller when entering SBC Normal Mode, depending on the mode where the SBC was before receiving the first SPI command. . Table 24 Sleep mode First SPI output data frame Previous SBC mode Fail-Safe mode Restart mode when failure and config 1 / 3 Restart mode when microcontroller has sent to Restart mode SBC Init mode Mode selection bits (MS2...0) Configuration select (CS 2..0) Sleep mode Wake Register interrupt1) Limp Home register1) Limp Home register1) SBC Configuration Register SBC Configuration Register Data Sheet C on fi 82 de 1) This does not clear the bits. It will be reset when the microcontroller requests the read out nt Restart mode Restart mode Init mode Fail-Safe mode ia l Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15.6.2 Read Only command In the Mode Selection Bits a Read Only can be selected. The Read Only access clears the INT bits that are selected in the Configuration Select (some interrupt bits show a state, and can not be cleared with a SPI read). With this SPI command no write access is done to the SBC, and the mode of the SBC is not changed. The watchdog can also be triggered with a Read Only command. The Read Only command delivers the information requested with the Configuration Select in the same SPI command on the SDO pin. As all other SPI commands deliver the requested information with the next SPI command. Figure 39 shows an example of a Read Only access. The bits are shown with LSB first, on the left side in difference to the register description. DI DI 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 ia 0 MS0 1 MS1 l 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 Mode Selection Bits nt WD refresh Configuration Select Configuration Registers x x x x x x x x Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WD refresh 1 1 1 0 0 0 x x 1 1 0 1 1 1 x 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 de 10 11 12 13 14 15 DO DO 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 Mode Selection Bits Configuration Select Configuration Registers x x x x x x x WK state Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WK state 1 1 0 0 0 0 x x x 1 1 0 1 0 0 x TIME Figure 40 shows an example of an SPI write access in normal mode for comparison. The requested information is sent out with the next SPI command. DI on 3 4 5 6 7 8 9 fi Figure 39 Read Only Command 0 MS0 1 MS1 2 10 11 12 13 14 15 DI 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 MS2 CS0 CS1 CS2 Mode Selection Bits Configuration Select Configuration Registers x x x x x x x WD refresh Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WD refresh 1 1 0 0 0 0 x x x 1 1 0 1 1 1 x DO C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DO 0 MS0 1 MS1 2 MS2 3 CS0 4 CS1 5 CS2 6 7 8 9 10 11 12 13 14 15 MS0 MS1 MS2 CS0 CS1 CS2 Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WK state Mode Selection Bits Configuration Select Configuration Registers x x x x x x x x x WK state 1 1 0 1 0 0 x 1 1 0 0 0 0 x TIME Figure 40 Write Command Data Sheet 83 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15.7 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Min. SPI Interface; Logic Inputs SDI, CLK and CSN 15.7.1 15.7.2 15.7.3 15.7.4 15.7.5 15.7.6 H-input Voltage Threshold VIH L-input Voltage Threshold VIL Hysteresis of input Voltage Pull-up Resistance at pin CSN Pull-down Resistance at pin SDI and CLK Input Capacitance at pin CSN, SDI or CLK H-output Voltage Level L-output Voltage Level – 0.3 x – – Limit Values Typ. Max. Unit Test Condition l 0.7 x – V – – –1) ia 0.12 x VCC1µC V V kΩ kΩ pF VCC1µC VIHY RICSN 20 VCC1µC RICLK/SDI 20 CI – nt 40 10 0.4 0.2 0.2 – 10 – -10 – 250 125 125 125 250 250 125 100 50 – – – – – – – – – 84 40 80 80 - VCSN = 0.7 × VCC1µC VSDI/CLK = 0.2 × VCC1µC -1) Logic Output SDO 15.7.7 15.7.8 15.7.9 15.7.10 de VSDOH VSDOL CSDO tpCLK tCLKH tCLKL tbef tlead tlag tDISU tDIHO VCC1µC - VCC1µC - – 0.4 10 15 V V µA pF IDOH = -1.6 mA IDOL = 1.6 mA VCSN = VCC1µC; 0 V < VDO < VCC1 1) Tri-state Input Capacitance Clock Period Data Input Timing1) 15.7.11 15.7.12 15.7.13 15.7.14 15.7.15 15.7.16 15.7.17 15.7.18 15.7.19 on fi Tri-state Leakage Current ISDOLK – – – – – – – – – ns ns ns ns ns ns ns ns ns – – – – – – – – – Clock High Time Clock Low Time Data Sheet C Clock Low before CSN Low CSN Setup Time CLK Setup Time Clock Low after CSN High tbeh SDI Set-up Time SDI Hold Time Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Serial Peripheral Interface 15.7 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. 15.7.20 15.7.21 15.7.22 Parameter Input Signal Rise Time at pin SDI, CLK and CSN Input Signal Fall Time at pin SDI, CLK and CSN Delay Time for Mode Change from Normal Mode to Sleep Mode CSN High Time SDO Rise Time SDO Fall Time SDO Enable Time SDO Disable Time SDO Valid Time Symbol Min. Limit Values Typ. – – – Max. – – – 50 50 10 Unit ns ns µs Test Condition – – – tfIN Data Output Timing 1) 15.7.24 15.7.25 15.7.26 15.7.27 15.7.28 de – – trSDO tfSDO tENSDO tDISSDO tVASDO nt – – – 30 30 – – – 15.7.23 tCSN(high) 10 ia – – 80 80 50 50 60 13 19 tfIN l µs ns ns ns ns ns MSB MSB trIN CL = 100 pF CL = 100 pF low impedance high impedance CL = 100 pF 1) Not subject to production test; specified by design CSN 14 CLK DI 15 fi 23 12 16 17 on not defined 26 18 LSB 28 LSB 27 DO Flag Figure 41 Note: Numbers in drawing correlate to the last 2 digits of the Pos. number in the Electrical Characteristics table. Data Sheet C SPI Timing Diagram 85 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Application Information 16 Application Information Note: The following information is given only as a hint for the implementation of the device and should not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VDD VBAT VBAT T1 C3 D1 C1 R1 l ia C 12 C13 V CC3ref Vcc1µC C9 CSN CLK SDO SDI TxD LIN 1 RxD LIN 1 TxD LIN2 RxD LIN2 TxD CAN RxD CAN INT RO V DD VCC2 R 10 V CCHSCAN C 11 VS Limp Home T2 VS LH_SI LH_PL/Test T3 VS S2 T4 VS VIO VCC IC2 C2 GND VS D2 VCC IC3 GND R2 BUS1 C4 VS D3 R3 BUS2 C5 Bus 1 VS V CC3shunt VS nt V CC3base LOGIC State Machine DEVICE GROUND V DD C10 R 12 de Bus 2 VS WK CAN cell TLE8263-2 fi CSN V DD CLK SDI µC SDO TxD LIN 1 RxD LIN1 TxD LIN 2 RxD LIN2 VBAT TxD CAN RxD CAN INT Reset VSS on WK S1 R9 VBAT C 14 VDD VBB CS SCLK SI SO LHI IN0 IN1 IN2 IN3 IN4 IN5 R5 C7 C CANH R7 C8 R8 CANH SPLIT IC1 CANL CANL GND D5 GND Application _information _TLE8263 -2E.vsd Figure 42 Application Example for a Body Controller Module Data Sheet 86 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Application Information Note: This is a very simplified example of an application circuit and bill of material. The function must be verified in the actual application. Table 25 Ref. C1 C2 C3 C4 C5 C7 C8 C9 C10 C11 C12 C13 C14 R1 R2 R3 R5 R7 R8 R9 R10 R12 Bills of material Option Vendor Y Kemet Y N N N Y Y Y N N Y Y Y N Y Y Y Y Y Y Y Y Murata Value 68µF optional depending on application 100nF 1nF OEM dependent 1nF OEM dependent 22nF 50V 10µF 100nF 47nF OEM dependent 10µF ceramic cap low ESR Purpose Capacitance nt 87 de 10µF CAN transceiver dependent 100nF 100nF 100nF Resistance fi on 1kΩ 10kΩ 500Ω 47kΩ 220mΩ 1kΩ / OEM dependent 1kΩ / OEM dependent 60Ω / OEM dependent 60Ω / OEM dependent Data Sheet C ia l EMC EMC Cut off battery spike Stability of the VCC3 LIN Master Termination LIN Master Termination Improve SPLIT pin stability Buffer of the VCC1µC depending on load. (µC) Stability of the VCC1µC Buffering of the VCC2 for CAN Transceiver Improve stability of the logic Improve stability of the logic Improve stability of the logic VCC3 current measurement for ICC3 400mA max LIN master termination LIN master termination Wetting current of the switch CAN bus termination CAN bus termination Limit the WK pin current in ISO pulses Insulation of the VDD supply Set config 1/3. If not connected config 2/4 is selected Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Table 25 Ref. T1 Bills of material Option Vendor N ON Semi Infineon T2 T3 T4 D1 D2 D3 µC IC1 IC2 IC3 N N N N N N N Y Y Y Infineon Infineon Infineon Infineon Infineon Infineon Infineon Infineon Infineon Infineon Value MJD253 BCP52-16 BCR191W BCR191W BCR191W BAS 3010A BAS70 06 (dual) BAS70 (single) BAS70 06 (dual) BAS70 (single) XC2xxx TLE 6254-3G TLE 6251DS Purpose Power element of VCC3 Alternative power element of VCC3, current limit to be adapted R1 to be changed. Application Information Active components nt 88 SPOC - BTS5672E de Data Sheet C on fi ia l High active Limp Home High active Limp Home High active Limp Home Reverse polarity protection Requested by LIN norm. Protect the application in reverse polarity. Requested by LIN norm. Protect the application in reverse polarity. micro-controller high side switches Low speed CAN High speed CAN Rev. 1.0, 2009-03-31 TLE8263-2E Confidential 16.1 ZthJA Curve Application Information 60 50 Zth-JA(Ch4; 300) Zth-JA(Ch4; 100) Zth-JA(Ch4; footprint) 40 Zth-JA [K/W] 30 20 10 0 0,00001 0,0001 0,001 de 0,01 0,1 nt 1 10 100 1000 ia 10000 tim e (s) Zthja curves.vsd Figure 43 ZthJA Curve, Function of Cooling Area C on fi 600mm² cooling area 300mm² cooling area 100mm² cooling area l minimum footprint PCB set up.vsd Zth-JA(Ch4; 600) Figure 44 Board Set-up Board set-up is done according to JESD 51-3, single layer FR4 PCB 70 µm. Data Sheet 89 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Application Information 16.2 Hints for SBC Factory Flash Mode The mode is used during production of the module to flash the µC. The idea is that the µC is not supplied from the SBC but from an external 5V power supply. The reset of the µC that is connected to the RO pin of the SBC can be driven from an external source and the SBC does not give a reset signal. Also no interrupt at the pin INT and no signal on the SPI SDO pin is generated by the SBC. The SPI pins can be driven externally. The mode is reached by applying 5V to the VCC1µC pin and no voltage to the Vs pin. The Vs pin will show a voltage of about 4.5V because of the internal diode from VCC1µC to Vs. The current drawn at Vs must not exceed the maximum rating of Ivs,max = -500mA. The function is designed for ambient temperature. In case the Vs was supplied before going to FF Mode, the voltage on pin Vs must be set below 3 V before applying 5V to VCC1µC (discharging the C) nt VCC1µC Internal supply Not supplied Not supplied VBAT C Vs IVS de ia 5V INT RO l Reset signal The current flowing to other devices from Vs should be limited to not exceed the maximum ratings. Other Devices on CSN CLK SDO SDI TxD LIN1 RxD LIN1 TxD LIN2 RxD LIN2 TxD LIN3 RxD LIN3 TxD CAN RxD CAN CSN V DD CLK SDI µC SDO TxD LIN1 RxD LIN1 TxD LIN2 RxD LIN2 TxD LIN3 RxD LIN3 TxD CAN RxD CAN INT Reset V SS C fi Application_ FF_Mode _2.vsd Figure 45 Application Hint for Factor Flash Mode Data Sheet 90 Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Application Information Table 26 Pin Vs Vcc1µC RO INT LH SDO CLK, SDI CSN PIN in Factory Flash Mode Level typ. 4.5V 5V ± 2% Pull-up resistor Pull-up resistor High impedance High impedance Pull-down resistor Pull-up resistor Pull-up resistor High impedance Comment Voltage output from SBC. No voltage applied from external. To be applied from external Can be driven from external Can be driven from external if required RxDCAN, RxDLIN1, RxDLIN2, RxDLIN3 Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) have been performed. The results and test condition is available in a test report. The values for the test are listed in Table 27 below. Table 27 ESD “Gun test” >8 Performed Test ESD at pin CANH, CANL, BUSx, Vs versus GND ESD at pin CANH, CANL, BUSx, Vs versus GND Result de 16.3 ESD Tests nt Unit TxDCAN, TxDLIN1, TxDLIN2, TxDLIN3 ia kV kV 91 Can be driven from external if required Can be driven from external if required Can be driven from external if required Can be driven from external if required Can be driven from external if required Can be driven from external if required l Remarks positive pulse1) fi < -8 negative pulse 1) ESD susceptibility “ESD GUN” contact discharge (R=330Ohm C=150pF) (DIN EN 61000-4-2) tested according LIN EMC 1.3 Test Specification and ICT EMC Evaluation of CAN Transceiver. Tested by external test house (IBEE Zwickau, EMC Test report Nr. 06-02-09a) Data Sheet C on Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Package Outline 17 Package Outline 0...0.10 STAND OFF 2.45 -0.2 2.55 MAX. 3) 0.35 x 45˚ 1.1 0.65 C 17 x 0.65 = 11.05 0.33 ±0.08 2) 0.1 C 36x SEATING PLANE ia 10.3 ±0.3 Bottom View 19 36 0.17 M A-B C D 36x A 19 36 Ejector Mark Cavity ID nt Y 18 1 18 B 12.8 -0.21) Index Marking Ejector Mark Polish Finish Exposed Diepad Dimensions 4) Leadframe X Y Package PG-DSO-36-24, -41, -42 A6901-C001 7 5.1 A6901-C003 7 5.1 PG-DSO-36-38 A6901-C007 5.2 4.6 PG-DSO-36-38 PG-DSO-36-24 A6901-C008 6.0 5.4 on 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side 3) Distance from leads bottom (= seating plane) to exposed diepad 4) Exclunding the mold flash allowance of 0.3mm MAX per side PG-DSO-36-24, -38, -41, -42-PO V08 Figure 46 PG-DSO-36-38 (Leadframe A6901-003);) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations, the Universal System Basis Chip is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD020). For information about packages and types of packing, refer to the Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 92 C Note: For the SBC product family the package PG-DSO-36-38 with the leadframe A6901-C003 is used. fi de l 0.7 ±0.2 D X 1 Exposed Diepad Index Marking 8˚ MAX. 7.6 -0.2 1) 0.23 +0.09 Dimensions in mm Rev. 1.0, 2009-03-31 TLE8263-2E Confidential Revision History 18 Version 1.0 1.0 Revision History Date 2009-02-06 2009-03-31 Parameter Changes First Rev. after Preliminary Data Sheet Editorial changes Data Sheet C on fi 93 de nt Rev. 1.0, 2009-03-31 ia l Edition 2009-03-31 Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. C on Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. fi de nt ia l