TLI5012

March 2009 TLI5012 GMR-Based Angular Sensor for Rotary Switches Target D ata Sheet V 0.41 Sensors Edition 2009-03 Published by Infineon Technologies AG 81726 München, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TLI5012 TLI5012 GMR-Based Angular Sensor Revision History: 2009-03, V 0.41 Previous Version: V0.4 Page general gerneral 7 12 14 15 16 18 19 20 42 Subjects (major changes since last revision) Correction of typing errors Name of product type changed Marking and Ordering Code added Figure 4 updated Figure 5 and figure 6 updated Magnetic Induction reduced in Table 3; Storage Temperature reduced in Table 2; Note added Calculation of the Junction Temperature added Figure 7 updated Angle Delay Time with Prediction in Table 7 added; Figure 8 updated Figure 9 and Figure 10 updated Table 14, Thermal resistance added We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com Target Data Sheet 3 V 0.41, 2009-03 TLI5012 1 1.1 1.2 1.3 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.1 3.5.1.1 3.5.1.2 3.5.1.3 3.5.1.3.1 3.5.2 4 4.1 4.2 4.3 4.4 4.5 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 8 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SD-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Digital Signal Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Communication (SSC) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLI5012 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 15 17 17 17 18 18 20 20 21 22 25 26 40 42 42 42 43 43 43 Target Data Sheet 4 V 0.41, 2009-03 TLI5012 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Sensitive Bridges of the GMR Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ideal Output of the GMR Sensor Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TLI5012 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application Circuit for TLI5012 with SSC and PWM Interface (using internal CLK) . . . . . . . . . . . . 14 Application Circuit for TLI5012 with only PWM Interface (using internal CLK) . . . . . . . . . . . . . . . . 14 TLI5012 Signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Delay of Sensor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SSC Configuration in Sensor-Slave Mode with Push-Pull Outputs (High Speed Application) . . . . 20 SSC Configuration in Sensor-Slave Mode and Open Drain (Safe Bus Systems) . . . . . . . . . . . . . 20 SSC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SSC Data Transfer (Data Read Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SSC Data Transfer (Data Write Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SSC Bit Ordering (Read Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fast CRC Polynomial Division Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical Example for a PWM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PG-DSO-8 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Footprint PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Target Data Sheet 5 V 0.41, 2009-03 TLI5012 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Push-Pull Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Open Drain Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Command Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Safety Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 15 15 17 17 18 18 21 21 23 23 25 41 42 Target Data Sheet 6 V 0.41, 2009-03 TLI5012 1 1.1 Product Description Overview The TLI5012 is a 360° angle sensor that detects the orientation of a magnetic field. This is achieved by measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR) elements. An angle error smaller than 5° will be achieved over temperature. Data communications are accomplished with a bi-directional SSC Interface that is SPI compatible. The absolute angle value and other values are transmitted via SSC or via a Pulse-Width-Modulation (PWM) Protocol. Also the sine and cosine raw values can be read out. These raw signals are digitally processed internally to calculate the angle orientation of the magnetic field (magnet). The TLI5012 is a precalibrated sensor. The calibration parameters are stored in laser fuses. At start-up the values of the fuses are written into Flip-Flops, where these values can be changed by the application specific parameters. Product Type TLI5012 Target Data Sheet Marking I5012 7 Ordering Code SP000634318 Package PG-DSO-8 V 0.41, 2009-03 TLI5012 Product Description 1.2 • • • • • • • • • • • Features Giant Magneto Resistance (GMR)-based principle Integrated magnetic field sensing for angle measurement Full calibrated 0 - 360° angle measurement with revolution counter and angle speed measurement Two separate highly accurate single bit SD-ADC 15 bit representation of absolute angle value on the output (resolution of 0.01°) Bi-directional SSC Interface up to 8Mbit/s Interfaces: SSC, PWM 0.25 µm CMOS technology Temperature range: -40°C to 125°C (Junction Temperature) ESD > 2kV (HBM) Green package with lead-free (Pb-free) plating 1.3 Application Example The TLI5012 GMR-Based Angular Sensor is designed for angular position sensing in industrial applications, such as: • • Rotary Switch General Angular Sensing Target Data Sheet 8 V 0.41, 2009-03 TLI5012 Functional Description 2 2.1 Functional Description General The GMR sensor is implemented using vertical integration. This means that the GMR sensitive areas are integrated above the logic portion of the TLI5012 device. These GMR elements change their resistance depending on the direction of the magnetic field. Four individual GMR elements are connected to one Wheatstone Sensor Bridge. These GMR elements sense one of two components of the applied magnetic field: • • X component, Vx (cosine) or the Y component, Vy (sine) The advantage of a full-bridge structure is that the amplitude of the GMR signal is doubled and temperature effects cancel out each other. GMR Resistors 90° S 0° VX VY N ADCX + ADCX - GND ADCY+ ADCY- VDD Figure 1 Sensitive Bridges of the GMR Sensor Note: In Figure 1, the arrows in the resistors symbolize the direction of the Reference Layer, which is used for the further explanation. The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are orientated orthogonally to each other to measure 360°. With the trigonometric function ARCTAN, the true 360° angle value can be calulated which is represented by the relation of X and Y signals. Because only the relative values influence the result, the absolute size of the two signals is of minor importance. Therefore, most influences to the amplitudes are compensated. Target Data Sheet 9 V 0.41, 2009-03 TLI5012 Functional Description Y Component (SIN) VY VX V VX (COS) X Component (COS) 0° 90° 180° 270° 360° Angle α VY (SIN) Figure 2 Ideal Output of the GMR Sensor Bridges Target Data Sheet 10 V 0.41, 2009-03 TLI5012 Functional Description 2.2 Pin Configuration 8 7 6 5 Center of Sensitive Area 1 Figure 3 2 3 4 Pin Configuration (Top View) 2.3 Pin Description Table 1 Pin No. 1 Pin Description Symbol CLK In/Out I Function External Clock (must be connected to GND for PWM output) SSC Clock SSC Chip Select SSC Data Interface A: PWM Supply Voltage Ground Interface B: could be remain open or connected via resistor to GND 2 3 4 5 6 7 8 SCK CSQ DATA IFA PWM VDD GND IFB I I I/O O O Target Data Sheet 11 V 0.41, 2009-03 TLI5012 Functional Description 2.4 Block Diagram TLI5012 Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Y GMR SDADC SDADC CCU Cordic Fuses PWM SSC Interface VDD CLK CSQ SCK DATA Temp IFA IFB GND Figure 4 TLI5012 Block Diagram 2.5 Functional Block Description 2.5.1 • • • Internal Power Supply The internal stages of the TLI5012 are supplied with different voltage regulators. GMR Voltage Regulator VRG Analog Voltage Regulator VRA Digital Voltage Regulator VRD (derived from VRA) These regulators are directly connected to the supply voltage VDD. 2.5.2 Oscillator and PLL The internal frequency oscillator feeds the Phase Locked Loop (PLL). Also the external clock (CLK) can be used therefore. 2.5.3 SD-ADC The SD-ADCs transform the analog GMR-voltages and temperature-voltage into the digital domain. Target Data Sheet 12 V 0.41, 2009-03 TLI5012 Functional Description 2.5.4 • • • Digital Signal Processing Unit The Digital Signal Processing Unit (DSPU) contains the: Capture Compare Unit (CCU), which is used to generate the PWM signal COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle calculation Fuses, which contain the calibration parameters 2.5.5 • • Interfaces Different Interfaces can be selected: SSC Interface PWM Target Data Sheet 13 V 0.41, 2009-03 TLI5012 Specification 3 3.1 Specification Application Circuit The application circuit in Figure 5 and Figure 6 show the different communication possibilities of TLI5012. TLI5012 Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Y GMR SDADC SDADC CCU Cordic Temp Fuses PWM IFB 10 kΩ IFB could be remain open or connected via 10 kΩ r esistor to GND. IFA (PWM) PWM SSC Interface CSQ CLK 100n 1 kΩ 1 kΩ VDD (3.0 – 5.5V) SCK *) SSC DATA GND * recommended , e.g. 470 Ω Figure 5 Application Circuit for TLI5012 with SSC and PWM Interface (using internal CLK) Figure 5 shows a basic block-diagram of the TLI5012 with PWM- Interface. This interface is selectable by connecting CLK to GND. Additionally to the PWM the SSC Interface could be used. Within the SSC- Interface the PWM mode is selectable between Push-Pull and Open Drain. TLI5012 Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Y GMR SDADC SD ADC CCU Cordic Temp Fuses PWM IFB 10 kΩ IFA (PWM) SSC Interface CSQ CLK 100 n 1 kΩ VDD (3.0 – 5.5V) SCK 10 kΩ DATA DATA and IFB could be remain open or connected via 10 kΩ r esistor to GND . GND Figure 6 Application Circuit for TLI5012 with only PWM Interface (using internal CLK) 14 V 0.41, 2009-03 Target Data Sheet TLI5012 Specification 3.2 Absolute Maximum Ratings Table 2 Parameter Absolute Maximum Ratings Symbol Min. VDD VIN TJ B TST -0.5 -0.5 -40 -40 Values Typ. Max. 6.5 6.5 125 125 125 100 Unit Note / Test Condition V V °C °C mT °C for 3000h not additive max. 5 min @ tA = 25°C max. 5 h @ tA = 25°C max 40 h/Lifetime additionally VDD + 0.5 V may not be exceeded Voltage on VDD pin respect to ground (VSS) Voltage on any pin respect to ground (VSS) Junction Temperature Magnetic Field Induction Storage Temperature 125 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the device. 3.3 Operating Range The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 3 Parameter Supply Voltage Output Current (DATA-Pad) Operating Range Symbol Min. VDD IQ 3.0 Output Current (IFA / IFB-Pad) Input Voltage Magnetic Induction Angle Range IQ VIN BXY Ang -0.3 30 0 Values Typ. 5.0 Max. 5.5 -25 -5 -0.4 -15 -5 5.5 50 360 V mT ° mA V mA 1) Unit Note / Test Condition PAD_DRV =’0x’, sink current2) PAD_DRV =’10’, sink current2) PAD_DRV =’11’, sink current2) PAD_DRV =’0x’, sink current2) PAD_DRV =’1x’, sink current2) VDD + 0.3 V may not be exceeded in X/Y direction3) 1) Directly blocked with 100nF ceramic capacitor 2) Max. current to GND over Open Drain Output 3) Values refer to an homogenous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT). Note: The thermal resistances listed in Table 14 “Package Parameters” on Page 42 must be used to calculate the corresponding ambient temperature. Table 3 is valid for -40°C < TJ < 125°C. Target Data Sheet 15 V 0.41, 2009-03 TLI5012 Specification Calculation of the Junction Temperature The total power dissipation PTOT of the chip increases its temperature above the ambient temperature. The power multiplied by the total thermal resistance RthJA (Junction to Ambient) leads to the final junction temperature. RthJA is the sum of the addition of the values of the two components Junction to Case and Case to Ambient. RthJA = RthJC + RthCA TJ = TA + ∆T ∆T = RthJA × PTOT = RthJA × (VDD × I DD + VOUT × I OUT Example (assuming no load on Vout): (1) (IDD, IOUT > 0, if direction is into IC) VDD = 5V I DD = 12mA K  ∆T = 150  × 5[V ]× 0.012[A] + 0[VA] = 9 K W  For moulded sensors, the calculation with RthJC is more adequate. (2) Target Data Sheet 16 V 0.41, 2009-03 TLI5012 Specification 3.4 Characteristics 3.4.1 Electrical Parameters The indicated electrical parameters apply to the full operating range, unless otherwise specified. The typical values correspond to a supply voltage VDD = 5.0 V and 25 °C, unless individually specified. All other values correspond to -40 °C < TJ < 125°C. Table 4 Parameter Supply Current POR Level POR Hysteresis Power On Time Input Signal Low Level Input Signal High Level Pull-Up Current Pull-Down Current Output Signal Low Level Electrical Parameters Symbol Min. IDD VPOR VPORhy tPon VL VH IPU IPD VOL 2.0 -10 -10 10 10 Values Typ. 12 30 4 Max. 13 2.9 5 0.3 VDD -225 -150 225 150 1 µA µA V mA V mV ms V V µA CSQ DATA SCK CLK, IFA, IFB DATA; IQ = - 25 mA (PAD_DRV=’0x’), IQ = - 5 mA (PAD_DRV=’10’), IQ = - 0.4 mA (PAD_DRV=’11’) IFA,IFB; IQ = - 15 mA (PAD_DRV=’0x’), IQ = - 5 mA (PAD_DRV=’1x’) VDD > VDDmin1) Power On Reset Unit Note / Test Condition 0.7 VDD - - - 1 1) Within “Power On Time” write access is not permitted 3.4.2 ESD Protection Table 5 Parameter ESD Protection Symbol VHBM VSDM Values min. max. ±2.0 ±0.5 kV kV Human Body Model1) Socketed Device Model2) Unit Notes ESD Voltage 1) Human Body Model (HBM) according to: JEDEC EIA/JESD22-A114-B 2) Socketed Device Model (SDM) according to: ESD ASS.STD.DS5.3-93 Target Data Sheet 17 V 0.41, 2009-03 TLI5012 Specification 3.4.3 Angle Performance After internal calculation the sensor has a remaining error, as shown in Table 6. The error value refers to BZ = 0mT and the operating conditions given in Table 3 “Operating Range” on Page 15. The overall angle error represents the relative angle error. This error describes the deviation to the reference line after zero angle definition. Table 6 Parameter Overall Angle Error Angle Performance Symbol Min. αErr Values Typ. 0.7 1) Unit ° Note / Test Condition including temperature drift2)3) Max. 5.0 - 1) At 25°C, B =30 mT 2) Including hysteresis error, caused by revolution direction change. 3) With magnetic setup in chip production (Fused Calibration Parameters); Relative error after zero angle definition. 3.4.4 Signal Processing The signal path of the TLI5012 is depicted in Figure 7. It consists of the GMR-bridge, ADC, filter and angle calculation. Depending on the filter configuration a different total delay time is achieved. Additional to this delay time, the delay time of the interface has to be considered. The delay time leads to an additional angle error at higher speeds. With enabling the prediction, the signal delay time will be reduced (Figure 8). TLI5012 Microcontroller tupd X GMR SDADC Filter Angle Calculation Y GMR SDADC Filter IF tdel Figure 7 TLI5012 Signal path tdelIF At FIR_MD = 0 only raw values can be read out, due to the more time consuming angle calculation. Table 7 Parameter Update Rate at Interface Signal Processing Symbol Min. tupd Values Typ. 21.3 42.7 85.3 170.6 Max. µs FIR_MD = 0 (only raw values)1)2) FIR_MD = 11)2) FIR_MD = 2 (default)1)2) FIR_MD = 31)2) Unit Note / Test Condition Target Data Sheet 18 V 0.41, 2009-03 TLI5012 Specification Table 7 Parameter Angle Delay Time 3) Signal Processing Symbol Min. tdel Values Typ. 60 80 120 20 5 -40 0.11 0.08 0.05 0.04 Max. 70 95 140 30 20 -20 ° µs µs FIR_MD = 11)2) FIR_MD = 21)2) FIR_MD = 31)2) FIR_MD = 1; PREDICT = 1 1)2) Unit Note / Test Condition Angle Delay Time with Prediction3) tdel - FIR_MD = 2; PREDICT = 1 1)2) FIR_MD = 3; PREDICT = 1 1)2) Angle Noise NAngle - FIR_MD = 0, (1 Sigma)2) FIR_MD = 1, (1 Sigma)2) FIR_MD = 2, (1 Sigma)2) (default) FIR_MD = 3, (1 Sigma)2) 1) depends on internal oscillator frequency variation 2) guaranteed by laboratory characterization 3) valid at constant rotation speed Angle Magnetic field direction With Prediction Without Prediction tdel Figure 8 Delay of Sensor Output tupd time Target Data Sheet 19 V 0.41, 2009-03 TLI5012 Specification 3.5 Interfaces 3.5.1 Synchronous Serial Communication (SSC) Interface The 3-pin SSC Interface has a bi-directional push-pull data line, serial clock signal and chip select. The SSC Interface is designed to communicate with a microcontroller pear to pear for fast applications. SSC Communication for pear to pear Data Transmission between TLI5012 and µC (SSC Slave) TLI5012 **) MRST µC (SSC Master) Shift Reg. EN DATA Shift Reg. EN MTSR SCK *) SCK Clock Gen. CSQ *) CSQ *) opional , e.g. 100 Ω **) opional , e.g. ≥ 470 Ω Figure 9 SSC Configuration in Sensor-Slave Mode with Push-Pull Outputs (High Speed Application) Another possibility is a 3-pin SSC Interface with bidirectional open-drain data line, serial clock signal and chip select. This setup is designed to communicate with a microcontroller in a bus system, together with other SSC slaves (e.g. two TLI5012 for redundancy reasons). This mode can be activated using bit SSC_OD. (SSC Slave) TLI5012 typ. 1kΩ *) *) MRST µC (SSC Master) Shift Reg. DATA Shift Reg. MTSR SCK *) SCK Clock Gen. CSQ *) CSQ *) opional , e.g. 100 Ω Figure 10 SSC Configuration in Sensor-Slave Mode and Open Drain (Safe Bus Systems) 20 V 0.41, 2009-03 Target Data Sheet TLI5012 Specification 3.5.1.1 SSC Timing Definition tCSs tSCKp tCSh tCSoff CSQ tSCKh tSCKl SCK DATA tDATAs tDATAh Figure 11 SSC Timing SSC Inactive Time (CSoff) The SSC inactive time defines the delay time after a transfer before the TLE5012 can be selected again. Table 8 Parameter SSC Baud Rate CSQ Setup Time CSQ Hold Time CSQ off SCK Period SCK High SCK Low DATA Setup Time DATA Hold Time Write Read Delay Table 9 Parameter SSC Baud Rate CSQ Setup Time CSQ Hold Time CSQ off SCK Period SCK High SSC Push-Pull Timing Specification Symbol Min. fSSC tCSs tCSh tCSoff tSCKp tSCKh tSCKl tDATAs tDATAh twr_delay 105 105 600 120 40 30 25 40 130 Values Typ. 8.0 125 Max. Mbit/s ns ns ns ns ns ns ns ns ns SSC inactive time Unit Note / Test Condition SSC Open Drain Timing Specification Symbol Min. fSSC tCSs tCSh tCSoff tSCKp tSCKh 300 400 600 500 Values Typ. 2.0 190 Max. Mbit/s ns ns ns ns ns SSC inactive time Pull-up Resistor = 1kΩ Unit Note / Test Condition Target Data Sheet 21 V 0.41, 2009-03 TLI5012 Specification Table 9 Parameter SCK Low DATA Setup Time DATA Hold Time Write Read Delay SSC Open Drain Timing Specification (cont’d) Symbol Min. tSCKl tDATAs tDATAh twr_delay 25 40 130 Values Typ. 190 Max. ns ns ns ns Unit Note / Test Condition 3.5.1.2 • • • SSC Data Transfer The SSC data transfer is word aligned. The following transfer words are possible: Command word (to access and change operating modes of the TLI5012) Data words (any data transferred in any direction) Safety word (confirms the data transfer and provide status information) twr_delay COMMAND READ Data 1 READ Data 2 SAFETY-WORD SSC-Master is driving DATA SSC-Slave is driving DAT A Figure 12 SSC Data Transfer (Data Read Example) twr_delay COMMAND WRITE Data 1 SAFETY-WORD SSC-Master is driving DATA SSC-Slave is driving DAT A Figure 13 SSC Data Transfer (Data Write Example) Target Data Sheet 22 V 0.41, 2009-03 TLI5012 Specification Command Word TheTLI5012 is controlled by a command word. It is sent first at every data transmission. Table 10 Name RW Structure of the Command Word Bits [15] Description Read - Write 0:Write 1:Read 4 bit Lock Value 0x00: Default Operating Access 0x02: Config- Access Update-Register Access 0: Access to current values 1: Access to updated values 6 bit Address 4 bit Number of Data-Words Lock [14..11] UPD [10] ADDR ND Safety Word [9..4] [3..0] The safety word contains following bits: Table 11 Name STAT Structure of the Safety Word Bits [15] Description Indication of Chip-Reset (resets after readout) via SSC 0: No reset 1: Reset occurred Reset: 0B System Error (e.g. Overvoltage; Undervoltage; VDD-, GND- off; ROM;...) 0: No error 1: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_ADCM) Interface Access Error (access to wrong address; wrong lock) 0: No error 1: Error occurred Valid Angle Value (no system error; no interface error; NO_GMR_A = ’0’; NO_GMR_XY=’0’) 0: Angle value valid 1: Angle value invalid Sensor Number Response Indicator The sensor no. bit is pulled low and the other bits are high. Cyclic Redundancy Check (CRC) Chip and Interface Status [14] [13] [12] RESP CRC [11..8] [7..0] Target Data Sheet 23 V 0.41, 2009-03 TLI5012 Specification Data Communication via SSC SSC Transfer Command Word SCK DATA CSQ RW LOCK SSC -Master is driving DAT A SSC -Slave is driving DAT A UPD ADDR LENGTH MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB MSB 1 LSB twr_delay Data Word (s) Figure 14 • • • • • • • • • • • • SSC Bit Ordering (Read Example) The data communication via SSC interface has the following characteristic: The data transmission order is “Most Significant Bit (MSB) first”. Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK. The SSC Interface is word-aligned. All functions are activated after each transmitted word. A “high” condition on the negated Chip Select pin (CSQ) of the selected TLE5012 interrupts the transfer immediately. The CRC calculator is automatically reset. After changing the data direction, a delay (twr_delay) has to be considered before continuing the data transfer. This is necessary for internal register access. Every access to the TLI5012 with the number of data (ND) ≥ 1 is performed with address auto-increment. At an overflow at address 3FH the transfer continuous at address 00H. With ND = 0 no auto-increment is done and a continuously readout of the same address can be realized. Afterwards no Safety Word is send and the transfer ends with high condition on CSQ. After every data transfer with ND ≥ 1 the 16 bit Safety Word will be appended by the selected TLI5012. At a rising edge of CSQ without data transfer before (no SCK-pulse), the update-registers are updated with according values. After sending the Safety Word the transfer ends. To start another data transfer, the CSQ has to be deselected once for tCSoff. The SSC is default Push-Pull. The Push-Pull driver is only active, if the TLI5012 has to send data, otherwise the Push-Pull is disabled for receiving data from the microcontroller. Cyclic Redundancy Check (CRC) • • • • • • This CRC is according to the J1850 Bus-Specification. Every new transfer resets the CRC generation. Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)). Generator-Polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used (see Figure 15) The remainder of the fast CRC circuit is initial set to ’11111111B’. Remainder is inverted before transmission. Serial CRC output X7 1 X6 1 X5 1 X4 1 xor X3 1 X2 xor 1 X1 xor 1 X0 1 & xor Input TX_CRC parallel Remainder Figure 15 Fast CRC Polynomial Division Circuit 24 V 0.41, 2009-03 Target Data Sheet TLI5012 Specification 3.5.1.3 Registers Chapter This chapter defines the registers of the TLI5012 . It also defines the read/write access rights of the specific registers. Table 12 identifies the values with symbols. Access to the registers is accomplished via the SSC Interface. Table 12 Registers Overview Register Long Name Status Register Activation Status Register Angle Value Register Angle Speed Register Angle Revolution Register Frame Synchronization Register Interface Mode1 Register SIL Register Interface Mode2 Register Interface Mode3 Register Offset X Offset Y Synchronicity IFAB Register Interface Mode4 Register Temperature Coeffizient Register X-raw value Y-raw value Offset Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H Page Number 26 28 29 30 30 31 32 33 34 35 36 36 37 37 38 39 39 40 Register Short Name STAT ACSTAT AVAL ASPD AREV FSYNC MOD_1 SIL MOD_2 MOD_3 OFFX OFFY SYNCH IFAB MOD_4 TCO_Y ADC_X ADC_Y Registers Chapter, TLI5012 Register The register is addressed wordwise. Target Data Sheet 25 V 0.41, 2009-03 TLI5012 Specification 3.5.1.3.1 TLI5012 Register Status Register STAT Status Register Offset 00H Reset Value 8001H Field RD_ST Bits 15 Type r Description Read Status 0B after readout 1B status values changed Reset: 1B Slave Number Reset: 00B No GMR Angle Value 0B valid GMR angle value on the interface 1B no valid GMR angle value on the interface Reset: 0B No GMR XY Values 0B valid GMR_XY values on the interface 1B no valid GMR_XY values on the interface Reset: 0B Status ROM 0B after readout, CRC ok 1B CRC fail or running Reset: 0B Status ADC-Test 0B after readout 1B Test vectors out of limit Reset: 0B Status Magnitude Out of Limit 0B after readout 1B GMR-magnitude out of limit (>23230 digits) Reset: 0B 26 V 0.41, 2009-03 S_NR NO_GMR_A 14:13 12 r r NO_GMR_XY 11 r S_ROM 10 r S_ADCT 9 r S_MAGOL 7 r Target Data Sheet TLI5012 Specification Field S_XYOL Bits 6 Type r Description Status X,Y Data Out of Limit 0B after readout 1B X,Y data out of limit (>23230 digits) Reset: 0B Status Overflow 0B after readout 1B DSPU overflow occurred Reset: 0B Status Digital Signal Processing Unit 0B after readout 1B DSPU self test not ok, or selftest is running Reset: 0B Status Fuse CRC 0B after readout, Fuse CRC ok 1B Fuse CRC fail Reset: 0B Status Voltage Regulator 0B after readout 1B VDD overvoltage; VDD undervoltage; VDD-off; GNDoff; or VOVG; VOVA; VOVD too high Reset: 0B Status Watchdog 0B after chip reset 1B watchdog counter expired Reset: 0B Status Reset 0B after readout 1B indication of power-up, short power-break or active reset Reset: 1B S_OV 5 r S_DSPU 4 r S_FUSE 3 r S_VR 2 r S_WD 1 r S_RST 0 r Target Data Sheet 27 V 0.41, 2009-03 TLI5012 Specification Activation Status Register ACSTAT Activation Status Register Offset 01H Reset Value 5CEEH Field Res AS_ADCT AS_VEC_MAG Bits 15:10 9 7 Type Description Reserved Reset: 010111B rw rw Enable GMR Vector check Reset: 0B Activation of ADC-Redundancy-BIST 0B after execution 1B activation of redundancy BIST Reset: 1B Activation of ADC-BIST 0B after execution 1B activation of BIST Reset: 1B Enable of DSPU Overflow Check Reset: 1B Activation DSPU BIST 0B after execution 1B activation of DSPU BIST Reset: 0B Activation Fuse CRC 0B after execution 1B activation of Fuse CRC Reset: 1B Enable Voltage Regulator Check Reset: 1B Enable DSPU Watchdog-HW-Reset Reset: 1B AS_VEC_XY 6 rw AS_OV AS_DSPU 5 4 rw rw AS_FUSE 3 rw AS_VR AS_WD 2 1 rw rw Target Data Sheet 28 V 0.41, 2009-03 TLI5012 Specification Field AS_RST Bits 0 Type rw Description Activation of Hardware Reset Activation occurs after CSQ switches from ’0’ to ’1’ after SSC transfer. 0B after execution 1B activation of HW Reset Reset: 0B Angle Value Register AVAL Angle Value Register Offset 02H Reset Value 8000H Field RD_AV Bits 15 Type r Description Read Status, Angle Value 0B after readout 1B new angle value (ANG_VAL) present Reset: 1B Calculated Angle Value (ANG_RANGE = 0x080) 4000H -180° 0000H 0° 3FFFH +179.99° Reset: 0H ANG_VAL 14:0 r Target Data Sheet 29 V 0.41, 2009-03 TLI5012 Specification Angle Speed Register ASPD Angle Speed Register Offset 03H Reset Value 8000H Field RD_AS Bits 15 Type r Description Read Status, Angle Speed 0B after readout 1B new angle speed value (ANG_SPD) present Reset: 1B Calculated Angle Speed Difference between two consecutive angle values. Reset: 0H ANG_SPD 14:0 r Angle Revolution Register AREV Angle Revolution Register Offset 04H Reset Value 8000H Target Data Sheet 30 V 0.41, 2009-03 TLI5012 Specification Field RD_REV Bits 15 Type r Description Read Status, Revolution 0B after readout 1B new value (REVOL) present Reset: 1B Frame Counter (unsigned 6 bit value) Counts every new angle value Reset: 0H Number of Revolutions (signed 9 bit value) Reset: 0H FCNT 14:9 rw REVOL 8:0 r Frame Synchronization Register FSYNC Frame Synchronization Register Offset 05H Reset Value 0000H Field FSYNC Bits 15:9 Type rw Description Frame Synchronization Counter Value Sub counter within one frame. Reset: 0H Target Data Sheet 31 V 0.41, 2009-03 TLI5012 Specification Interface Mode1 Register MOD_1 Interface Mode1 Register Offset 06H Reset Value 8001H Field FIR_MD Bits 15:14 Type rw Description Filter Decimation Setting 00B 21.3µs 01B 42.7µs 10B 85.3µs 11B 170.6µs Reset: 10B Clock Source Select 0B internal oscillator 1B external 4MHz clock Reset: 0B SSC-Interface 0B Push-Pull 1B Open Drain Reset: 0B Hold DSPU Operation 0B DSPU in normal schedule operation 1B DSPU is on hold Reset: 0B Reserved Reset: 01B CLK_SEL 4 rw SSC_OD 3 rw DSPU_HOLD 2 rw Res 1:0 Target Data Sheet 32 V 0.41, 2009-03 TLI5012 Specification SIL Register SIL SIL Register Offset 07H Reset Value 0000H Field FILT_PAR Bits 15 Type rw Description Filter Parallel 0B filter parallel disabled 1B filter parallel enabled (source: X-value) Reset: 0B Filter Inverted 0B filter inverted disabled 1B filter inverted enabled Reset: 0B Fuse Reload 0B fuse reload disabled 1B fuse parameters reloaded to DSPU at next cycle start Reset: 0B ADC-Test vectors 0B ADC-Test vectors disabled 1B ADC-Test vectors enabled Reset: 0B Test vector Y 000B 0V 001B +70% 010B +100% 011B +Overflow 101B -70% 110B -100% 111B -Overflow Reset: 000B FILT_INV 14 rw FUSE_REL 10 rw ADCTV_EN 6 rw ADCTV_Y 5:3 rw Target Data Sheet 33 V 0.41, 2009-03 TLI5012 Specification Field ADCTV_X Bits 2:0 Type rw Description Test vector X 000B 0V 001B +70% 010B +100% 011B +OV 101B -70% 110B -100% 111B -OV Reset: 000B Interface Mode2 Register MOD_2 Interface Mode2 Register Offset 08H Reset Value 0800H Field ANG_RANGE Bits 14:4 Type rw Description Angle Range Angle Range [°] = 360° * (27 / ANG_RANGE) 200H represents 90° 080H represents 360° Reset: 080H Angle Direction 0B counterclockwise rotation of magnet° 1B clockwise rotation of magnet Reset: 0B ANG_DIR 3 rw Target Data Sheet 34 V 0.41, 2009-03 TLI5012 Specification Interface Mode3 Register MOD_3 Interface Mode3 Register Offset 09H Reset Value 0000H Field ANG_BASE Bits 15:4 Type rw Description Angle Base 800H -180° 000H 0° 001H 0.00879° 7FFH +179.912° Reset: 0H Analog Spike Filters of Input Pads 0B spike filter disabled 1B spike filter enabled Reset: 0B Configuration of Pad-Driver 00B IFA/IFB: strong driver, DATA: strong driver, fast edge 01B IFA/IFB: strong driver, DATA: strong driver, slow edge 10B IFA/IFB: weak driver, DATA: medium driver, fast edge 11B IFA/IFB: weak driver, DATA: weak driver, slow edge Reset: 00B SPIKEF 3 rw PAD_DRV 1:0 rw Target Data Sheet 35 V 0.41, 2009-03 TLI5012 Specification Offset X Register OFFX Offset X Offset 0AH Reset Value 0000H Field X_OFFSET Bits 15:4 Type rw Description Offset Correction of X-value Reset: 0H Offset Y Register OFFY Offset Y Offset 0BH Reset Value 0000H Field Y_OFFSET Bits 15:4 Type rw Description Offset Correction of Y-value Reset: 0H Target Data Sheet 36 V 0.41, 2009-03 TLI5012 Specification Synchronicity Register SYNCH Synchronicity Offset 0CH Reset Value 0000H Field SYNCH Bits 15:4 Type rw Description Amplitude Synchronicity +2047D 112.494% 0D 100% -2047D 87.500% Reset: 0H IFAB Register IFAB IFAB Register Offset 0DH Reset Value 0004H Field ORTHO Bits 15:4 Type rw Description Orthogonality Correction of X and Y Components +2047D 11.2445° 0D 0° -2047D -11.2500° Reset: 0H 37 V 0.41, 2009-03 Target Data Sheet TLI5012 Specification Field IFAB_OD Bits 2 Type rw Description IFA & IFB Open Drain 0B Push-Pull 1B Open Drain Reset: 1B Interface Mode4 Register MOD_4 Interface Mode4 Register Offset 0EH Reset Value 0011H Field TCO_X_T IFAB_RES Bits 15:9 4:3 Type rw rw Description Offset Temperature Coefficient for X-Component Reset: 0H IFAB Resolution 00B 12bit = 0.088° (244Hz) 01B 11bit = 0.176° (488Hz) 10B 10bit = 0.352° (977Hz) 11B 9bit = 0.703° (1953Hz) Reset: 10B Interface Mode PWM if CLK is connected to GND at startup. Note: Not mentioned combinations are not allowed IF_MD 2:0 rw 001B SSC mode; PWM Reset: 001B Target Data Sheet 38 V 0.41, 2009-03 TLI5012 Specification Temperature Coeffizient Register TCO_Y Temperature Coeffizient Register Offset 0FH Reset Value 0000H Field TCO_Y_T CRC_PAR Bits 15:9 7:0 Type rw rw Description Offset Temperature Coefficient for Y-Component Reset: 0H CRC of Parameters CRC of parameters from address 08H to 0FH Reset: 0H X-raw Value Register ADC_X X-raw value Offset 10H Reset Value 0000H Field ADC_X Bits 15:0 Type r Description ADC value of X-GMR Read out of this register will update ADC_Y Reset: 0H Target Data Sheet 39 V 0.41, 2009-03 TLI5012 Specification Y-raw Value Register ADC_Y Y-raw value Offset 11H Reset Value 0000H Field ADC_Y Bits 15:0 Type r Description ADC value of Y-GMR Updated when ADC_X or ADC_y is read. Reset: 0H 3.5.2 Pulse Width Modulation Interface The Pulse Width Modulation (PWM) update rate can be programmed within the register 0EH (IFAB_RES) in following steps: • • • • 0.25 kHz with 12 bit resolution 0.5 kHz with 11 bit resolution 1.0 kHz with 10 bit resolution (default) 2.0 kHz with 9 bit resolution PWM uses a square wave with constant frequency whose duty cycle is modulated resulting in an average value of the waveform. Figure 16 shows the principle behavior of a PWM with different duty cycles and the definition of timing values. The duty cycle of a PWM is defined by following general formulas: Duty Cycle = ton t PWM t PWM = t on + toff f PWM = 1 t PWM (3) The range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. More details are given in Table 13. Target Data Sheet 40 V 0.41, 2009-03 TLI5012 Specification UIFA Vdd ON = High level OFF = Low level tON Duty cycle = 5% tPWM t OFF Duty cycle = 50% UIFA ‚0' Vdd t UIFA ‚0' Vdd Duty cycle = 95% t ‚0' Figure 16 Table 13 Parameter PWM Output Frequency Output Duty Cycle Range Typical Example for a PWM Signal PWM Interface Symbol Min. fPWM DYPWM 244 6.25 2 98 Values Typ. Max. 1953 93.75 Hz % % % Unit Note / Test Condition t selectable by IFAB_RES1) Absolute Angle Electrical Error (S_RST; S_VR) System Error (S_FUSE; S_OV; S_XYOL; S_MAGOL; S_ADCT) Short to GND Short to VDD, Power-Loss 2) 0 99 PWM Period Variation tPWMvar -5 1) fPWM = (fDIG * 2IFAB_RES) / (24 * 4096) 2) depends on internal oscillator frequency variation - 1 100 5 % % % Target Data Sheet 41 V 0.41, 2009-03 TLI5012 Package Information 4 4.1 Package Information Package Parameters Table 14 Parameter Package Parameters Symbol Limit Values min. typ. max. RthJA RthJC RthJL 150 200 75 85 MSL 3 Cu Sn 100% > 7 µm Unit K/W K/W K/W Notes Junction to Air1) Junction to Case Junction to Lead 260°C Thermal Resistance Soldering Moisture Level Lead Frame Plating 1) according to Jedec JESD51-7 4.2 Package Outline 1.75 MAX. 0.35 x 45˚ 4 -0.2 1) +0.06 0.175 ±0.07 (1.45) 1.27 2) 0.41 +0.1 -0.06 B 0.2 M 0.19 0.1 A B 8x SEATING PLANE 0.64 ±0.25 E 6 ±0.2 0.2 8˚MAX. M A C 1.22 ±0.18 C 8x 4) D 8 3 x 1.27 = 3.81 5 Detail A ø0.6 Sensitive Area 3) Index Marking 1 4 A 0.75 D E CENTER OF SENSITIVE AREA 5 -0.2 1) 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area 3) Max. 3˚ tilt of sensitive area to preference "B" 4) Reference "D" is defined with the center of all 8 pins P-PG-DSO-08-16-S-PO V03 Figure 17 PG-DSO-8 Package Dimension Target Data Sheet 42 0.32 MIN. V 0.41, 2009-03 TLI5012 Package Information 4.3 Footprint 1.31 0.65 5.69 1.27 Figure 18 Footprint PG-DSO-8 4.4 Packing 8 0.3 12 ±0.3 5.2 6.4 1.75 2.1 Figure 19 Tape and Reel 4.5 Marking Position 1st Line 2nd Line 3rd Line Processing Marking I5012xx xxx Gxxxx Description See ordering table on page 7 Lot code G..green, 4-digit..date code Note: For processing recommendations, please refer to Infineon’s Notes on processing Target Data Sheet 43 V 0.41, 2009-03 www.infineon.com Published by Infineon Technologies AG