TUA6045-2

D a ta S he et , R ev i s i on 3. 1, D e c em be r 20 0 6 TUA 6045-2 Low P ow er 3 -Ba nd D i gita l T V / Po r tab le Tu ne r IC TA IF UN 3 Co mmu nicat i on So lutio ns Edition 2006-12-19 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2006. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a ta S he et , R ev i s i on 3. 1, D e c em be r 20 0 6 TUA 6045-2 Low P ow er 3 -Ba nd D i gita l T V / Po r tab le Tu ne r IC TA IF UN 3 Co mmu nicat i on So lutio ns TUA 6045-2 TUA 6045-2 ’TAIFUN 3’ Revision History: Previous Version: Page 2006-12-19 2006-09-12 Data Sheet, Revision 3.1 Preliminary Specification, Revision 3.0 Subjects (major changes since last revision) 9 - 11, 28, L-Band application added. Operating range and AC/DC Characteristics 30 - 41 extended for L-Band. 31 - 41 Table Footnote added with description for impedance measurement. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: horst.klein@infineon.com Data Sheet 4 Revision 3.1, 2006-12-19 Table of Contents Page List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2 2.2.1 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 4 4.1 4.2 4.3 5 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 5.5 Product Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixer/Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAW Filter Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IF AGC Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IF switch and Loop through for tuner alignment . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended band limits in MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixer-Oscillator-block, SAW filter driver . . . . . . . . . . . . . . . . . . . . . . . . RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IF AGC amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL block, XTAL oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC/DC clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Reset, Stand-by Condition . . . . . . . . . . . . . . . . . . . . . . . . . . IF switch, Loop thru . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tuner application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit for hybrid application . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit for L-Band application . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Byte Specification, Function and Defaults . . . . . . . . . . . . . . . . . . . . . 5 10 10 10 10 11 11 11 11 11 12 13 13 14 21 22 22 22 22 23 23 24 24 25 26 26 27 28 29 29 29 30 31 41 43 45 48 Data Sheet Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 5.5.1 5.5.2 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 6 Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain (GV) measurement in LOW band . . . . . . . . . . . . . . . . . . . . . . . . . Gain (GV) measurement in MID and HIGH bands . . . . . . . . . . . . . . . . Matching circuit for optimum noise figure in LOW band . . . . . . . . . . . . Noise figure (NF) measurement in LOW band . . . . . . . . . . . . . . . . . . . Noise figure (NF) measurement in MID and HIGH bands . . . . . . . . . . . Cross modulation measurement in LOW band . . . . . . . . . . . . . . . . . . . Cross modulation measurement in MID and HIGH bands . . . . . . . . . . . Ripple susceptibility measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 56 59 59 59 60 60 61 61 62 62 Package PG-VQFN-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Data Sheet 6 Revision 3.1, 2006-12-19 TUA 6045-2 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 ATSC tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DVB-T and analog tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISDB-T tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics, TA = 25°C, VCC = 3.3V . . . . . . . . . . . . . . . . . . Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Address Organization in I2C Mode . . . . . . . . . . . . . . . . . . . . . . . Address selection in I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Addresses of Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . Sub Addresses of Read Data Registers . . . . . . . . . . . . . . . . . . . . . . . Bus Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subaddress 00H, Main Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subaddress 01H, Control Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subaddress 02H, Reference Divider R and Crystal Oscillator Control Subaddress 03H, AGC control and IF Signal Processing Control . . . . Subaddress 04H, DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . Subaddress 06H, Mode Bytes, Test Mode and Standby Control . . . . Subaddress 80H, Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subaddress 8EH, Chip Code “6045” . . . . . . . . . . . . . . . . . . . . . . . . . . Subaddress 8FH, Revision Code, advanced with design steps . . . . . 12 12 12 29 30 31 41 42 42 42 43 43 46 48 49 50 52 54 55 56 57 58 Data Sheet 7 Revision 3.1, 2006-12-19 TUA 6045-2 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Pin Configuration TUA 6045-2 in VQFN-48 Package . . . . . . . . . . . . . Block Diagram TUA 6045-2 in VQFN-48 package. . . . . . . . . . . . . . . . Functional Block Diagram of IF switch and Loop thru . . . . . . . . . . . . . Tuner application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit diagram for hybrid application (DVB-T / PAL). . . . . . . . . . . . . . Circuit diagram for L-Band application. . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-Wire Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain (GV) measurement in LOW band . . . . . . . . . . . . . . . . . . . . . . . . Gain (GV) measurement in MID and HIGH bands. . . . . . . . . . . . . . . . Matching circuit for optimum noise figure in LOW band . . . . . . . . . . . Noise figure (NF) measurement in LOW band. . . . . . . . . . . . . . . . . . . Noise figure (NF) measurement in MID and HIGH bands . . . . . . . . . . Cross modulation measurement in LOW band . . . . . . . . . . . . . . . . . . Cross modulation measurement in MID and HIGH bands . . . . . . . . . . Ripple susceptibility measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-VQFN-48 Vignette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-VQFN-48 Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 21 25 26 27 28 45 45 59 59 60 60 61 61 62 62 63 63 Data Sheet 8 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Product Info 1 Product Info General Description The TUA 6045-2 integrates the mixer-oscillator, AGC amplifier and a digitally programmable phase lock loop (PLL). This makes the TUA 6045-2 an ideal product for applications where size and low power consumption are required design key factors. Typical applications include TV's, VCR's, Set Top Boxes (STB) and also a range of portable products. Features General • • • • • • • • Suitable for PAL, NTSC, SECAM, DVB, DMB, DAB, ISDB-T and ATSC High band covers frequency range for L-Band up to 1.5 GHz Supply voltage range from 3 to 5.5 V Combined small - wide AGC detection AGC + AGC buffer output Low phase noise Full ESD protection Qualified according to JEDEC for consumer applications Three band tuner Unbalanced highohmic LOW band input Balanced lowohmic MID band input Balanced lowohmic HIGH band input Two pin oscillators for LOW/MID band Four pin oscillator for HIGH band 4 IF pins to connect a 2 pole bandpass Symmetrical SAW driver Fully balanced IF AGC amplifier PLL • • • • • • • • • I2C / three wire combi bus 4 independent I2C addresses High voltage VCO tuning output Two PMOS ports One voltage referred port Internal LOW/MID/HIGH band switch Xtal oscillator, range from 4 to 16 MHz Xtal buffer output with programmable level and output divider Clock generator for DC/DC converter with programmable low and high time Bus controlled stand by mode Mixer/Oscillator • • • • • • • • • Power management • Application • The IC is suitable for PAL, NTSC, SECAM, DVB-C, DVB-T, DVB-H, DMB-T, DAB, ISDB-T, ATSC and LBand tuners. IF-Amplifier Ordering Information Type TUA 6045-2 Ordering Code SP000250164 Package PG-VQFN-48 Data Sheet 9 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Product Description 2 Product Description The TUA 6045-2 integrates the mixer-oscillator, variable AGC output amplifier and a digitally programmable phase lock loop (PLL) not requiring an external high voltage buffer. Furthermore, the TUA 6045-2 integrates a buffered RF AGC and programmable clock signals for an external DC-DC up converter. The integrated mixer oscillator function comprises of three balanced mixers. The first mixer has an unbalanced high impedance input while the other two have balance low impedance inputs. The tuner also has firstly, 2-pin asymmetric oscillators for both Low and Mid bands and secondly a 4-pin symmetrical oscillator for High band operations including a band selector switch. The output signal from the mixer is amplified via a SAW filter driver followed by variable gain amplifier stage in order to achieve a constant output level used for A/D conversion. All functions can be programmed with up to four different IC addresses. Also, the PLL connected to a 4-16 MHz reference crystal which is buffered on-chip, allows the setting of the tuner oscillator with a minimum step size of 20 kHz. A Lock flag will be set once the PLL is locked and communicated via the I2C/3-Wire bus. The complete control setting of the IC is done by a microprocessor via the I2C/3-Wire bus. The device also has three output ports of which P2 can be configured as a programmable output voltage port. 2.1 2.1.1 • • • Features General • • Supply voltage range 3 to 5.5 V. Suitable for PAL, NTSC, SECAM, DVB-T/H/C, DAB, ISDB-T, ATSC and L-Band. Wideband and Narrow AGC detectors for tuner RF AGC − 5 programmable take-over points − 2 programmable time constants. Low phase noise. Full ESD protection. 2.1.2 • • • • • • • Mixer/Oscillator High impedance mixer input (common emitter) for LOW band. Low impedance mixer input (common base) for MID band. Low impedance mixer input (common base) for HIGH band. 2 pin oscillator for LOW band. 2 pin oscillator for MID band. 4 pin oscillator for HIGH band. Oscillator for HIGH band divided by 3 available for MID band mixer. Data Sheet 10 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Product Description 2.1.3 • SAW Filter Driver Symmetrical IF preamplifier with low output impedance able to drive a compensated SAW filter (500 Ω//40 pF). 2.1.4 • IF AGC Amplifier Symmetrical variable gain IF output amplifier with low noise, high linearity, high dynamic range. 2.1.5 • • • • • • • • • • • PLL 4 independent I2C addresses, or 3-Wire bus mode. I2C bus protocol compatible with 3.3 V and 5V micro-controllers up to 400 kHz. High voltage VCO tuning output. 3 PNP ports, one of them realized as programmable voltage output. 1 clock output for external DC/DC upconversion to generate the tuning supply voltage, may be used as NPN port. Stand-by programmable for functional blocks allows customized ramping. Internal LOW/MID/HIGH band switch. Lock-in flag. 4 to 16 MHz crystal oscillator with programmable output buffer. programmable reference divider ratios. 4 charge pump currents, programmable in 15 steps. 2.1.6 • IF switch and Loop through for tuner alignment 2 programmable switches to bypass the bandpass/SAW filter to facilitate the tuner pre-stage alignment. 2.2 • • Application The IC is suitable for PAL, NTSC, SECAM, DVB-T/H/C, DAB, ISDB-T, ATSC and LBand tuners. The integrated RF AGC control has wide band detectors at the mixer inputs and a narrowband detector at the saw filter driver output. Data Sheet 11 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Product Description 2.2.1 Table 1 Recommended band limits in MHz ATSC tuners RF input Oscillator max. 157.25 451.25 861.25 min. 101 201 503 max. 203 479 907 Band LOW MID HIGH min. 55.25 163.25 457.25 Table 2 DVB-T and analog tuners RF input Oscillator max. 154.25 439.25 863.25 min. 87.15 200.15 486.15 max. 193.15 478.15 902.15 Band LOW MID HIGH min. 48.25 161.25 447.25 Table 3 ISDB-T tuners RF input Oscillator max. 167 467 767 min. 150 230 530 max. 224 524 824 Band LOW MID HIGH min. 93 173 473 Note: Tuning margin of 3 MHz not included. Data Sheet 12 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description 3 3.1 Functional Description Pin Configuration 48 OSCLOWIN 38 MIXOUT OSCLOWOUT 1 OSCGND 2 OSCMIDIN 3 OSCMIDOUT 4 OSCHIGHIN 5 OSCHIGHOUT 6 OSCHIGHOUT 7 OSCHIGHIN 8 VCC 9 SAWOUT 10 SAWOUT 11 GND 12 IFIN 13 IFIN 14 IFAMPAGC 15 IFOUT 16 IFOUT 17 VT 18 CP 19 VDD 20 DC/DC_GND 21 DC/DC Clock 22 X_TAL Buff 23 49 X_TAL OUT 24 37 MIXOUT 36 SAWIN 35 SAWIN 34 P2, VRF 33 P1 32 P0 31 RFAGC 30 RFAGC Buffer 29 SDA 28 SCL 27 CAS/EN 26 Busmode 25 X_TAL IN 42 RFGND 47 HIGHIN 46 HIGHIN 43 LOWIN 45 MIDIN 44 MIDIN 41 n.c. 40 n.c. TUA 6045-2 VQFN-48 package 39 n.c. GND package Figure 1 Pin Configuration TUA 6045-2 in VQFN-48 Package Data Sheet 13 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description 3.2 • Pin Definition and Functions Pin Definition and Functions Equivalent I/O Schematic Average DC voltage at VCC = 3.3V LOW MID HIGH 2.3 V 1.8 V 1 48 Pin Symbol No. 48 1 OSCLOWIN OSCLOWOUT 2 3 4 OSCGND OSCMIDIN OSCMIDOUT Oscillator ground 0.0 V 0.0 V 2.3 V 1.8 V 0.0 V 4 3 Data Sheet 14 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description Pin Symbol No. 5 6 7 8 OSCHIGHIN OSCHIGOUT OSCHIGOUT OSCHIGHIN 6 7 Equivalent I/O Schematic Average DC voltage at VCC = 3.3V LOW MID HIGH 2.3 V 2.25 V 2.25 V 2.3 V 5 8 9 10 11 VCC SAWOUT SAWOUT Supply voltage 3.3 V 3.3 V 3.3 V 1.65 V 1.65 V 1.65 V 1.65 V 1.65 V 1.65 V 10, 11 12 13 14 GND IFIN IFIN 13 14 0.0 V 0.0 V 0.0 V 2.64 V 2.64 V 2.64 V 2.64 V 2.64 V 2.64 V Data Sheet 15 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description Pin Symbol No. 15 IFAMPAGC Equivalent I/O Schematic Average DC voltage at VCC = 3.3V LOW n.a. MID n.a. HIGH n.a. 15 16 17 IFOUT IFOUT 1.6 V 1.6 V 1.6 V 1.6 V 1.6 V 1.6 V 16 17 18 19 VT CP VT 1.7 V VT 1.7 V VT 1.7 V 18 19 20 21 22 VDD DC/DC_GND DC/DC Clock Supply voltage 3.3 V 0.0 V n.a. 3.3 V 0.0 V n.a. 3.3 V 0.0 V n.a. 22 21 Data Sheet 16 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description Pin Symbol No. 23 XTAL Buffer Equivalent I/O Schematic Average DC voltage at VCC = 3.3V LOW MID HIGH 23 24 25 XTAL Out XTAL In 25 0.9 V 0.9 V 0.9 V 0.9 V 0.9 V 0.9 V 24 26 Busmode n.a. n.a. n.a. 26 27 CAS/EN n.a. n.a. n.a. 27 V ref Data Sheet 17 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description Pin Symbol No. 28 SCL Equivalent I/O Schematic Average DC voltage at VCC = 3.3V LOW n.a. MID n.a. HIGH n.a. 28 29 SDA 29 n.a. n.a. n.a. 30 31 RFAGC Buffer RFAGC 3.2 V 3.2 V 3.2 V 3.2 V 3.2 V 3.2 V 31 + disable 30 32 P0 0 V or 0 V or 0 V or VCC- VCC- VCCVCE VCE VCE 32, 33 33 P1 0 V or 0 V or 0 V or VCC- VCC- VCCVCE VCE VCE Data Sheet 18 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description Pin Symbol No. 34 P2, VRF Equivalent I/O Schematic Average DC voltage at VCC = 3.3V LOW VRF MID VRF HIGH VRF 34 35 36 SAWIN SAWIN 35 36 VCC VCC VCC VCC VCC VCC 37 38 MIXOUT MIXOUT 37 38 VCC VCC VCC VCC VCC VCC Oscillator 39 40 41 42 n. c. n. c. n. c. RFGND IF ground 0.0 V 0.0 V 0.0 V Data Sheet 19 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description Pin Symbol No. 43 LOWIN Equivalent I/O Schematic Average DC voltage at VCC = 3.3V LOW 2 MID HIGH 43 44 45 MIDIN MIDIN 1 1 44 45 46 47 HIGHIN HIGHIN 46 47 1 1 49 GND package Exposed pad ground (Die pad) 0.0 V 0.0 V 0.0 V Data Sheet 20 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description 3.3 Functional Block Diagram OSCLOWIN MIXOUT LOWIN 48 47 46 45 44 43 42 41 40 39 38 37 MIXOUT HIGHIN HIGHIN RFGND MIDIN MIDIN n.c. n.c. n.c. OSCLOWOUT 1 36 SAWIN Oscillator LOW 2 OSCGND Mixer HIGH Oscillator MID RF Input HIGH 35 SAWIN OSCMIDIN 3 34 P2, VRF Mixer MID RF Input MID 33 OSCMIDOUT 4 P1 Oscillator HIGH OSCHIGHIN 5 Mixer LOW RF Input LOW PORTS 32 P0 OSCHIGHOUT 6 SAW Filter Driver Lock Detector AGC Detector AGC fref FL 31 RFAGC OSCHIGHOUT 7 30 RFAGC Buffer OSCHIGHIN 8 Prog. Divider I2C Bus 29 SDA VCC 9 VCC fdiv 28 SCL SAWOUT 10 1/N Divider Phase/ Freq Comp Reference Divider 27 CAS / EN SAWOUT 11 IF AGC Amplifier Charge Pump DC / DC Signal 26 Busmode GND 12 VDD R Crystal Oscillator 25 X_TAL IN 13 14 15 16 17 18 19 20 21 22 23 24 DC/DC_GND X_TAL OUT DC/DC Clock IFIN IFIN CP X_TAL Buff IFOUT IFOUT IFAMPAGC VT VDD TUA 6045-2 Figure 2 Block Diagram TUA 6045-2 in VQFN-48 package Data Sheet 21 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description 3.4 3.4.1 Circuit Description Mixer-Oscillator-block, SAW filter driver The mixer-oscillator block includes three balanced mixers (one mixer with an unbalanced high-impedance input and two mixers with a balanced low-impedance input), two 2-pin asymmetrical oscillators for the LOW and the MID band, one 4-pin symmetrical oscillator for the HIGH band, a reference voltage, and a band switch. Filters between tuner input and IC separate the TV frequency signals into three bands. The band switching in the tuner front-end is done by using three PNP port outputs. In the selected band, the signal passes through a tuner input stage with a MOSFET amplifier, a double-tuned bandpass filter and is finally fed to the mixer input of the IC. The impedance of the mixer at LOW band has high ohmic, while MID or HIGH band has a low ohmic input. The input signal is mixed there with the signal from the activated on chip oscillator to the IF frequency. The IF is filtered by means of an external SAW filter (Surface Acoustic Waves filter) in between the 2 mixer output pins and the 2 input pins of the following SAW filter driver. The SAW filter driver has a low output impedance to drive the SAW filter directly. 3.4.2 RF AGC The RF AGC stage combines a wide band and a narrow band detection. The wide band detector (WB) detects the input signal directly at the RF input for each band. The narrow band detector (NB) detects the level of the SAW filter driver output signal. If both detected levels are below the RF AGC take-over points, a external capacity will be charged with the source current of 300 nA or 9 µA (release current). If one of the detected levels is above the RF AGC take-over points, the external capacity will be discharged with the sink current of 100 µA (attack current). The integrated current generates an AGC voltage for gain control of the tuners input transistors. The AGC takeover and the time constant are selectable by the I2C bus as shown in Table 17 "Subaddress 03H, AGC control and IF Signal Processing Control" on Page 52. An integrated RF AGC buffer allows to monitor the AGC voltage without any influence on the tuner gain control. This buffer can be disabled as shown in Table 16 "Subaddress 02H, Reference Divider R and Crystal Oscillator Control" on Page 50 3.4.3 IF AGC amplifier Coming out of the SAW filter the IF signal is sent through a VGA (Variable Gain Amplifier) which will set the differential IF output signal to the desired level (preferably 1 Vpp). The gain of the VGA is determined by the DC-voltage at pin IFAMPAGC Data Sheet 22 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description 3.4.4 PLL block, XTAL oscillator The VCO frequency fOSC is stabilized by a digital CMOS PLL (Phase Locked Loop, Frequency Synthesizer). The oscillator signal is internally DC-coupled as a differential signal to the programmable divider input. The signal subsequently passes through a programmable divider (N) and then the divided VCO signal: f OSC f div = -----------, ( N = 240 … 65535 ) N is compared in a digital frequency/phase detector (PD, frequency detector) with a programmable reference frequency: f XTAL f ref = ---------------, ( R = 2 … 1023 ) R which is derived from a quartz reference fXTAL divided by a programmable reference divider (R). The phase detector has a linear operating range without a dead zone for very small phase deviations. A programmable ABL pulse width (Anti BackLash) works against the delay of the charge pump cell. The selectable ABL pulse width values have been implemented for test purpose only and have no performance effects. The phase detector has two outputs (up & down) that drive two current sources of opposite polarity as charge pump (CP). If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the positive current source (Isource) pulses for the duration of the phase difference. In the reverse case the negative current source (Isink) pulses. If the two signals are in phase (PLL is locked), the integrated charge pump current is approximately zero. In case of active closed loop control the charge pump provides programmable output current drive capability to optimize the loop requirements. The charge pump currents are programmable from 0 to 1.125 mA in steps of 75 µA. The PLL contains an integrated lock detector. A lock-in flag is set when the loop is locked. It can be read by the processor via the common I2C/3-Wire bus. The crystal oscillator (XTAL) is an unbalanced Pierce oscillator which operates in parallel resonance with quartz crystals from 4...16 MHz. By programming it’s possible to pass the oscillator frequency fXTAL through a divider stage to a buffered output pin or to use an external quartz clock for the reference oscillator via a switchable preamplifier for test purpose only. 3.4.5 Bus Interface The programming of the CMOS frequency synthesizer is done via a combined serial I2C/3-Wire bus interface. The choice of the desired bus is made by a bus mode select signal at pin BUSMODE. Data Sheet 23 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description In I2C-bus mode four different chip addresses can be set by appropriate DC levels at pin CAS (Chip Address Select), while in 3-Wire mode the chip is addressed by a low active enable signal at pin EN. The content of the bus telegram (serial data format) is controlled by software programming and assigned to the registers of the functional units according to the several sub addresses. The most significant bit (MSB) of the data protocol is shifted in first. The clock is generated by the processor (input pin SCL/Clock), while pin SDA/Data functions as an input or an output (open drain, external pull-up resistor) depending on the direction of the data (write or read mode). Both inputs have schmitt-trigger circuits with hysteresis and furthermore a low-pass characteristic, which suppress a certain noise level on the bus lines and enhance so the noise immunity of the combi-bus. A detailed description of the chip address organization in I2C-mode as well as the used sub addresses of the data registers is given in chapter 5.2 "Bus Interface" on page 41 - and the programmable I2C/3-Wire bus data format is shown in chapter 5.3 "Bus Data Format" on page 43. 3.4.6 DC/DC clock output To drive a bipolar NPN switching transistor of an external DC/DC converter directly, a programmable DC/DC clock generator is integrated. The clock frequency and the duty cycle of the DC/DC clock generator can be set over the I2C/3-Wire bus as shown in Table 18 "Subaddress 04H, DC-DC Converter" on Page 54. 3.4.7 Power-on Reset, Stand-by Condition While applying the supply voltage, integrated power-on reset circuits ensure a defined state after initial power-up. The required programming data will be set to default values. When VCC fall below approximately 1.2 V (typ.) the power-on resets go active and tie all write data registers to their power-on defaults (= power-down reset). While power-on reset is active no programming is possible. The power-on flags (POFx) are set at power-on and when VVCCx falls below appr. 1.2 V (typ.). They will be reset at the end of a READ operation of the status register. By programmable stand-by control bits it’s possible to reduce the current consumption of the IC up to 99%. In the full stand-by mode only bus interface is staying active and the current consumption is reduced below 200 µA. After power-on reset only bus interface and XTAL-oscillator with bandgap are active and the current consumption is about 2.6 mA (typ.). Data Sheet 24 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Functional Description 3.4.8 IF switch, Loop thru For the alignment procedure of the tuner module two programmable switches are integrated to bypass the bandpass, the SAW driver and the SAW filter. The first switch called “IF switch” can switch between the mixer output signal and the bandpass output signal. The second switch called “Loop thru” can switch between the signal after the first stage of the IF AGC amplifier and the SAW filter output signal. Bandpass IF switch control = bit 15 of sub address 03H Loop thru control = bit 14 of sub address 03H IF AGC amplifier IF switch MIXER input MIXER Loop thru IF output SAW Filter SAWDRV Figure 3 Functional Block Diagram of IF switch and Loop thru Data Sheet 25 Revision 3.1, 2006-12-19 4 4.1 Figure 4 Data Sheet    9ROW VXSSO\ HIGH band $*& ,) %DQGILOWHU  0+] Applications 6$: 'ULYHU H[WHUQDO $*& WR &KDQQHO 'HFRGHU ,) $PSOLILHU MID band $*& $*& (QFRGHU $*& 'HWHFWRU ZLGH $*& 'HWHFWRU VPDOO $*& %XIIHU %XIIHUHG $*& 9ROWDJH Tuner application block diagram Tuner application block diagram 3 1 3RUWV 26 &3 3' 5 3 3 9UHI 3RUW 6&/ ,&  ZLUH %XV 6'$ &$6  (1 %XVPRGH LOW band a a a a a a a a a a a a ;WDO ;WDO,2 'LYLGHU %XIIHU '&'& &ORFN 3RZHU 6XSS\ 9&& 9'' « 0+] ;7$/ ,2 3IODXP 9 VXSSO\ /2: 0,' +,*+ NVM TUA 6045-2 TAIFUN 3 Applications Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Applications 4.2 Application circuit for hybrid application X6 HICH GND X5 MID GND MACOM 1:1(ETC1-1-13) MACOM 1:1(ETC1-1-13) GND 2 GND 2 1 3 1 3 VCC 6 TR3 4 6 TR2 4 X4 LOW GND 390nH C50 100n GND R27 50R C56 22p C55 R1 12R C10 100p R2 2k7 D1 BB659C C2 2p2 1 GND C54 22p C53 1n C52 1n C51 1n GND GND C49 np R26 np 38 /MIXOUT 390nH L11 L10 R25 0R np C48 GND np R24 L1 8,5 turns GND C1 2p7 48 OSCLOWIN 2p2 47 HIGHIN L9 46 /HIGHIN 45 MIDIN 44 /MIDIN 43 LOWIN 42 RFGND 41 n.c 40 n.c 39 n.c 37 MIXOUT 0R C47 5p6 OSCLOWOUT SAWIN 36 C46 22p C45 22p GND GND P2,VRF GND R3 2k7 C11 GND GND C15 22n R4 8R2 R5 2k2 C14 3n3 R8 150k Vt C57 270p GND GND VCC R6 2k2 R7 0R L4 C13 100n GND 1 2 2 OSCGND /SAWIN 35 D2 BB659C C3 1p5 82p L2 2,5 turns C4 1p2 3 OSCMIDIN P2,VRF 34 C44 4n7 4 OSCMIDOUT P1 33 GND P1 GND P0 GND C12 22p C5 1p2 5 OSCHIGHIN IC1 TUA6045-2 (VQFN48) C43 4n7 PO 32 C6 1p2 D3 BB555 L3 2 turns C42 4n7 6 /OSCHIGHOUT RF AGC 31 R9 2k2 C41 100n 30 GND RF AGC Buffer C7 1p2 C8 1p2 7 OSCHIGHOUT RF AGC Buffer 8 /OSCHIGHIN SDA 29 R23 220R R22 220R R21 100R C36 47p GND C40 4n7 C39 100p GND SDA GND SCL GND CAS/EN GND Busmode J1 JUMPER 1X2 GND C9 100n 9 VCC SCL 28 68nH R10 0R L5 1u2H R11 0R 10 SAWOUT CAS/EN 27 C38 100p C37 47p C35 11 /SAWOUT DC/DC Clock X_TAL Buff IFAMPAGC Busmode X_TAL OUT 26 IN IN /IFOUT GND 3 GND 12 GND IFIN IFIN X_tal in 25 C34 R20 0R np X3 SMA 4n7 OUT OUT SAW1 X6966D IFOUT VDD VT GND C17 CP GND GND GND GND GND GND GND 13 14 15 16 17 18 19 20 21 22 23 24 Q1 C33 39p 4MHz C32 39p SIP5D 5 4 2p7 np C16 GND GND 6 7 C19 10n C20 1n C21 1n C23 6n8 GND2 R17 0R C31 1n C18 2p7 GND 1 C22 2 12p 3 VCC C28 GND R13 C24 100k 33p GND2 C29 100n R12 10k GND V1 BC847 100n L6 68nH GND X2 GND SMA R19 np L8 L7 1mH np R18 D4 BAS 70-02W C30 100n GND2 220nH VCC X1 SMA IF GND GND 4 /IFOUT nc. GND 5 GND IFOUT TR1 TOKO(A1010)-TRANSFORMER GND IFAMPAGC R14 10K C25 100n GND R15 10K D5 Z33 C26 100n GND2 R16 33k C27 22n GND2 PLL GND2 J3 SDA SCL GND CAS/EN STOCKO 4pol Figure 5 Circuit diagram for hybrid application (DVB-T / PAL) Data Sheet 27 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Applications 4.3 Application circuit for L-Band application X6 HICH GND X5 MID GND MACOM 1:1(ETC1-1-13) GND PULSE 1:1(CX2156) GND 2 2 1 3 1 3 VCC 6 TR3 4 6 TR2 4 X4 LOW GND 390nH C50 100n GND R27 50R C56 22p C55 R1 12R C10 100p R2 2k7 D1 BB659C C2 2p2 1 GND C54 22p C53 1n C52 1n C51 1n GND GND C49 np R26 np 38 /MIXOUT 390nH L11 L10 R25 0R np C48 GND np R24 L1 8,5 turns GND C1 2p7 48 OSCLOWIN 2p2 47 HIGHIN L9 46 /HIGHIN 45 MIDIN 44 /MIDIN 43 LOWIN 42 RFGND 41 n.c 40 n.c 39 n.c 37 MIXOUT 0R C47 5p6 OSCLOWOUT SAWIN 36 C46 22p C45 22p GND GND P2,VRF GND R3 2k7 C11 GND GND C15 22n R4 8R2 R5 2k2 C14 3n3 R8 1M Vt C57 270p GND GND VCC R6 2k2 R7 0R L4 C13 100n GND 1 2 2 OSCGND /SAWIN 35 D2 BB659C C3 1p5 82p L2 2,5 turns C4 1p2 3 OSCMIDIN P2,VRF 34 C44 4n7 4 OSCMIDOUT P1 33 GND P1 GND P0 GND C12 1p8 L3 2 turns (small) C5 1p2 5 OSCHIGHIN IC1 TUA6045-2 (VQFN48) C43 4n7 PO 32 C6 1p2 C7 1p2 C8 1p2 C42 4n7 6 /OSCHIGHOUT RF AGC 31 R9 2k2 D3 BB555 C41 100n 30 GND RF AGC Buffer 7 OSCHIGHOUT RF AGC Buffer 8 /OSCHIGHIN SDA 29 R23 220R R22 220R R21 100R C36 47p GND C40 4n7 C39 100p GND SDA GND SCL GND CAS/EN GND Busmode J1 JUMPER 1X2 GND C9 100n 9 VCC SCL 28 68nH R10 0R L5 1u2H R11 0R 10 SAWOUT CAS/EN 27 C38 100p C37 47p C35 11 /SAWOUT DC/DC Clock X_TAL Buff IFAMPAGC Busmode X_TAL OUT 26 IN IN /IFOUT GND 3 GND 12 GND IFIN IFIN X_tal in 25 C34 R20 0R np X3 SMA 4n7 OUT OUT SAW1 X6966D IFOUT VDD VT GND C17 CP GND GND GND GND GND GND GND 13 14 15 16 17 18 19 20 21 22 23 24 Q1 C33 39p 4MHz C32 39p SIP5D 5 4 2p7 np C16 GND GND 6 7 C19 10n C20 1n C21 1n C23 6n8 GND2 R17 0R C31 1n C18 2p7 GND 1 C22 2 12p 3 VCC C28 GND R13 C24 100k 33p GND2 C29 100n R12 10k GND V1 BC847 100n L6 68nH GND X2 GND SMA R19 np L8 L7 1mH np R18 D4 BAS 70-02W C30 100n GND2 220nH VCC X1 SMA IF GND GND 4 /IFOUT nc. GND 5 GND IFOUT TR1 TOKO(A1010)-TRANSFORMER GND IFAMPAGC R14 10K C25 100n GND R15 10K D5 Z33 C26 100n GND2 R16 33k C27 22n GND2 PLL GND2 J3 SDA SCL GND CAS/EN STOCKO 4pol Figure 6 Circuit diagram for L-Band application Data Sheet 28 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference 5 5.1 5.1.1 Reference Electrical Data Absolute Maximum Ratings Attention: The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 4 # 1. 2. 3. 4. 5. PLL 6. 7. 8. 9. Bus input/output SDA CP VCP ICP VSDA VSCL -0.3 -0.3 -0.3 -0.3 -10 -2 -10 -20 Bus output current SDA ISDA(L) -0.3 3 1 5.5 10 5.5 5.5 35 0 2 0 0 20 29 Absolute Maximum Ratings Symbol VCC TA TJ TStg RTHJA Limit Values min. max. 5.5 +85 +125 +125 39 V °C °C °C K/W exposed GND pad soldered exposed GND pad soldered -0.3 -40 -40 -40 Unit Remarks Parameter Supply voltage Ambient temperature Junction temperature Storage temperature Thermal resistance junction to ambient V mA V mA V V V mA mA mA mA mA Revision 3.1, 2006-12-19 open drain 10. Bus input SCL 11. Chip address switch AS VAS 12. VCO tuning output (loop VVT filter) 13. PMOS port output current of P0, P1 14. PMOS port output current of P2,VRF IP(L) IP(L) open drain analog voltage digital switch tmax = 0.1 s at 5.5 V 15. Total port output current ΣIP(L) of PMOS ports 16. DC/DC output current Data Sheet IDC/DC TUA 6045-2 TAIFUN 3 Reference # Parameter Symbol Limit Values min. Mixer-Oscillator 17. Mix inputs LOW band 18. Mix inputs MID/HIGH 19. band 20. VCO base voltage VLOW VMID/HIGH IMID/HIGH VB -5 -0.3 -0.3 3 2 6 3 V V mA V LOW, MID and HIGH band oscillators LOW, MID and HIGH band oscillators max. Unit Remarks 21. VCO collector voltage VC 5.5 V 22. Voltage on all other Vmax inputs, outputs, except GNDs ESD-Protection 23. all pins VESD -0.3 VCC V 2 kV 5.1.2 Table 5 # 1. 2. 3. 4. 5. Operating Range Operating Range Symbol VCC TA N fMIXL fMIXM Limit Values min. max. +5.5 +85 65535 200 500 MHz MHz V °C nominal 3.3 V exposed GND pad soldered +3.0 -20 240 30 130 Unit Remarks Parameter Supply voltage Ambient temperature Programmable divider factor LOW mixer input frequency range MID band mixer input frequency range Data Sheet 30 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference # 6. 7. 8. 9. Parameter Symbol Limit Values min. HIGH band mixer input fMIXH frequency range LOW oscillator frequency range MID band oscillator frequency range HIGH band oscillator frequency range fOL fOM fOH 350 65 165 400 max. 1500 250 530 1550 MHz MHz MHz MHz Unit Remarks 5.1.3 Table 6 # AC/DC Characteristics AC/DC Characteristics, TA = 25°C, VCC = 3.3V Symbol min. Limit Values typ. 39 47 54 64 IMIX IVDD Istby 7 8 2.6 max. mA mA mA mA mA mA mA VGA V1,V0=11, SAW S1,S0=11 VGA V1,V0=10, SAW S1,S0=10 VGA V1,V0=01, SAW S1,S0=01 VGA V1,V0=00, SAW S1,S0=00 Mixer current Digital part bias, bus-interface and crystal oscillator active full standby IIC mode full standby 3-wire mode Revision 3.1, 2006-12-19 Parameter1) Unit Test Conditions ■ Supply 10. Current consumption in 11. active mode 12. 13. 14. 15. 16. Current consumption in stand-by mode 17. 18. IVCC 170 7 µA µA Data Sheet 31 TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. Digital Part PLL Crystal oscillator connections XTAL 19. Crystal frequency 20. Crystal resistance 21. 22. Crystal oscillator transconductance 23. Oscillator 24. impedance 25. Buffer output frequency gm,XTAL YXTALOSC fXTALIO 0.4 0 50 200 400 800 VACin 1 50 0.4 3 200 -850 -150 -200 16 100 fXTAL RXTAL 3.2 4.0 16 270 90 MHz Ω Ω 4 MHz, 2x39pF 16 MHz, 2x18pF Limit Values typ. max. Unit Test Conditions ■ -600 µA/V VOUT = 0.9V VIN = 0.8 to 1.0V µA/V 4 MHz, 2x39pF µA/V 16 MHz, 2x18pF MHz Divider ratios 1, 2, 4, 8 mV mVpp XTAL3,XTAL2=0,1 mVpp XTAL3,XTAL2=1,0 mVpp XTAL3,XTAL2=1,1 Vpp Amp off mVpp Amp on 32.7 V 26. XTAL Buffer output Vlow low voltage 27. Buffer signal 28. voltage 29. 30. External input 31. signal voltage VAC Tuning voltage output VT (open collector) 32. Output voltage VTL when the loop is closed, (test mode in normal operation) Ports 33. Standard Ports (PMOS) 34. Output saturation voltage 35. Voltage refered port Data Sheet Imax Vmax Imax -10 0.25 -2 0.4 mA V mA 32 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. 36. Voltage refered port V0 V1 ... V26 V27 THigh 1 1 250 10 Limit Values typ. 0 0.1 2.6 2.7 127 127 µA Ω max. V V V V Multiple of crystal oscillator period Multiple of crystal oscillator period Functional Range 0-2V Unit Test Conditions ■ DC/DC clock generator 37. Programmable high 38. Programmable low TLow 39. Output high current Ihigh 40. Output low impedance Rlow Analog Part without IF AGC LOW band mixer and SAW driver at power level S1,S0=10 41. RF frequency 42. Voltage gain fRF GV 44.25 21 24 170.25 MHz picture carrier2) 27 dB fRF = 48.25 MHz to 154.25 MHz see 5.6.1 on page 59 43. Noise figure NF 8 10 dB fRF = 48.25 MHz to 154.25 MHz see 5.6.4 on page 60 44. SAWOUT output Vo voltage causing 0.8% of crossmodulation in channel 45. Input IP3 IIP3 111 dBµV fRF = 48.25 MHz to 154.25 MHz see 5.6.6 on page 61 120 dBµV fRF1 = 48.25 MHz, fRF2 = 49.25 MHz, PRF1 = PRF2 dBµV fRF1 = 154.25 MHz, fRF2 = 155.25 MHz, PRF1 = PRF2 46. 120 Data Sheet 33 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. 47. Output voltage Vo causing 1 dB compression 48. Local oscillator FM FMI2C caused by I2C communication 49. (N+5) - 1 MHz pulling 50. Input impedance 51. Zi = (Rp || 1/jωCp) 52. RF frequency 53. Voltage gain N+5 - 1 MHz Rp Cp fRF GV 154.25 31 34 77 80 Limit Values typ. 125 max. dBµV fRF = 48.25 MHz to 154.25 MHz 2.12 kHz fRF = 154.25 MHz3) Unit Test Conditions ■ dBµV fRFw = 69.25 MHz, fOSC = 108.15 MHz, fRFu = 108.25 MHz4) kΩ pF parallel equivalent circuit at 100 MHz5) 1 2 Mid band mixer and SAW driver at power level S1,S0=10 454.25 MHz picture carrier2) 37 dB fRF = 161.25 MHz to 439.25 MHz see 5.6.2 on page 59 54. Noise figure (not corrected for image) NF 6 8 dB fRF = 161.25 MHz to 439.25 MHz see 5.6.5 on page 61 55. SAWOUT output Vo voltage causing 0.8% of crossmodulation in channel 56. Input IP3 IIP3 110 dBµV fRF = 161.25 MHz to 439.25 MHz see 5.6.7 on page 62 110 dBµV fRF1 = 161.25 MHz, fRF2 = 162.25 MHz, PRF1 = PRF2 dBµV fRF1 = 439.25 MHz, fRF2 = 440.25 MHz, PRF1 = PRF2 dBµV fRF = 161.25 MHz to 439.25 MHz 2.12 kHz fRF = 439.25 MHz3) 57. 108 58. Output voltage Vo causing 1 dB compression 59. Local oscillator FM FMI2C caused by I2C communication Data Sheet 34 125 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. 60. (N+5) - 1 MHz pulling 61. Input impedance 62. Zi = (Rs + jωLs) 63. RF frequency 64. Voltage gain N+5 - 1 MHz Rs Ls fRF GV 399.25 31 34 77 Limit Values typ. 80 max. dBµV fRFw = 359.25 MHz, fOSC = 398.15 MHz, fRFu = 398.25 MHz4) Ω nH fRF = 161.25 MHz to 439.25 MHz5) Unit Test Conditions ■ 35 8 HIGH band mixer and SAW driver at power level S1,S0=10 863.25 MHz picture carrier2) 37 dB fRF = 447.25 MHz to 863.25 MHz see 5.6.2 on page 59 65. Noise figure (not corrected for image) NF 6 8 dB fRF = 447.25 MHz to 863.25 MHz see 5.6.5 on page 61 66. SAWOUT output Vo voltage causing 0.8% of crossmodulation in channel 67. Input IP3 IIP3 110 dBµV fRF = 447.25 MHz to 863.25 MHz see 5.6.7 on page 62 106 dBµV fRF1 = 447.25 MHz, fRF2 = 448.25 MHz, PRF1 = PRF2 dBµV fRF1 = 863.25 MHz, fRF2 = 864.25 MHz, PRF1 = PRF2 dBµV fRF = 447.25 MHz to 863.25 MHz 2.12 kHz fRF = 863.25 MHz3) 68. 108 69. Output voltage Vo causing 1 dB compression 70. Local oscillator FM FMI2C caused by I2C communication 71. (N+5) - 1 MHz pulling 72. Input impedance 73. Zi = (Rs + jωLs) N+5 - 1 MHz Rs Ls 35 125 77 80 dBµV fRFw = 823.25 MHz, fOSC = 862.15 MHz, fRFu = 862.25 MHz4) Ω nH fRF = 447.25 MHz to 863.25 MHz5) 35 8 Data Sheet Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. 74. RF frequency 75. Voltage gain fRF GV 1452 29 32 Limit Values typ. max. 1492 MHz picture carrier2) 35 dB fRF = 1452 MHz to 1492 MHz see 5.6.2 on page 59 Unit Test Conditions ■ HIGH band mixer and SAW driver in L-Band application (see 4.3 on page 28) 76. Noise figure (not corrected for image) LOW band oscillator 77. Oscillator frequency 78. Phase noise, carrier to noise sideband 79. NF 8 10 dB fRF = 1452 MHz to 1492 MHz see 5.6.5 on page 61 fOSC ΦOSC 80 -84 210 -77 MHz 6) dBc/ ±1 kHz frequency Hz offset, wide loop, worst case in the frequency range dBc/ ±10 kHz frequency Hz offset, narrow loop, worst case in the frequency range -92 -88 80. -112 -106 dBc/ ±100 kHz Hz frequency offset, worst case in the frequency range dBc dBc VRipple = 20 mVpp, fRipple = 1 kHz7) VRipple = 20 mVpp, fRipple = 100 kHz7) 6) RSC 81. Ripple susceptibility of VCC 82. MID band oscillator 83. Oscillator frequency fOSC 201 -22 -50 493 MHz Data Sheet 36 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. 84. Phase noise, carrier to noise sideband 85. ΦOSC Limit Values typ. -82 max. -75 dBc/ ±1 kHz frequency Hz offset, wide loop, worst case in the frequency range dBc/ ±10 kHz frequency Hz offset, narrow loop, worst case in the frequency range Unit Test Conditions ■ -92 -88 86. -112 -106 dBc/ ±100 kHz Hz frequency offset, worst case in the frequency range dBc dBc VRipple = 20 mVpp, fRipple = 1 kHz7) VRipple = 20 mVpp, fRipple = 100 kHz7) 6) 87. Ripple RSC susceptibility of VCC 88. HIGH band oscillator 89. Oscillator frequency 90. Phase noise, carrier to noise sideband 91. fOSC ΦOSC 435 -25 -55 905 -80 -73 MHz dBc/ ±1 kHz frequency Hz offset, wide loop, worst case in the frequency range dBc/ ±10 kHz frequency Hz offset, narrow loop, worst case in the frequency range -90 -86 92. -110 -106 dBc/ ±100 kHz Hz frequency offset, worst case in the frequency range dBc dBc VRipple = 20 mVpp, fRipple = 1 kHz7) VRipple = 20 mVpp, fRipple = 100 kHz7) RSC 93. Ripple susceptibility of VCC 94. -30 -55 HIGH band oscillator in L-Band application (see 4.3 on page 28) Data Sheet 37 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. 95. Oscillator frequency 96. Phase noise, carrier to noise sideband SAW driver 97. Voltage gain 98. Input impedance 99. Zi = (Rp || 1/jωCp) GV RP CP 20 450 5 65 20 -66 -60 dB Ω pF Ω nH dBc fIF = 36 MHz to 54 MHz parallel equivalent circuit at 36 MHz5) series equivalent circuit at 36 MHz5) fOSC 1488 -85 Limit Values typ. max. 1528 MHz -80 6) Unit Test Conditions ■ dBc/ ±10 kHz frequency Hz offset, narrow loop, fRF = 1452 MHz to 1492 MHz 100. Output impedance RS 101. Zo = (Rs + jωLs) LS Rejection at the SAW driver output 102. Level of divider INTDIV interferences in the IF signal 103. Crystal oscillator interferences rejection INTXTAL VOUT = 100 dBµV8) -66 -60 dBc VOUT = 100 dBµV9) 104. Reference INTREF frequency rejection 105. Channel S02 beat INTS02 RF AGC output 106. RF AGC take-over AGCTOP point wide band wide (RF input) 107. RF AGC take-over AGCTOP point narrow band narrow (SAWOUT) 108. Source current 1 109. Source current 2 IAGCfast IAGCslow 87 77 103 -66 -60 -60 -57 dBc dBc VOUT = 100 dBµV10) fRFpix = 76.25 MHz, VRFpix = 80 dBµV11) 99 89 115 dBµV LOW Band MID, HIGH Band dBµV 9.0 300 100 38 µA nA µA Revision 3.1, 2006-12-19 110. Peak sink to ground IAGCpeak Data Sheet TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. 111. RF AGC leakage current 112. RF AGC output voltage 113. AGCLEAK VAGCmax VAGCmin -50 VCC0.25 0 Limit Values typ. max. 50 VCC nA V 0 < VAGC < VCC maximum level minimum level Unit Test Conditions ■ 0.25 V 0.5 dB 114. RF voltage range to AGCSLIP switch the AGC from active to inactive mode RF AGC buffer output 115. RF AGC buffer output current Imax 100 200 100 200 0 2 mA mV mV mV mV V Iload = 1mA Iload = 2mA Iload = 1mA Iload = 2mA Power down 116. Saturation voltage VSat_low 117. low 118. Saturation voltage VSat_high 119. high 120. RF AGC Buffer output voltage IF amplifier 121. Voltage gain 122. 123. Maximum IF input level Gmax Gmin VIF/IF AGCOFF 65 9 102 dB dB VIFAGC ≥ 2.5 V VIFAGC ≤ 0.2 V dBµV min. gain, fIF/IF = 36 MHz (sine), VIFAGC = 0.2 V, VOUT/OUT = 1 Vpp max. gain, fIF/IF = 36 MHz (sine), VIFAGC = 2.5 V, VOUT/OUT = 1 Vpp kΩ pF fIF/IF = 36 MHz, parallel equivalent circuit5) Revision 3.1, 2006-12-19 124. Minimum IF input level VIF/IF 46 125. Input impedance 126. Data Sheet RIF/IF CIF/IF 39 2 1.5 TUA 6045-2 TAIFUN 3 Reference # Parameter1) Symbol min. 127. Low end cutoff frequency (-1 dB) 128. High end cutoff frequency (-1 dB) fL Limit Values typ. max. 25 MHz VIF/IF = 60 dBµV, RLOAD ≥ 5 kΩ, CLOAD ≤ 1.5 pF, MHz VOUT/OUT = 1 Vpp at fIF/IF = 36 MHz (sine) dBc dBc dBc fIF/IF1 = 37 MHz, fIF/IF2 = 38 MHz, VIF/IF1 = 90 dBµV, VIF/IF2 = 90 dBµV RLOAD=1 kΩ, CLOAD = 10pF, VOUT/OUT = 1 Vpp fIF/IF1 = 37 MHz, fIF/IF2 = 38 MHz, VIF/IF1 = 90 dBµV, VIF/IF2 = 90 dBµV RLOAD ≥ 15 kΩ, CLOAD = 1.5pF, VOUT/OUT = 1 Vpp Unit Test Conditions ■ fH 65 129. Intermodulation V1,V0 = 00 (5.0mA) C/IM3 V1,V0 = 01 (3.6mA) C/IM3 V1,V0 = 10 (2.1mA) C/IM3 -59 -58 -56 -50 -50 -50 130. Intermodulation V1,V0 = 11 (1.1mA) C/IM3 -56 -50 dBc 131. Third order output OIP3 intercept point V1,V0 = 00 (5.0mA) 133 dBµV fIF/IF1 = 37 MHz, fIF/IF2 = 38 MHz, VIF/IF1 = 90 dBµV, VIF/IF2 = 90 dBµV RLOAD = 1 kΩ, CLOAD =10 pF, VOUT/OUT = 1 Vpp dB fIF/IF = 36 MHz (sine), VIF/IF = 60 dBµV, VOUT/OUT = 1 Vpp, BW = 8 MHz max. gain fOUT/OUT = 36 MHz, series equivalent circuit5) 132. Signal to noise ratio SNR 43 133. Noise figure 134. Output impedance RIF/IF 135. LIF/IF 10 90 120 150 dB Ω nH Data Sheet 40 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference 1) Values are referred to Figure 4.2 "Application circuit for hybrid application" on Page 27 and fIF = 36 MHz, unless stated otherwise. 2) The RF frequency range is defined by the oscillator frequency range and the intermediate frequency (IF). 3) Local oscillator FM modulation resulting from I2C communication is measured at the IF output using a modulation analyzer with a peak to peak detector ((P+ + P-) / 2) and a post detection filter 20 Hz - 100 kHz. The I2C messages are sent to the tuner in such a way that the tuner is addressed but the content of the PLL registers are not altered. The refresh interval between each data set shall be 20 ms to 1 s. 4) (N+5) -1 MHz is defined as the input level of channel N+5, at frequency 1 MHz lower, causing 100 kHz FM sidebands 30 dB below the wanted carrier. 5) Impedance measured with differential 2-port measurement at input or output. Input and output pins directly connected to measurement equipment with 50 Ω strip lines. 6) Limits are related to the tank circuit used in the application board. Frequency bands may be adjusted by the choice of external components. 7) The supply ripple susceptibility is a sideband measurement using a spectrum analyzer connected to the IF output. An unmodulated RF signal with a level of 80 dBµV is applied to the test board RF input. A sinewave signal with a defined frequency is superposed onto the supply voltage (see Figure 16 "Ripple susceptibility measurement" on Page 62). The specified value is the worst case in the frequency range. 8) This is the level of divider interferences close to the IF frequency. For example channel S3: fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. The rejection has to be greater than 60 dB for an SAW driver output of 100 dBµV. 9) Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. The rejection has to be greater than 60 dB for an SAW driver output of 100 dBµV. 10) The reference frequency rejection is the level of reference frequency sidebands (e.g. 62.5 kHz) related to the carrier. The rejection has to be greater than 60 dB for an SAW driver output of 100dBµV. 11) Channel S02 beat is the interfering product of fRFpix, fIF and fOSC of channel S02, fBEAT = 37.35 MHz. The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC. 5.2 Table 7 Bus Interface Pin Function BUSMODE bus mode select 0 1 or open data in/out clock in SDA / Data serial data SCL / Clock clock CAS / EN I2C: chip address select, 3-W: enable four chip addresses 1) 0: chip is addressed Pin Designation Function I2C mode 3-Wire mode 1) see Table 8 Chip Address Organization in I2C Mode on page 42, see Table 9 Address selection in I2C Mode on page 42 Data Sheet 41 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 8 Name Write Mode Address Byte Read Mode Address Byte Chip Address Organization in I2C Mode Byte ADB ADB MSB 1 1 bit6 1 1 bit5 0 0 bit4 0 0 bit3 0 0 bit2 MA1 MA1 bit1 MA0 MA0 LSB R/W=0 R/W=1 Table 9 Address selection in I2C Mode Chip Address (Hex) Voltage at pin CAS/EN (0 to 0.1) x VVCCD open circuit or (0.2 to 0.3) x VVCCD (0.4 to 0.6) x VVCCD (0.9 to 1) x VVCCD MA1 0 0 1 1 MA0 0 1 0 1 Write Mode C0 C2 C4 C6 Read Mode C1 C3 C5 C7 Table 10 Function Sub Addresses of Write Data Registers Hex MSB 00 01 02 03 04 05 06 0 0 0 0 0 0 0 S6 0 0 0 0 0 0 0 S5 0 0 0 0 0 0 0 S4 0 0 0 0 0 0 0 S3 0 0 0 0 0 0 0 S2 0 0 0 0 1 1 1 S1 0 0 1 1 0 0 1 LSB 0 1 0 1 0 1 0 Main Divider (N) Control bytes Ref. Divider (R) AGC control, IF signal processing control DC-DC converter not used Mode bytes, stand by, test Data Sheet 42 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 11 Function Status Chip Code Sub Addresses of Read Data Registers Hex MSB 80 8E 8F 1 1 1 S6 0 0 0 S5 0 0 0 S4 0 0 0 S3 0 1 1 S2 0 1 1 S1 0 1 1 LSB 0 0 1 Revision Code 5.3 Table 12 Bus Data Format Bus Data Format I2C-bus Write Mode I2C-bus Read Mode 3W-bus Write Mode 3W-bus Read Mode Bit STA 1 1 0 0 0 MA0 MA1 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 LSB sub address (Write) 00H...06H MSB LSB chip address (Write) MSB Function Bit STA 1 1 0 0 0 MA0 MA1 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 LSB sub address (Read) 80H, 8EH, 8FH MSB S7 S6 S5 S4 S3 S2 S1 S0 LSB sub address (Write) 00H...06H MSB S7 S6 S5 S4 S3 S2 S1 S0 LSB sub address (Read) 80H 8EH, 8FH MSB LSB chip address (Write) MSB Function Bit Function Bit Function Data Sheet 43 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference I2C-bus Write Mode I2C-bus Read Mode 3W-bus Write Mode 3W-bus Read Mode Bit ACK DX ... D5 D4 D3 D2 D1 D0 ACK STO 1) Function Bit ACK Function Bit Function Bit Function STA restart MSB 1 1 data in X...0 (X=7,15 or 23) 1) 0 0 0 MA0 MA1 LSB 1 ACK DX ... D5 D4 D3 2) MSB DX ... D5 D4 D3 D2 D1 MSB DX ... D5 D4 D3 D2 D1 MSB chip address (Read) data in X...0 (X=7,15 or 23) data out X...0 (X=7 or 15) LSB MSB D0 LSB D0 LSB after each byte an acknowledge is generated by TUA 6045. after each byte an acknowledge is generated by the processor. TUA 6045 keeps data line high. data out X...0 (X=7 or 15) 2) D2 D1 D0 1 STO LSB STA: Start condition, STO: Stop condition, ACK: Acknowledge from TUA 6045. Data Sheet 44 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference 5.4 Bus Timing BUSMODE = 0 tBUF SDA tLOW tR SCL P S tHD.STA tHD.DAT tHIGH tSU.DAT tHD.STA S tSU.STA tSU.STO P tF tSP S - START condition P - STOP condition Figure 7 I2C Bus BUSMODE = 1 DATA tLOW tR CLOCK tWHEN ENABLE S tSU.SCLENA P tSU.SCLENA tHD.STA tHD.DAT tHIGH tSU.DAT tSU.STO tF tSP Figure 8 3-Wire Bus Data Sheet 45 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 13 Bus Timing Symbol VIL VIH VHys Limit Values min. max. 0.54 5.5 V V V 50 ns -0.5 1.26 0.15 0 Unit # Parameter 1. LOW level input voltage (SDA, SCL, CAS/EN, BUSMODE) 2. HIGH level input voltage (SDA, SCL, CAS/EN, BUSMODE) 3. Hysteresis of Schmitt trigger inputs 4. Pulse width of spikes tSP which must be suppressed by the input filter 5. LOW level output voltage (SDA), only I2C-bus at 3mA sink current at 6mA sink current VOL 0 20+0.1Cb1) 0.4 0.6 250 V V ns 6. Output fall time from VIH min to VIL max with tOF a bus capacitance from 10pF to 400pF with up to 3mA sink current at VOL 7. SCL clock frequency 8. Bus free time between a STOP and START condition 2) fSCL tBUF 0 1.3 0.6 400 - kHz µs µs 9. Hold time (repeated) START/ENABLE tHD.STA ON condition. After this period, the first clock pulse is generated. 10. LOW period of the SCL clock pulse 11. HIGH period of the SCL clock pulse 12. Set-up time for a repeated START condition 2) 13. Data hold time 14. Data set-up time 15. Rise time, fall time of SDA and SCL signals 16. Set-up time for STOP/ENABLE OFF condition tLOW tHIGH tSU.STA tHD.DAT tSU.DAT tR, tF tSU.STO 1.3 0.6 0.6 0 100 20+0.1Cb1) 0.6 300 - µs µs µs ns ns ns µs Data Sheet 46 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference # Parameter 17. Setup time CAS/EN to SDA 18. Setup time SCL to CAS/EN 19. H-pulse width (CAS/EN) for new data protocol 3) 20. Capacitive load for each bus line 3) Symbol tSU.ENASD A Limit Values min. 0.6 0.6 0.6 -max. 400 Unit µs µs µs pF tSU.SCLEN A tWHEN Cb 1) Cb = capacitance of one bus line in pF. Note that the maximum tF for the SDA and SCL bus lines quoted in table above (300ns) is longer than the specified maximum tOF for the output stages (250ns).This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tF. 2) only for I2C bus mode. 3) only for 3-Wire bus mode. Data Sheet 47 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference 5.5 5.5.1 Table 14 Data Byte Specification, Function and Defaults Write Data Registers Subaddress 00H, Main Divider Bits V 2 2 2 2 15 14 Bit Symbol 15 N15 14 N14 13 N13 12 N12 11 N11 10 N10 9 N9 8 N8 7 N7 6 N6 5 N5 4 N4 3 N3 2 N2 1 N1 0 N0 Function Description Synthesizer N-counter programmable divider bits: Defaults 0 0 0 1 1 Default 1 divider 1 ratio 0 N= 1 79061) 1 1 0 0 0 1 0 213 12 11 210 29 28 27 26 25 2 4 3 N = 2 x N15 + ... + N0 15 N = 240 ... 65535 2 22 (internal A-counter 21 A = 0 ... 15)) 20 1) Default: fRF = 458MHz with fref = 62.5kHz, f IF = 36.125MHz. Data Sheet 48 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 15 Bit Symbol 15 P2_4 ... P2_0 14 P2_4 13 P2_3 12 P2_2 11 P2_1 10 P2_0 9 P1 8 P0 7 BS1 00000 11011 111X1 11110 11100 0 1 0 1 BS1 BS0 0 0 6 BS0 1 1 5 CP3 4 CP2 3 CP1 2 CP0 1 ABL1 ABL ABL 1 0 0 0 0 ABL0 1 1 Data Sheet Subaddress 01H, Control Bytes Bits V Function not used analog output 0V to 0V 2.7 to 2.7V V on (Vcc) standard port function 1 1 1 1 1 Port 1 current off Port 1 current on Portswitch Band switch selection Osc. 3 + Mix 3 on HIGH Osc. 1 + Mix 1 on LOW Osc. 2 + Mix 2 on MID Osc. 3 + Mix 2 on MID, HIGH Osc. /3 Synth. charge600 µA pump current 300 µA CP=CP0+CP1+C 150 µA P2+CP3 75 µA Anti-Backlash pulse width of phase detector PD Pulse width 2.2 ns 3.2 ns 4.4 ns 5.6 ns 49 Revision 3.1, 2006-12-19 Description not used Defaults 0 off (50k to GND) standard port function off (switch to GND) Portswitch 0 0 BS1 BS0 Port 0 current off Port 0 current on 0 1 0 1 0 0 0 0 1 0 ABL ABL 1 0 0 1 0 1 0 1 TUA 6045-2 TAIFUN 3 Reference Table 16 Bit Symbol 15 14 RFAGC B_OFF 13 XTAL3 Subaddress 02H, Reference Divider R and Crystal Oscillator Control Bits V Function not used Description not used Defaults 0 0 XTA XTA L3 L2 RF AGC buffer off disable RF AGC buffer XTA XTA L3 L2 0 0 0 1 0 1 XTAL I/O control output off, input on output 200 mVpp output 400 mVpp output 800 mVpp XTAL I/O control output mode XTAL3 OR Fout/1 XTAL2 =1 Fout/2 Fout/4 Fout/8 XTAL I/O control input mode XTAL3=0 XTAL_IN XTAL2=0 XTAL_IN XTAL_Buff XTAL_Buff+Amp 12 XTAL2 11 XTAL1 1 1 1 1 XTA XTA L1 L0 0 0 1 1 0 1 0 1 XTA XTA L1 L0 0 0 10 XTAL0 XTA XTA L1 L0 0 0 1 1 0 1 0 1 XTA XTA L1 L0 0 0 Data Sheet 50 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Bit Symbol 9 R9 8 R8 7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0 Bits V 2 2 2 2 2 2 2 9 8 Function Synthesizer R-counter Description Synthesizer R-counter programmable divider bits: R= 2 x R9 + ... + R0 9 Defaults 0 0 0 1 Default div. ratio 0 0 R=64 0 0 0 0 27 6 25 4 3 22 1 0 R = 2 ... 1023 Data Sheet 51 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 17 Bit Symbol 15 SW Subaddress 03H, AGC control and IF Signal Processing Control Bits 0 1 V Function IF Switch Description normal mode bypass mixer output tank Loop thru control normal mode bypass SAW driver stage VGA output power control quiescent current V1 of emitter follower per side 5.0 mA 3.6 mA 2.1 mA 1.1 mA 1 1 S0 V0 Defaults 0 14 LP 0 1 0 13 V1 V1 V0 12 V0 0 0 1 1 0 1 0 1 S0 11 S1 S1 SAW driver power quiescent current S1 control for SAW driver stage per side 9.7 mA 6.7 mA 4.7 mA 2.1 mA RF-AGC time constant bit RF-AGC time standby mode if RF-AGC in standby (Bit6 in register 06H is set) NB-AGC control 0.3 µA 9.0 µA tristate 200 kΩ pull-up 1 10 S0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 9 ATC 8 PU 7 AL2 6 AL1 AL2 AL1 AL0 0 0 0 NB-AGC take over point don’t use AL2 AL1 AL0 Data Sheet 52 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Bit Symbol 5 AL0 0 0 0 1 1 1 1 4 NBE Bits 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 V Function Description 115 dBµV 112 dBµV (default) don’t use 109 dBµV 106 dBµV 103 dBµV don’t use Disable NB-AGC Narrowband level detector detector active Narrowband level detector does not affect AGC Disable WB-AGC Wideband level detector detector active Wideband level detector does not affect AGC WB-AGC control LOW/MID/HIGH take over point 87 / 77 / 77 dBµV 90 / 80 / 80 dBµV 93 / 83 / 83 dBµV 96 / 86 / 86 dBµV 99 / 89 / 89 dBµV don’t use don’t use don’t use 0 1 0 WB WB WB 2 1 0 Defaults 0 1 0 0 3 WBE 0 1 0 2 WB2 1 WB1 0 WB0 WB WB WB 2 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Data Sheet 53 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 18 Bit Symbol 15 14 DCh_6 13 DCh_5 12 DCh_4 11 DCh_3 10 DCh_2 9 DCh_1 8 DCh_0 7 6 DCl_6 5 DCl_5 4 DCl_4 3 DCl_3 2 DCl_2 1 DCl_1 0 DCl_0 Subaddress 04H, DC-DC Converter Bits 1 26 2 2 2 2 1 26 2 2 2 2 5 5 V Function Output HIGH Description High current or tristate Output high time: High count register DCh=sum(DCh_i *2i); 2i =1 to 127 tHigh = DCh / fCrystal Defaults 0 0 0 0 0 1 0 0 24 3 2 21 0 Output LOW 24 3 2 If bit15 = 0, load count registers; Output low time: Low count register DCh=sum(DCl_i *2i); 2i =1 to 127 tLow = DCl / fCrystal 0 0 0 1 0 0 0 0 21 0 Default fDCDC = 4 MHz / (4 +16) = 200 kHz, 20% duty cycle Data Sheet 54 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 19 Bit Symbol 15 CPT Subaddress 06H, Mode Bytes, Test Mode and Standby Control Bits 0 1 V Function Description Defaults 0 Charge pump test CP is in normal mode control mode (=bipolar) CP current sink or source (=monopolar) CP = sinking current if CPT=1 CP = sourcing current if CPT=1 Ports test mode control Ports in normal mode (=bits P0, P1 to ports) Ports in test mode (=RFAGC Detector or fPD/2) Ports test output RFAGC_WB, select RFAGC_NB to P0, P1 if PT=1 fPD/2 to P0, P1 if PT=11) not used not used not used not used Integrator IFAGC SAW driver Mixer + RFAGC Ports PLL (and Rfosc/3) RF oscillator DCDC converter 14 CPP 0 1 0 13 PT 0 0 1 12 PTSEL 0 0 1 11 10 9 STBY9 8 STBY8 7 STBY7 6 STBY6 5 STBY5 4 STBY4 3 STBY3 2 STBY2 1 1 1 1 1 1 1 1 Standby for: Standby for: Standby for: Standby for: Standby for: Standby for: Standby for: Standby for: 1 1 1 1 1 1 1 1 Data Sheet 55 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Bit Symbol 1 STBY1 0 STBY0 Bits 1 1 V Function Standby for: Standby for: Description Crystal oscillator BIAS (disables all except bus) Defaults 0 0 1) P0, P1 are outputs for fref, fdiv. P0 is output for fref divided by 2. P1 is output for fdiv divided by 2. 5.5.2 Table 20 Read Data Registers Subaddress 80H, Status Bits V Function Power-on flag Lock-in flag not used RFAGC flag NB detector flag =1 if RFAGC is active (< 3V) =1 if NB detector is above threshold =0 if NB detector is below threshold Description =1 after power-on. Reset after first read of register Bit Symbol 7 POF 6 LF 5 4 RFAGC 3 RFAGC _NB =1 if lock-in 2 RFAGC _WB WB detector flag =1 if WB detector is above threshold =0 if WB detector is below threshold Port P1 input Port P0 input =1 if P1 is high =1 if P0 is high 1 P1 0 P0 Data Sheet 56 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 21 Bit Symbol 15 CC15 14 CC14 13 CC13 12 CC12 11 CC11 10 CC10 9 CC9 8 CC8 7 CC7 6 CC6 5 CC5 4 CC4 3 CC3 2 CC2 1 CC1 0 CC0 Subaddress 8EH, Chip Code “6045” Bits V 2 2 2 2 15 Function Description Defaults 0 0 0 1 0 1 1 214 13 212 11 10 29 2 2 2 2 2 2 8 7 Chip Code (binary coded) 26 5 CC = 215 x CC15 + 214 x CC14 + ... + 21 x CC1 + 20 x CC0 1 1 0 0 1 1 1 0 1 24 3 2 21 0 Data Sheet 57 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference Table 22 Bit Symbol 15 RC15 14 RC14 13 RC13 12 RC12 11 RC11 10 RC10 9 RC9 8 RC8 7 RC7 6 RC6 5 RC5 4 RC4 3 RC3 2 RC2 1 RC1 0 RC0 Subaddress 8FH, Revision Code, advanced with design steps Bits V Function Description Defaults first digit Revision Code (ASCII coded) depends on design step second digit Data Sheet 58 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference 5.6 5.6.1 Measurement Circuits Gain (GV) measurement in LOW band LOWIN SAWOUT 50 Ω Vmeas RMS Voltmeter Transformer N1 V0 C N2 V'meas 50 Ω spectrum analyser V 50 Ω Vi Device under Test SAWOUT N1 : N2 = 10 : 2 turns Figure 9 • • • • Gain (GV) measurement in LOW band Zi >> 50 Ω => Vi = 2 x Vmeas = 80 dBµV Vi = Vmeas + 6dB = 80 dBµV V0 = V’meas + 17 dB (transformer ratio N1:N2 and transformer loss) Gv = 20 log(V0 / Vi) 5.6.2 Gain (GV) measurement in MID and HIGH bands 50 Ω Vmeas RMS Voltmeter MIDIN SAWOUT HIGHIN Transformer N1 V0 C V'meas N2 50 Ω spectrum analyser V 50 Ω Vi Balun 1:1 Device under Test MIDIN SAWOUT HIGHIN N1 : N2 = 10 : 2 turns Figure 10 • • • Gain (GV) measurement in MID and HIGH bands Vi = Vmeas = 70 dBµV V0 = V’meas + 17 dB (transformer ratio N1:N2 and transformer loss Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun) Data Sheet 59 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference 5.6.3 Matching circuit for optimum noise figure in LOW band 15p 22p In 22p 1n In Out 7 turns wire Ε 0.5 mm coil Ε 5.5 mm 1n Out 50 Ω semi rigid cable 300 mm long 96 pF/m 33dB/100m 22p For fRF = 50 MHz loss = 0 dB image suppression = 16 dB Figure 11 For fRF = 150 MHz loss = 1.3 dB image suppression = 13 dB Matching circuit for optimum noise figure in LOW band 5.6.4 Noise figure (NF) measurement in LOW band Noise Source IN OUT LOWIN SAWOUT Transformer N1 C N2 Matching Circuit Device under Test SAWOUT Noise Figure Meter N1 : N2 = 10 : 2 turns NF = NFmeas - loss of matching circuit (dB) Figure 12 Noise figure (NF) measurement in LOW band Data Sheet 60 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference 5.6.5 Noise figure (NF) measurement in MID and HIGH bands Noise Source MIDIN SAWOUT HIGHIN Transformer N1 C N2 Balun 1:1 Device under Test MIDIN SAWOUT HIGHIN Noise Figure Meter N1 : N2 = 10 : 2 turns loss of balun = 1 dB NF = NFmeas - loss of balun (dB) Figure 13 Noise figure (NF) measurement in MID and HIGH bands 5.6.6 Cross modulation measurement in LOW band V' meas RMS Voltmeter V 50 Ω unwanted signal source AM = 80%, 1 kHz 50 Ω A C LOWIN SAWOUT Transformer N1 Vo C N2 IF filter 50 Ω modulation analyser Hybrid 50 Ω wanted signal source B D 50 Ω Device under Test SAWOUT N1 : N2 = 10 : 2 turns Figure 14 • • • Cross modulation measurement in LOW band V’meas = V0 - 17 dB (transformer ratio N1:N2 and transformer loss) wanted output signal at fpix, Vo = 100 dBµV unwanted output signal at fsnd Data Sheet 61 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Reference 5.6.7 Cross modulation measurement in MID and HIGH bands V' meas RMS Voltmeter V 50 Ω unwanted signal source AM = 80%, 1 kHz 50 Ω A C MIDIN SAWOUT HIGHIN Transformer N1 Vo C N2 IF filter 50 Ω modulation analyser Hybrid 50 Ω wanted signal source B D 50 Ω Balun 1:1 Device under Test MIDIN SAWOUT HIGHIN N1 : N2 = 10 : 2 turns Figure 15 • • • Cross modulation measurement in MID and HIGH bands V’meas = V0 - 17 dB (transformer ratio N1:N2 and transformer loss) wanted output signal at fpix, Vo = 100 dBµV unwanted output signal at fsnd 5.6.8 Ripple susceptibility measurement Stabilizer DC Supply 5k 1u 240 IC supply 1u Ripple 50 2* 22uF Figure 16 Ripple susceptibility measurement Data Sheet 62 Revision 3.1, 2006-12-19 TUA 6045-2 TAIFUN 3 Package PG-VQFN-48 6 Package PG-VQFN-48 Figure 17 PG-VQFN-48 Vignette Figure 18 PG-VQFN-48 Outline Drawing You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 63 Dimensions in mm Revision 3.1, 2006-12-19 www.infineon.com Published by Infineon Technologies AG