XC866L-2FR

U ser’s Manual, V 0 .2, Jan 2005 XC866 8-Bit Single Chip Microcontroller Microcontrollers Never stop thinking. Edition 2005-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2005. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. U ser’s Manual, V 0 .2, Jan 2005 XC866 8-Bit Single Chip Microcontroller Microcontrollers Never stop thinking. XC866 Revision History: Previous Version: 2005-01 V 0.2 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com XC866 Table of Contents Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4 Textual Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.5 Reserved, Undefined and Unimplemented Terminology . . . . . . . . . . . . 1-13 1.6 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.3 3 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.4.1 3.3.5 3.3.5.1 3.3.5.2 3.3.5.3 3.3.5.4 3.3.5.5 3.3.5.6 3.3.5.7 3.3.5.8 3.3.5.9 3.4 3.4.1 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Operation Register (EO) . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Control Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 2-4 2-4 2-4 2-4 2-4 2-5 2-6 2-7 2-8 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Bit-Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 XC866 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Boot ROM Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 I-1 V 0.2, 2005-01 User’s Manual XC866 Table of Contents Page 3.4.2 BootStrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.4.3 OCDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.7.1 4.7.2 5 5.1 5.2 5.2.1 5.2.2 5.2.3 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 5.6 6 6.1 6.1.1 6.1.1.1 6.1.1.2 6.1.1.3 6.1.1.4 6.1.1.5 6.1.1.6 6.2 6.3 6.3.1 6.3.2 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Wordline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 D-Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 D-Flash Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Non-maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Internal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Extended Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Interrupt Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Interrupt Request Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Interrupt Request Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 General Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 General Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Open Drain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Pull-Up/Pull-Down Device Register . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Alternate Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Alternate Output Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 User’s Manual I-2 V 0.2, 2005-01 XC866 Table of Contents 6.4 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.1 7.2 7.2.1 7.2.1.1 7.2.1.2 7.2.1.3 7.2.1.4 7.2.1.5 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.1.1 7.3.2 7.3.3 7.3.4 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.2 9 9.1 9.2 9.3 10 10.1 Page 6-19 6-19 6-21 6-24 6-24 6-26 6-28 6-28 6-31 Power Supply, Reset and Clock Management . . . . . . . . . . . . . . . . . . 7-1 Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . 7-1 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Types of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Power-Down Wake-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Clock Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description ...................................... Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-2 8-2 8-2 8-3 8-4 8-6 9-1 9-2 9-5 9-5 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 I-3 V 0.2, 2005-01 User’s Manual XC866 Table of Contents Page 10.1.1 UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.1.1.1 Mode 1, 8-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 10-2 10.1.1.2 Mode 2, 9-Bit UART, Fixed Baud Rate . . . . . . . . . . . . . . . . . . . . . 10-5 10.1.1.3 Mode 3, 9-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 10-5 10.1.2 Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.1.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.1.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.1.4.1 Baud-rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.1.5 Interfaces of UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.2 LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.2.1 LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.2.2 LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10.2.3 Baud Rate Detection of LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10.3 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . 10-19 10.3.1 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.3.1.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.3.1.2 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.3.1.3 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.3.1.4 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.3.1.5 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.3.1.6 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.3.1.7 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.3.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.3.3 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.3.4.1 Port Input Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.3.4.2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10.3.4.3 Baud Rate Timer Reload Register . . . . . . . . . . . . . . . . . . . . . . . . 10-37 10.3.4.4 Transmit and Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . 10-38 11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1 Basic Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.2 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.1.2.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.1.2.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.1.2.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.1.2.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.1.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.2 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.2.1 Auto-Reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.2.1.1 Up/Down Count Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 User’s Manual I-4 V 0.2, 2005-01 XC866 Table of Contents 11.2.1.2 Up/Down Count Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12.1 12.1.1 12.1.1.1 12.1.1.2 12.1.1.3 12.1.1.4 12.1.1.5 12.1.1.6 12.1.1.7 12.1.1.8 12.1.1.9 12.1.2 12.1.2.1 12.1.2.2 12.1.2.3 12.1.2.4 12.1.3 12.1.4 12.1.5 12.1.6 12.1.6.1 12.1.6.2 12.1.7 12.1.8 12.2 12.3 12.3.1 12.3.1.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.5.1 12.3.5.2 12.3.6 13 Page 11-14 11-16 11-17 11-17 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Timer T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Counting Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Switching Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Compare Mode of T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 Duty Cycle of 0% and 100% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 Dead-time Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 Hysteresis-Like Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Timer T13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Synchronization of T13 to T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 Sampling of the Hall Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 Brushless-DC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31 Port Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31 Timer T12 – Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35 Timer T13 – Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41 Capture/Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . . 12-45 Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57 Global Module Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57 Multi-Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-77 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 I-5 V 0.2, 2005-01 User’s Manual XC866 Table of Contents Page 13.1 Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.2.1 Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4.1 Request Source Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.4.2 Conversion Start Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.3 Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.4 Sequential Request Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.4.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.4.4.2 Request Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.4.5 Parallel Request Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.4.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.4.5.2 Request Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.4.5.3 External Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.4.5.4 Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.4.5.5 Autoscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.4.6 Wait-for-Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.4.7 Result Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.4.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.4.7.2 Limit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.4.7.3 Data Reduction Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.4.7.4 Result FIFO Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.4.7.5 Result Register View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 13.4.8.1 Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22 13.4.8.2 Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.4.9 External Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.5 ADC Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 13.6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28 13.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.7.1 General Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.7.2 Priority and Arbitration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33 13.7.3 External Trigger Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35 13.7.4 Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36 13.7.5 Input Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37 13.7.6 Sequential Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38 13.7.7 Parallel Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-44 13.7.8 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-48 13.7.9 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52 14 14.1 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 I-6 V 0.2, 2005-01 User’s Manual XC866 Table of Contents 14.2 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1.1 Hardware Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1.2 Software Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1.3 External Breaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2.1 Call the Monitor Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2.2 Activate the MBC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15.1 15.2 Page 14-3 14-3 14-4 14-5 14-6 14-6 14-6 14-6 14-7 14-9 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 User’s Manual I-7 V 0.2, 2005-01 XC866 Introduction 1 Introduction The XC866 is a member of the high-performance XC800 family of 8-bit microcontrollers. It is based on the XC800 Core that is compatible with the industry standard 8051 processor. The XC866 features a great number of enhancements to enable new application technologies through its highly integrated on-chip components, such as on-chip oscillator or an integrated voltage regulator, allowing a single voltage supply of 3.0 to 5.5 V. In addition, the XC866 is equipped with either embedded Flash memory to offer high flexibility in development and ramp-up, or compatible ROM versions to provide cost-saving potential in high-volume production. The multi-bank Flash architecture supports In-Application Programming (IAP), allowing user program to run from one bank, while programming or erasing another bank. In-System Programming (ISP) is available through the Boot ROM-based BootStrap Loader (BSL), enabling convenient programming and erasing of the embedded Flash via an external host (e.g., personal computer). Other key features of the XC866 include a Capture/Compare Unit 6 (CCU6) for the generation of pulse width modulated signal with special modes for motor control, and a 10-bit Analog-to-Digital Converter (ADC) with extended functionalities like autoscan and result accumulation for anti-aliasing filtering or for averaging. Local Interconnect Network (LIN) applications are also supported through extended UART features and the provision of LIN low level drivers for most devices. For low power applications, various power saving modes are available for selection by the user. Control of the numerous on-chip peripheral functionalities is achieved by extending the Special Function Register (SFR) address range with an intelligent paging mechanism optimized for interrupt handling. Figure 1-1 shows the functional units of the XC866. Flash or ROM 1) 8K/16K x 8 On-Chip Debug Support UART SSC Port 0 6-bit Digital I/O Boot ROM 8K x 8 XC800 Core XRAM 512 x 8 Capture/Compare Unit 16-bit Port 1 5-bit Digital I/O Compare Unit 16-bit ADC 10-bit 8-channel Port 2 8-bit Digital/Analog Input RAM 256 x 8 Timer 0 16-bit Timer 1 16-bit Timer 2 16-bit Watchdog Timer Port 3 8-bit Digital I/O 1) All ROM devices include 4K x 8 Flash Figure 1-1 User’s Manual Intro, V 0.3 XC866 Functional Units 1-1 V 0.2, 2005-01 XC866 Introduction The XC866 product family features eight devices with different configurations and program memory sizes, offering cost-effective solution for different application requirements. In general, each device contains a non-volatile 8K × 8 read-only program memory, a volatile 768 × 8 read/write data memory, four ports, three 16-bit timers, a 16-bit capture/compare unit, a 16-bit compare timer, 14 interrupt vectors (and an NMI), four priority-level interrupt structure, two serial ports, versatile fail-safe mechanisms, on-chip debugging support logic and a 10-bit ADC. The list of XC866 devices and their differences are summarized in Table 1-1. Table 1-1 Device Type Flash Device Summary Device Name XC866L-4FR XC866-4FR XC866L-2FR XC866-2FR ROM XC866L-4RR XC866-4RR XC866L-2RR XC866-2RR Flash Size 16 Kbytes 16 Kbytes 8 Kbytes 8 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes ROM Size – – – – 16 Kbytes 16 Kbytes 8 Kbytes 8 Kbytes LIN Support Yes No Yes No Yes No Yes No The term “XC866” in this document refers to all devices of the XC866 family unless otherwise stated. User’s Manual Intro, V 0.3 1-2 V 0.2, 2005-01 XC866 Introduction 1.1 Feature Summary The following list summarizes the main features of the XC866: • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers • On-chip memory – 8 Kbytes of Boot ROM – 256 bytes of RAM – 512 bytes of XRAM – 8/16 Kbytes of Flash; or 8/16 Kbytes of ROM, with additional 4 Kbytes of Flash • I/O port supply at 3.0 to 5.5 V and core logic supply at 2.5 V (generated by embedded voltage regulator) • Power-on reset generation • Brownout detection for core logic supply • On-chip OSC and PLL for clock generation – PLL loss-of-lock detection • Power saving modes – slow-down mode – idle mode – power-down mode with wake-up capability via RXD or EXINT0 – clock gating control to each peripheral • Programmable 16-bit Watchdog Timer (WDT) • Four ports – 19 pins as digital I/O – 8 pins as digital/analog input • 8-channel, 10-bit ADC • Three 16-bit timers – Timer 0 and Timer 1 (T0 and T1) – Timer 2 • Capture/compare unit for PWM signal generation (CCU6) • Full-duplex serial interface (UART) • Synchronous serial channel (SSC) • On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM • PG-TSSOP-38 pin package • Temperature range TA: – SAF (-40 to 85 °C) – SAK (-40 to 125 °C) User’s Manual Intro, V 0.3 1-3 V 0.2, 2005-01 XC866 Introduction The block diagram of the XC866 is shown in Figure 1-2. XC866 8-Kbyte Boot ROM 1) 256-byte RAM + 64-byte monitor RAM Internal Bus Port 0 XC800 Core T0 & T1 UART P0.0 - P0.5 Port 1 TMS MBC RESET VDDP VSSP VDDC VSSC P1.0 - P1.1 P1.5-P1.7 CCU6 Port 2 512-byte XRAM SSC 8/16-Kbyte Flash or ROM 2) Clock Generator 10 MHz On-chip OSC PLL Timer 2 ADC WDT Port 3 OCDS P2.0 - P2.7 XTAL1 XTAL2 VAREF VAGND P3.0 - P3.7 1) Includes 1-Kbyte monitor ROM 2) Includes additional 4-Kbyte Flash Figure 1-2 XC866 Block Diagram User’s Manual Intro, V 0.3 1-4 V 0.2, 2005-01 XC866 Introduction 1.2 Pin Configuration The pin configuration of the XC866, based on the PG-TSSOP-38 package, is shown in Figure 1-3. MBC P0.3/SCLK_1/COUT63_1 P0.4/MTSR_1/CC62_1 P0.5/MRST_1/EXINT0_0/COUT62_1 XTAL2 XTAL1 VSSC VDDC P1.6/CCPOS1_1/T12HR_0/EXINT6 P1.7/CCPOS2_1/T13HR_0 TMS P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT P0.2/CTRAP_2/TDO_0/TXD_1 P0.1/TDI_0/T13HR_1/RXD_1/COUT61_1 P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/AN0 P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/AN1 P2.2/CCPOS2_0/CTRAP_1/AN2 VDDP VSSP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 XC866 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 RESET P3.5/COUT62_0 P3.4/CC62_0 P3.3/COUT61_0 P3.2/CC61_0 P3.1/COUT60_0 P3.0/CC60_0 P3.7/EXINT4/COUT63_0 P3.6/CTRAP_0/RSTOUT P1.5/CCPOS0_1/EXINT5 P1.1/EXINT3/TDO_1/TXD_0 P1.0/RXD_0/T2EX P2.7/AN7 VAREF VAGND P2.6/AN6 P2.5/AN5 P2.4/AN4 P2.3/AN3 Figure 1-3 XC866 Pin Configuration, PG-TSSOP-38 Package (top view) User’s Manual Intro, V 0.3 1-5 V 0.2, 2005-01 XC866 Introduction 1.3 Pin Definitions and Functions After reset, all pins are configured as input with one of the following: • Pull-up device enabled (PU) • Pull-down device enabled (PD) • High impedance with both pull-up and pull-down devices disabled (Hi-Z) The functions and default states of the XC866 external pins are provided in Table 1-2. Table 1-2 Pin Definitions and Functions Symbol Pin Type Reset Function Number State P0 I/O Port 0 Port 0 is a 6-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC. Hi-Z TCK_0 T12HR_1 CC61_1 CLKOUT P0.1 14 Hi-Z TDI_0 T13HR_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input Input/Output of Capture/Compare channel 1 10 MHz On-Chip OSC Clock Output P0.0 12 JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input RXD_1 UART Receive Input COUT61_1 Output of Capture/Compare channel 1 CTRAP_2 TDO_0 TXD_1 CCU6 Trap Input JTAG Serial Data Output UART Transmit Output P0.2 13 PU P0.3 2 Hi-Z SCK_1 SSC Clock Input/Output COUT63_1 Output of Capture/Compare channel 3 MTSR_1 CC62_1 SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/Compare channel 2 P0.4 3 Hi-Z User’s Manual Intro, V 0.3 1-6 V 0.2, 2005-01 XC866 Introduction Table 1-2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State P0.5 4 Hi-Z SSC Master Receive Input/ Slave Transmit Output EXINT0_0 External Interrupt Input 0 COUT62_1 Output of Capture/Compare channel 2 MRST_1 User’s Manual Intro, V 0.3 1-7 V 0.2, 2005-01 XC866 Introduction Table 1-2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State P1 I/O Port 1 Port 1 is a 5-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC. PU PU RXD_0 T2EX EXINT3 TDO_1 TXD_0 UART Receive Input Timer 2 External Trigger Input External Interrupt Input 3 JTAG Serial Data Output UART Transmit Output P1.0 P1.1 27 28 P1.5 P1.6 29 9 PU PU CCPOS0_1 CCU6 Hall Input 0 EXINT5 External Interrupt Input 5 CCPOS1_1 CCU6 Hall Input 1 T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6 External Interrupt Input 6 CCPOS2_1 CCU6 Hall Input 2 T13HR_0 CCU6 Timer 13 Hardware Run Input P1.5 and P1.6 can be used as a software chip select output for the SSC. P1.7 10 PU User’s Manual Intro, V 0.3 1-8 V 0.2, 2005-01 XC866 Introduction Table 1-2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State P2 I Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC. Hi-Z CCPOS0_0 CCU6 Hall Input 0 EXINT1 External Interrupt Input 1 T12HR_2 CCU6 Timer 12 Hardware Run Input TCK_1 JTAG Clock Input AN0 Analog Input 0 CCPOS1_0 CCU6 Hall Input 1 EXINT2 External Interrupt Input 2 T13HR_2 CCU6 Timer 13 Hardware Run Input TDI_1 JTAG Serial Data Input AN1 Analog Input 1 CCPOS2_0 CCU6 Hall Input 2 CCU6 Trap Input CTRAP_1 AN2 Analog Input 2 AN3 AN4 AN5 AN6 AN7 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7 P2.0 15 P2.1 16 Hi-Z P2.2 17 Hi-Z P2.3 P2.4 P2.5 P2.6 P2.7 20 21 22 23 26 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z User’s Manual Intro, V 0.3 1-9 V 0.2, 2005-01 XC866 Introduction Table 1-2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State P3 I Port 3 Port 3 is a bidirectional general purpose I/O port. It can be used as alternate functions for the CCU6. Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z PD CC60_0 Input/Output of Capture/Compare channel 0 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 32 33 34 35 36 37 30 COUT60_0 Output of Capture/Compare channel 0 CC61_0 Input/Output of Capture/Compare channel 1 COUT61_0 Output of Capture/Compare channel 1 CC62_0 Input/Output of Capture/Compare channel 2 COUT62_0 Output of Capture/Compare channel 2 CTRAP_0 RSTOUT CCU6 Trap Input Reset output indication for internal reset condition in microcontroller P3.7 31 Hi-Z EXINT4 External Interrupt Input 4 COUT63_0 Output of Capture/Compare channel 3 User’s Manual Intro, V 0.3 1-10 V 0.2, 2005-01 XC866 Introduction Table 1-2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State VDDP VSSP VDDC VSSC VAREF VAGND XTAL1 XTAL2 TMS RESET MBC 18 19 8 7 25 24 6 5 11 38 1 – – – – – – I O I I I – – – – – – Hi-Z Hi-Z PD PU PU I/O Port Supply (3.0 - 5.5 V) I/O Port Ground Core Supply Output (2.5 V) Core Supply Ground ADC Reference Voltage ADC Reference Ground External Oscillator Input (backup for on-chip OSC, normally NC) External Oscillator Output (backup for on-chip OSC, normally NC) Test Mode Select Reset Input for PG-TSSOP-38 package Monitor & BootStrap Loader Control User’s Manual Intro, V 0.3 1-11 V 0.2, 2005-01 XC866 Introduction 1.4 Textual Convention This document uses the following textual conventions for named components of the XC866: • Functional units of the XC866 are shown in upper case. For example: “The SSC can be used to communicate with shift registers.” • Pins using negative logic are indicated by an overbar. For example: “A reset input pin RESET is provided for the hardware reset.” • Bit fields and bits in registers are generally referenced as “Register name.Bit field” or “Register name.Bit”. Most of the register names contain a module name prefix, separated by an underscore character “_” from the actual register name. In the example of “SSC_CON”, “SSC” is the module name prefix, and “CON” is the actual register name). • Variables that are used to represent sets of processing units or registers appear in mixed-case type. For example, the register name “CC6xR” refers to multiple “CC6xR” registers with the variable x (x = 0, 1, 2). The bounds of the variables are always specified where the register expression is first used (e.g., “x = 0 - 2”), and is repeated as needed. • The default radix is decimal. Hexadecimal constants have a suffix with the subscript letter “H” (e.g., C0H). Binary constants have a suffix with the subscript letter “B” (e.g., 11B). • When the extents of register fields, groups of signals, or groups of pins are collectively named in the body of the document, they are represented as “NAME[A:B]”, which defines a range, from B to A, for the named group. Individual bits, signals, or pins are represented as “NAME[C]”, with the range of the variable C provided in the text (e.g., CFG[2:0] and TOS[0]). • Units are abbreviated as follows: – MHz = Megahertz – µs = Microseconds – kBaud, kbit = 1000 characters/bits per second – MBaud, Mbit = 1,000,000 characters/bits per second – Kbyte = 1024 bytes of memory – Mbyte = 1,048,576 bytes of memory In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The kBaud unit scales the expression preceding it by 1000. The M prefix scales by 1,000,000 or 1,048,576, and µ scales by 0.000001. For example, 1 Kbyte is 1024 bytes, 1 Mbyte is 1024 × 1024 bytes, 1 kBaud/kbit are 1000 characters/bits per second, 1 MBaud/Mbit are 1,000,000 characters/bits per second, and 1 MHz is 1,000,000 Hz. • Data format quantities are defined as follows: – byte = 8-bit quantity User’s Manual Intro, V 0.3 1-12 V 0.2, 2005-01 XC866 Introduction 1.5 Reserved, Undefined and Unimplemented Terminology In tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. Further, types of bits and bit fields are defined using the abbreviations shown in Table 1-3. Table 1-3 Bit Function Terminology Description Register bit fields named “0” indicate unimplemented functions with the following behavior. – Reading these bit fields returns 0. – Writing to these bit fields has no effect. These bit fields are reserved. When writing, software should always set such bit fields to 0 in order to preserve compatibility with future products. Setting the bit fields to 1 may lead to unpredictable results. Certain bit combinations in a bit field can be labeled “Reserved”, indicating that the behavior of the XC866 is undefined for that combination of bits. Setting the register to undefined bit combinations may lead to unpredictable results. Such bit combinations are reserved. When writing, software must always set such bit fields to legal values as provided in the bit field description tables. The bit or bit field can be read and written. The bit or bit field can only be read (read-only). The bit or bit field can only be written (write-only). Reading always return 0. The bit or bit field can also be modified by hardware (such as a status bit). This attribute can be combined with ‘rw’ or ‘r’ bits to ‘rwh’ and ‘rh’ bits, respectively. Function of Bits Unimplemented Undefined rw r w h User’s Manual Intro, V 0.3 1-13 V 0.2, 2005-01 XC866 Introduction 1.6 Table 1-4 ADC ALU BSL CCU6 CGU CPU ECC EVR FIFO GPIO IAP I/O ISP JTAG LIN NMI OCDS PC POR PLL PSW PWM RAM ROM SFR SPI SSC UART WDT Acronyms Acronyms Analog-to-Digital Converter Arithmetic/Logic Unit BootStrap Loader Capture/Compare Unit 6 Clock Generation Unit Central Processing Unit Error Correction Code Embedded Voltage Regulator First-In First-Out General Purpose I/O In-Application Programming Input/Output In-System Programming Joint Test Action Group Local Interconnect Network Non-Maskable Interrupt On-Chip Debug Support Program Counter Power-On Reset Phase-Locked Loop Program Status Word Pulse Width Modulation Random Access Memory Read-Only Memory Special Function Register Serial Peripheral Interface Synchronous Serial Controller Universal Asynchronous Receiver/Transmitter Watchdog Timer 1-14 V 0.2, 2005-01 Table 1-4 lists the acronyms used in this document. User’s Manual Intro, V 0.3 XC866 Processor Architecture 2 Processor Architecture The XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC866 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). See Section 2.3. The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The XC866 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and SFRs. Features: • • • • • • • • • Two clocks per machine cycle architecture (for memory access without wait state) Wait state support for Flash memory Program memory download option 15-source, 4-level interrupt controller Two data pointers Power saving modes Dedicated debug mode and debug signals Two 16-bit timers (Timer 0 and Timer 1) Full-duplex serial port (UART) User’s Manual Processor Architecture, V 0.3 2-1 V 0.2, 2005-01 XC866 Processor Architecture 2.1 Functional Description Figure 2-1 shows the CPU functional blocks. The CPU consists of the instruction decoder, the arithmetic section, and the program control section. Each program instruction is decoded by the instruction decoder. This instruction decoder generates internal signals that control the functions of the individual units within the CPU. The internal signals have an effect on the source and destination of data transfers and control the arithmetic/logic unit (ALU) processing. Internal Data Memory Core SFRs External Data Memory 16-bit Registers & Memory Interface Program Memory Register Interface External SFRs ALU Opcode & Immediate Registers Multiplier / Divider Opcode Decoder Timer 0 / Timer 1 fCCLK Memory Wait Reset State Machine & Power Saving UART Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt Interrupt Controller Figure 2-1 CPU Block Diagram User’s Manual Processor Architecture, V 0.3 2-2 V 0.2, 2005-01 XC866 Processor Architecture The arithmetic section of the processor performs extensive data manipulation and consists of the ALU, ACC register, B register, and PSW register. The ALU accepts 8-bit data words from one or two sources, and generates an 8-bit result under the control of the instruction decoder. The ALU performs both arithmetic and logic operations. Arithmetic operations include add, subtract, multiply, divide, increment, decrement, BCD-decimal-add-adjust, and compare. Logic operations include AND, OR, Exclusive OR, complement, and rotate (right, left, or swap nibble (left four)). Also included is a Boolean processor performing the bit operations such as set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set-and-clear, and move to/from carry. The ALU can perform the bit operations of logical AND or logical OR between any addressable bit (or its complement) and the carry flag, and place the new result in the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit Program Counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. User’s Manual Processor Architecture, V 0.3 2-3 V 0.2, 2005-01 XC866 Processor Architecture 2.2 CPU Register Description The CPU registers occupy direct Internal Data Memory space locations in the range 80H to FFH. 2.2.1 Stack Pointer (SP) The SP register contains the Stack Pointer (SP). The SP is used to load the Program Counter (PC) into Internal Data Memory during LCALL and ACALL instructions, and to retrieve the PC from memory during RET and RETI instructions. Data may also be saved on or retrieved from the stack using PUSH and POP instructions, respectively. Instructions that use the stack automatically pre-increment or post-decrement the stack pointer so that the stack pointer always points to the last byte written to the stack, i.e., the top of the stack. On reset, the SP is reset to 07H. This causes the stack to begin at a location = 08H above register bank zero. The SP can be read or written under software control. 2.2.2 Data Pointer (DPTR) The Data Pointer (DPTR) is stored in registers DPL (Data Pointer Low byte) and DPH (Data Pointer High byte) to form 16-bit addresses for External Data Memory accesses (MOVX A,@DPTR and MOVX @DPTR,A), for program byte moves (MOVC A,@A+DPTR), and for indirect program jumps (JMP @A+DPTR). Two true 16-bit operations are allowed on the Data Pointer: load immediate (MOV DPTR,#data) and increment (INC DPTR). 2.2.3 Accumulator (ACC) This register provides one of the operands for most ALU operations. While ACC is the symbol for the accumulator register, the mnemonics for accumulator-specific instructions refer to the accumulator simply as “A”. 2.2.4 B Register The B register is used during multiply and divide operations to provide the second operand. For other instructions, it can be treated as another scratch pad register. User’s Manual Processor Architecture, V 0.3 2-4 V 0.2, 2005-01 XC866 Processor Architecture 2.2.5 Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. PSW Program Status Word Register 7 CY rw 6 AC rwh 5 F0 rwh 4 RS1 rw 3 RS0 rw 2 OV rwh Reset Value: 00H 1 F1 rwh 0 P rh Field P Bits 0 Type Description rh Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of “one” bits in the accumulator, i.e., even parity. General Purpose Flag Overflow Flag Used by arithmetic instructions Register Bank Select These bits are used to select one of the four register banks. RS1 RS0 Function 0 0 1 1 0 1 0 1 Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH F1 OV RS0 RS1 1 2 3 4 rwh rwh rw F0 AC CY 5 6 7 rwh rwh rw General Purpose Flag Auxiliary Carry Flag Used by instructions that execute BCD operations Carry Flag Used by arithmetic instructions User’s Manual Processor Architecture, V 0.3 2-5 V 0.2, 2005-01 XC866 Processor Architecture 2.2.6 Extended Operation Register (EO) The instruction set includes an additional instruction MOVC @(DPTR++),A which allows program memory to be written. This instruction may be used to download code into the program memory when the CPU is initialized and subsequently, also to provide software updates. The instruction copies the contents of the accumulator to the code memory at the location pointed to by the current data pointer, and then increments the data pointer. The instruction uses the opcode A5H, which is the same as the software break instruction TRAP (see Table 2-1). Register bit EO.TRAP_EN is used to select the instruction executed by the opcode A5H. When TRAP_EN is 0 (default), the A5H opcode executes the MOVC instruction. When TRAP_EN is 1, the A5H opcode executes the software break instruction TRAP, which switches the CPU to debug mode for breakpoint processing. EO Extended Operation Register 7 6 0 r 5 4 TRAP_EN rw 3 2 0 r Reset Value: 00H 1 0 DPSEL0 rw Field DPSEL0 Bits 0 Type Description rw Data Pointer Select 0 DPTR0 is selected. 1 DPTR1 is selected. TRAP Enable 0 Select MOVC @(DPTR++),A 1 Select software TRAP instruction Reserved Returns 0 if read; should be written with 0. TRAP_EN 4 rw 0 [3:1], [7:5] r User’s Manual Processor Architecture, V 0.3 2-6 V 0.2, 2005-01 XC866 Processor Architecture 2.2.7 Power Control Register (PCON) The CPU has two power-saving modes: idle mode and power-down mode. The idle mode can be entered via the PCON register. In idle mode, the clock to the CPU is stopped while the timers, serial port and interrupt controller continue to run using a half-speed clock. In power-down mode, the clock to the entire CPU is stopped. PCON Power Control Register 7 SMOD rw 6 5 0 r 4 3 GF1 rw 2 GF0 rw Reset Value: 00H 1 0 r 0 IDLE rw The functions of the shaded bits are not described here Field IDLE Bits 0 Type Description rw Idle Mode Enable 0 Do not enter idle mode 1 Enter idle mode General Purpose Flag Bit 0 General Purpose Flag Bit 1 GF0 GF1 2 3 rw rw User’s Manual Processor Architecture, V 0.3 2-7 V 0.2, 2005-01 XC866 Processor Architecture 2.3 Instruction Timing For memory access without wait state, a CPU machine cycle comprises two input clock periods referred to as Phase 1 (P1) and Phase 2 (P2) that correspond to two different CPU states. A CPU state within an instruction is denoted by reference to the machine cycle and state number, e.g., C2P1 is the first clock period within machine cycle 2. Memory accesses take place during one or both phases of the machine cycle. SFR writes only occur at the end of P2. An instruction takes one, two or four machine cycles to execute. Registers are generally updated and the next opcode read at the end of P2 of the last machine cycle for the instruction. With each access to the Flash memory, instruction execution times are extended by one machine cycle (one wait state), starting from either P1 or P2. Figure 2-2 shows the fetch/execute timing related to the internal states and phases. Execution of an instruction occurs at C1P1. For a 2-byte instruction, the second reading starts at C1P1. Figure 2-2 (a) shows two timing diagrams for a 1-byte, 1-cycle (1 × machine cycle) instruction. The first diagram shows the instruction being executed within one machine cycle since the opcode (C1P2) is fetched from a memory without wait state. The second diagram shows the corresponding states of the same instruction being executed over two machine cycles (instruction time extended), with one wait state inserted for opcode fetching from the Flash memory. Figure 2-2 (b) shows two timing diagrams for a 2-byte, 1-cycle (1 × machine cycle) instruction. The first diagram shows the instruction being executed within one machine cycle since the second byte (C1P1) and the opcode (C1P2) are fetched from a memory without wait state. The second diagram shows the corresponding states of the same instruction being executed over three machine cycles (instruction time extended), with one wait state inserted for each access to the Flash memory (two wait states inserted in total). Figure 2-2 (c) shows two timing diagrams of a 1-byte, 2-cycle (2 × machine cycle) instruction. The first diagram shows the instruction being executed over two machine cycles with the opcode (C2P2) fetched from a memory without wait state. The second diagram shows the corresponding states of the same instruction being executed over three machine cycles (instruction time extended), with one wait state inserted for opcode fetching from the Flash memory. User’s Manual Processor Architecture, V 0.3 2-8 V 0.2, 2005-01 XC866 Processor Architecture fCCLK Read next opcode (without wait state) C1P1 C1P2 next instruction Read next opcode (one wait state) C1P1 (a) 1-byte, 1-cycle instruction, e.g. INC A C1P2 WAIT WAIT next instruction Read 2nd byte (without wait state) C1P1 C1P2 Read next opcode (without wait state) next instruction Read 2nd byte (one wait state) Read next opcode (one wait state) C1P1 WAIT WAIT C1P2 WAIT WAIT next instruction (b) 2-byte, 1-cycle instruction, e.g. ADD A, #data Read next opcode (without wait state) C1P1 C1P2 C2P1 C2P2 next instruction Read next opcode (one wait state) C1P1 C1P2 C2P1 C2P2 WAIT WAIT next instruction (b) 1-byte, 2-cycle instruction, e.g. MOVX Figure 2-2 CPU Instruction Timing User’s Manual Processor Architecture, V 0.3 2-9 V 0.2, 2005-01 XC866 Processor Architecture Instructions are 1, 2 or 3 bytes long as indicated in the “Bytes” column of Table 2-1. For the XC866, the time taken for each instruction includes: • decoding/executing the fetched opcode • fetching the operand/s (for instructions > 1 byte) • fetching the first byte (opcode) of the next instruction (due to XC866 CPU pipeline) Note: The XC866 CPU fetches the opcode of the next instruction while executing the current instruction. Table 2-1 provides a reference for the number of clock cycles required by each instruction. The first value applies to fetching operand(s) and opcode from fast program memory (e.g., Boot ROM and XRAM) without wait state. The second value applies to fetching operand(s) and opcode from slow program memory (e.g., Flash) with one wait state inserted. The instruction time for the standard 8051 processor is provided in the last column for performance comparison with the XC866 CPU. Even with one wait state inserted for each byte of operand/opcode fetched, the XC866 CPU executes instructions faster than the standard 8051 processor by a factor of between two (e.g., 2-byte, 1-cycle instructions) to six (e.g., 1-byte, 4-cycle instructions). Table 2-1 Mnemonic CPU Instruction Timing Hex Code Bytes Number of fCCLK Cycles XC866 no ws ARITHMETIC ADD A,Rn ADD A,dir ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,dir ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,dir SUBB A,@Ri SUBB A,#data INC A INC Rn User’s Manual Processor Architecture, V 0.3 8051 1 ws 4 6 4 6 4 6 4 6 4 6 4 6 4 4 12 12 12 12 12 12 12 12 12 12 12 12 12 12 V 0.2, 2005-01 28-2F 25 26-27 24 38-3F 35 36-37 34 98-9F 95 96-97 94 04 08-0F 2-10 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 XC866 Processor Architecture Table 2-1 Mnemonic CPU Instruction Timing (cont’d) Hex Code Bytes Number of fCCLK Cycles XC866 no ws INC dir INC @Ri DEC A DEC Rn DEC dir DEC @Ri INC DPTR MUL AB DIV AB DA A ANL A,Rn ANL A,dir ANL A,@Ri ANL A,#data ANL dir,A ANL dir,#data ORL A,Rn ORL A,dir ORL A,@Ri ORL A,#data ORL dir,A ORL dir,#data XRL A,Rn XRL A,dir XRL A,@Ri XRL A,#data XRL dir,A 05 06-07 14 18-1F 15 16-17 A3 A4 84 D4 LOGICAL 58-5F 55 56-57 54 52 53 48-4F 45 46-47 44 42 43 68-6F 65 66-67 64 62 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 2 2 2 2 2 4 2 2 2 2 2 4 2 2 2 2 2 4 6 4 6 6 10 4 6 4 6 6 10 4 6 4 6 6 12 12 12 12 12 24 12 12 12 12 12 24 12 12 12 12 12 2 1 1 1 2 1 1 1 1 1 2 2 2 2 2 2 4 8 8 2 1 ws 6 4 4 4 6 4 4 8 8 4 12 12 12 12 12 12 24 48 48 12 8051 User’s Manual Processor Architecture, V 0.3 2-11 V 0.2, 2005-01 XC866 Processor Architecture Table 2-1 Mnemonic CPU Instruction Timing (cont’d) Hex Code Bytes Number of fCCLK Cycles XC866 no ws XRL dir,#data CLR A CPL A SWAP A RL A RLC A RR A RRC A MOV A,Rn MOV A,dir MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,dir MOV Rn,#data MOV dir,A MOV dir,Rn MOV dir,dir MOV dir,@Ri MOV dir,#data MOV @Ri,A MOV @Ri,dir MOV @Ri,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri 63 E4 F4 C4 23 33 03 13 DATA TRANSFER E8-EF E5 E6-E7 74 F8-FF A8-AF 78-7F F5 88-8F 85 86-87 75 F6-F7 A6-A7 76-77 90 93 83 E2-E3 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 2 2 2 2 2 4 2 2 4 4 4 4 2 4 2 4 4 4 4 4 6 4 6 4 8 6 6 8 10 8 10 4 8 6 10 6 6 6 12 12 12 12 12 24 12 12 24 24 24 24 12 24 12 24 24 24 24 3 1 1 1 1 1 1 1 4 2 2 2 2 2 2 2 1 ws 10 4 4 4 4 4 4 4 24 12 12 12 12 12 12 12 8051 User’s Manual Processor Architecture, V 0.3 2-12 V 0.2, 2005-01 XC866 Processor Architecture Table 2-1 Mnemonic CPU Instruction Timing (cont’d) Hex Code Bytes Number of fCCLK Cycles XC866 no ws MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,dir XCH A,@Ri XCHD A,@Ri CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C ACALL addr11 LCALL addr16 RET RETI AJMP addr 11 E0 F2-F3 F0 C0 D0 C8-CF C5 C6-C7 D6-D7 BOOLEAN C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 BRANCHING 11->F1 12 22 32 01->E1 2 3 1 1 2 4 4 4 4 4 8 10 4 4 8 24 24 24 24 24 1 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 2 4 4 6 4 6 4 6 8 8 8 8 6 8 12 12 12 12 12 12 24 24 24 24 12 24 1 1 1 2 2 1 2 1 1 4 4 4 4 4 2 2 2 2 1 ws 6 6 6 8 8 4 6 4 4 24 24 24 24 24 12 12 12 12 8051 User’s Manual Processor Architecture, V 0.3 2-13 V 0.2, 2005-01 XC866 Processor Architecture Table 2-1 Mnemonic CPU Instruction Timing (cont’d) Hex Code Bytes Number of fCCLK Cycles XC866 no ws LJMP addr 16 SJMP rel JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel JMP @A+DPTR JZ rel JNZ rel CJNE A,dir,rel CJNE A,#d,rel CJNE Rn,#d,rel CJNE @Ri,#d,rel DJNZ Rn,rel DJNZ dir,rel NOP MOVC @(DPTR++),A TRAP 02 80 40 50 20 30 10 73 60 70 B5 B4 B8-BF B6-B7 D8-DF D5 MISCELLANEOUS 00 A5 A5 1 1 1 2 4 2 4 4 tbd 12 – – ADDITIONAL INSTRUCTIONS 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 ws 10 8 8 8 10 10 10 4 8 8 10 10 10 10 8 10 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 8051 User’s Manual Processor Architecture, V 0.3 2-14 V 0.2, 2005-01 XC866 Memory Organization 3 Memory Organization The XC866 CPU operates in the following five address spaces: • 8 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 512 bytes of XRAM memory (XRAM can be read/written as program memory or external data memory) • a 128-byte Special Function Register area • 8/16 Kbytes of Flash program memory (Flash devices); or 8/16 Kbytes of ROM program memory, with additional 4 Kbytes of Flash (ROM devices) Figure 3-1 illustrates the memory address spaces of the 16-Kbyte Flash devices. For the 8-Kbyte Flash devices, the shaded banks are not available. FFFF H F200H F000H FFFF H F200H F000H XRAM 512 bytes XRAM 512 bytes E000H Boot ROM 8 Kbytes C000H B000H D-Flash Bank 4 Kbytes A000H 3000H Indirect Address Direct Address Special Function Registers FFH P-Flash Bank 2 4 Kbytes 2000H Internal RAM P-Flash Bank 1 4 Kbytes 1000H 80H 7FH P-Flash Bank 0 4 Kbytes 0000H 0000H Internal RAM 00H Program Space External Data Space Internal Data Space Figure 3-1 Memory Map of XC866 Flash Device 3-1 V 0.2, 2005-01 User’s Manual Memory Organization, V 0.2 XC866 Memory Organization Figure 3-2 illustrates the memory address spaces of the 16-Kbyte ROM devices. For the 8-Kbyte ROM devices, the shaded address regions are not available. FFFF H F200H F000H FFFF H F200H F000H XRAM 512 bytes XRAM 512 bytes E000H Boot ROM 8 Kbytes C000H B000H D-Flash Bank 4 Kbytes A000H 4000H Indirect Address Direct Address FFH ROM 16 Kbytes 2000H Internal RAM Special Function Registers 80H 7FH Internal RAM 0000H 0000H 00H Program Space External Data Space Internal Data Space Figure 3-2 Memory Map of XC866 ROM Device User’s Manual Memory Organization, V 0.2 3-2 V 0.2, 2005-01 XC866 Memory Organization 3.1 Program Memory The performance of the CPU is optimized with a dedicated interface for direct interfacing with the program memory without using any port pin. This means that a code fetch can occur on every rising edge of the clock. Hence, there is no concept of ‘internal’ or ‘external’ program memory as all code is fetched from a single program memory interface. 3.2 Data Memory The data memory space consists of an internal and external memory space. The labels ‘internal’ and ‘external’ for data memory are used to distinguish between the register memory and the 64-Kbyte data space accessed using ‘MOVX’ instructions. They do not imply that the external data memory is located off-chip. 3.2.1 Internal Data Memory The internal data memory is divided into two physically separate and distinct blocks: the 256-byte RAM and the 128-byte Special Function Register (SFR) area. While the upper 128 bytes of RAM and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of RAM can be accessed through either direct or register indirect addressing, while the upper 128 bytes of RAM can be accessed through register indirect addressing only. The SFRs are accessible through direct addressing. The 16 bytes of RAM that occupy addresses from 20H to 2FH are bitaddressable. RAM occupying direct addresses from 30H to 7FH can be used as scratch pad registers or used for the stack. 3.2.2 External Data Memory The 512-byte XRAM is mapped to both the external data memory area and the program memory area. It can be accessed using both ‘MOVX’ and ‘MOVC’ instructions. User’s Manual Memory Organization, V 0.2 3-3 V 0.2, 2005-01 XC866 Memory Organization 3.3 Special Function Registers The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include: • Mapping • Paging 3.3.1 Address Extension by Mapping Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 3-3. SYSCON0 System Control Register 0 7 6 5 4 0 r 3 2 Reset Value: 00H 1 0 RMAP rw Field RMAP Bits 0 Type Description rw Special Function Register Map Control 0 The access to the standard SFR area is enabled. 1 The access to the mapped SFR area is enabled. Reserved Returns 0 if read; should be written with 0. 0 [7:1] r As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software. User’s Manual Memory Organization, V 0.2 3-4 V 0.2, 2005-01 XC866 Memory Organization S ta n d a rd A re a (R M A P = 0 ) FF M o d u le 1 S F R s H S Y S C O N 0 .R M A P rw M o d u le 2 S F R s M o d u le n S F R s … ... S F R D a ta (to /fro m C P U ) 80 M a p p e d A re a (R M A P = 1 ) FF M o d u le ( n + 1 ) S F R s H H M o d u le ( n + 2 ) S F R s M o d u le m S F R s … ... 80 H D ir e c t In te rn a l D a ta M e m o ry A d d re s s Figure 3-3 Address Extension by Mapping User’s Manual Memory Organization, V 0.2 3-5 V 0.2, 2005-01 XC866 Memory Organization 3.3.2 Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the XC866 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 3-4. S F R A d d re s s (fro m C P U ) M O D _ P A G E .P A G E rw PAGE 0 SFR0 SFR1 SFRx … ... PAGE 1 SFR0 S F R D a ta (to /fro m C P U ) SFR1 SFRy … ... … ... PAGE q SFR0 SFR1 SFRz … ... M o d u le Figure 3-4 Address Extension by Paging 3-6 V 0.2, 2005-01 User’s Manual Memory Organization, V 0.2 XC866 Memory Organization In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and finally, the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can: • Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or • Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred) ST3 ST2 ST1 ST0 STNR value update from CPU Figure 3-5 Storage Elements for Paging PAGE With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC866 supports local address extension for: • • • • Parallel Ports Analog-to-Digital Converter (ADC) Capture/Compare Unit 6 (CCU6) System Control Registers User’s Manual Memory Organization, V 0.2 3-7 V 0.2, 2005-01 XC866 Memory Organization The page register has the following definition: MOD_PAGE Page Register for module MOD 7 OP w 6 5 STNR w 4 3 0 r 2 Reset Value: 00H 1 PAGE rw 0 Field PAGE Bits [2:0] Type Description rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. STNR [5:4] w User’s Manual Memory Organization, V 0.2 3-8 V 0.2, 2005-01 XC866 Memory Organization Field OP Bits [7:6] Type Description w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. Reserved Returns 0 if read; should be written with 0. 0 3 r 3.3.3 Bit-Addressing SFRs that have addresses in the form of 1XXXX000B (e.g., 80H, 88H, 90H, ..., F0H, F8H) are bitaddressable. The addresses of these bitaddressable SFRs appear in bold typeface in Table 3-1 to Table 3-9. User’s Manual Memory Organization, V 0.2 3-9 V 0.2, 2005-01 XC866 Memory Organization 3.3.4 System Control Registers The system control SFRs are used to control the overall system functionalities, such as interrupts, variable baud rate generation, clock management, bit protection scheme, oscillator and PLL control. The SFRs are located in the standard memory area (RMAP = 0) and organized into 2 pages. The SCU_PAGE register is located at B2H. It contains the page value and page control information. SCU_PAGE Page Register for System Control 7 OP w 6 5 STNR w 4 3 0 r 2 Reset Value: 00H 1 PAGE rw 0 Field PAGE Bits [2:0] Type Description rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. STNR [5:4] w User’s Manual Memory Organization, V 0.2 3-10 V 0.2, 2005-01 XC866 Memory Organization Field OP Bits [7:6] Type Description w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. Reserved Returns 0 if read; should be written with 0. 0 3 r User’s Manual Memory Organization, V 0.2 3-11 V 0.2, 2005-01 XC866 Memory Organization 3.3.4.1 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. Note that access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD. PASSWD Password Register 7 6 5 PASS wh 4 3 2 PROTECT _S rh Reset Value: 07H 1 MODE rw 0 Field MODE Bits [1:0] Type Description rw Bit Protection Scheme Control bits 00 Scheme Disabled 11 Scheme Enabled (default) Others: Scheme Enabled These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. Bit Protection Signal Status bit This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected bits. Password bits The Bit Protection Scheme only recognizes three patterns. 11000B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits. PROTECT_S 2 rh PASS [7:3] wh User’s Manual Memory Organization, V 0.2 3-12 V 0.2, 2005-01 XC866 Memory Organization 3.3.5 XC866 Register Overview The SFRs of the XC866 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Section 3.3.5.1 to Section 3.3.5.9. Note: The addresses of the bitaddressable SFRs appear in bold typeface in Table 3-1 to Table 3-9. 3.3.5.1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 3-1 Addr 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 98H 99H A2H RMAP = 0 or 1 SP Stack Pointer Register Reset: 07H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type CY rw SM0 rw SM1 rw SM2 rw DPL7 DPL6 rw rw DPH7 DPH6 rw rw SMOD rw TF1 rwh GATE1 rw TR1 rw 0 r DPL5 rw DPH5 rw 0 r TF0 rwh SP rw DPL4 DPL3 rw rw DPH4 DPH3 rw rw GF1 rw IE1 rwh GATE0 rw CPU Register Overview Bit 7 6 5 4 3 2 1 0 Register Name DPL Reset: 00H Data Pointer Register Low DPH Reset: 00H Data Pointer Register High PCON Power Control Register TCON Timer Control Register TMOD Timer Mode Register TL0 Timer 0 Register Low TL1 Timer 1 Register Low TH0 Timer 0 Register High TH1 Timer 1 Register High Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H DPL2 rw DPH2 rw GF0 rw IT1 rw 0 r DPL1 rw DPH1 rw 0 r IE0 rwh DPL0 rw DPH0 rw IDLE rw IT0 rw TR0 rw T1M rw T0M rw VAL rwh VAL rwh VAL rwh VAL rwh REN rw VAL rwh 0 r 0 r 0 r 0 r AC rwh TRAP_ EN rw ES rw PS rw PSH rw RS1 rw 0 r EX1 rw PX1 rw PX1H rw OV rwh DPSEL 0 rw EX0 rw PX0 rw PX0H rw P rh TB8 rw RB8 rwh TI rwh RI rwh SCON Reset: 00H Serial Channel Control Register SBUF Reset: 00H Serial Data Buffer Register EO Reset: 00H Extended Operation Register IEN0 Reset: 00H Interrupt Enable Register 0 IP Reset: 00H Interrupt Priority Register IPH Reset: 00H Interrupt Priority Register High PSW Reset: 00H Program Status Word Register A8H B8H B9H D0H EA rw ET2 rw PT2 rw PT2H rw F0 rwh ET1 rw PT1 rw PT1H rw RS0 rw ET0 rw PT0 rw PT0H rw F1 rwh User’s Manual Memory Organization, V 0.2 3-13 V 0.2, 2005-01 XC866 Memory Organization Table 3-1 Addr E0H E8H CPU Register Overview (cont’d) Bit Reset: 00H Bit Field Type Bit Field Type Register Name ACC Accumulator Register 7 6 5 4 3 2 ACC2 rw EX2 rw B2 rw PX2 rw 1 ACC1 rw ESSC rw B1 rw PSSC rw 0 ACC0 rw EADC rw B0 rw PADC rw IEN1 Reset: 00H Interrupt Enable Register 1 B B Register Reset: 00H F0H F8H Bit Field Type Bit Field Type ACC7 ACC6 ACC5 ACC4 ACC3 rw rw rw rw rw ECCIP ECCIP ECCIP ECCIP EXM 3 2 1 0 rw rw rw rw rw B7 B6 B5 B4 B3 rw rw rw rw rw PCCIP PCCIP PCCIP PCCIP 3 2 1 0 rw rw rw rw PXM rw IP1 Reset: 00H Interrupt Priority Register 1 IPH1 Reset: 00H Interrupt Priority Register 1 High F9H Bit Field Type PCCIP PCCIP PCCIP PCCIP PXMH 3H 2H 1H 0H rw rw rw rw rw PX2H PSSCH PADC H rw rw rw 3.3.5.2 Table 3-2 Addr System Control Registers System Control Register Overview Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type OP w 0 STNR w The system control SFRs can be accessed in the standard memory area (RMAP = 0). Register Name 7 6 5 4 0 r 0 r PAGE rw 3 2 1 0 RMAP rw RMAP = 0 or 1 SYSCON0 Reset: 00H 8FH System Control Register 0 RMAP = 0 SCU_PAGE Reset: 00H BFH Page Register for System Control RMAP = 0, Page 0 B3H MODPISEL Reset: 00H Peripheral Input Select Register IRCON0 Reset: 00H Interrupt Request Register 0 IRCON1 Reset: 00H Interrupt Request Register 1 EXICON0 Reset: 00H External Interrupt Control Register 0 EXICON1 Reset: 00H External Interrupt Control Register 1 NMICON NMI Control Register Reset: 00H B4H 0 r JTAG JTAG 0 EXINT URRIS TDIS TCKS 0IS r rw rw r rw rw EXINT EXINT EXINT EXINT EXINT EXINT EXINT 6 5 4 3 2 1 0 rwh rwh rwh rwh rwh rwh rwh 0 r ADCS RC1 rwh EXINT2 rw EXINT6 NMI ECC rw FNMI ECC rwh rw NMI NMI VDDP VDD rw FNMI VDDP rwh rw rw FNMI VDD rwh ADCS RC0 RIR TIR EIR B5H Bit Field Type B7H BAH BBH Bit Field Type Bit Field Type Bit Field EXINT3 rw 0 r 0 rwh rwh EXINT1 rw EXINT5 rw NMI NMI OCDS FLASH TIMER rw rw rwh rwh EXINT0 rw EXINT4 rw NMI PLL rw NMI WDT rw FNMI WDT rwh R rw BCH NMISR NMI Status Register Reset: 00H Type Bit Field r 0 FNMI FNMI FNMI OCDS FLASH PLL TIMER rwh rwh BRPRE rw rwh BDH BEH BCON Reset: 00H Baud Rate Control Register BG Reset: 00H Baud Rate Timer/Reload Register Type Bit Field Type Bit Field Type r rw BGSEL T2EXIS BREN rw BR_VALUE rw User’s Manual Memory Organization, V 0.2 3-14 V 0.2, 2005-01 XC866 Memory Organization Table 3-2 Addr System Control Register Overview (cont’d) Bit Reset: 01H Bit Field Type Bit Field Type 0 r WDT RST rwh 0 r 0 r NDIV rw 0 r PASS OSC PD rw Register Name 7 6 5 PRODID r WKRS rwh 4 3 2 1 VERID r 0 RMAP = 0, Page 1 ID B3H Identity Register B4H PMCON0 Reset: 00H Power Mode Control Register 0 PMCON1 Reset: 00H Power Mode Control Register 1 OSC_CON OSC Control Register PLL_CON PLL Control Register CMCON Clock Control Register PASSWD Password Register Reset: 08H WK SEL rw SD rw T2_DIS rw XPD rw VCO BYP rw PD rwh CCU _DIS rw WS rw SSC _DIS rw ADC _DIS rw B5H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type B6H B7H Reset: 20H OSC ORD OSCR SS RES rw rwh rw OSC RESLD LOCK DISC rw rwh rh CLKREL rw BAH BBH Reset: 00H Reset: 07H BCH BDH FEAL Reset: 00H Flash Error Address Register Low FEAH Reset: 00H Flash Error Address Register High PROTE CT_S rh wh ECCERRADDR[7:0] rh ECCERRADDR[15:8] rh MODE rw User’s Manual Memory Organization, V 0.2 3-15 V 0.2, 2005-01 XC866 Memory Organization 3.3.5.3 Table 3-3 Addr WDT Registers WDT Register Overview Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Register Name 7 0 r 6 5 WINB EN rw 4 3 2 WDT EN rw 1 WDT RS rwh 0 WDT IN rw RMAP = 1 WDTCON Reset: 00H BBH Watchdog Timer Control Register BCH BDH WDTREL Reset: 00H Watchdog Timer Reload Register WDTWINB Reset: 00H Watchdog Window-Boundary Count Register WDTL Reset: 00H Watchdog Timer Register Low WDTH Reset: 00H Watchdog Timer Register High WDT 0 PR r rh WDTREL rw WDTWINB rw WDT[7:0] rh WDT[15:8] rh BEH BFH 3.3.5.4 Table 3-4 Addr Port Registers Port Register Overview Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type P7 rw P7 rw P7 rw P7 rw P7 rw 0 r 0 r P7 rw P6 rw The Port SFRs can be accessed in the standard memory area (RMAP = 0). Register Name 7 OP w 0 r 0 r P6 rw P6 rw P6 rw P6 rw P6 rw 6 5 STNR w P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw 4 3 0 r P3 rw P3 rw 0 r 0 r P3 rw P3 rw P3 rw P3 rw P3 rw 0 r 2 1 PAGE rw 0 RMAP = 0 PORT_PAGE Reset: 00H B2H Page Register for PORT RMAP = 0, Page 0 P0_DATA 80H P0 Data Register 86H 90H 91H A0H B0H B1H P0_DIR P0 Direction Register P1_DATA P1 Data Register P1_DIR P1 Direction Register P2_DATA P2 Data Register P3_DATA P3 Data Register P3_DIR P3 Direction Register Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H P4 rw P4 rw P2 rw P2 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P4 rw P4 rw P4 rw P4 rw P4 rw P2 rw P2 rw P2 rw P2 rw P2 rw RMAP = 0, Page 1 P0_PUDSEL Reset: FFH 80H P0 Pull-Up/Pull-Down Select Register 86H 90H P0_PUDEN Reset: C4H Bit Field P0 Pull-Up/Pull-Down Enable Register Type P1_PUDSEL Reset: FFH Bit Field P1 Pull-Up/Pull-Down Select Register Type User’s Manual Memory Organization, V 0.2 3-16 V 0.2, 2005-01 XC866 Memory Organization Table 3-4 Addr 91H A0H A1H B0H B1H Port Register Overview (cont’d) Bit 7 P7 rw P7 rw P7 rw P7 rw P7 rw 0 r 0 r P7 rw P7 rw P7 rw P7 rw 0 r P7 rw P7 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw Register Name 6 P6 rw P6 rw P6 rw P6 rw P6 rw 5 P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw 4 3 0 r P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw 0 r 0 r P3 rw P3 rw P3 rw 0 r P3 rw 2 1 P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw 0 P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P1_PUDEN Reset: FFH Bit Field P1 Pull-Up/Pull-Down Enable Register Type P2_PUDSEL Reset: FFH Bit Field P2 Pull-Up/Pull-Down Select Register Type P2_PUDEN Reset: 00H Bit Field P2 Pull-Up/Pull-Down Enable Register Type P3_PUDSEL Reset: BFH Bit Field P3 Pull-Up/Pull-Down Select Register Type P3_PUDEN Reset: 40H Bit Field P3 Pull-Up/Pull-Down Enable Register Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw RMAP = 0, Page 2 P0_ALTSEL0 Reset: 00H 80H P0 Alternate Select 0 Register 86H 90H 91H B0H B1H P0_ALTSEL1 Reset: 00H P0 Alternate Select 1 Register P1_ALTSEL0 Reset: 00H P1 Alternate Select 0 Register P1_ALTSEL1 Reset: 00H P1 Alternate Select 1 Register P3_ALTSEL0 Reset: 00H P3 Alternate Select 0 Register P3_ALTSEL1 Reset: 00H P3 Alternate Select 1 Register P4 rw P4 rw P4 rw P2 rw P2 rw P2 rw RMAP = 0, Page 3 P0_OD Reset: 00H 80H P0 Open Drain Control Register 90H B0H P1_OD Reset: 00H P1 Open Drain Control Register P3_OD Reset: 00H P3 Open Drain Control Register P4 rw P2 rw 3.3.5.5 Table 3-5 Addr D1H RMAP = 0 ADC Registers ADC Register Overview Bit Reset: 00H Bit Field Type Reset: 00H Reset: 00H Bit Field Type Bit Field Type The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Register Name ADC_PAGE Page Register for ADC 7 OP w ANON rw 0 6 5 STNR w 4 3 0 r 2 1 PAGE rw 0 r 0 CAH CBH RMAP = 0, Page 0 ADC_GLOBCTR Global Control Register ADC_GLOBSTR Global Status Register DW rw CTC rw CHNR 0 CCH CDH ADC_PRAR Reset: 00H Priority and Arbitration Register ADC_LCBR Reset: B7H Limit Check Boundary Register Bit Field Type Bit Field Type r ASEN1 ASEN0 rw rw 0 r r rh rh ARBM CSM1 PRIO1 CSM0 PRIO0 rw rw rw rw rw BOUND0 rw SAM PLE rh BUSY BOUND1 rw User’s Manual Memory Organization, V 0.2 3-17 V 0.2, 2005-01 XC866 Memory Organization Table 3-5 Addr CEH CFH ADC Register Overview (cont’d) Bit Reset: 00H Bit Field Type Bit Field Type SYNEN SYNEN 1 0 rw rw 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r RESULT[1:0] rh LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw 0 r VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh RESULT[2:0] rh VF DRC CHNR rh Register Name ADC_INPCR0 Input Class Register 0 7 6 5 4 STC rw ETRSEL1 rw 3 2 1 0 ADC_ETRCR Reset: 00H External Trigger Control Register ETRSEL0 rw 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw CHNR rh RMAP = 0, Page 1 CAH CBH CCH CDH CEH CFH D2H D3H ADC_CHCTR0 Reset: 00H Channel Control Register 0 ADC_CHCTR1 Reset: 00H Channel Control Register 1 ADC_CHCTR2 Reset: 00H Channel Control Register 2 ADC_CHCTR3 Reset: 00H Channel Control Register 3 ADC_CHCTR4 Reset: 00H Channel Control Register 4 ADC_CHCTR5 Reset: 00H Channel Control Register 5 ADC_CHCTR6 Reset: 00H Channel Control Register 6 ADC_CHCTR7 Reset: 00H Channel Control Register 7 Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type RMAP = 0, Page 2 ADC_RESR0L CAH Result Register 0 Low CBH CCH CDH CEH CFH D2H D3H ADC_RESR0H Result Register 0 High ADC_RESR1L Result Register 1 Low ADC_RESR1H Result Register 1 High ADC_RESR2L Result Register 2 Low ADC_RESR2H Result Register 2 High ADC_RESR3L Result Register 3 Low ADC_RESR3H Result Register 3 High RESULT[1:0] rh 0 r CHNR rh RESULT[1:0] rh 0 r CHNR rh RESULT[1:0] rh 0 r CHNR rh RMAP = 0, Page 3 ADC_RESRA0L Reset: 00H CAH Result Register 0, View A Low CBH CCH CDH CEH ADC_RESRA0H Reset: 00H Result Register 0, View A High ADC_RESRA1L Reset: 00H Result Register 1, View A Low ADC_RESRA1H Reset: 00H Result Register 1, View A High ADC_RESRA2L Reset: 00H Result Register 2, View A Low RESULT[2:0] rh rh rh RESULT[10:3] rh VF DRC rh RESULT[10:3] rh VF rh DRC rh rh CHNR rh RESULT[2:0] rh CHNR rh User’s Manual Memory Organization, V 0.2 3-18 V 0.2, 2005-01 XC866 Memory Organization Table 3-5 Addr C FH D2H D3H ADC Register Overview (cont’d) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type VFCTR WFR rw rw FEN rw FEN rw FEN rw FEN rw 0 r RESULT[2:0] rh Register Name ADC_RESRA2H Reset: 00H Result Register 2, View A High ADC_RESRA3L Reset: 00H Result Register 3, View A Low ADC_RESRA3H Reset: 00H Result Register 3, View A High 7 6 5 4 3 2 1 0 RESULT[10:3] rh VF DRC rh rh RESULT[10:3] rh IEN rw IEN rw IEN rw IEN rw VFC3 w 0 r 0 r 0 r 0 r VFC2 w CHNR rh RMAP = 0, Page 4 ADC_RCR0 Reset: 00H CAH Result Control Register 0 CBH ADC_RCR1 Reset: 00H Result Control Register 1 ADC_RCR2 Reset: 00H Result Control Register 2 ADC_RCR3 Reset: 00H Result Control Register 3 ADC_VFCR Reset: 00H Valid Flag Clear Register DRCT R rw DRCT R rw DRCT R rw DRCT R VFC1 w rw VFC0 w CHINF 0 rh CHINC 0 w CHINS 0 w CHINP 0 rw Bit Field Type Bit Field Type VFCTR WFR rw rw VFCTR WFR rw rw VFCTR WFR rw rw CCH CDH Bit Field Type CEH Bit Field Type Bit Field Type Bit Field Type RMAP = 0, Page 5 ADC_CHINFR Reset: 00H CAH Channel Interrupt Flag Register CBH ADC_CHINCR Reset: 00H Channel Interrupt Clear Register ADC_CHINSR Reset: 00H Channel Interrupt Set Register ADC_CHINPR Reset: 00H Channel Interrupt Node Pointer Register ADC_EVINFR Reset: 00H Event Interrupt Flag Register ADC_EVINCR Reset: 00H Event Interrupt Clear Flag Register ADC_EVINSR Reset: 00H Event Interrupt Set Flag Register ADC_EVINPR Reset: 00H Event Interrupt Node Pointer Register CCH Bit Field Type CDH Bit Field Type Bit Field Type CHINF CHINF CHINF CHINF CHINF CHINF CHINF 7 6 5 4 3 2 1 rh rh rh rh rh rh rh CHINC CHINC CHINC CHINC CHINC CHINC CHINC 7 6 5 4 3 2 1 w w w w w w w CHINS CHINS CHINS CHINS CHINS CHINS CHINS 7 6 5 4 3 2 1 w w w w w w w CHINP CHINP CHINP CHINP CHINP CHINP CHINP 7 6 5 4 3 2 1 rw rw rw rw rw rw rw EVINF EVINF EVINF EVINF 7 6 5 4 rh rh rh rh EVINC EVINC EVINC EVINC 7 6 5 4 w w w w EVINS EVINS EVINS EVINS 7 6 5 4 w w w w EVINP EVINP EVINP EVINP 7 6 5 4 rw rw rw rw CH7 rwh CHP7 rwh CH6 rwh CHP6 rwh CH5 rwh CHP5 rwh CH4 rwh CHP4 rwh 0 r 0 r 0 r 0 r 0 r 0 r CEH EVINF EVINF 1 0 rh rh EVINC EVINC 1 0 w w EVINS EVINS 1 0 w w EVINP EVINP 1 0 rw rw CFH Bit Field Type Bit Field Type D2H D3H Bit Field Type RMAP = 0, Page 6 ADC_CRCR1 Reset: 00H Bit Field CAH Conversion Request Control Register 1 CBH ADC_CRPR1 Reset: 00H Conversion Request Pending Register 1 Type Bit Field Type User’s Manual Memory Organization, V 0.2 3-19 V 0.2, 2005-01 XC866 Memory Organization Table 3-5 Addr CCH ADC Register Overview (cont’d) Bit Bit Field Type Register Name ADC_CRMR1 Reset: 00H Conversion Request Mode Register 1 ADC_QMR0 Reset: 00H Queue Mode Register 0 ADC_QSR0 Reset: 20H Queue Status Register 0 ADC_Q0R0 Queue 0 Register 0 Reset: 00H 7 0 6 LDEV 5 4 3 2 1 0 CDH CEH CFH D2H D2H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type CLR SCAN ENSI ENTR ENGT PND rw rw rw r w w rw CEV TREV FLUSH CLRV TRMD ENTR ENGT w w w w rw rw rw 0 EMPTY EV 0 r rh rh r EXTR ENSI RF V 0 REQCHNR rh rh rh rh r rh EXTR rh EXTR w ENSI rh ENSI w RF rh RF w V rh 0 r 0 r REQCHNR rh REQCHNR w ADC_QBUR0 Reset: 00H Queue Backup Register 0 ADC_QINR0 Queue Input Register 0 Reset: 00H 3.3.5.6 Table 3-6 Addr C0H Timer 2 Registers Timer 2 Register Overview Bit Bit Field Type Bit Field Type The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Register Name T2_T2CON Reset: 00H Timer 2 Control Register T2_T2MOD Timer 2 Mode Register Reset: 00H 7 TF2 rwh 0 r 6 EXF2 rwh 5 0 4 3 EXEN2 2 TR2 rwh T2PRE rw 1 C/T2 rw 0 CP/ RL2 rw DCEN rw C1H C2H C3H C4H C5H T2_RC2L Reset: 00H Timer 2 Reload/Capture Register Low Bit Field Type T2_RC2H Reset: 00H Bit Field Timer 2 Reload/Capture Register High Type T2_T2L Reset: 00H Bit Field Timer 2 Register Low Type T2_T2H Reset: 00H Bit Field Timer 2 Register High Type r rw EDGE PREN SEL rw rw RC2[7:0] rwh RC2[15:8] rwh THL2[7:0] rwh THL2[15:8] rwh 3.3.5.7 Table 3-7 Addr A3H RMAP = 0 CCU6 Registers CCU6 Register Overview Bit Bit Field Type The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Register Name CCU6_PAGE Reset: 00H Page Register for CCU6 7 OP w 6 5 STNR w 4 3 0 r 2 1 PAGE rw 0 9AH RMAP = 0, Page 0 CCU6_CC63SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC63 Low Type CC63SL rw User’s Manual Memory Organization, V 0.2 3-20 V 0.2, 2005-01 XC866 Memory Organization Table 3-7 Addr 9BH CCU6 Register Overview (cont’d) Bit 7 6 5 4 3 rw DTRES w 0 r Register Name 2 1 0 9CH CCU6_CC63SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC63 High Type CCU6_TCTR4L Reset: 00H Bit Field Timer Control Register 4 Low Type CCU6_TCTR4H Reset: 00H Timer Control Register 4 High CCU6_MCMOUTSL Reset: 00H Multi-Channel Mode Output Shadow Register Low CCU6_MCMOUTSH Reset: 00H Multi-Channel Mode Output Shadow Register High CCU6_ISRL Reset: 00H Capture/Compare Interrupt Status Reset Register Low CCU6_ISRH Reset: 00H Capture/Compare Interrupt Status Reset Register High CCU6_CMPMODIFL Reset: 00H Compare State Modification Register Low CCU6_CMPMODIFH Reset: 00H Compare State Modification Register High Bit Field Type CC63SH T12 STD w T13 STD w STRM CM w STRHP w T12 STR w T13 STR w 0 r 0 r 0 r T12 RES w T12RS T12RR w w 9DH 9EH Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type T13 RES w MCMPS rw T13RS T13RR w w 9FH CURHS rw EXPHS rw A4H A5H RT12P RT12O RCC62 RCC62 RCC61 RCC61 RCC60 RCC60 M M F R F R F R w w w w w w w w RSTR RIDLE RWHE RCHE 0 RTRPF RT13 RT13 PM CM w w w w r w w w 0 r 0 r MCC63 S w MCC63 R w 0 r 0 r CC60SL rwh CC60SH rwh CC61SL rwh CC61SH rwh CC62SL rwh CC62SH rwh CC63VL rh CC63VH rh T12PVL rwh MCC62 MCC61 MCC60 S S S w w w MCC62 MCC61 MCC60 R R R w w w A6H A7H FAH FBH CCU6_CC60SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC60 Low Type CCU6_CC60SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC60 High Type CCU6_CC61SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC61 Low Type CCU6_CC61SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC61 High Type CCU6_CC62SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC62 Low Type CCU6_CC62SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC62 High Type CCU6_CC63RL Reset: 00H Bit Field Capture/Compare Register for Channel CC63 Low Type CCU6_CC63RH Reset: 00H Bit Field Capture/Compare Register for Channel CC63 High Type CCU6_T12PRL Reset: 00H Timer T12 Period Register Low Bit Field Type FCH FDH FEH FFH RMAP = 0, Page 1 9AH 9BH 9CH User’s Manual Memory Organization, V 0.2 3-21 V 0.2, 2005-01 XC866 Memory Organization Table 3-7 Addr 9DH 9EH 9FH A4H CCU6 Register Overview (cont’d) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r CTM rw 0 r DTR2 rh CDIR rh DTR1 rh STE12 rh STE13 rh Register Name CCU6_T12PRH Reset: 00H Timer T12 Period Register High CCU6_T13PRL Reset: 00H Timer T13 Period Register Low CCU6_T13PRH Reset: 00H Timer T13 Period Register High CCU6_T12DTCL Reset: 00H Dead-Time Control Register for Timer T12 Low CCU6_T12DTCH Reset: 00H Dead-Time Control Register for Timer T12 High CCU6_TCTR0L Reset: 00H Timer Control Register 0 Low CCU6_TCTR0H Reset: 00H Timer Control Register 0 High 7 6 5 4 3 2 1 0 T12PVH rwh T13PVL rwh T13PVH rwh DTM rw DTR0 rh T12R rh T13R rh 0 r T12 PRE rw T13 PRE rw DTE2 rw DTE1 rw T12CLK rw T13CLK rw DTE0 rw A5H A6H A7H Bit Field Type FAH FBH CCU6_CC60RL Reset: 00H Bit Field Capture/Compare Register for Channel CC60 Low Type CCU6_CC60RH Reset: 00H Bit Field Capture/Compare Register for Channel CC60 High Type CCU6_CC61RL Reset: 00H Bit Field Capture/Compare Register for Channel CC61 Low Type CCU6_CC61RH Reset: 00H Bit Field Capture/Compare Register for Channel CC61 High Type CCU6_CC62RL Reset: 00H Bit Field Capture/Compare Register for Channel CC62 Low Type CCU6_CC62RH Reset: 00H Bit Field Capture/Compare Register for Channel CC62 High Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type DBYP MSEL61 rw HSYNC CC60VL rh CC60VH rh CC61VL rh CC61VH rh CC62VL rh CC62VH rh MSEL60 rw MSEL62 FCH FDH FEH FFH RMAP = 0, Page 2 CCU6_T12MSELL Reset: 00H 9AH T12 Capture/Compare Mode Select Register Low 9BH CCU6_T12MSELH Reset: 00H T12 Capture/Compare Mode Select Register High CCU6_IENL Reset: 00H Capture/Compare Interrupt Enable Register Low CCU6_IENH Reset: 00H Capture/Compare Interrupt Enable Register High CCU6_INPL Reset: 40H Capture/Compare Interrupt Node Pointer Register Low 9CH 9DH 9EH rw rw rw ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC PM OM 62F 62R 61F 61R 60F 60R rw rw rw rw rw rw rw rw ENSTR EN EN EN 0 EN ENT13 ENT13 IDLE WHE CHE TRPF PM CM r rw rw rw rw rw rw rw INPCHE INPCC62 INPCC61 INPCC60 rw rw rw rw User’s Manual Memory Organization, V 0.2 3-22 V 0.2, 2005-01 XC866 Memory Organization Table 3-7 Addr 9FH CCU6 Register Overview (cont’d) Bit Bit Field Register Name CCU6_INPH Reset: 39H Capture/Compare Interrupt Node Pointer Register High 7 0 6 5 4 3 2 1 0 INPT13 INPT12 INPERR A4H Type CCU6_ISSL Reset: 00H Bit Field Capture/Compare Interrupt Status Set Register Low Type CCU6_ISSH Reset: 00H Bit Field Capture/Compare Interrupt Status Set Register High Type CCU6_PSLR Reset: 00H Bit Field Passive State Level Register Type CCU6_MCMCTR Reset: 00H Multi-Channel Mode Control Register CCU6_TCTR2L Reset: 00H Timer Control Register 2 Low CCU6_TCTR2H Reset: 00H Timer Control Register 2 High CCU6_MODCTRL Reset: 00H Modulation Control Register Low CCU6_MODCTRH Reset: 00H Modulation Control Register High CCU6_TRPCTRL Reset: 00H Trap Control Register Low CCU6_TRPCTRH Reset: 00H Trap Control Register High Bit Field Type Bit Field Type rw rw r rw ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60 M M F R F R F R w w w w w w w w SSTR SIDLE SWHE SCHE SWHC STRPF ST13 ST13 PM CM w w w w w w w w PSL63 0 PSL rwh r rwh 0 SWSYN 0 SWSEL r rw r rw 0 T13TED T13TEC T13 T12 SSC SSC rw rw r rw rw 0 T13RSEL T12RSEL r rw rw MC MEN rw ECT13 O rw 0 r 0 r 0 r TRPPE TRPEN N 13 rw rw 0 r 0 R rh CURH T12MODEN rw T13MODEN rw TRPM2 TRPM1 TRPM0 rw rw rw TRPEN rw MCMP rh EXPH A5H A6H A7H FAH FBH FCH Bit Field Type Bit Field Type Bit Field Type FDH FEH FFH Bit Field Type Bit Field Type RMAP = 0, Page 3 9AH CCU6_MCMOUTL Reset: 00H Multi-Channel Mode Output Register Low CCU6_MCMOUTH Reset: 00H Multi-Channel Mode Output Register High CCU6_ISL Reset: 00H Capture/Compare Interrupt Status Register Low CCU6_ISH Reset: 00H Capture/Compare Interrupt Status Register High CCU6_PISEL0L Reset: 00H Port Input Select Register 0 Low CCU6_PISEL0H Reset: 00H Port Input Select Register 0 High CCU6_PISEL2 Reset: 00H Port Input Select Register 2 CCU6_T12L Reset: 00H Timer T12 Counter Register Low Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type A4H FAH Bit Field Type Bit Field Type 9BH 9CH rh r rh T12PM T12OM ICC62F ICC62 ICC61F ICC61 ICC60F ICC60 R R R rh STR rh IDLE rh WHE rh CHE rh TRPS rh rh rh TRPF T13PM T13CM rh rh ISCC60 rw ISPOS0 rw IST13HR rw T12CVL rwh 9DH 9EH 9FH rh rh ISTRP rw IST12HR rw rh rh ISCC62 rw ISPOS2 rw 0 r rh rh ISCC61 rw ISPOS1 rw User’s Manual Memory Organization, V 0.2 3-23 V 0.2, 2005-01 XC866 Memory Organization Table 3-7 Addr FBH FCH FDH FEH CCU6 Register Overview (cont’d) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 Register Name CCU6_T12H Reset: 00H Timer T12 Counter Register High CCU6_T13L Reset: 00H Timer T13 Counter Register Low CCU6_T13H Reset: 00H Timer T13 Counter Register High CCU6_CMPSTATL Reset: 00H Compare State Register Low CCU6_CMPSTATH Reset: 00H Compare State Register High 7 6 5 4 3 2 1 0 T12CVH rwh T13CVL rwh T13CVH rwh CC63 CCPO CCPO CCPO ST S2 S1 S0 rh r rh rh rh T13IM COUT COUT CC62 COUT 63PS 62PS PS 61PS rwh rwh rwh rwh rwh CC62 ST rh CC61 PS rwh CC61 ST rh COUT 60PS rwh CC60 ST rh CC60 PS rwh FFH Bit Field Type 3.3.5.8 Table 3-8 Addr SSC Registers SSC Register Overview Bit Bit Field Type Bit Field Type Bit Field Reset: 00H Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type EN rw EN rw MS rw MS rw LB rw PO rw 0 r 0 r 0 r AREN BEN PEN rw PE rwh The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Register Name 7 6 5 0 r PH rw HB rw 4 3 2 CIS rw BM rw BC rh 1 SIS rw 0 MIS rw RMAP = 0 SSC_PISEL Reset: 00H A9H Port Input Select Register AAH SSC_CONL Control Register Low Programming Mode Operating Mode ABH SSC_CONH Control Register High Programming Mode Operating Mode ACH ADH AEH AFH SSC_TBL Reset: 00H Transmitter Buffer Register Low SSC_RBL Reset: 00H Receiver Buffer Register Low SSC_BRL Reset: 00H Baudrate Timer Reload Register Low SSC_BRH Reset: 00H Baudrate Timer Reload Register High Reset: 00H REN rw RE rwh TEN rw TE rwh rw rw BSY BE rh rwh TB_VALUE rw RB_VALUE rh BR_VALUE[7:0] rw BR_VALUE[15:8] rw User’s Manual Memory Organization, V 0.2 3-24 V 0.2, 2005-01 XC866 Memory Organization 3.3.5.9 Table 3-9 Addr OCDS Registers OCDS Register Overview Bit Bit Field Type Bit Field Type The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). Register Name 7 6 5 4 3 2 1 0 RMAP = 1 MMCR2 Reset: 0UH E9H Monitor Mode Control Register 2 F1H MMCR Reset: 00H Monitor Mode Control Register MMSR Reset: 00H Monitor Mode Status Register MMBPCR Reset: 00H BreakPoints Control Register F2H Bit Field Type F3H Bit Field F4H Type MMICR Reset: 00H Bit Field Monitor Mode Interrupt Control Register Type MMDR Reset: 00H Monitor Mode Data Register Receive Transmit Bit Field Type Bit Field F5H EXBC_ EXBC MBCO MBCO MMEP MMEP MMOD JENA P N_P N _P E w rwh rh rh w rw w rwh MEXIT MEXIT MSTEP MSTEP MRAM MRAM TRF RRF _P _P S_P S w rwh rh rh w hw w rw MBCA MBCIN EXBF SWBF HWB3 HWB2 HWB1 HWB0 M F F F F rw rh rwh rwh rwh rwh rwh rwh SWBC HWB3C HWB2C HWB1 HWB0C C rw rw rw rw rw DVECT DRETR 0 MMUIE MMUIE RRIE_ RRIE _P P w rw w rw rwh rwh r MMRR rh MMTR w BPSEL _P w HWBPxx rw F6H Type HWBPSR Reset: 00H Bit Field Hardware Breakpoints Select Register HWBPDR Reset: 00H Hardware Breakpoints Data Register Type Bit Field Type 0 r BPSEL rw F7H User’s Manual Memory Organization, V 0.2 3-25 V 0.2, 2005-01 XC866 Memory Organization 3.4 Boot ROM Operating Mode After a reset, the CPU will always start by executing the Boot ROM code which occupies the program memory address space 0000H – 1FFFH. The Boot ROM start-up procedure will first switch the address space for the Boot ROM to C000H – DFFFH, as shown in Figure 3-6. As a result, the program memory (Flash or ROM) previously occupying the address range C000H – DFFFH will be mapped to 0000H – 1FFFH instead. After the address space switch, the remaining Boot ROM start-up procedure will be executed from C00XH. This includes checking the latched values of pins MBC, TMS and P0.0 to enter the selected Boot ROM operating modes. Refer to Chapter 7.2.3 for the selection of different Boot ROM operating modes. The memory organization of the XC866 shown in this document is after the address space switch where the different operating modes are executed. FFFFH E000H FFFFH Memory Space C000H Address 2 space E000H switch C000H Boot ROM 2000H 2000H CPU starts 1 execution Boot ROM 0000H 0000H Memory Space After address space switch Immediately after reset Figure 3-6 Boot ROM Address Space Switch 3.4.1 User Mode If (MBC, TMS, P0.0) = (1, x, x), the Boot ROM will jump to program memory address 0000H to execute the user code in the Flash or ROM memory. This is the normal operating mode of the XC866. User’s Manual Memory Organization, V 0.2 3-26 V 0.2, 2005-01 XC866 Memory Organization 3.4.2 BootStrap Loader Mode If (MBC, TMS, P0.0) = (0, 0, x), the software routines of the BootStrap Loader (BSL) located in the Boot ROM will be executed, allowing the XRAM and Flash memory (if available) to be programmed, erased and executed. Refer to Chapter 4.6 for the different BSL working modes. 3.4.3 OCDS Mode If (MBC, TMS, P0.0) = (0, 1, 1), the OCDS mode will be entered for debugging program code. The OCDS hardware is initialized and a jump to program memory address 0000H is next performed. The user code in the Flash or ROM memory is executed and the debugging process may be started. During the OCDS mode, the lowest 64 bytes (00H – 3FH) in the internal data memory address range may be alternatively mapped to the 64-byte monitor RAM or the internal data RAM. User’s Manual Memory Organization, V 0.2 3-27 V 0.2, 2005-01 XC866 Flash Memory 4 Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The sectorization of the Flash memory allows each sector to be erased independently. Features: • • • • • • • In-System Programming (ISP) via UART In-Application Programming (IAP) Error Correction Code (ECC) for dynamic correction of single-bit errors 32-byte minimum program width 1-sector minimum erase width 1-byte read access 3 × CCLK period read access time (inclusive of one wait state) User’s Manual Flash Memory, V 0.3 4-1 V 0.2, 2005-01 XC866 Flash Memory 4.1 Flash Memory Map The XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of embedded Flash memory. These Flash memory sizes are made up of two or four 4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash (P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization. The program memory map for the two different Flash sizes is shown in Figure 4-1. B000 H D-Flash Bank 4 Kbytes A000 H D-Flash Bank 4 Kbytes 3000 H P-Flash Bank 2 4 Kbytes 2000 H P-Flash Bank 1 4 Kbytes 1000 H P-Flash Bank 0 4 Kbytes 0000 H P-Flash Bank 0 4 Kbytes 16 Kb y tes 8 Kb y tes Figure 4-1 Flash Memory Map For the 8-Kbyte Flash devices, P-Flash bank 0 is available and occupies the lower part of the program memory address, starting from 0000H where the reset and interrupt vectors are located. For the 16-Kbyte Flash devices, two additional P-Flash banks (1 and 2) are provided for storing user code: • P-Flash bank 1 occupies the address range 1000H – 1FFFH • P-Flash bank 2 occupies 2000H – 2FFFH All devices in the XC866 product family (including ROM devices) offer a 4-Kbyte D-Flash bank, occupying the address region A000H – AFFFH. User’s Manual Flash Memory, V 0.3 4-2 V 0.2, 2005-01 XC866 Flash Memory 4.2 Flash Bank Sectorization The XC866 Flash devices consist of two types of 4-Kbyte banks, namely Program Flash (P-Flash) bank and Data Flash (D-Flash) bank, with different sectorization as shown in Figure 4-2. Both types can be used for code and data storage. The label “Data” neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage. It is used to distinguish the different Flash bank sectorizations. 128-byte Sector 2 128-byte Sector 1 128-byte Sector 9 128-byte Sector 8 128-byte Sector 7 128-byte Sector 6 256-byte Sector 5 256-byte Sector 4 512-byte Sector 3 3.75-Kbyte Sector 0 512-byte Sector 2 1-Kbyte Sector 1 1-Kbyte Sector 0 P-Flash D-Flash Figure 4-2 Flash Bank Sectorization Sector Partitioning in P-Flash: • One 3.75-Kbyte sector • Two 128-byte sectors Sector Partitioning in D-Flash: • • • • Two 1-Kbyte sectors Two 512-byte sectors Two 256-byte sectors Four 128-byte sectors The internal structure of each Flash bank represents a sector architecture for flexible erase capability. The minimum erase width is always a complete sector, and sectors can be erased separately or in parallel. Contrary to standard EPROMs, erased Flash memory cells contain 0s. User’s Manual Flash Memory, V 0.3 4-3 V 0.2, 2005-01 XC866 Flash Memory The D-Flash bank is divided into more physical sectors for extended erasing and reprogramming capability; even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements. For example, the user’s program can implement a buffer mechanism for each sector. Double copies of each data set can be stored in separate sectors of similar size to ensure that a backup copy of the data set is available in the event that the actual data set is corrupted or erased. Alternatively, the user can implement an algorithm for EEPROM emulation, which uses the D-Flash bank like a circular stack memory; the latest data updates are always programmed on top of the actual region. When the top of the sector is reached, all actual data (representing the EEPROM data) is copied to the bottom area of the next sector and the last sector is then erased. This round robin procedure, using multifold replications of the emulated EEPROM size, significantly increases the endurance. To speed up data search, the RAM can be used to contain the pointer to the valid data set. User’s Manual Flash Memory, V 0.3 4-4 V 0.2, 2005-01 XC866 Flash Memory 4.3 Wordline Address The wordline (WL) addresses of the P-Flash and D-Flash banks are given in Figure 4-3. Byte 31 2FFFH …… 2F9FH 2F7FH …… 2F1FH 2EFFH ………. 207FH 205FH 203FH 201FH 1FFFH …… 1F9FH 1F7FH …… 1F1FH 1EFFH ………. 107FH 105FH 103FH 101FH 0FFFH …… 0F9FH 0F7FH …… 0F1FH 0EFFH ………. 007FH 005FH 003FH 001FH …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. …………………………….. Byte 2 Byte 1 Byte 0 Sector 2 W L 124 - 127 12 8-byte Byte 31 AFFFH …… …………………………….. Byte 2 Byte 1 Byte 0 Sector 9 W L 124 - 127 12 8-byte S ector 0 W L 0 - 31 1-K Byte S ector 1 W L 32 - 63 1- KByte Sector 2 W L 64 - 7 9 512-b yte Secto r 3 W L 80 - 9 5 512- byte Secto r 4 WL 96 - 103 256 -byte Secto r 5 W L 104 - 111 256 -byte Sector 6 W L 112 - 115 128 -byte Sector 7 W L 116 - 119 12 8-byte Sector 8 W L 120 - 123 12 8-byte 2FE2H 2FE1H 2FE0H …… …… …… 2F82H 2F62H …… AFE2H AFE1H AFE0H …… …… …… 2F81H 2F61H …… 2F80H 2F60H …… AF9FH AF7FH …… …………………………….. …………………………….. AF82H AF81H AF80H AF62H AF61H AF60H …… …… …… P-Flash 2 2F02H ………. 2062H 2042H 2022H 2002H 1F82H 1F62H …… …… 2F01H ………. 2061H 2041H 2021H 2001H 1F81H 1F61H …… …… 2F00H ………. 2060H 2040H 2020H 2000H 1F80H 1F60H …… …… Sector 1 W L 120 - 123 12 8-byte AF1FH AEFFH …… …………………………….. AF02H AF01H AF00H …… …… …… 2EE2H 2EE1H 2EE0H …………………………….. AEE2 H AEE1H AEE0H Sector 0 W L 0 - 119 3.75-K Byte AE9FH AE7FH …… AE1FH ADFFH …………………………….. …………………………….. AE82H AE81H AE80 H AE62H AE61H AE60 H …… …… …… …………………………….. AE02H AE01H AE00 H …………………………….. ADE2H ADE1H ADE0H …….. …….. …….. Secto r 2 W L 124 - 127 128 -byte 1FE2H 1FE1H 1FE0H AD1FH ACFFH …….. …….. …………………………….. AD02H AD01H AD00H Secto r 1 W L 120 - 123 128 -byte …………………………….. ACE2H ACE1H ACE0H …….. …….. …….. P-Flash 1 1F02H ………. 1062H 1042H 1022H 1002H 0F82H 0F62H …… …… 1F01H ………. 1061H 1041H 1021H 1001H 0F81H 0F61H …… …… 1F00H ………. 1060H 1040H 1020H 1000H 0F80H 0F60H …… …… 1EE2H 1EE1H 1EE0H D-Flash AC1FH ABFFH …... …………………………….. AC02H AC01H AC00H …... …... …... …………………………….. ABE2 H ABE1H ABE0H Sector 0 W L 0 - 11 9 3.75-KB yte AA3FH AA1FH A9FFH …... …………………………….. …………………………….. …………………………….. AA22H AA21H AA20 H AA02H AA01H AA00 H A9E2H A9E1H A9E0 H …... …... …... S ector 2 W L 1 24 - 1 27 128-b yte 0FE2H 0FE1H 0FE0H A83FH A81FH A7FFH …... …………………………….. …………………………….. …………………………….. A822H A802H A821H A820H A801H A800H A7E2H A7E1H A7E0 H …... …... …... P-Flash 0 S ector 1 W L 1 20 - 12 3 128-b yte 0F02H ………. 0062H 0042H 0022H 0002H 0F01H ………. 0061H 0041H 0021H 0001H 0F00H ………. 0060H 0040H 0020H 0000H WL Address A45FH A43FH A41FH A3FFH …………………………….. …………………………….. …………………………….. …………………………….. A442H A422H A402H A441H A440H A421H A420H A401H A400H 0EE2H 0EE1H 0EE0H A3E2H A3E1H A3E0 H …... …... …... S ector 0 W L 0 - 119 3.7 5-KByte A05FH A03FH A01FH …... …………………………….. …………………………….. …………………………….. A042H A022H A002H A041H A040H A021H A020H A001H A000H WL Address Figure 4-3 Flash Wordline Addresses 4-5 V 0.2, 2005-01 User’s Manual Flash Memory, V 0.3 XC866 Flash Memory A WL address can be calculated as follow: 0000H + 20H × n, with 0 < n < 127 for P-Flash 0 1000H + 20H × n, with 0 < n < 127 for P-Flash 1 2000H + 20H × n, with 0 < n < 127 for P-Flash 2 A000H + 20H × n, with 0 < n < 127 for D-Flash [4.1] [4.2] [4.3] [4.4] Only one out of all the wordlines in the Flash banks can be programmed at a time. The width of each WL is 32 bytes (minimum/maximum program width). Before programming can be done, the user must first write 32 bytes of data into the IRAM using MOV instructions. Then, the BootStrap Loader (BSL) routine (see Section 4.6) or D-Flash program subroutine (see Section 4.7.1) will transfer these IRAM data to the corresponding write buffer of the targeted Flash bank. After 32 bytes of data are assembled in the write buffers, the programming sequence will start the charge pumps, storing the data content into the Flash cells along the selected WL. The WL is selected via the WL addresses shown in Figure 4-3. It is necessary to fill the IRAM with 32 bytes of data, otherwise the previous values stored in the write buffers will remain and be programmed into the WL. For the P-Flash banks, a programmed WL must be erased before it can be reprogrammed again as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL. For the D-Flash bank, the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to program the same WL, for example, with 16 bytes of data in two times (see Figure 4-4). 32 bytes (1 WL) 0000 ….. 0000 H 0000 ….. 0000 H Program 1 16 bytes 0000 ….. 0000 H 16 bytes 1111 ….. 1111 H 0000 ….. 0000 H 1111 ….. 1111 H Program 2 1111 ….. 0000 H 0000 ….. 0000 H 1111 ….. 0000 H 1111 ….. 1111 H Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0. Flash memory cells 32-byte write buffers Figure 4-4 D-Flash Program 4-6 V 0.2, 2005-01 User’s Manual Flash Memory, V 0.3 XC866 Flash Memory 4.4 Operating Modes The Flash operating modes for each bank are shown in Figure 4-5. Sector(s) Erase Call of DFLASH_ERASE routine or by BSL Ready-to-Read Call of DFLASH_PROG routine or by BSL Program Power-Down System Power-Down Figure 4-5 Flash Operating Modes In general, the Flash operating modes are controlled by the BSL and D-Flash program/ erase subroutines (see Section 4.7). Each Flash bank must be in ready-to-read mode before the program mode or sector(s) erase mode can be entered. In the ready-to-read mode, the 32-byte write buffers for each Flash bank can be written, and the memory cell contents can be read via CPU access. In the program mode, data in the 32-byte write buffers is programmed into the Flash memory cells of the targeted wordline. The operating modes for each Flash bank are enforced by its state machine to ensure the correct sequence of Flash mode transition. This avoids inadvertent destruction of the Flash contents with a reasonably low software overhead. The state machine also ensures that a Flash bank is blocked (no read access possible) while it is being programmed or erased. However, it is possible to program/erase one Flash bank while reading from another. When the user sets bit PMCON0.PD = 1 to enter the system power-down mode, the Flash banks will automatically be brought to its power-down state by hardware. Upon wake-up from system power-down, the Flash banks are brought to ready-to-read mode to allow access by the CPU. User’s Manual Flash Memory, V 0.3 4-7 V 0.2, 2005-01 XC866 Flash Memory 4.5 Error Detection and Correction The 8-bit data from the CPU is encoded with an Error Correction Code (ECC) before being stored in the Flash memory. During a read access, data is retrieved from the Flash memory and decoded for dynamic error detection and correction. The correction algorithm (hamming code) has the capability to: • Detect and correct all 1-bit errors • Detect all 2-bit errors, but cannot correct A corrected 1-bit error (result is valid) and an uncorrected 2-bit error (result is invalid) are not distinguished, with an ECC non-maskable interrupt (NMI) generated for both cases. The 16-bit Flash address at which the ECC error occurs is stored in the system control SFRs FEAL and FEAH, and can be accessed by the interrupt service routine to determine the Flash bank/sector in which the error occurred. FEAL Flash Error Address Register Low 7 6 5 4 3 2 Reset Value: 00H 1 0 ECCERRADDR[7:0] rh FEAH Flash Error Address Register High 7 6 5 4 3 2 Reset Value: 00H 1 0 ECCERRADDR[15:8] rh Field ECCERRADDR Bits Type Description ECC Error Address Value [7:0] of rh FEAL, [7:0] of FEAH User’s Manual Flash Memory, V 0.3 4-8 V 0.2, 2005-01 XC866 Flash Memory 4.6 In-System Programming In-System Programming (ISP) of the Flash memory is supported via the Boot ROMbased BootStrap Loader (BSL), allowing a blank microcontroller device mounted onto an application board to be programmed with the user-code, and also a previously programmed device to be erased then reprogrammed without removal from the board. This feature offers ease-of-use and versatility for the embedded design. ISP is supported through the microcontroller’s serial interface (UART) which is connected to the personal computer host via the commonly available RS-232 serial cable. The BSL mode is selected if the latched values of the MBC and TMS pins are 0 after power-on or hardware reset. The BSL routine will first perform an automatic synchronization with the transfer speed (baud rate) of the serial communication partner (personal computer host). Communication between the BSL routine and the host is done via a simple transfer protocol; information is sent from the host to the microcontroller in blocks with specified block structure, and the BSL routine acknowledges the received data by returning a single acknowledge or error byte. User can program, erase or execute the P-Flash and/or D-Flash bank(s). The available working modes are: • • • • Transfer user program from host to XRAM and/or Flash Execute user program in XRAM Execute user program in Flash Erase Flash sector(s) from the same or different bank(s) User’s Manual Flash Memory, V 0.3 4-9 V 0.2, 2005-01 XC866 Flash Memory 4.7 In-Application Programming In most applications, data in the D-Flash needs to be modified during program execution. In-Application Programming (IAP) is supported so that users can program or erase the D-Flash data from their Flash user program by calling some special subroutines that utilize the Flash Timer NMI. Hence, it is necessary to incorporate a Flash Timer NMI service routine code as part of the Flash user program. The Flash Timer NMI service routine is required as part of the D-Flash program and erase sequences. Boot ROM special D-Flash program/erase subroutines user program user NMI routine Flash Timer NMI service routine Flash Timer NMI 0073H RETI instruction Figure 4-6 D-Flash Program/Erase Flow User’s Manual Flash Memory, V 0.3 4-10 V 0.2, 2005-01 XC866 Flash Memory 4.7.1 D-Flash Programming The Flash program subroutine can be called by the user to program 32 bytes of data into a single D-Flash wordline (WL). At the beginning of this subroutine, the Flash Timer NMI is enabled to enter the Flash Timer NMI service routine at each of the several timer underflows throughout the programming sequence. Before calling this subroutine, the user must ensure that the 32-byte WL contents are stored incrementally in the IRAM, starting from the address specified in R0 of Register Bank 3. In addition, the input DPTR0 (EO.DPSEL0 = 0) must contain the D-Flash WL address. Otherwise, bit PSW.CY will be set and no programming will occur. If valid inputs are available before calling the subroutine, the microcontroller will continue to initialize the programming sequence (includes transferring the 32-byte IRAM data to the D-Flash write buffers), exit the subroutine and then return to the user program code. User program code will continue execution, from where it last stopped, until the next Flash Timer NMI is triggered and the Flash Timer NMI service routine entered (see Figure 4-6). The Flash Timer NMI service routine will first check the Flash Timer NMI status bit (NMISR.FNMIFLASHTIMER = 1) to ensure that the NMI source is from the Flash Timer before executing the remaining service routine instructions. Table 4-1 Subroutine Input D-Flash Program Subroutine DFF6H: DFLASH_PROG DPTR0: D-Flash WL address R0 of Register Bank 3 (IRAM address 18H): IRAM start address for 32-byte D-Flash data 32-byte D-Flash data Output PSW.CY: 0 = D-Flash programming is in progress 1 = DPTR0 is not pointing to valid D-Flash WL address DPTR0 is incremented by 20H Flash Timer NMI is enabled (NMICON.NMIFLASHTIMER = 1) Stack size required Resources used/destroyed Resources reserved1) Machine cycles taken 2) 8 PSW.CY, A, SCU_PAGE, DPTR1 R0 – R7 of Register Bank 3 (IRAM address 18H – 1FH) IRAM address 36H – 3DH 904 User’s Manual Flash Memory, V 0.3 4-11 V 0.2, 2005-01 XC866 Flash Memory 1) The data in the reserved resources must not be altered throughout the programming period (including Flash Timer NMI servicing) to ensure correct programming flow. 2) Estimated value without wait state. Upon completing the D-Flash programming sequence, the Flash Timer NMI will be disabled (NMICON.NMIFLASHTIMER = 0) by the program subroutine. For ‘end of D-Flash programming’ indication, the user can check one of the following: • Bit NMICON.NMIFLASHTIMER is cleared • R3 of Register Bank 3 (IRAM address 1BH) is 03H A manual check on the D-Flash data is necessary to determine the success of the programming via using the MOVC instruction to read out the D-Flash data. User’s Manual Flash Memory, V 0.3 4-12 V 0.2, 2005-01 XC866 Flash Memory 4.7.2 D-Flash Erasing The Flash erase subroutine can be called by the user to erase the sector(s) of the D-Flash bank. For each erasing sequence, it is possible to select one sector, a combination of several sectors or all 10 sectors to be erased. At the beginning of this subroutine, the Flash Timer NMI is enabled to enter the Flash Timer NMI service routine at each of the several timer underflows throughout the erasing sequence. Before calling this subroutine, the user must ensure that R3 and R4 of Register Bank 3 are set accordingly. The microcontroller will first initialize the erasing sequence, exit the subroutine, then return to the user program code. User program code will continue execution, from where it last stopped, until the next Flash Timer NMI is triggered and the Flash Timer NMI service routine is entered (see Figure 4-6). The Flash Timer NMI service routine will first perform a check on the Flash Timer NMI status bit (NMISR.FNMIFLASHTIMER = 1) to ensure that the NMI source is from the Flash Timer before executing the remaining service routine instructions. Table 4-2 Subroutine Input D-Flash Erase Subroutine DFF9H: DFLASH_ERASE R3 of Register Bank 3 (IRAM address 1BH): Select sector(s) to be erased for D-Flash bank. LSB represents sector 0, MSB represents sector 7. R4 of Register Bank 3 (IRAM address 1CH): Select sector(s) to be erased for D-Flash bank. LSB represents sector 8, bit 1 represents sector 9. Output Stack size required Resources used/destroyed Resources reserved1) Machine cycles taken 2) 1) Flash Timer NMI is enabled (NMICON.NMIFLASHTIMER = 1) 8 PSW.CY, A, SCU_PAGE, DPTR1 R0 – R7 of Register Bank 3 (IRAM address 18H – 1FH) IRAM address 36H – 3DH 358 The data in the reserved resources must not be altered throughout the erasing period (including Flash Timer NMI servicing) to ensure correct erasing flow. 2) Estimated value without wait state. User’s Manual Flash Memory, V 0.3 4-13 V 0.2, 2005-01 XC866 Flash Memory Upon completing the D-Flash erasing sequence, the Flash Timer NMI will be disabled (NMICON.NMIFLASHTIMER = 0) by the erase subroutine. For ‘end of D-Flash erasing’ indication, the user can check for one of the following: • Bit NMICON.NMIFLASHTIMER is cleared • R3 of Register Bank 3 (IRAM address 1BH) is 03H A manual check on the D-Flash data is necessary to determine the success of the erasing via a MOVC instruction. User’s Manual Flash Memory, V 0.3 4-14 V 0.2, 2005-01 XC866 Interrupt System 5 Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC866 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and determining the interrupt source. 5.1 Non-maskable Interrupt The Non-Maskable Interrupt (NMI) is similar to regular interrupts, except it has the highest priority (over other regular interrupts) when addressing important system events. In the XC866, any one of the following seven events can generate an NMI: • • • • • • WDT prewarning has occurred The PLL has lost the lock to the external crystal Flash Timer has overflowed JTAG-receiving or user interrupt is requested in monitor mode VDD is below the prewarning voltage level (2.3 V) VDDP is below the prewarning voltage level (4.0 V if the external power supply is 5.0 V) • Flash ECC error has occurred The NMISR register is used to hold the NMI request flags for these events. Corresponding bits in the NMICON register determine whether the NMI requests will be accepted or ignored. When any enabled NMI request is serviced, the software routine may clear the NMI request flags in the NMISR register. 5.2 Maskable Interrupts All regular interrupts are called maskable interrupts. A maskable interrupt can be masked or temporarily ignored by the processor while it completes its task. These interrupts can be classified into three types: internal interrupts, external interrupts, and extended interrupts. 5.2.1 Internal Interrupts There are three internal interrupts that proceed from Timer 0, Timer 1, and UART. These interrupt request signals go directly to the XC800 Core and their interrupt status is maintained by the core. Two interrupt flags TF0 and TF1 in the TCON register are set whenever Timer 0 or Timer 1, respectively, overflows. TF0 and TF1 are automatically cleared by hardware on entry to the corresponding interrupt service routine. User’s Manual Interrupt System, V 0.5 5-1 V 0.2, 2005-01 XC866 Interrupt System The UART interrupt source comprises the logical OR of the two serial interface interrupts. The interrupt flags RI and TI in register SCON are set automatically upon receipt or transmission of a data frame. These two bits must be cleared by software. 5.2.2 External Interrupts Seven external interrupts, EXT_INT[6:0], are driven into the XC866 from the ports. External interrupts can be positive, negative or double edge triggered. Registers EXICON0 and EXICON1 specify the active edge for the triggering of the external interrupt. Among the external interrupts, external interrupt 0 and external interrupt 1 can also be selected without edge detection. The interrupt request signal (caused with/without the edge triggered) to the core can further be programmed to either level activated or negative transition activated by setting or clearing bit ITx (x = 0 or 1), respectively, in the TCON register. If the external interrupt is positive (negative) edge triggered, the external source must hold the request pin low (high) for at least one CCLK cycle, and then hold it high (low) for at least one CCLK cycle to ensure that the transition is recognized. If edge detection is bypassed for external interrupt 0 and external interrupt 1, the external source must hold the request pin “high” or “low” for at least two CCLK cycles. 5.2.3 Extended Interrupts The extended interrupts are mainly for on-chip peripherals, which send interrupt requests to the core. There are nine interrupt request signals, XINTR_SRC[13:5], that are driven to the core, and each in turn receives an acknowledge signal XINTR_ACK[13:5] from the core. Some interrupt sources have their own request flag(s) located in a special function register (e.g., TCON, T2CON, SCON). Registers IRCON0 and IRCON1 are used to hold other interrupt request flags for extended and external interrupts. As the peripherals/devices have more interrupts lines than the core supports, some interrupts can be multiplexed and use the same interrupt input to the core. A few critical peripheral (e.g., timers, CCU6) interrupts are connected directly to the interrupt inputs of the core. Each interrupt input requested by the corresponding flag can be individually enabled or disabled by the enable/disabled bit in the SFR IEN0 or IEN1. In addition, there is a global enable bit EA (contained in Register IEN0) for all interrupts, which when cleared, disables all interrupts independent of their individual enable bits. Figure 5-1 to Figure 5-5 give a general overview of the interrupt sources and illustrate the request and control flags. User’s Manual Interrupt System, V 0.5 5-2 V 0.2, 2005-01 XC866 Interrupt System WDT Overflow FNMIWDT NMIISR.0 NMIWDT NMICON.0 PLL Loss of Lock FNMIPLL NMIISR.1 NMIPLL NMICON.1 Flash Timer Overflow FNMIFLASH TIMER NMIISR.2 NMIFLASHTIMER NMICON.2 Int 0 Int 1 Int 2 Int 3 Int 4 Int 5 Int 6 Int 7 Int 8 Int 9 Int 10 Int 11 Int 12 Int 13 >=1 OCDS interrupt FNMIOCDS NMISR.3 NMIOCDS NMICON.3 >=1 0073 H Non Maskable Interrupt VDD Pre-Warning FNMIVDD NMIISR.4 NMIVDD NMICON.4 VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIVDDP NMICON.5 Flash ECC Error FNMIECC NMIISR.6 NMIECC NMICON.6 Figure 5-1 Non-Maskable Interrupt Request Source User’s Manual Interrupt System, V 0.5 5-3 V 0.2, 2005-01 XC866 Interrupt System Highest Timer 0 Overflow TF0 TCON.5 ET0 IEN0.1 000B H IP.1/ IPH.1 Lowest Priority Level Timer 1 Overflow TF1 TCON.7 ET1 IEN0.3 001B H IP.3/ IPH.3 RI UART SCON.0 TI SCON.1 >=1 ES IEN0.4 0023 H IP.4/ IPH.4 P o l l i n g S e q u e n c e EINT0 EXINT0 IRCON0.0 IE0 TCON.1 IT0 TCON.0 EX0 IEN0.0 0003 H IP.0/ IPH.0 EXINT0 EXICON0.0/1 EINT1 EXINT1 IRCON0.1 IE1 TCON.3 IT1 TCON.2 EX1 IEN0.2 0013 H IP.2/ IPH.2 EXINT1 EXICON0.2/3 EA IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 5-2 Interrupt Request Sources (Part 1) User’s Manual Interrupt System, V 0.5 5-4 V 0.2, 2005-01 XC866 Interrupt System Highest Timer 2 Overflow TF2 T2CON.7 >=1 ET2 IEN0.5 002B H IP.5/ IPH.5 Lowest Priority Level T2EX EXEN2 EDGES EL T2MOD.5 T2CON.3 EXF2 T2CON.6 EINT2 EXINT2 IRCON0.2 EX2 IEN1.2 0043 H EXINT2 EXICON0.4/5 IP1.2/ IPH1.2 P o l l i n g S e q u e n c e EINT3 EXINT3 IRCON0.3 EXINT3 EXICON0.6/7 EINT4 EXINT4 IRCON0.4 EXINT3 EXICON1.0/1 EXM >=1 IEN1.3 004B H IP1.3/ IPH1.3 EINT5 EXINT5 IRCON0.5 EXINT5 EXICON1.2/3 EA EINT6 EXINT6 IRCON0.6 IEN0.7 EXINT6 EXICON1.4/5 Bit-addressable Request flag is cleared by hardware Figure 5-3 Interrupt Request Sources (Part 2) User’s Manual Interrupt System, V 0.5 5-5 V 0.2, 2005-01 XC866 Interrupt System Highest ADC_SRC0 ADCSRC0 IRCON1.3 >=1 EADC IEN1.0 0033 H IP1.0/ IPH1.0 ADC_SRC1 ADCSRC1 IRCON1.4 Lowest Priority Level SSC_EIR EIR IRCON1.0 SSC_TIR TIR IRCON1.1 >=1 ESSC IEN1.1 003B H IP1.1/ IPH1.1 SSC_RIR RIR IRCON1.2 Capture/Compare interrupt node 0 ECCIP0 IEN1.4 0053 H IP1.4/ IPH1.4 P o l l i n g S e q u e n c e Capture/Compare interrupt node 1 ECCIP1 IEN1.5 005B H IP1.5/ IPH1.5 Capture/Compare interrupt node 2 ECCIP2 IEN1.6 0063 H IP1.6/ IPH1.6 Capture/Compare interrupt node 3 ECCIP3 IEN1.7 006B H IP1.7/ IPH1.7 EA IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 5-4 Interrupt Request Sources (Part 3) User’s Manual Interrupt System, V 0.5 5-6 V 0.2, 2005-01 XC866 Interrupt System ICC60R CC60 ISL.0 ICC60F ISL.1 ICC61R CC61 ISL.2 ICC61F ISL.3 ICC62R CC62 ISL.4 ICC62F ISL.5 T12 One match T12 Period match T13 Compare match T13 Period match T12OM ISL.6 T12PM ISL.7 T13CM ISH.0 T13PM ISH.1 TRPF ISH.2 Wrong Hall Event Correct Hall Event Multi-Channel Shadow Transfer WHE ISH.5 CHE ISH.4 STR ISH.7 ENCC60R IENL.0 ENCC60F IENL.1 ENCC61R IENL.2 ENCC61F IENL.3 ENCC62R IENL.4 ENCC62F IENL.5 ENT12OM IENL.6 ENT12PM IENL.7 ENT13CM IENH.0 ENT13PM IENH.1 ENTRPF IENH.2 ENWHE IENH.5 >=1 INPL.1 INPL.0 >=1 INPL.3 INPL.2 >=1 INPL.5 INPL.4 >=1 INPH.3 INPH.2 >=1 INPH.5 INPH.4 CTRAP >=1 INPH.1 INPH.0 ENCHE IENH.4 ENSTR IENH.7 >=1 INPL.7 INPL.6 CCU6 Interrupt node 0 CCU6 Interrupt node 1 CCU6 Interrupt node 2 CCU6 Interrupt node 3 Figure 5-5 Interrupt Request Sources (Part 4) User’s Manual Interrupt System, V 0.5 5-7 V 0.2, 2005-01 XC866 Interrupt System 5.3 Interrupt Source and Vector Each interrupt input has an associated interrupt vector address. This vector is accessed in order to service the corresponding interrupt source. The assignment of the XC866 interrupt sources is summarized in Table 5-1. Table 5-1 Interrupt Input NMI XINTR0 XINTR1 XINTR2 XINTR3 XINTR4 XINTR5 XINTR6 XINTR7 XINTR8 XINTR9 XINTR10 XINTR11 XINTR12 XINTR13 Interrupt Vector Addresses Vector Address 0073H 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 004BH 0053H 005BH 0063H 006BH Interrupt Sources Watchdog Timer, PLL, Flash Interface Timer, OCDS, VDD and VDDP prewarning, Flash ECC External Interrupt 0 Timer 0 External Interrupt 1 Timer 1 UART Timer 2 ADC_SRC[1:0] SSC External Interrupt 2 External Interrupt [6:3] CCU6 INP0 CCU6 INP1 CCU6 INP2 CCU6 INP3 User’s Manual Interrupt System, V 0.5 5-8 V 0.2, 2005-01 XC866 Interrupt System 5.4 5.4.1 Interrupt Register Description Interrupt Enable Registers Each interrupt input can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 or IEN1. Register IEN0 also contains the global enable/disable bit (EA), which can be cleared to disable all interrupts. The NMI interrupt is shared by a number of sources, each of which can be enabled or disabled individually via register NMICON. After reset, the enable bits of IEN0, IEN1 and NMICON are cleared to 0. This implies that the corresponding interrupts are disabled. IEN0 Interrupt Enable Register 0 7 EA rw 6 0 r 5 ET2 rw 4 ES rw 3 ET1 rw 2 EX1 rw Reset Value: 00H 1 ET0 rw 0 EX0 rw Field EX0 Bits 0 Type Description rw Enable External Interrupt 0 0 External Interrupt 0 is disabled. 1 External Interrupt 0 is enabled. Enable Timer 0 Overflow Interrupt 0 Timer 0 Overflow interrupt is disabled. 1 Timer 0 Overflow interrupt is enabled. Enable External Interrupt 1 0 External interrupt 1 is disabled. 1 External interrupt 1 is enabled. Enable Timer 1 Overflow Interrupt 0 Timer 1 Overflow interrupt is disabled. 1 Timer 1 Overflow interrupt is enabled. Enable Serial Port Interrupt 0 Serial Port interrupt is disabled. 1 Serial Port interrupt is enabled. Enable Timer 2 Interrupt 0 Timer 2 interrupt is disabled. 1 Timer 2 interrupt is enabled. ET0 1 rw EX1 2 rw ET1 3 rw ES 4 rw ET2 5 rw User’s Manual Interrupt System, V 0.5 5-9 V 0.2, 2005-01 XC866 Interrupt System Field EA Bits 7 Type Description rw Enable/Disable All Interrupts 0 No interrupt will be acknowledged 1 Each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Returns 0 if read; should be written with 0. 0 6 r IEN1 Interrupt Enable Register 1 7 ECCIP3 rw 6 ECCIP2 rw 5 ECCIP1 rw 4 ECCIP0 rw 3 EXM rw 2 EX2 rw Reset Value: 00H 1 ESSC rw 0 EADC rw Field EADC Bits 0 Type Description rw ADC Interrupt Enable 0 ADC interrupts are disabled. 1 ADC interrupts are enabled. SSC Interrupt Enable 0 SSC interrupts are disabled. 1 SSC interrupts are enabled. External Interrupt 2 Enable 0 External interrupt 2 is disabled. 1 External interrupt 2 is enabled. External Interrupts [6:3] Enable 0 External interrupts [6:3] are disabled. 1 External interrupt [6:3] are enabled. CCU6 Interrupt Node Pointer 0 Enable 0 CCU6 Interrupt Node Pointer 0 is disabled. 1 CCU6 Interrupt Node Pointer 0 is enabled. CCU6 Interrupt Node Pointer 1 Enable 0 CCU6 Interrupt Node Pointer 1 is disabled. 1 CCU6 Interrupt Node Pointer 1 is enabled. ESSC 1 rw EX2 2 rw EXM 3 rw ECCIP0 4 rw ECCIP1 5 rw User’s Manual Interrupt System, V 0.5 5-10 V 0.2, 2005-01 XC866 Interrupt System Field ECCIP2 Bits 6 Type Description rw CCU6 Interrupt Node Pointer 2 Enable 0 CCU6 Interrupt Node Pointer 2 is disabled. 1 CCU6 Interrupt Node Pointer 2 is enabled. CCU6 Interrupt Node Pointer 3 Enable 0 CCU6 Interrupt Node Pointer 3 is disabled. 1 CCU6 Interrupt Node Pointer 3 is enabled. ECCIP3 7 rw NMICON NMI Control Register 7 0 r 6 NMIECC rw 5 NMIVDDP rw 4 NMIVDD rw 3 NMIOCDS rw 2 NMIFLASHTIMER rw Reset Value: 00H 1 NMIPLL rw 0 NMIWDT rw Field NMIWDT Bits 0 Type Description rw Watchdog Timer NMI Enable 0 WDT NMI is disabled. 1 WDT NMI is enabled. PLL Loss of Lock NMI Enable 0 PLL Loss of Lock NMI is disabled. 1 PLL Loss of Lock NMI is enabled. Flash Timer NMI Enable 0 Flash Timer NMI is disabled. 1 Flash Timer NMI is enabled. OCDS NMI Enable 0 OCDS NMI is disabled. 1 OCDS NMI is enabled. VDD Prewarning NMI Enable 0 VDD NMI is disabled. 1 VDD NMI is enabled. VDDP Prewarning NMI Enable 0 VDDP NMI is disabled. 1 VDDP NMI is enabled. Note: When the external power supply is 3.3 V, the user must disable NMIVDDP. NMIPLL 1 rw NMIFLASHTIMER NMIOCDS 2 rw 3 rw NMIVDD 4 rw NMIVDDP 5 rw User’s Manual Interrupt System, V 0.5 5-11 V 0.2, 2005-01 XC866 Interrupt System Field NMIECC Bits 6 Type Description rw ECC NMI Enable 0 ECC NMI is disabled. 1 ECC NMI is enabled. Reserved Returns 0 if read; should be written with 0. 0 7 r EXICON0 External Interrupt Control Register 0 7 EXINT3 rw 6 5 EXINT2 rw 4 3 EXINT1 rw 2 Reset Value: 00H 1 EXINT0 rw 0 Field EXINT0 Bits [1:0] Type Description rw External Interrupt 0 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Bypass the edge detection External Interrupt 1 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Bypass the edge detection External Interrupt 2 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved External Interrupt 3 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved EXINT1 [3:2] rw EXINT2 [5:4] rw EXINT3 [7:6] rw User’s Manual Interrupt System, V 0.5 5-12 V 0.2, 2005-01 XC866 Interrupt System EXICON1 External Interrupt Control Register 1 7 0 r 6 5 EXINT6 rw 4 3 EXINT5 rw 2 Reset Value: 00H 1 EXINT4 rw 0 Field EXINT4 Bits [1:0] Type Description rw External Interrupt 4 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved External Interrupt 5 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved External Interrupt 6 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved Reserved Returns 0 if read; should be written with 0. EXINT5 [3:2] rw EXINT6 [5:4] rw 0 [7:6] r User’s Manual Interrupt System, V 0.5 5-13 V 0.2, 2005-01 XC866 Interrupt System 5.4.2 Interrupt Request Flags The interrupt request flags for the different sources are located in several Special Function Registers (SFRs). This section details the locations and meanings of these interrupt request flags. IRCON0 Interrupt Request Register 0 7 0 r 6 EXINT6 rwh 5 EXINT5 rwh 4 EXINT4 rwh 3 EXINT3 rwh 2 EXINT2 rwh Reset Value: 00H 1 EXINT1 rwh 0 EXINT0 rwh Field EXINTx (x = 0 - 6) Bits [6:0] Type Description rwh Interrupt Request Flag for External Interrupts This bit is set by hardware and can only be cleared by software. 0 Interrupt request is not active. 1 Interrupt request is active. Reserved Returns 0 if read; should be written with 0. 0 7 r User’s Manual Interrupt System, V 0.5 5-14 V 0.2, 2005-01 XC866 Interrupt System IRCON1 Interrupt Request Register 1 7 6 0 r 5 4 3 2 RIR rwh Reset Value: 00H 1 TIR rwh 0 EIR rwh ADCSRC1 ADCSRC0 rwh rwh Field EIR Bits 0 Type Description rwh Error Interrupt Request Flag for SSC This bit is set by hardware and can only be cleared by software. 0 Interrupt request is not active. 1 Interrupt request is active. Transmit Interrupt Request Flag for SSC This bit is set by hardware and can only be cleared by software. 0 Interrupt request is not active. 1 Interrupt request is active. Receive Interrupt Request Flag for SSC This bit is set by hardware and can only be cleared by software. 0 Interrupt request is not active. 1 Interrupt request is active. Interrupt Request 0 Flag for ADC This bit is set by hardware and can only be cleared by software. 0 Interrupt request is not active. 1 Interrupt request is active. Interrupt Request 1 Flag for ADC This bit is set by hardware and can only be cleared by software. 0 Interrupt request is not active. 1 Interrupt request is active. Reserved Returns 0 if read; should be written with 0. TIR 1 rwh RIR 2 rwh ADCSRC0 3 rwh ADCSRC1 4 rwh 0 [7:5] r User’s Manual Interrupt System, V 0.5 5-15 V 0.2, 2005-01 XC866 Interrupt System TCON Timer Control Register 7 TF1 rwh 6 TR1 rw 5 TF0 rwh 4 TR0 rw 3 IE1 rwh 2 IT1 rw Reset Value: 00H 1 IE0 rwh 0 IT0 rw The functions of the shaded bits are not described here Field IT0 Bits 0 Type Description rw External Interrupt 0 Level/Edge Trigger Control Flag 0 Low level triggered external interrupt 0 is selected. 1 Falling edge triggered external interrupt 0 is selected. External Interrupt 0 Request Flag Set by hardware when external interrupt 0 edge is detected. Cleared by hardware when the processor vectors to interrupt routine. External Interrupt 1 Level/Edge Trigger Control Flag 0 Low level triggered external interrupt 1 is selected. 1 Falling edge triggered external interrupt 1 is selected. External Interrupt 1 Request Flag Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when the processor vectors to interrupt routine. Timer 0 Overflow Flag Set by hardware on Timer/Counter 0 overflow. Cleared by hardware when processor vectors to interrupt routine. IE0 1 rwh IT1 2 rw IE1 3 rwh TF0 5 rwh User’s Manual Interrupt System, V 0.5 5-16 V 0.2, 2005-01 XC866 Interrupt System Field TF1 Bits 7 Type Description rwh Timer 1 Overflow Flag Set by hardware on Timer/Counter 1 overflow. Cleared by hardware when processor vectors to interrupt routine. SCON Serial Channel Control Register 7 SM0 rw 6 SM1 rw 5 SM2 rw 4 REN rw 3 TB8 rw 2 RB8 rwh Reset Value: 00H 1 TI rwh 0 RI rwh The functions of the shaded bits are not described here Field RI Bits 0 Type Description rwh Serial Interface Receiver Interrupt Flag Set by hardware if a serial data byte has been received. Must be cleared by software. Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission. Must be cleared by software. TI 1 rwh NMISR NMI Status Register 7 0 r 6 FNMIECC rwh 5 FNMI VDDP rwh 4 FNMI VDD rwh 3 FNMI OCDS rwh 2 FNMIFLASHTIMER rwh Reset Value: 00H 1 0 FNMIPLL FNMIWDT rwh rwh Field FNMIWDT Bits 0 Type Description rwh Watchdog Timer NMI Flag 0 No Watchdog NMI occurred. 1 WDT prewarning has occurred. 5-17 V 0.2, 2005-01 User’s Manual Interrupt System, V 0.5 XC866 Interrupt System Field FNMIPLL Bits 1 Type Description rwh PLL NMI Flag 0 No PLL NMI occurred. 1 The PLL has lost the lock to the external crystal. Flash Timer NMI Flag 0 No Flash NMI occurred. 1 Flash Timer has overflowed. OCDS NMI Flag 0 No OCDS NMI occurred. 1 JTAG-receiving or user interrupt requested in monitor mode. VDD Prewarning NMI Flag 0 No VDD NMI occurred. 1 VDD is below the prewarning voltage level (2.3 V). VDDP Prewarning NMI Flag 0 No VDDP NMI occurred. 1 VDDP is below the prewarning voltage level (4.0 V if the external power supply is 5.0 V). ECC NMI Flag 0 No ECC error occurred. 1 ECC error has occurred. Reserved Returns 0 if read; should be written with 0. FNMIFLASHTIMER FNMIOCDS 2 rwh 3 rwh FNMIVDD 4 rwh FNMIVDDP 5 rwh FNMIECC 6 rwh 0 7 r Register NMISR can only be cleared by software or reset to the default value after the power-on reset/hardware reset/brownout reset. The register value is retained on any other reset such as watchdog timer reset or power-down wake-up reset. This allows the system to detect what caused the previous NMI. User’s Manual Interrupt System, V 0.5 5-18 V 0.2, 2005-01 XC866 Interrupt System 5.4.3 Interrupt Priority Registers Each interrupt source can be individually programmed to one of the four possible priority levels. Two pairs of interrupt priority registers are available to program the priority level of each interrupt vector. The first pair of registers is SFRs IP and IPH. IP Interrupt Priority Register 7 0 r 6 5 PT2 rw 4 PS rw 3 PT1 rw 2 PX1 rw Reset Value: 00H 1 PT0 rw 0 PX0 rw IPH Interrupt Priority Register High 7 0 r 6 5 PT2H rw 4 PSH rw 3 PT1H rw 2 PX1H rw Reset Value: 00H 1 PT0H rw 0 PX0H rw Field PX0, PX0H PT0, PT0H PX1, PX1H PT1, PT1H PS, PSH PT2, PT2H 0 Bits 0 1 2 3 4 5 [7:6] Type Description rw rw rw rw rw rw r Priority Level for External Interrupt 0 Priority Level for Timer 0 Overflow Interrupt Priority Level for External Interrupt 1 Priority Level for Timer 1 Overflow Interrupt Priority Level for Serial Port Interrupt Priority Level for Timer 2 Interrupt Reserved Returns 0 if read; should be written with 0. User’s Manual Interrupt System, V 0.5 5-19 V 0.2, 2005-01 XC866 Interrupt System The second pair of interrupt priority registers is SFRs IP1 and IPH1. IP1 Interrupt Priority Register 1 7 PCCIP3 rw 6 PCCIP2 rw 5 PCCIP1 rw 4 PCCIP0 rw 3 PXM rw 2 PX2 rw Reset Value: 00H 1 PSSC rw 0 PADC rw IPH1 Interrupt Priority Register 1 High 7 PCCIP3H rw 6 PCCIP2H rw 5 PCCIP1H rw 4 PCCIP0H rw 3 PXMH rw 2 PX2H rw Reset Value: 00H 1 PSSCH rw 0 PADCH rw Field PADC, PADCH PSSC, PSSCH PX2, PX2H PXM, PXMH PCCIP0, PCCIP0H PCCIP1, PCCIP1H PCCIP2, PCCIP2H PCCIP3, PCCIP3H Bits 0 1 2 3 4 5 6 7 Type Description rw rw rw rw rw rw rw rw Priority Level for ADC Interrupt Priority Level for SSC Interrupt Priority Level for External Interrupt 2 Priority Level for External Interrupt 3 to 6 Priority Level for CCU6 Interrupt Node Pointer 0 Priority Level for CCU6 Interrupt Node Pointer 1 Priority Level for CCU6 Interrupt Node Pointer 2 Priority Level for CCU6 Interrupt Node Pointer 3 User’s Manual Interrupt System, V 0.5 5-20 V 0.2, 2005-01 XC866 Interrupt System 5.4.4 Interrupt Priority The respective bit fields of the interrupt priority registers together select one of the four priority levels as shown in Table 5-2. Table 5-2 0 0 1 1 Interrupt Priority Level Selection IP.x / IP1.x 0 1 0 1 Priority Level Level 0 (lowest) Level 1 Level 2 Level 3 (highest) IPH.x / IPH1.x Note: As the NMI has the highest priority, it does not use the level selection shown in Table 5-2. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot be interrupted by any other interrupt source. If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced first. Thus, within each priority level, there is a second priority structure determined by the polling sequence as shown in Table 5-3. Table 5-3 Source Non-Maskable Interrupt (NMI) External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt UART Interrupt Timer 2 Interrupt ADC Interrupt SSC Interrupt External Interrupt 2 External Interrupt [6:3] CCU6 Interrupt Node Pointer 0 User’s Manual Interrupt System, V 0.5 Priority Structure within Interrupt Level Level (highest) 1 2 3 4 5 6 7 8 9 10 11 5-21 V 0.2, 2005-01 XC866 Interrupt System Table 5-3 Source CCU6 Interrupt Node Pointer 1 CCU6 Interrupt Node Pointer 2 CCU6 Interrupt Node Pointer 3 Priority Structure within Interrupt Level (cont’d) Level 12 13 14 5.4.5 Interrupt Request Flags The interrupt request flags are located in different SFRs. Table 5-4 shows the bit locations of the interrupt request flags. Detailed information about the interrupt request flags is provided in the respective peripheral chapters. Table 5-4 Locations of the Interrupt Request Flags Request Flags TF0 TF1 TF2 EXF2 UART External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 ADC Interrupt SSC Interrupt RI TI IE0 IE1 EXINT2 EXINT3 EXINT4 EXINT5 EXINT6 ADCSRC0 ADCSRC1 EIR TIR RIR CCU6 Node 0 Interrupt CCU6 Node 1 Interrupt CCU6 Node 2 Interrupt User’s Manual Interrupt System, V 0.5 5-22 Interrupt Source Timer 0 Interrupt Timer 1 Interrupt Timer 2 Interrupt SFR TCON TCON T2CON T2CON SCON SCON TCON TCON IRCON0 IRCON0 IRCON0 IRCON0 IRCON0 IRCON1 IRCON1 IRCON1 IRCON1 IRCON1 INPL/INPH INPL/INPH INPL/INPH V 0.2, 2005-01 See note 1) See note1) See note1) XC866 Interrupt System Table 5-4 Locations of the Interrupt Request Flags (cont’d) Request Flags See note FNMIWDT FNMIPLL FNMI FLASHTIMER FNMIOCDS FNMIVDD FNMIVDDP FNMIECC 1) Interrupt Source CCU6 Node 3 Interrupt Watchdog Timer NMI PLL NMI Flash Timer NMI OCDS NMI VDD NMI VDDP NMI ECC NMI 1) SFR INPL/INPH NMISR NMISR NMISR NMISR NMISR NMISR NMISR Different CCU6 interrupts can be assigned to different CCU6 interrupt nodes[3:0], which are selected via registers INPL/INPH. 5.5 Interrupt Handling The interrupt flags are sampled at phase 2 in each machine cycle. The sampled flags are then polled during the following machine cycle. If one of the flags was in a set condition at phase 2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: • An interrupt of equal or higher priority is already in progress. • The current (polling) cycle is not in the final cycle of the instruction in progress. • The instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP,IPH/IP1,IP1H. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP,IPH/IP1,IP1H, then at least one more instruction will be executed before any interrupt is vectored to; this delay guarantees that changes of the interrupt status can be observed by the CPU. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at phase 2 of the previous machine cycle. Note that if any interrupt flag is active but was not responded to for one of the conditions already mentioned, or if the flag was no longer active at the time of removal of the blocking condition, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the pending interrupt requests. Figure 5-6 shows the timing example for extended interrupts. User’s Manual Interrupt System, V 0.5 5-23 V 0.2, 2005-01 XC866 Interrupt System | C..P2 | C L P1 | C L P2 | C 1P1 | C 1P2 | C 2P1 | C 2P2 PCLK XINTR_SCR[1] XINTR_ACK[1] Interrupts sampled here Figure 5-6 Timing for Extended Interrupt The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. In some cases, hardware also clears the flag that generated the interrupt, while in other cases, the flag must be cleared by the user’s software. The hardware-generated LCALL pushes the contents of the Program Counter (PC) onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to, as shown in the Table 5-1. Program execution returns to the next instruction after calling the interrupt when the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the two top bytes from the stack and reloads the PC. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI instruction is important because it informs the processor that the program has left the current interrupt priority level. A simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system on the assumption that an interrupt was still in progress. In this case, no interrupt of the same or lower priority level would be acknowledged. 5.6 Interrupt Response Time If an interrupt is recognized, its corresponding request flag is set at phase 2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two machine cycles. Thus, a minimum of three complete machine cycles will elapse from activation of the interrupt request to the beginning of execution of the first instruction of the service routine. A longer response time would be obtained if the request is blocked by one of the three previously listed conditions. If an User’s Manual Interrupt System, V 0.5 5-24 V 0.2, 2005-01 XC866 Interrupt System interrupt of equal or higher priority is already in progress, the additional wait time will depend on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than three machine cycles. The longest instructions (MUL and DIV) are only four machine cycles long. If the instruction in progress is RETI or a write access to registers IEN0, IEN1 or IP(H), IP1(H), the additional wait time cannot be more than five cycles (a maximum of one more machine cycle to complete the instruction in progress, plus four machine cycles to complete the next instruction, if the instruction is MUL or DIV). Thus, in a single interrupt system, if the wait states are not considered, the response time is between three and nine machine cycles. User’s Manual Interrupt System, V 0.5 5-25 V 0.2, 2005-01 XC866 Parallel Ports 6 Parallel Ports The XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Port P2 is an input-only port, providing general purpose input functions, alternate input functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital Converter (ADC). Bidirectional Port Features: • • • • • Configurable pin direction Configurable pull-up/pull-down devices Configurable open drain mode Transfer of data through digital inputs and outputs (general purpose I/O) Alternate input/output for on-chip peripherals Input Port Features: • • • • Configurable pull-up/pull-down devices Receive of data through digital input (general purpose input) Alternate input for on-chip peripherals Analog input for ADC module User’s Manual Parallel Ports, V 0.3 6-1 V 0.2, 2005-01 XC866 Parallel Ports 6.1 General Port Operation Figure 6-1 shows the block diagram of an XC866 bidirectional port pin. Each port pin is equipped with a number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the control register, each individual pin can be configured as an input or an output. The user can also configure each pin as an open drain pin with or without internal pull-up/pull-down device. Each bidirectional port pin can be configured for input or output operation. Switching between input and output mode is accomplished through the register Px_DIR (x = 0, 1 or 3), which enables or disables the output and input drivers. A port pin can only be configured as either input or output mode at any one time. In input mode (default after reset), the output driver is switched off (high-impedance). The actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt-Trigger device and can be read via the register Px_DATA. In output mode, the output driver is activated and drives the value supplied through the multiplexer to the port pin. In the output driver, each port line can be switched to open drain mode or normal mode (push-pull mode) via the register Px_OD. The output multiplexer in front of the output driver enables the port output function to be used for different purposes. If the pin is used for general purpose output, the multiplexer is switched by software to the data register Px_DATA. Software can set or clear the bit in Px_DATA and therefore directly influence the state of the port pin. If an on-chip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be switched via the multiplexer to the output driver circuitry. Selection of the alternate function is defined in registers Px_ALTSEL0 and Px_ALTSEL1. When a port pin is used as an alternate function, its direction must be set accordingly in the register Px_DIR. Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register Px_PUDSEL selects whether a pull-up or the pull-down device is activated while register Px_PUDEN enables or disables the pull device. To achieve high speed I/O data transfer, each I/O pin can be switched for direct connection to the various inputs of the peripheral units (AltDataIn). The function of the input line from the pin to the data register Px_DATA and to AltDataIn is independent of whether the port pin operates as input or output. This means that when the pin is in output mode, the level of the pin can be read by software via Px_DATA or a peripheral can use the pin level as an input. This offers additional advantages in an application: • When the pin is configured as general purpose output, the data written to the data register Px_DATA by software can be used as input data to an on-chip peripheral. This enables, for example, peripheral tests via software without external circuitry. Examples for this can be the triggering of a timer count input, generating an external interrupt, or simulating the incoming serial data stream to a serial port receive input via software. User’s Manual Parallel Ports, V 0.3 6-2 V 0.2, 2005-01 XC866 Parallel Ports • When the pin is configured for alternate output function, the output data that is driven to the pin by a peripheral can be read through software via Px_DATA or used by the same or another peripheral as input data. This enables testing of peripheral functions or provides additional connections between on-chip peripherals via the same pin without external wires. Internal Bus Px_PUDSEL Pull-up/Pull-down Select Register Pull-up/Pull-down Control Logic Px_PUDEN Pull-up/Pull-down Enable Register Open Drain Control Register Px_OD Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 Alternate Select Register 1 Px_ALTSEL1 Pull Device 10 01 00 AltDataOut 2 AltDataOut1 Output Driver Pin Data Register Px_Data Out In Input Driver AltDataIn Schmitt Trigger Pad Figure 6-1 General Structure of Bidirectional Port User’s Manual Parallel Ports, V 0.3 6-3 V 0.2, 2005-01 XC866 Parallel Ports Figure 6-2 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. The actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt-Trigger device and can be read via the register P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register P2_PUDSEL selects whether a pull-up or the pull-down device is activated while register P2_PUDEN enables or disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt-Trigger device for direct feedthrough to the ADC input channel. Internal Bus P2_PUDSEL Pull-up/Pull-down Select Register Pull-up/Pull-down Control Logic Pull-up/Pull-down Enable Register P2_PUDEN Pull Device Data Register P2_Data In Input Driver Pin Schmitt Trigger Pad AltDataIn AnalogIn Figure 6-2 General Structure of Input Port User’s Manual Parallel Ports, V 0.3 6-4 V 0.2, 2005-01 XC866 Parallel Ports 6.1.1 General Register Description The individual control and data bits of each parallel port are implemented in a number of 8-bit registers. Bits with the same meaning and function are assembled together in the same register. The registers configure and use the port as general purpose I/O or alternate function input/output. For port P2, not all the registers in Table 6-1 are implemented. The availability and definition of registers specific to each port is defined in Section 6.3 to Section 6.6. This section provides only an overview of the different port registers. Table 6-1 Port Registers Register Full Name Port x Data Register Port x Direction Register Port x Open Drain Control Register Port x Pull-Up/Pull-Down Select Register Port x Pull-Up/Pull-Down Enable Register Port x Alternate Select Register 0 Port x Alternate Select Register 1 Description see Page 6-6 Page 6-7 Page 6-7 Page 6-8 Page 6-8 Page 6-10 Page 6-10 Register Short Name Px_DATA Px_DIR Px_OD Px_PUDSEL Px_PUDEN Px_ALTSEL0 Px_ALTSEL1 User’s Manual Parallel Ports, V 0.3 6-5 V 0.2, 2005-01 XC866 Parallel Ports 6.1.1.1 Data Register If a port pin is used as general purpose output, output data is written into the data register Px_DATA. If a port pin is used as general purpose input, the latched value of the port pin can be read through register Px_DATA. Note: A port pin that has been assigned as input will latch in the active internal pull-up/ pull-down setting if it is not driven by an external source. This results in register Px_DATA being updated with the active pull value. Px_DATA Port x Data Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type rw Description Port x Pin n Data Value 0 Port x pin n data value = 0 1 Port x pin n data value = 1 Bit Px_DATA.n can only be written if the corresponding pin is set to output (Px_DIR.n = 1) and cannot be written if the corresponding pin is set to input (Px_DIR.n = 0). The content of Px_DATA.n is output on the assigned pin if the pin is assigned as GPIO pin and the direction is switched/set to output. A read operation of Px_DATA returns the register value and not the state of the corresponding Px_DATA pin. User’s Manual Parallel Ports, V 0.3 6-6 V 0.2, 2005-01 XC866 Parallel Ports 6.1.1.2 Direction Register The direction of port pins is controlled by the respective direction register Px_DIR. Px_DIR Port x Direction Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Port x Pin n Direction Control 0 Direction is set to input. 1 Direction is set to output. 6.1.1.3 Open Drain Control Register Each pin in output mode can be switched to open drain mode. If driven with 1, no driver will be activated and the pin output state depends on the internal pull-up/pull-down device setting. If driven with 0, the driver’s pull-down transistor will be activated. The open drain mode is controlled by the register Px_OD. Px_OD Port x Open Drain Control Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Port x Pin n Open Drain Mode 0 Normal mode; output is actively driven for 0 and 1 state 1 Open drain mode; output is actively driven only for 0 state User’s Manual Parallel Ports, V 0.3 6-7 V 0.2, 2005-01 XC866 Parallel Ports 6.1.1.4 Pull-Up/Pull-Down Device Register Internal pull-up/pull-down devices can be optionally applied to a port pin. This offers the possibility of configuring the following input characteristics: • tristate • high-impedance with a weak pull-up device • high-impedance with a weak pull-down device and the following output characteristics: • push/pull (optional pull-up/pull-down) • open drain with internal pull-up • open drain with external pull-up The pull-up/pull-down device can be fixed or controlled via the registers Px_PUDSEL and Px_PUDEN. Register Px_PUDSEL selects the type of pull-up/pull-down device, while register Px_PUDEN enables or disables it. The pull-up/pull-down device can be selected pinwise. Px_PUDSEL Port x Pull-Up/Pull-Down Select Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Pull-Up/Pull-Down Select Port x Bit n 0 Pull-down device is selected. 1 Pull-up device is selected. Px_PUDEN Port x Pull-Up/Pull-Down Enable Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw 1 P1 rw 0 P0 rw User’s Manual Parallel Ports, V 0.3 6-8 V 0.2, 2005-01 XC866 Parallel Ports Field Pn (n = 0 – 7) Bits n Type Description rw Pull-Up/Pull-Down Enable at Port x Bit n 0 Pull-up or Pull-down device is disabled. 1 Pull-up or Pull-down device is enabled. User’s Manual Parallel Ports, V 0.3 6-9 V 0.2, 2005-01 XC866 Parallel Ports 6.1.1.5 Alternate Input Functions The number of alternate functions that uses a pin for input is not limited. Each port control logic of an I/O pin provides several input paths: • Digital input value via register • Direct digital input value 6.1.1.6 Alternate Output Functions Alternate functions are selected via an output multiplexer. This multiplexer can be controlled by the following registers: • Register Px_ALTSEL0 • Register Px_ALTSEL1 Selection of alternate functions is defined in registers Px_ALTSEL0 and Px_ALTSEL1. Px_ALTSELn (n = 0 - 1) Port x Alternate Select Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw 1 P1 rw 0 P0 rw Function of Bits Px_ALTSEL0.Pn and Px_ALTSEL1.Pn Px_ALTSEL0.Pn 0 1 0 1 Px_ALTSEL1.Pn 0 0 1 1 Function Normal GPIO Alternate Output 1 Alternate Output 2 Reserved Note: Set Px_ALTSEL0.Pn and Px_ALTSEL1.Pn to select only implemented alternate output functions. User’s Manual Parallel Ports, V 0.3 6-10 V 0.2, 2005-01 XC866 Parallel Ports 6.2 Register Map The Port SFRs are located in the standard memory area (RMAP = 0) and are organized into 4 pages. The PORT_PAGE register is located at address B2H. It contains the page value and page control information. PORT_PAGE Page Register for PORT 7 OP w 6 5 STNR w 4 3 0 r 2 Reset Value: 00H 1 PAGE rw 0 Field PAGE Bits [2:0] Type Description rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. STNR [5:4] w User’s Manual Parallel Ports, V 0.3 6-11 V 0.2, 2005-01 XC866 Parallel Ports Field OP Bits [7:6] Type Description w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. Reserved Returns 0 if read; should be written with 0. 0 3 r User’s Manual Parallel Ports, V 0.3 6-12 V 0.2, 2005-01 XC866 Parallel Ports The addresses of the Port SFRs are listed in Table 6-2. Table 6-2 Address 80H 86H 90H 91H A0H A1H B0H B1H SFR Address List for Pages 0-3 Page 0 P0_DATA P0_DIR P1_DATA P1_DIR P2_DATA – P3_DATA P3_DIR Page 1 P0_PUDSEL P0_PUDEN P1_PUDSEL P1_PUDEN P2_PUDSEL P2_PUDEN P3_PUDSEL P3_PUDEN Page 2 P0_ALTSEL0 P0_ALTSEL1 P1_ALTSEL0 P1_ALTSEL1 – – P3_ALTSEL0 P3_ALTSEL1 Page 3 P0_OD – P1_OD – – – P3_OD – User’s Manual Parallel Ports, V 0.3 6-13 V 0.2, 2005-01 XC866 Parallel Ports 6.3 Port 0 Port P0 is a 6-bit general purpose bidirectional port. The registers of P0 are summarized in Table 6-3. Table 6-3 P0_DATA P0_DIR P0_OD P0_PUDSEL P0_PUDEN P0_ALTSEL0 P0_ALTSEL1 Port 0 Registers Port 0 Data Register Port 0 Direction Register Port 0 Open Drain Control Register Port 0 Pull-Up/Pull-Down Select Register Port 0 Pull-Up/Pull-Down Enable Register Port 0 Alternate Select Register 0 Port 0 Alternate Select Register 1 Register Short Name Register Full Name 6.3.1 Table 6-4 Port Pin P0.0 Functions Port 0 Input/Output Functions Input/Output Select Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 Connected Signal(s) P0_DATA.P0 TCK_0 T12HR_1 CC61_1 P0_DATA.P0 CLKOUT CC61_1 P0_DATA.P1 TDI_0 T13HR_1 RXD_1 P0_DATA.P1 – COUT61_1 From/to Module – JTAG CCU6 CCU6 – On-chip OSC CCU6 – JTAG CCU6 UART – – CCU6 P0.1 Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 User’s Manual Parallel Ports, V 0.3 6-14 V 0.2, 2005-01 XC866 Parallel Ports Table 6-4 Port Pin P0.2 Port 0 Input/Output Functions (cont’d) Input/Output Select Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 P0.3 Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 P0.4 Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 P0.5 Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 Connected Signal(s) P0_DATA.P2 – CTRAP_2 – P0_DATA.P2 TDO_0 TXD_1 P0_DATA.P3 SCK_1 – – P0_DATA.P3 SCK_1 COUT63_1 P0_DATA.P4 MTSR_1 – CC62_1 P0_DATA.P4 MTSR_1 CC62_1 P0_DATA.P5 MRST_1 EXINT0_0 – P0_DATA.P5 MRST_1 COUT62_1 From/to Module – – CCU6 – – JTAG UART – SSC – – – SSC CCU6 – SSC – CCU6 – SSC CCU6 – SSC External interrupt 0 – – SSC CCU6 User’s Manual Parallel Ports, V 0.3 6-15 V 0.2, 2005-01 XC866 Parallel Ports 6.3.2 Register Description P0_DATA Port 0 Data Register 7 0 r 6 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 5) 0 Bits n Type rw Description Port 0 Pin n Data Value 0 Port 0 pin n data value = 0 (default) 1 Port 0 pin n data value = 1 Reserved Returns 0 if read; should be written with 0. [7:6] r P0_DIR Port 0 Direction Register 7 0 r 6 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 5) 0 Bits n Type Description rw Port 0 Pin n Direction Control 0 Direction is set to input (default). 1 Direction is set to output. Reserved Returns 0 if read; should be written with 0. [7:6] r User’s Manual Parallel Ports, V 0.3 6-16 V 0.2, 2005-01 XC866 Parallel Ports P0_OD Port 0 Open Drain Control Register 7 0 r 6 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 5) Bits n Type Description rw Port 0 Pin n Open Drain Mode 0 Normal mode; output is actively driven for 0 and 1 state (default) 1 Open drain mode; output is actively driven only for 0 state Reserved Returns 0 if read; should be written with 0. 0 [7:6] r P0_PUDSEL Port 0 Pull-Up/Pull-Down Select Register 7 0 r 6 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: FFH 1 P1 rw 0 P0 rw Field Pn (n = 0 – 5) 0 Bits n Type Description rw Pull-Up/Pull-Down Select Port 0 Bit n 0 Pull-down device is selected. 1 Pull-up device is selected (default). Reserved Returns 0 if read; should be written with 0. [7:6] r User’s Manual Parallel Ports, V 0.3 6-17 V 0.2, 2005-01 XC866 Parallel Ports P0_PUDEN Port 0 Pull-Up/Pull-Down Enable Register 7 0 r 6 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: C4H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 5) 0 Bits n Type Description rw Pull-Up/Pull-Down Enable at Port 0 Bit n 0 Pull-up or Pull-down device is disabled. 1 Pull-up or Pull-down device is enabled (default). Reserved Returns 0 if read; should be written with 0. [7:6] r P0_ALTSELn (n = 0 – 1) Port 0 Alternate Select Register 7 0 r 6 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Table 6-5 0 1 0 1 Function of Bits P0_ALTSEL0.Pn and P0_ALTSEL1.Pn P0_ALTSEL1.Pn 0 0 1 1 Function Normal GPIO Alternate Output 1 Alternate Output 2 Reserved P0_ALTSEL0.Pn User’s Manual Parallel Ports, V 0.3 6-18 V 0.2, 2005-01 XC866 Parallel Ports 6.4 Port 1 Port P1 is a 5-bit general purpose bidirectional port. The registers of P1 are summarized in Table 6-6. Table 6-6 P1_DATA P1_DIR P1_OD P1_PUDSEL P1_PUDEN P1_ALTSEL0 P1_ALTSEL1 Port 1 Registers Port 1 Data Register Port 1 Direction Register Port 1 Open Drain Control Register Port 1 Pull-Up/Pull-Down Select Register Port 1 Pull-Up/Pull-Down Enable Register Port 1 Alternate Select Register 0 Port 1 Alternate Select Register 1 Register Short Name Register Full Name 6.4.1 Table 6-7 Port Pin P1.0 Functions Port 1 Input/Output Functions Input/Output Select Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 Connected Signal(s) P1_DATA.P0 RXD_0 T2EX – P1_DATA.P0 – – P1_DATA.P1 – EXINT3 – P1_DATA.P1 TDO_1 TXD_0 From/to Module – UART Timer 2 – – – – – – External interrupt 3 – – JTAG UART P1.1 Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 User’s Manual Parallel Ports, V 0.3 6-19 V 0.2, 2005-01 XC866 Parallel Ports Table 6-7 Port Pin P1.5 Port 1 Input/Output Functions (cont’d) Input/Output Select Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 P1.6 Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 P1.7 Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 1) 2) Connected Signal(s) P1_DATA.P5 CCPOS0_1 EXINT5 – P1_DATA.P5 1) – – P1_DATA.P6 CCPOS1_1 T12HR_0 EXINT6 P1_DATA.P62) – – P1_DATA.P7 CCPOS2_1 T13HR_0 – P1_DATA.P7 – – From/to Module – CCU6 External interrupt 5 – – – – – CCU6 CCU6 External interrupt 6 – – – – CCU6 CCU6 – – – – P1.5 can be used as a software Chip Select function for the SSC. P1.6 can be used as a software Chip Select function for the SSC. User’s Manual Parallel Ports, V 0.3 6-20 V 0.2, 2005-01 XC866 Parallel Ports 6.4.2 Register Description P1_DATA Port 1 Data Register 7 P7 rw 6 P6 rw 5 P5 rw 4 3 0 r 2 Reset Value: 00H 1 P1 rw 0 P0 rw Field Bits Type rw Description Port 1 Pin n Data Value 0 Port 1 pin n data value = 0 (default) 1 Port 1 pin n data value = 1 Reserved Returns 0 if read; should be written with 0. Pn n (n = 0 – 1, 5 – 7) 0 [4:2] r P1_DIR Port 1 Direction Register 7 P7 rw 6 P6 rw 5 P5 rw 4 3 0 r 2 Reset Value: 00H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 1, 5 – 7) 0 Bits n Type Description rw Port 1 Pin n Direction Control 0 Direction is set to input (default). 1 Direction is set to output. Reserved Returns 0 if read; should be written with 0. [4:2] r User’s Manual Parallel Ports, V 0.3 6-21 V 0.2, 2005-01 XC866 Parallel Ports P1_OD Port 1 Open Drain Control Register 7 P7 rw 6 P6 rw 5 P5 rw 4 3 0 r 2 Reset Value: 00H 1 P1 rw 0 P0 rw Field Bits Type Description rw Port 1 Pin n Open Drain Mode 0 Normal mode; output is actively driven for 0 and 1 state (default) 1 Open drain mode; output is actively driven only for 0 state Reserved Returns 0 if read; should be written with 0. Pn n (n = 0 – 1, 5 – 7) 0 [4:2] r P1_PUDSEL Port 1 Pull-Up/Pull-Down Select Register 7 P7 rw 6 P6 rw 5 P5 rw 4 3 0 r 2 Reset Value: FFH 1 P1 rw 0 P0 rw Field Bits Type Description rw Pull-Up/Pull-Down Select Port 1 Bit n 0 Pull-down device is selected. 1 Pull-up device is selected (default). Reserved Returns 0 if read; should be written with 0. Pn n (n = 0 – 1, 5 – 7) 0 [4:2] r User’s Manual Parallel Ports, V 0.3 6-22 V 0.2, 2005-01 XC866 Parallel Ports P1_PUDEN Port 1 Pull-Up/Pull-Down Enable Register 7 P7 rw 6 P6 rw 5 P5 rw 4 3 0 r 2 Reset Value: FFH 1 P1 rw 0 P0 rw Field Bits Type Description rw Pull-Up/Pull-Down Enable at Port 1 Bit n 0 Pull-up or Pull-down device is disabled. 1 Pull-up or Pull-down device is enabled (default). Reserved Returns 0 if read; should be written with 0. Pn n (n = 0 – 1, 5 – 7) 0 [4:2] r P1_ALTSELn (n = 0 – 1) Port 1 Alternate Select Register 7 P7 rw 6 P6 rw 5 P5 rw 4 3 0 r 2 Reset Value: 00H 1 P1 rw 0 P0 rw Table 6-8 0 1 0 1 Function of Bits P1_ALTSEL0.Pn and P1_ALTSEL1.Pn P1_ALTSEL1.Pn 0 0 1 1 Function Normal GPIO Alternate Output 1 Alternate Output 2 Reserved P1_ALTSEL0.Pn User’s Manual Parallel Ports, V 0.3 6-23 V 0.2, 2005-01 XC866 Parallel Ports 6.5 Port 2 Port P2 is an 8-bit general purpose input-only port. The registers of P2 are summarized in Table 6-9. Table 6-9 P2_DATA P2_PUDSEL P2_PUDEN Port 2 Registers Port 2 Data Register Port 2 Pull-Up/Pull-Down Select Register Port 2 Pull-Up/Pull-Down Enable Register Register Short Name Register Full Name 6.5.1 Table 6-10 Port Pin P2.0 Functions Port 2 Input Functions Input/Output Select Input GPI ALT 1 ALT 2 ALT 3 ALT 4 ANALOG Connected Signal(s) P2_DATA.P0 CCPOS0_0 EXINT1 T12HR_2 TCK_1 AN0 P2_DATA.P1 CCPOS1_0 EXINT2 T13HR_2 TDI_1 AN1 P2_DATA.P2 CCPOS2_0 – CTRAP_1 – AN2 From/to Module – CCU6 External interrupt 1 CCU6 JTAG ADC – CCU6 External interrupt 2 CCU6 JTAG ADC – CCU6 – CCU6 – ADC P2.1 Input GPI ALT 1 ALT 2 ALT 3 ALT 4 ANALOG P2.2 Input GPI ALT 1 ALT 2 ALT 3 ALT 4 ANALOG User’s Manual Parallel Ports, V 0.3 6-24 V 0.2, 2005-01 XC866 Parallel Ports Table 6-10 Port Pin P2.3 Port 2 Input Functions (cont’d) Input/Output Select Input GPI ALT 1 ALT 2 ALT 3 ANALOG P2.4 Input GPI ALT 1 ALT 2 ALT 3 ANALOG P2.5 Input GPI ALT 1 ALT 2 ALT 3 ANALOG P2.6 Input GPI ALT 1 ALT 2 ALT 3 ANALOG P2.7 Input GPI ALT 1 ALT 2 ALT 3 ANALOG Connected Signal(s) P2_DATA.P3 – – – AN3 P2_DATA.P4 – – – AN4 P2_DATA.P5 – – – AN5 P2_DATA.P6 – – – AN6 P2_DATA.P7 – – – AN7 From/to Module – – – – ADC – – – – ADC – – – – ADC – – – – ADC – – – – ADC User’s Manual Parallel Ports, V 0.3 6-25 V 0.2, 2005-01 XC866 Parallel Ports 6.5.2 Register Description P2_DATA Port 2 Data Register 7 P7 r 6 P6 r 5 P5 r 4 P4 r 3 P3 r 2 P2 r Reset Value: 00H 1 P1 r 0 P0 r Field Pn (n = 0 – 7) Bits n Type r Description Port 2 Pin n Data Value 0 Port 2 pin n data value = 0 (default) 1 Port 2 pin n data value = 1 P2_PUDSEL Port 2 Pull-Up/Pull-Down Select Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: FFH 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Pull-Up/Pull-Down Select Port 2 Bit n 0 Pull-down device is selected. 1 Pull-up device is selected. User’s Manual Parallel Ports, V 0.3 6-26 V 0.2, 2005-01 XC866 Parallel Ports P2_PUDEN Port 2 Pull-Up/Pull-Down Enable Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Pull-Up/Pull-Down Enable at Port 2 Bit n 0 Pull-up or Pull-down device is disabled (default). 1 Pull-up or Pull-down device is enabled. User’s Manual Parallel Ports, V 0.3 6-27 V 0.2, 2005-01 XC866 Parallel Ports 6.6 Port 3 Port P3 is an 8-bit general purpose bidirectional port. The registers of P3 are summarized in Table 6-11. Table 6-11 P3_DATA P3_DIR P3_OD P3_PUDSEL P3_PUDEN P3_ALTSEL0 P3_ALTSEL1 Port 3 Registers Port 3 Data Register Port 3 Direction Register Port 3 Open Drain Control Register Port 3 Pull-Up/Pull-Down Select Register Port 3 Pull-Up/Pull-Down Enable Register Port 3 Alternate Select Register 0 Port 3 Alternate Select Register 1 Register Short Name Register Full Name 6.6.1 Table 6-12 Port Pin P3.0 Functions Port 3 Input/Output Functions Input/Output Select Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 Connected Signal(s) P3_DATA.P0 CC60_0 – – P3_DATA.P0 CC60_0 – P3_DATA.P1 – – – P3_DATA.P1 COUT60_0 – From/to Module – CCU6 – – – CCU6 – – – – – – CCU6 – P3.1 Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 User’s Manual Parallel Ports, V 0.3 6-28 V 0.2, 2005-01 XC866 Parallel Ports Table 6-12 Port Pin P3.2 Port 3 Input/Output Functions (cont’d) Input/Output Select Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 P3.3 Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 P3.4 Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 P3.5 Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 Connected Signal(s) P3_DATA.P2 CC61_0 – – P3_DATA.P3 CC61_0 – P3_DATA.P3 – – – P3_DATA.P3 COUT61_0 – P3_DATA.P4 CC62_0 – – P3_DATA.P4 CC62_0 – P3_DATA.P5 – – – P3_DATA.P5 COUT62_0 – From/to Module – CCU6 – – – CCU6 – – – – – – CCU6 – – CCU6 – – – CCU6 – – – – – – CCU6 – User’s Manual Parallel Ports, V 0.3 6-29 V 0.2, 2005-01 XC866 Parallel Ports Table 6-12 Port Pin P3.6 Port 3 Input/Output Functions (cont’d) Input/Output Select Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 P3.7 Input GPI ALT 1 ALT 2 ALT 3 Output GPO ALT1 ALT2 Connected Signal(s) P3_DATA.P6 CTRAP_0 – – P3_DATA.P6 – RSTOUT P3_DATA.P7 – EXINT4 – P3_DATA.P7 COUT63 – From/to Module – CCU6 – – – – Internal reset – – External interrupt 4 – – CCU6 – User’s Manual Parallel Ports, V 0.3 6-30 V 0.2, 2005-01 XC866 Parallel Ports 6.6.2 Register Description P3_DATA Port 3 Data Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type rw Description Port 3 Pin n Data Value 0 Port 3 pin n data value = 0 (default) 1 Port 3 pin n data value = 1 P3_DIR Port 3 Direction Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Port 3 Pin n Direction Control 0 Direction is set to input (default). 1 Direction is set to output. User’s Manual Parallel Ports, V 0.3 6-31 V 0.2, 2005-01 XC866 Parallel Ports P3_OD Port 3 Open Drain Control Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Port 3 Pin n Open Drain Mode 0 Normal mode; output is actively driven for 0 and 1 state (default) 1 Open drain mode; output is actively driven only for 0 state P3_PUDSEL Port 3 Pull-Up/Pull-Down Select Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: BFH 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Pull-Up/Pull-Down Select Port 3 Bit n 0 Pull-down device is selected. 1 Pull-up device is selected. User’s Manual Parallel Ports, V 0.3 6-32 V 0.2, 2005-01 XC866 Parallel Ports P3_PUDEN Port 3 Pull-Up/Pull-Down Enable Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 40H 1 P1 rw 0 P0 rw Field Pn (n = 0 – 7) Bits n Type Description rw Pull-Up/Pull-Down Enable at Port 3 Bit n 0 Pull-up or Pull-down device is disabled. 1 Pull-up or Pull-down device is enabled. P3_ALTSELn (n = 0 – 1) Port 3 Alternate Select Register 7 P7 rw 6 P6 rw 5 P5 rw 4 P4 rw 3 P3 rw 2 P2 rw Reset Value: 00H 1 P1 rw 0 P0 rw Table 6-13 0 1 0 1 Function of Bits P3_ALTSEL0.Pn and P3_ALTSEL1.Pn P3_ALTSEL1.Pn 0 0 1 1 Function Normal GPIO Alternate Output 1 Alternate Output 2 Reserved P3_ALTSEL0.Pn User’s Manual Parallel Ports, V 0.3 6-33 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management 7 Power Supply, Reset and Clock Management The XC866 provides a range of utility features for secure system performance under critical conditions (e.g., brownout). The power supply to the core, memories and the peripherals is regulated by the Embedded Voltage Regulator (EVR), with detection circuitries to ensure that the supplied voltages are within the specified operating range. The main voltage and low power voltage regulators in the EVR may be independently switched off to reduce power consumption for the different power saving modes. At the center of the XC866 clock system is the Clock Generation Unit (CGU), which generates a master clock frequency using the Phase-Locked Loop (PLL) and oscillator units. In-phase synchronized clock signals are derived from the master clock and distributed throughout the system. A programmable clock divider is available for scaling the master clock into lower frequencies for power savings. 7.1 Power Supply System with Embedded Voltage Regulator The XC866 microcontroller requires two different levels of power supply: • 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports • 2.5 V for the core, memory, on-chip oscillator, and peripherals Figure 7-1 shows the XC866 power supply system. A power supply of 3.3 V or 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps reduce the power consumption of the whole chip and the complexity of the application board design. CPU & Memory On-chip OSC Peripheral logic ADC VDD (2.5V) FLASH PLL GPIO Ports (P0-P3) XTAL1& XTAL2 EVR VDDP (3.3V/5.0V) VSSP Figure 7-1 XC866 Power Supply System 7-1 V 0.2, 2005-01 User’s Manual Power, Reset and Clock, V 0.4 XC866 Power Supply, Reset and Clock Management EVR Features: • • • • • Input voltage (VDDP): 3.3 V/5.0 V Output voltage (VDD): 2.5 V +/-7.5% Low power voltage regulator provided in power-down mode VDD and VDDP prewarning detection VDD brownout detection The EVR consists of a main voltage regulator and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption. The EVR has the VDD and VDDP detectors. There are two threshold voltage levels for VDD detection: prewarning (2.3 V) and brownout (2.1 V). When VDD is below 2.3 V, the VDD NMI flag NMISR.FNMIVDD is set and an NMI request to the CPU is activated if VDD NMI is enabled (NMICON.NMIVDD). If VDD is below 2.1 V, the brownout reset will be activated, putting the microcontroller into a reset state. For VDDP, there is only one prewarning threshold of 4.0 V if the external power supply is 5.0 V. When VDDP is below 4.0 V, the VDDP NMI flag NMISR.FNMIVDDP is set and an NMI request to the CPU is activated if VDDP NMI is enabled (NMICON.NMIVDDP). If an external power supply of 3.3 V is used, the user must disable VDDP detector by clearing bit NMICON.NMIVDDP. In power-down mode, the VDD detector is switched off and VDDP detector will continue to function. The EVR also has a power-on reset (POR) detector for VDD to ensure correct power up. The voltage level detection of POR is 1.6 V. The monitoring function is used in both active mode and power-down mode. During power up, after VDD exceeds 1.6 V, the reset of EVR is extended by a delay that is typically 300 µs. In active mode, VDD is monitored mainly by the VDD detector, and a reset is generated when VDD drops below 2.1 V. In power-down mode, the VDD is monitored by the POR and a reset is generated when VDD drops below 1.6 V. User’s Manual Power, Reset and Clock, V 0.4 7-2 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management 7.2 Reset Control The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC866 is first powered up, the status of certain pins (see Table 7-2) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device. The hardware reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode. A brownout reset is triggered if the VDD supply voltage dips below 2.1 V. 7.2.1 7.2.1.1 Types of Reset Power-On Reset The supply voltage VDDP is used to power up the chip. The EVR is the first module in the chip to be reset, which includes: 1. Startup of the main voltage regulator and the low power voltage regulator. 2. When VDDP and VDD reach the threshold of the VDDP and VDD detectors, the reset of EVR becomes inactive. When the system starts up, the PLL is disconnected from the oscillator and will run at its base frequency. Once the EVR is stable, provided the oscillator is running, the PLL is connected and the continuous lock detection ensures that PLL starts functioning. Following this, as soon as the system clock is stable, each 4-Kbyte Flash bank will enter the ready-to-read mode. The status of pins MBC, TMS and P0.0 is latched by the reset. The latched values are used to select the boot options (see Section 7.2.3). A correctly executed reset leaves the system in a defined state. The program execution starts from location 0000H. Figure 7-2 shows the power-on reset sequence. User’s Manual Power, Reset and Clock, V 0.4 7-3 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management EVR is stable Typ. 300 µs Figure 7-2 Power-on Reset PLL is locked Max. 200 µs Reset is FLASH go to released and Ready-to-Read start of program Mode Typ. 160 µs 7.2.1.2 Hardware Reset An external hardware reset sequence is started when the reset input pin RESET is asserted low. The RESET pin must be held low for at least 1ms. After the RESET pin is deasserted, the reset sequence is the same as the power-on reset sequence, as shown in Figure 7-2. A hardware reset through RESET pin will terminate the idle mode or the power-down mode. The status of pins MBC, TMS and P0.0 is latched by the reset. The latched value is used to select the boot options (see Section 7.2.3). 7.2.1.3 Watchdog Timer Reset The watchdog timer reset is an internal reset. The Watchdog Timer (WDT) maintains a counter that must be refreshed or cleared periodically. If the WDT is not serviced correctly and in time, it will generate an NMI request to the CPU and then reset the device after a predefined time-out period. Bit PMCON0.WDTRST is used to indicate the watchdog timer reset status. For watchdog timer reset, as the EVR is already stable and PLL lock detection is not needed, the timing for watchdog timer reset is approximately 200 µs, which is shorter as compared to the other types of reset. 7.2.1.4 Power-Down Wake-Up Reset Power is still applied to the XC866 during power-down mode, as the low power voltage regulator is still operating. If power-down mode is entered appropriately, all important system state will have been preserved in the Flash by software. If the XC866 is in power-down mode, three options are available to awaken it: • through RXD • through EXINT0 • through RXD or EXINT0 User’s Manual Power, Reset and Clock, V 0.4 7-4 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management Selection of these options is made via the control bit PMCON0.WS. The wake-up from power-down can be with reset or without reset; this is chosen by the PMCON0.WKSET bit. The wake-up status (with or without reset) is indicated by the PMCON0.WKRS bit. Figure 7-3 shows the power-down wake-up reset sequence. The EVR takes approximately 150 µs to become stable, which is a shorter time period as compared to the power-on reset. EVR is stable Typ. 150 µs Figure 7-3 PLL is locked Max. 200 µs Reset is FLASH go to released and Ready-to-Read start of program Mode Typ. 160 µs Power-down Wake-up Reset In addition to the above-mentioned three options, the power-down mode can also be exited by the hardware reset through RESET pin. 7.2.1.5 Brownout Reset In active mode, the VDD detector in EVR detects brownout when the core supply voltage VDD dips below the threshold voltage VDD_TH (2.1 V). The brownout will cause the device to be reset. In power-down mode, the VDD is monitored by the POR in EVR and a reset is generated when VDD drops below 1.6 V. Once the brownout reset takes place, the reset sequence is the same as the power-on reset sequence, as shown in Figure 7-2. User’s Manual Power, Reset and Clock, V 0.4 7-5 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management 7.2.2 Module Reset Behavior Table 7-1 shows how the functions of the XC866 are affected by the various reset types. A “ ” means that this function is reset to its default state. Table 7-1 Module/ Function CPU Core Peripherals On-Chip Static RAM Oscillator, PLL Port Pins EVR Not affected, Not affected, Not affected, Affected, un- Affected, unreliable reliable reliable reliable reliable Not affected See Chapter 6, “Parallel Ports” The voltage Not affected regulator is switched on Disabled Disabled Effect of Reset on Device Functions Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset FLASH NMI 7.2.3 Booting Scheme When the XC866 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectively select the different boot options. Table 7-2 shows the available boot options in the XC866. Table 7-2 MBC 1 0 0 TMS x 0 1 XC866 Boot Selections P0.0 x x 0 Type of Mode User Mode; OSC/PLL non-bypassed BSL Mode; OSC/PLL non-bypassed OCDS Mode; OSC/PLL non-bypassed PC Start Value 0000H 0000H 0000H User’s Manual Power, Reset and Clock, V 0.4 7-6 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management 7.2.4 Register Description Reset Value: See Table 7-3 4 WKSEL rw 3 SD rw 2 PD rwh 1 WS rw 0 PMCON0 Power Mode Control Register 0 7 0 r 6 WDTRST rwh 5 WKRS rwh The functions of the shaded bits are not described here Field WS Bits [1:0] Type Description rw Wake-Up Source Select 00 No wake-up is selected. 01 Wake-up source RXD is selected. 10 Wake-up source EXINT0 is selected. 11 Wake-up source RXD or EXINT0 is selected. Wake-Up Reset Select Bit 0 Wake-up without reset 1 Wake-up with reset Wake-Up Indication Bit 0 No wake-up occurred. 1 Wake-up has occurred. This bit can only be set by hardware and reset by software. Watchdog Timer Reset Indication Bit 0 No watchdog timer reset occurred. 1 Watchdog timer reset has occurred. This bit can only be set by hardware and reset by software. Reserved Returns 0 if read; should be written with 0. WKSEL 4 rw WKRS 5 rwh WDTRST 6 rwh 0 7 r User’s Manual Power, Reset and Clock, V 0.4 7-7 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management Table 7-3 Reset Values of Register PMCON0 Reset Value 0000 0000B 0100 0000B 0010 0000B Reset Source Power-on Reset/Hardware Reset/Brownout Reset Watchdog Timer Reset Power-down Wake-up Reset User’s Manual Power, Reset and Clock, V 0.4 7-8 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management 7.3 Clock System The XC866 clock system performs the following functions: • Acquires and buffers incoming clock signals to create a master clock frequency • Distributes in-phase synchronized clock signals throughout the system • Divides a system master clock frequency into lower frequencies for power saving mode 7.3.1 Clock Generation Unit The Clock Generation Unit (CGU) in the XC866 consists of an oscillator circuit and a Phase-Locked Loop (PLL). In the XC866, the oscillator can be from either of these two sources: the on-chip oscillator (10 MHz) or the external oscillator (3 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be used by default. The external oscillator can be selected via software. The PLL can convert a low-frequency external clock signal from the oscillator circuit to a high-speed internal clock for maximum performance. Figure 7-4 shows the block diagram of CGU. osc fail detect lock detect OSC OSCR LOCK fosc P:1 fp fn PLL core fvco K:1 fsys N:1 PLLBYP OSCDISC NDIV VCOBYP Figure 7-4 CGU Block Diagram User’s Manual Power, Reset and Clock, V 0.4 7-9 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management 7.3.1.1 Functional Description When the XC866 is powered up, the PLL is disconnected from the oscillator and will run at its VCO base frequency. After the EVR is stable, provided the oscillator is running, the PLL will be connected and the continuous lock detection will ensure that the PLL starts functioning. Once reset has been released, bit OSCR will be set to 1 if the oscillator is running and bit LOCK will be set to 1 if the PLL is locked. Loss-of-Lock Operation If the PLL is not the system’s clock source (VCOBYP = 1) when the loss of lock is detected, only the lock flag is reset (PLL_CON.LOCK = 0) and no further action is taken. This allows the PLL parameters to be switched dynamically. If PLL loses its lock to the oscillator, the PLL Loss-of-Lock NMI flag NMISR.FNMIPLL is set and an NMI request to the CPU is activated if PLL NMI is enabled (NMICON.NMIPLL). In addition, the LOCK flag in PLL_CON is reset. PLL VCO gradually slows down to its base frequency. Emergency routines can be executed with the XC866 clocked with this base frequency. The XC866 remains in this loss-of-lock state until the next power-on reset, hardware reset or after a successful lock recovery has been performed. Loss-of-Lock Recovery If PLL has lost its lock to the oscillator, the PLL can be re-locked by software. The following sequence must be performed: 1. Disconnect the oscillator from the PLL (OSCDISC = 1). 2. Set the N-divider of the PLL to the value 16 (PLL_CON.NDIV = 0010B). 3. Wait for 50 µs until the oscillator is stable. 4. Restart the Oscillator Run Detection by setting bit OSC_CON.ORDRES. If bit OSC_CON.OSCR is set, then: 1. Select the VCO bypass mode (VCOBYP = 1). 2. Reconnect oscillator to the PLL (OSCDISC = 0). 3. Reprogram the NDIV factor to the original value. 4. The RESLD bit must be set and the LOCK flag checked. Only if the LOCK flag is set again can the VCO bypass mode be deselected and normal operation resumed. If neither OSCR nor LOCK is set, emergency measures must be executed. Emergency measures such as a system shut down can be carried out by the user. User’s Manual Power, Reset and Clock, V 0.4 7-10 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management Changing PLL Parameters To change the PLL parameters, (OSC_CON.OSCR = 1). In this case: first check if the oscillator is running 1. Select VCO bypass mode (VCOBYP = 1). 2. Connect oscillator to PLL (OSCDISC = 0). 3. Program desired NDIV value. 4. Wait till the LOCK bit has been set. 5. Disable VCO bypass mode. Select the External Oscillator To select the external oscillator, the following sequence must be performed: 1. Select the VCO bypass mode (VCOBYP = 1). 2. Disconnect the oscillator from the PLL (OSCDISC = 1). 3. External OSC is powered up by resetting bit XPD. 4. The source of external oscillator is selected by setting bit OSCSS. 5. Wait for 50 µs until the external oscillator is stable. 6. Restart the Oscillator Run Detection by setting bit OSC_CON.ORDRES. If bit OSC_CON.OSCR is set, then: 1. Select the VCO bypass mode (VCOBYP = 1). 2. Reconnect oscillator to the PLL (OSCDISC = 0). 3. Reprogram the NDIV factor to the required value. 4. The RESLD bit must be set and the LOCK flag checked. Only if the LOCK flag is set again, can the VCO bypass mode be deselected and normal operation resumed. In order to minimize power consumption while the on-chip oscillator is used, XTAL is powered down by setting bit XPD, but when the external oscillator is used, the on-chip oscillator cannot be powered down by setting bit OSCPD. 7.3.2 Clock Source Control The clock system provides four ways to generate CPU clock: Direct Drive (PLL Bypass Operation) In PLL bypass operation, the system clock has exactly the same frequency as the external clock source. The PLL bypass is set inactive in the XC866. f SYS = f OSC User’s Manual Power, Reset and Clock, V 0.4 7-11 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management PLL Base Mode The system clock is derived from the VCO base frequency clock divided by the K factor. Both VCO bypass and PLL bypass must be inactive for this PLL mode. 1 f SYS = f VCObase × --K Prescaler Mode (VCO Bypass Operation) In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors. 1 f SYS = f OSC × ------------P×K PLL Mode The system clock is derived from the oscillator clock, divided by the P factor, multiplied by the N factor, and divided by the K factor. Both VCO bypass and PLL bypass must be inactive for this PLL mode. N f SYS = f OSC × ------------P×K In normal running mode, the system works in the PLL mode. For different source oscillator, the selection of typical output frequency fsys = 80 MHz is shown in Table 7-4. Table 7-4 Oscillator On-chip External System frequency (fsys = 80 MHz) fosc 10 MHz 10 MHz 8 MHz 5 MHz N 16 16 20 32 P 1 1 1 1 K 2 2 2 2 fsys 80 MHz 80 MHz 80 MHz 80 MHz For the XC866, the values of P and K are fixed to “1” and “2”, respectively. In order to obtain the required fsys, the value of N can be selected by bit NDIV for different oscillator inputs. See Table 7-4. The output frequency needs to be within the range 75 MHz to 80 MHz. User’s Manual Power, Reset and Clock, V 0.4 7-12 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management Table 7-5 shows the VCO range in the XC866. Table 7-5 fVCOmin 150 VCO Ranges fVCOmax 200 fVCOFREEmin 40 fVCOFREEmax 130 Unit MHz 7.3.3 Clock Management The Clock Management sub-module generates all clock signals required within the microcontroller from the basic clock. It consists of: • Basic clock slow down circuitry • Centralized enable/disable circuit for clock control Figure 7-5 shows the clock generation from the system frequency fsys. In normal running mode, the typical frequencies of different modules are as follows: • • • • CPU clock: CCLK, SCLK = 26.7 MHz CCU6 clock: FCLK = 26.7 MHz Other peripherals: PCLK = 26.7 MHz Flash Interface clock: CCLK3 = 80 MHz and CCLK = 26.7 MHz Furthermore, the oscillator clock outputs to pin CLKOUT(P0.0). In idle mode, only the CPU clock CCLK is disabled. In power-down mode, CCLK, SCLK, FCLK, CCLK3 and PCLK are all disabled. If slow-down mode is enabled, the clock to the core and peripherals will be divided by a programmable factor that is selected by the bit field CMCON.CLKREL. CLKREL FCLK CCU6 Peripherals CORE OSC fosc PLL fsys=80MHz /3 PCLK SCLK CCLK CLKOUT N,P,K CCLK3 FLASH Interface Figure 7-5 Clock Generation from fsys User’s Manual Power, Reset and Clock, V 0.4 7-13 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management 7.3.4 Register Description Reset Value: 0000 1000B 5 4 OSCPD rw 3 XPD rw 2 OSCSS rw 1 ORDRES rwh 0 OSCR rh OSC_CON OSC Control Register 7 6 0 r Field OSCR Bits 0 Type Description rh Oscillator Run Status Bit This bit shows the state of the oscillator run detection. 0 The oscillator is not running. 1 The oscillator is running. Oscillator Run Detection Reset 0 No operation 1 The oscillator run detection logic is reset and restarted. This bit will automatically be reset to 0. Oscillator Source Select 0 On-chip oscillator is selected. 1 External oscillator is selected. XTAL Power-down Control 0 XTAL is not powered down. 1 XTAL is powered down. On-chip OSC Power-down Control 0 The on-chip oscillator is not powered down. 1 The on-chip oscillator is powered down. Reserved Returns 0 if read; should be written with 0. ORDRES 1 rwh OSCSS 2 rw XPD 3 rw OSCPD 4 rw 0 [7:5] r Note: The reset value of register OSC_CON is 0000 1000B. One clock cycle after reset, bit OSCR will be set to 1 if the oscillator is running, then the value 0000 1001B will be observed. User’s Manual Power, Reset and Clock, V 0.4 7-14 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management PLL_CON PLL Control Register 7 6 NDIV rw 5 4 3 VCOBYP rw 2 Reset Value: 0010 0000B 1 RESLD rwh 0 LOCK rh OSCDISC rw Field LOCK Bits 0 Type Description rh PLL Lock Status Flag 0 PLL is not locked. 1 PLL is locked. Restart Lock Detection Setting this bit will reset the PLL lock status flag and restart the lock detection. This bit will automatically be reset to 0 and thus always be read back as 0. 0 No effect 1 Reset lock flag and restart lock detection Oscillator Disconnect 0 Oscillator is connected to the PLL. 1 Oscillator is disconnected from the PLL. PLL VCO Bypass Mode Select 0 Normal operation (default) 1 VCO bypass mode (PLL output clock is derived from input clock divided by P- and K-dividers). RESLD 1 rwh OSCDISC 2 rw VCOBYP 3 rw User’s Manual Power, Reset and Clock, V 0.4 7-15 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management Field NDIV Bits [7:4] Type Description rw PLL N-Divider 0000B N = 14 0001B N = 15 0010B N = 16 0011B N = 17 0100B N = 18 0101B N = 19 0110B N = 20 0111B N = 21 1000B N = 24 1001B N = 28 1010B N = 30 1011B N = 32 1100B N = 40 1101B N = 42 1110B N = 45 1111B N = 50 The NDIV bit is a protected bit. When the Protection Scheme (see Chapter 3.3.4.1) is activated, this bit cannot be written directly. Note: The reset value of register PLL_CON is 0010 0000B. One clock cycle after reset, bit LOCK will be set to 1 if the PLL is locked, then the value 0010 0001B will be observed. User’s Manual Power, Reset and Clock, V 0.4 7-16 V 0.2, 2005-01 XC866 Power Supply, Reset and Clock Management CMCON Clock Control Register 7 6 0 r 5 4 3 2 Reset Value: 00H 1 CLKREL rw 0 Field CLKREL Bits [3:0] Type Description rw Clock Divider 0000B fsys/1 0001B fsys/2 0010B fsys/4 0011B fsys/8 0100B fsys/16 0101B fsys/32 0110B fsys/64 0111B fsys/128 1000B fsys/256 1001B fsys/512 1010B fsys/1024 1011B fsys/2048 1100B Reserved 1101B Reserved 1110B Reserved 1111B Reserved Reserved Returns 0 if read; should be written with 0. 0 [7:4] r Note: Registers OSC_CON, PLL_CON and CMCON are not reset during the watchdog timer reset. User’s Manual Power, Reset and Clock, V 0.4 7-17 V 0.2, 2005-01 XC866 Power Saving Modes 8 Power Saving Modes The power saving modes in the XC866 provide flexible power consumption through a combination of techniques, including: • • • • Stopping the CPU clock Stopping the clocks of individual system components Reducing clock speed of some peripheral components Power-down of the entire system with fast restart capability After a reset, the active mode (normal operating mode) is selected by default (see Figure 8-1) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are: • Idle mode • Slow-down mode • Power-down mode any interrupt & SD=0 set IDLE bit ACTIVE EXINT0/RXD pin & SD=0 set PD bit IDLE set SD bit clear SD bit POWER-DOWN set IDLE bit any interrupt & SD=1 SLOW-DOWN set PD bit EXINT0/RXD pin & SD=1 Figure 8-1 Transition between Power Saving Modes User’s Manual SCU, V 0.4 8-1 V 0.2, 2005-01 XC866 Power Saving Modes 8.1 Functional Description This section describes the various power saving modes, their operations, and how they are entered and exited. 8.1.1 Idle Mode The idle mode is used to reduce power consumption by stopping the core’s clock. In idle mode, the oscillator continues to run, but the core is stopped with its clock disabled. Peripherals whose input clocks are not disabled are still functional. The user should disable the Watchdog Timer (WDT) before the system enters the idle mode; otherwise, it will generate an internal reset when an overflow occurs and thus will disrupt the idle mode. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The port pins hold the logical state they had at the time the idle mode was activated. Software requests idle mode by setting the bit PCON.IDLE to 1. The system will return to active mode on occurrence of any of the following conditions: • The idle mode can be terminated by activating any enabled interrupt. The CPU operation is resumed and the interrupt will be serviced. Upon RETI instruction, the core will return to execute the next instruction after the instruction which sets the IDLE bit to 1. • An external hard reset signal (RESET) is asserted. 8.1.2 Slow-Down Mode The slow-down mode is used to reduce power consumption by decreasing the internal clock in the device. The slow-down mode is activated by setting the bit SD in SFR PMCON0. The bit field CMCON.CLKREL is used to select different slow-down frequency. The CPU and peripherals are clocked at this lower frequency. The slow-down mode is terminated by clearing bit SD. The slow-down mode can be combined with the idle mode by performing the following sequence: 1. The slow-down mode is activated by setting the bit PMCON0.SD. 2. The idle mode is activated by setting the bit PCON.IDLE. There are two ways to terminate the combined idle and slow-down modes: • The idle mode can be terminated by activation of any enabled interrupt. CPU operation is resumed, and the interrupt will be serviced. The next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLE. Nevertheless, the slow-down mode stays enabled and if required User’s Manual SCU, V 0.4 8-2 V 0.2, 2005-01 XC866 Power Saving Modes termination must be done by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the slow-down mode. • The other way of terminating the combined idle and slow-down mode is through a hardware reset. 8.1.3 Power-down Mode In power-down mode, the oscillator and the PLL are turned off. The FLASH is put into the power-down mode. The main voltage regulator is switched off, but the low power voltage regulator continues to operate. Therefore, all functions of the microcontroller are stopped and only the contents of the FLASH, on-chip RAM, XRAM and the SFRs are maintained. The port pins hold the logical state they had when the power-down mode was activated. For the digital ports, the user must take care from external side that the ports are not floating in power-down mode. This can be done with external pull-up/pulldown or putting the port to output. In power-down mode, the clock is turned off. Hence, it cannot be awakened by an interrupt or by the WDT. It will be awakened only when it receives an external wake-up signal or reset signal. Entering Power-down Mode Software requests power-down mode by setting the bit PMCON0.PD to 1. If the external wake-up from power-down is used, software must prepare the external environment of the XC866 to trigger one of these signals under the appropriate conditions before entering power-down mode. A wake-up circuit is used to detect a wake-up signal and activate the power-up. During power-down, this circuit remains active. It does not depend on any clocks. Exit from power-down mode can be achieved by applying a falling edge trigger into the: • EXINT0 pin • RXD pin • RXD pin or EXINT0 pin The wake-up source can be selected by the WS bit of the PMCON0 register. The wake-up with reset or without reset is selected by bit PMCON0.WKSET. The wake-up source and wake-up type must be selected before the system enters the power-down mode. Exiting Power-down Mode If power-down mode is exited via a hardware reset, the device is put into the hardware reset state. When the wake-up source and wake-up type have been selected prior to entering power-down mode, the power-down mode can be exited via EXINT0 pin/RXD pin. User’s Manual SCU, V 0.4 8-3 V 0.2, 2005-01 XC866 Power Saving Modes Bit MODPISEL.URRIS is used to select one of the two RXD inputs and bit MODPISEL.EXINT0IS is used to select one of the two EXINT0 inputs. If bit WKSEL was set to 1 before entering power-down mode, the system will execute a reset sequence similar to the power-on reset sequence. Therefore, all port pins are put into their reset state and will remain in this state until they are affected by program execution. If bit WKSEL was cleared to 0 before entering power-down mode, a fast wake-up sequence is used. The port pins continue to hold their state which was valid during power-down mode until they are affected by program execution. The wake-up from power-down without reset uses the following procedures: 1. In power-down mode, EXINT0 pin/RXD pin must be held at high level. 2. Power-down mode is exited when EXINT0 pin/RXD pin goes low for at least 100 ns. 3. The main voltage regulator is switched on and takes approximately 150 µs to become stable. 4. The on-chip oscillator and the PLL are started. Typically, the on-chip oscillator takes approximately 500 ns to stabilize. The PLL will be locked within 200 µs after the onchip oscillator clock is detected for stable nominal frequency. 5. Subsequently, the FLASH will enter ready-to-read mode. This does not require the typical 160 µs as is the case for the normal reset. The timing for this part can be ignored. 6. The CPU operation is resumed. If wake-up source is EXINT0 pin, the interrupt will be serviced if EXINT0 is enabled before entering power-down mode. Upon RETI instruction, the core will return to execute the next instruction after the instruction which sets the PD bit. If wake-up source is RXD pin, the core will return to execute the next instruction after the instruction which sets the PD bit. 8.1.4 Peripheral Clock Management The degree of reduction in power consumption that can be achieved by this feature depends on the number of peripherals running. Peripherals that are not required for a particular functionality can be disabled by gating off the clock inputs. For example, in idle mode, if all timers are stopped, and ADC, CCU6 and the serial interfaces are not running, maximum power reduction can be achieved. However, the user must take care in determining which peripherals should continue running and which must be stopped during active and idle modes. The ADC, SSC, CCU6 and Timer 2 can be disabled (clock is gated off) by setting the corresponding bit in the PMCON1 register. Furthermore, the analog part of the ADC module may be disabled by resetting the GLOBCTR.ANON bit. This feature causes the generation of fADCI to be stopped and allows a reduction in power consumption when no conversion is needed. User’s Manual SCU, V 0.4 8-4 V 0.2, 2005-01 XC866 Power Saving Modes In order to save power consumption when the on-chip oscillator is used, XTAL should be powered down by setting bit OSC_CON.XPD. However, when the external oscillator is used, the on-chip oscillator cannot be powered down by setting bit OSC_CON.OSCPD. User’s Manual SCU, V 0.4 8-5 V 0.2, 2005-01 XC866 Power Saving Modes 8.2 Register Description Reset Value: See Table 8-1 4 WKSEL rw 3 SD rw 2 PD rwh 1 WS rw 0 PMCON0 Power Mode Control Register 0 7 0 r 6 WDTRST rwh 5 WKRS rwh The functions of the shaded bits are not described here Field WS Bits [1:0] Type Description rw Wake-up Source Select 00 No wake-up is selected. 01 Wake-up source RXD is selected. 10 Wake-up source EXINT0 is selected. 11 Wake-up source RXD or EXINT0 is selected. Power-down Enable. Active High. Setting this bit will cause the chip to enter power-down mode. It is reset by wake-up circuit. The PD bit is a protected bit. When the Protection Scheme (see Chapter 3.3.4.1) is activated, this bit cannot be written directly. Slow-down Enable. Active High. Setting this bit will cause the chip to enter slow-down mode. It is reset by the user. The SD bit is a protected bit. When the Protection Scheme is activated, this bit cannot be written directly. Wake-up Reset Select Bit 0 Wake-up without reset 1 Wake-up with reset Wake-up Indication Bit 0 No wake-up occurred. 1 Wake-up has occurred. This bit can only be set by hardware and reset by software. PD 2 rwh SD 3 rw WKSEL 4 rw WKRS 5 rwh User’s Manual SCU, V 0.4 8-6 V 0.2, 2005-01 XC866 Power Saving Modes Field 0 Bits 7 Type Description r Reserved Returns 0 if read; should be written with 0. Table 8-1 Reset Values of Register PMCON0 Reset Values 0100 0000B 0010 0000B Reset Source Watchdog Timer Reset Power-down Wake-up Reset Power-on Reset/Hardware Reset/Brownout Reset 0000 0000B PCON Power Control Register 7 SMOD rw 6 5 0 r 4 3 GF1 rw 2 GF0 rw Reset Value: 00H 1 0 r 0 IDLE rw The functions of the shaded bits are not described here Field IDLE Bits 0 Type Description rw Idle Mode Enable 0 Do not enter idle mode 1 Enter idle mode User’s Manual SCU, V 0.4 8-7 V 0.2, 2005-01 XC866 Power Saving Modes MODPISEL Peripheral Input Select Register 7 0 r 6 5 4 3 0 r 2 Reset Value: 00H 1 EXINT0IS rw 0 URRIS rw JTAGTDIS JTAGTCK S rw rw The functions of the shaded bits are not described here Field URRIS Bits 0 Type Description rw UART Receive Input Select 0 UART Receiver Input RXD_0 is selected. 1 UART Receiver Input RXD_1 is selected. External Interrupt 0 Input Select 0 External Interrupt Input EXINT0_0 is selected. 1 External Interrupt Input EXINT0_1 is selected. Reserved Returns 0 if read; should be written with 0. EXINT0IS 1 rw 0 [3:2], r [7:6] PMCON1 Power Mode Control Register 1 7 6 0 r 5 4 3 T2_DIS rw 2 CCU_DIS rw Reset Value: 00H 1 SSC_DIS rw 0 ADC_DIS rw Field ADC_DIS Bits 0 Type Description rw ADC Disable Request. Active high. 0 ADC is in normal operation (default). 1 ADC is disabled. SSC Disable Request. Active high. 0 SSC is in normal operation (default). 1 SSC is disabled. SSC_DIS 1 rw User’s Manual SCU, V 0.4 8-8 V 0.2, 2005-01 XC866 Power Saving Modes Field CCU_DIS Bits 2 Type Description rw CCU6 Disable Request. Active High. 0 CCU6 is in normal operation (default). 1 CCU6 is disabled. Timer 2 Disable Request. Active High. 0 Timer 2 is in normal operation (default). 1 Timer 2 is disabled. Reserved Returns 0 if read; should be written with 0. T2_DIS 3 rw 0 [7:4] r ADC_GLOBCTR Global Control Register 7 ANON rw 6 DW rw 5 CTC rw 4 3 2 0 r Reset Value: 00H 1 0 The functions of the shaded bits are not described here Field ANON Bits 7 Type Description rw Analog Part Switched On This bit enables the analog part of the ADC module and defines its operation mode. 0 The analog part is switched off and conversions are not possible. To achieve minimal power consumption, the internal analog circuitry is in its power-down state and the generation of fADCI is stopped. 1 The analog part of the ADC module is switched on and conversions are possible. The automatic power-down capability of the analog part is disabled. Reserved Returns 0 if read; should be written with 0. 0 [3:0] r User’s Manual SCU, V 0.4 8-9 V 0.2, 2005-01 XC866 Power Saving Modes OSC_CON OSC Control Register 7 6 0 r 5 4 OSCPD rw 3 XPD rw 2 Reset Value: 0000 1000B 1 ORDRES rwh 0 OSCR rh OSCSS rw The functions of the shaded bits are not described here Field XPD Bits 3 Type Description rw XTAL Power-down Control 0 XTAL is not powered down. 1 XTAL is powered down. On-chip OSC Power-down Control 0 The on-chip oscillator is not powered down. 1 The on-chip oscillator is powered down. Reserved Returns 0 if read; should be written with 0. OSCPD 4 rw 0 [7:5] r User’s Manual SCU, V 0.4 8-10 V 0.2, 2005-01 XC866 Watchdog Timer 9 Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this time interval to prevent the WDT from causing an XC866 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the XC866 will be aborted in a user-specified time period. Features: • • • • 16-bit Watchdog Timer Programmable reload value for upper 8 bits of timer Programmable window boundary Selectable input frequency of fPCLK/2 or fPCLK/128 User’s Manual Watchdog Timer, V 0.4 9-1 V 0.2, 2005-01 XC866 Watchdog Timer 9.1 Functional Description The Watchdog Timer (WDT) is a 16-bit timer, which is incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access. Figure 9-1 shows the block diagram of the WDT unit. WDT Control Clear MUX f PCLK 1:128 WDT Low Byte WDTREL 1:2 WDT High Byte Overflow/Time-out Control & Window-boundary control ENWDT Logic ENWDT_P WDTWINB WDTTO WDTRST WDTIN Figure 9-1 WDT Block Diagram If the WDT is enabled by setting bit WDTEN to 1, the timer is set to a user-defined start value and begins counting up. It must be serviced before the counter overflows. Servicing is performed through the refresh operation (setting WDTRS to 1). This reloads the timer with the start value, and normal operation continues. If the WDT is not serviced before the timer overflows, a system malfunction is assumed and normal mode is terminated. A WDT NMI request (WDTTO) is then asserted and prewarning is entered. The prewarning lasts for 30H count. During the prewarning period, refreshing of the WDT is ignored and the WDT cannot be disabled. A reset (WDTRST) of the XC866 is imminent and can no longer be stopped. The occurrence of a WDT reset is indicated by the bit WDTRST, which is set to 1 once hardware detects the assertion of the signal WDTRST. If refresh happens at the same time an overflow occurs, WDT will not go into prewarning period. The WDT must be serviced periodically so that its count value will not overflow. Servicing the WDT clears the low byte and reloads the high byte with the preset value in bit field WDTREL. Servicing the WDT also clears the bit WDTRS. The WDT has a “programmable window boundary”, which disallows any refresh during the WDT’s count-up. A refresh during this window-boundary constitutes an invalid User’s Manual Watchdog Timer, V 0.4 9-2 V 0.2, 2005-01 XC866 Watchdog Timer access to the WDT and causes the WDT to activate WDTRST, although no NMI request is generated in this instance. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. This feature can be enabled by WINBEN. After being serviced, the WDT continues counting up from the value ( * 28). The time period for an overflow of the WDT is programmable in two ways: • the input frequency to the WDT can be selected via bit WDTIN in register WDTCON to be either fPCLK/2 or fPCLK/128. • the reload value WDTREL for the high byte of WDT can be programmed in register WDTREL. The period PWDT between servicing the WDT and the next overflow can be determined by the following formula: ( 1 + WDTIN × 6 ) × ( 2 16 – WDTREL × 2 8 ) ----------------------------------------------------------------------------------------------------P WDT = 2 f PCLK If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL. See also Figure 9-2. This period can be calculated by the same formula by replacing WDTREL with WDTWINB. In order for this feature to be useful, WDTWINB cannot be smaller than WDTREL. Count FFFF H WDTWINB WDTREL time No refresh allowed Refresh allowed Figure 9-2 WDT Timing Diagram 9-3 V 0.2, 2005-01 User’s Manual Watchdog Timer, V 0.4 XC866 Watchdog Timer Table 9-1 lists the possible ranges for the watchdog time which can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 9-1 Reload value in WDTREL FFH 7FH 00H Watchdog Time Ranges Prescaler for fPCLK 2 (WDTIN = 0) 20 MHz 25.6 µs 3.3 ms 6.55 ms 16 MHz 4.13 ms 12 MHz 5.5 ms 32.0 µs 42.67 µs 8.19 ms 10.92 ms 128 (WDTIN = 1) 20 MHz 1.64 ms 211 ms 419 ms 16 MHz 2.05 ms 264 ms 524 ms 12 MHz 2.73 ms 352 ms 699 ms Note: For safety reasons, the user is advised to rewrite WDTCON each time before the WDT is serviced. User’s Manual Watchdog Timer, V 0.4 9-4 V 0.2, 2005-01 XC866 Watchdog Timer 9.2 Register Map The WDT SFRs are located in the mapped SFR area. Table 9-2 lists the addresses of these SFRs. Table 9-2 Address BBH BCH BDH BEH BFH SFR Address list Name WDTCON WDTREL WDTWINB WDTL WDTH 9.3 Register Description The current count value of the WDT is contained in the Watchdog Timer Register WDT, which is a non-bitaddressable read-only register. The operation of the WDT is controlled by its bitaddressable WDT Control Register WDTCON. This register also selects the input clock prescaling factor. The register WDTREL specifies the reload value for the high byte of the timer. WDTREL Watchdog Timer Reload Register 7 6 5 4 WDTREL rw 3 2 Reset Value: 00H 1 0 Field WDTREL Bits [7:0] Type Description rw Watchdog Timer Reload Value (for the high byte of WDT) A new reload value can be written to WDTREL and this value is loaded to the upper 8 bits of the WDT upon the enabling of the timer or the next service for refresh. User’s Manual Watchdog Timer, V 0.4 9-5 V 0.2, 2005-01 XC866 Watchdog Timer WDTCON Watchdog Timer Control Register 7 0 r 6 5 WINBEN rw 4 WDTPR rh 3 0 r 2 WDTEN rw Reset Value: 00H 1 WDTRS rwh 0 WDTIN rw Field WDTIN Bits 0 Type Description rw Watchdog Timer Input Frequency Selection 0 Input frequency is fWDT/2. 1 Input frequency is fWDT/128. WDT Refresh Start Active high. Set to start refresh operation on the WDT. Cleared automatically by hardware. WDT Enable 0 WDT is disabled. 1 WDT is enabled. WDTEN is a protected bit. If the Protection Scheme (see Chapter 3.3.4.1) is activated, then this bit cannot be written directly. Watchdog Prewarning Mode Flag 0 Normal mode (default after reset) 1 The Watchdog is operating in prewarning mode. This bit is set to 1 when a Watchdog error is detected. The WDT has issued an NMI trap and is in prewarning mode. A reset of the chip occurs after the prewarning period has expired. Watchdog Window-Boundary Enable 0 Watchdog Window-Boundary feature is disabled (default). 1 Watchdog Window-Boundary feature is enabled. Reserved Returns 0 if read; should be written with 0. WDTRS 1 rwh WDTEN 2 rw WDTPR 4 rh WINBEN 5 rw 0 3, [7:6] r User’s Manual Watchdog Timer, V 0.4 9-6 V 0.2, 2005-01 XC866 Watchdog Timer WDTL Watchdog Timer Register Low 7 6 5 4 WDT rh 3 2 Reset Value: 00H 1 0 WDTH Watchdog Timer Register High 7 6 5 4 WDT rh 3 2 Reset Value: 00H 1 0 Field WDT Bits [7:0] of WDTL, [7:0] of WDTH Type Description rh Watchdog Timer Current Value WDTWINB Watchdog Window-Boundary Count 7 6 5 4 3 2 Reset Value: 00H 1 0 WDTWINB rw Field WDTWINB Bits [7:0] Type Description rw Watchdog Window-Boundary Count Value This value is programmable. The WDT cannot do a refresh within the Window Boundary range from 0000H to the value obtained from the concatenation of WDTWINB and 00H, as it would cause WDTRST to be asserted. WDTWINB is matched to WDTH. User’s Manual Watchdog Timer, V 0.4 9-7 V 0.2, 2005-01 XC866 Watchdog Timer PMCON0 Power Mode Control Register 0 7 0 r 6 WDTRST rwh 5 WKRS rwh 4 WKSEL rw 3 SD rw Reset Value: See Table 8-1 2 PD rwh 1 WS rw 0 The functions of the shaded bits are not described here Field WDTRST Bits 6 Type Description rwh Watchdog Timer Reset Indication Bit 0 No WDT reset has occurred. 1 WDT reset has occurred. Reserved Returns 0 if read; should be written with 0. 0 7 r User’s Manual Watchdog Timer, V 0.4 9-8 V 0.2, 2005-01 XC866 Serial Interfaces 10 Serial Interfaces The XC866 contains two serial interfaces, the Universal Asynchronous Receiver/ Transmitter (UART) and the High-Speed Synchronous Serial Interface (SSC), for serial communication with external devices. Additionally, the UART can be used to support the Local Interconnect Network (LIN) protocol. UART Features: • Full-duplex asynchronous modes – 8-bit or 9-bit data frames, LSB first – fixed or variable baud rate • Receive buffered • Multiprocessor communication • Interrupt generation on the completion of a data transmission or reception LIN Features: • Master and slave mode operation SSC Features: • Master and slave mode operation – Full-duplex or half-duplex operation • Transmit and receive buffered • Flexible data format – Programmable number of data bits: 2 to 8 bits – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock • Variable baud rate • Compatible with Serial Peripheral Interface (SPI) • Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error) User’s Manual Serial Interfaces, V 0.3 10-1 V 0.2, 2005-01 XC866 Serial Interfaces 10.1 UART The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. 10.1.1 UART Modes The UART can be used in three asynchronous modes. In mode 1, it operates as an 8-bit serial port, and in modes 2 and 3, it operates as a 9-bit serial port. The only difference between mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is derived from the dedicated baud-rate generator. The different modes are selected by setting bits SM0 and SM1 to their corresponding values, as shown in Table 10-1. The selection where the value of both SM0 and SM1 is zero, is reserved. Table 10-1 SM0 0 0 1 1 UART Modes SM1 0 1 0 1 Operating Mode Reserved Mode 1: 8-bit shift UART Mode 2: 9-bit shift UART Mode 3: 9-bit shift UART – Variable fPCLK/32 or fPCLK/64 Variable Baud Rate 10.1.1.1 Mode 1, 8-Bit UART, Variable Baud Rate In mode 1, the UART behaves as an 8-bit serial port. A start bit (0), 8 data bits, and a stop bit (1) are transmitted on TXD or received on RXD at the baud rate set by the underflow rate on the dedicated baud-rate generator. This baud rate is variable. The transmission cycle is activated by a write to SBUF. The data is transferred to the transmit register and a 1 is loaded to the 9th bit position. At phase 1 of the machine cycle after the next rollover in the divide-by-16 counter, the start bit is copied to TXD, and data is activated one bit time later. One bit time after the data is activated, the data starts getting shifted right with zeros shifted in from the left. When the MSB gets to the output position, the control block executes one last shift and sets the TI bit. Reception is started by a high to low transition on RXD (sampled at 16 times the baud rate). The divide-by-16 counter is then reset and 1111 1111B is written to the receive register. If a valid start bit (0) is then detected (based on two out of three samples), it is shifted into the register followed by 8 data bits. If the transition is not followed by a valid start bit, the controller goes back to looking for a high to low transition on RXD. When the User’s Manual Serial Interfaces, V 0.3 10-2 V 0.2, 2005-01 XC866 Serial Interfaces start bit reaches the leftmost position, the control block executes one last shift, then loads SBUF with the 8 data bits, loads RB8 (SCON.2) with the stop bit, and sets the RI bit, provided RI = 0, and either SM2 = 0 (see Section 10.1.2) or the received stop bit = 1. If none of these conditions is met, the received byte is lost. The associated timings for transmit/receive in mode 1 are illustrated in Figure 10-1. User’s Manual Serial Interfaces, V 0.3 10-3 V 0.2, 2005-01 XC866 Serial Interfaces Transmit Stop Bit Stop Bit D7 D6 D5 D4 D3 D2 D1 Start Bit D0 reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Bit Detector Sample Times RX Clock RXD Shift TX Clock Data TXD Shift TI Receive Figure 10-1 Serial Interface, Mode 1, Timing Diagram User’s Manual Serial Interfaces, V 0.3 10-4 V 0.2, 2005-01 RI XC866 Serial Interfaces 10.1.1.2 Mode 2, 9-Bit UART, Fixed Baud Rate In mode 2, the UART behaves as a 9-bit serial port. A start bit (0), 8 data bits plus a programmable 9th bit and a stop bit (1) are transmitted on TXD or received on RXD. The 9th bit for transmission is taken from TB8 (SCON.3) while for reception, the 9th bit received is placed in RB8 (SCON.2). The transmission cycle is activated by a write to SBUF. The data is transferred to the transmit register and TB8 is copied into the 9th bit position. At phase 1 of the machine cycle following the next rollover in the divide-by-16 counter, the start bit is copied to TXD and data is activated one bit time later. One bit time after the data is activated, the data starts shifting right. For the first shift, a stop bit (1) is shifted in from the left and for subsequent shifts, zeros are shifted in. When the TB8 bit gets to the output position, the control block executes one last shift and sets the TI bit. Reception is started by a high to low transition on RXD (sampled at 16 times the baud rate). The divide-by-16 counter is then reset and 1111 1111B is written to the receive register. If a valid start bit (0) is then detected (based on two out of three samples), it is shifted into the register followed by 8 data bits. If the transition is not followed by a valid start bit, the controller goes back to looking for a high to low transition on RXD. When the start bit reaches the leftmost position, the control block executes one last shift, then loads SBUF with the 8 data bits, loads RB8 (SCON.2) with the 9th data bit, and sets the RI bit, provided RI = 0, and either SM2 = 0 (see Section 10.1.2) or the 9th bit = 1. If none of these conditions is met, the received byte is lost. The baud rate for the transfer is either fPCLK/64 or fPCLK/32, depending on the setting of the top bit (SMOD) of the PCON (Power Control) register, which acts as a Double Baud Rate selector. 10.1.1.3 Mode 3, 9-Bit UART, Variable Baud Rate Mode 3 is the same as mode 2 in all respects except that the baud rate is variable and is set by the underflow rate on the dedicated baud-rate generator. In all modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in the modes by the incoming start bit if REN = 1. The serial interface also provides interrupt requests when transmission or reception of the frames has been completed. The corresponding interrupt request flags are TI or RI, respectively. If the serial interrupt is not used (i.e., serial interrupt not enabled), TI and RI can also be used for polling the serial interface. The associated timings for transmit/receive in modes 2 and 3 are illustrated in Figure 10-2. User’s Manual Serial Interfaces, V 0.3 10-5 V 0.2, 2005-01 TX Clock User’s Manual Serial Interfaces, V 0.3 Transmit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Data Shift TXD Start Bit TI Figure 10-2 Serial Interface, Modes 2 and 3, Timing Diagram 10-6 Stop Bit Generation RX Clock RXD Receive Bit Detector Sample Times Shift Serial Interfaces V 0.2, 2005-01 RI XC866 XC866 Serial Interfaces 10.1.2 Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communication using a system of address bytes with bit 9 = 1 and data bytes with bit 9 = 0. In these modes, 9 data bits are received. The 9th data bit goes into RB8. The communication always ends with one stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One of the ways to use this feature in multiprocessor systems is described in the following paragraph. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte that identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that were not being addressed retain their SM2s as set and ignore the incoming data bytes. Bit SM2 can be used in mode 1 to check the validity of the stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 10.1.3 Register Description The UART uses two Special Function Registers (SFRs), SCON and SBUF. SCON is the control register and SBUF is the data register. On reset, both SCON and SBUF return 00H. The serial port control and status register is the SFR SCON. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8) and the serial port interrupt bits (TI and RI). SBUF is the receive and transmit buffer of the serial interface. Writing to SBUF loads the transmit register and initiates transmission. This register is used for both transmit and receive data. Transmit data is written to this location and receive data is read from this location, but the two paths are independent. Reading out SBUF accesses a physically separate receive register. SBUF Serial Data Buffer 7 6 5 4 VAL rwh 3 2 Reset Value: 00H 1 0 User’s Manual Serial Interfaces, V 0.3 10-7 V 0.2, 2005-01 XC866 Serial Interfaces Field VAL Bits [7:0] Type Description rwh Serial Interface Buffer Register SCON Serial Channel Control Register 7 SM0 rw 6 SM1 rw 5 SM2 rw 4 REN rw 3 TB8 rw 2 RB8 rwh Reset Value: 00H 1 TI rwh 0 RI rwh Field RI Bits 0 Type Description rwh Receive Interrupt Flag This is set by hardware at the half point of the stop bit in modes 1, 2, and 3. Must be cleared by software. Transmit Interrupt Flag This is set by hardware at the beginning of the stop bit in modes 1, 2, and 3. Must be cleared by software. Serial Port Receiver Bit 9 In modes 2 and 3, this is the 9th data bit received. In mode 1, this is the stop bit received. Serial Port Transmitter Bit 9 In modes 2 and 3, this is the 9th data bit sent. Enable Receiver of Serial Port 0 Serial reception is disabled. 1 Serial reception is enabled. Enable Serial Port Multiprocessor Communication in Modes 2 and 3 In mode 2 or 3, if SM2 is set to 1, RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 is set to 1, RI will not be activated if a valid stop bit (RB8) was not received. TI 1 rwh RB8 2 rwh TB8 REN 3 4 rw rw SM2 5 rw User’s Manual Serial Interfaces, V 0.3 10-8 V 0.2, 2005-01 XC866 Serial Interfaces Field SM1 SM0 Bits 6 7 Type Description rw Serial Port Operating Mode Selection SM0 SM1 Selected operating mode 0 0 1 1 0 1 0 1 Mode 0: Reserved Mode 1: 8-bit UART, variable baud rate Mode 2: 9-bit UART, fixed baud rate (fPCLK/32 or fPCLK/64) Mode 3: 9-bit UART, variable baud rate 10.1.4 Baud Rate Generation There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. “Baud rate clock” and “baud rate” must be distinguished from each other. The serial interface requires a clock rate that is 16 times the baud rate for internal synchronization. Therefore, the baud-rate generators must provide a “baud rate clock” to the serial interface where it is divided by 16 to obtain the actual “baud rate”. The abbreviation fPCLK refers to the input clock frequency. In mode 2, the baud rate is either fPCLK/64 or fPCLK/32 depending on the setting of PCON.SMOD, which acts as a Double Baud Rate selector. However, when the serial port is being used in either mode 1 or mode 3, it has a variable baud rate principally set by the underflow rate of the dedicated baud-rate generator. User’s Manual Serial Interfaces, V 0.3 10-9 V 0.2, 2005-01 XC866 Serial Interfaces The fixed baud rate of the serial port in mode 2 is controlled by bit SMOD in SFR PCON, as shown below. The variable baud rate supplied by the dedicated baud-rate generator, for modes 1 and 3, is unaffected by this bit. PCON Power Control Register 7 SMOD rw 6 5 0 r 4 3 GF1 rw 2 GF0 rw Reset Value: 00H 1 0 r 0 IDLE rw The functions of the shaded bits are not described here Field SMOD Bits 7 Type Description rw Double Baud Rate Enable 0 Do not double the baud rate of serial interface in mode 2. 1 Double baud rate of serial interface in mode 2. Note: Depending on the programmed operating mode, different paths are selected for the baud rate clock. 10.1.4.1 Baud-rate Generator The XC866 provides a dedicated baud-rate generator to generate the baud rate for the UART module. It has programmable 8-bit reload value and 3-bit prescaler. The baud-rate generator is clocked with a clock (fDIV) derived via a prescaler from the input clock fPCLK. The baud rate timer counts downwards and can be started or stopped through the baud rate control run bit BCON.R. Each underflow of the timer provides one clock pulse to the serial channel. The timer is reloaded with the value stored in its 8-bit reload register each time it underflows. The prescaler is selected by the bit field BCON.BRPRE. Register BG is the dual-function Baud-rate Generator/Reload register. Reading BG returns the contents of the timer, while writing to BG always updates the reload register. An auto-reload of the timer with the contents of the reload register is performed each time BG is written to. However, if BCON.R is cleared at the time a write operation to BG is performed, the timer will not be reloaded until the first instruction cycle after BCON.R is set. User’s Manual Serial Interfaces, V 0.3 10-10 V 0.2, 2005-01 XC866 Serial Interfaces The baud rate of the baud-rate generator depends on the following bits and register values: • Input clock fPCLK • Value of register BCON.BRPRE • Value of the 8-bit reload register BG 8-Bit Baudrate Timer fPCLK Prescaler fDIV 8-Bit Baudrate Timer fBR R Figure 10-3 Baud-rate Generator Circuitry The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud-rate generators must provide a “baud rate clock” to the serial interface, which is divided by 16 and results in the actual baud rate. The following formula includes the factor and calculates the final baud rate. baud rate = fPCLK 16 x PRE x (BG+1) The value of PRE (prescaler) is chosen by the bit BCON.BRPRE. BG represents the contents of the reload register BG.BR_VALUE, which is taken as unsigned 8-bit integer. The maximum baud rate that can be achieved for a module clock of 26.7 MHz is 1.67 MBaud. Table 10-2 lists various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baud rate. Table 10-2 Typical Baud Rates of UART PRE 1 (BRPRE=000) 1 (BRPRE=000) 2 (BRPRE=001) 4 (BRPRE=010) Reload Value 87 (57H) 174 (AEH) 174 (AEH) 174 (AEH) Deviation Error -0.22 % -0.22 % -0.22 % -0.22 % Baud rate (fPCLK = 26.7 MHz) 19.2 kBaud 9600 Baud 4800 Baud 2400 Baud User’s Manual Serial Interfaces, V 0.3 10-11 V 0.2, 2005-01 XC866 Serial Interfaces Register BCON contains control bits for baud-rate generator and the prescaler bit field. BCON Baud Rate Control Register 7 BGSEL rw 6 5 T2EXIS rw 4 BRDIS rw 3 2 BRPRE rw Reset Value: 00H 1 0 R rw Field R Bits 0 Type Description rw Baud-rate Generator Run Control Bit 0 Baud-rate generator is disabled. 1 Baud-rate generator is enabled. Note: BR_VALUE should only be written if R = 0. Prescaler Bit Selects the input clock for fDIV which is derived from the peripheral clock. 000 fDIV= fPCLK 001 fDIV = fPCLK/2 010 fDIV = fPCLK/4 011 fDIV = fPCLK/8 100 fDIV = fPCLK/16 101 fDIV = fPCLK/32 Others: reserved Baud Rate Detection Disable 0 Baud rate detection is enabled. 1 Baud rate detection is disabled. T2EX Function Select 0 T2EX is selected for baud rate detection. 1 T2EX is selected for Timer 2 function. Baud Rate Select for detection 00 10 kHz to 20 kHz 01 5 kHz to 10 kHz 10 2.5 kHz to 5 kHz 11 1.25 kHz to 2.5 kHz BRPRE [3:1] rw BRDIS 4 rw T2EXIS 5 rw BGSEL [7:6] rw User’s Manual Serial Interfaces, V 0.3 10-12 V 0.2, 2005-01 XC866 Serial Interfaces Register BG contains the 8-bit reload value for the baud rate timer. BG Baud Rate Timer/Reload Register 7 6 5 4 3 2 Reset Value: 00H 1 0 BR_VALUE rw Field BR_VALUE Bits [7:0] Type Description rw Baud Rate Timer/Reload Value Reading returns the 8-bit content of the baud rate timer; writing loads the baud rate timer/reload value. Note: BG should only be written if R = 0. 10.1.5 Interfaces of UART The UART has two input/output lines; TXD for data transmission and RXD for data reception. Data that is shifted into the UART module through RXD can be selected from two different sources, RXD_0 and RXD_1. This selection is performed by the SFR bit MODPISEL.URRIS. MODPISEL Peripheral Input Select Register 7 0 r 6 5 4 3 0 r 2 Reset Value: 00H 1 EXINT0IS rw 0 URRIS rw JTAGTDIS JTAGTCK S rw rw The functions of the shaded bits are not described here Field URRIS Bits 0 Type Description rw UART Receive Input Select 0 UART Receiver Input RXD_0 is selected. 1 UART Receiver Input RXD_1 is selected. User’s Manual Serial Interfaces, V 0.3 10-13 V 0.2, 2005-01 XC866 Serial Interfaces 10.2 LIN The UART can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception. 10.2.1 LIN Protocol LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An attractive feature of LIN is self-synchronization of the slave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame. The structure of a LIN frame is shown in Figure 10-4. The frame consists of the: • • • • header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field response time data bytes (according to UART protocol) checksum Frame slot Frame Response space Interframe space Header Response Synch Protected identifier Data 1 Data 2 Data N Checksum Figure 10-4 The Structure of LIN Frame Each byte field is transmitted as a serial byte, as shown in Figure 10-5. The LSB of the data is sent first and the MSB is sent last. The start bit is encoded as a bit with value zero (dominant) and the stop bit is encoded as a bit with value one (recessive). User’s Manual Serial Interfaces, V 0.3 10-14 V 0.2, 2005-01 XC866 Serial Interfaces Byte field LSB (bit 0) MSB (bit 7) Start Bit Stop Bit Figure 10-5 The Structure of Byte Field The break is used to signal the beginning of a new frame. It is the only field that does not comply with Figure 10-5. A break is always generated by the master task (in the master mode) and it must be at least 13 bits of dominant value, including the start bit, followed by a break delimiter, as shown in Figure 10-6. The break delimiter will be at least one nominal bit time long. A slave node will use a break detection threshold of 11 nominal bit times. Start Bit Break delimit Figure 10-6 The Break Field Synch Byte is a specific pattern for determination of time base. The byte field is with the data value 55H, as shown in Figure 10-7. A slave task is always able to detect the Break/Synch sequence, even if it expects a byte field (assuming the byte fields are separated from each other). If this happens, detection of the Break/Synch sequence will abort the transfer in progress and processing of the new frame will commence. Start Bit Stop Bit Figure 10-7 The Synch Byte Field User’s Manual Serial Interfaces, V 0.3 10-15 V 0.2, 2005-01 XC866 Serial Interfaces The slave task will receive and transmit data when an appropriate ID is sent by the master: 1. Slave waits for Synch Break 2. Slave synchronizes on Synch Byte 3. Slave snoops for ID 4. According to ID, slave determines whether to receive or transmit data, or do nothing 5. When transmitting, the slave sends 2, 4 or 8 data bytes, followed by check byte 10.2.2 LIN Header Transmission LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by each frame. The information needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame. The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data. The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. The UART can be used to transmit a 20-bit break field by the following sequence: Step 1: Set the UART to mode 1: • This configures the UART as an 8-bit UART with a variable baud rate. Step 2: Set the baud rate to two times of the desired baud rate Step 3: Write 00H to the transmit buffer to begin transmission By having two times of the desired baud rate, the 10-bit UART frame consisting of the start, stop and 8 data bits will achieve the effect of a 20-bit break field on the LIN bus. For subsequent synch and identifier fields, the baud rate must then be adjusted back to the initial value. User’s Manual Serial Interfaces, V 0.3 10-16 V 0.2, 2005-01 XC866 Serial Interfaces 10.2.3 Baud Rate Detection of LIN In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of frame. For this purpose, every frame starts with a sequence consisting of a break field followed by a synch byte field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field. In order to detect the baud rate of LIN, the bit timing Tbit is calculated by measuring the time between the falling edges of pattern. In baud rate detection mode, the timing of the two bits in Synch Byte field is captured, which is shown in Figure 10-8. Synch Byte 2Tbit START 0 BIT 1 2 3 4 5 6 7 STOP BIT Figure 10-8 The Bit Timing in Synch Byte Register bits 4-7 of BCON register (see Page 10-12) are used for the LIN baud rate detection. Register bit BRDIS is used to enable/disable the baud rate detection. Register bit T2EXIS is used to choose the T2EX pin (P1.0) for the baud rate detection purpose or for the normal Timer 2 function use. Users should specify the baud rate range via the register bit BGSEL if they know the range of the LIN baud rate. The baud rate detection unit will use different sampling rates for different baud rates according to this information. This will result in accurate baud rate detection. The following sequence is generally executed to start the baud rate detection: Step1: With the first falling edge of RXD: • If the system is in the power-down mode and PMCON0.WS = 01, a wake-up from the power-down through the RXD pin will be activated. • Once the system enters normal mode, the following settings must be done by software: – Bit PMCON1.T2_DIS is set to 0 (enable Timer 2) – Bit BCON.BRDIS is set to 0 (enable baud rate detection) – Bit BCON.T2EXIS is set to 0 (T2EX pin is used for baud rate detection) – Provide the baud rate range via bit BCON.BGSEL – Bits T2CON.CP/RL2 and T2CON. EXEN2 are set to 1. T2MOD.EDGESEL is set to 0. (Timer 2 is set to the capture mode with falling edge trigger) User’s Manual Serial Interfaces, V 0.3 10-17 V 0.2, 2005-01 XC866 Serial Interfaces • The UART is running with an estimated baud rate, which is generated by the baud-rate generator. (See Section 10.1.4.1) Step 2: With the second falling edge of Synch Byte: • Start Timer 2 by hardware (Bit 1 of Synch Byte field). Step 3: With the third falling edge of Synch Byte: • The capture action of Timer 2 will be triggered and lead to a capture of the time of bit 1 and bit 2 in Synch Byte field. The contents of the timer register (THL2) are captured into the RC2 register. The captured value is 2 LIN bit times long. If the capture signal is detected while the counter is being incremented, the counter is first incremented before the capture operation is performed. This ensures that the latest value of the timer register is always captured. • When the capture operation is completed, bit T2CON.EXF2 is set and can be used to generate an interrupt request. • The software will use the RC2 value of Timer 2 to retrieve the reload value BG_VALUE and prescaler BRPRE of the baud-rate generator. • The software updates the baud-rate generator with the new BG value and prescaler value, and generates the new baud rate. The reload register of Timer 2 (RC2) is reloaded with value 0000H by software. User’s Manual Serial Interfaces, V 0.3 10-18 V 0.2, 2005-01 XC866 Serial Interfaces 10.3 High-Speed Synchronous Serial Interface The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces. Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. Figure 10-9 shows the block diagram of the SSC. P CLK SS_CLK MS_CLK Baud-rate Generator Clock Control Shift Clock RIR SSC Control Block Register CON TIR EIR Receive Int. Request Transmit Int. Request Error Int. Request Status Control TXD(Master) RXD(Slave) TXD(Slave) RXD(Master) 16-Bit Shift Register Pin Control Transmit Buffer Register TB Receive Buffer Register RB Internal Bus Figure 10-9 Synchronous Serial Channel SSC Block Diagram User’s Manual Serial Interfaces, V 0.3 10-19 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.1 General Operation 10.3.1.1 Operating Mode Selection The operating mode of the serial channel SSC is controlled by its control register CON. This register has a double function: • During programming (SSC disabled by CON.EN = 0), it provides access to a set of control bits • During operation (SSC enabled by CON.EN = 1), it provides access to a set of status flags. The shift register of the SSC is connected to both the transmit lines and the receive lines via the pin control logic. Transmission and reception of serial data are synchronized and take place at the same time, i.e., the same number of transmitted bits is also received. Transmit data is written into the Transmitter Buffer register (TB) and is moved to the shift register as soon as this is empty. An SSC master (CON.MS = 1) immediately begins transmitting, while an SSC slave (CON.MS = 0) will wait for an active shift clock. When the transfer starts, the busy flag CON.BSY is set and the Transmit Interrupt Request line (TIR) will be activated to indicate that register TB may be reloaded again. When the programmed number of bits (2...8) have been transferred, the contents of the shift register are moved to the Receiver Buffer register (RB) and the Receive Interrupt Request line (RIR) will be activated. If no further transfer is to take place (TB is empty), CON.BSY will be cleared at the same time. Software should not modify CON.BSY, as this flag is hardware controlled. Note: Only one SSC can be the master at a given time. The transfer of serial data bits can be programmed in a number of ways: The data width can be specified from 2 to 8 bits A transfer may start with either the LSB or the MSB The shift clock may be idle low or idle high The data bits may be shifted with the leading edge or the trailing edge of the shift clock signal • The baud rate may be set within a certain range depending on the module clock • The shift clock can be generated (MS_CLK) or can be received (SS_CLK) These features allow the SSC to be adapted to a wide range of applications requiring serial data transfer. The Data Width Selection supports the transfer of frames of any data length, from 2-bit “characters” up to 8-bit “characters”. Starting with the LSB (CON.HB = 0) allows communication with SSC devices in synchronous mode or with serial interfaces such as the one in 8051. Starting with the MSB (CON.HB = 1) allows operation compatible with the SPI interface. Regardless of the data width selected and whether the MSB or the LSB is transmitted first, the transfer data is always right-aligned in registers TB and RB, with the LSB of the User’s Manual Serial Interfaces, V 0.3 10-20 V 0.2, 2005-01 • • • • XC866 Serial Interfaces transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the internal shift register logic. The unselected bits of TB are ignored; the unselected bits of RB will not be valid and should be ignored by the receiver service routine. The Clock Control allows the transmit and receive behavior of the SSC to be adapted to a variety of serial interfaces. A specific shift clock edge (rising or falling) is used to shift out transmit data, while the other shift clock edge is used to latch in receive data. Bit CON.PH selects the leading edge or the trailing edge for each function. Bit CON.PO selects the level of the shift clock line in the idle state. Thus, for an idle-high clock, the leading edge is a falling one, a 1 - to - 0 transition (see Figure 10-10). CON. PO CON. PH 0 0 1 1 0 1 0 1 Shift Clock MS_CLK/SS_CLK Pins MTSR/MRST First Bit Latch Data Shift Data Transmit Data Last Bit Figure 10-10 Serial Clock Phase and Polarity Options When initializing the devices for serial communication, one device must be selected for master operation while all other devices must be programmed for slave operation. 10.3.1.2 Full-Duplex Operation The various devices are connected through three lines. The definition of these lines is always determined by the master: the line connected to the master’s data output line TXD is the transmit line; the receive line is connected to its data input line RXD; the shift clock line is either MS_CLK or SS_CLK. Only the device selected for master operation generates and outputs the shift clock on line MS_CLK. Since all slaves receive this clock, their pin SCLK must be switched to input mode. The external connections are hard-wired, and the function and direction of these pins are determined by the master or slave operation of the individual device. User’s Manual Serial Interfaces, V 0.3 10-21 V 0.2, 2005-01 XC866 Serial Interfaces Master Shift Register Device #1 MTSR Device #2 Shift Register Slave Transmit Receive Clock MTSR MRST MRST Clock CLK CLK Clock Device #3 Shift Register MTSR Slave MRST CLK Clock Figure 10-11 SSC Full-Duplex Configuration The data output pins MRST of all slave devices are connected together onto the single receive line in the configuration shown in Figure 10-11. During a transfer, each slave shifts out data from its shift register. There are two ways to avoid collisions on the receive line due to different slave data: • Only one slave drives the line, i.e., enables the driver of its MRST pin. All the other slaves must have their MRST pins programmed as input so only one slave can put its data onto the master's receive line. Only the receiving of data from the master is possible. The master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. The selected slave then switches its MRST line to output until it gets a de-selection signal or command. • The slaves use open drain output on MRST. This forms a wired-AND connection. The receive line needs an external pull-up in this case. Corruption of the data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master send ones only. Because this high level is not actively driven onto the line, but only held through the pull-up device, the selected slave can pull this line actively to a low level when transmitting a zero bit. The master selects the User’s Manual Serial Interfaces, V 0.3 10-22 V 0.2, 2005-01 XC866 Serial Interfaces slave device from which it expects data either by separate select lines or by sending a special command to this slave. After performing the necessary initialization of the SSC, the serial interfaces can be enabled. For a master device, the clock line will now go to its programmed polarity. The data line will go to either 0 or 1 until the first transfer starts. After a transfer, the data line will always remain at the logic level of the last transmitted data bit. When the serial interfaces are enabled, the master device can initiate the first data transfer by writing the transmit data into register TB. This value is copied into the shift register (assumed to be empty at this time), and the selected first bit of the transmit data will be placed onto the TXD line on the next clock from the baud-rate generator (transmission starts only if CON.EN = 1). Depending on the selected clock phase, a clock pulse will also be generated on the MS_CLK line. At the same time, with the opposite clock edge, the master latches and shifts in the data detected at its input line RXD. This “exchanges” the transmit data with the receive data. Because the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master’s shift register—shifting out the data contained in the registers, and shifting in the data detected at the input line. With the start of the transfer, the busy flag CON.BSY is set and the TIR will be activated to indicate that register TB may be reloaded again. After the preprogrammed number of clock pulses (via the data width selection), the data transmitted by the master is contained in all the slaves’ shift registers, while the master’s shift register holds the data of the selected slave. In the master and all slaves, the contents of the shift register are copied into the receive buffer RB and the RIR is activated. If no further transfer is to take place (TB is empty), CON.BSY will be cleared at the same time. Software should not modify CON.BSY, as this flag is hardware controlled. When configured as a slave device, the SSC will immediately output the selected first bit (MSB or LSB of the transfer data) at the output pin once the contents of the transmit buffer are copied into the slave's shift register. Bit CON.BSY is not set until the first clock edge at SS_CLK appears. Note: On the SSC, a transmission and a reception take place at the same time, regardless of whether valid data has been transmitted or received. Note: The initialization of the CLK pin on the master requires some attention in order to avoid undesired clock transitions, which may disturb the other devices. Before the clock pin is switched to output via the related direction control register, the clock output level will be selected in the control register CON and the alternate output be prepared via the related ALTSEL register, or the output latch must be loaded with the clock idle level. User’s Manual Serial Interfaces, V 0.3 10-23 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.1.3 Half-Duplex Operation In a half-duplex mode, only one data line is necessary for both receiving and transmitting of data. The data exchange line is connected to both the MTSR and MRST pins of each device, the shift clock line is connected to the SCLK pin. The master device controls the data transfer by generating the shift clock, while the slave devices receive it. Due to the fact that all transmit and receive pins are connected to one data exchange line, serial data may be moved between arbitrary stations. As in full-duplex mode, there are two ways to avoid collisions on the data exchange line: • only the transmitting device may enable its transmit pin driver • the non-transmitting devices use open drain output and send only ones. Since the data inputs and outputs are connected together, a transmitting device will clock in its own data at the input pin (MRST for a master device, MTSR for a slave). By this method, any corruptions on the common data exchange line are detected if the received data is not equal to the transmitted data. Master Shift Register MTSR MTSR Device #1 Transmit Device #2 Shift Register Slave MRST MRST Clock CLK Clock CLK Clock Common Transmit/ Receive Device #3 Line MTSR Slave Shift Register MRST CLK Clock Figure 10-12 SSC Half-Duplex Configuration User’s Manual Serial Interfaces, V 0.3 10-24 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.1.4 Continuous Transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer TB is empty and ready to be loaded with the next transmit data. If TB has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission will start without any additional delay. On the data line, there is no gap between the two successive frames. For example, two byte transfers would look the same as one word transfer. This feature can be used to interface with devices that can operate with or require more than 8 data bits per transfer. It is just a matter of software specifying the total data frame length. This option can also be used to interface with byte-wide and word-wide devices. Note: This feature allows only multiples of the selected basic data width, because it would require disabling/enabling of the SSC to reprogram the basic data width onthe-fly. 10.3.1.5 Port Control The SSC uses three lines to communicate with the external world as shown in Figure 10-13. Pin SCLK serves as the clock line, while pins MRST and MTSR serve as the serial data input/output lines. EIR Master Interrupt System TBIR TIR MRST MTSR P0.4/MTSR_1 Port Control P0.5/MRST_1 SCLK P0.3/SCLK_1 Slave Master/ Slave SSC Module (Kernel) MTSR MRST Figure 10-13 SSC Module I/O Interface Operation of the SSC I/O lines depends on the selected operating mode (master or slave). The direction of the port lines depends on the operating mode. The SSC will User’s Manual Serial Interfaces, V 0.3 10-25 V 0.2, 2005-01 XC866 Serial Interfaces automatically use the correct kernel output or kernel input line of the ports when switching modes. Since the SSC I/O lines are connected with the bidirectional lines of the general purpose I/O ports, software I/O control is used to control the port pins assigned to these lines. The port registers must be programmed for alternate output and input selection. When switching between master and slave modes, port registers must be reprogrammed. 10.3.1.6 Baud Rate Generation The serial channel SSC has its own dedicated 16-bit baud-rate generator with 16-bit reload capability, allowing baud rate generation independent of the timers. Figure 10-14 shows the baud-rate generator. 16-Bit Reload Register fPCLK .2 . 16-Bit Counter f MS_CLK/SS_CLK fMS_CLK max in Master Mode< fPCLK /2 f SS_CLK max in Master Mode< fPCLK /4 Figure 10-14 SSC Baud-rate Generator The baud-rate generator is clocked with the module clock fPCLK. The timer counts downwards. Register BR is the dual-function Baud-rate Generator/Reload register. Reading BR, while the SSC is enabled, returns the contents of the timer. Reading BR, while the SSC is disabled, returns the programmed reload value. In this mode, the desired reload value can be written to BR. Note: Never write to BR while the SSC is enabled. The formulas below calculate either the resulting baud rate for a given reload value, or the required reload value for a given baud rate: Baud rate = fPCLK 2 x ( + 1) BR = fPCLK 2 x Baud rate -1 represents the contents of the reload register, taken as an unsigned 16-bit integer, while baud rate is equal to fMS_CLK/SS_CLK as shown in Figure 10-14. User’s Manual Serial Interfaces, V 0.3 10-26 V 0.2, 2005-01 XC866 Serial Interfaces The maximum baud rate that can be achieved when using a module clock of 26.7 MHz is 13.3 MBaud in master mode (with = 0000H) or 6.7 MBaud in slave mode (with = 0001H). Table 10-3 lists some possible baud rates together with the required reload values and the resulting deviation errors, assuming a module clock frequency of 26.7 MHz. Table 10-3 Reload Value 0000H 0001H 0009H 000CH 0011H 0013H 0015H 001AH 0031H 0042H 0063H 0084H FFFFH Typical Baud Rates of the SSC (fhw_clk = 26.7 MHz) Baud Rate (= fMS_CLK/SS_CLK) 13.3 MBaud (only in Master mode) 6.7 MBaud 1.3 MBaud 1 MBaud 750 kBaud 666.7 kBaud 600 kBaud 500 kBaud 266.7 kBaud 200 kBaud 133.3 kBaud 100 kBaud 203.45 Baud Deviation 0.0% 0.0% 0.0% 2.5% 1.2% 0.0% 1.0% 1.2% 0.0% 0.5% 0.0% 0.25% 0.0% 10.3.1.7 Error Detection Mechanisms The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes; Transmit Error and Baud Rate Error apply only to slave mode. When an error is detected, the respective error flag is set and an error interrupt request will be generated by activating the Error Interrupt Request line (EIR) (see Figure 10-15). The error interrupt handler may then check the error flags to determine the cause of the error interrupt. The error flags are not reset automatically, but rather must be cleared by software after servicing. This allows servicing of some error conditions via interrupt, while the others may be polled by software. Note: The error interrupt handler must clear the associated (enabled) error flag(s) to prevent repeated interrupt requests. User’s Manual Serial Interfaces, V 0.3 10-27 V 0.2, 2005-01 XC866 Serial Interfaces Bits in Register CON TEN Transmit Error TE & REN Receive Error RE & >1 Error Interrupt EIR PEN Phase Error PE & BEN Baud rate Error BE & Figure 10-15 SSC Error Interrupt Control A Receive Error (master or slave mode) is detected when a new data frame is completely received, but the previous data was not read out of the register RB. This condition sets the error flag CON.RE and, when enabled via CON.REN, sets the EIR. The old data in the receive buffer RB will be overwritten with the new value and this lost data is irretrievable. A Phase Error (master or slave mode) is detected when the incoming data at pin MRST (master mode) or MTSR (slave mode), sampled with the same frequency as the module clock, changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK. This condition sets the error flag CON.PE and, when enabled via CON.PEN, sets the EIR. A Baud Rate Error (slave mode) is detected when the incoming clock signal deviates from the programmed baud rate by more than 100%, i.e., it is either more than double or less than half the expected baud rate. This condition sets the error flag CON.BE and, when enabled via CON.BEN, sets the EIR. Using this error detection capability requires that the slave’s baud-rate generator be programmed to the same baud rate as the master device. This feature detects false, additional or missing pulses on the clock line (within a certain frame). User’s Manual Serial Interfaces, V 0.3 10-28 V 0.2, 2005-01 XC866 Serial Interfaces Note: If this error condition occurs and bit CON.REN = 1, an automatic reset of the SSC will be performed. This is done to re-initialize the SSC if too few or too many clock pulses have been detected. A Transmit Error (slave mode) is detected when a transfer was initiated by the master (SS_CLK gets active), but the transmit buffer TB of the slave had not been updated since the last transfer. This condition sets the error flag CON.TE and, when enabled via CON.TEN, sets the EIR. If a transfer starts without the transmit buffer having been updated, the slave will shift out the ‘old’ contents of the shift register, which normally is the data received during the last transfer. This may lead to corruption of the data on the transmit/receive line in half-duplex mode (open drain configuration) if this slave is not selected for transmission. This mode requires that slaves not selected for transmission only shift out ones; that is, their transmit buffers must be loaded with ‘FFFFH’ prior to any transfer. Note: A slave with push/pull output drivers not selected for transmission, will normally have its output drivers switched off. However, in order to avoid possible conflicts or misinterpretations, it is recommended to always load the slave's transmit buffer prior to any transfer. The cause of an error interrupt request (receive, phase, baud rate or transmit error) can be identified by the error status flags in control register CON. Note: In contrast to the EIR, the error status flags CON.TE, CON.RE, CON.PE, and CON.BE are not reset automatically upon entry into the error interrupt service routine, but must be cleared by software. User’s Manual Serial Interfaces, V 0.3 10-29 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.2 Interrupts An overview of the various interrupts in SSC is provided in Table 10-4. Table 10-4 Interrupt SSC Interrupt Sources Signal Description Indicates that the transmit buffer can be reloaded with new data. The configured number of bits have been transmitted and shifted to the receive buffer. This interrupt occurs if a new data frame is completely received and the last data in the receive buffer was not read. This interrupt is generated if the incoming data changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK. This interrupt is generated when the incoming clock signal deviates from the programmed baud rate by more than 100%. This interrupt is generated when TB was not updated since the last transfer if a transfer is initiated by a master. Transmission TIR starts Transmission RIR ends Receive Error Phase Error EIR EIR Baud Rate Error (Slave mode only) Transmit Error (Slave mode only) EIR EIR User’s Manual Serial Interfaces, V 0.3 10-30 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.3 Table 10-5 Address A9H AAH ABH ACH ADH AEH AFH Register Mapping SFR Address List Register PISEL CONL CONH TBL RBL BRL BRH The addresses of the kernel SFRs are listed in Table 10-5. User’s Manual Serial Interfaces, V 0.3 10-31 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.4 Register Description All SSC register names described in this section will be referenced in other chapters of this document with the module name prefix “SSC_”, e.g., SSC_PISEL. 10.3.4.1 Port Input Select Register The PISEL register controls the receiver input selection of the SSC module. PISEL Port Input Select Register 7 6 5 0 r 4 3 2 CIS rw Reset Value: 00H 1 SIS rw 0 MIS rw Field MIS Bits 0 Type Description rw Master Mode Receiver Input Select 0 Receiver input is disabled for master mode. 1 Receiver input is enabled for master mode. Slave Mode Receiver Input Select 0 Receiver input is disabled for slave mode. 1 Receiver input is enabled for slave mode. Slave Mode Clock Input Select 0 Clock input is disabled. 1 Clock input is enabled. Reserved Returns 0 if read; should be written with 0. SIS 1 rw CIS 2 rw 0 [7:3] r User’s Manual Serial Interfaces, V 0.3 10-32 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.4.2 Configuration Register The operating mode of the serial channel SSC is controlled by the control register CON. This register contains control bits for mode and error check selection, and status flags for error identification. Depending on bit EN, either control functions or status flags and master/slave control are enabled. CON.EN = 0: Programming Mode CONL Control Register Low 7 LB rw 6 PO rw 5 PH rw 4 HB rw 3 2 BM rw Reset Value: 00H 1 0 Field BM Bits [3:0] Type Description rw Data Width Selection 0000 Reserved. Do not use this combination. 0001 0111 Transfer Data Width is 2...8 bits (+1) Note: BM[3] is fixed to 0. Heading Control 0 Transmit/Receive LSB First 1 Transmit/Receive MSB First Clock Phase Control 0 Shift transmit data on the leading clock edge, latch on trailing edge 1 Latch receive data on leading clock edge, shift on trailing edge Clock Polarity Control 0 Idle clock line is low, leading clock edge is lowto-high transition 1 Idle clock line is high, leading clock edge is highto-low transition Loop Back Control 0 Normal output 1 Receive input is connected with transmit output (half-duplex mode) HB 4 rw PH 5 rw PO 6 rw LB 7 rw User’s Manual Serial Interfaces, V 0.3 10-33 V 0.2, 2005-01 XC866 Serial Interfaces CONH Control Register High 7 EN rw 6 MS rw 5 0 r 4 AREN rw 3 BEN rw 2 PEN rw Reset Value: 00H 1 REN rw 0 TEN rw Field TEN Bits 0 Type Description rw Transmit Error Enable 0 Ignore transmit errors 1 Check transmit errors Receive Error Enable 0 Ignore receive errors 1 Check receive errors Phase Error Enable 0 Ignore phase errors 1 Check phase errors Baud Rate Error Enable 0 Ignore baud rate errors 1 Check baud rate errors Automatic Reset Enable 0 No additional action upon a baud rate error 1 The SSC is automatically reset upon a baud rate error. Master Select 0 Slave mode. Operate on shift clock received via SCLK. 1 Master mode. Generate shift clock and output it via SCLK. Enable Bit = 0 Transmission and reception disabled. Access to control bits. Reserved Returns 0 if read; should be written with 0. REN 1 rw PEN 2 rw BEN 3 rw AREN 4 rw MS 6 rw EN 7 rw 0 5 r User’s Manual Serial Interfaces, V 0.3 10-34 V 0.2, 2005-01 XC866 Serial Interfaces CON.EN = 1: Operating Mode CONL Control Register Low 7 6 5 4 3 2 BC rh Reset Value: 00H 1 0 0 r Field BC Bits [3:0] Type Description rh Bit Count Field 0001 1111 Shift counter is updated with every shifted bit Reserved Returns 0 if read; should be written with 0. 0 [7:4] r CONH Control Register High 7 EN rw 6 MS rw 5 0 r 4 BSY rh 3 BE rwh 2 PE rwh Reset Value: 00H 1 RE rwh 0 TE rwh Field TE Bits 0 Type Description rwh Transmit Error Flag 0 No error 1 Transfer starts with the slave’s transmit buffer not being updated Receive Error Flag 0 No error 1 Reception completed before the receive buffer was read Phase Error Flag 0 No error 1 Received data changes around sampling clock edge RE 1 rwh PE 2 rwh User’s Manual Serial Interfaces, V 0.3 10-35 V 0.2, 2005-01 XC866 Serial Interfaces Field BE Bits 3 Type Description rwh Baud rate Error Flag 0 No error 1 More than factor 2 or 0.5 between slave’s actual and expected baud rate Busy Flag Set while a transfer is in progress Master Select Bit 0 Slave mode. Operate on shift clock received via SCLK. 1 Master mode. Generate shift clock and output it via SCLK. Enable Bit = 1 Transmission and reception enabled. Access to status flags and Master/Slave control. Reserved Returns 0 if read; should be written with 0. BSY MS 4 6 rh rw EN 7 rw 0 5 r Note: The target of an access to CON (control bits or flags) is determined by the state of CON.EN prior to the access; that is, writing C057H to CON in programming mode (CON.EN = 0) will initialize the SSC (CON.EN was 0) and then turn it on (CON.EN = 1). When writing to CON, ensure that reserved locations receive zeros. User’s Manual Serial Interfaces, V 0.3 10-36 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.4.3 Baud Rate Timer Reload Register The SSC baud rate timer reload register BR contains the 16-bit reload value for the baud rate timer. BRL Baud Rate Timer Reload Register Low 7 6 5 4 3 2 Reset Value: 00H 1 0 BR_VALUE[7:0] rw BRH Baud Rate Timer Reload Register High 7 6 5 4 3 2 Reset Value: 00H 1 0 BR_VALUE[15:8] rw Field BR_VALUE Bits [7:0] of BRL, [7:0] of BRH Type Description rw Baud Rate Timer/Reload Register Value Reading BR returns the 16-bit contents of the baud rate timer. Writing to BR loads the baud rate timer reload register with BR_VALUE. User’s Manual Serial Interfaces, V 0.3 10-37 V 0.2, 2005-01 XC866 Serial Interfaces 10.3.4.4 Transmit and Receive Buffer Register The SSC transmitter buffer register TB contains the transmit data value. TBL Transmitter Buffer Register Low 7 6 5 4 3 2 Reset Value: 00H 1 0 TB_VALUE rw Field TB_VALUE Bits [7:0] Type Description rw Transmit Data Register Value TB_VALUE is the data value to be transmitted. Unselected bits of TB are ignored during transmission. The SSC receiver buffer register RB contains the receive data value. RBL Receiver Buffer Register Low 7 6 5 4 3 2 Reset Value: 00H 1 0 RB_VALUE rh Field RB_VALUE Bits [7:0] Type Description rh Receive Data Register Value RB contains the received data value RB_VALUE. Unselected bits of RB will not be valid and should be ignored. User’s Manual Serial Interfaces, V 0.3 10-38 V 0.2, 2005-01 XC866 Timers 11 Timers The XC866 provides three 16-bit timers, Timer 0, Timer 1 and Timer 2. They are useful in many timing applications such as measuring the time interval between events and generating signals at regular intervals. Timer 0 and Timer 1 Features: • Four operational modes: – Mode 0: 13-bit timer – Mode 1: 16-bit timer – Mode 2: 8-bit timer with auto-reload – Mode 3: Two 8-bit timers Timer 2 Features: • Selectable up/down counting • 16-bit auto-reload mode • 1 channel, 16-bit capture mode 11.1 Timer 0 and Timer 1 Timer 0 and Timer 1 are count-up timers which are incremented every machine cycle, or in terms of the input clock, every 2 PCLK cycles. Both have four modes of operation that are used in a variety of applications. 11.1.1 Basic Timer Operations The operations of the two timers are controlled using the Special Function Registers (SFRs) TCON and TMOD. To enable a timer, i.e., allow the timer to run, its control bit TCON.TRx is set. Note: The “x” (e.g., TCON.TRx) in this chapter denotes either 0 or 1. Each timer consists of two 8-bit registers, TLx (low byte) and THx (high byte), which default to 00H on reset. Setting or clearing TCON.TRx does not affect the timer registers. Timer Overflow When a timer overflow occurs, the timer overflow flag TCON.TFx is set, and an interrupt may be raised if the interrupt enable control bit IEN0.ETx is set. The overflow flag is automatically cleared when the interrupt service routine is entered. When Timer 0 operates in mode 3, the Timer 1 control bits TR1, TF1 and ET1 are reserved for TH0. See Section 11.1.2.4. User’s Manual Timers, V 0.4 11-1 V 0.2, 2005-01 XC866 Timers External Control In addition to pure software control, the timers can be enabled or disabled through external port control. When a timer is enabled (TCON.TRx = 1) and TMOD.GATEx is set, the respective timer will only run if the core external interrupt EXINTx = 1. This facilitates pulse width measurements. However, this is not applicable for Timer 1 in mode 3. If TMOD.GATEx is cleared, the timer reverts to pure software control. 11.1.2 Timer Modes Timers 0 and 1 are fully compatible and can be configured in four different operating modes, as shown in Table 11-1. The bit field TxM in register TMOD selects the operating mode to be used for each timer. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 11-1 Mode 0 Timer 0 and Timer 1 Modes Operation 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 8-bit timer with auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow. Timer 0 operates as two 8-bit timers The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled. 1 2 3 User’s Manual Timers, V 0.4 11-2 V 0.2, 2005-01 XC866 Timers 11.1.2.1 Mode 0 Putting either Timer 0 or Timer 1 into mode 0 configures it as an 8-bit timer with a divide-by-32 prescaler. Figure 11-1 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag TFx. The overflow flag TFx can then be used to request an interrupt. The counted input is enabled for the timer when TRx = 1 and either GATEx = 0 or EXINTx = 1 (setting GATEx = 1 allows the timer to be controlled by external input EXINTx to facilitate pulse width measurements). TRx is a control bit in the register TCON; bit GATEx is in register TMOD. The 13-bit register consists of all the 8 bits of THx and the lower 5 bits of TLx. The upper 3 bits of TLx are indeterminate and should be ignored. Setting the run flag (TRx) does not clear the registers. Mode 0 operation is the same for Timer 0 and Timer 1. fPCLK/2 TL0 (5 Bits) TH0 (8 Bits) TF0 Interrupt Control TR0 & GATE0 =1 >1 EXINT0 Timer0_Mode0 Figure 11-1 Timer 0, Mode 0: 13-bit Timer User’s Manual Timers, V 0.4 11-3 V 0.2, 2005-01 XC866 Timers 11.1.2.2 Mode 1 Mode 1 operation is similar to that of mode 0, except that the timer register runs with all 16 bits. Mode 1 operation for Timer 0 is shown in Figure 11-2. fPCLK/2 TL0 (8 Bits) TH0 (8 Bits) TF0 Interrupt Control TR0 & GATE0 =1 >1 EXINT0 Timer0_Mode1 Figure 11-2 Timer 0, Mode 1: 16-bit Timer User’s Manual Timers, V 0.4 11-4 V 0.2, 2005-01 XC866 Timers 11.1.2.3 Mode 2 In mode 2 operation, the timer is configured as an 8-bit counter (TLx) with automatic reload, as shown in Figure 11-3 for Timer 0. An overflow from TLx not only sets TFx, but also reloads TLx with the contents of THx that has been preset by software. The reload leaves THx unchanged. fPCLK/2 TL0 (8 Bits) TF0 Interrupt Control Reload TR0 =1 & TH0 (8 Bits) >1 GATE0 EXINT0 Timer0_Mode2 Figure 11-3 Timer 0, Mode 2: 8-bit Timer with Auto-Reload User’s Manual Timers, V 0.4 11-5 V 0.2, 2005-01 XC866 Timers 11.1.2.4 Mode 3 In mode 3, Timer 0 and Timer 1 behave differently. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1 = 0. The logic for mode 3 operation for Timer 0 is shown in Figure 11-4. TL0 uses the Timer 0 control bits GATE0, TR0 and TF0, while TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now sets TF1 upon overflow and generates an interrupt if ET1 is set. Mode 3 is provided for applications requiring an extra 8-bit timer. When Timer 0 is in mode 3 and TR1 is set, Timer 1 can be turned on by switching it to any of the other modes and turned off by switching it into mode 3. fPCLK/2 Timer Clock TL0 (8 Bits) TF0 Interrupt Control TR0 =1 >1 & GATE0 EXINT0 TH0 (8 Bits) TF1 Interrupt TR1 Timer0_Mode3 Figure 11-4 Timer 0, Mode 3: Two 8-bit Timers User’s Manual Timers, V 0.4 11-6 V 0.2, 2005-01 XC866 Timers 11.1.3 Register Map Seven SFRs control the operations of Timer 0 and Timer 1. They can be accessed from both the standard (non-mapped) and mapped SFR area. Table 11-2 lists the addresses of these SFRs. Table 11-2 Address 88H 89H 8AH 8BH 8CH 8DH SFR Address List Register TCON TMOD TL0 TL1 TH0 TH1 User’s Manual Timers, V 0.4 11-7 V 0.2, 2005-01 XC866 Timers 11.1.4 Register Description The low and high bytes of both Timer 0 and Timer 1 can be combined to a one-timer configuration depending on the mode used. TLx (x = 0 - 1) Timer x Register Low 7 6 5 4 VAL rwh 3 2 Reset Value: 00H 1 0 THx (x = 0 - 1) Timer x Register High 7 6 5 4 VAL rwh 3 2 Reset Value: 00H 1 0 Field TLx.VAL (x = 0 - 1) Bits [7:0] Type Description rwh Timer 0/1 Low Register Operating Description Mode 0 1 2 3 “TLx” holds the 5-bit prescaler value. “TLx” holds the lower 8-bit part of the 16-bit timer value. “TLx” holds the 8-bit timer value. TL0 holds the 8-bit timer value; TL1 is not used. User’s Manual Timers, V 0.4 11-8 V 0.2, 2005-01 XC866 Timers Field THx.VAL (x = 0 - 1) Bits [7:0] Type Description rwh Timer 0/1 High Register Operating Mode 0 1 2 3 Description “THx” holds the 8-bit timer value. “THx” holds the higher 8-bit part of the 16-bit timer value. “THx” holds the 8-bit reload value. TH0 holds the 8-bit timer value; TH1 is not used. User’s Manual Timers, V 0.4 11-9 V 0.2, 2005-01 XC866 Timers Register TCON controls the operations of Timer 0 and Timer 1. TCON Timer Control Register 7 TF1 rw 6 TR1 rw 5 TF0 rw 4 TR0 rw 3 IE1 rw 2 IT1 rw Reset Value: 00H 1 IE0 rw 0 IT0 rw The functions of the shaded bits are not described here Field TR0 Bits 4 Type Description rw Timer 0 Run Control 0 Timer is halted 1 Timer runs Timer 0 Overflow Flag Set by hardware when Timer 0 overflows. Cleared by hardware when the processor calls the interrupt service routine. Timer 1 Run Control1) 0 Timer is halted 1 Timer runs Timer 1 Overflow Flag Set by hardware when Timer 12) overflows. Cleared by hardware when the processor calls the interrupt service routine. TF0 5 rw TR1 6 rw TF1 7 rw 1) 2) Also affects TH0 if Timer 0 operates in mode 3. TF1 is set by TH0 instead if Timer 0 operates in mode 3. User’s Manual Timers, V 0.4 11-10 V 0.2, 2005-01 XC866 Timers Register TMOD contains bits that select the operating modes of Timer 0 and Timer 1. TMOD Timer Mode Register 7 GATE1 rw 6 0 r 5 T1M rw 4 3 GATE0 rw 2 0 r Reset Value: 00H 1 T0M rw 0 Field T0M[1:0] T1M[1:0] Bits [1:0] [5:4] Type Description rw Mode select bits T0M/T1M [1:0] 00 01 10 11 Function 13-bit timer (M8048 compatible mode) 16-bit timer 8-bit auto-reload timer Timer 0: Timer 0 is divided into two parts. TL0 is an 8-bit timer controlled by the standard Timer 0 control bits, and TH0 is the other 8-bit timer controlled by the standard Timer 1 control bits. Timer 1: TL1 and TH1 are held (Timer 1 is stopped). GATE0 3 rw Timer 0 Gate Flag 0 Timer 0 will only run if TCON.TR0 = 1 (software control). 1 Timer 0 will only run if EXINT0 pin = 1 (hardware control) and TCON.TR0 is set. Timer 1 Gate Flag 0 Timer 1 will only run if TCON.TR1 = 1 (software control). 1 Timer 1 will only run if EXINT1 pin = 1 (hardware control) and TCON.TR1 is set. GATE1 7 rw User’s Manual Timers, V 0.4 11-11 V 0.2, 2005-01 XC866 Timers Field 0 Bits 2, 6 Type Description r Reserved Returns 0 if read; should be written with 0. Register IEN0 contains bits that enable interrupt operations in Timer 0 and Timer 1. IEN0 Interrupt Enable Register 7 EA rw 6 0 r 5 ET2 rw 4 ES rw 3 ET1 rw 2 EX1 rw Reset Value: 00H 1 ET0 rw 0 EX0 rw The functions of the shaded bits are not described here Field ET0 Bits 1 Type Description rw Timer 0 Overflow Interrupt Enable 0 Timer 0 interrupt is disabled. 1 Timer 0 interrupt is enabled. Timer 1 Overflow Interrupt Enable1) 0 Timer 1 interrupt is disabled. 1 Timer 1 interrupt is enabled. ET1 3 rw 1) When Timer 0 operates in mode 3, this interrupt indicates an overflow in the Timer 0 register, TH0. User’s Manual Timers, V 0.4 11-12 V 0.2, 2005-01 XC866 Timer 11.2 Timer 2 Timer 2 is a 16-bit general purpose timer that has two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is disabled, Timer 2 counts with an input clock of PCLK/12. 11.2.1 Auto-Reload Mode The auto-reload mode is selected when the bit CP/RL2 in register T2CON is zero. In this mode, Timer 2 counts to an overflow value and then reloads its register contents with a 16-bit start value for a fresh counting sequence. The overflow condition is indicated by setting bit TF2 in the T2CON register. This will then generate an interrupt request to the core. The overflow flag TF2 must be cleared by software. The auto-reload mode is further classified into two categories depending upon the DCEN control bit in register T2MOD. 11.2.1.1 Up/Down Count Disabled If DCEN = 0, the up-down count selection is disabled. The timer, therefore, functions as a pure up counting timer only. The operational block diagram is shown in Figure 11-5. If the T2CON register bit EXEN2 = 0, the timer starts to count up to a maximum of FFFFH once the timer is started by setting the bit TR2 in register T2CON to 1. Upon overflow, bit TF2 is set and the timer register is reloaded with the 16-bit reload value of the RC2 register. This reload value is chosen by software, prior to the occurrence of an overflow condition. A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence. If EXEN2 = 1, the timer counts up to a maximum of FFFFH once TR2 is set. A 16-bit reload of the timer registers from register RC2 is triggered either by an overflow condition or by a negative/positive edge (chosen by the bit EDGESEL in register T2MOD) at input pin T2EX. If an overflow caused the reload, the overflow flag TF2 is set. If a negative/ positive transition at pin T2EX caused the reload, bit EXF2 in register T2CON is set. In either case, an interrupt is generated to the core and the timer proceeds to its next count sequence. The EXF2 flag, similar to the TF2, must be cleared by software. Note: When T2EX is used for the Timer 2 function, the bit BCON.T2EXIS must be set. User’s Manual Timer, V 0.4 11-13 V 0.2, 2005-01 XC866 Timer PREN f PCLK prescaler ( ÷12) THL2 TR2 Overflow OR RC2 TF2 Timer 2 OR Interrupt EXF2 EXEN2 T2EX Figure 11-5 Auto-Reload Mode (DCEN = 0) 11.2.1.2 Up/Down Count Enabled If DCEN = 1, the up-down count selection is enabled. The direction of count is determined by the level at input pin T2EX. The operational block diagram is shown in Figure 11-6. A logic 1 at pin T2EX sets the Timer 2 to up counting mode. The timer, therefore, counts up to a maximum of FFFFH. Upon overflow, bit TF2 is set and the timer register is reloaded with a 16-bit reload value of the RC2 register. A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence. This reload value is chosen by software, prior to the occurrence of an overflow condition. A logic 0 at pin T2EX sets the Timer 2 to down counting mode. The timer counts down and underflows when the THL2 value reaches the value stored at register RC2. The underflow condition sets the TF2 flag and causes FFFFH to be reloaded into the THL2 User’s Manual Timer, V 0.4 11-14 V 0.2, 2005-01 XC866 Timer register. A fresh down counting sequence is started and the timer counts down as in the previous counting sequence. In this mode, bit EXF2 toggles whenever an overflow or an underflow condition is detected. This flag, however, does not generate an interrupt request. FFFF H (Down count reload) EXF2 Underflow PREN fP CLK prescaler ( ÷12) Timer 2 THL2 OR TF2 Interrupt TR2 16-bit Comparator Overflow RC2 T2EX Figure 11-6 Auto-Reload Mode (DCEN = 1) User’s Manual Timer, V 0.4 11-15 V 0.2, 2005-01 XC866 Timer 11.2.2 Capture Mode In order to enter the 16-bit capture mode, bits CP/RL2 and EXEN2 in register T2CON must be set. In this mode, the down count function must remain disabled. The timer functions as a 16-bit timer and always counts up to FFFFH, after which, an overflow condition occurs. Upon overflow, bit TF2 is set and the timer reloads its registers with 0000H. The setting of TF2 generates an interrupt request to the core. Additionally, with a falling/rising edge (chosen by T2MOD.EDGESEL) on pin T2EX, the contents of the timer register (THL2) are captured into the RC2 register. If the capture signal is detected while the counter is being incremented, the counter is first incremented before the capture operation is performed. This ensures that the latest value of the timer register is always captured. When the capture operation is completed, bit EXF2 is set and can be used to generate an interrupt request. Figure 11-7 describes the capture function of Timer 2. PB_CLK ÷ 12 TR2 THL2 Overflow RC2 TF2 Timer 2 OR Interrupt EXF2 EXEN2 T2EX Figure 11-7 Capture Mode User’s Manual Timer, V 0.4 11-16 V 0.2, 2005-01 XC866 Timer 11.2.3 Register Map All Timer 2 register names described in the following sections will be referenced in other chapters of this document with the module name prefix “T2_”, e.g., T2_T2CON. The Timer 2 SFRs are located in the standard (non-mapped) SFR area. Table 11-3 lists the addresses of these SFRs. Table 11-3 Address C0H C1H C2H C3H C4H C5H SFR Address List Register T2CON T2MOD RC2L RC2H T2L T2H 11.2.4 Register Description Register T2MOD is used to configure Timer 2 for the various modes of operation. T2MOD Timer 2 Mode Register 7 0 r 6 5 EDGESEL rw 4 PREN rw 3 2 T2PRE rw Reset Value: 00H 1 0 DCEN rw Field DCEN Bits 0 Type Description rw Up/Down Counter Enable 0 Up/Down Counter function is disabled. 1 Up/Down Counter function is enabled and controlled by pin T2EX (Up = 1, Down = 0). User’s Manual Timer, V 0.4 11-17 V 0.2, 2005-01 XC866 Timer Field T2PRE Bits [3:1] Type Description rw Timer 2 Prescaler Bit Selects the input clock for Timer 2 which is derived from the peripheral clock. 000 fT2 = fPCLK 001 fT2 = fPCLK/2 010 fT2 = fPCLK/4 011 fT2 = fPCLK/8 100 fT2 = fPCLK/16 Others: reserved Prescaler Enable 0 Prescaler is disabled and the 2/12 divider takes effect. 1 Prescaler is enabled (see T2PRE bit) and the 2/12 divider is bypassed. Edge Select in Capture Mode/Reload Mode 0 The falling edge at pin T2EX is selected. 1 The rising edge at pin T2EX is selected. Reserved Returns 0 if read; should be written with 0. PREN 4 rw EDGESEL 5 rw 0 [7:6] r User’s Manual Timer, V 0.4 11-18 V 0.2, 2005-01 XC866 Timer Register T2CON controls the operating modes of Timer 2. In addition, it contains the status flags for interrupt generation. T2CON Timer 2 Control Register 7 TF2 rwh 6 EXF2 rwh 5 0 r 4 3 EXEN2 rw 2 TR2 rwh Reset Value: 00H 1 0 r 0 CP/RL2 rw Field CP/RL2 Bits 0 Type Description rw Capture/Reload Select 0 Reload upon overflow or upon negative/ positive transition at pin T2EX (when EXEN2 = 1). 1 Capture Timer 2 data register contents on the negative/positive transition at pin T2EX, provided EXEN2 = 1. The negative or positive transition at pin T2EX is selected by bit EDGESEL. Timer 2 Start/Stop Control 0 Stop Timer 2 1 Start Timer 2 Timer 2 External Enable Control 0 External events are disabled. 1 External events are enabled in capture/ reload mode. Timer 2 External Flag In capture/reload mode, this bit is set by hardware when a negative/positive transition occurs at pin T2EX, if bit EXEN2 = 1. An interrupt request to the core is generated, unless bit DCEN = 1. This bit must be cleared by software. Timer 2 Overflow/Underflow Flag Set by a Timer 2 overflow/underflow. Must be cleared by software. Reserved Returns 0 if read; should be written with 0. TR2 2 rwh EXEN2 3 rw EXF2 6 rwh TF2 7 rwh 0 1, [5:4] r User’s Manual Timer, V 0.4 11-19 V 0.2, 2005-01 XC866 Timer Register RC2 is used for a 16-bit reload of the timer count upon overflow or a capture of current timer count depending on the mode selected. RC2L Timer 2 Reload/Capture Register Low 7 6 5 4 RC2L rwh 3 2 Reset Value: 00H 1 0 RC2H Timer 2 Reload/Capture Register High 7 6 5 4 RC2H rwh 3 2 Reset Value: 00H 1 0 Field RC2 Bits Type Description Reload/Capture Value If CP/RL2 = 0, these contents are loaded into the timer register upon an overflow condition. If CP/RL2 = 1, this register is loaded with the current timer count upon a negative/positive transition at pin T2EX when EXEN2 = 1. [7:0] of rwh RC2L, [7:0] of RC2H User’s Manual Timer, V 0.4 11-20 V 0.2, 2005-01 XC866 Timer Register T2 holds the current 16-bit value of the Timer 2 count. T2L Timer 2 Register Low 7 6 5 4 THL2 rwh 3 2 Reset Value: 00H 1 0 T2H Timer 2 Register High 7 6 5 4 THL2 rwh 3 2 Reset Value: 00H 1 0 Field THL2 Bits Type Description Timer 2 Value These bits indicate the current timer value. [7:0] of rwh T2L, [7:0] of T2H User’s Manual Timer, V 0.4 11-21 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12 Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and multi-phase machines. The block diagram of the CCU6 module is shown in Figure 12-1. The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only. The multi-channel control unit generates output patterns, which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. Timer T12 Features: • Three capture/compare channels, each channel can be used either as a capture or as a compare channel • Supports generation of a three-phase PWM (six outputs, individual signals for highside and lowside switches) • 16-bit resolution, maximum count frequency = peripheral clock frequency • Dead-time control for each channel to avoid short-circuits in the power stage • Concurrent update of the required T12/13 registers • Generation of center-aligned and edge-aligned PWM • Supports single-shot mode • Supports many interrupt request sources • Hysteresis-like control mode Timer T13 Features: • • • • • One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock frequency Can be synchronized to T12 Interrupt generation at period-match and compare-match Supports single-shot mode Additional Features: • • • • • • • Implements block commutation for Brushless DC-drives Position detection via Hall-sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage User’s Manual CCU6, V 0.4 12-1 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 module kernel address decoder channel 0 T12 channel 1 channel 2 start compare compare capture compare 1 1 deadtime control multichannel control trap control output select output select 3 clock control 1 T13 interrupt control channel 3 compare 1 3 2 2 2 trap input 1 input / output control CCPOS0 CCPOS1 CCPOS2 COUT63 COUT60 COUT61 COUT62 Hall input compare port control CCU6_block_diagram Figure 12-1 CCU6 Block Diagram User’s Manual CCU6, V 0.4 12-2 V 0.2, 2005-01 CTRAP T12HR T13HR CC60 CC61 CC62 XC866 Capture/Compare Unit 6 12.1 12.1.1 Functional Description Timer T12 The timer T12 is built with three channels in capture/compare mode. The input clock for timer T12 can be from fCCU6 to a maximum of fCCU6/128 and is configured by bit field T12CLK. In order to support higher clock frequencies, an additional prescaler factor of 1/256 can be enabled for the prescaler of T12 if bit T12PRE = 1. The timer period, compare values, passive state selects bits and passive levels bits are written to shadow registers and not directly to the actual registers, while the read access targets the registers actually used (except for the three compare channels, where both the actual and the shadow registers can be read). The transfer from the shadow registers to the actual registers is enabled by setting the shadow transfer enable bit STE12. If this transfer is enabled, the shadow registers are copied to the respective registers as soon as the associated timer reaches the value zero the next time (being cleared in edge-aligned mode or counting down to 1 in center-aligned mode). When timer T12 is operating in center-aligned mode, it will also copy the registers (if enabled by STE12) if it reaches the currently programmed period value (counting up). When timer T12 is stopped, the shadow transfer takes place immediately if the corresponding bit STE12 is set. Once the transfer is complete, the respective bit STE12 is cleared automatically. Figure 12-2 shows an overview of Timer T12. =1? =0? =? 16 one-match zero-match period-match T12PR compare-match 16 T12PS period shadow transfer compare shadow transfer CC6xSR capture events according to bitfield MSEL6x =? CC6xR 16 counter register T12 T12clk CCU6_T12_overv Figure 12-2 T12 Overview User’s Manual CCU6, V 0.4 12-3 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.1.1 Timer Configuration Register T12 represents the counting value of timer T12. It can be written only while timer T12 is stopped. Write actions while T12 is running are not taken into account. Register T12 can always be read by software. In edge-aligned mode, T12 only counts up, whereas in center-aligned mode, T12 can count up and down. Timer T12 can be started and stopped by using bit T12R by hardware or software. • Bit field T12RSEL defines the event on pin T12HR: rising edge, falling edge, or either of these two edges, that can set the run bit T12R by hardware. • If bit field T12RSEL = 00B, the external setting of T12R is disabled and the timer run bit can only be controlled by software. Bit T12R is set/reset by software by setting bit T12RR or T12RS. • In single-shot mode, bit T12R is reset by hardware according to the function defined by bit T12SSC. If bit T12SSC = 1, the bit T12R is reset by hardware when: – T12 reaches its period value in edge-aligned mode – T12 reaches the value 1 while counting down in center-aligned mode Register T12 can be reset to zero by setting bit T12RES. Setting of T12RES has no impact on run bit T12R. 12.1.1.2 Counting Rules With reference to the T12 input clock, the counting sequence is defined by the following counting rules: T12 in edge-aligned mode (Bit CTM = 0): The count direction is set to counting up (CDIR = 0). The counter is reset to zero if a period-match is detected, and the T12 shadow register transfer takes place if STE12 = 1. T12 in center-aligned mode (Bit CTM = 1): • The count direction is set to counting up (CDIR = 0) if a one-match is detected while counting down. • The count direction is set to counting down (CDIR = 1) if a period-match is detected while counting up. • If STE12 = 1, shadow transfer takes place when: – a period-match is detected while counting up – a one-match is detected while counting down The timer T12 prescaler is reset when T12 is not running to ensure reproducible timings and delays. 12.1.1.3 Switching Rules Compare actions take place in parallel for the three compare channels. Depending on the count direction, the compare matches have different meanings. In order to get the User’s Manual CCU6, V 0.4 12-4 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 PWM information independent of the output levels, two different states have been introduced for the compare actions: the active state and the passive state. Both these states are used to generate the desired PWM as a combination of the control by T13, the trap control unit and the multi-channel control unit. If the active state is interpreted as a 1 and the passive state as a 0, the state information is combined with a logical AND function. • • • active AND active = active active AND passive = passive passive AND passive = passive The compare states change with the detected compare-matches and are indicated by the CC6xST bits. The compare states of T12 are defined as follows: • passive if the counter value is below the compare value • active if the counter value is above the compare value This leads to the following switching rules for the compare states: • set to the active state when the counter value reaches the compare value counting up • reset to the passive state when the counter value reaches the compare value counting down • reset to the passive state in case of a zero-match without compare-match counting up • set to the active state in case of a zero-match with a parallel compare-match counting up while while while while T12clk compare-match 2 1 0 active passive compare state CCU6_T12_center_cm2 2 1 T12 Figure 12-3 Compared States for Compare Value = 2 The switching rules are considered only while the timer is running. As a result, write actions to the timer registers while the timer is stopped do not lead to compare actions. User’s Manual CCU6, V 0.4 12-5 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.1.4 Compare Mode of T12 In compare mode, the registers CC6xR (x = 0 - 2) are the actual compare registers for T12. The values stored in CC6xR are compared (all three channels in parallel) to the counter value of T12. The register CC6xR can only be read by software and the modification of the value is done by a shadow register transfer from register CC6xSR. Register T12PR contains the period value for timer T12. The period value is compared to the actual counter value of T12 and the resulting counter actions depend on the defined counting rules. Figure 12-4 shows an example in the center-aligned mode without dead-time. The bit CC6xST indicates the occurrence of a capture or compare event of the corresponding channel. It can be set (if it is 0) by the following events: • a software set (MCC6xS) • a compare set event (T12 counter value above the compare value) if the T12 runs and if the T12 set event is enabled • upon a capture set event The bit CC6xST can be reset (if it is 1) by the following events: • a software reset (MCC6xR) • a compare reset event (T12 counter value below the compare value) if the T12 runs and if the T12 reset event is enabled (including in single-shot mode at the end of the T12 period) • a reset event in the hysteresis-like control mode The bit CC6xPS represents passive state select bit. The timer T12’s two output lines (CC6x, COUT6x) can be selected to be in the passive state while CC6xST is 0 (with CC6xPS = 0) or while CC6xST is 1 (with CC6xPS = 1). The output level that is driven while the output is in the passive state is defined by the corresponding bit in bit field PSL. Hardware modifications of the compare state bits are only possible while timer T12 is running. Therefore, the bit T12R can be used to enable/disable the modification by hardware. User’s Manual CCU6, V 0.4 12-6 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 period value compare value T12 0 CC6xST Pin CC6x (CC6xPS=0, PSL=0) Pin COUT6x (COUT6xPS=1, PSL=0) passive active passive active passive active CCU6_T12_comp_states Figure 12-4 Compare States of Timer T12 For the hysteresis-like compare mode (MSEL6x = 1001B) (see Section 12.1.1.9), the setting of the compare state bit is possible only while the corresponding input CCPOSx = 1 (inactive). If the hall sensor mode (MSEL6x = 1000B) is selected (see Section 12.1.6), the compare state bits of the compare channels 1 and 2 are modified by the timer T12 in order to indicate that a programmed time interval has elapsed. The set is only generated when bit CC6xST is reset; a reset can only take place when the bit is set. Thus, the events triggering the set and reset actions of the CC6xST bit must be combined. This OR-combination of the resulting set and reset permits the reload of the dead-time counter to be triggered (see Figure 12-5). This is triggered only if bit CC6xST is changed, permitting a correct PWM generation with dead-time and the complete duty cycle range of 0% to 100% in edge-aligned and center-aligned modes. 12.1.1.5 Duty Cycle of 0% and 100% These counting and switching rules ensure a PWM functionality in the full range between 0% and 100% duty cycle (duty cycle = active time/total PWM period). In order to obtain a duty cycle of 0% (compare state never active), a compare value of T12P+1 must be programmed (for both compare modes). A compare value of 0 will lead to a duty cycle of 100% (compare state always active). User’s Manual CCU6, V 0.4 12-7 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.1.6 Dead-time Generation In most cases, the switching behavior of the connected power switches is not symmetrical with respect to the times needed to switch on and to switch off. A general problem arises if the time taken to switch on is less than the time to switch off the power device. This leads to a short-circuit in the inverter bridge leg, which may damage the entire system. In order to solve this problem by hardware, the CCU6 contains a programmable dead-time counter, which delays the passive to active edge of the switching signals (the active to passive edge is not delayed). T12 Center-aligned T12 Edge-aligned CC6xST CC6xST DTCx_o Pin CC6x (CC6xPS=0, PSL=0) Pin COUT6x (COUT6xPS=1, PSL=0) CC6xST AND DTCx_o CC6xST AND DTCx_o Figure 12-5 PWM-signals with Dead-time Generation Register T12DTC controls the dead-time generation for the timer T12 compare channels. Each channel can be independently enabled/disabled for dead-time generation by bit DTEx. If enabled, the transition from passive state to active state is delayed by the value defined by bit field DTM (8-bit down counter, clocked with T12CLK). The dead-time counter can only be reloaded when it is zero. Each of the three channels works independently with its own dead-time counter, trigger and enable signals. The value of bit field DTM is valid for all three channels. User’s Manual CCU6, V 0.4 12-8 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.1.7 Capture Mode In capture mode, the bits CC6xST indicate the occurrence of the selected capture event according to the bit fields MSEL6x. • MSEL6x = 01XXB, double register capture mode (see Table 12-5) • MSEL6x = 101XB or 11XXB, multi-input capture modes (see Table 12-7) A rising and/or a falling edge on the pins CC6x or CCPOSx can be selected as the capture event that is used to transfer the contents of timer T12 to the CC6xR and CC6xSR registers. In order to work in capture mode, the capture pins must be configured as inputs. There are several ways to store the captured values in the registers. For example, in double register capture mode, the timer value is stored in the channel shadow register CC6xSR. The value previously stored in this register is simultaneously copied to the channel register CC6xR. The software can then check the newly captured value while still preserving the possibility of reading the value captured earlier. Note: In capture mode, a shadow transfer can be requested according to the shadow transfer rules, except for the capture/compare registers that are left unchanged. 12.1.1.8 Single-Shot Mode The single-shot mode of timer T12 is selected when bit T12SSC is set to 1. In single-shot mode, the timer T12 stops automatically at the end of its counting period. Figure 12-6 shows the functionality at the end of the timer period in edge-aligned and center-aligned modes. If the end of period event is detected while bit T12SSC is set, the bit T12R and all CC6xST bits are reset. edge-aligned mode T12P T12P-1 T12P-2 2 0 1 T12 T12R CC6xST if T12SSC = '1' one-match while counting down 0 T12 T12R CC6xST CCU6_T12_singleshot center-aligned mode period-match while counting up if T12SSC = '1' Figure 12-6 End of Single-Shot Mode of T12 User’s Manual CCU6, V 0.4 12-9 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.1.9 Hysteresis-Like Control Mode The hysteresis-like control mode (MSEL6x = 1001B) offers the possibility of switching off the PWM output, if the input CCPOSx becomes 0, by resetting bit CC6xST. This can be used as a simple motor control feature by using a comparator to indicate, for example, over-current. While CCPOSx = 0, the PWM outputs of the corresponding channel are driving their passive levels. The setting of bit CC6xST is only possible while CCPOSx = 1. Figure 12-7 shows an example of hysteresis-like control mode. This mode can be used to introduce a timing-related behavior to a hysteresis controller. A standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result. Depending on the operating conditions, the switching frequency and the duty cycle may change constantly. Period value Compare value 0 Period value Compare value 0 Center-aligned mode CC6xST Pin CC6x (CC6xPS=0, PSL=0) Pin COUT6x (COUT6xPS=1 PSL=0) P in CCPOSx T12 Edge-aligned mode T12 Figure 12-7 Hysteresis-Like Control Mode User’s Manual CCU6, V 0.4 12-10 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.2 Timer T13 The timer T13 is similar to timer T12, except that it has only one channel in compare mode. The counter can only count up (similar to the edge-aligned mode of T12). The input clock for timer T13 can be from fCCU6 to a maximum of fCCU6/128 and is configured by bit field T13CLK. In order to support higher clock frequencies, an additional prescaler factor of 1/256 can be enabled for the prescaler of T13 if bit T13PRE = 1. The T13 shadow transfer, in case of a period-match, is enabled by bit STE13. During the T13 shadow transfer, the contents of register CC63SR are transferred to register CC63R. Both registers can be read by software, while only the shadow register can be written by software. The bits CC63PS, T13IM and PSL63 have shadow bits. The contents of these shadow bits are transferred to the actually used bits during the T13 shadow transfer. Write actions target the shadow bits, while read actions deliver the value of the actually used bits. =0? =? 16 zero-match period-match T13PR compare-match 16 T13PS T13 shadow transfer CC63SR =? CC63R counter register T13 16 T13clk CCU6_t13_overv Figure 12-8 T13 Overview Timer T13 counts according to the same counting and switching rules as timer T12 in edge-aligned mode. Figure 12-8 shows an overview of Timer T13. 12.1.2.1 Timer Configuration Register T13 represents the counting value of timer T13. It can be written only while the timer T13 is stopped. Write actions are not taken into account while T13 is running. Register T13 can always be read by software. Timer T13 supports only edge-aligned mode (counting up). Timer T13 can be started and stopped by using bit T13R by hardware or software. User’s Manual CCU6, V 0.4 12-11 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 • Bit T13R is set/reset by software by setting bit T13RR or T13RS. • In single-shot mode, if bit T13SSC = 1, the bit T13R is reset by hardware when T13 reaches its period value. • Bit fields T13TEC and T13TED select the trigger event that will set bit T13R for synchronization of different T12 compare events. The T13 counter register can be reset to zero by setting bit T13RES. Setting of T13RES has no impact on bit T13R. 12.1.2.2 Compare Mode Register CC63R is the actual compare register for T13. The value stored in CC63R is compared to the counter value of T13. The register CC63R can only be read by software and the modification of the value is done by a shadow register transfer from register CC63SR. The corresponding shadow register CC63SR can be read and written by software. Register T13PR contains the period value for timer T13. The period value is compared to the actual counter value of T13 and the resulting counter actions depend on the defined counting rules. The bit CC63ST indicates the occurrence of a compare event of the corresponding channel. It can be set (if it is 0) by the following events: • a software set (MCC63S) • a compare set event (T13 counter value above the compare value) if the T13 runs and if the T13 set event is enabled The bit CC63ST can be reset (if it is 1) by the following events: • a software reset (MCC63R) • a compare reset event (T13 counter value below the compare value) if the T13 runs and if the T13 reset event is enabled (including in single-shot mode at the end of the T13 period) Timer T13 is used to modulate the other output signals with a T13 PWM. In order to decouple COUT63 from the internal modulation, the compare state can be selected independently by bits T13IM and COUT63PS. 12.1.2.3 Single-Shot Mode The single-shot mode of timer T13 is selected when bit T13SSC is set to 1. In single-shot mode, the timer T13 stops automatically at the end of its counting period. If the end of period event is detected while bit T13SSC is set, the bit T13R and the bit CC63ST are reset. User’s Manual CCU6, V 0.4 12-12 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.2.4 Synchronization of T13 to T12 The timer T13 can be synchronized on a T12 event. The events include: • • • • • • • a T12 compare event on channel 0 a T12 compare event on channel 1 a T12 compare event on channel 2 any T12 compare event on channel 0, 1, or 2 a period-match of T12 a zero-match of T12 (while counting up) any edge of inputs CCPOSx The bit fields T13TEC and T13TED select the event that is used to start timer T13. This event sets bit T13R by hardware and T13 starts counting. Combined with the single-shot mode, this can be used to generate a programmable delay after a T12 event. 5 compare-match while counting up T12 0 2 T13 T13R CCU6_T13_sync 4 3 2 1 1 0 Figure 12-9 Synchronization of T13 to T12 Figure 12-9 shows the synchronization of T13 to a T12 event. The selected event in this example is a compare-match (compare value = 2) while counting up. The clocks of T12 and T13 can be different (use other prescaler factor), but in this example T12CLK is shown as equal to T13CLK for the sake of simplicity. 12.1.3 Modulation Control The modulation control part combines the different modulation sources (CC6x_T12_o and COUT6x_T12_o are the output signals that are configured with CC6xPS/ COUT6xPS; MOD_T13_o is the output signal after T13 Inverted Modulation (T13IM)). Each modulation source can be individually enabled per output line. Furthermore, the User’s Manual CCU6, V 0.4 12-13 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 trap functionality is taken into account to disable the modulation of the corresponding output line during the trap state (if enabled). OR T12MODENx CC6x_T12_o, COUT6x_T12_o T13MODENx MOD_T13_o MCMEN MCMPx O R 0 = passive state 1 = active state O R A N D O R 1 0 to output pin CC6x, COUT6x TRPENx TRPS A N D PSLx (1 x for each T12-related output) CCU6_mod_ctr Figure 12-10 Modulation Control of T12-related Outputs For each of the six T12-related output lines (represented by “x”) in the Figure 12-10: • • • • • T12MODENx enables the modulation by a PWM pattern generated by timer T12 T13MODENx enables the modulation by a PWM pattern generated by timer T13 MCMPx chooses the multi-channel patterns TRPENx enables the trap functionality PSLx defines the output level that is driven while the output is in the passive state As shown in Figure 12-11, the modulation control part for the T13-related output COUT63 combines the T13 output signal (COUT63_T13_o is the output signal that is configured by COUT63PS) and the enable bit ECT13O with the trap functionality. The output level of the passive state is selected by bit PSL63. User’s Manual CCU6, V 0.4 12-14 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 ECT13O COUT63_T13_o TRPEN13 TRPS A N D A N D 0 = passive state 1 = active state 1 0 A N D to output pin COUT63 PSL63 CCU6_T13_mod_ctr Figure 12-11 Modulation Control of the T13-related Output COUT63 Figure 12-12 shows a modulation control example for CC60 and COUT60. T13 CC60 (MCMP0, no modulation) COUT60 (MCMP1, no modulation) CC60 (T12, no modulation) COUT60 (T12, no modulation) CC60 (MCMP0 modulated with T12) COUT60 (MCMP1 modulated with T12) CC60 (MCMP0 modulated with T12 and 13) COUT60 (MCMP1 modulated with T12 and T13) Figure 12-12 Modulation Control Example for CC60 and COUT60 User’s Manual CCU6, V 0.4 12-15 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.4 Trap Handling The trap functionality permits the PWM outputs to react to the state of the input pin CTRAP. This functionality can be used to switch off the power devices if the trap input becomes active (e.g., as emergency stop). During the trap state, the selected outputs are forced into the passive state and no active modulation is possible. The trap state is entered immediately by hardware if the CTRAP input signal becomes active and the trap function is enabled by bit TRPPEN. It can also be entered by software by setting bit TRPF (trap input flag), thus leading to TRPS = 1 (trap state indication flag). The trap state can be left when the input is inactive by software control and synchronized to the following events: • TRPF is automatically reset after CTRAP becomes inactive (if TRPM2 = 0) • TRPF must be reset by software after CTRAP becomes inactive (if TRPM2 = 1) • synchronized to T12 PWM after TRPF is reset (T12 period-match in edge-aligned mode or one-match while counting down in center-aligned mode) • synchronized to T13 PWM after TRPF is reset (T13 period-match) • no synchronization to T12 or T13 T12 T13 TRPF TRPS TRPS TRPS CTRAP active sync. to T13 sync. to T12 no sync. CCU6_trap_sync Figure 12-13 Trap State Synchronization (with TRM2 = 0) User’s Manual CCU6, V 0.4 12-16 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.5 Multi-Channel Mode The multi-channel mode offers the possibility of modulating all six T12-related outputs. The bits in bit field MCMP are used to select the outputs that may become active. If the multi-channel mode is enabled (bit MCMEN = 1), only those outputs that have a 1 at the corresponding bit positions in bit field MCMP may become active. This bit field has its own shadow bit field MCMPS, which can be written by software. The transfer of the new value in MCMPS to the bit field MCMP can be triggered by and synchronized to T12 or T13 events. This structure permits the software to write the new value, which is then taken into account by the hardware at a well-defined moment and synchronized to a PWM period. This avoids unintended pulses due to unsynchronized modulation sources (T12, T13, SW). SW SEL Correct Hall Event T13pm T12pm T12om T12c1cm no action T12zm write to bitfield MCMPS with STRMCM = '1' T13zm direct set write by software 6 reset MCMPS O R A N D O R set R MCMP 6 clear to modulation selection shadow transfer interrupt SW SYN STR IDLE CCU6_mod_sync_int Figure 12-14 Modulation Selection and Synchronization Figure 12-14 shows the modulation selection for the multi-channel mode. The event that triggers the update of bit field MCMP is chosen by SWSEL. If the selected switching event occurs, the reminder flag R is set. This flag monitors the update request and it is automatically reset when the update takes place. In order to synchronize the update of MCMP to a PWM generated by T12 or T13, bit field SWSYN allows the selection of the User’s Manual CCU6, V 0.4 12-17 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 synchronization event, which leads to the transfer from MCMPS to MCMP. Due to this structure, an update takes place with a new PWM period. The update can also be requested by software by writing to bit field MCMPS with the shadow transfer request bit STRMCM set. If this bit is set during the write action to the register, the flag R is automatically set. By using this, the update takes place completely under software control. A shadow transfer interrupt can be generated when the shadow transfer takes place. The possible hardware request events are: • • • • • a T12 period-match while counting up (T12pm) a T12 one-match while counting down (T12om) a T13 period-match (T13pm) a T12 compare-match of channel 1 (T12c1cm) a correct Hall event The possible hardware synchronization events are: • a T12 zero-match while counting up (T12zm) • a T13 zero-match (T13zm) User’s Manual CCU6, V 0.4 12-18 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.6 Hall Sensor Mode In Brushless-DC motors, the next multi-channel state values depend on the pattern of the Hall inputs. There is a strong correlation between the Hall pattern (CURH) and the modulation pattern (MCMP). Because of different machine types, the modulation pattern for driving the motor can vary. Therefore, it is beneficial to have wide flexibility in defining the correlation between the Hall pattern and the corresponding modulation pattern. The CCU6 offers this by having a register which contains the actual Hall pattern (CURHS), the next expected Hall pattern (EXPHS), and its output pattern (MCMPS). At every correct Hall event, a new Hall pattern with its corresponding output pattern can be loaded (from a predefined table) by software into the register MCMOUTS. This shadow register can also be loaded by a write action on MCMOUTS with bit STRHP = 1. In case of a phase delay (generated by T12 channel 1), a new pattern can be loaded when the multi-channel mode shadow transfer (indicated by bit STR) occurs. 12.1.6.1 Sampling of the Hall Pattern The Hall pattern (on CCPOSx) is sampled with the module clock fCCU6. By using the dead-time counter DTC0 (mode MSEL6x = 1000B), a hardware noise filter can be implemented to suppress spikes on the Hall inputs. In case of a Hall event, the DTC0 is reloaded, and it starts counting and generates a delay between the detected event and the sampling point. After the counter value of 1 is reached, the CCPOSx inputs are sampled (without noise and spikes) and are compared to the current Hall pattern (CURH) and to the expected Hall pattern (EXPH). If the sampled pattern equals to the current pattern, it means that the edge on CCPOSx was due to a noise spike and no action will be triggered (implicit noise filter by delay). If the sampled pattern equals to the next expected pattern, the edge on CCPOSx was a correct Hall event, and the bit CHE is set which causes an interrupt. If it is required that the multi-channel mode and the Hall pattern comparison work independently of timer T12, the delay generation by DTC0 can be bypassed. In this case, timer T12 can be used for other purposes. Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields. The hall compare action can also be triggered by software by writing a 1 to bit SWHC. The triggering sources for the sampling by hardware include: • • • • • • • Any edge at one of the inputs CCPOSx (x = 0 - 2) A T13 compare-match A T13 period-match A T12 period-match (while counting up) A T12 one-match (while counting down) A T12 compare-match of channel 0 (while counting up) A T12 compare-match of channel 0 (while counting down) User’s Manual CCU6, V 0.4 12-19 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 This correct Hall event can be used as a transfer request event for register MCMOUTS. The transfer from MCMOUTS to MCMOUT transfers the new CURH-pattern as well as the next EXPH-pattern. In case the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (wrong Hall event) is set, which can also cause an interrupt and set the IDLE mode to clear MCMP (modulation outputs are inactive). To restart from IDLE, the transfer request of MCMOUTS must be initiated by software (bit STRHP and bit fields SWSEL/SWSYN). 12.1.6.2 Brushless-DC Control For Brushless-DC motors, there is a special mode (MSEL6x = 1000B) which is triggered by a change of the Hall inputs (CCPOSx). In this case, T12’s channel 0 acts in capture function, channel 1 and 2 act in compare function (without output modulation), and the multi-channel-block is used to trigger the output switching together with a possible modulation of T13. After the detection of a valid Hall edge, the T12 count value is captured to channel 0 (representing the actual motor speed) and the T12 is reset. When the timer reaches the compare value in channel 1, the next multi-channel state is switched by triggering the shadow transfer of bit field MCMP (if enabled in bit field SWEN). This trigger event can be combined with several conditions which are necessary to implement noise filtering (correct Hall event) and to synchronize the next multi-channel state to the modulation sources (avoiding spikes on the output lines). This compare function of channel 1 can be used as a phase delay for the position input to the output switching which is necessary if a sensorless back-EMF technique is used instead of Hall sensors. The compare value in channel 2 can be used as a time-out trigger (interrupt) indicating that the motor’s destination speed is far below the desired value (which can be caused by an abnormal load change). In this mode, the modulation of T12 must be disabled (T12MODENx = 0). CC60 CC61 CC62 act. speed phase delay timeout capture event resets T12 CCPOS0 CCPOS1 CCPOS2 CC6x COUT6y 1 0 1 1 0 0 1 1 0 0 1 0 0 1 1 Ch1 compare for phase delay Ch0 gets captured value for act. speed Ch2 compare for timeout 0 0 1 Figure 12-15 Timer T12 Brushless-DC Mode (all MSEL6x = 1000B) User’s Manual CCU6, V 0.4 12-20 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Table 12-1 lists an example of block commutation in BLDC motor control. If the input signal combination CCPOS0-CCPOS2 changes its state, the outputs CC6x and COUT6x are set to their new states. Figure 12-16 shows the block commutation in rotate left mode and Figure 12-17 shows the block commutation in rotate right mode. These figures are derived directly from Table 12-1. Table 12-1 Mode Block Commutation Control Table CCPOS0CCPOS2 Inputs CCP CCP CCP CC60 OS0 OS1 OS2 Rotate left, 1 0° phase shift 1 1 0 0 0 Rotate right 1 1 1 0 0 0 Slow-down Idle1) 1) CC60 - CC62 Outputs CC61 CC62 COUT60 - COUT62 Outputs COUT6 COUT6 COUT6 0 1 2 inactive active active inactive inactive inactive inactive inactive 0 0 1 1 1 0 1 0 0 0 1 1 X X 1 0 0 0 1 1 0 0 1 1 1 0 X X inactive inactive active inactive inactive active inactive active inactive active active active active active inactive active inactive inactive inactive active inactive inactive inactive inactive inactive inactive active inactive inactive inactive active inactive inactive inactive active inactive inactive inactive inactive active inactive inactive inactive active inactive active active inactive inactive inactive inactive inactive active active inactive active inactive active inactive inactive active inactive inactive active inactive active X X inactive inactive inactive active inactive inactive inactive inactive inactive inactive In case the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (Wrong Hall Event) is set, which can also cause an interrupt and set the IDLE mode to clear MCMP (modulation outputs are inactive). User’s Manual CCU6, V 0.4 12-21 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 CCPOS0 1 0 1 0 1 1 0 0 0 CCPOS1 1 1 0 CCPOS2 1 0 0 0 1 1 CC60 CC61 CC62 COUT60 COUT61 COUT62 Figure 12-16 Block Commutation in Rotate Left Mode CCPOS0 1 1 1 0 1 0 0 0 0 CCPOS1 0 1 1 CCPOS2 0 0 1 1 1 0 CC60 CC61 CC62 COUT60 COUT61 COUT62 Figure 12-17 Block Commutation in Rotate Right Mode User’s Manual CCU6, V 0.4 12-22 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.1.7 Interrupt Generation The interrupt generation can be triggered by the interrupt event or the setting of the corresponding interrupt bit in register IS by software. The interrupt is generated independently of the interrupt flag in register IS. Register IS can only be read; write actions have no impact on the contents of this register. The software can set or reset the bits individually by writing to register ISS or register ISR, respectively. If enabled by the related interrupt enable bit in register IEN, an interrupt will be generated. The interrupt sources of the CCU6 module can be mapped to four interrupt output lines by programming the interrupt node pointer register INP. 12.1.8 Port Connection Table 12-2 shows how bits and bit fields must be programmed for the required I/O functionality of the CCU6 I/O lines. This table also shows the values of the peripheral input select registers. Table 12-2 Port Lines P3.6/CTRAP_0 P2.2/CTRAP_1 P0.2/CTRAP_2 P2.0/CCPOS0_0 P1.5/CCPOS0_1 P2.1/CCPOS1_0 P1.6/CCPOS1_1 P2.2/CCPOS2_0 P1.7/CCPOS2_1 P3.0/CC60 CCU6 I/O Control Selection PISEL Register Bit ISTRP = 00B ISTRP = 01B ISTRP = 10B ISPOS0 = 00B ISPOS0 = 01B ISPOS1 = 00B ISPOS1 = 01B ISPOS2 = 00B ISPOS2 = 01B – – Input/Output Control Register Bits P3_DIR.P6 = 0B P2_DIR.P2 = 0B P0_DIR.P2 = 0B P2_DIR.P0 = 0B P1_DIR.P5 = 0B P2_DIR.P1 = 0B P1_DIR.P6 = 0B P2_DIR.P2 = 0B P1_DIR.P7 = 0B P3_DIR.P0 = 0B P3_DIR.P0 = 1B P3_ALTSEL0.P0 = 1B P3_ALTSEL1.P0 = 0B P3.1/COUT60 – P3_DIR.P1 = 1B P3_ALTSEL0.P1 = 1B P3_ALTSEL1.P1 = 0B Output I/O Input Input Input Input Input Input Input Input Input Input Output User’s Manual CCU6, V 0.4 12-23 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Table 12-2 Port Lines P3.2/CC61_0 CCU6 I/O Control Selection (cont’d) PISEL Register Bit ISCC61 = 00 – Input/Output Control Register Bits P3_DIR.P2 = 0B P3_DIR.P2 = 1B P3_ALTSEL0.P2 = 1B P3_ALTSEL1.P2 = 0B P0.0/CC61_1 ISCC61 = 01 – P0_DIR.P0 = 0B P0_DIR.P0 = 1B P0_ALTSEL0.P0 = 0B P0_ALTSEL1.P0 = 1B P3.3/COUT61_0 – P3_DIR.P3 = 1B P3_ALTSEL0.P3 = 1B P3_ALTSEL1.P3 = 0B P0.0/COUT61_1 – P0_DIR.P0 = 1B P0_ALTSEL0.P0 = 0B P0_ALTSEL1.P0 = 1B P3.4/CC62_0 ISCC62= 00 – P3_DIR.P4 = 0B P3_DIR.P4 = 1B P3_ALTSEL0.P4 = 1B P3_ALTSEL1.P4 = 0B P0.4/CC62_1 ISCC62 = 01 – P0_DIR.P4 = 0B P0_DIR.P4 = 1B P0_ALTSEL0.P4 = 0B P0_ALTSEL1.P4 = 1B P3.5/COUT62_0 – P3_DIR.P5 = 1B P3_ALTSEL0.P5 = 1B P3_ALTSEL1.P5 = 0B P0.5/COUT62_1 – P0_DIR.P5 = 1B P0_ALTSEL0.P5 = 0B P0_ALTSEL1.P5 = 1B Output Output Input Output Input Output Output Output Input Output I/O Input Output User’s Manual CCU6, V 0.4 12-24 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Table 12-2 Port Lines P3.7/COUT63_0 CCU6 I/O Control Selection (cont’d) PISEL Register Bit – Input/Output Control Register Bits P3_DIR.P7 = 1B P3_ALTSEL0.P7 = 1B P3_ALTSEL1.P7 = 0B P0.3/COUT63_1 – P0_DIR.P3 = 1B P0_ALTSEL0.P3 = 0B P0_ALTSEL1.P3 = 1B P1.6/T12HR_0 P0.0/T12HR_1 P2.0/T12HR_2 P1.7/T13HR_0 P0.1/T13HR_1 P2.1/T13HR_2 IST12HR = 00 IST12HR = 01 IST12HR = 10 IST13HR = 00 IST13HR = 01 IST13HR = 10 P1_DIR.P6 = 0B P0_DIR.P0 = 0B P2_DIR.P0 = 0B P1_DIR.P7 = 0B P0_DIR.P1 = 0B P2_DIR.P1 = 0B Input Input Input Input Input Input Output I/O Output User’s Manual CCU6, V 0.4 12-25 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.2 Register Map The CCU6 SFRs are located in the standard memory area (RMAP = 0) and are organized into 4 pages. The CCU6_PAGE register is located at address A3H. It contains the page value and the page control information. CCU6_PAGE Page Register for CCU6 7 OP w 6 5 STNR w 4 3 0 r 2 Reset Value: 00H 1 PAGE rw 0 Field PAGE Bits [2:0] Type Description rw Page Bits When written, the value indicates the new page address. When read, the value indicates the currently active page = addr [y:x+1]. Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. STNR [5:4] w User’s Manual CCU6, V 0.4 12-26 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field OP Bits [7:6] Type Description w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. Reserved Returns 0 if read; should be written with 0. 0 3 r User’s Manual CCU6, V 0.4 12-27 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 All CCU6 register names described in the following sections will be referenced in other chapters of this document with the module name prefix “CCU6_”, e.g., CCU6_CC63SRL. The addresses (non-mapped) of the CCU6 SFRs are listed in Table 12-3. Table 12-3 Address 9AH 9BH 9CH 9DH 9EH 9FH A4H A5H A6H A7H FAH FBH FCH FDH FEH FFH SFR Address List for Pages 0-3 Page 0 CC63SRL CC63SRH TCTR4L TCTR4H MCMOUTSL MCMOUTSH ISRL ISRH CMPMODIFL CMPMODIFH CC60SRL CC60SRH CC61SRL CC61SRH CC62SRL CC62SRH Page 1 CC63RL CC63RH T12PRL T12PRH T13PRL T13PRH T12DTCL T12DTCH TCTR0L TCTR0H CC60RL CC60RH CC61RL CC61RH CC62RL CC62RH Page 2 T12MSELL T12MSELH IENL IENH INPL INPH ISSL ISSH PSLR MCMCTR TCTR2L TCTR2H MODCTRL MODCTRH TRPCTRL TRPCTRH Page 3 MCMOUTL MCMOUTH ISL ISH PISEL0L PISEL0H PISEL2 – – – T12L T12H T13L T13H CMPSTATL CMPSTATH User’s Manual CCU6, V 0.4 12-28 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.3 Table 12-4 Register Description CCU6 Module Registers Register Full Name Description see Page 12-31 Page 12-33 Page 12-34 Page 12-35 Page 12-35 Page 12-36 Page 12-36 Page 12-37 Page 12-37 Table 12-4 shows all registers associated with the CCU6 module. Register Short Name PISEL0L PISEL0H PISEL2 T12 Registers T12L T12H T12PRL T12PRH CC6xRL CC6xRH CC6xSRL CC6xSRH T12DTCL T12DTCH T13 Registers T13L T13H T13PRL T13PRH CC63RL CC63RH Timer T13 Counter Register Low Timer T13 Counter Register High Timer T13 Period Register Low Timer T13 Period Register High Capture/Compare Register for Channel CC63 Low Capture/Compare Register for Channel CC63 High Page 12-41 Page 12-41 Page 12-42 Page 12-42 Page 12-43 Page 12-44 Timer T12 Counter Register Low Timer T12 Counter Register High Timer T12 Period Register Low Timer T12 Period Register High Capture/Compare Register for Channel CC6x Low Capture/Compare Register for Channel CC6x High System Registers Port Input Select Register 0 Low Port Input Select Register 0 High Port Input Select Register 2 Capture/Compare Shadow Register for Channel Page 12-38 CC6x Low Capture/Compare Shadow Register for Channel Page 12-38 CC6x High Dead-Time Control Register for Timer T12 Low Dead-Time Control Register for Timer T12 High Page 12-39 Page 12-39 User’s Manual CCU6, V 0.4 12-29 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Table 12-4 Register Short Name CC63SRL CC63SRH CCU6 Module Registers (cont’d) Register Full Name Description see Capture/Compare Shadow Register for Channel Page 12-44 CC63 Low Capture/Compare Shadow Register for Channel Page 12-44 CC63 High Compare State Register Low Compare State Register High Compare State Modification Register Low Compare State Modification Register High Timer Control Register 0 Low Timer Control Register 0 High Timer Control Register 2 Low Timer Control Register 2 High Timer Control Register 4 Low Timer Control Register 4 High Modulation Control Register Low Modulation Control Register High Trap Control Register Low Trap Control Register High Passive State Level Register Multi_Channel Mode Output Shadow Register Low Multi_Channel Mode Output Shadow Register High Multi_Channel Mode Output Register Low Multi_Channel Mode Output Register High Multi_Channel Mode Control Register T12 Capture/Compare Mode Select Register Low Page 12-45 Page 12-46 Page 12-47 Page 12-47 Page 12-48 Page 12-49 Page 12-52 Page 12-54 Page 12-55 Page 12-56 Page 12-57 Page 12-58 Page 12-60 Page 12-61 Page 12-63 Page 12-65 Page 12-66 Page 12-67 Page 12-69 Page 12-70 Page 12-72 CCU6 Control Registers CMPSTATL CMPSTATH CMPMODIFL CMPMODIFH TCTR0L TCTR0H TCTR2L TCTR2H TCTR4L TCTR4H MODCTRL MODCTRH TRPCTRL TRPCTRH PSLR MCMOUTSL MCMOUTSH MCMOUTL MCMOUTH MCMCTR T12MSELL Modulation Control Registers User’s Manual CCU6, V 0.4 12-30 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Table 12-4 Register Short Name T12MSELH CCU6 Module Registers (cont’d) Register Full Name T12 Capture/Compare Mode Select Register High Interrupt Status Register Low Interrupt Status Register High Interrupt Status Set Register Low Interrupt Status Set Register High Interrupt Status Reset Register Low Interrupt Status Reset Register High Interrupt Enable Register Low Interrupt Enable Register High Interrupt Node Pointer Register Low Interrupt Node Pointer Register High Description see Page 12-73 Interrupt Control Registers ISL ISH ISSL ISSH ISRL ISRH IENL IENH INPL INPH Page 12-77 Page 12-78 Page 12-80 Page 12-81 Page 12-82 Page 12-83 Page 12-84 Page 12-85 Page 12-88 Page 12-89 Note: For all CCU6 registers: the write-only bit positions (indicated by “w”) always deliver the value of 0 when they are read out. If a hardware and a software request to modify a bit occur simultaneously, the software wins. 12.3.1 System Registers 12.3.1.1 Port Input Selection Registers PISEL0 and PISEL2 contain bit fields that select the actual input signals for the module inputs. This permits the pin functionality of the device to be adapted as per the application’s requirements. The output pins are chosen according to the registers in the ports. PISEL0L Port Input Select Register 0 Low 7 ISTRP rw 6 5 ISCC62 rw 4 3 ISCC61 rw 2 Reset Value: 00H 1 ISCC60 rw 0 User’s Manual CCU6, V 0.4 12-31 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field ISCC60 Bits [1:0] Type Description rw Input Select for CC60 This bit field defines the port pin that is used for the CC60 capture input signal. 00 The input pin is selected for CC60_0. 01 Reserved 10 Reserved 11 Reserved Input Select for CC61 This bit field defines the port pin that is used for the CC61 capture input signal. 00 The input pin is selected for CC61_0. 01 The input pin is selected for CC61_1. 10 Reserved 11 Reserved Input Select for CC62 This bit field defines the port pin that is used for the CC62 capture input signal. 00 The input pin is selected for CC62_0. 01 The input pin is selected for CC62_1. 10 Reserved 11 Reserved Input Select for CTRAP This bit field defines the port pin that is used for the CTRAP input signal. 00 The input pin is selected for CTRAP_0. 01 The input pin is selected for CTRAP_1. 10 The input pin is selected for CTRAP_2. 11 Reserved ISCC61 [3:2] rw ISCC62 [5:4] rw ISTRP [7:6] rw User’s Manual CCU6, V 0.4 12-32 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 PISEL0H Port Input Select Register 0 High 7 IST12HR rw 6 5 ISPOS2 rw 4 3 ISPOS1 rw 2 Reset Value: 00H 1 ISPOS0 rw 0 Field ISPOS0 Bits [1:0] Type Description rw Input Select for CCPOS0 This bit field defines the port pin that is used for the CCPOS0 input signal. 00 The input pin is selected for CCPOS0_0. 01 The input pin is selected for CCPOS0_1. 10 Reserved 11 Reserved Input Select for CCPOS1 This bit field defines the port pin that is used for the CCPOS1 input signal. 00 The input pin is selected for CCPOS1_0. 01 The input pin is selected for CCPOS1_1. 10 Reserved 11 Reserved Input Select for CCPOS2 This bit field defines the port pin that is used for the CCPOS2 input signal. 00 The input pin is selected for CCPOS2_0. 01 The input pin is selected for CCPOS2_1. 10 Reserved 11 Reserved Input Select for T12HR This bit field defines the port pin that is used for the T12HR input signal. 00 The input pin is selected for T12HR _0. 01 The input pin is selected for T12HR_1. 10 The input pin is selected for T12HR_2. 11 Reserved ISPOS1 [3:2] rw ISPOS2 [5:4] rw IST12HR [7:6] rw User’s Manual CCU6, V 0.4 12-33 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 PISEL2 Port Input Select Register 2 7 6 5 0 r 4 3 2 Reset Value: 00H 1 IST13HR rw 0 Field IST13HR Bits [1:0] Type Description rw Input Select for T13HR This bit field defines the port pin that is used for the T13HR input signal. 00 The input pin is selected for T13HR_0. 01 The input pin is selected for T13HR_1. 10 The input pin is selected for T13HR_2. 11 Reserved Reserved Returns 0 if read; should be written with 0. 0 [7:2] r User’s Manual CCU6, V 0.4 12-34 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.3.2 Timer T12 – Related Registers The generation of the patterns for a 3-channel PWM is based on timer T12. The registers related to timer T12 can be concurrently updated (with well-defined conditions) in order to ensure consistency of the three PWM channels. Timer T12 supports capture and compare modes, which can be independently selected for its three channels CC60, CC61 and CC62. T12L Timer T12 Counter Register Low 7 6 5 4 T12CVL rwh 3 2 Reset Value: 00H 1 0 T12H Timer T12 Counter Register High 7 6 5 4 T12CVH rwh 3 2 Reset Value: 00H 1 0 Field T12CV Bits [7:0] of T12L, [7:0] of T12H Type Description rwh Timer T12 Counter Value This register represents the 16-bit counter value of timer T12. Note: Once timer T12 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays. User’s Manual CCU6, V 0.4 12-35 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 T12PRL Timer T12 Period Register Low 7 6 5 4 T12PVL rwh 3 2 Reset Value: 00H 1 0 T12PRH Timer T12 Period Register High 7 6 5 4 T12PVH rwh 3 2 Reset Value: 00H 1 0 Field T12PV Bits Type Description T12 Period Value The value T12PV defines the counter value for T12, which leads to a period-match. On reaching this value, the timer T12 is set to zero (edge-aligned mode) or changes its count direction to down counting (center-aligned mode). [7:0] of rwh T12PRL, [7:0] of T12PRH User’s Manual CCU6, V 0.4 12-36 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 CC6xRL (x = 0 - 2) Capture/Compare Register for Channel CC6x Low 7 6 5 4 3 2 Reset Value: 00H 1 0 CC6xVL (x = 0 - 2) rh CC6xRH (x = 0 - 2) Capture/Compare Register for Channel CC6x High 7 6 5 4 3 2 Reset Value: 00H 1 0 CC6xVH (x = 0 - 2) rh Field CC6xV (x = 0 - 2) Bits Type Description Channel x Capture/Compare Value In compare mode, the bit fields CC6xV contain the values that are compared to the T12 counter value. In capture mode, the captured value of T12 can be read from these registers. [7:0] of rh CC6xRL, [7:0] of CC6xRH User’s Manual CCU6, V 0.4 12-37 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 CC6xSRL (x = 0 - 2) Capture/Compare Shadow Register for Channel CC6x Low 7 6 5 4 3 2 Reset Value: 00H 1 0 CC6xSL (x = 0 - 2) rwh CC6xSRH (x = 0 - 2) Capture/Compare Shadow Register for Channel CC6x High 7 6 5 4 3 2 Reset Value: 00H 1 0 CC6xSH (x = 0 - 2) rwh Field CC6xS (x = 0 - 2) Bits Type Description Shadow Register for Channel x Capture/Compare Value In compare mode, the contents of bit fields CC6xS are transferred to the bit fields CC6xV during a shadow transfer. In capture mode, the captured value of T12 can be read from these registers. [7:0] of rwh CC6xSRL, [7:0] of CC6xSRH User’s Manual CCU6, V 0.4 12-38 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 T12DTCL Dead-Time Control Register for Timer T12 Low 7 6 5 4 DTM rw 3 2 Reset Value: 00H 1 0 Field DTM Bits [7:0] Type Description rw Dead-Time Bit field DTM determines the programmable delay between switching from the passive state to the active state of the selected outputs. The switching from the active state to the passive state is not delayed. T12DTCH Dead-Time Control Register for Timer T12 High 7 0 r 6 DTR2 rh 5 DTR1 rh 4 DTR0 rh 3 0 r 2 DTE2 rw Reset Value: 00H 1 DTE1 rw 0 DTE0 rw Field DTE0 DTE1 DTE2 Bits 0 1 2 Type Description rw Dead-Time Enable Bits Bits DTEx (x = 0 - 2) enable and disable the deadtime generation for each compare channel (0, 1, 2) of timer T12. 0 Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 1 Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM. User’s Manual CCU6, V 0.4 12-39 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field DTR0 DTR1 DTR2 Bits 4 5 6 Type Description rh Dead-Time Run Indication Bits Bits DTRx (x = 0 - 2) indicate the status of the deadtime generation for each compare channel (0, 1, 2) of timer T12. 0 The value of the corresponding dead-time counter channel is 0. 1 The value of the corresponding dead-time counter channel is not 0. Reserved Returns 0 if read; should be written with 0. 0 3, 7 r Note: The dead-time counters are clocked with the same frequency as T12. This structure allows symmetrical dead-time generation in center-aligned and in edge-aligned PWM mode. A duty cycle of 50% leads to CC6x; COUT6x is switched on for: 0.5 * period - dead-time. Note: The dead-time counters are not reset by bit T12RES, but by bit DTRES. User’s Manual CCU6, V 0.4 12-40 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.3.3 Timer T13 – Related Registers The generation of the patterns for a single-channel PWM is based on timer T13. The registers related to timer T13 can be concurrently updated (with well-defined conditions) in order to ensure consistency of the PWM signal. Timer T13 can be synchronized to several timer T12 events. Timer T13 supports only compare mode on its compare channel CC63. T13L Timer T13 Counter Register Low 7 6 5 4 T13CVL rwh 3 2 Reset Value: 00H 1 0 T13H Timer T13 Counter Register High 7 6 5 4 T13CVH rwh 3 2 Reset Value: 00H 1 0 Field T13CV Bits [7:0] of T13L, [7:0] of T13H Type Description rwh Timer T13 Counter Value This register represents the 16-bit counter value of timer T13. Note: Once timer T13 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays. User’s Manual CCU6, V 0.4 12-41 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 T13PRL Timer T13 Period Register Low 7 6 5 4 T13PVL rwh 3 2 Reset Value: 00H 1 0 T13PRH Timer T13 Period Register High 7 6 5 4 T13PVH rwh 3 2 Reset Value: 00H 1 0 Field T13PV Bits Type Description T13 Period Value The value T13PV defines the counter value for T13, which leads to a period-match. On reaching this value, the timer T13 is set to zero. [7:0] of rwh T13PRL, [7:0] of T13PRH User’s Manual CCU6, V 0.4 12-42 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 CC63RL Capture/Compare Register for Channel CC63 Low 7 6 5 4 CC63VL rh 3 2 Reset Value: 00H 1 0 CC63RH Capture/Compare Register for Channel CC63 High 7 6 5 4 CC63VH rh 3 2 Reset Value: 00H 1 0 Field CC63V Bits [7:0] of CC63RL, [7:0] of CC63RH Type Description rh Channel CC63 Compare Value The bit fields CC63V contain the values that are compared to the T13 counter value. User’s Manual CCU6, V 0.4 12-43 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 CC63SRL Capture/Compare Shadow Register for Channel CC63 Low 7 6 5 4 CC63SL rw 3 2 Reset Value: 00H 1 0 CC63SRH Capture/Compare Shadow Register for Channel CC63 High 7 6 5 4 CC63SH rw 3 2 Reset Value: 00H 1 0 Field CC63S Bits Type Description Shadow Register for Channel CC63 Compare Value The contents of bit fields CC63S are transferred to the bit fields CC63V during a shadow transfer. [7:0] of rw CC63SRL, [7:0] of CC63SRH User’s Manual CCU6, V 0.4 12-44 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.3.4 Capture/Compare Control Registers Register CMPSTAT contains status bits that monitor the current capture and compare state, and control bits that define the active/passive state of the compare channels. CMPSTATL Compare State Register Low 7 0 r 6 CC 63ST rh 5 CC POS 2 rh 4 CC POS 1 rh 3 CC POS 0 rh 2 CC 62ST rh Reset Value: 00H 1 CC 61ST rh 0 CC 60ST rh Field CC60ST CC61ST CC62ST CC63ST 1) Bits 0 1 2 6 Type Description rh Capture/Compare State Bits Bits CC6xST monitor the state of the capture/compare channels. Bits CC6xST (x = 0 - 2) are related to T12; bit CC63ST is related to T13. 0 In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not been detected since the bit was reset by software. 1 In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. Sampled Hall Pattern Bits Bits CCPSOx (x = 0 - 2) indicate the value of the input Hall pattern that has been compared to the current and expected value. The value is sampled when the event hcrdy (Hall compare ready) occurs. 0 The input CCPOSx has been sampled as 0. 1 The input CCPOSx has been sampled as 1. Reserved Returns 0 if read; should be written with 0. CCPOS0 CCPOS1 CCPOS2 3 4 5 rh 0 1) 7 r These bits are set and reset according to the T12 and T13 switching rules. User’s Manual CCU6, V 0.4 12-45 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 CMPSTATH Compare State Register High 7 T13 IM rwh 6 5 4 CC 62PS rwh 3 C OUT61PS rwh 2 CC 61PS rwh Reset Value: 00H 1 C OUT60PS rwh 0 CC 60PS rwh C C OUT63PS OUT62PS rwh rwh Field CC60PS CC61PS CC62PS COUT60PS COUT61PS COUT62PS COUT63PS 1) Bits 0 2 4 1 3 5 6 Type Description rwh Passive State Select for Compare Outputs Bits CC6xPS and COUT6xPS (x = 0 - 2) select the state of the corresponding compare channel, which is considered to be the passive state. During the passive state, the passive level (defined in register PSLR) is driven by the output pin. Bits CC6xPS and COUT6xPS are related to T12, while bit CC63PS is related to T13. 0 The corresponding compare output drives passive level while CC6xST is 0. 1 The corresponding compare output drives passive level while CC6xST is 1. In capture mode, these bits are not used. T13 Inverted Modulation Bit T13IM inverts the T13 signal for the modulation of the CC6x and COUT6x (x = 0 - 2) signals. 0 T13 output is not inverted. 1 T13 output is inverted for further modulation. T13IM2) 7 rwh 1) These bits have shadow bits and are updated in parallel to the capture/compare registers of T12 and T13, respectively. A read action targets the actually used values, whereas a write action targets the shadow bits. This bit has a shadow bit and is updated in parallel to the compare and period registers of T13. A read action targets the actually used values, whereas a write action targets the shadow bit. 2) User’s Manual CCU6, V 0.4 12-46 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register CMPMODIF contains control bits that allow modification by software of the capture/compare state bits. CMPMODIFL Compare State Modification Register Low 7 0 r 6 MCC 63S w 5 4 0 r 3 2 MCC 62S w Reset Value: 00H 1 MCC 61S w 0 MCC 60S w CMPMODIFH Compare State Modification Register High 7 0 r 6 MCC 63R w 5 4 0 r 3 2 MCC 62R w Reset Value: 00H 1 MCC 61R w 0 MCC 60R w Field MCC60S1) MCC61S1) MCC62S1) MCC63S1) MCC60R2) MCC61R2) MCC62R2) MCC63R2) Bits 0 1 2 6 0 1 2 6 Type Description w Capture/Compare Status Modification Bits These bits are used to set (MCC6xS) or reset (MCC6xR) the corresponding CC6xST bits by software. This feature allows the user to individually change the status of the output lines by software, e.g., when the corresponding compare timer is stopped. This enables a manipulation of CC6xST bits by a single data write action. MCC6xR, MCC6xS = 0,0 Bit CC6xST is not changed. 0,1 Bit CC6xST is set. 1,0 Bit CC6xST is reset. 1,1 Reserved (toggle) Reserved Returns 0 if read; should be written with 0. 0 1) 2) [5:3], r 7 This bit field is contained in the Compare State Modification Register Low. This bit field is contained in the Compare State Modification Register High. User’s Manual CCU6, V 0.4 12-47 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register TCTR0 controls the basic functionality of both timers T12 and T13. TCTR0L Timer Control Register 0 Low 7 CTM rw 6 CDIR rh 5 STE12 rh 4 T12R rh 3 T12 PRE rw 2 Reset Value: 00H 1 T12CLK rw 0 Field T12CLK Bits [2:0] Type Description rw Timer T12 Input Clock Select Selects the input clock for timer T12 which is derived from the peripheral clock according to the equation fT12 = fCCU6/2. 000 fT12 = fCCU6 001 fT12 = fCCU6/2 010 fT12 = fCCU6/4 011 fT12 = fCCU6/8 100 fT12 = fCCU6/16 101 fT12 = fCCU6/32 110 fT12 = fCCU6/64 111 fT12 = fCCU6/128 Timer T12 Prescaler Bit In order to support higher clock frequencies, an additional prescaler factor of 1/256 can be enabled for the prescaler for T12. 0 The additional prescaler for T12 is disabled. 1 The additional prescaler for T12 is enabled. Timer T12 Run Bit T12R starts and stops timer T12. It is set/reset by software by setting bit T12RR or T12RS, or it is reset by hardware according to the function defined by bit T12SSC. 0 Timer T12 is stopped. 1 Timer T12 is running. T12PRE 3 rw T12R1) 4 rh User’s Manual CCU6, V 0.4 12-48 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field STE12 Bits 5 Type Description rh Timer T12 Shadow Transfer Enable Bit STE12 enables or disables the shadow transfer of the T12 period value, the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected. Bit STE12 is cleared by hardware after the shadow transfer. A T12 shadow transfer event is a period-match while counting up or a one-match while counting down. 0 The shadow register transfer is disabled. 1 The shadow register transfer is enabled. Count Direction of Timer T12 This bit is set/reset according to the counting rules of T12. 0 T12 counts up. 1 T12 counts down. T12 Operating Mode 0 Edge-aligned mode: T12 always counts up and continues counting from zero after reaching the period value. 1 Center-aligned mode: T12 counts down after detecting a period-match and counts up after detecting a one-match. CDIR 6 rh CTM 7 rw 1) A concurrent set/reset action on T12R (from T12SSC, T12RR or T12RS) will have no effect. The bit T12R will remain unchanged. TCTR0H Timer Control Register 0 High 7 0 r 6 5 STE 13 rh 4 T13R rh 3 T13 PRE rw 2 Reset Value: 00H 1 T13CLK rw 0 User’s Manual CCU6, V 0.4 12-49 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field T13CLK Bits [2:0] Type Description rw Timer T13 Input Clock Select Selects the input clock for timer T13 which is derived from the peripheral clock according to the equation fT13 = fCCU6/2. 000 fT13 = fCCU6 001 fT13 = fCCU6/2 010 fT13 = fCCU6/4 011 fT13 = fCCU6/8 100 fT13 = fCCU6/16 101 fT13 = fCCU6/32 110 fT13 = fCCU6/64 111 fT13 = fCCU6/128 Timer T13 Prescaler Bit In order to support higher clock frequencies, an additional prescaler factor of 1/256 can be enabled for the prescaler for T13. 0 The additional prescaler for T13 is disabled. 1 The additional prescaler for T13 is enabled. Timer T13 Run Bit T13R starts and stops timer T13. It is set/reset by software by setting bit T13RR or T13RS, or it is set/ reset by hardware according to the function defined by bit T13SSC, and bit fields T13TEC and T13TED. 0 Timer T13 is stopped. 1 Timer T13 is running. Timer T13 Shadow Transfer Enable Bit STE13 enables or disables the shadow transfer of the T13 period value, the compare value and passive state select bit and level from their shadow registers to the actual registers if a T13 shadow transfer event is detected. Bit STE13 is cleared by hardware after the shadow transfer. A T13 shadow transfer event is a period-match. 0 The shadow register transfer is disabled. 1 The shadow register transfer is enabled. Reserved Returns 0 if read; should be written with 0. T13PRE 3 rw T13R1) 4 rh STE13 5 rh 0 1) [7:6] r A concurrent set/reset action on T13R (from T13SSC, T13TEC, T13RR or T13RS) will have no effect. The bit T12R will remain unchanged. User’s Manual CCU6, V 0.4 12-50 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Note: A write action to the bit field T12CLK or bit T12PRE is only taken into account when the timer T12 is not running (T12R = 0). A write action to the bit field T13CLK or bit T13PRE is only taken into account when the timer T13 is not running (T13R = 0). User’s Manual CCU6, V 0.4 12-51 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register TCTR2 controls the single-shot and the synchronization functionality of both timers T12 and T13. Both timers can run in single-shot mode. In this mode, they stop their counting sequence automatically after one counting period with a count value of zero. The single-shot mode and the synchronization of T13 to T12 allow the generation of events with a programmable delay after well-defined PWM actions of T12. For example, this feature can be used to trigger AD conversions, after a specified delay (to avoid problems due to switching noise), synchronously to a PWM event. TCTR2L Timer Control Register 2 Low 7 0 r 6 T13 TED rw 5 4 3 T13 TEC rw 2 Reset Value: 00H 1 T13 SSC rw 0 T12 SSC rw Field T12SSC Bits 0 Type Description rw Timer T12 Single-Shot Control This bit controls the single-shot mode of T12. 0 The single-shot mode is disabled, no hardware action on T12R. 1 The single-shot mode is enabled, the bit T12R is reset by hardware if: – T12 reaches its period value in edge-aligned mode – T12 reaches the value 1 while counting down in center-aligned mode. In parallel to the reset action of bit T12R, the bits CC6xST (x = 0 - 2) are reset. Timer T13 Single-Shot Control This bit controls the single-shot mode of T13. 0 No hardware action on T13R 1 The single-shot mode is enabled, the bit T13R is reset by hardware if T13 reaches its period value. In parallel to the reset action of bit T13R, the bit CC63ST is reset. T13SSC 1 rw User’s Manual CCU6, V 0.4 12-52 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field T13TEC Bits [4:2] Type Description rw T13 Trigger Event Control Bit field T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare signals) according to following combinations: 000 No action 001 Set T13R on a T12 compare event on channel 0 010 Set T13R on a T12 compare event on channel 1 011 Set T13R on a T12 compare event on channel 2 100 Set T13R on any T12 compare event on channel 0, 1, or 2 101 Set T13R upon a period-match of T12 110 Set T13R upon a zero-match of T12 (while counting up) 111 Set T13R on any edge of inputs CCPOSx Timer T13 Trigger Event Direction Bit field T13TED delivers additional information to control the automatic set of bit T13R in case the trigger action defined by T13TEC is detected. 00 Reserved, no action 01 While T12 is counting up 10 While T12 is counting down 11 Independent of the count direction of T12 Reserved Returns 0 if read; should be written with 0. T13TED1) [6:5] rw 0 1) 7 r Example: If the timer T13 is intended to start at any compare event on T12 (T13TEC = 100B), the trigger event direction can be programmed to: - counting up >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting up - counting down >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting down - independent of bit CDIR >> each T12 channel 0, 1, 2 compare match triggers T13R The timer count direction is taken from the value of bit CDIR. As a result, if T12 is running in edge-aligned mode (counting up only), T13 can only be started automatically if bit field T13TED = 01B or 11B. User’s Manual CCU6, V 0.4 12-53 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 TCTR2H Timer Control Register 2 High 7 6 0 r 5 4 3 T13 RSEL rw 2 Reset Value: 00H 1 T12 RSEL rw 0 Field T12RSEL Bits [1:0] Type Description rw Timer T12 External Run Selection Bit field T12RSEL defines the event of signal T12HR that can set the run bit T12R by hardware. 00 The external setting of T12R is disabled. 01 Bit T12R is set if a rising edge of signal T12HR is detected. 10 Bit T12R is set if a falling edge of signal T12HR is detected. 11 Bit T12R is set if an edge of signal T12HR is detected. Timer T13 External Run Selection Bit field T13RSEL defines the event of signal T13HR that can set the run bit T13R by hardware. 00 The external setting of T13R is disabled. 01 Bit T13R is set if a rising edge of signal T13HR is detected. 10 Bit T13R is set if a falling edge of signal T13HR is detected. 11 Bit T13R is set if an edge of signal T13HR is detected. Reserved Returns 0 if read; should be written with 0. T13RSEL [3:2] rw 0 [7:4] r User’s Manual CCU6, V 0.4 12-54 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register TCTR4 allows the software control of the run bits T12R and T13R through independent set and reset conditions. Furthermore, the timers can be reset (while running) and the bits STE12 and STE13 can be controlled by software. TCTR4L Timer Control Register 4 Low 7 T12 STD w 6 T12 STR w 5 0 r 4 3 DT RES w 2 T12 RES w Reset Value: 00H 1 T12 RS w 0 T12 RR w Field T12RR Bits 0 Type Description w Timer T12 Run Reset Setting this bit resets the T12R bit. 0 T12R is not influenced. 1 T12R is cleared, T12 stops counting Timer T12 Run Set Setting this bit sets the T12R bit. 0 T12R is not influenced. 1 T12R is set, T12 counts. Timer T12 Reset 0 No effect on T12 1 The T12 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T12RES has no impact on bit T12R. Dead-Time Counter Reset 0 No effect on the dead-time counters 1 The three dead-time counter channels are reset to zero. Timer T12 Shadow Transfer Request 0 No action 1 STE12 is set, enabling the shadow transfer. Timer T12 Shadow Transfer Disable 0 No action 1 STE12 is reset without triggering the shadow transfer. Reserved Returns 0 if read; should be written with 0. 12-55 V 0.2, 2005-01 T12RS 1 w T12RES 2 w DTRES 3 w T12STR 6 w T12STD 7 w 0 [5:4] r User’s Manual CCU6, V 0.4 XC866 Capture/Compare Unit 6 TCTR4H Timer Control Register 4 High 7 T13 STD w 6 T13 STR w 5 4 0 r 3 2 T13 RES w Reset Value: 00H 1 T13 RS w 0 T13 RR w Field T13RR Bits 0 Type Description w Timer T13 Run Reset Setting this bit resets the T13R bit. 0 T13R is not influenced. 1 T13R is cleared, T13 stops counting. Timer T13 Run Set Setting this bit sets the T13R bit. 0 T13R is not influenced. 1 T13R is set, T13 counts. Timer T13 Reset 0 No effect on T13 1 The T13 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T13RES has no impact on bit T13R. Timer T13 Shadow Transfer Request 0 No action 1 STE13 is set, enabling the shadow transfer. Timer T13 Shadow Transfer Disable 0 No action 1 STE13 is reset without triggering the shadow transfer. Reserved Returns 0 if read; should be written with 0. T13RS 1 w T13RES 2 w T13STR 6 w T13STD 7 w 0 [5:3] r Note: A simultaneous write of a 1 to bits which set and reset the same bit will trigger no action (for example, writing 1 to bits T13RR and T13RS will not modify bit T13R). The corresponding bit will remain unchanged. User’s Manual CCU6, V 0.4 12-56 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.3.5 Modulation Control Registers 12.3.5.1 Global Module Control Register MODCTR contains control bits that enable the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13. Furthermore, the multi-channel mode can be enabled as additional modulation source for the output signals. MODCTRL Modulation Control Register Low 7 MCMEN rw 6 0 r 5 4 3 2 Reset Value: 00H 1 0 T12MODEN rw Field T12MODEN Bits [5:0] Type Description rw T12 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T12. The bit positions correspond to the following output signals: Bit 0 Modulation of CC60 Bit 1 Modulation of COUT60 Bit 2 Modulation of CC61 Bit 3 Modulation of COUT61 Bit 4 Modulation of CC62 Bit 5 Modulation of COUT62 The enable feature of the modulation is defined as follows: 0 The modulation of the corresponding output signal by a T12 PWM pattern is disabled. 1 The modulation of the corresponding output signal by a T12 PWM pattern is enabled. User’s Manual CCU6, V 0.4 12-57 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field MCMEN Bits 7 Type Description rw Multi-Channel Mode Enable 0 The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMP is disabled. 1 The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMP is enabled. Reserved Returns 0 if read; should be written with 0. 0 6 r MODCTRH Modulation Control Register High 7 ECT 13O rw 6 0 r 5 4 3 2 T13MODEN rw Reset Value: 00H 1 0 Field T13MODEN Bits [5:0] Type Description rw T13 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T13. The bit positions correspond to the following output signals: Bit 0 Modulation of CC60 Bit 1 Modulation of COUT60 Bit 2 Modulation of CC61 Bit 3 Modulation of COUT61 Bit 4 Modulation of CC62 Bit 5 Modulation of COUT62 The enable feature of the modulation is defined as follows: 0 The modulation of the corresponding output signal by a T13 PWM pattern is disabled. 1 The modulation of the corresponding output signal by a T13 PWM pattern is enabled. User’s Manual CCU6, V 0.4 12-58 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field ECT13O Bits 7 Type Description rw Enable Compare Timer T13 Output 0 The alternate output function COUT63 is disabled. 1 The alternate output function COUT63 is enabled for the PWM signal generated by T13. Reserved Returns 0 if read; should be written with 0. 0 6 r User’s Manual CCU6, V 0.4 12-59 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register TRPCTR controls the trap functionality. It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition. The trap condition is a low level on the CTRAP input pin, which is monitored (inverted level) by bit TRPF (in register IS). While TRPF = 1 (trap input active), the trap state bit TRPS (in register IS) is set to 1. TRPCTRL Trap Control Register Low 7 6 5 0 r 4 3 2 TRP M2 rw Reset Value: 00H 1 TRP M1 rw 0 TRP M0 rw Field TRPM0, TRPM1 Bits [1:0] Type Description rw Trap Mode Control Bits 0, 1 These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again. A synchronization to the timer driving the PWM pattern avoids unintended short pulses when leaving the trap state. The combination (TRPM0 and TRPM1) leads to: 00 The trap state is left (return to normal operation according to TRPM2) when a zeromatch of T12 (while counting up) is detected (synchronization to T12). 01 The trap state is left (return to normal operation according to TRPM2) when a zeromatch of T13 is detected (synchronization to T13). 10 Reserved 11 The trap state is left (return to normal operation according to TRPM2) immediately without any synchronization to T12 or T13. User’s Manual CCU6, V 0.4 12-60 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field TRPM2 Bits 2 Type Description rw Trap Mode Control Bit 2 0 The trap state can be left (return to normal operation = bit TRPS = 0) as soon as the input CTRAP becomes inactive. Bit TRPF is automatically cleared by hardware if the input pin CTRAP becomes 1. Bit TRPS is automatically cleared by hardware if bit TRPF is 0 and if the synchronization condition (according to TRPM0 and TRPM1) is detected. 1 The trap state can be left (return to normal operation = bit TRPS = 0) as soon as bit TRPF is reset by software after the input CTRAP becomes inactive (TRPF is not cleared by hardware). Bit TRPS is automatically cleared by hardware if bit TRPF = 0 and if the synchronization condition (according to TRPM0 and TRPM1) is detected. Reserved Returns 0 if read; should be written with 0. 0 [7:3] r TRPCTRH Trap Control Register High 7 TRP PEN rw 6 TRP EN 13 rw 5 4 3 TRPEN rw 2 Reset Value: 00H 1 0 User’s Manual CCU6, V 0.4 12-61 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field TRPEN Bits [5:0] Type Description rw Trap Enable Control Setting these bits enables the trap functionality for the following corresponding output signals: Bit 0 Trap functionality of CC60 Bit 1 Trap functionality of COUT60 Bit 2 Trap functionality of CC61 Bit 3 Trap functionality of COUT61 Bit 4 Trap functionality of CC62 Bit 5 Trap functionality of COUT62 The enable feature of the trap functionality is defined as follows: 0 The trap functionality of the corresponding output signal is disabled. The output state is independent of bit TRPS. 1 The trap functionality of the corresponding output signal is enabled. The output is set to the passive state while TRPS = 1. Trap Enable Control for Timer T13 0 The trap functionality for T13 is disabled. Timer T13 (if selected and enabled) provides PWM functionality even while TRPS = 1. 1 The trap functionality for T13 is enabled. The timer T13 PWM output signal is set to the passive state while TRPS = 1. Trap Pin Enable 0 The trap functionality based on the input pin CTRAP is disabled. A trap can only be generated by software by setting bit TRPF. 1 The trap functionality based on the input pin CTRAP is enabled. A trap can be generated by software by setting bit TRPF or by CTRAP = 0. TRPEN13 6 rw TRPPEN 7 rw User’s Manual CCU6, V 0.4 12-62 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register PSLR defines the passive state level driven by the output pins of the module. The passive state level is the value that is driven by the port pin during the passive state of the output. During the active state, the corresponding output pin drives the active state level, which is the inverted passive state level. The passive state level permits the adaptation of the driven output levels to the driver polarity (inverted or not inverted) of the connected power stage. PSLR Passive State Level Register 7 PSL 63 rwh 6 0 r 5 4 3 PSL rwh 2 Reset Value: 00H 1 0 Field PSL1) Bits [5:0] Type Description rwh Compare Outputs Passive State Level The bits of this bit field define the passive level driven by the module outputs during the passive state. The bit positions are: Bit 0 Passive level for output CC60 Bit 1 Passive level for output COUT60 Bit 2 Passive level for output CC61 Bit 3 Passive level for output COUT61 Bit 4 Passive level for output CC62 Bit 5 Passive level for output COUT62 The value of each bit position is defined as: 0 The passive level is 0. 1 The passive level is 1. Passive State Level of Output COUT63 This bit field defines the passive level of the output pin COUT63. 0 The passive level is 0. 1 The passive level is 1. Reserved Returns 0 if read; should be written with 0. PSL632) 7 rwh 0 1) 6 r Bit field PSL has a shadow register to allow for updates without undesired pulses on the output lines. The bits are updated with the T12 shadow transfer. A read action targets the actually used values, while a write action targets the shadow bits. User’s Manual CCU6, V 0.4 12-63 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 2) Bit PSL63 has a shadow register to allow for updates without undesired pulses on the output line. The bit is updated with the T13 shadow transfer. A read action targets the actually used values, while a write action targets the shadow bits. User’s Manual CCU6, V 0.4 12-64 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.3.5.2 Multi-Channel Control Register MCMOUTS contains bits that control the output states for multi-channel mode. Furthermore, the appropriate signals for the block commutation by Hall sensors can be selected. This register is a shadow register (that can be written) for register MCMOUT, which indicates the currently active signals. MCMOUTSL Multi-Channel Mode Output Shadow Register Low 7 STR MCM w 6 0 r 5 4 3 MCMPS rw 2 Reset Value: 00H 1 0 Field MCMPS Bits [5:0] Type Description rw Multi-Channel PWM Pattern Shadow Bit field MCMPS is the shadow bit field for bit field MCMP. The multi-channel shadow transfer is triggered according to the transfer conditions defined by register MCMCTR. Shadow Transfer Request for MCMPS Setting this bit during a write action leads to an immediate update of bit field MCMP by the value written to bit field MCMPS. This functionality permits an update triggered by software. When read, this bit always delivers 0. 0 Bit field MCMP is updated according to the defined hardware action. The write access to bit field MCMPS does not modify bit field MCMP. 1 Bit field MCMP is updated by the value written to bit field MCMPS. Reserved Returns 0 if read; should be written with 0. STRMCM 7 w 0 6 r User’s Manual CCU6, V 0.4 12-65 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 MCMOUTSH Multi-Channel Mode Output Shadow Register High 7 STR HP w 6 0 r 5 4 CURHS rw 3 2 Reset Value: 00H 1 EXPHS rw 0 Field EXPHS Bits [2:0] Type Description rw Expected Hall Pattern Shadow Bit field EXPHS is the shadow bit field for bit field EXPH. The bit field is transferred to bit field EXPH if an edge on the hall input pins CCPOSx (x = 0 - 2) is detected. Current Hall Pattern Shadow Bit field CURHS is the shadow bit field for bit field CURH. The bit field is transferred to bit field CURH if an edge on the hall input pins CCPOSx (x = 0 - 2) is detected. Shadow Transfer Request for the Hall Pattern Setting these bits during a write action leads to an immediate update of bit fields CURH and EXPH by the value written to bit fields CURHS and EXPHS. This functionality permits an update triggered by software. When read, this bit always delivers 0. 0 The bit fields CURH and EXPH are updated according to the defined hardware action. The write access to bit fields CURHS and EXPHS does not modify the bit fields CURH and EXPH. 1 The bit fields CURH and EXPH are updated by the value written to the bit fields CURHS and EXPHS. Reserved Returns 0 if read; should be written with 0. CURHS [5:3] rw STRHP 7 w 0 6 r User’s Manual CCU6, V 0.4 12-66 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register MCMOUT specifies the multi-channel control bits that are currently used. MCMOUTL Multi-Channel Mode Output Register Low 7 0 r 6 R rh 5 4 3 MCMP rh 2 Reset Value: 00H 1 0 Field MCMP1) Bits [5:0] Type Description rh Multi-Channel PWM Pattern Bit field MCMP is written by a shadow transfer from bit field MCMPS. It contains the output pattern for the multi-channel mode. If this mode is enabled by bit MCMEN in register MODCTR, the output state of the following output signal can be modified: Bit 0 Multi-channel state for output CC60 Bit 1 Multi-channel state for output COUT60 Bit 2 Multi-channel state for output CC61 Bit 3 Multi-channel state for output COUT61 Bit 4 Multi-channel state for output CC62 Bit 5 Multi-channel state for output COUT62 The multi-channel patterns can set the related output to the passive state. 0 The output is set to the passive state. The PWM generated by T12 or T13 is not taken into account. 1 The output can deliver the PWM generated by T12 or T13 (according to register MODCTR). User’s Manual CCU6, V 0.4 12-67 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field R Bits 6 Type Description rh Reminder Flag This reminder flag indicates that the shadow transfer from bit field MCMPS to MCMP has been requested by the selected trigger source. This bit is cleared when the shadow transfer takes place and while MCMEN = 0. 0 No shadow transfer from MCMPS to MCMP is requested 1 A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source, but has not been executed, because the selected synchronization condition has not occurred. Reserved Returns 0 if read; should be written with 0. 0 1) 7 r While IDLE = 1, bit field MCMP is cleared. User’s Manual CCU6, V 0.4 12-68 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 MCMOUTH Multi-Channel Mode Output Register High 7 0 r 6 5 4 CURH rh 3 2 Reset Value: 00H 1 EXPH rh 0 Field EXPH1) Bits [2:0] Type Description rh Expected Hall Pattern Bit field EXPH is written by a shadow transfer from bit field EXPHS. The contents are compared after every detected edge at the hall input pins in order to detect the occurrence of the next desired (expected) hall pattern or a wrong pattern. If the current hall pattern at the hall input pins is equal to the bit field EXPH, bit CHE (correct hall event) is set and an interrupt request is generated (if enabled by bit ENCHE). If the current hall pattern at the hall input pins is not equal to the bit fields CURH or EXPH, bit WHE (wrong hall event) is set and an interrupt request is generated (if enabled by bit ENWHE). Current Hall Pattern Bit field CURH is written by a shadow transfer from bit field CURHS. The contents are compared after every detected edge at the hall input pins in order to detect the occurrence of the next desired (expected) hall pattern or a wrong pattern. If the current Hall input pattern is equal to bit field CURH, the detected edge at the hall input pins was an invalid transition (e.g., a spike). Reserved Returns 0 if read; should be written with 0. CURH [5:3] rh 0 1) [7:6] r The bits in the bit fields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx (x = 0 - 2) in the following order (EXPH.2, EXPH.1, EXPH.0), (CURH.2, CURH.1, CURH.0), (CCPOS2, CCPOS1, CCPOS0). User’s Manual CCU6, V 0.4 12-69 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register MCMCTR contains control bits for the multi-channel functionality. MCMCTR Multi-Channel Mode Control Register 7 0 r 6 5 SWSYN rw 4 3 0 r 2 Reset Value: 00H 1 SWSEL rw 0 Field SWSEL Bits [2:0] Type Description rw Switching Selection Bit field SWSEL selects one of the following trigger request sources (next multi-channel event) for the shadow transfer from MCMPS to MCMP. The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer. The shadow transfer takes place synchronously with an event selected in bit field SWSYN. 000 No trigger request will be generated 001 Correct hall pattern on CCPOSx detected 010 T13 period-match detected (while counting up) 011 T12 one-match (while counting down) 100 T12 channel 1 compare-match detected (phase delay function) 101 T12 period match detected (while counting up); else reserved, no trigger request will be generated User’s Manual CCU6, V 0.4 12-70 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field SWSYN Bits [5:4] Type Description rw Switching Synchronization Bit field SWSYN triggers the shadow transfer between MCMPS and MCMP if it has been requested before (flag R set by an event selected by SWSEL). This feature permits the synchronization of the outputs to the PWM source that is used for modulation (T12 or T13). 00 Direct; the trigger event directly causes the shadow transfer 01 T13 zero-match triggers the shadow transfer 10 A T12 zero-match (while counting up) triggers the shadow transfer 11 Reserved; no action Reserved Returns 0 if read; should be written with 0. 0 3, [7:6] r Note: The generation of the shadow transfer request by hardware is only enabled if bit MCMEN = 1. User’s Manual CCU6, V 0.4 12-71 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register T12MSEL contains control bits that select the capture/compare functionality of the three channels of timer T12. T12MSELL T12 Capture/Compare Mode Select Register Low 7 6 MSEL61 rw 5 4 3 2 MSEL60 rw Reset Value: 00H 1 0 Field MSEL60, MSEL61 Bits Type Description Capture/Compare Mode Selection These bit fields select the operating mode of the three timer T12 capture/compare channels. Each channel (n = 0 - 2) can be programmed individually either for compare or capture operation according to: 0000 Compare outputs disabled, pins CC6n and COUT6n can be used for I/O pins. No capture action. 0001 Compare output on pin CC6n, pin COUT6n can be used for I/O pins. No capture action. 0010 Compare output on pin COUT6n, pin CC6n can be used for I/O pins. No capture action. 0011 Compare output on pins COUT6n and CC6n 01XX Double-register capture modes, see Table 12-5. 1000 Hall sensor mode, see Table 12-6. In order to enable the hall edge detection, MSEL6x (x = 0 - 2) must be programmed to hall sensor mode. 1001 Hysteresis-like mode, see Table 12-6 101X Multi-input capture modes, see Table 12-7 11XX Multi-input capture modes, see Table 12-7 [3:0], rw [7:4] User’s Manual CCU6, V 0.4 12-72 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 T12MSELH T12 Capture/Compare Mode Select Register High 7 D BYP rw 6 5 HSYNC rw 4 3 2 Reset Value: 00H 1 MSEL62 rw 0 Field MSEL62 Bits [3:0] Type Description rw Capture/Compare Mode Selection These bit fields select the operating mode of the three timer T12 capture/compare channels. Each channel (n = 0 - 2) can be programmed individually either for compare or capture operation according to: 0000 Compare outputs disabled, pins CC6n and COUT6n can be used for I/O pins. No capture action. 0001 Compare output on pin CC6n, pin COUT6n can be used for I/O pins. No capture action. 0010 Compare output on pin COUT6n, pin CC6n can be used for I/O pins. No capture action. 0011 Compare output on pins COUT6n and CC6n. 01XX Double-register capture modes, see Table 12-5. 1000 Hall sensor mode, see Table 12-6. In order to enable the hall edge detection, all three MSEL6x must be programmed to hall sensor mode. 1001 Hysteresis-like mode, see Table 12-6. 101X Multi-input capture modes, see Table 12-7. 11XX Multi-input capture modes, see Table 12-7. User’s Manual CCU6, V 0.4 12-73 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field HSYNC Bits [6:4] Type Description rw Hall Synchronization Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields. In all modes, a trigger by software by writing a 1 to bit SWHC is possible. 000 Any edge at one of the inputs CCPOSx (x = 0 - 2) triggers the sampling. 001 A T13 compare-match triggers the sampling. 010 A T13 period-match triggers the sampling. 011 The Hall sampling triggered by hardware sources is switched off. 100 A T12 period-match (while counting up) triggers the sampling. 101 A T12 one-match (while counting down) triggers the sampling. 110 A T12 compare-match of channel 0 (while counting up) triggers the sampling. 111 A T12 compare-match of channel 0 (while counting down) triggers the sampling. Delay Bypass Bit DBYP determines if the source signal for the sampling of the Hall input pattern (selected by HSYNC) uses the dead-time counter DTC0 of timer T12 as additional delay or if the delay is bypassed. 0 The delay bypass is not active. The dead-time counter DTC0 generates a delay after the source signal becomes active. 1 The delay bypass is active. The dead-time counter DTC0 is not used by the sampling of the Hall pattern. DBYP 7 rw Note: In the capture modes, all edges at the CC6x inputs lead to the setting of the corresponding interrupt status flags in register IS. In order to monitor the selected capture events at the CCPOSx inputs in the multi-input capture modes, the CC6xST bits of the corresponding channel are set when detecting the selected event. The interrupt status bits and the CC6xST bits must be reset by software. User’s Manual CCU6, V 0.4 12-74 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Table 12-5 Description Double-Register Capture Modes 0100 The contents of T12 are stored in CC6nR after a rising edge and in CC6nSR after a falling edge on the input pin CC6n. 0101 The value stored in CC6nSR is copied to CC6nR after a rising edge on the input pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for time measurements between consecutive rising edges on pins CC6n. COUT6n is I/O pin. 0110 The value stored in CC6nSR is copied to CC6nR after a falling edge on the input pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for time measurements between consecutive falling edges on pins CC6n. COUT6n is I/O pin. 0111 The value stored in CC6nSR is copied to CC6nR after any edge on the input pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for time measurements between consecutive edges on pins CC6n. COUT6n is I/O pin. Table 12-6 Description Combined T12 Modes 1000 Hall sensor mode: Capture mode for channel 0, compare mode for channels 1 and 2. The contents of T12 are captured into CC60 at a valid hall event (which is a reference to the actual speed). CC61 can be used for a phase delay function between hall event and output switching. CC62 can act as a time-out trigger if the expected hall event is too late. The value 1000B must be programmed to MSEL0, MSEL1 and MSEL2 if the hall signals are used. In this mode, the contents of timer T12 are captured in CC60 and T12 is reset after the detection of a valid hall event. In order to avoid noise effects, the dead-time counter channel 0 is started after an edge has been detected at the hall inputs. On reaching the value of 000001B, the hall inputs are sampled and the pattern comparison is done. 1001 Hysteresis-like control mode with dead-time generation: The negative edge of the CCPOSx input signal is used to reset bit CC6nST. As a result, the output signals can be switched to passive state immediately and switched back to active state (with dead-time) if the CCPOSx is high and the bit CC6nST is set by a compare event. Combined T12 Modes Double-Register Compare Modes User’s Manual CCU6, V 0.4 12-75 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Table 12-7 Description Multi-Input Capture Modes 1010 The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx. 1011 The timer value of T12 is stored in CC6nR after a falling edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx. 1100 The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx. 1101 The timer value of T12 is stored in CC6nR after a falling edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx. 1110 The timer value of T12 is stored in CC6nR after any edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after any edge at the input pin CCPOSx. 1111 Reserved (no capture or compare action) Multi-Input Capture Modes User’s Manual CCU6, V 0.4 12-76 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 12.3.6 Interrupt Control Registers ISL Capture/Compare Interrupt Status Register Low 7 T12 PM rh 6 T12 OM rh 5 ICC 62F rh 4 ICC 62R rh 3 ICC 61F rh 2 ICC 61R rh Reset Value: 00H 1 ICC 60F rh 0 ICC 60R rh Field ICC60R, ICC61R, ICC62R Bits 0, 2, 4 Type Description rh Capture, Compare-Match Rising Edge Flag In compare mode, a compare-match has been detected while T12 was counting up. In capture mode, a rising edge has been detected at the input CC6x (x = 0 - 2). 0 The event has not occurred since this bit was reset. 1 The event described above has been detected. Capture, Compare-Match Falling Edge Flag In compare mode, a compare-match has been detected while T12 was counting down. In capture mode, a falling edge has been detected at the input CC6x (x = 0 - 2). 0 The event has not occurred since this bit was reset. 1 The event described above has been detected. Timer T12 One-Match Flag 0 A timer T12 one-match (while counting down) has not been detected since this bit was reset. 1 A timer T12 one-match (while counting down) has been detected. Timer T12 Period-Match Flag 0 A timer T12 period-match (while counting up) has not been detected since this bit was reset. 1 A timer T12 period-match (while counting up) has been detected. ICC60F, ICC61F, ICC62F 1, 3, 5 rh T12OM 6 rh T12PM 7 rh User’s Manual CCU6, V 0.4 12-77 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 ISH Capture/Compare Interrupt Status Register High 7 STR rh 6 IDLE rh 5 WHE rh 4 CHE rh 3 TRP S rh 2 TRP F rh Reset Value: 00H 1 T13 PM rh 0 T13 CM rh Field T13CM Bits 0 Type Description rh Timer T13 Compare-Match Flag 0 A timer T13 compare-match has not been detected since this bit was reset. 1 A timer T13 compare-match has been detected. Timer T13 Period-Match Flag 0 A timer T13 period-match has not been detected since this bit was reset. 1 A timer T13 period-match has been detected. Trap Flag The trap flag TRPF will be set by hardware if TRPPEN = 1 and CTRAP = 0 or by software. If TRPM2 = 0, bit TRPF is reset by hardware if the input CTRAP becomes inactive (TRPPEN = 1). If TRPM2 = 1, bit TRPF must be reset by software in order to leave the trap state. 0 The trap condition has not been detected. 1 The trap condition has been detected (input CTRAP has been 0 or by software). Trap State 0 The trap state is not active. 1 The trap state is active. Bit TRPS is set while bit TRPF = 1. It is reset according to the mode selected in register TRPCTR. Correct Hall Event 0 A transition to a correct (expected) hall event has not been detected since this bit was reset. 1 A transition to a correct (expected) hall event has been detected. T13PM 1 rh TRPF 2 rh TRPS1) 3 rh CHE2) 4 rh User’s Manual CCU6, V 0.4 12-78 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field WHE3) Bits 5 Type Description rh Wrong Hall Event 0 A transition to a wrong hall event (not the expected one) has not been detected since this bit was reset. 1 A transition to a wrong hall event (not the expected one) has been detected. IDLE State This bit is set together with bit WHE (wrong hall event) and it must be reset by software. 0 No action 1 Bit field MCMP is cleared, the selected outputs are set to passive state. Multi-Channel Mode Shadow Transfer Request This bit is set when a shadow transfer from MCMOUTS to MCMOUT takes places in multi-channel mode. 0 The shadow transfer has not taken place. 1 The shadow transfer has taken place. IDLE4) 6 rh STR 7 rh 1) During the trap state, the selected outputs are set to the passive state. The logic level driven during the passive state is defined by the corresponding bit in register PSLR. Bit TRPS = 1 and TRPF = 0 can occur if the trap condition is no longer active but the selected synchronization has not yet taken place. 2) On every valid hall edge, the contents of EXPH are compared with the pattern on pin CCPOSx and if both are equal, bit CHE is set. 3) On every valid hall edge, the contents of EXPH are compared with the pattern on pin CCPOSx. If both comparisons (CURH and EXPH with CCPOSx) are not true, bit WHE (wrong hall event) is set. 4) Bit field MCMP is held to 0 by hardware as long as IDLE = 1. Note: Not all bits in register IS can generate an interrupt. Other status bits have been added, which have a similar structure for their set and reset actions. Note: The interrupt generation is independent of the value of the bits in register IS, e.g., the interrupt will be generated (if enabled) even if the corresponding bit is already set. The trigger for an interrupt generation is the detection of a set condition (by hardware or software) for the corresponding bit in register IS. Note: In compare mode (and hall mode), the timer-related interrupts are only generated while the timer is running (TxR = 1). In capture mode, the capture interrupts are also generated when the timer T12 is stopped. User’s Manual CCU6, V 0.4 12-79 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 ISSL Capture/Compare Interrupt Status Set Register Low 7 S T12 PM w 6 S T12 OM w 5 S CC 62F w 4 S CC 62R w 3 S CC 61F w 2 S CC 61R w Reset Value: 00H 1 S CC 60F w 0 S CC 60R w Field SCC60R Bits 0 Type Description w Set Capture, Compare-Match Rising Edge Flag 0 No action 1 Bit ICC60R in register IS will be set. Set Capture, Compare-Match Falling Edge Flag 0 No action 1 Bit ICC60F in register IS will be set. Set Capture, Compare-Match Rising Edge Flag 0 No action 1 Bit ICC61R in register IS will be set. Set Capture, Compare-Match Falling Edge Flag 0 No action 1 Bit ICC61F in register IS will be set. Set Capture, Compare-Match Rising Edge Flag 0 No action 1 Bit ICC62R in register IS will be set. Set Capture, Compare-Match Falling Edge Flag 0 No action 1 Bit ICC62F in register IS will be set. Set Timer T12 One-Match Flag 0 No action 1 Bit T12OM in register IS will be set. Set Timer T12 Period-Match Flag 0 No action 1 Bit T12PM in register IS will be set. SCC60F 1 w SCC61R 2 w SCC61F 3 w SCC62R 4 w SCC62F 5 w ST12OM 6 w ST12PM 7 w Note: If the setting by hardware of the corresponding flags leads to an interrupt, the setting by software has the same effect. User’s Manual CCU6, V 0.4 12-80 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 ISSH Capture/Compare Interrupt Status Set Register High 7 S STR w 6 S IDLE w 5 S WHE w 4 S CHE w 3 S WHC w 2 S TRPF w Reset Value: 00H 1 S T13 PM w 0 S T13 CM w Field ST13CM Bits 0 Type Description w Set Timer T13 Compare-Match Flag 0 No action 1 Bit T13CM in register IS will be set. Set Timer T13 Period-Match Flag 0 No action 1 Bit T13PM in register IS will be set. Set Trap Flag 0 No action 1 Bits TRPF and TRPS in register IS will be set. Software Hall Compare 0 No action 1 The Hall compare action is triggered. Set Correct Hall Event Flag 0 No action 1 Bit CHE in register IS will be set. Set Wrong Hall Event Flag 0 No action 1 Bit WHE in register IS will be set. Set IDLE Flag 0 No action 1 Bit IDLE in register IS will be set. Set STR Flag 0 No action 1 Bit STR in register IS will be set. ST13PM 1 w STRPF 2 w SWHC 3 w SCHE 4 w SWHE 5 w SIDLE 6 w SSTR 7 w User’s Manual CCU6, V 0.4 12-81 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Register ISR contains the individual interrupt request reset bits to reset the corresponding flags by software. ISRL Capture/Compare Interrupt Status Reset Register Low 7 R T12 PM w 6 R T12 OM w 5 R CC 62F w 4 R CC 62R w 3 R CC 61F w 2 R CC 61R w Reset Value: 00H 1 R CC 60F w 0 R CC 60R w Field RCC60R Bits 0 Type Description w Reset Capture, Compare-Match Rising Edge Flag 0 No action 1 Bit ICC60R in register IS will be reset. Reset Capture, Compare-Match Falling Edge Flag 0 No action 1 Bit ICC60F in register IS will be reset. Reset Capture, Compare-Match Rising Edge Flag 0 No action 1 Bit ICC61R in register IS will be reset. Reset Capture, Compare-Match Falling Edge Flag 0 No action 1 Bit ICC61F in register IS will be reset. Reset Capture, Compare-Match Rising Edge Flag 0 No action 1 Bit ICC62R in register IS will be reset. Reset Capture, Compare-Match Falling Edge Flag 0 No action 1 Bit ICC62F in register IS will be reset. Reset Timer T12 One-Match Flag 0 No action 1 Bit T12OM in register IS will be reset. Reset Timer T12 Period-Match Flag 0 No action 1 Bit T12PM in register IS will be reset. RCC60F 1 w RCC61R 2 w RCC61F 3 w RCC62R 4 w RCC62F 5 w RT12OM 6 w RT12PM 7 w User’s Manual CCU6, V 0.4 12-82 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 ISRH Capture/Compare Interrupt Status Reset Register High 7 R STR w 6 R IDLE w 5 R WHE w 4 R CHE w 3 0 r 2 R TRPF w Reset Value: 00H 1 R T13 PM w 0 R T13 CM w Field RT13CM Bits 0 Type Description w Reset Timer T13 Compare-Match Flag 0 No action 1 Bit T13CM in register IS will be reset. Reset Timer T13 Period-Match Flag 0 No action 1 Bit T13PM in register IS will be reset. Reset Trap Flag 0 No action 1 Bit TRPF in register IS will be reset (not taken into account while input CTRAP = 0 and TRPPEN = 1). Reset Correct Hall Event Flag 0 No action 1 Bit CHE in register IS will be reset. Reset Wrong Hall Event Flag 0 No action 1 Bit WHE in register IS will be reset. Reset IDLE Flag 0 No action 1 Bit IDLE in register IS will be reset. Reset STR Flag 0 No action 1 Bit STR in register IS will be reset. Reserved Returns 0 if read; should be written with 0. RT13PM 1 w RTRPF 2 w RCHE 4 w RWHE 5 w RIDLE 6 w RSTR 7 w 0 3 r User’s Manual CCU6, V 0.4 12-83 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 IENL Capture/Compare Interrupt Enable Register Low 7 EN T12 PM rw 6 EN T12 OM rw 5 EN CC 62F rw 4 EN CC 62R rw 3 EN CC 61F rw 2 EN CC 61R rw Reset Value: 00H 1 EN CC 60F rw 0 EN CC 60R rw Field ENCC60R Bits 0 Type Description rw Capture, Compare-Match Rising Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the set condition for bit ICC60R in register IS occurs. 1 An interrupt will be generated if the set condition for bit ICC60R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60. Capture, Compare-Match Falling Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the set condition for bit ICC60F in register IS occurs. 1 An interrupt will be generated if the set condition for bit ICC60F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60. Capture, Compare-Match Rising Edge Interrupt Enable for Channel 1 0 No interrupt will be generated if the set condition for bit ICC61R in register IS occurs. 1 An interrupt will be generated if the set condition for bit ICC61R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61. Capture, Compare-Match Falling Edge Interrupt Enable for Channel 1 0 No interrupt will be generated if the set condition for bit ICC61F in register IS occurs. 1 An interrupt will be generated if the set condition for bit ICC61F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61. 12-84 V 0.2, 2005-01 ENCC60F 1 rw ENCC61R 2 rw ENCC61F 3 rw User’s Manual CCU6, V 0.4 XC866 Capture/Compare Unit 6 Field ENCC62R Bits 4 Type Description rw Capture, Compare-Match Rising Edge Interrupt Enable for Channel 2 0 No interrupt will be generated if the set condition for bit ICC62R in register IS occurs. 1 An interrupt will be generated if the set condition for bit ICC62R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62. Capture, Compare-Match Falling Edge Interrupt Enable for Channel 2 0 No interrupt will be generated if the set condition for bit ICC62F in register IS occurs. 1 An interrupt will be generated if the set condition for bit ICC62F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62. Enable Interrupt for T12 One-Match 0 No interrupt will be generated if the set condition for bit T12OM in register IS occurs. 1 An interrupt will be generated if the set condition for bit T12OM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12. Enable Interrupt for T12 Period-Match 0 No interrupt will be generated if the set condition for bit T12PM in register IS occurs. 1 An interrupt will be generated if the set condition for bit T12PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12. ENCC62F 5 rw ENT12OM 6 rw ENT12PM 7 rw IENH Capture/Compare Interrupt Enable Register High 7 EN STR rw 6 EN IDLE rw 5 EN WHE rw 4 EN CHE rw 3 0 r 2 EN TRPF rw Reset Value: 00H 1 EN T13 PM rw 0 EN T13 CM rw User’s Manual CCU6, V 0.4 12-85 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field ENT13CM Bits 0 Type Description rw Enable Interrupt for T13 Compare-Match 0 No interrupt will be generated if the set condition for bit T13CM in register IS occurs. 1 An interrupt will be generated if the set condition for bit T13CM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13. Enable Interrupt for T13 Period-Match 0 No interrupt will be generated if the set condition for bit T13PM in register IS occurs. 1 An interrupt will be generated if the set condition for bit T13PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13. Enable Interrupt for Trap Flag 0 No interrupt will be generated if the set condition for bit TRPF in register IS occurs. 1 An interrupt will be generated if the set condition for bit TRPF in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR. Enable Interrupt for Correct Hall Event 0 No interrupt will be generated if the set condition for bit CHE in register IS occurs. 1 An interrupt will be generated if the set condition for bit CHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE. Enable Interrupt for Wrong Hall Event 0 No interrupt will be generated if the set condition for bit WHE in register IS occurs. 1 An interrupt will be generated if the set condition for bit WHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR. ENT13PM 1 rw ENTRPF 2 rw ENCHE 4 rw ENWHE 5 rw User’s Manual CCU6, V 0.4 12-86 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field ENIDLE Bits 6 Type Description rw Enable Idle This bit enables the automatic entering of the idle state (bit IDLE will be set) after a wrong hall event has been detected (bit WHE is set). During the idle state, the bit field MCMP is automatically cleared. 0 The bit IDLE is not automatically set when a wrong hall event is detected. 1 The bit IDLE is automatically set when a wrong hall event is detected. Enable Multi-Channel Mode Shadow Transfer Interrupt 0 No interrupt will be generated if the set condition for bit STR in register IS occurs. 1 An interrupt will be generated if the set condition for bit STR in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE. Reserved Returns 0 if read; should be written with 0. ENSTR 7 rw 0 3 r User’s Manual CCU6, V 0.4 12-87 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 INPL Capture/Compare Interrupt Node Pointer Register Low 7 INP CHE rw 6 5 INP CC62 rw 4 3 INP CC61 rw 2 Reset Value: 40H 1 INP CC60 rw 0 Field INPCC60 Bits [1:0] Type Description rw Interrupt Node Pointer for Channel 0 Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit ICC60R (if enabled by bit ENCC60R) or for bit ICC60F (if enabled by bit ENCC60F). 00 Interrupt output line SR0 is selected. 01 Interrupt output line SR1 is selected. 10 Interrupt output line SR2 is selected. 11 Interrupt output line SR3 is selected. Interrupt Node Pointer for Channel 1 Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit ICC61R (if enabled by bit ENCC61R) or for bit ICC61F (if enabled by bit ENCC61F). 00 Interrupt output line SR0 is selected. 01 Interrupt output line SR1 is selected. 10 Interrupt output line SR2 is selected. 11 Interrupt output line SR3 is selected. INPCC61 [3:2] rw User’s Manual CCU6, V 0.4 12-88 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field INPCC62 Bits [5:4] Type Description rw Interrupt Node Pointer for Channel 2 Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit ICC62R (if enabled by bit ENCC62R) or for bit ICC62F (if enabled by bit ENCC62F). 00 Interrupt output line SR0 is selected. 01 Interrupt output line SR1 is selected. 10 Interrupt output line SR2 is selected. 11 Interrupt output line SR3 is selected. Interrupt Node Pointer for the CHE Interrupt This bit field defines the interrupt output line, which is activated due to a set condition for bit CHE (if enabled by bit ENCHE) or for bit STR (if enabled by bit ENSTR). 00 Interrupt output line SR0 is selected. 01 Interrupt output line SR1 is selected. 10 Interrupt output line SR2 is selected. 11 Interrupt output line SR3 is selected. INPCHE [7:6] rw INPH Capture/Compare Interrupt Node Pointer Register High 7 0 r 6 5 INP T13 rw 4 3 INP T12 rw 2 Reset Value: 39H 1 INP ERR rw 0 User’s Manual CCU6, V 0.4 12-89 V 0.2, 2005-01 XC866 Capture/Compare Unit 6 Field INPERR Bits [1:0] Type Description rw Interrupt Node Pointer for Error Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit TRPF (if enabled by bit ENTRPF) or for bit WHE (if enabled by bit ENWHE). 00 Interrupt output line SR0 is selected. 01 Interrupt output line SR1 is selected. 10 Interrupt output line SR2 is selected. 11 Interrupt output line SR3 is selected. Interrupt Node Pointer for Timer T12 Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit T12OM (if enabled by bit ENT12OM) or for bit T12PM (if enabled by bit ENT12PM). 00 Interrupt output line SR0 is selected. 01 Interrupt output line SR1 is selected. 10 Interrupt output line SR2 is selected. 11 Interrupt output line SR3 is selected. Interrupt Node Pointer for Timer T13 Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit T13CM (if enabled by bit ENT13CM) or for bit T13PM (if enabled by bit ENT13PM). 00 Interrupt output line SR0 is selected. 01 Interrupt output line SR1 is selected. 10 Interrupt output line SR2 is selected. 11 Interrupt output line SR3 is selected. Reserved Returns 0 if read; should be written with 0. INPT12 [3:2] rw INPT13 [5:4] rw 0 [7:6] r User’s Manual CCU6, V 0.4 12-90 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13 Analog-to-Digital Converter The XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. Features: • Successive approximation • 8-bit or 10-bit resolution (TUE of ± 1 LSB and ± 2 LSB, respectively) • Eight analog channels • Four independent result registers (configurable for FIFO functionality) • Result data protection for slow CPU access (wait-for-read mode) • Single conversion mode • Autoscan functionality • Limit checking for conversion results • Data reduction filter (accumulation of up to 2 conversion results) • Two independent conversion request sources with programmable priority • Selectable conversion request trigger • Flexible interrupt generation with configurable service nodes • Programmable sample time • Programmable clock divider • Cancel/restart feature for running conversions • Integrated sample and hold circuitry • Compensation of offset errors • Low power modes User’s Manual ADC, V 0.3 13-1 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.1 Structure Overview The ADC module consists of two main parts, i.e., analog and digital, with each containing independent building blocks. The analog part includes: • Analog input multiplexer (for selecting the channel to be converted) • Analog converter stage (e.g., capacitor network and comparator as part of the ADC) • Digital control part of the analog converter stage (for controlling the analog-to-digital conversion process and generating the conversion result) The digital part defines and controls the overall functionality of the ADC module, and includes: • Digital data and conversion request handling (for controlling the conversion trigger mechanisms and handling the conversion results) • Bus interface to the device-internal data bus (for controlling the interrupts and register accesses) The block diagram of the ADC module is shown in Figure 13-1. The analog input channel x (x = 0 - 7) is available at port pin P2.x/ANx. analog part analog input 0 AD converter ... analog input 7 conversion control analog clock fADCA Figure 13-1 Overview of ADC Building Blocks User’s Manual ADC, V 0.3 digital part data (result) handling request control digital clock fADCD bus interface fADC 13-2 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.2 Clocking Scheme A common module clock fADC generates the various clock signals used by the analog and digital parts of the ADC module: • fADCA is input clock for the analog part. • fADCI is internal clock for the analog part (defines the time base for conversion length and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components. • fADCD is input clock for the digital part. This clock is used for the arbiter (defines the duration of an arbitration round) and other digital control structures (e.g., registers and the interrupt generation). The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz. Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required. f ADC = fPCLK fADCD arbiter registers interrupts digital part fADCA CTC ÷ 32 f ADCI ÷4 MUX ÷3 ÷2 clock prescaler analog components analog part 1 f ADCI Condition: f ADCI ≤ 10 MHz, where t ADCI = Figure 13-2 Clocking Scheme User’s Manual ADC, V 0.3 13-3 V 0.2, 2005-01 XC866 Analog-to-Digital Converter For module clock fADC = 26.7 MHz, the analog clock fADCI frequency can be selected as shown in Table 13-1. Table 13-1 26.7 MHz fADCI Frequency Selection CTC 00B 01B 10B 11B (default) Prescaling Ratio ÷2 ÷3 ÷4 ÷ 32 Analog Clock fADCI 13.3 MHz (N.A) 8.9 MHz 6.7 MHz 833.3 kHz Module Clock fADC As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00B when fADC is 26.7 MHz. During slow-down mode where fADC may be reduced to 13.3 MHz, 6.7 MHz etc., CTC can be set to 00B as long as the divided analog clock fADCI does not exceed 10 MHz. However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode. 13.2.1 • • • • Conversion Timing The analog-to-digital conversion procedure consists of the following phases: Synchronization phase (tSYN) Sample phase (tS) Conversion phase Write result phase (tWR) conversion start trigger Sample Phase fADCI BUSY Bit SAMPLE Bit t SYN tS tCONV Conversion Phase Source interrupt Channel interrupt Result interrupt Write Result Phase tWR Figure 13-3 Conversion Timing User’s Manual ADC, V 0.3 13-4 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Synchronization Phase tSYN One fADCI period is required for synchronization between the conversion start trigger (from the digital part) and the beginning of the sample phase (in the analog part). The BUSY and SAMPLE bits will be set with the conversion start trigger. Sample Phase tS During this period, the analog input voltage is sampled. The internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted. The analog voltage is internally fed to a voltage comparator. With the beginning of the sampling phase, the SAMPLE and BUSY flags in register GLOBSTR are set. The duration of this phase is common to all analog input channels and is controlled by bit field STC in register INPCR0: tS = (2 + STC) × tADCI Conversion Phase During the conversion phase, the analog voltage is converted into an 8-bit or 10-bit digital value using the successive approximation technique with a binary weighted capacitor network. At the beginning of the conversion phase, the SAMPLE flag is reset (to indicate the sample phase is over), while the BUSY flag continues to be asserted. The BUSY flag is deasserted only at the end of the conversion phase with the corresponding source interrupt (of the source that started the conversion) asserted. Write Result Phase tWR At the end of the conversion phase, the corresponding channel interrupt (of the converted channel) is asserted three fADCI periods later, after the limit checking has been performed. The result interrupt is asserted, once the conversion result has been written into the target result register. [13.1] User’s Manual ADC, V 0.3 13-5 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Total Conversion Time tCONV The total conversion time (synchronizing + sampling + charge redistribution) tCONV is given by: tCONV = tADC × (1 + r × (3 + n + STC)) where r = CTC + 2 for CTC = 00B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control, STC = Sample Time Control, n = 8 or 10 (for 8-bit and 10-bit conversion, respectively), tADC = 1 / fADC Example: STC = 00H, CTC = 01B, fADC = 26.7 MHz, n = 10, tCONV = tADC × (1 + 3 × (3 + 10 + 0)) = 1.5 µs [13.2] User’s Manual ADC, V 0.3 13-6 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.3 Low Power Mode The ADC module may be disabled, either partially or completely, when no conversion is required in order to reduce power consumption: • The analog part of the ADC module may be disabled by resetting the ANON bit. This causes the generation of fADCI to be stopped and results in a reduction in power consumption. Conversions are possible only by enabling the analog part (ANON = 1) again. The wake-up time is approximately 100 ns. Refer to Section 13.7.1 for register description of disabling the ADC analog part. • If the ADC functionality is not required at all, it can be completely disabled by gating off its clock input (fADC) for maximal power reduction. This is done by setting bit ADC_DIS in register PMCON1 as described below. Refer to Chapter 8.1.4 for details on peripheral clock management. PMCON1 Power Mode Control Register 1 7 6 0 r 5 4 3 T2_DIS rw 2 CCU_DIS rw Reset Value: 00H 1 SSC_DIS rw 0 ADC_DIS rw The function of the shaded bit is not described here Field ADC_DIS Bits 0 Type Description rw ADC Disable Request. Active high. 0 ADC is in normal operation (default) 1 Request to disable the ADC Reserved Returns 0 if read; should be written with 0. 0 [7:4] r User’s Manual ADC, V 0.3 13-7 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4 Functional Description The ADC module functionality includes: • Two different conversion request sources (sequential and parallel) with independent registers. The request sources are used to trigger conversions due to external events (synchronization to PWM signals), sequencing schemes, etc. • An arbiter that regularly scans the request sources to find the channel with the highest priority for the next conversion. The priority of each source can be programmed individually to obtain the required flexibility to cover the desired range of applications. • Control registers for each of the eight channels that define the behavior of each analog input (such as the interrupt behavior, a pointer to a result register, a pointer to a channel class, etc.). • An input class register that delivers general channel control information (sample time) from a centralized location. • Four result registers (instead of one result register per analog input channel) for storing the conversion results and controlling the data reduction. This allows the creation of result data FIFOs. • A decimation stage for conversion results, adding the incoming result to the value already stored in the targeted result register. This stage allows fast consecutive conversions without the risk of data loss for slow CPU clock frequency. channel control 7 .. . channel control 0 analog input 7 ... analog input 0 Figure 13-4 ADC Block Diagram parallel request source 1 (arbitration slot 1) arbiter sequential request source 0 (arbitration slot 0) analog part input class 0 data reduction result register 3 ... result register 0 User’s Manual ADC, V 0.3 13-8 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.1 Request Source Arbiter The arbiter can operate in two modes that are selectable by bit ARBM: • Permanent arbitration: In this mode, the arbiter will continuously poll the request sources even when there is no pending conversion request. • Arbitration started by pending conversion request: In this mode, the arbiter will start polling the request sources only if there is at least one conversion pending request. Once started, the arbiter polls the two request sources (source x at slot x, x = 0 - 1) to find the analog channel with the highest priority that must be converted. For each arbitration slot, the arbiter polls the request pending signal (REQPND) and the channel number valid signal (REQCHNRV) of one request source. The sum of all arbitration slots is called an arbitration round. An arbitration slot must be enabled (ASENx = 1) before it can take part in the arbitration. Each request source has a source priority that can be programmed via bit PRIOx. Starting with request source 0 (arbitration slot 0), the arbiter checks if a request source has a pending request (REQPND = 1) for a conversion. If more than one request source is found with the same programmed priority level and a pending conversion request, the channel specified by the request source that was found first is selected. The REQCHNRV signal is also checked by the arbiter and a conversion can only be started if REQCHNRV = 1 (and REQPND = 1). If both request sources are programmed with the same priority, the channel number specified by request source 0 will be converted first since it is connected to arbitration slot 0. The period tARB of a complete arbitration round is fixed at: tARB = 4 * tADCD Refer to Section 13.7.2 for register description of priority and arbitration control. [13.3] User’s Manual ADC, V 0.3 13-9 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.2 Conversion Start Modes At the end of each arbitration round, the arbiter would have found the request source with the highest priority and a pending conversion request. It stores the arbitration result, namely the channel number, the sample time and the targeted result register for further actions. If the analog part is idle, a conversion can be started immediately. If a conversion is currently running, the arbitration result is compared to the priority of the currently running conversion. If the current conversion has the same or a higher priority, it will continue to completion. Immediately after its completion, the next conversion can begin. As soon as the analog part is idle and the arbiter has output a conversion request, the conversion will start. In case the new conversion request has a higher priority than the current conversion, two conversion start modes exist (selectable by bit CSMx, x = 0 - 1): • Wait-for-Start: In this mode, the current conversion is completed normally. The pending conversion request will be treated immediately after the conversion is completed. The conversion start takes place as soon as possible. • Cancel-Inject-Repeat: In this mode, the current conversion is aborted immediately if a new request with a higher priority has been found. The new conversion is started as soon as possible after the abort action. The aborted conversion request is restored in the request source that has requested the aborted conversion. As a result, it takes part in the next arbitration round. The priority of an active request source (including pending or active conversion) must not be changed by software. The abort will not be accepted during the last 3 clock cycles of a running conversion. Refer to Section 13.7.2 for register description relating to conversion start control. 13.4.3 Channel Control Each channel has its own control information that defines the target result register for the conversion result (see Section 13.7.4). The only control information that is common to all channels is the sampling time defined by the input class register (see Section 13.7.5). User’s Manual ADC, V 0.3 13-10 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.4 Sequential Request Source 13.4.4.1 Overview The sequential request source at arbitration slot 0 requests one conversion after another for channel numbers between 0 and 7. The queue stage stores the requested channel number and some additional control information. As a result, the order in which the channels are to be converted is freely programmable without restrictions in the sequence. The additional control information is used to enable the request source interrupt (when the requested channel conversion is completed) and to enable the automatic refill process. A sequential source consists of a queue stage (Q0R0), a backup stage (QBUR0) and a mode control register (QMR0). The backup stage stores the information about the latest conversion requested after it has been aborted. If the backup register contains an aborted request (V = 1), it is treated before the entry in the queue stage. This implies that only the bit V in the backup register is cleared when the requested conversion is started. If the bit V in the backup register is not set, the bit V in the queue stage is reset when the requested conversion is started. The request source can take part in the source arbitration if the backup stage or queue stage contains a valid request (V = 1). data written by CPU queue input register w 1 queue stage (CHNR, RF, ENSI) rh V backup stage (CHNR, RF, ENSI) rh set reset start of conversion abort of conversion V OR Figure 13-5 Base Structure of Sequential Request Source The automatic refill feature can be activated (RF = 1) to allow automatic re-insertion of the pending request into the queue stage after a successful execution (conversion start). Otherwise, the pending request will be discarded once it is executed. While the automatic refill feature is enabled, software should not write data to the queue input register. The write address in which to enter a conversion request is given by the write-only queue input register (QINR0). If the queue stage is empty (V = 0), the written value will be stored there (bit V becomes set), or else the write action is ignored. User’s Manual ADC, V 0.3 13-11 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Refer to Section 13.7.6 for description of the sequential request source registers. 13.4.4.2 Request Source Control If the conversion requested by the source is not related to an external trigger event (EXTR = 0), the valid bit V = 1 directly requests the conversion by setting signals REQPND and REQCHNRV to 1. In this case, no conversion will be requested if V = 0. A gating mechanism allows the user to enable/disable conversion requests according to bit ENGT. conversion started CEV w OR OR w set reset TREV ENTR rw EV rh AND 1 0 V EXTR rh REQTR ENGT rw 1 0 TRMD rw 0 1 0 1 AND REQPND AND REQCHNRV Figure 13-6 Sequential Request Source Control If the requested conversion is sensitive to an external trigger event (EXTR = 1), the signal REQTR can be taken into account (with ENTR = 1) or the software can write TREV = 1. Both actions set the event flag EV. The event flag EV = 1 indicates that an external event has taken place and a conversion can be requested (EV can be set only if a conversion request is valid with V = 1). In this case, the signal REQCHNRV is derived from bit EV. Bit TRMD (trigger mode) offers the possibility to wait, with the valid bit already set, for an event to be detected before taking part in the arbitration. This ensures that the reaction to an event is with minimum delay. If this feature is not desired (TRMD = 0), the event bit EV can be used to generate both REQPND and REQCHNRV. User’s Manual ADC, V 0.3 13-12 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.5 Parallel Request Source 13.4.5.1 Overview The parallel request source at arbitration slot 1 generates one or more conversion requests for channel numbers between 4 and 7 in parallel. The requests are always treated one after the other (in separate arbitration rounds) in a predefined sequence (higher channel numbers before lower channel numbers). The parallel request source consists of a conversion request control register (CRCR1), a conversion request pending register (CRPR1) and a conversion request mode register (CRMR1). The contents of the conversion request control register are copied (overwrite) to the conversion request pending register when a selected load event (LDE) occurs. The type of the event defines the behavior and the trigger of the request source. The activation of a conversion request to the arbiter may be started if the content of the conversion pending register is not 0. The highest bit position number among the pending bits with values equal to 1 specifies the channel number for conversion. To take part in the source arbitration, both the REQCHNRV and REQPND signals must be 1. Refer to Section 13.7.7 for description of the parallel request source registers. 13.4.5.2 Request Source Control All conversion pending bits are ORed together to deliver an intermediate signal PND for generating REQCHNRV and REQPND. The signal PND is gated with bit ENGT, allowing the user to enable/disable conversion requests. See Figure 13-7. data written by CPU LDE conversion request control register rwh parallel load conversion request pending register rwh ... bitwise OR bitwise set/reset by arbiter ENGT rw PND AND AND 0 1 0 1 REQPND REQCHNRV Figure 13-7 Parallel Request Source Control User’s Manual ADC, V 0.3 13-13 V 0.2, 2005-01 XC866 Analog-to-Digital Converter The load event for a parallel load can be: • External trigger at the input line REQTR. See Section 13.4.5.3. • Write operation to a specific address of the conversion request control register. See Section 13.4.5.4. • Write operation with LDEV = 1 to the request source mode register. See Section 13.4.5.4. • Source internal action (conversion completed and PND = 0 for autoscan mode). See Section 13.4.5.5. Each bit (bit x, x = 4 - 7) in the conversion request control/pending registers corresponds to one analog input channel. The bit position directly defines the channel number. The bits in the conversion request pending register can be set or reset bitwisely by the arbiter: • The corresponding bit in the conversion request pending register is automatically reset when the arbiter indicates the start of conversion for this channel. • The bit is automatically set when the arbiter indicates that the conversion has been aborted. A source interrupt can be generated (if enabled) when a conversion (requested by this source) is completed while PND = 0. These rules apply only if the request source has triggered the conversion. 13.4.5.3 External Trigger The conversion request for the parallel source (and also the sequential source) can be synchronized to an external trigger event. For the parallel source, this is done by coupling the reload event to a request trigger input, REQTR. 13.4.5.4 Software Control The load event for the parallel source can also be generated under software control in two ways: • The conversion request control register can be written at two different addresses (CRCR1 and CRPR1). Accessed at CRCR1, the write action changes only the bits in this register. Accessed at CRPR1, the load event will take place one clock cycle after the write access. This automatic load event can be used to start conversions with a single move operation. In this case, the information about the channels to be converted is given as an argument in the move instruction. • Bit LDEV can be written with 1 by software to trigger the load event. In this case, the load event does not contain any information about the channels to be converted, but always takes the contents of the conversion request control register. This allows the conversion request control register to be written at a second address without triggering the load event. User’s Manual ADC, V 0.3 13-14 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.5.5 Autoscan The autoscan is a functionality of the parallel source. If autoscan mode is enabled, the load event takes place when the conversion is completed while PND = 0, provided the parallel request source has triggered the conversion. This automatic reload feature allows channels 4 and 7 to be constantly scanned for pending conversion requests without the need for external trigger or software action. 13.4.6 Wait-for-Read Mode The wait-for-read mode can be used for all request sources to allow the CPU to treat each conversion result independently without the risk of data loss. Data loss can occur if the CPU does not read a conversion result in a result register before a new result overwrites the previous one. In wait-for-read mode, the conversion request generated by a request source for a specific channel will be disabled (and conversion not possible) if the targeted result register contains valid data (indicated by its valid flag being set). Conversion of the requested channel will not start unless the valid flag of the targeted result register is cleared (data is invalid). The wait-for-read mode for a result register can be enabled by setting bit WFR (see Section 13.7.8). User’s Manual ADC, V 0.3 13-15 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.7 Result Generation 13.4.7.1 Overview The result generation of the ADC module consists of several parts: • A limit checking unit, comparing the conversion result to two selected boundary values (BOUND0 and BOUND1). A channel interrupt can be generated according to the limit check result. • A data reduction filter, accumulating the conversion results. The accumulation is done by adding the new conversion result to the value stored in the selected result register. • Four result registers, storing the conversion results. The software can read the conversion result from the result registers. The result register used to store the conversion result is selected individually for each input channel. analog part conversion result result buffer boundary values add/sub 0 from channel control result register 0 result register 1 VF0 VF1 result register 3 .. . VF3 result path control limit check control channel interrupt DRC event interrupt data reduction control Figure 13-8 Result Path Refer to Section 13.7.8 for description of the result generation registers. User’s Manual ADC, V 0.3 13-16 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.7.2 Limit Checking The limit checking and the data reduction filter are based on a common add/subtract structure. The incoming result is compared with BOUND0, then with BOUND1. Depending on the result flags (lower-than compare), the limit checking unit can generate a channel interrupt. It can become active when the valid result of the data reduction filter is stored in the selected result register. n new result in buffer? y compare result with BOUND0 rw BOUND0 compare result with BOUND1 rw BOUND1 data reduction filter limit checking channel interrupt Figure 13-9 Limit Checking Flow User’s Manual ADC, V 0.3 13-17 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.7.3 Data Reduction Filter Each result register can be controlled to enable or disable the data reduction filter. The data reduction block allows the accumulation of conversion results for anti-aliasing filtering or for averaging. A pseudo-parallel sampling on two analog inputs is possible by converting the channels A - B - B - A in a quick sequence. The result register for A stores the sum of both conversions of channel A and the result register B works similarly for channel B. conversion ready c0 c1 r0 0 DRCTR = 1 1 c2 r1 0 r0 + r1 c3 r2 1 c4 r3 0 r2 + r3 c5 r4 1 c6 r5 0 r4 + r5 c7 r6 1 c8 r7 0 r6 + r7 running conversion delivered result data reduction counter DRC content of result register x valid flag for result register x VFx 0 DRCTR = 0 0 0 r0 0 r1 0 r2 0 r3 0 r4 0 r5 0 r6 0 r7 DRC content of result register x VFx 0 r0 r2 r4 r6 Figure 13-10 Data Reduction Flow If DRC is 0 and a new conversion result comes in, DRC is reloaded with its reload value (defined by bit DRCTR in the result control register) and the value of 0 is added to the conversion result (instead of the previous result register content). Then, the complete result is stored in the selected result register. If the reload value is 0 (data reduction filter disabled), accumulation is done over one conversion. Hence, a result event is generated and the valid bit (VF) for the result register becomes set. If the reload value is 1 (data reduction filter enabled), accumulation is done over two conversions. In this case, neither a result event is generated nor the valid bit is set. User’s Manual ADC, V 0.3 13-18 V 0.2, 2005-01 XC866 Analog-to-Digital Converter If DRC is 1 and a new conversion result comes in, the data reduction filter adds the incoming result to the value already stored in the result register and decrements DRC. After this addition, the complete result is stored in the selected result register. The result event is generated and the valid bit becomes set. It is possible to have an identical cycle behavior of the path to the result register, with the data reduction filter being enabled or disabled. Furthermore, an overflow of the result register is avoided, because a maximum of 2 conversion results are added (a 10-bit result added twice delivers a maximum of 11 bits). 13.4.7.4 Result FIFO Functionality The four result registers can be independently configured to provide a 2, 3 or 4-stage FIFO functionality. This allows the storing of measurement results with ‘relaxed’ CPU access timing. If the FIFO mechanism is enabled (FEN = 1) for result register x (independent from the read views), the following actions take place (the setting of result register x+1 has no influence on these actions). If the valid flag VFx is not set (result register x does not contain valid data) and VFx+1 (of result register x+1) is set, the contents of result register x+1 are transferred to result register x. Furthermore, VFx becomes set and VFx+1 becomes reset. The setting of VFx can generate an event interrupt. A result interrupt x is generated when new data is stored in result register x if the previous register (x-1) is not enabled for FIFO functionality. 13.4.7.5 Result Register View In order to cover a wide range of applications, the content of result register x (x = 0 to 3) is available as different read views at different addresses (see Figure 13-11): • Normal read view RESRxL/H: This view delivers the 8-bit or 10-bit conversion result. • Accumulated read view RESRAxL/H: This view delivers the accumulated 9-bit or 11-bit conversion result. All conversion results (with or without accumulation) are stored in the result registers, but can be viewed at either RESRxL/H or RESRAxL/H which shows different data alignment and width. When the data reduction filter is enabled (DRCTR = 1), read access should be performed on RESRAxL/H as it shows the full 9-bit (R8:R0) or 11-bit (R10:R0) accumulated conversion result. Reading from RESRxL/H gives the appended (MSB unavailable) accumulated result. When the data reduction filter is disabled (DRCTR = 0), the user can read the 8-bit or 10-bit conversion result from either RESRxL/H or RESRAxL/H. In particular, for 8-bit User’s Manual ADC, V 0.3 13-19 V 0.2, 2005-01 XC866 Analog-to-Digital Converter conversion (without accumulation), the result can be read from RESRxH with a single instruction. Hence, depending on the application requirement, the user can choose to read from the different views. Result Register x High 7 6 5 4 3 2 1 0 Result Register x Low 7 6 5 4 3 2 1 CHNR 0 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 VF DRC RESRxH 7 6 5 4 rh RESRxL 2 1 0 7 0 RESRAxH 2 1 CHNR RESRAxL 1 0 7 R0 3 6 0 5 0 4 rh 3 0 7 0 6 5 4 rh 3 2 6 0 5 0 4 rh 3 2 1 CHNR 0 R7 R6 R5 R4 R3 R2 R1 R0 VF DRC R7 R6 R5 R4 R3 R2 R1 VF DRC 8-bit conversion (with/without accumulation) 8-bit conversion (without accumulation) 7 6 5 4 rh 3 2 1 0 7 6 5 0 4 rh 3 2 1 CHNR 0 7 6 5 4 rh 3 2 1 0 7 R0 6 0 5 0 4 rh 3 2 1 CHNR 0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 VF DRC R8 R7 R6 R5 R4 R3 R2 R1 VF DRC 10-bit conversion (with/without accumulation) 8-bit conversion (accumulated 9-bit) 7 0 6 5 4 rh 3 2 1 0 7 6 5 4 rh 3 2 1 CHNR 0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 VF DRC 10-bit conversion (without accumulation) 7 6 5 4 rh 3 2 1 0 7 6 5 4 rh 3 2 1 CHNR 0 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 VF DRC 10-bit conversion (accumulated 11-bit) Figure 13-11 Result Register View User’s Manual ADC, V 0.3 13-20 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.8 Interrupts The ADC module provides 2 service request outputs SR[1:0] that can be activated by different interrupt sources. The interrupt structure of the ADC supports two different types of interrupt sources: • Event Interrupts: Activated by events of the request sources (source interrupts) or result registers (result interrupts). • Channel Interrupts: Activated by the completion of any input channel conversion. They are enabled according to the control bits for the limit checking. The settings are defined individually for each input channel. The interrupt compressor is an OR-combination of all incoming interrupt pulses for each of the SR lines. request sources event interrupt unit to SR0 to SR1 interrupt compressor to SR0 to SR1 SR0 SR1 arbiter limit check unit channel interrupt routing analog part Figure 13-12 Interrupt Overview Refer to Section 13.7.9 for description of the interrupt registers. User’s Manual ADC, V 0.3 13-21 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.8.1 Event Interrupts event 7 event 6 event 5 event 4 rh to SR0 to SR0 CHINF4 AND to SR0 to SR1 to SR0 to SR1 ... to SR1 to SR1 EVINP4 rw interrupt trigger 0 IEN rw event 1 event 0 interrupt trigger 0 ENSI rw CHINF0 rh to SR0 to SR0 . .. to SR1 to SR1 EVINP0 rw AND Figure 13-13 Event Interrupt Structure Event interrupts can be generated by the request sources and the result registers. The event interrupt enable bits are located in the request sources (ENSI) and result register control (IEN). An interrupt node pointer (EVINP) for each event allows the selection of the targeted service output line. A request source event is generated when the requested channel conversion is completed: • Event 0: Request source event of sequential request source 0 (arbitration slot 0) • Event 1: Request source event of parallel request source 1 (arbitration slot 1) A result event is generated according to the data reduction control (see Section 13.4.7.3): • • • • Event 4: Result register event of result register 0 Event 5: Result register event of result register 1 Event 6: Result register event of result register 2 Event 7: Result register event of result register 3 13-22 V 0.2, 2005-01 User’s Manual ADC, V 0.3 XC866 Analog-to-Digital Converter 13.4.8.2 Channel Interrupts The channel interrupts occur when a conversion is completed and the selected limit checking condition is met. As a result, only one channel interrupt can be activated at a time. An interrupt can be triggered according to the limit checking result by comparing the conversion result with two selectable boundaries for each channel. request sources conversion finished boundaries BOUND0 BOUND1 arbiter channel number analog part result limit check unit channel interrupt trigger channel number channel interrupt routing to SR0 to SR1 Figure 13-14 Channel Interrupt Overview The limit checking unit uses two boundaries (BOUND0 and BOUND1) to compare with the conversion result. With these two boundaries, the conversion result space is split into three areas: • Area I: The conversion result is below both boundaries. • Area II: The conversion result is between the two boundaries. • Area III: The conversion result is above both boundaries. After a conversion has been completed, a channel interrupt can be triggered according to the following conditions (selected by the limit check control bit field LCC): • • • • • • • • LCC = 000: No trigger, the channel interrupt is disabled. LCC = 001: A channel interrupt is generated if the conversion result is not in area I. LCC = 010: A channel interrupt is generated if the conversion result is not in area II. LCC = 011: A channel interrupt is generated if the conversion result is not in area III. LCC = 100: A channel interrupt is always generated (regardless of the boundaries). LCC = 101: A channel interrupt is generated if the conversion result is in area I. LCC = 110: A channel interrupt is generated if the conversion result is in area II. LCC = 111: A channel interrupt is generated if the conversion result is in area III. User’s Manual ADC, V 0.3 13-23 V 0.2, 2005-01 XC866 Analog-to-Digital Converter The channel-specific interrupt node pointer CHINPx (x = 0 to 7) selects the service request output (SR[1:0]) that will be activated upon a channel interrupt trigger. See Figure 13-15. CHINF0 rh CHINP0 rw to SR0 CHINF1 rh CHINP1 rw . .. . .. CHINF7 rh CHINP7 rw to SR1 channel number Figure 13-15 Channel Interrupt Routing User’s Manual ADC, V 0.3 13-24 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.4.9 External Trigger Inputs The sequential and parallel request sources has one request trigger input REQTRx (x = 0 - 1) each, through which a conversion request can be started. The input to REQTRx is selected from eight external trigger inputs (ETRx0 to ETRx7) via a multiplexer depending on bit field ETRSELx. It is possible to bypass the synchronization stages for external trigger requests that come synchronous to ADC. This selection is done via bit SYNENx. Refer to Section 13.7.9 for description of the external trigger control registers. ETRx0 ETRx1 syn. stages rising edge detect REQTRx ... ETRx7 ETRSELx rw SYNENx rw Figure 13-16 External Trigger Input The external trigger inputs to the ADC module are driven by events occuring in the CCU6 module. See Table 13-2. Table 13-2 ETRx0 ETRx1 ETRx2 ETRx3 ETRx4 ETRx5 ETRx6 ETRx7 External Trigger Input Source CCU6 Event T13 period-match T13 compare-match T12 period-match T12 compare-match for channel 0 T12 compare-match for channel 1 T12 compare-match for channel 2 Shadow transfer event for multi-channel mode Correct hall event for multi-channel mode External Trigger Input User’s Manual ADC, V 0.3 13-25 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.5 ADC Module Initialization Sequence The following steps is meant to provide a general guideline on how to initialize the ADC module. Some steps may be varied or omitted depending on the application requirements: 1. Configure global control functions: • Select conversion width (GLOBCTR.DW) • Select analog clock fADCI divider ratio (GLOBCTR.CTC) 2. Configure arbitration control functions: • Select request source x – priority (PRAR.PRIOx) – conversion start mode (PRAR.CSMx) • Enable arbitration slot x (PRAR.ASENx) • Select arbitration mode (PRAR.ARBM) 3. Configure channel control information: • Select channel x – limit check control (CHCTRx.LCC) – target result register (CHCTRx.RESRSEL) • Select sample time for all channels (INPCR0.STC) 4. Configure result control information: • Enable/disable result register x – data reduction (RCRx.DRCTR) – event interrupt (RCRx.IEN) – FIFO functionality (RCRx.FEN) – wait-for-read mode (RCRx.WFR) – valid flag reset by read access (RCRx.VFCTR) 5. Configure interrupt control functions: • Select channel x interrupt node pointer (CHINPR.CHINPx) • Select event x interrupt node pointer (CHINPR.EVINFx) 6. Configure limit check boundaries: • Select limit check boundaries for all channels (LCBR.BOUND0, LCBR.BOUND1) 7. Configure external trigger control functions: • Select source x external trigger input (ETRCR.ETRSELx) • Enable/disable source x external trigger input synchronization (ETRCR.SYNENx) 8. Setup sequential source: • Enable conversion request (QMR0.ENGT) • Enable/disable external trigger (QMR0.ENTR) • Select trigger mode (QMR0.TRMD) User’s Manual ADC, V 0.3 13-26 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 9. Setup parallel source: • Enable conversion request (CRMR1.ENGT) • Enable/disable external trigger (CRMR1.ENTR) • Enable/disable source interrupt (CRMR1.ENSI) • Enable/disable autoscan (CRMR1.SCAN) 10.Turn on analog part: • Set GLOBCTR.ANON (wait for 100 ns) 11.Start sequential request: • Write to QINR0 (with information such as REQCHNR, RF, ENSI and EXTR) • Generate a pending conversion request using any method described in Section 13.4.4.2 12.Start parallel request: • Write to CRCR1 (no load event) or CRPR1 (automatic load event) the channels to be converted. • Generate a load event (if not already available) to trigger a pending conversion request, using any method described in Section 13.4.5.2 13.Wait for ADC conversion to be completed: • The source interrupt indicates that the conversion requested by the source is completed. • The channel interrupt indicates that the corresponding channel conversion is completed (with limit check performed). • The result interrupt indicates that the result (with/without accumulation or FIFO) in the corresponding result register is ready and can be read. 14.Read ADC result User’s Manual ADC, V 0.3 13-27 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.6 Register Map The ADC SFRs are located in the standard memory area (RMAP = 0) and are organized into 7 pages. The ADC_PAGE register is located at address D1H. It contains the page value and page control information. ADC_PAGE Page Register for ADC 7 OP w 6 5 STNR w 4 3 0 r 2 Reset Value: 00H 1 PAGE rw 0 Field PAGE Bits [2:0] Type Description rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. STNR [5:4] w User’s Manual ADC, V 0.3 13-28 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Field OP Bits [7:6] Type Description w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions of PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. Reserved Returns 0 if read, should be written with 0. 0 3 r User’s Manual ADC, V 0.3 13-29 V 0.2, 2005-01 XC866 Analog-to-Digital Converter All ADC register names described in the following sections will be referenced in other chapters of this document with the module name prefix “ADC_”, e.g., ADC_GLOBCTR. The addresses of the ADC SFRs are listed in Table 13-3 and Table 13-4. Table 13-3 Address CAH CBH CCH CDH CEH CFH D2H D3H Table 13-4 Address CAH CBH CCH CDH CEH CFH D2H D3H SFR Address List for Pages 0-2 Page 0 GLOBCTR GLOBSTR PRAR LCBR INPCR0 ETRCR – – Page 1 CHCTR0 CHCTR1 CHCTR2 CHCTR3 CHCTR4 CHCTR5 CHCTR6 CHCTR7 Page 2 RESR0L RESR0H RESR1L RESR1H RESR2L RESR2H RESR3L RESR3H SFR Address List for Pages 3-6 Page 3 RESRA0L RESRA0H RESRA1L RESRA1H RESRA2L RESRA2H RESRA3L RESRA3H Page 4 RCR0 RCR1 RCR2 RCR3 VFCR – – – Page 5 CHINFR CHINCR CHINSR CHINPR EVINFR EVINCR EVINSR EVINPR Page 6 CRCR1 CRPR1 CRMR1 QMR0 QSR0 Q0R0 QBUR0/QINR0 – User’s Manual ADC, V 0.3 13-30 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7 13.7.1 Register Description General Function Registers Register GLOBCTR contains bits that control the analog converter and the conversion delay. GLOBCTR Global Control Register 7 ANON rw 6 DW rw 5 CTC rw 4 3 2 0 r Reset Value: 30H 1 0 Field CTC Bits [5:4] Type Description rw Conversion Time Control This bit field defines the divider ratio for the divider stage of the internal analog clock fADCI. This clock provides the internal time base for the conversion and sample time calculations. 00 fADCI = 1/2 × fADCA 01 fADCI = 1/3 × fADCA 10 fADCI = 1/4 × fADCA 11 fADCI = 1/32 × fADCA (default) Data Width This bit defines the conversion resolution. 0 The result is 10 bits wide (default). 1 The result is 8 bits wide. Analog Part Switched On This bit enables the analog part of the ADC module and defines its operation mode. 0 The analog part is switched off and conversions are not possible. To achieve minimal power consumption, the internal analog circuitry is in its power-down state and the generation of fADCI is stopped. 1 The analog part of the ADC module is switched on and conversions are possible. The automatic power-down capability of the analog part is disabled. DW 6 rw ANON 7 rw User’s Manual ADC, V 0.3 13-31 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Field 0 Bits [3:0] Type Description r Reserved Returns 0 if read; should be written with 0. Register GLOBSTR contains bits that indicate the current status of a conversion. GLOBSTR Global Status Register 7 0 r 6 5 4 CHNR rh 3 2 0 r Reset Value: 00H 1 SAMPLE rh 0 BUSY rh Field BUSY Bits 0 Type Description rh Analog Part Busy This bit indicates that a conversion is currently active. 0 The analog part is idle. 1 A conversion is currently active. Sample Phase This bit indicates that an analog input signal is currently sampled. 0 The analog part is not in the sampling phase. 1 The analog part is in the sampling phase. Channel Number This bit field indicates which analog input channel is currently converted. This information is updated when a new conversion is started. Reserved Returns 0 if read; should be written with 0. SAMPLE 1 rh CHNR [5:3] rh 0 2, [7:6] r User’s Manual ADC, V 0.3 13-32 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7.2 Priority and Arbitration Register Register PRAR contains bits that define the request source priority and the conversion start mode. It also contains bits that enable/disable the conversion request treatment in the arbitration slots. PRAR Priority and Arbitration Register 7 ASEN1 rw 6 ASEN0 rw 5 0 r 4 ARBM rw 3 CSM1 rw 2 PRIO1 rw Reset Value: 00H 1 CSM0 rw 0 PRIO0 rw Field PRIO0 Bits 0 Type Description rw Priority of Request Source 0 This bit defines the priority of the sequential request source 0. 0 Low priority 1 High priority Conversion Start Mode of Request Source 0 This bit defines the conversion start mode of the sequential request source 0. 0 The wait-for-start mode is selected. 1 The cancel-inject-repeat mode is selected. Priority of Request Source 1 This bit defines the priority of the parallel request source 1. 0 Low priority 1 High priority Conversion Start Mode of Request Source 1 This bit defines the conversion start mode of the parallel request source 1. 0 The wait-for-start mode is selected. 1 The cancel-inject-repeat mode is selected. Arbitration Mode This bit defines which arbitration mode is selected. 0 Permanent arbitration (default) 1 Arbitration started by pending conversion request CSM0 1 rw PRIO1 2 rw CSM1 3 rw ARBM 4 rw User’s Manual ADC, V 0.3 13-33 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Field ASENx (x = 0 - 1) Bits [7:6] Type Description rw Arbitration Slot x Enable Each bit enables an arbitration slot of the arbiter round. ASEN0 enables arbitration slot 0, ASEN1 enables slot 1. If an arbitration slot is disabled, a pending conversion request of a request source connected to this slot is not taken into account for arbitration. 0 The corresponding arbitration slot is disabled. 1 The corresponding arbitration slot is enabled. Reserved Returns 0 if read; should be written with 0. 0 5 r User’s Manual ADC, V 0.3 13-34 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7.3 External Trigger Control Register Register ETRCR contains bits that select the external trigger input signal source and enable synchronization of the external trigger input. ETRCR External Trigger Control Register 7 SYNEN1 rw 6 SYNEN0 rw 5 4 ETRSEL1 rw 3 2 Reset Value: 00H 1 ETRSEL0 rw 0 Field ETRSELx (x = 0 - 1) Bits [2:0], [5:3] Type Description rw External Trigger Selection for Request Source x This bit field defines which external trigger input signal is selected. 000 The trigger input ETRx0 is selected. 001 The trigger input ETRx1 is selected. ..... ..... 111 The trigger input ETRx7 is selected. Synchronization Enable 0 Synchronizing stage is not in external trigger input REQTRx path. 1 Synchronizing stage is in external trigger input REQTRx path. SYNENx (x = 0 - 1) 6, 7 rw User’s Manual ADC, V 0.3 13-35 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7.4 Channel Control Registers The channel control registers contain bits that select the targeted result register and control the limit check mechanism. Register CHCTRx defines the settings for the input channel x. CHCTRx (x = 0 - 7) Channel Control Register x 7 0 r 6 5 LCC rw 4 3 0 r 2 Reset Value: 00H 1 RESRSEL rw 0 Field RESRSEL Bits [1:0] Type Description rw Result Register Selection This bit field defines which result register will be the target of a conversion of this channel. 00 The result register 0 is selected. 01 The result register 1 is selected. 10 The result register 2 is selected. 11 The result register 3 is selected. Limit Check Control This bit field defines the behavior of the limit checking mechanism. See coding in Section 13.4.8.2. Reserved Returns 0 if read; should be written with 0. LCC [6:4] rw 0 [3:2], 7 r User’s Manual ADC, V 0.3 13-36 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7.5 Input Class Register Register INPCR0 contains bits that control the sample time for the input channels. INPCR0 Input Class 0 Register 7 6 5 4 STC rw 3 2 Reset Value: 00H 1 0 Field STC Bits [7:0] Type Description rw Sample Time Control This bit field defines the additional length of the sample time, given in terms of fADCI clock cycles. A sample time of 2 analog clock cycles is extended by the programmed value. User’s Manual ADC, V 0.3 13-37 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7.6 Sequential Source Registers These registers contain the control and status bits of sequential request source 0. Register QMR0 contains bits that are used to set the sequential request source in the desired mode. QMR0 Queue Mode Register 7 CEV w 6 TREV w 5 FLUSH w 4 CLRV w 3 TRMD rw 2 ENTR rw Reset Value: 00H 1 0 r 0 ENGT rw Field ENGT Bits 0 Type Description rw Enable Gate This bit enables the gating functionality for the request source. 0 The gating line is permanently 0. The source is switched off. 1 The gating line is permanently 1. The source is switched on. Enable External Trigger This bit enables the external trigger possibility. If enabled, bit EV is set if a rising edge is detected at the external trigger input REQTR when at least one V bit is set in register Q0R0 or QBUR0. 0 The external trigger is disabled. 1 The external trigger is enabled. Trigger Mode This bit defines which trigger mode is selected. In trigger mode 0, the output lines REQPND and REQCHNRV can become active at the same time. In trigger mode 1, the signal REQPND can become active before REQCHNRV. 0 Trigger mode 0 is selected. 1 Trigger mode 1 is selected. Clear V Bits 0 No action 1 The bit V in register Q0R0 or QBUR0 is reset. If QBUR0.V = 1, then QBUR0.V is reset. If QBUR0.V = 0, then Q0R0.V is reset. 13-38 V 0.2, 2005-01 ENTR 2 rw TRMD 3 rw CLRV 4 w User’s Manual ADC, V 0.3 XC866 Analog-to-Digital Converter Field FLUSH Bits 5 Type Description w Flush Queue 0 No action 1 All bits V in the queue registers and bit EV are reset. The queue contains no more valid entry. Trigger Event 0 No action 1 A trigger event is generated by software. If the source waits for a trigger event, a conversion request is started. Clear Event Bit 0 No action 1 Bit EV is cleared. Reserved Returns 0 if read; should be written with 0. TREV 6 w CEV 7 w 0 1 r User’s Manual ADC, V 0.3 13-39 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Register QSR0 contains bits that indicate the status of the sequential source. QSR0 Queue Status Register 7 0 r 6 5 EMPTY rh 4 EV rh 3 2 0 r Reset Value: 20H 1 0 Field EV Bits 4 Type Description rh Event Detected This bit indicates that an event has been detected while V = 1. Once set, this bit is reset automatically when the requested conversion is started. 0 An event has not been detected. 1 An event has been detected. Queue Empty This bit indicates if the queue (Q0R0) contains a valid entry. It is incremented each time a new entry is written to QINR0. It is decremented each time a conversion request from the queue is started. A new entry is ignored if the queue is filled (EMPTY = 0). 0 The queue is filled (1 valid entry). 1 The queue is empty. Reserved Returns 0 if read; should be written with 0. EMPTY 5 rh 0 [3:0], [7:6] r Register Q0R0 contains bits that monitor the status of the current sequential request. Q0R0 Queue 0 Register 0 7 EXTR rh 6 ENSI rh 5 RF rh 4 V rh 3 0 r 2 Reset Value: 00H 1 REQCHNR rh 0 User’s Manual ADC, V 0.3 13-40 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Field REQCHNR Bits [2:0] Type Description rh Request Channel Number This bit field indicates the channel number that will be or is currently requested. Request Channel Number Valid This bit indicates if the data in REQCHNR, RF, ENSI and EXTR is valid. Bit V is set when a valid entry is written to the queue input register QINR0 (or by an update by intermediate queue registers). 0 The data is not valid. 1 The data is valid. Refill This bit indicates if the pending request is discarded after being executed (conversion start) or if it is automatically refilled in the top position of the request queue. 0 The request is discarded after conversion start. 1 The request is refilled in the queue after conversion start. Enable Source Interrupt This bit indicates if a source interrupt will be generated when the conversion is completed. The interrupt trigger becomes activated if the conversion requested by the source has been completed and ENSI = 1. 0 The source interrupt generation is disabled. 1 The source interrupt generation is enabled. External Trigger This bit defines if the conversion request is sensitive to an external trigger event. The event flag (bit EV) indicates if an external event has taken place and a conversion can be requested. 0 Bit EV not used to start conversion request. 1 Bit EV is used to start conversion request. Reserved Returns 0 if read; should be written with 0. V 4 rh RF 5 rh ENSI 6 rh EXTR 7 rh 0 3 r User’s Manual ADC, V 0.3 13-41 V 0.2, 2005-01 XC866 Analog-to-Digital Converter The registers QBUR0 and QINR0 share the same register address. A read operation at this register address will deliver the ‘rh’ bits of the QBUR0 register, while a write operation to the same address will target the ‘w’ bits of the QINR0 register. Register QBUR0 contains bits that monitor the status of an aborted sequential request. QBUR0 Queue Backup Register 0 7 EXTR rh 6 ENSI rh 5 RF rh 4 V rh 3 0 r 2 Reset Value: 00H 1 REQCHNR rh 0 Field REQCHNR Bits [2:0] Type Description rh Request Channel Number This bit field is updated by bit field Q0R0.REQCHNR when the conversion requested by Q0Rs is started. Request Channel Number Valid This bit indicates if the data in REQCHNR, RF, ENSI, and EXTR is valid. Bit V is set if a running conversion is aborted. It is reset when the conversion is started. 0 The backup register does not contain valid data, because the conversion described by this data has not been aborted. 1 The data is valid. The aborted conversion is requested before taking into account what is requested by Q0R0. Refill This bit is updated by bit Q0R0.RF when the conversion requested by Q0R0 is started. Enable Source Interrupt This bit is updated by bit Q0R0.ENSI when the conversion requested by Q0R0 is started. External Trigger This bit is updated by bit Q0R0.EXTR when the conversion requested by Q0R0 is started. Reserved Returns 0 if read; should be written with 0. V 4 rh RF 5 rh ENSI 6 rh EXTR 7 rh 0 3 r User’s Manual ADC, V 0.3 13-42 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Register QINR0 is the entry register for sequential requests. QINR0 Queue Input Register 0 7 EXTR w 6 ENSI w 5 RF w 4 0 r 3 2 Reset Value: 00H 1 REQCHNR w 0 Field REQCHNR RF ENSI EXTR 0 Bits [2:0] 5 6 7 [4:3] Type Description w w w w r Request Channel Number This bit field defines the requested channel number. Refill This bit defines the refill functionality. Enable Source Interrupt This bit defines the source interrupt functionality. External Trigger This bit defines the external trigger functionality. Reserved Returns 0 if read; should be written with 0. User’s Manual ADC, V 0.3 13-43 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7.7 Parallel Source Registers These registers contain the control and status bits of parallel request source 1. Register CRCR1 contains the bits that are copied to the pending register (CRPR1) when the load event occurs. This register can be accessed at two different addresses (one read view, two write views). The first address for read and write access is the address given for CRCR1. The second address for write actions is given for CRPR1. A write operation to CRPR1 leads to a data write to the bits in CRCR1 with an automatic load event one clock cycle later. CRCR1 Conversion Request Control Register 1 7 CH7 rwh 6 CH6 rwh 5 CH5 rwh 4 CH4 rwh 3 2 0 r Reset Value: 00H 1 0 Field CHx (x = 4 - 7) Bits x Type Description rwh Channel Bit x Each bit corresponds to one analog channel, the channel number x is defined by the bit position in the register. The corresponding bit x in the conversion request pending register will be overwritten by this bit when the load event occurs. 0 The analog channel x will not be requested for conversion by the parallel request source. 1 The analog channel x will be requested for conversion by the parallel request source. Reserved Returns 0 if read; should be written with 0. 0 [3:0] r User’s Manual ADC, V 0.3 13-44 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Register CRPR1 contains bits that request a conversion of the corresponding analog channel. The bits in this register have only a read view. A write operation to this address leads to a data write to CRCR1 with an automatic load event one clock cycle later. CRPR1 Conversion Request Pending Register 1 7 CHP7 rwh 6 CHP6 rwh 5 CHP5 rwh 4 CHP4 rwh 3 2 0 r Reset Value: 00H 1 0 Field CHPx (x = 4 - 7) Bits x Type Description rwh Channel Pending Bit x Write view: A write to this address targets the bits in register CRCR1. Read view: Each bit corresponds to one analog channel; the channel number x is defined by the bit position in the register. The arbiter automatically resets (at start of conversion) or sets it again (at abort of conversion) for the corresponding analog channel. 0 The analog channel x is not requested for conversion by the parallel request source. 1 The analog channel x is requested for conversion by the parallel request source. Reserved Returns 0 if read; should be written with 0. 0 [3:0] r Note: The bits that can be read from this register location are generally ‘rh’. They cannot be modified directly by a write operation. A write operation modifies the bits in CRCR1 (that is why they are marked ‘rwh’) and leads to a load event one clock cycle later. User’s Manual ADC, V 0.3 13-45 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Register CRMR1 contains bits that are used to set the request source in the desired mode. CRMR1 Conversion Request Mode Register 1 7 0 r 6 LDEV w 5 CLRPND w 4 SCAN rw 3 ENSI rw 2 ENTR rw Reset Value: 00H 1 0 r 0 ENGT rw Field ENGT Bits 0 Type Description rw Enable Gate This bit enables the gating functionality for the request source. 0 The gating line is permanently 0. The source is switched off. 1 The gating line is permanently 1. The source is switched on. Enable External Trigger This bit enables the external trigger possibility. If enabled, the load event takes place if a rising edge is detected at the external trigger input REQTR. 0 The external trigger is disabled. 1 The external trigger is enabled. Enable Source Interrupt This bit enables the request source interrupt. This interrupt can be generated when the last pending conversion is completed for this source (while PND = 0). 0 The source interrupt is disabled. 1 The source interrupt is enabled. Autoscan Enable This bit enables the autoscan functionality. If enabled, the load event is automatically generated when a conversion (requested by this source) is completed and PND = 0. 0 The autoscan functionality is disabled. 1 The autoscan functionality is enabled. ENTR 2 rw ENSI 3 rw SCAN 4 rw User’s Manual ADC, V 0.3 13-46 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Field CLRPND Bits 5 Type Description w Clear Pending Bits 0 No action 1 The bits in register CRPR1 are reset. Generate Load Event 0 No action 1 The load event is generated. Reserved Returns 0 if read; should be written with 0. LDEV 6 w 0 1, 7 r User’s Manual ADC, V 0.3 13-47 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7.8 Result Registers The result registers deliver the conversion results and, optionally, the channel number that has lead to the latest update of the result register. The result registers are available as different read views at different addresses. The following bit fields can be read from the result registers, depending on the selected read address. For details on the conversion result alignment and width, see Section 13.4.7.5. Field Bits Type Description rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter. RESULT RESRxL[7:6], RESRxH or RESRAxL[7:5], RESRAxH CHNR [2:0] rh Channel Number This bit field contains the channel number of the latest register update. Data Reduction Counter This bit indicates how many conversion results have still to be accumulated to generate the final result for data reduction. 0 The final result is available in the result register. The valid flag is automatically set when this bit field is set to 0. 1 One more conversion result must be added to obtain the final result in the result register. The valid flag is automatically reset when this bit field is set to 1. Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid. 0 The result register x does not contain valid data. 1 The result register x contains valid data. DRC 3 rh VF 4 rh User’s Manual ADC, V 0.3 13-48 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Normal Read View RESRx This view delivers the 8-bit or 10-bit conversion result and a 3-bit channel number. The corresponding valid flag is cleared when the high byte of the register is accessed by a read command, provided that bit RCRx.VFCR is set. RESRxL (x = 0 - 3) Result Register x Low 7 6 5 0 r 4 VF rh 3 DRC rh 2 Reset Value: 00H 1 CHNR rh 0 RESULT[1:0] rh RESRxH (x = 0 - 3) Result Register x High 7 6 5 4 3 2 Reset Value: 00H 1 0 RESULT[9:2] rh Accumulated Read View RESRAx This view delivers the accumulated 9-bit or 11-bit conversion result and a 3-bit channel number. The corresponding valid flag is cleared when the high byte of the register is accessed by a read command, provided that bit RCRx.VFCR is set. RESRAxL (x = 0 - 3) Result Register x, View A Low 7 6 RESULT[2:0] rh 5 4 VF rh 3 DRC rh 2 Reset Value: 00H 1 CHNR rh 0 RESRAxH (x = 0 - 3) Result Register x, View A High 7 6 5 4 3 2 Reset Value: 00H 1 0 RESULT[10:3] rh User’s Manual ADC, V 0.3 13-49 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Writing a 1 to a bit position in register VFCR clears the corresponding valid flag in registers RESRx/RESRAx. If a hardware event triggers the setting of a bit VFx and VFCx = 1, the bit VFx is cleared (software overrules hardware). VFCR Valid Flag Clear Register 7 6 0 r 5 4 3 VFC3 w 2 VFC2 w Reset Value: 00H 1 VFC1 w 0 VFC0 w Field VFCx (x = 0 - 3) 0 Bits x Type Description w Clear Valid Flag for Result Register x 0 No action 1 Bit VFR.x is reset. Reserved Returns 0 if read; should be written with 0. [7:4] r The result control registers RCRx contain bits that control the behavior of the result registers and monitor their status. RCRx (x = 0 - 3) Result Control Register x 7 VFCTR rw 6 WFR rw 5 FEN rw 4 IEN rw 3 2 0 r Reset Value: 00H 1 0 DRCTR rw User’s Manual ADC, V 0.3 13-50 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Field DRCTR Bits 0 Type Description rw Data Reduction Control This bit defines how many conversion results are accumulated for data reduction. It defines the reload value for bit DRC. 0 The data reduction filter is disabled. The reload value for DRC is 0, so the accumulation is done over 1 conversion. 1 The data reduction filter is enabled. The reload value for DRC is 1, so the accumulation is done over 2 conversions. Interrupt Enable This bit enables the event interrupt related to the result register x. An event interrupt can be generated when DRC is set to 0 (after decrementing or by reload). 0 The event interrupt is disabled. 1 The event interrupt is enabled. FIFO Enable This bit enables the FIFO functionality for result register x. 0 The FIFO functionality is disabled. 1 The FIFO functionality is enabled. Wait-for-Read Mode This bit enables the wait-for-read mode for result register x. 0 The wait-for-read mode is disabled. 1 The wait-for-read mode is enabled. Valid Flag Control This bit enables the reset of valid flag (by read access to high byte) for result register x. 0 VF unchanged by read access to RESRxH/ RESRAxH. (default) 1 VF reset by read access to RESRxH/ RESRAxH. Reserved Returns 0 if read; should be written with 0. IEN 4 rw FEN 5 rw WFR 6 rw VFCTR 7 rw 0 [3:1] r User’s Manual ADC, V 0.3 13-51 V 0.2, 2005-01 XC866 Analog-to-Digital Converter 13.7.9 Interrupt Registers Register CHINFR monitors the activated channel interrupt flags. CHINFR Channel Interrupt Flag Register 7 CHINF7 rh 6 CHINF6 rh 5 CHINF5 rh 4 CHINF4 rh 3 CHINF3 rh 2 CHINF2 rh Reset Value: 00H 1 CHINF1 rh 0 CHINF0 rh Field CHINFx (x = 0 - 7) Bits x Type Description rh Interrupt Flag for Channel x This bit monitors the status of the channel interrupt x. 0 A channel interrupt for channel x has not occurred. 1 A channel interrupt for channel x has occurred. Writing a 1 to a bit position in register CHINCR clears the corresponding channel interrupt flag in register CHINFR. If a hardware event triggers the setting of a bit CHINFx and CHINCx = 1, the bit CHINFx is cleared (software overrules hardware). CHINCR Channel Interrupt Clear Register 7 CHINC7 w 6 CHINC6 w 5 CHINC5 w 4 CHINC4 w 3 CHINC3 w 2 CHINC2 w Reset Value: 00H 1 CHINC1 w 0 CHINC0 w Field CHINCx (x = 0 - 7) Bits x Type Description w Clear Interrupt Flag for Channel x 0 No action 1 Bit CHINFR.x is reset. User’s Manual ADC, V 0.3 13-52 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Writing a 1 to a bit position in register CHINSR sets the corresponding channel interrupt flag in register CHINFR and generates an interrupt pulse. CHINSR Channel Interrupt Set Register 7 CHINS7 w 6 CHINS6 w 5 CHINS5 w 4 CHINS4 w 3 CHINS3 w 2 CHINS2 w Reset Value: 00H 1 CHINS1 w 0 CHINS0 w Field CHINSx (x = 0 - 7) Bits x Type Description w Set Interrupt Flag for Channel x 0 No action 1 Bit CHINFR.x is set and an interrupt pulse is generated. The bits in register CHINPR define the service request output line, SRx (x = 0 or 1), that is activated if a channel interrupt is generated. CHINPR Channel Interrupt Node Pointer Register 7 CHINP7 rw 6 CHINP6 rw 5 CHINP5 rw 4 CHINP4 rw 3 CHINP3 rw 2 CHINP2 rw Reset Value: 00H 1 CHINP1 rw 0 CHINP0 rw Field CHINPx (x = 0 - 7) Bits x Type Description rw Interrupt Node Pointer for Channel x This bit defines which SR lines becomes activated if the channel x interrupt is generated. 0 The line SR0 becomes activated. 1 The line SR1 becomes activated. User’s Manual ADC, V 0.3 13-53 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Register EVINFR monitors the activated event interrupt flags. EVINFR Event Interrupt Flag Register 7 EVINF7 rh 6 EVINF6 rh 5 EVINF5 rh 4 EVINF4 rh 3 0 r 2 Reset Value: 00H 1 EVINF1 rh 0 EVINF0 rh Field Bits Type Description rh Interrupt Flag for Event x This bit monitors the status of the event interrupt x. 0 An event interrupt for event x has not occurred. 1 An event interrupt for event x has occurred. Reserved Returns 0 if read; should be written with 0. EVINFx [1:0], (x = 0 - 1, 4 - 7) [7:4] 0 [3:2] r Writing a 1 to a bit position in register EVINCR clears the corresponding event interrupt flag in register EVINFR. If a hardware event triggers the setting of a bit EVINFx and EVINCx = 1, the bit EVINFx is cleared (software overrules hardware). EVINCR Event Interrupt Clear Flag Register 7 EVINC7 w 6 EVINC6 w 5 EVINC5 w 4 EVINC4 w 3 0 r 2 Reset Value: 00H 1 EVINC1 w 0 EVINC0 w Field Bits Type Description w Clear Interrupt Flag for Event x 0 No action 1 Bit EVINFR.x is reset. Reserved Returns 0 if read; should be written with 0. EVINCx [1:0], (x = 0 - 1, 4 - 7) [7:4] 0 [3:2] r User’s Manual ADC, V 0.3 13-54 V 0.2, 2005-01 XC866 Analog-to-Digital Converter Writing a 1 to a bit position in register EVINSR sets the corresponding event interrupt flag in register EVINFR and generates an interrupt pulse (if the interrupt is enabled). EVINSR Event Interrupt Set Flag Register 7 EVINS7 w 6 EVINS6 w 5 EVINS5 w 4 EVINS4 w 3 0 r 2 Reset Value: 00H 1 EVINS1 w 0 EVINS0 w Field Bits Type Description w Set Interrupt Flag for Event x 0 No action 1 Bit EVINFR.x is set. Reserved Returns 0 if read; should be written with 0. EVINSx [1:0], (x = 0 - 1, 4 - 7) [7:4] 0 [3:2] r The bits in register EVINPR define the service request output line, SRx (x = 0 or 1), that is activated if an event interrupt is generated. EVINPR Event Interrupt Node Pointer Register 7 EVINP7 rw 6 EVINP6 rw 5 EVINP5 rw 4 EVINP4 rw 3 0 r 2 Reset Value: 00H 1 EVINP1 rw 0 EVINP0 rw Field Bits Type Description rw Interrupt Node Pointer for Event 0 This bit defines which SR lines becomes activated if the event 0 interrupt is generated. 0 The line SR0 becomes activated. 1 The line SR1 becomes activated. Reserved Returns 0 if read; should be written with 0. EVINPx [1:0], (x = 0 - 1, 4 - 7) [7:4] 0 [3:2] r User’s Manual ADC, V 0.3 13-55 V 0.2, 2005-01 XC866 Analog-to-Digital Converter The bit fields in register LCBR define the four MSB of the compare values (boundaries) used by the limit checking unit. The values defined in bit fields BOUND0 and BOUND1 are concatenated with either four (8-bit conversion) or six (10-bit conversion) 0s at the end to form the final value used for comparison with the converted result. For example, the reset value of BOUND1 (BH) will translate into B0H for an 8-bit comparison, and 2C0H for a 10-bit comparison. LCBR Limit Check Boundary Register 7 6 BOUND1 rw 5 4 3 2 BOUND0 rw Reset Value: B7H 1 0 Field BOUNDx (x = 0 - 1) Bits [3:0], [7:4] Type Description rw Boundary for Limit Checking This bit field defines the four MSB of the compare value used by the limit checking unit. The result of the limit check is used for interrupt generation. User’s Manual ADC, V 0.3 13-56 V 0.2, 2005-01 XC866 On-Chip Debug Support 14 On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: • • • • use the built-in debug functionality of the XC800 Core add a minimum of hardware overhead provide support for most of the operations by a Monitor Program use standard interfaces to communicate with the Host (a Debugger) Features: • • • • • Set breakpoints on instruction address and within a specified address range Set breakpoints on internal RAM address Support unlimited software breakpoints in Flash/RAM code region Process external breaks Step through the program code User’s Manual OCDS, V 0.2 14-1 V 0.2, 2005-01 XC866 Functional Description 14.1 Functional Description The OCDS functional blocks are shown in Figure 14-1. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control signals and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is accessed through the JTAG1), which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application. The dedicated MBC pin is used for external configuration and debugging control. Note: All the debug functionality described here can normally be used only after XC866 has been started in OCDS mode. Note: For more information on boot configuration options, see Chapter 7.2.3. JTAG Module Primary Debug Interface TMS TCK TDI TDO TCK TDI TDO Control Reset JTAG Memory Control Unit User Boot/ Program Monitor Memory ROM Monitor & Bootstrap loader Control line MBC OCDS Interrupt Monitor Mode Control System Control Unit NMI Report User Internal RAM Monitor RAM CPU Reset Clock - parts of OCDS Reset Clock Debug PROG PROG Memory Interface & IRAM Data Control Addresses XC800 Figure 14-1 XC866 OCDS: Block Diagram 1) The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system. User’s Manual OCDS, V 0.2 14-2 V 0.2, 2005-01 XC866 On-Chip Debug Support 14.2 Debugging The on-chip debug system can be described in two parts. The first part covers the generation of Debug Events and the second part describes the Debug Actions that are taken when a debug event is generated. • Debug events: – Hardware Breakpoints – Software Breakpoints – External Breaks • Debug event actions: – Call the Monitor Program – Activate the MBC pin The XC866 debug operation is based on close interaction between the OCDS hardware and a specialized software called the Monitor program. 14.2.1 Debug Events The OCDS system recognizes a number of different debug events, which are also called breakpoints or simply breaks. Depending on how the break events are processed in time, they can be classified into three types of breakpoints: • Break Before Make The break happens just before the break instruction, i.e. the instruction causing the break, is executed. Therefore, the break instruction itself will be the next instruction from the user program flow but executed only after the relevant debug action has been taken. • Break After Make The break happens immediately after the break instruction causing it has been executed. Therefore, the break instruction itself has already been executed when the relevant debug action is taken. • Break Now The events of this type are asynchronous to the code execution inside the XC866 and there is no “instruction causing the debug event” in this case. The debug action is performed by OCDS “as soon as possible” once the debug event is raised. User’s Manual OCDS, V 0.2 14-3 V 0.2, 2005-01 XC866 Debugging 14.2.1.1 Hardware Breakpoints Hardware breakpoints are generated by observing certain address buses within the XC866 system. The bus relevant to the hardware breakpoint type is continuously compared against certain registers where addresses for the breakpoints have been programmed. The hardware breakpoints can be classified under two types: • depending on the address bus supervised – Breakpoints on Instruction Address Program Memory Address (PROGA) is observed – Breakpoints on IRAM Address Internal Data Memory Addresses (SOURCE_A, DESTIN_A) are observed • depending on the way comparison is done – Equal breakpoints Comparison is done only against one value; the break event is raised when only this value is matched. – Range breakpoints Comparison is done against two values; the break event is raised when a value observed is found belonging to the range between two programmed values (inclusively). Breakpoints on Instruction Address These Instruction Pointer (IP) breakpoints are generated when a break address is matched for the first byte of an instruction that is going to be executed i.e., for the address within Program Memory where an instruction opcode is to be fetched from. Note: In the cases of 2- and 3-byte instructions, the break will not be generated for addresses of the second and third instruction bytes. If the IP breakpoints are of the Break Before Make type, the instruction at the breakpoint will be executed only after the proper debug action is taken. The OCDS in XC866 supports both equal breakpoints and range breakpoints on Instruction address (see “Configurations of Hardware Breakpoints” on Page 14-5). Breakpoints on IRAM Address These breakpoints are generated when a break address is matched with the address from the Internal Data Memory (IRAM), to which location an instruction performs read or write access. The IRAM breakpoints are of the Break After Make type; the proper debug action is taken immediately after the operation to the breakpoint address is already performed. The OCDS in XC866 supports only range breakpoints on IRAM address. User’s Manual OCDS, V 0.2 14-4 V 0.2, 2005-01 XC866 On-Chip Debug Support When the Internal Data Memory is RAM, the OCDS differentiates between a breakpoint on read and a breakpoint on write operation to this IRAM. Configurations of Hardware Breakpoints The OCDS in XC866 allows the setting of up to 4 hardware breakpoints labeled HWBPx (x = 0 - 3) (16-bit values) in various configurations as follows: • HWBP0 • HWBP1 – two equal breakpoints on Instruction Address=HWBP0 and Instruction Address=HWBP1, or – one range breakpoint on HWBP0