IA2910A-CLC44M

Page 1 of 19 IA2910A Microprogram Controller FEATURES • • • • • Preliminary Data Sheet Form, Fit, and Function Compatible with the AMD™ Am2910A Packaging options available: 40 Pin Plastic or Ceramic DIP, 44 Pin Plastic Leaded Chip Carrier Twelve Bits Wide Internal Loop Counter Four Address Sources - push/pop stack counter - internal holding register - microprogram counter - branch address bus 9 Word Deep Stack Register - push/pop control for nesting subroutines 16 Sequence Control Microinstructions Output Enable controls 3 Branch Address Sources • • • The IA2910A uses innovASIC’ innovative new f 3 Program to provide industry with parts that s other vendors have declared obsolete. By specifying parts through this program a customer is assured of never having a component become obsolete again. This data sheet assumes the original part has been designed in, and so provides a summary of capabilities only. For new designs contact innovASIC for more detailed information. AMD is a trademark of Advanced Micro Devices, Inc. YOUT5 YOUT4 YOUT3 YOUT2 (41) VECTn DIN5 DIN4 DIN3 DIN2 DIN4 YOUT5 DIN5 VECTn PLn MAPn I3 I2 VCC I1 I0 CCENn CCn RLDn FULLn DIN6 YOUT6 DIN7 YOUT7 (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) 40 Pin DIP (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21) YOUT3 DIN2 (44) (43) (42) DIN1 YOUT1 DIN0 YOUT0 CIN CLK VDD OEn YOUT11 DIN11 YOUT10 DIN10 YOUT9 DIN9 (40) (6) (5) (4) (3) (2) (1) YOUT2 PLn MAPn I3 I2 VCC I1 I0 CCENn CCn RLDn N.C. DIN1 N. C. YOUT4 (1) IA2910A (40) DIN3 (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (39) (38) YOUT1 DIN0 YOUT0 N. C. CIN CLK VDD N. C. OEn YOUT11 DIN11 IA2910A 44 Pin LCC (37) (36) (35) (34) (33) (32) (31) (30) (29) FULLn YOUT7 YOUT8 DIN10 DIN7 DIN8 YOUT8 DIN8 Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions YOUT10 YOUT6 YOUT9 DIN6 DIN9 Page 2 of 19 IA2910A Microprogram Controller Preliminary Data Sheet The IA2910A is a form, fit and function compatible part to the AMD 2910A microprogram controller. The IA2910A is an address controller which will sequence through a series of microinstructions contained in a ROM or PROM. There are four sources of addresses from which the IA2910A may select. The first is a direct data bus (DIN) input, which is straightforward. The second is an internal address register. This register contains data loaded during a previous microinstruction. The third source is a program counter register, which generally contains the previous address incremented by one. The final source of addresses is a nine word deep stack register which gives the capability to execute nested subroutine linkages. All internal registers are clocked on the rising edge of the clock input (CLK). An OEn input enables the YOUT output bus to be tri-stated. A block diagram is shown in Figure 1. Functional Block Diagram Figure 1 DIN CLK RLDn FULLn Register/Counter Stack Pointer Zero Detector 9 word X 12 Bit Stack DECREMENT/ R=0 HOLD/LOAD Mux Microprogram counter-register SELECT CCn CCENn Instruction CIN Incrementer PLA I(3:0) PUSH/POP/ HOLD/CLEAR CLEAR/COUNT 12 PLn VECTn MAPn YOUT Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 3 of 19 IA2910A Microprogram Controller Functional Overview Preliminary Data Sheet The IA2910A is a 0.8 µm CMOS microprogram controller intended for use in high-speed microprocessor applications. It allows addressing of up to 4K words of microprogram. The controller contains a four-input mux that is used to select either the register/counter, direct data input, microprogram counter, or stack as the source of the next microinstruction address. The register/counter consists of 12 D-type, edge-triggered flip-flops, with a common clock enable. When its load control, RLDn, is LOW, new data is loaded on a positive clock transition. A few instructions include load; in most systems, these instructions will be sufficient, simplifying the microcode. The output of the register/counter is available to the mux as a source for the next microinstruction address. The direct input furnishes a source of data for loading the register/counter. The IA2910A contains a microprogram counter that is composed of a 12-bit incrementer followed by a 12-bit register. The counter can be used in either of two ways. When the carry-in to the incrementer is HIGH, the microprogram register is loaded on the next clock cycle with the current YOUT output word plus one. Sequential microinstructions are thus executed. When the carry-in is LOW, the incrementer passes the YOUT output word unmodified so that the counter is reloaded with the same YOUT word on the next clock cycle. The same microinstruction is thus executed any number of times. The third source for the mux is the direct DIN input. This source is used for branching. The fourth source available at the mux input is a 9-word by 12-bit stack (file). The stack is used to provide return address linkage when executing microsubroutines or loops. The stack contains a built-in stack pointer (SP) which always points to the last file word written. This allows stack reference operations (looping) to be performed without a pop. The stack pointer operates as an up/down counter. During microinstructions 1, 4, and 5, the PUSH operation may occur. This causes the stack pointer to increment and the file to be written with the required return linkage. On the cycle following the PUSH, the return data is at the new location pointed to by the stack pointer. During five microinstructions, a POP operation may occur. The stack pointer decrements at the next rising clock edge following a POP, effectively removing old information from the top of the stack. The stack pointer linkage is such that any sequence of pushes, pops, or stack references can be achieved. At RESET (Instruction 0), the depth of nesting becomes zero. For each PUSH, the nesting depth increases by one; for each POP, the depth decreases by one. The depth can grow to nine. After a depth of nine is reached, FULLn goes LOW. Any further PUSHes onto a full stack overwrite information at the top of the stack, but leave the stack pointer unchanged. This operation will usually destroy useful information and is normally avoided. A POP from an empty stack may place non-meaningful data on the YOUT outputs, but is otherwise safe. The stack Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 4 of 19 IA2910A Microprogram Controller Preliminary Data Sheet pointer remains at zero whenever a POP is attempted from a stack already empty. The register/counter is operated during three microinstructions (8, 9, and 15) as a 12-bit down counter, with result = zero available as a microinstruction branch test criterion. This provides efficient iteration of microinstructions. The register/counter is arranged such that if it is preloaded with a number N and then used as a loop termination counter, the sequence will be executed exactly N + 1 times. During instruction 15, a three-way branch under combined control of the loop counter and the condition code is available. The device provides three-state YOUT outputs. These can be particularly useful in designs requiring automatic checkout of the processor. The microprogram controller outputs can be forced into the high-impedance state, and pre-programmed sequences of microinstructions can be executed via external access to the address lines. Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 5 of 19 IA2910A Microprogram Controller I/O Signal Description Table 1 Symbol CLK I(3:0) CCn CCENn RLDn OEn CIN FULLn DIN(11:0) YOUT(11:0) PLn MAPn VECTn Type I I I I I I I O I O O O O Description Preliminary Data Sheet Table 1 below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. Clock Input - Clock source for address register, microprogram counter register, and stack file. Active high instruction bits. Selects instruction to be executed by the IA2910A. Active low. Condition code. Used as test criterion, pass is low on CCn. Active low. Condition code enable. When set high, CCn is ignored and the IA2910A operates as it CCn were a low. Active low. Clock enable to address register, allows loading of register/counter regardless of instruction or condition. Active low. Output enable, when high tri-states the output bus YOUT. Active high. Carry in signal to the incrementer. Active low. Indicates there are nine items on the stack. Active high. Data bus input to the multiplexer. Active high. Data bus output from the IA2910A. Active low. Pipeline address enable. Selects source number one (usually pipeline register) as direct input source. Active low. Map address enable. Selects source number two (usually mapping PROM or PLA) as direct input source. Active low. Vector address enable. Selects source number three (usually interrupt starting address) as direct input source. Theory of Operation Table 2 shows the result of each instruction in controlling the mux which determines the YOUT outputs, and in controlling the three enable signals PLn, MAPn, and VECTn. The effect on the register/counter and the stack after the next positive-going clock edge is also shown. The mux determines which internal source drives the YOUT outputs. The value loaded into the counter is Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 6 of 19 IA2910A Microprogram Controller Preliminary Data Sheet either identical to the YOUT output, or else one greater, as determined by CIn. For each instruction, one and only one of the three outputs PLn, MAPn, and VECTn is LOW. If these outputs control three-state enables for the primary source of microprogram jumps (usually part of a pipeline register), a PROM which maps the instruction to a microinstruction starting location, and an optional third source (often a vector from a DMA or interrupt source), respectively, the threestate sources can drive the DIN inputs without further logic. Several inputs, as shown in Table 2, can modify instruction execution. The combination CCn HIGH and CCENn LOW is used as a test in 9 of the 16 instructions. RLDn, when LOW, causes the DIN input to be loaded into the register/counter, overriding any HOLD or DEC operation specified in the instruction. OEn, normally LOW, may be forced HIGH to remove the IA2910A YOUT outputs from a three-state bus. The stack, a nine-word last-in, first-out 12-bit memory, has a pointer which addresses the value presently on the top of the stack. Explicit control of the stack pointer occurs during instruction 0 (RESET), which makes the stack empty by resetting the SP to zero. After a RESET, and whenever else the stack is empty, the contents of the top of stack is undefined until a PUSH occurs. Any POPs performed while the stack is empty put undefined data on the F outputs and leave the stack pointer at zero. Any time the stack is full (nine more PUSHes than POPs have occurred since the stack was last empty), the FULLn warning output occurs. This signal first appears on the microcycle after a ninth PUSH. No additional PUSH should be attempted onto a full stack; if tried, information within the stack will be overwritten and lost. Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 7 of 19 IA2910A Microprogram Controller Instruction Set Description Table 2 I(3:0) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mnemonic JZ CJS JMAP CJP PUSH JSRP CJV JRP RFCT RPCT CRTN CJPP LDCT LOOP CONT TWB Name Jump Zero Cond JSB PL Jump Map Cond Jump PL Push/cond LD cntr Cond JSB R/PL Cond Jump Vector Cond Jump R/PL Repeat Loop, Cntr .NE. 0 Repeat PL, cntr .NE. 0 Cond RTN Cond Jump PL & POP LD Cntr & Continue Test End Loop Continue Three-Way Branch Reg/cntr contents X X X X X X X X .NE. 0 =0 .NE. 0 =0 X X X X X .NE. 0 =0 Fail Y 0 PC D PC PC R PC R F PC D PC PC PC PC F PC F D Fail Stack CLEAR HOLD HOLD HOLD PUSH PUSH HOLD HOLD HOLD POP HOLD HOLD HOLD HOLD HOLD HOLD HOLD HOLD POP Pass Y 0 D D D PC D D D F PC D PC F D PC PC PC PC PC Preliminary Data Sheet Pass Stack CLEAR PUSH HOLD HOLD PUSH PUSH HOLD HOLD HOLD POP HOLD HOLD POP POP HOLD POP HOLD POP POP Reg/cntr HOLD HOLD HOLD HOLD NOTE 1 HOLD HOLD HOLD DEC HOLD DEC HOLD HOLD HOLD LOAD HOLD HOLD DEC HOLD Enable PL PL MAP PL PL PL VECT PL PL PL PL PL PL PL PL PL PL PL PL NOTE 1: If CCENn is LOW and CCn is HIGH, HOLD; ELSE LOAD. X = Don’ Care t .NE. = Not equal IA2910A Instruction Set The IA2910A provides sixteen instructions which select the address of the next microinstruction to be executed. Four of the instructions are unconditional – their effect depends only on the instruction. Ten of the instructions have an effect which is partially controlled by an external, datadependent condition. Three of the instructions have an effect which is partially controlled by the contents of the internal register/counter. The instruction set is shown in Table 2. Examples of the Instruction Execution are illustrated in Figure 2. In this discussion it is assumed that CIN is tied HIGH. In the ten conditional instructions, the result of the data-dependent test is applied to CCn. If the CCn input is LOW, the test is considered to have been passed, and the action specified in the name occurs; otherwise, the test has failed and an alternate (often simply the execution of the next sequential microinstruction) occurs. Testing of CCn may be disabled for a specific microinstruction by setting CCENn HIGH, which unconditionally forces the action specified in the name; that is, it forces a pass. Other ways of using CCENn include (1) tying it HIGH, which is useful if no microinstruction is data-dependent; (2) tying it LOW if data-dependent instructions are never Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 8 of 19 IA2910A Microprogram Controller Preliminary Data Sheet forced unconditionally; or (3) tying it to the source of IA2910A instruction bit I(0), which leaves instructions 4, 6, and 10 as data-dependent but makes others unconditional. All of these tricks save one bit of microcode width. The effect of three instructions depends on the contents of the register/counter. Unless the counter holds a value of zero, it is decremented; if it does hold zero, it is held and a different microprogram next address is selected. These instructions are useful for executing a microinstruction loop a known number of times. Instruction 15 is affected both by the external condition code and the internal register/counter. Instruction 0 JZ JUMP and ZERO, or RESET unconditionally specifies that the address of the next microinstruction is zero. Many designs use this feature for power-up sequences and provide the power-up firmware beginning at microprogram memory word location 0. Instruction 1 CJS is a CONDITIONAL JUMP-TO-SUBROUTINE via the address provided in the pipeline register. As shown in Figure II, the machine might have executed words at address 50, 51, and 52. When the contents of address 52 is in the pipeline register, the next address control function is the CJS. Here, if the test is passed, the next instruction executed will be the contents of microprogram memory location 90. If the test has failed, the CJS will not be executed; the contents of microprogram memory location 53 will be executed instead. Thus the CJS instruction at location 52 will cause the instruction either in location 90 or location 53 to be executed next. If the TEST input is such that location 90 is selected, value 53 will be pushed onto the internal stack. This provides the return linkage for the machine when the subroutine beginning at location 90 is completed. In this example, the subroutine was completed at location 93 and a RETURN-FROMSUBOUTINE would be found at location 93. Instruction 2 JMAP is the JUMP MAP instruction. This is an unconditional instruction which causes the MAPn output to be enabled so that the next microinstruction location is determined by the address supplied via the mapping PROMs. Normally, the JMAP instruction is used at the end of the instruction fetch sequence for the machine. In the example of Figure II, microinstructions at locations 50, 51, 52, and 53 might have been the fetch sequence and at its completion at location 53, the JMAP function would be contained in the pipeline register. This example shows the mapping PROM outputs to be 90; therefore, an unconditional jump to microprogram memory address 90 is performed. Instruction 3 CJP, CONDITIONAL JUMP PIPELINE, derives its branch address from the pipeline register branch address value (BR(0) – BR(11) in FIGURE II). This instruction provides a technique for branching to various microprogram sequences depending upon the test condition inputs. Quite often, state machines are designed which simply execute tests on various inputs waiting for the condition to come true. When the true condition is reached, the machine then branches and executes a set of microinstructions to perform some function. This usually has the effect of resetting the input being tested until some point in the future. Figure II shows the conditional jump via the pipeline register address at location 52. When the contents of microprogram memory word 52 are in the pipeline register, the next address will be either location 53 or location 30 in this example. If the test is passed, the value currently in the pipeline register (30) will be contained in the microprogram counter which, in this example, is 53. Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 9 of 19 IA2910A Microprogram Controller Preliminary Data Sheet Instruction 4 PUSH is the PUSH/CONDITIONAL LOAD COUNTER instruction and is used primarily for setting up loops in microprogram firmware. In Figure II, when instruction 52 is in the pipeline register, a PUSH will be made onto the stack and the counter will be loaded based on the condition. When a PUSH occurs, the value pushed is always the next sequential instruction address. In this case, the address is 53. If the test fails, the counter is not loaded; if it is passed, the counter is loaded with the value contained in the pipeline register branch address field. Thus, a single microinstruction can be used to set up a loop to be executed a specific number of times. Instruction 8 will describe how to use the pushed value and the register/counter for looping. Instruction 5 JSRP is a CONDITIONAL JUMP-TO-SUBROUTINE via the register/counter or the contents of the PIPELINE register. As shown in Figure II, a PUSH is always performed and one of two subroutines executed. In this example, either the subroutine beginning at address 80 or the subroutine beginning at address 90 will be performed. A return-from-subroutine (instruction 10) returns the microprogram flow to address 55. In order for this microinstruction control sequence to operate correctly, both the next address fields of instruction 53 and 54 would have to contain the proper value. Let’ assume that the branch address fields of instruction 53 contain the s value 90 so that it will be in the IA2910A register/counter when the contents of address 54 are in the pipeline register. This requires that the instruction at address 53 load the register/counter. Now, during the execution of instruction 5 (at address 54), if the test failed, the contents of the register (value = 90) will select the address of the next microinstruction. If the test input passes, the pipeline register contents (value = 80) will determine the address of the next microinstruction. Therefore, this instruction provides the ability to select one of two subroutines to be executed based on a test condition. Instruction 6 CJV is a CONDITIONAL JUMP VECTOR instruction which provides the capability to take the branch address from a third source heretofore not discussed. In order for this instruction to be useful, the IA2910A output, VECTn is used to control a three-state control input of a register, buffer, or PROM containing the next microprogram address. This instruction provides one technique for performing interrupt type branching at the microprogram level. Since this instruction is conditional, a pass causes the next address to be taken from the vector source, while failure causes the next address to be taken from the microprogram counter. In the example of Figure II, if the CJV instruction is contained at location 52, execution will continue at vector address 20 if the CCn input is LOW and the microinstruction at address 53 will be executed if the CCn input is HIGH. Instruction 7 JRP is a CONDITIONAL JUMP via the contents of the IA2910A register/counter or the contents of the pipeline register. This instruction is very similar to instruction 5; the conditional jump-to-subroutine via R or PL. The major difference between instruction 5 and instruction 7 is that no push onto the stack is performed with 7. Figure II depicts this instruction as a branch to one of two locations depending on the test condition. the example assumes the pipeline register contains the value 70 when the contents of address 52 is being executed. As the contents of address 53 is clocked into the pipeline register, the value 70 is loaded into the register/counter in the IA2910A. The value 80 is available when the contents of address 53 is in the pipeline register. Thus, control is transferred to either address 70 or address 80 depending on the test condition. Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 10 of 19 IA2910A Microprogram Controller Preliminary Data Sheet Instruction 8 RFCT is the REPEAT LOOP, COUNTER NOT EQUAL ZERO instruction. This microinstruction makes use of the decrementing capability of the register/counter. To be useful, some previous instruction, such as 4, must have loaded a count value into the register/counter. This instruction checks to see whether the register/counter contains a non-zero value. If so, the register/counter is decremented, and the address of the next microinstruction is taken from the top of the stack. If the register counter contains zero, the loop exit condition is occurring; control falls through to the next sequential microinstruction by selecting uPC; the stack is POP’ by decrementing the stack pointer, but the contents of the top of the stack are thrown d away. An example of the RFCT instruction is shown in Figure II. In this example, location 50 most likely would contain a PUSH/CONDITIONAL LOAD COUNTER instruction which would have caused address 51 to be PUSHed on the stack and the counter to be loaded with the proper value for looping the desired number of times. In this example, since the loop test is made at the end of the instructions to be repeated (microaddress 54), the proper value to be loaded by the instructions at address 50 is one less than the desired number of passes through the loop. This method allows a loop to be executed 1 to 4096 times. If it is desired to execute the loop from 0 to 4095 times, the firmware should be written to make the loop exit test immediately after loop entry. Instruction 9 RPCT is the REPEAT PIPELINE REGISTER, COUNTER NOT EQUAL ZERO instruction. This instruction is similar to instruction 8 except that the branch address now comes from the pipeline register rather than the file. In some cases, this instruction may be thought of as a one-word file extension; that is, by using this instruction, a loop with the counter can still be performed when subroutines are nested five deep. This instruction’ operation is very s similar to that of instruction 8. The differences are that on this instruction, a failed test condition causes the source of the next microinstruction address to be the DIN inputs; and, when the test condition is passed, this instruction does not perform a POP because the stack is not being used. In the example of Figure II, the RPCT instruction is instruction 52 and is shown as a single microinstruction loop. The address in the pipeline register would be 52. Instruction 51 in this example could be the LOAD COUNTER AND CONTINUE instruction (number 12). While the example shows a single microinstruction loop, by simply changing the address in a pipeline register, multi-instruction loops can be performed in this manner for a fixed number of times as determined by the counter. Instruction 10 CRTN is the CONDITIONAL RETURN-FROM-SUBROUTINE instruction. As the name implies, this instruction is used to branch from the subroutine back to the next microinstruction address following the subroutine call. Since this instruction is conditional, the return is performed only if the test is passed. If the test is failed, the next sequential microinstruction is performed. The example in Figure II depicts the use of the CRTN instruction in both the conditional and the unconditional modes. This example first shows a jump-tosubroutine at instruction location 52 where control is transferred to location 90. At location 93, a CRTN instruction is performed. If the test is passed, the stack is accessed and the program will Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 11 of 19 IA2910A Microprogram Controller Preliminary Data Sheet transfer to the next instruction at address 53. If the test is failed, the next microinstruction at address 94 will be executed. The program will continue to address 97 where the subroutine is complete. To perform an unconditional RETURN-FROM-SUBROUTINE, the CRTN instruction is executed unconditionally; the microinstruction at address 97 is programmed to force CCENn HIGH, disabling the test and the forced PASS causes an unconditional return. Instruction 11 CJPP is the CONDITIONAL JUMP PIPELINE register address and POP stack instruction. This instruction provides another technique for loop termination and stack maintenance. The example in Figure II shows a loop being performed from address 55 back to address 51. The instructions at locations 52, 53, and 54 are all conditional JUMP and POP instructions. At address 52, if the CCn input is LOW, a branch will be made to address 70 and the stack will be properly maintained via a POP. Should the test fail, the instruction at location 53 (the next sequential instruction) will be executed. Likewise, at address 53, either the instruction at 90 or 54 will be subsequently executed, respective to the test being passed or failed. The instruction at 54 follows the same rules, going to either 80 or 55. An instruction sequence as described here, using the CJPP instruction, is very useful when several inputs are being tested and the microprogram is looping waiting for any of the inputs being tested to occur before proceeding to another sequence of instructions. This provides the powerful jump-table programming technique at the firmware level. Instruction 12 LDCT is the LOAD COUNTER AND CONTINUE instruction, which simply enables the counter to be loaded with the value at its parallel inputs. These inputs are normally connected to the pipeline branch address field which (in the architecture being described here) serves to supply either a branch address or a counter value depending upon the microinstruction being executed. There are altogether three ways of loading the counter – the explicit load by this instruction 12; the conditional load included as part of instruction 4; and the use of the RLDn input along with any instruction. The use of RLDn with any instruction overrides any counting or decrementation specified in the instruction, calling for a load instead. Its use provides additional microinstruction power, at the expense of one bit of microinstruction width. This instruction 12 is exactly equivalent to the combination of instruction 14 and RLDn LOW. Its purpose is to provide a simple capability to load the register/counter in those implementations which do not provide microprogrammed control for RLDn. Instruction 13 LOOP is the TEST END-OF-LOOP instruction, which provides the capability of conditionally exiting a loop at the bottom; that is, this is a conditional instruction that will cause the microprogram to loop, via the file, if the test is failed else to continue to the next sequential instruction. The example in Figure II shows the LOOP microinstruction at address 56. If the test fails, the microprogram will branch to address 52. Address 52 is on the stack because a PUSH instruction had been executed at address 51. If the test is passed at instruction 56, the loop is terminated and the next sequential microinstruction at address 57 is executed, which also causes the stack to be POP’ thus, accomplishing the required stack maintenance. d; Instruction 14 CONT is the CONTINUE instruction, which simply causes the microprogram counter to increment so that the next sequential microinstruction is executed. This is the simplest microinstruction of all and should be the default instruction which the firmware requests whenever there is nothing better to do. Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 12 of 19 IA2910A Microprogram Controller Preliminary Data Sheet Instruction 15 TWB, THREE-WAY-BRANCH, is the most complex. It provides for testing for both a data-dependent condition and the counter during one microinstruction and provides for selecting among one of three microinstruction addresses as the next microinstruction to be performed. Like instruction 8, a previous instruction will have loaded a count into the register/counter while pushing a microbranch address onto the stack. Instruction 15 performs a decrement-and-branch-until-zero function similar to instruction 8. The next address is taken from the top of the stack until the count reaches zero; then the next address comes from the pipeline register. The above action continues as long as the test condition fails. If at any execution of instruction 15 the test condition is passed, no branch is taken; the microprogram counter register furnishes the next address. When the loop is ended, either by the count becoming zero, or by passing the conditional test, the stack is POP’ by decrementing the stack pointer, since interest in d the value contained at the top of the stack is then complete. As one example, consider the case of a memory search instruction. As shown in Figure II, the instruction at microprogram address 63 can be Instruction 4 (PUSH), which will push the value 64 onto the microprogram stack and load the number N, which is one less than the number of memory locations to be searched before giving up. Location 64 contains a microinstruction which fetches the next operand from the memory area to be searched and compares it with the search key. Location 65 contains a microinstruction which tests the result of the comparison and also is a TWB for microprogram control. If no match is found, the test fails and the microprogram goes back to location 64 for the next operand address. When the count becomes zero, the microprogram branches to location 72, which does whatever is necessary if no match is found. If a match occurs on any execution of the TWB at location 65, control falls through to location 66 which handles this case. Whether the instruction ends by finding a match or not, the stack will have been POP’ once, removing the value 64 from the top of the stack. d Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 13 of 19 IA2910A Microprogram Controller Absolute Maximum Ratings PARAMETER Supply voltage, VDD Input voltage, VIN Input Pin Current IIN Operating temperature range Storage temperature range Ambient Temperature, Ta Lead Temperature Power Dissipation Min TBD TBD TBD TBD TBD TBD TBD Max Preliminary Data Sheet UNITS V V mA ° C ° C ° C ° C mW Notes Stresses beyond those listed under “ absolute maximum ratings”may cause permanent damage to the device. Operating the device beyond the conditions indicated in the “ recommended operating conditions” section is not recommended. Operation at the “ absolute maximum ratings”may adversely affect device reliability. DC Characteristics PARAMETER DC Supply voltage, VDD Static Supply Current, IDD Power Supply Current, IDD Standby Supply Current, Istby Input Capacitance, CIN I/O Capacitance, CI/O Circuit Ground, VSS Notes: (1) Static IDD current is exclusive of input/output drive requirements and is measured with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current. Min 4.5 Max 5.5 TBD TBD TBD TBD TBD TBD UNITS V µA mA/MHz µA pF pF V Notes (1) Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 14 of 19 IA2910A Microprogram Controller Preliminary Data Sheet Parametric Voltage and Current Levels (Ambient Temperature = -40 to 85 C) Input Pin TBD VIL VIH Hysteresis Note Output Pin TBD VOL VOH IOL IOH Min IOZ Max Note Pullup Pin TBD IPU Min Note Max AC Specifications Parameter TBD Min Max Notes Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 15 of 19 IA2910A Microprogram Controller IA2910A Execution Examples Figure 2 0 JUMP ZERO 0 1 2 50 51 52 53 54 55 1 COND JSB PL STACK 53 90 91 92 93 2 JUMP MAP 50 51 52 53 90 91 Preliminary Data Sheet 3 COND JUMP PL 50 51 52 53 54 30 31 4 PUSH/COND LD CNTR 50 51 52 53 REGISTER/ COUNTER N 90 91 92 93 94 STACK 53 5 COND JSB R/PL 50 51 52 53 54 55 56 57 80 81 82 83 84 STACK 55 6 COND JUMP VECTOR 50 51 52 53 54 20 21 7 COND JUMP R/PL 50 51 52 53 70 71 8 REPEAT LOOP, CNTR .NE. 0 STACK PUSH 51 50 51 52 80 81 53 54 55 REGISTER/ COUNTER N 9 REPEAT PL, CNTR .NE. 0 COUNTER (LDCT) N 50 51 52 53 10 COND RETURN STACK 53 50 51 52 53 54 55 90 91 92 93 94 95 96 97 11 COND JUMP PL & POP STACK PUSH 51 50 51 52 53 54 55 56 80 81 82 90 91 92 70 71 72 12 LD CNTR & CONTINUE 50 51 52 53 COUNTER N 13 TEST END LOOP STACK PUSH 52 14 CONTINUE 15 THREE-WAY BRANCH STACK PUSH 64 50 51 52 53 54 55 56 57 50 51 62 63 64 65 66 REGISTER/ COUNTER N 72 73 Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 16 of 19 IA2910A Microprogram Controller Preliminary Data Sheet PLCC Packaging Dimensions (Theta J = TBD) D PIN 1 IDENTIFIER & ZONE D1 TOP VIEW E1 E BOTTOM VIEW .030 ± .005 LEAD COUNT Symbol 44 (in Inches) MIN .150 .0007 .652 .610 .652 .610 MAX .154 .0103 .656 .630 .656 .630 SEATING PLANE A A1 A A1 D1 .03R .013/.021 .020 MIN. R 70 ± 2 Deg. D2 E1 E2 e D e .050 ± .002 .685 .685 .695 .695 D2 / E2 SIDE VIEW E Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 17 of 19 IA2910A Microprogram Controller Preliminary Data Sheet PDIP Packaging Dimensions (Theta J = TBD) TOP E1 E LEAD 1 IDENTIFIER eA 1 LEAD COUNT DIRECTION C eB SIDE VIEW (WIDTH) Lead Count Symbol D 28 (in Inches) MIN .015 .016 .040 2.045 .600 .545 .700 TYP .620 .125 TYP .660 MAX .220 2.055 .620 .555 A A1 A2 A1 A B B1 C L B D E E1 B1 e e eA SIDE VIEW (LENGTH) eB L Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 18 of 19 IA2910A Microprogram Controller Package Options Preliminary Data Sheet The IA2910A is available in two package styles as shown in the table below. Package Type 40 Lead Ceramic DIP, 600 mil wide 40 Lead Plastic DIP, 600 mil wide 44 Lead Ceramic Leaded Chip Carrier 44 Lead Ceramic Leadless Chip Carrier 44 Lead Plastic Leaded Chip Carrier Environment Military Industrial Commercial Military Military Industrial Commercial Order Number IA2910A-CD40M IA2910A-PDW40I IA2910A-PDW40C IA2910A-CLC44M IA2910A-CLL44M IA2910A-PLC44I IA2910A-PLC44C The following diagram depicts the innovASIC Product Identification Number. IAXXXXX-PPPPNNNT/SP Special Processing: S = Space Q = MIL-STD-883 Temperature: C = Commercial I = Industrial M = Military Number of Leads Package Type: Per Package Designator Table IC Base Number innovASIC Designator Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions Page 19 of 19 IA2910A Microprogram Controller Package Designator Table Package Type Ceramic side brazed Dual In-line Cerdip with window Ceramic leaded chip carrier Cerdip without window Ceramic leadless chip carrier PLCC Plastic DIP standard (300 mil) Plastic DIP standard (600 mil) Plastic metric quad flat pack Plastic thin quad flat pack Skinny Cerdip Small outline plastic gull-wing(150 mil body) Small outline medium plastic gull-wing (207 mil body) Small outline narrow plastic gull wing (150 mil body) Small outline wide plastic gull wing (300 mil body) Skinny Plastic Dip Shrink small outline plastic (5.3mm .208 body) Thin shrink small outline plastic Small outline large plastic gull wing (330 mil body) Thin small outline plastic gull-wing (8 x 20mm) [TSOP] PGA BGA Preliminary Data Sheet innovASIC Designator CDB CDW CLC CD CLL PLC PD PDW PQF PTQ CDS PSO PSM PSN PSW PDS PS PTS PSL PST CPGA CBGA Contact innovASIC for other package and processing options. Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions