243658-020

Intel® Celeron® Processor up to 1.10 GHz Datasheet s s s s s s s Available at 1.10 GHz, 1 GHz, 950 MHz, 900 MHz, 850 MHz, 800 MHz, 766 MHz, 733 MHz, 700 MHz, 667 MHz, 633 MHz, 600 MHz, 566 MHz, 533 MHz, 533A MHz, 500 MHz, 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, and 300A MHz core frequencies with 128 KB level-two cache (on die); 300 MHz and 266 MHz core frequencies without level-two cache. Intel’s latest Celeron® processors in the FC-PGA/FC-PGA2 package are manufactured using the advanced 0.18 micron technology. Binary compatible with applications running on previous members of the Intel microprocessor line. Dynamic execution microarchitecture. Operates on a 100/66 MHz, transactionoriented system bus. Specifically designed for uni-processor based Value PC systems, with the capabilities of MMX™ technology. Power Management capabilities. s s s s Optimized for 32-bit applications running on advanced 32-bit operating systems. Uses cost-effective packaging technology. — Single Edge Processor (S.E.P.) Package to maintain compatibility with SC242 (processor core frequencies (MHz): 266, 300, 300A, 333, 366, 400, 433). — Plastic Pin Grid Array (PPGA) Package (processor core frequencies (MHz): 300A, 333, 366, 400, 433, 466, 500, 533). — Flip-Chip Pin Grid Array (FC-PGA / FC-PGA2) Package (processor core frequencies (MHz); 533A, 566, 600, 633, 667, 700, 733, 766, 800, 850, 900, 950); (GHz); 1, 1.10 Integrated high-performance 32 KB instruction and data, nonblocking, levelone cache: separate 16 KB instruction and 16 KB data caches. Integrated thermal diode. The Intel® Celeron® processor is designed for uni-processor based Value PC desktops and is binary compatible with previous generation Intel architecture processors. The Celeron processor provides good performance for applications running on advanced operating systems such as Microsoft* Windows*98, Windows NT*, Windows* 2000, Windows XP* and Linux*. This is achieved by integrating the best attributes of Intel processors—the dynamic execution performance of the P6 microarchitecture plus the capabilities of MMX™ technology—bringing a balanced level of performance to the Value PC market segment. The Celeron processor offers the dependability you would expect from Intel at an exceptional value. Systems based on Celeron processors also include the latest features to simplify system management and lower the cost of ownership for small business and home environments. FC-PGA2 Package FC-PGA Package PPGA Package S.E.P. Package Document Number: 243658-020 January 2002 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Celeron® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Intel, Celeron, Pentium, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright© 1996–2002, Intel Corporation Datasheet Intel® Celeron® Processor up to 1.10 GHz Contents 1.0 Introduction.......................................................................................................................11 1.1 Terminology.........................................................................................................11 1.1.1 Package Terminology.............................................................................12 1.1.2 Processor Naming Convention...............................................................13 References ..........................................................................................................14 System Bus and Vref...........................................................................................15 Clock Control and Low Power States..................................................................15 2.2.1 Normal State—State 1 ...........................................................................16 2.2.2 AutoHALT Power Down State—State 2 .................................................16 2.2.3 Stop-Grant State—State 3 .....................................................................17 2.2.4 HALT/Grant Snoop State—State 4 ........................................................17 2.2.5 Sleep State—State 5..............................................................................17 2.2.6 Deep Sleep State—State 6 ....................................................................18 2.2.7 Clock Control..........................................................................................18 Power and Ground Pins ......................................................................................18 2.3.1 Phase Lock Loop (PLL) Power...............................................................19 Processor Decoupling .........................................................................................19 2.4.1 System Bus AGTL+ Decoupling.............................................................19 Voltage Identification ...........................................................................................20 System Bus Unused Pins....................................................................................21 Processor System Bus Signal Groups ................................................................21 2.7.1 Asynchronous Vs. Synchronous for System Bus Signals ......................23 2.7.2 System Bus Frequency Select Signal (BSEL[1:0]).................................23 Test Access Port (TAP) Connection....................................................................23 Maximum Ratings................................................................................................23 Processor DC Specifications...............................................................................24 AGTL+ System Bus Specifications .....................................................................33 System Bus AC Specifications ............................................................................34 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines ....................................................................................52 AGTL+ Signal Quality Specifications and Measurement Guidelines ..................55 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........57 3.3.1 Overshoot/Undershoot Guidelines .........................................................57 3.3.2 Ringback Specification ...........................................................................58 3.3.3 Settling Limit Guideline...........................................................................59 AGTL+ Signal Quality Specifications and Measurement Guidelines (FC-PGA/FC-PGA2 Packages) ...........................................................................59 3.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages) .......59 3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages) .......59 3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2 Packages) ..............................................................................................60 3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages) ......................................60 1.2 2.0 2.1 2.2 Electrical Specifications....................................................................................................15 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3.0 3.1 3.2 3.3 System Bus Signal Simulations........................................................................................52 3.4 Datasheet 3 Intel® Celeron® Processor up to 1.10 GHz 3.5 4.0 4.1 5.0 Reading Overshoot/Undershoot Specification Tables (FC-PGA/FC-PGA2 Packages) .............................................................. 61 3.4.6 Determining if a System meets the Overshoot/Undershoot Specifications (FC-PGA/FC-PGA2 Packages)....................................... 62 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines........... 64 Thermal Specifications........................................................................................ 65 4.1.1 Thermal Diode........................................................................................ 68 S.E.P. Package ................................................................................................... 69 5.1.1 Materials Information.............................................................................. 69 5.1.2 Signal Listing (S.E.P. Package) ............................................................ 70 PPGA Package ................................................................................................... 79 5.2.1 PPGA Package Materials Information.................................................... 79 5.2.2 PPGA Package Signal Listing ................................................................ 81 FC-PGA/FC-PGA2 Packages ............................................................................. 92 5.3.1 FC-PGA Mechanical Specifications ....................................................... 92 5.3.2 Mechanical Specifications (FC-PGA2 Package) .................................... 94 5.3.2.1 Recommended Mechanical Keep-Out Zones (FC-PGA2 Package) ................................................................. 96 5.3.3 FC-PGA/FC-PGA2 Package Signal List................................................. 97 Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages) ............................. 108 Heatsink Volumetric Keepout Zone Guidelines................................................. 109 Mechanical Specifications for the Boxed Intel® Celeron® Processor ................ 110 6.1.1 Mechanical Specifications for the S.E.P. Package............................... 110 6.1.1.1 Boxed Processor Heatsink Weight.......................................... 112 6.1.1.2 Boxed Processor Retention Mechanism ................................. 112 6.1.2 Mechanical Specifications for the PPGA Package............................... 113 6.1.2.1 Boxed Processor Heatsink Weight.......................................... 114 6.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages......... 114 6.1.3.1 Boxed Processor Heatsink Weight.......................................... 115 Thermal Specifications...................................................................................... 115 6.2.1 Thermal Requirements for the Boxed Intel® Celeron® Processor........ 115 6.2.1.1 Boxed Processor Cooling Requirements ................................ 115 6.2.1.2 Boxed Processor Thermal Cooling Solution Clip .................... 117 Electrical Requirements for the Boxed Intel® Celeron® Processor ................... 117 6.3.1 Electrical Requirements ....................................................................... 117 Signal Summaries ............................................................................................. 126 3.4.5 Thermal Specifications and Design Considerations......................................................... 65 Mechanical Specifications................................................................................................ 69 5.1 5.2 5.3 5.4 5.5 6.0 6.1 Boxed Processor Specifications..................................................................................... 110 6.2 6.3 7.0 Processor Signal Description ......................................................................................... 120 7.1 4 Datasheet Intel® Celeron® Processor up to 1.10 GHz Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Clock Control State Machine...............................................................................16 BCLK to Core Logic Offset ..................................................................................48 BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................49 System Bus Valid Delay Timings ........................................................................49 System Bus Setup and Hold Timings..................................................................49 System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages) ................................................................................................50 System Bus Reset and Configuration Timings (For the FC-PGA/FC-PGA2 Package) ..............................................................................50 Power-On Reset and Configuration Timings.......................................................51 Test Timings (TAP Connection) ..........................................................................51 Test Reset Timings .............................................................................................51 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....53 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers .......................................................................................................54 Low to High AGTL+ Receiver Ringback Tolerance.............................................56 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .....................57 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform (FC-PGA/FC-PGA2 Packages) ...........................................................................63 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ....................64 Processor Functional Die Layout (CPUID 0686h)...............................................67 Processor Functional Die Layout (up to CPUID 0683h)......................................67 Processor Substrate Dimensions (S.E.P. Package) ...........................................70 Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)....70 Package Dimensions (PPGA Package) ..............................................................79 PPGA Package (Pin Side View)..........................................................................81 Package Dimensions (FC-PGA Package)...........................................................92 Package Dimensions (FC-PGA2 Package).........................................................94 Volumetric Keep-Out ...........................................................................................96 Component Keep-Out .........................................................................................96 Package Dimensions (FC-PGA/FC-PGA2 Packages) ........................................97 Top Side Processor Markings (PPGA Package)...............................................108 Top Side Processor Markings (FC-PGA Package) ...........................................108 Top Side Processor Markings (FC-PGA2 Package) .........................................108 Retention Mechanism for the Boxed Intel® Celeron® Processor in the S.E.P. Package .................................................................................................111 Side View Space Requirements for the Boxed Processor in the S.E.P. Package ............................................................................................................111 Front View Space Requirements for the Boxed Processor in the S.E.P. Package ............................................................................................................112 Boxed Intel® Celeron® Processor in the PPGA Package..................................113 Side View Space Requirements for the Boxed Processor in the PPGA Package ............................................................................................................113 Conceptual Drawing of the Boxed Intel® Celeron® Processor in the 370-Pin Socket (FC-PGA/FC-PGA2 Packages)................................................114 Dimensions of Mechanical Step Feature in Heatsink Base for the FC-PGA/FC-PGA2 Packages ...........................................................................114 Top View Airspace Requirements for the Boxed Processor in the S.E.P. Package .................................................................................................115 Datasheet 5 Intel® Celeron® Processor up to 1.10 GHz 39 40 41 42 43 44 Side View Airspace Requirements for the Boxed Intel® Celeron® Processor in the FC-PGA/FC-PGA2 and PPGA Packages .............................. 116 Volumetric Keepout Requirements for The Boxed Fan Heatsink...................... 116 Clip Keepout Requirements for the 370-Pin (Top View) ................................... 117 Boxed Processor Fan Heatsink Power Cable Connector Description .............. 118 Motherboard Power Header Placement for the S.E.P. Package ...................... 119 Motherboard Power Header Placement Relative to the 370-pin Socket........... 119 6 Datasheet Intel® Celeron® Processor up to 1.10 GHz Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Processor Identification .......................................................................................13 Voltage Identification Definition ...........................................................................20 Intel® Celeron® Processor System Bus Signal Groups.......................................22 Absolute Maximum Ratings................................................................................24 Voltage and Current Specifications .....................................................................25 AGTL+ Signal Groups DC Specifications............................................................31 Non-AGTL+ Signal Group DC Specifications......................................................32 Processor AGTL+ Bus Specifications .................................................................33 System Bus AC Specifications (Clock) at the Processor Edge Fingers (for S.E.P. Package)............................................................................................35 System Bus AC Specifications (Clock) at the Processor Core Pins (for Both S.E.P. and PGA Packages) .................................................36 System Bus AC Specifications (SET Clock)........................................................37 Valid Intel® Celeron® Processor System Bus, Core Frequency..........................38 System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge Fingers (for S.E.P. Package) .....................................................................39 System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for S.E.P. Package)...........................................................................39 Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for PPGA Package)..........................................................40 System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for FC-PGA/FC-PGA2 Packages) .....................................................40 System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers (for S.E.P. Package) .....................................................................41 System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins (for Both S.E.P., PGA, and FC-PGA/FC-PGA2 Packages)................41 System Bus AC Specifications (CMOS Signal Group) .......................................42 System Bus AC Specifications (Reset Conditions) (for Both S.E.P. and PPGA Packages) ...............................................................42 System Bus AC Specifications (Reset Conditions) (for the FC-PGA/FC-PGA2 Packages) ............................................................................42 System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge Fingers (for S.E.P. Package) ....................................................43 System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core Pins (For S.E.P. and PGA Packages) .......................................44 System Bus AC Specifications (APIC Clock and APIC I/O) ................................45 System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers (For S.E.P. Package) ....................................................................45 System Bus AC Specifications (TAP Connection) at the Processor Core Pins (for Both S.E.P. and PPGA Packages)...............................................46 System Bus AC Specifications (TAP Connection) ..............................................47 BCLK Signal Quality Specifications for Simulation at the Processor Core (for Both S.E.P. and PPGA Packages) ...............................................................52 BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins (for the FC-PGA/FC-PGA2 Packages).......................................53 BCLK Signal Quality Guidelines for Edge Finger Measurement (for the S.E.P. Package)......................................................................................54 AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core (For Both the S.E.P. and PPGA Packages) ..............................55 Datasheet 7 Intel® Celeron® Processor up to 1.10 GHz 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins (For FC-PGA/FC-PGA2 Packages) ........................................... 55 AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement on the S.E.P. Package ................................................................. 56 Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Core (S.E.P. and PPGA Packages)................................................... 58 Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement (S.E.P. Package).......................................................................... 58 Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Pins (FC-PGA/FC-PGA2 Packages).................................................. 58 Example Platform Information............................................................................. 61 66 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages).................................................. 62 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages).................................................. 63 Processor Power for the PPGA and FC-PGA Packages .................................... 66 Intel® Celeron® Processor for the FC-PGA2 Package Thermal Design Power . 67 Thermal Diode Parameters (S.E.P. and PPGA Packages)................................. 68 Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages)............................... 68 Thermal Diode Interface...................................................................................... 68 S.E.P. Package Signal Listing by Pin Number.................................................... 71 S.E.P. Package Signal Listing by Signal Name .................................................. 75 Package Dimensions (PPGA Package) .............................................................. 80 Information Summary (PPGA Package) ............................................................. 80 PPGA Package Signal Listing by Pin Number .................................................... 82 PPGA Package Signal Listing in Order by Signal Name .................................... 87 Package Dimensions (FC-PGA Package) .......................................................... 93 Processor Die Loading Parameters (FC-PGA Package) .................................... 93 Package Dimensions (FC-PGA2 Package) ........................................................ 95 Processor Case Loading Parameters (FC-PGA2 Package) ............................... 95 FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name ............................... 98 FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number ............................... 103 Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package ... 112 Fan Heatsink Power and Signal Specifications................................................. 118 Alphabetical Signal Reference .......................................................................... 120 Output Signals................................................................................................... 126 Input Signals ..................................................................................................... 127 Input/Output Signals (Single Driver).................................................................. 128 Input/Output Signals (Multiple Driver) ............................................................... 128 8 Datasheet Intel® Celeron® Processor up to 1.10 GHz Revision History Revision -020 Date January 2002 Description • Added IHS specifications for 900 MHz, 950 MHz, and 1 GHz. • Added 566 MHz specification for CPUID of 068Ah. Datasheet 9 Intel® Celeron® Processor up to 1.10 GHz This page is intentionally left blank. 10 Datasheet Intel® Celeron® Processor up to 1.10 GHz 1.0 Introduction The Intel® Celeron® processor is based on the P6 microarchitecture and is optimized for the Value PC market segment. The Intel Celeron processor, like the Pentium ® II processor, features a Dynamic Execution microarchitecture and executes MMX™ technology instructions for enhanced media and communication performance. The Intel Celeron processor also utilizes multiple lowpower states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle times. The Intel Celeron processor is capable of running today’s most common PC applications with up to 4 GB of cacheable memory space. As this processor is intended for Value PC systems, it does not provide multiprocessor support. The Pentium II and Pentium ® III processors should be used for multiprocessor system designs. To be cost-effective at both the processor and system level, the Intel Celeron processor utilizes cost-effective packaging technologies. They are the S.E.P. (Single-Edge Processor) package, the PPGA (Plastic Pin Grid Array) package, the FC-PGA (Flip-Chip Pin Grid Array) package, and the FC-PGA2 (Flip-Chip Pin Grid Array) package. Refer to the Intel® Celeron® Processor Specification Update for the latest packaging and frequency support information (Order Number 243337). Note: This datasheet describes the Intel Celeron processor for the PPGA package, FC-PGA/FC-PGA2 packages, and the S.E.P. Package versions. Unless otherwise specified, the information in this document applies to all versions and information on PGA packages, refer to both PPGA and FC-PGA packages. 1.1 Terminology In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level). The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the AGPset components), and other bus agents. The system bus is an interface to the processor, memory, and I/O. Datasheet 11 Intel® Celeron® Processor up to 1.10 GHz 1.1.1 Package Terminology The following terms are used often in this document and are explained here for clarification: • Processor substrate—The structure on which passive components (resistors and capacitors) are mounted. • Processor core—The processor’s execution engine. • S.E.P. Package—Single-Edge Processor Package, which consists of a processor substrate, processor core, and passive components. This package differs from the S.E.C. Cartridge as this processor has no external plastic cover, thermal plate, or latch arms. • PPGA package—Plastic Pin Grid Array package. The package is a pinned laminated printed circuit board structure. • FC-PGA — Flip-Chip Pin Grid Array. The FC-PGA uses the same 370-pin zero insertion force socket (PGA370) as the PPGA. Thermal solutions are attached directly to the back of the processor core package without the use of a thermal plate or heat spreader. • FC-PGA2 — Flip Chip Pin Grid Array 2. The FC-PG2A uses the same 370-pin zero insertion force socket (PGA370) as the PPGA. The FC-PGA2 package contains an Integrated Heat Spreader that covers the processor die. • Keepout zone - The area on or near a FC-PGA/FC-PGA2 packaged processor that system designs can not utilize. • Keep-in zone - The area of a FC-PGA packaged processor that thermal solutions may utilize. Additional terms referred to in this and other related documentation: • SC242—242-contact slot connector. A processor in the S.E.P. Package uses this connector to interface with a system board. • 370-pin socket (PGA370)—The zero insertion force (ZIF) socket in which a processor in the PPGA package will use to interface with a system board. • Retention mechanism—A mechanical assembly which holds the package in the SC242 connector. 12 Datasheet Intel® Celeron® Processor up to 1.10 GHz 1.1.2 Processor Naming Convention A letter(s) is added to certain processors (e.g., 533A MHz) when the core frequency alone may not uniquely identify the processor. Below is a summary of what each letter means as well as a table listing all the FC-PGA/FC-PGA2 processors for the PGA370 socket. Table 1. Processor Identification Processor 300 MHz 300A MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533A MHz 566 MHz 600 MHz 633 MHz 667 MHz 700 MHz 733 MHz 766 MHz 800 MHz 850 MHz 900 MHz 950 MHz 1 GHz 1.10 GHz Core Frequency 300 MHz 300 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533 MHz 566 MHz 600 MHz 633 MHz 667 MHz 700 MHz 733 MHz 766 MHz 800 MHz 850 MHz 900 MHz 950 MHz 1 GHz 1.10 MHz System Bus Frequency (MHz) 66 66 66 66 66 66 66 66 66 66 66 66 66 66 66 66 100 100 100 100 100 100 CPUID1 065xh 066xh 066xh 066xh 066xh 066xh 066xh 066xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh NOTES: ® 1. Refer to the Intel® Celeron Processor Specification Update for the exact CPUID for each processor. Datasheet 13 Intel® Celeron® Processor up to 1.10 GHz 1.2 References The reader of this specification should also be familiar with material and concepts presented in the following documents: • AP-485, Intel® Processor Identification and the CPUID Instruction (Order Number 241618)1 • AP-589, Design for EMI (Order Number 243334)1 • AP-900, Identifying Support for Streaming SIMD Extensions in the Processor and Operating System1 • AP-905, Pentium® III Processor Thermal Design Guidelines1 • AP-907, Pentium® III Processor Power Distribution Guidelines1 • Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 933 MHz Datasheet (Order Number 245264) • • • • • Intel® Pentium® III Processor Thermal Metrology for CPUID 068h Family1 Intel® Pentium® III Processor Software Application Development Application Notes1 Intel® Celeron® Processor Specification Update (Order Number 243748) 370-Pin Socket (PGA370) Design Guidelines (Order Number 244410) Intel® Architecture Software Developer's Manual (Order Number 243193) — Volume I: Basic Architecture (Order Number 243190) — Volume II: Instruction Set Reference (Order Number 243191) — Volume III: System Programming Guide (Order Number 243192) • Intel® 440EX AGPset Design Guide (Order Number 290637) • Intel® Celeron® Processor with the Intel® 440LX AGPset Design Guide (Order Number 245088) • Intel® 440BX AGPset Design Guide (Order Number 290634) • Intel® Celeron® Processor with the Intel® 440ZX-66 AGPset Design Guide (Order Number 245126) • Intel® Celeron® Processor (PPGA) at 466 MHz Thermal Solutions Guidelines (Order Number 245156) Notes: 1. This reference material can be found on the Intel Developer’s Web site located at http://developer.intel.com. 2. For a complete listing of the Intel® Celeron® processor reference material, refer to the Intel Developer’s Web site when this processor is formally launched. The Web site is located at http://developer.intel.com/design/celeron/. 14 Datasheet Intel® Celeron® Processor up to 1.10 GHz 2.0 2.1 Electrical Specifications System Bus and VREF Celeron processor signals use a variation of the low voltage Gunning Transceiver Logic (GTL) signaling technology. The Intel Celeron processor system bus specification is similar to the GTL specification, but has been enhanced to provide larger noise margins and reduced ringing. The improvements are accomplished by increasing the termination voltage level and controlling the edge rates. Because this specification is different from the standard GTL specification, it is referred to as Assisted Gunning Transceiver Logic (AGTL+) in this document. The Celeron processor varies from the Pentium Pro processor in its output buffer implementation. The buffers that drive the system bus signals on the Celeron processor are actively driven to VCCCORE for one clock cycle during the low-to-high transition. This improves rise times and reduces overshoot. These signals should still be considered open-drain and require termination to a supply that provides the logic-high signal level. The AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used by the receivers to determine if a signal is a logic-high or a logic-low, and is provided to the processor core by either the processor substrate (S.E.P. Package) or the motherboard (PGA370 socket). Local VREF copies should be generated on the motherboard for all other devices on the AGTL+ system bus. Termination is used to pull the bus up to the high voltage level and to control reflections on the transmission line. The processor may contain termination resistors (S.E.P. Package, FC-PGA Package, and FC-PGA2 Package) that provide termination for one end of the Intel Celeron processor system bus. Otherwise, this termination must exist on the motherboard. Solutions exist for single-ended termination as well, though this implementation changes system design and eliminate backwards compatibility for Celeron processors in the PPGA package. Single-ended termination designs must still provide an AGTL+ termination resistor on the motherboard for the RESET# signal. The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+ signals are based on motherboard flight time as opposed to capacitive deratings. Analog signal simulation of the Intel Celeron processor system bus, including trace lengths, is highly recommended when designing a system. See the Pentium® II Processor AGTL+ Layout Guidelines and the Pentium® II Processor I/O Buffer Models, Quad Format (Electronic Form) for details. 2.2 Clock Control and Low Power States Celeron processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 1 for a visual representation of the Intel Celeron processor low power states. For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02Ah (hex), bit 26 must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks during these modes. For more information, see the Pentium® II Processor Developer's Manual (Order Number 243502). Datasheet 15 Intel® Celeron® Processor up to 1.10 GHz 2.2.1 Normal State—State 1 This is the normal operating state for the processor. 2.2.2 AutoHALT Power Down State—State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide (Order Number 243192) for more information. FLUSH# will be serviced during the AutoHALT state, and the processor will return to the AutoHALT state. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. Figure 1. Clock Control State Machine HALT Instruction and HALT Bus Cycle generated INIT#, BINIT#, INTR, SMI#, RESET# 2. Auto HALT Power Down State BCLK running. Snoops and interrupts allowed. 1. Normal State Normal execution. Snoop Event Occurs Snoop Event Serviced STPCLK# Deasserted and Stop Grant entered from Auto HALT. STPCLK# asserted STPCLK# deasserted 4. Auto HALT Power Down State BCLK running. Snoops and interrupts allowed. Snoop event occurs Snoop event serviced 3. Stop Grant State BCLK running. Snoops and interrupts allowed. SLP# asserted SLP# deasserted 5. Sleep State BCLK running. Snoops and interrupts allowed. BCLK input stopped BCLK input restarted 6. Deep Sleep State BCLK stopped. No Snoops and interrupts allowed. 16 Datasheet Intel® Celeron® Processor up to 1.10 GHz 2.2.3 Stop-Grant State—State 3 The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from Stop-Grant state. FLUSH# will not be serviced during Stop-Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the system bus (see Section 2.2.4). A transition to the Sleep state (see Section 2.2.5) will occur with the assertion of the SLP# signal. While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. 2.2.4 HALT/Grant Snoop State—State 4 The processor will respond to snoop transactions on the Celeron processor system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the Intel Celeron processor system bus has been serviced (whether by the processor or another agent on the Intel Celeron processor system bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate. 2.2.5 Sleep State—State 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT states. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. Datasheet 17 Intel® Celeron® Processor up to 1.10 GHz While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep state, by stopping the BCLK input. (See Section 2.2.6.) Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum assertion of one BCLK period. 2.2.6 Deep Sleep State—State 6 The Deep Sleep state is the lowest power state the processor can enter while maintaining context. The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK is stopped. It is recommended that the BLCK input be held low during the Deep Sleep State. Stopping of the BCLK input lowers the overall current consumption to leakage levels. To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals are allowed on the system bus while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. 2.2.7 Clock Control BCLK provides the clock signal for the processor and on die L2 cache. During AutoHALT Power Down and Stop-Grant states, the processor processes a system bus snoop. The processor does not stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state. When the processor is in the Sleep or Deep Sleep states, it does not respond to interrupts or snoop transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache will be restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor has re-entered Sleep state). PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states. PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep Sleep state to the Sleep state, PICCLK must be restarted with BCLK. 2.3 Power and Ground Pins There are five pins defined on the S.E.P. Package for voltage identification (VID) and four pins on the PPGA, FC-PGA, and FC-PGA2 packages. These pins specify the voltage required by the processor core. These have been added to cleanly support voltage specification variations on current and future Celeron processors. For clean on-chip power distribution, Intel Celeron processors in the S.E.P. Package have 27 VCC (power) and 30 VSS (ground) inputs. The 27 VCC pins are further divided to provide the different voltage levels to the components. VCCCORE inputs for the processor core account for 19 of the VCC pins, while 4 VTT inputs (1.5 V) are used to provide a AGTL+ termination voltage to the processor. For only the S.E.P. Package, one VCC5 pin is provided for Voltage Transient Tools. VCC5 and VCCCORE must remain electrically separated from each other. 18 Datasheet Intel® Celeron® Processor up to 1.10 GHz The PPGA package has more power (88) and ground (80) pins than the S.E.P. Package. Of the power pins, 77 are used for the processor core (VCCCORE) and 8 are used as a AGTL+ reference voltage (VREF). The other 3 power pins are VCC1.5, VCC2.5 and VCCCMOS and are used for future processor compatibility. FC-PGA/FC-PGA2 packages have 77 VCCCORE, 77 ground pins, eight VREF, one VCC1.5, one VCC2.5, and one VCCCMOS. VCCCORE inputs supply the processor core, including the on-die L2 cache. The VREF inputs are used as the AGTL+ reference voltage for the processor. The VCCCMOS pin is provided as a feature for future processor support in a flexible design. In such a design, the VCCCMOS pin is used to provide the CMOS voltage for use by the platform. Additionally, 2.5 V must be provided to the VCC2.5 input and 1.5 V must be provided to the Vcc1.5 input. The processor routes the CMOS voltage level through the package that it is compatible with. For example, processors requiring 1.5 V CMOS voltage levels route 1.5 V to the VCCCMOS output. Each power signal, regardless of package, must meet the specifications stated in Table 4. In addition, all VCCCORE pins must be connected to a voltage island while all VSS pins have to connect to a system ground plane. In addition, the motherboard must implement the VTT pins as a voltage island or large trace. Similarly, all VSS pins must be connected to a system ground plane. 2.3.1 Phase Lock Loop (PLL) Power It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements. A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated, decoupled power source for the internal PLL. 2.4 Processor Decoupling Due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or a reduced lifetime of the component. 2.4.1 System Bus AGTL+ Decoupling The S.E.P. Package and FC-PGA/FC-PGA2 packages contain high frequency decoupling capacitance on the processor substrate, where the PPGA package does not. Therefore, Celeron processors in the PGA packages require high frequency decoupling on the system motherboard. Bulk decoupling must be provided on the motherboard for proper AGTL+ bus operation for all packages. See AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330), AP587, Pentium® II Processor Power Distribution Guidelines (Order Number 243332), and the Pentium® II Processor Developer's Manual (Order Number 243502) for more information. Datasheet 19 Intel® Celeron® Processor up to 1.10 GHz 2.5 Voltage Identification The processor’s voltage identification (VID) pins can be used to automatically select the VCCCORE voltage from a compatible voltage regulator. There are five VID pins (VID[4:0]) on the S.E.P. Package, while there are only four (VID[3:0]) on the PGA packages. This is because there are no Celeron processors in the PGA package that require more than 2.05 V (see Table 2). VID pins are not signals, but rather are an open or short circuit to VSS on the processor. The combination of opens and shorts defines the processor core’s required voltage. The VID pins also allow for compatibility with current and future Intel Celeron processors. Note that the ‘11111’ (all opens) ID can be used to detect the absence of a processor core in a given slot (S.E.P. Package only), as long as the power supply used does not affect the VID signals. Detection logic and pull-ups should not affect VID inputs at the power source (see Section 7.0). External logic monitoring the VID signals or the voltage regulator may require the VID pins to be pulled-up. If this is the case, the VID pins should be pulled up to a TTL-compatible level with external resistors to the power source of the regulator. The power source chosen must be guaranteed to be stable whenever the voltage regulator’s supply is stable. This will prevent the possibility of the processor supply going above the specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can be accomplished by using the input voltage to the converter for the VID line pull-ups. In addition, the power supply must supply the requested voltage or disable itself. Table 2. Voltage Identification Definition VID4 (S.E.P.P. only) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCCCORE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 No Core4 2.14 NOTES: 1. 0 = Processor pin connected to VSS. 2. 1 = Open on processor; may be pulled up to TTL VIH on motherboard. 3. The Celeron processor core uses a 2.0 V power source. 4. VID4 applies only to the S.E.P. Package. VID[3:0] applies to both S.E.P. and PGA packages. 20 Datasheet Intel® Celeron® Processor up to 1.10 GHz 2.6 System Bus Unused Pins All RESERVED pins must remain unconnected. Connection of these pins to VCCCORE, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Celeron processor products. See Section 5.0 for a pin listing of the processor and the location of each RESERVED pin. For Intel Celeron processors in the S.E.P. Package, the TESTHI pin must be at a logic-high level when the core power supply comes up. For more information, please refer to erratum C26 of the Intel® Celeron® Processor Specification Update (Order Number 243748). Also note that the TESTHI signal is not available on Intel Celeron processors in the PGA package. PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to 2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each PICD line. For reliable operation, always connect unused inputs or bi-directional signals to their deasserted signal level. The pull-up or pull-down resistor value is system dependent and should be chosen such that the logic-high (VIH) and logic-low (VIL) requirements are met. For the S.E.P. Package, unused AGTL+ inputs should not be connected as the package substrate has termination resistors. On the other hand, the PGA packages do not have AGTL+ termination in their package and must have any unused AGTL+ inputs terminated through a pull-up resistor. For designs that intend to only support the FC-PGA/FC-PGA2 processors, unused AGTL+ inputs will be terminated by the processor’s on-die termination resistors and, thus, do not need to be terminated on the motherboard. However, the reset pin should always be terminated on the motherboard. For unused CMOS inputs, active-low signals should be connected through a pull-up resistor to meet VIH requirements and active-high signals should be connected through a pull-down resistor to meet VIL requirements. Unused CMOS outputs can be left unconnected. A resistor must be used when tying bi-directional signals to power or ground. For any signal pulled to either power or ground, a resistor will allow for system testability. 2.7 Processor System Bus Signal Groups To simplify the following discussion, the Celeron processor system bus signals have been combined into groups by buffer type. All Celeron processor system bus outputs are open drain and require a high-level source provided externally by the termination or pull-up resistor. AGTL+ input signals have differential input buffers, which use VREF as a reference signal. AGTL+ output signals require termination to 1.5 V. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. EMI pins (S.E.P. Package only) should be connected to motherboard ground and/or to chassis ground through zero ohm (0 Ω) resistors. The zero ohm resistors should be placed in close proximity to the SC242 connector. The path to chassis ground should be short in length and have a low impedance. The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and STPCLK#) must be pulled up to VCCCMOS. In addition, the CMOS, APIC, and TAP outputs are Datasheet 21 Intel® Celeron® Processor up to 1.10 GHz open drain and should be pulled high to VCCCMOS. This ensures not only correct operation for current Intel Celeron processors, but compatibility for future Intel Celeron processor products as well. The groups and the signals contained within each group are shown in Table 3. Refer to Section 7.0 for descriptions of these signals. Table 3. Intel® Celeron® Processor System Bus Signal Groups Group Name AGTL+ Input AGTL+ Output AGTL+ I/O CMOS Input4 CMOS Input CMOS Output4 System Bus Clock APIC Clock APIC I/O 4 4 4 Signals BPRI#, DEFER#, RESET#11, RS[2:0]#, TRDY# PRDY# A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#8, D[63:0]#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#2, STPCLK# PWRGOOD1,9 FERR#, IERR#, THERMTRIP#3 BCLK9 PICCLK9 PICD[1:0] TCK, TDI, TMS, TRST# TDO CPUPRES#7, EDGCTRL7, EMI6, PLL[2:1]7, SLOTOCC#6, THERMDP, THERMDN, VCC1.57, VCC2.57, VCCL25, VCC56, VCCCMOS7, VCCCORE, VCOREDET7, VID[3:0]7, VID[4:0]6, VREF[7:0]7, VSS, VTT14, RTTCTRL12, BSEL[1:0]10, SLEWCTRL13 TAP Input TAP Output Power/Other5 NOTES: 1. See Section 7.0 for information on the PWRGOOD signal. 2. See Section 7.0 for information on the SLP# signal. 3. See Section 7.0 for information on the THERMTRIP# signal. 4. These signals are specified for 2.5 V operation for S.E.P.P. and PPGA packages; they are specified at 1.5V operation for the FC-PGA/FC-PGA2 packages. 5. VCCCORE is the power supply for the processor core. VID[4:0] and VID[3:0] are described in Section 2.0. VTT is used to terminate the system bus and generate VREF on the processor substrate. VSS is system ground. VCC5 is not connected to the Celeron processor. This supply is used for Voltage Transient Tools. SLOTOCC# is described in Section 7.0. BSEL is described in Section 2.7.2 and Section 7.0. EMI pins are described in Section 7.0. VCCL2 is a Pentium® II processor reserved signal provided to maintain compatibility with the Pentium® II processor and may be left as a no-connect for “Intel Celeron processor-only” designs. 6. Only applies to Intel Celeron processors in the S.E.P. Package. 7. Only applies to Intel Celeron processors in the PPGA and FC-PGA/FC-PGA2 packages. 8. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information. 9. These signals are specified for 2.5 V operation. 10.BSEL1 is not used in Celeron processors. 11. RESET# must always be terminated to VTT on the motherboard for PGA packages. On-die termination is not provided for this signal on FC-PGA/FC-PGA2 packages. 12.For the FC-PGA/FC-PGA2 packages, this signal is used to control the value of the processor on-die termination resistance. Refer to the specific platform design guide for the recommended pull-down resistor value. 13.Only applies to Intel Celeron processors in the FC-PGA/FC-PGA2 packages. 14.S.E.P. Package and FC-PGA/FC-PGA2 packages. 22 Datasheet Intel® Celeron® Processor up to 1.10 GHz 2.7.1 Asynchronous Vs. Synchronous for System Bus Signals All AGTL+ signals are synchronous to BCLK. All of the CMOS, APIC, and TAP signals can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK. 2.7.2 System Bus Frequency Select Signal (BSEL[1:0]) The BSEL pins have two functions. First, they can act as outputs and can be used by an external clock generator to select the proper system bus frequency. Second, they can act as an inputs and can be used by a system BIOS to detect and report the processor core frequency. See the Intel® Celeron® Processor with the Intel® 440ZX-66 AGPset Design Guide (Order Number 245126) for an example implementation of BSEL. BSEL0 is 3.3 V tolerant for the S.E.P. Package, while it is 2.5 V tolerant on the PPGA package. A logic-low on BSEL0 is defined as 66 MHz. On the FC-PGA/FC-PGA2 packages a logic low on both BSEL0 and BSEL1 are defined as 66 MHz and are 3.3V tolerant. 2.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Celeron processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting a VccCMOS (1.5V or 2.5 V) input. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a different voltage level. A Debug Port may be placed at the start and end of the TAP chain with the TDI of the first component coming from the Debug Port and the TDO from the last component going to the Debug Port. 2.9 Maximum Ratings Table 4 contains the Celeron processor stress ratings only. Functional operation at the absolute maximum and minimum is not implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. Datasheet 23 Intel® Celeron® Processor up to 1.10 GHz Table 4. Absolute Maximum Ratings Symbol TSTORAGE Parameter Processor storage temperature Any processor supply voltage with respect to VSS VCC(All) • PPGA and S.E.P.P. • FC-PGA/FC-PGA2 AGTL+ buffer DC input voltage with respect to VSS VinAGTL+ • PPGA and S.E.P.P. • FC-PGA/FC-PGA2 CMOS buffer DC input voltage with respect to VSS VinCMOS • PPGA and S.E.P.P. • FC-PGA/FC-PGA2 IVID ISLOTOCC# ICPUPRES# Mech Max Edge Fingers5 Max VID pin current Max SLOTOCC# pin current Max CPUPRES# pin current Mechanical integrity of processor edge fingers -0.3 VTT - 2.18 -0.58 3.3 2.18 3.18 5 5 5 50 V V V mA mA mA Insertions/ Extractions 5 6 4, 5 3 7, 8, 9 10 –0.3 VTT - 2.18 VCCCORE + 0.7 2.18 V V 7, 8 –0.5 –0.5 Operating voltage + 1.0 2.1 V V 1, 2 Min –40 Max 85 Unit °C Notes NOTES: 1. Operating voltage is the voltage to which the component is designed to operate. See Table 5. 2. This rating applies to the VCCCORE, VCC5, and any input (except as noted below) to the processor. 3. Parameter applies to CMOS, APIC, and TAP bus signal groups only. 4. The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/ extraction cycles. 5. S.E.P. Package Only 6. PGA Packages Only 7. Input voltage can never exceed VSS + 2.8 volts. 8. Input voltage can never go below VTT - 2.18 volts. 9. Parameter applies to CMOS (except BCLK, PICCLK, and PWRGOOD), APIC, and TAP bus signal groups only for VinCMOS on the FC-PGA/FC-PGA2 Packages only. 10.Parameter applies to CMOS signals BCLK, PICCLK, and PWRGOOD for VinCMOS1.5 on FC-PGA/ FC-PGA2 Package only. 2.10 Processor DC Specifications The processor DC specifications in this section are defined for the Celeron processor. See Section 7.0 for signal definitions and Section 5.0 for signal listings. Most of the signals on the Intel Celeron processor system bus are in the AGTL+ signal group. These signals are specified to be terminated to 1.5 V. The DC specifications for these signals are listed in Table 6. To allow connection with other devices, the Clock, CMOS, APIC, and TAP signals are designed to interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 7. Table 5 through Table 8 list the DC specifications for Intel Celeron processors operating at 66 MHz Intel Celeron processor system bus frequencies. Specifications are valid only while meeting specifications for case temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter. 24 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 5. Symbol Voltage and Current Specifications (Sheet 1 of 5) Processor Parameter Core Freq 266 MHz 300 MHz 300A MHz 333 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533A MHz CPUID 0650h 0651h 0650h 0651h 0660h 0665h 0660h 0665h 0660h 0665h 0660h 0665h 0660h 0665h 0665h 0665h 0665h 0683h 0686h 0683h 0686h 068Ah 0683h 600 MHz 0686h 068Ah 0683h 633 MHz 0686h 068Ah 0683h 667 MHz 0686h 068Ah 0683h 700 MHz 0686h 068Ah 0683h 733 MHz 0686h 068Ah 0683h 766 MHz 0686h 068Ah 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 1.50 1.70 1.50 — 1.70 1.75 1.50 1.70 1.75 1.65 1.70 1.75 1.65 1.70 1.75 1.65 1.70 1.75 1.65 1.70 1.75 1.65 1.70 1.75 — V 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 20, 25 2, 3, 4 2, 3, 4 2, 3, 20, 25 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 2, 3, 20 Min Typ Max Unit Notes VCCCORE VCC for processor core 566 MHz Datasheet 25 Intel® Celeron® Processor up to 1.10 GHz Table 5. Symbol Voltage and Current Specifications (Sheet 2 of 5) Processor Parameter Core Freq CPUID 0683h 800 MHz 0686h 068Ah — 850 MHz 0686h 068Ah — 900 MHz — 068Ah — 950 MHz — 068Ah — 1 GHz — 068Ah — 1.10 GHz AGTL+ input reference voltage Static AGTL+ bus termination voltage — 068Ah — VCC for processor core 1.65 1.70 1.75 — 1.70 1.75 — — 1.75 — — 1.75 — — 1.75 — — 1.75 2/ VTT – 3 Min Typ Max Unit Notes 2, 3, 20 2, 3, 20 2, 3, 20 — 2, 3, 20 2, 3, 20 — — 2, 3, 20 — — 2, 3, 20 — — 2, 3, 20 — — 2, 3, 20 VCCCORE — V VREF19 — — — — — — — — — — 2% 1.50 1.50 2.5 1.50 2/ 3VTT + 2% V V V V V ± 2%, 11 1.5 ± 3% 1.5 ± 3% 2.5 ± 5% 1.5 ± 9%5 1.455 1.365 2.375 1.365 1.545 1.365 2.625 1.635 VCC1.516 Transient AGTL+ bus termination voltage VCC for VCCCMOS AGTL+ bus termination voltage Processor core voltage static tolerance level at SC242 pins Processor core voltage transient tolerance level at SC242 pins Processor core voltage static tolerance level at: VCC2.518 VTT Baseboard Tolerance, Static Baseboard Tolerance, Transient — — –0.070 — 0.100 V 6 — — –0.120 — 0.120 V 6 VCCCORE Tolerance, Static • SC242 edge fingers • PPGA processor pins • FC-PGA/ FC-PGA2 processor pins — — — — — — –0.085 -0.089 -0.080 — — — 0.100 0.100 0.040 V V V 7 8 17 26 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 5. Symbol Voltage and Current Specifications (Sheet 3 of 5) Processor Parameter Core Freq Processor core voltage transient tolerance level at: CPUID Min Typ Max Unit Notes VCCCORE Tolerance, Transient • SC242 edge fingers • PPGA processor pins • FC-PGA/ FC-PGA2 processor pins — — — — 266 MHz 300 MHz 300A MHz 333 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533A MHz 566 MHz 600 MHz — — — — — — — — — — — — — — — — 068Ah 0686h 068Ah 0686h 068Ah 0686h 068Ah 0686h 068Ah 0686h 068Ah 0686h 068Ah 0686h 068Ah 0686h 068Ah 068Ah 068Ah 068Ah 068Ah — –0.140 -0.144 -0.130 -0.110 — — — 0.140 0.144 0.080 0.080 8.2 9.3 9.3 10.1 11.2 12.2 12.6 13.4 14.2 14.9 11.4 11.9 12.1 12.0 12.6 12.7 V V V 7 8 17 24 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10, 25 9, 10 9, 10, 25 9, 10 ICCCORE ICC for processor core 633 MHz 667 MHz 700 MHz 733 MHz 766 MHz 800 MHz 850 MHz 900 MHz 950 MHz 1 GHz 1.10 GHz Termination voltage supply current — 13.0 13.3 13.9 14.0 14.8 14.6 15.4 15.5 16.0 16.0 16.6 16.2 17.3 18.4 19.4 20.2 22.6 A 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 9, 10 IVTT — — — 2.7 A 11 Datasheet 27 Intel® Celeron® Processor up to 1.10 GHz Table 5. Symbol Voltage and Current Specifications (Sheet 4 of 5) Processor Parameter Core Freq 266 MHz 300 MHz 300A MHz 333 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533A MHz ICC Stop-Grant for processor core 566 MHz 600 MHz 633 MHz 667 MHz 700 MHz 733 MHz 766 MHz 800 MHz 850 MHz 900 MHz 950 MHz 1 GHz 1.10 GHz CPUID 1.12 1.15 1.15 1.18 1.21 1.25 1.30 1.35 1.43 1.52 2.5 — — — 6.921 6.921 6.921 6.921 6.921 6.921 6.921 6.921 6.921 6.921 6.921 6.921 6.921 A 12 Min Typ Max Unit Notes ISGNT 28 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 5. Symbol Voltage and Current Specifications (Sheet 5 of 5) Processor Parameter Core Freq 266 MHz 300 MHz 300A MHz 333 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533A MHz ICC Sleep for processor core 566 MHz 600 MHz 633 MHz 667 MHz 700 MHz 733 MHz 766 MHz 800 MHz 850 MHz 900 MHz 950 MHz 1 GHz 1.10 GHz ICC Deep Sleep for processor core: CPUID 0.90 0.94 0.94 0.96 0.97 0.99 1.01 1.03 1.09 1.16 2.5 — — — 6.622 6.922 6.922 6.922 6.922 6.922 6.922 6.922 6.922 6.922 6.922 6.922 6.922 A Min Typ Max Unit Notes ISLP IDSLP • S.E.P.P and PPGA • FC-PGA/ FC-PGA2 ICC for VCCCMOS • S.E.P.P and PPGA • FC-PGA/ FC-PGA2 Power supply current slew rate — — — — — — — — 0.90 6.623 A ICCCMOS — — — — — — — — 500 250 mA mA dICCCORE/dt • S.E.P.P • PPGA and FC-PGA/ FC-PGA2 Termination current slew rate — — — — — — — — 20 240 A/µs A/µs 13, 14, 15 13, 14 See Table 8, Table 20, Table 22 dICCVTT/dt — — — — 8 A/µs Datasheet 29 Intel® Celeron® Processor up to 1.10 GHz NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VCCCORE and ICCCORE supply the processor core. 3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. 4. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to the processor. 5. VTT must be held to 1.5 V ± 9%. It is recommended that V TT be held to 1.5 V ± 3% while the Celeron® processor system bus is idle. This is measured at the processor edge fingers. 6. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC242 connector pin on the bottom side of the baseboard. The requirements at the SC242 connector pins account for voltage drops (and impedance discontinuities) across the connector, processor edge fingers, and to the processor core. VCCCORE must return to within the static voltage specification within 100 µs after a transient event. 7. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the processor edge fingers and to the processor core. VCCCORE must return to within the static voltage specification within 100 µs after a transient event. 8. These are the tolerance requirements, across a 20 MHz bandwidth, at the top of the PPGA package. VCCCORE must return to within the static voltage specification within 100 µs after a transient event. 9. Max ICCCORE measurements are measured at VCCCORE max voltage (VCCCORE_TYP + maximum static tolerance), under maximum signal loading conditions. 10.Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of VCCCORE (VCCCORE_TYP). In this case, the maximum current level for the regulator, ICCCORE_REG, can be reduced from the specified maximum current ICCCORE_MAX and is calculated by the equation: ICCCORE_REG = ICCCORE_MAX × VCCCORE_TYP/(VCCCORE_TYP + VCCCORE Tolerance, Transient) 11. The current specified is the current required for a single Intel Celeron processor. A similar amount of current is drawn through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is used (see Section 2.1). 12.The current specified is also for AutoHALT state. 13.Maximum values are specified by design/characterization at nominal VCCCORE. 14.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance tolerable and reaction time of the voltage regulator. This parameter is not tested. 15.dICC/dt specifications are measured and specified at the SC242 connector pins. 16.FC-PGA/FC-PGA2 packages only 17.These are the tolerance requirements across a 20 MHz bandwidth at the FC-PGA/FC-PGA2 socket pins on the solder side of the motherboard. VCCCORE must return to within the static voltage specification within 100 µs after a transient event. 18.PGA only 19.S.E.P Package and FC-PGA/FC-PGA2 Packages only 20.These processors implement independent VTT and VCCCORE power planes. 21.For processors with CPUID of 0686h, the ISGNT is 2.5 A. 22.For processors with CPUID of 0686h, the ISLP is 2.5 A. 23.For processors with CPUID of 0686h, the IDSLP is 2.2 A. 24.This specification is applicable only for processor frequencies of 933 MHz and above. 25.This Intel® Celeron® processor is a Telecommunications and Embedded Group (TSEG) and Embedded Intel Architecture Division (EID) product only. 30 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 6. AGTL+ Signal Groups DC Specifications Symbol Parameter Input Low Voltage VIL • S.E.P.P and PPGA • FC-PGA/FC-PGA2 Input High Voltage VIH • S.E.P.P and PPGA • FC-PGA/FC-PGA2 RON IL Buffer On Resistance Leakage Current for inputs, outputs, and I/O 1.22 VREF + 0.200 VTT VTT 16.67 ±100 V V Ω µA 2, 3 2, 3 8 6, 7 –0.3 –0.150 0.82 VREF – 0.200 V V 9 Min Max Unit Notes NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies and cache sizes. 2. VIH and VOH for the Intel Celeron processor may experience excursions of up to 200 mV above VTT for a single system bus clock. However, input signal drivers must comply with the signal quality specifications in Section 3.0. 3. Minimum and maximum VTT are given in Table 8. 4. Parameter correlated to measurement into a 25 Ω resistor terminated to 1.5 V. 5. IOH for the Intel Celeron processor may experience excursions of up to 12 mA for a single system bus clock. 6. (0 ≤ VIN ≤ 2.0 V +5%) for S.E.P Package and PPGA Package; (0 ≤ VIN ≤ 1.5V +3%) for FC-PGA/FC-PGA2 packages. 7. (0 ≤ VOUT ≤ 2.0 V +5%) for S.E.P Package and PPGA Package; (0 ≤ VOUT ≤ 1.5V +3%) for FC-PGA/ FC-PGA2 packages. 8. Refer to the I/O Buffer Models for IV characteristics. 9. Steady state input voltage must not be above VSS + 1.65 V or below VTT - 1.65 V. Datasheet 31 Intel® Celeron® Processor up to 1.10 GHz Table 7. Non-AGTL+ Signal Group DC Specifications Symbol VIL VIH VIL1.5 VIL2.5 VIH1.5 VIH2.5 VOL Parameter Input Low Voltage Input High Voltage Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output High Voltage VOH • S.E.P.P and PPGA • FC-PGA/FC-PGA2 Output Low Current IOL • S.E.P.P and PPGA • FC-PGA/FC-PGA2 IL Leakage Current for Inputs, Outputs, and I/O 14 9 ±100 mA mA µA 9 3, 4, 5, 6 N/A 2.625 VTT V V All outputs are opendrain to 2.5 V +5% 6, 8, 9 Min –0.3 1.7 –0.150 -0.58 VREF + 0.200 2.0 Max 0.7 2.625 VREF - 0.200 0.700 VTT 3.18 0.4 Unit V V V V V V V 10 2.5 V +5% maximum, Note 10 8, 9 7, 9 5, 8, 9 7, 9 2 Notes NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. Parameter measured at 14 mA (for use with TTL inputs) for S.E.P Package and PPGA Package. It is 9 mA for FC-PGA/FC-PGA2 packages. 3. (0 ≤ VIN ≤ 2.5 V +5%) for PPGA package and S.E.P package only. 4. (0 ≤ VOUT ≤ 2.5 V +5%) for PPGA package and S.E.P package only. 5. (0≤ VIN ≤ 1.5V +3%) for FC-PGA/FC-PGA2 packages only. 6. (0≤ VOUT ≤ 1.5V +3%) for FC-PGA/FC-PGA2 packages only. 7. Applies to non-AGTL+ signals BCLK, PICCLK, and PWRGOOD for FC-PGA/FC-PGA2 Packages only. 8. Applies to non-AGTL+ signals except BCLK, PICCLK, and PWRGOOD for FC-PGA/FC-PGA2 packages only. 9. These values are specified at the processor pins for FC-PGA/FC-PGA2 packages only. 10.S.E.P. package and PPGA package only. 32 Datasheet Intel® Celeron® Processor up to 1.10 GHz 2.11 AGTL+ System Bus Specifications It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination resistors to VTT at each end of the signal trace. These termination resistors are placed electrically between the ends of the signal traces and the VTT voltage supply and generally are chosen to approximate the substrate impedance. The valid high and low levels are determined by the input buffers using a reference voltage called VREF. Single ended termination may be possible if trace lengths are tightly controlled, see the Intel® 440EX AGPset Design Guide (Order Number 290637) or the Intel® Celeron ® Processor (PPGA) with the Intel® 440LX AGPset Design Guide (Order Number 245088) for more information. Table 8 below lists the nominal specification for the AGTL+ termination voltage (VTT). The AGTL+ reference voltage (VREF) is generated on the processor substrate (S.E.P. Package only) for the processor core, but should be set to 2/3 VTT for other AGTL+ logic using a voltage divider on the motherboard. It is important that the motherboard impedance be specified and held to: • ±20% tolerance (S.E.E.P. and PPGA) • ±15% tolerance (FC-PGA/FC-PGA2) It is also important that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on AGTL+, see the Pentium® II Processor Developer's Manual (Order Number 243502) and AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330). Table 8. Processor AGTL+ Bus Specifications Symbol Parameter Bus Termination Voltage VTT • S.E.P.P and PPGA • FC-PGA/FC-PGA2 Termination Resistor RTT • S.E.P.P and PPGA • FC-PGA/FC-PGA2 (on die RTT) Bus Reference Voltage VREF • S.E.P.P and PPGA • FC-PGA/FC-PGA2 0.950 2 Min Typ Max Units Notes 1.365 1.50 1.50 1.635 V V 1.5 V ± 9% 2 4 56 40 130 Ω Ω ± 5% 5 /3 VTT 1.05 V V ± 2% 3 6 2/3 VTT NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. VTT must be held to 1.5 V ± 9%; dICCVTT/dt is specified in Table 5. It is recommended that VTT be held to 1.5 V ± 3% while the Intel Celeron processor system bus is idle. This is measured at the processor edge fingers. 3. VREF is generated on the processor substrate to be 2/3 VTT nominally with the S.E.P. package. It must be created on the motherboard for processors in the PPGA package. 4. VTT and Vcc1.5 must be held to 1.5V ±9%. It is required that VTT and Vcc1.5 be held to 1.5 V ±3% while the processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom side of the baseboard. 5. The value of the on-die RTT is determined by the resistor value measured by the RTTCTRL signal pin. The on-die RTT tolerance is ±15% based on the RTTCTRL resistor pull-down of ±1%. See Section 7.0 for more details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific chipset/processor combination. 6. VREF is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate VREF decoupling on the motherboard. Datasheet 33 Intel® Celeron® Processor up to 1.10 GHz 2.12 System Bus AC Specifications The Celeron processor system bus timings specified in this section are defined at the Intel Celeron processor edge fingers and the processor core pins. Timings specified at the processor edge fingers only apply to the S.E.P. Package and timings given at the processor core pins apply to all S.E.P. Package and PGA packages. Unless otherwise specified, timings are tested at the processor core during manufacturing. Timings at the processor edge fingers are specified by design characterization. See Section 7.0 for the Intel Celeron processor signal definitions. Note that at 66 MHz system bus operation, the Intel Celeron processor timings at the processor edge fingers are identical to the Pentium II processor timings at the edge fingers. See the Pentium® II Processor at 233, 266, 300, and 333 MHz (Order Number 243335) for more detail. Table 9 through Table 26 list the AC specifications associated with the Intel Celeron processor system bus. These specifications are broken into the following categories: Table 9 through Table 12 contain the system bus clock specifications, Table 13 and Table 14 contain the AGTL+ specifications, Table 17 and Table 18 are the CMOS signal group specifications, Table 20 contains timings for the Reset conditions, Table 22 and Table 23 cover APIC bus timing, and Table 25 and Table 26 cover TAP timing. For each pair of tables, the first table contains timing specifications for measurement or simulation at the processor edge fingers. The second table contains specifications for simulation at the processor core pads. All Intel Celeron processor system bus AC specifications for the AGTL+ signal group are relative to the rising edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and ‘1’ logic levels unless otherwise specified. The timings specified in this section should be used in conjunction with the I/O buffer models provided by Intel. These I/O buffer models, which include package information, are available in Quad format as the Intel Celeron® Processor I/O Buffer Models, Quad XTK Format (Electronic Form). AGTL+ layout guidelines are also available in AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330). Care should be taken to read all notes associated with a particular timing parameter. 34 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers (for S.E.P. Package) T# Parameter System Bus Frequency T1’: BCLK Period T1B’: SC242 to Core Logic BCLK Offset T2’: BCLK Period Stability T3’: BCLK High Time T4’: BCLK Low Time T5’: BCLK Rise Time T6’: BCLK Fall Time 4.44 4.44 0.84 0.84 2.31 2.31 15.0 0.78 ± 300 Min Nom 66.67 Max Unit MHz ns ns ps ns ns ns ns 3 3 3 3 3 3 4, 5, 6 Absolute Value 7,8 See Table 10 @>2.0 V 6 @2.0 V 6 @ 1.7 V @ < 0.7 V (0.7 V–1.7 V) (1.7 V–0.7 V) 4 4 4, 5, 6 4, 5, 6 Figure Notes NOTES: 1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies. 2. These specifications are tested during manufacturing. 3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins. 4. Referenced to PICCLK rising edge. 5. For open drain signals, valid delay is synonymous with float delay. 6. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V. Table 25. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers (For S.E.P. Package) T# Parameter T30’: TCK Frequency T31’: TCK Period T32’: TCK High Time T33’: TCK Low Time T34’: TCK Rise Time T35’: TCK Fall Time T36’: TRST# Pulse Width T37’: TDI, TMS Setup Time T38’: TDI, TMS Hold Time T39’: TDO Valid Delay T40’: TDO Float Delay T41’: All Non-Test Outputs Valid Delay T42’: All Non-Test Inputs Setup Time T43’: All Non-Test Inputs Setup Time T44’: All Non-Test Inputs Hold Time 5.5 14.5 2.0 40.0 5.5 14.5 2.0 13.5 28.5 27.5 27.5 60.0 25.0 25.0 5.0 5.0 Min Max 16.667 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 3 3 3 6 9 9 9 9 9 9 9 9 @1.7 V @0.7 V (0.7 V–1.7 V) 4 (1.7 V–0.7 V) 4 Asynchronous 5 5 6, 7 6, 7 6, 8, 9 6, 8, 9 5, 8, 9 5, 8, 9 Figure Notes NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Intel ® Celeron® processor frequencies. 2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.70 V at the processor edge fingers. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor edge fingers. 3. Not 100% tested. Specified by design characterization. 4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz. 5. Referenced to TCK rising edge. 6. Referenced to TCK falling edge. 7. Valid delay timing for this signal is specified to 2.5 V +5%. 8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These timings correspond to the response of these signals due to TAP operations. 9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings. Datasheet 45 Intel® Celeron® Processor up to 1.10 GHz Table 26. System Bus AC Specifications (TAP Connection) at the Processor Core Pins (for Both S.E.P. and PPGA Packages) T# Parameter T30: TCK Frequency T31: TCK Period T32: TCK High Time T33: TCK Low Time T34: TCK Rise Time T35: TCK Fall Time T36: TRST# Pulse Width T37: TDI, TMS Setup Time T38: TDI, TMS Hold Time T39: TDO Valid Delay T40: TDO Float Delay T41: All Non-Test Outputs Valid Delay T42: All Non-Test Inputs Setup Time T43: All Non-Test Inputs Setup Time T44: All Non-Test Inputs Hold Time 5.0 13.0 2.0 40.0 5.0 14.0 1.0 10.0 25.0 25.0 25.0 60.0 25.0 25.0 5.0 5.0 Min Max 16.667 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 3 3 3 6 9 9 9 9 9 9 9 9 @1.7 V; 10 @0.7 V; 10 (0.7 V–1.7 V); 4, 10 (1.7 V–0.7 V); 4, 10 Asynchronous; 10 5 5 6, 7 6, 7, 10 6, 8, 9 6, 8, 9, 10 5, 8, 9 5, 8, 9 Figure Notes NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. For the S.E.P. and PPGA packages: All AC timings for the TAP signals are referenced to the TCK rising edge at 1.25 V at the processor core pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor core pins. For the FC-PGA/FC-PGA2 packages: All AC timings for the TAP signals are referenced to the TCK rising edge at 0.75 V at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor pins. 3. These specifications are tested during manufacturing, unless otherwise noted. 4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz. 5. Referenced to TCK rising edge. 6. Referenced to TCK falling edge. 7. For the S.E.P. and PPGA packages: Valid delay timing for this signal is specified to 2.5 V +5%. For the FC-PGA/FC-PGA2 packages: Valid delay timing for this signal is specified to 1.5 V +3%. 8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These timings correspond to the response of these signals due to TAP operations. 9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings. 10.Not 100% tested. Specified by design characterization. 46 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 27. System Bus AC Specifications (TAP Connection)1, 2, 3 T# Parameter T30: TCK Frequency T31: TCK Period T32: TCK High Time T33: TCK Low Time T34: TCK Rise Time 60.0 25.0 25.0 5.0 Min Max 16.667 Unit MHz ns ns ns ns 3 3 3 3 VREF + 0.200 V, 10 VREF – 0.200 V, 10 (VREF – 0.200 V) – (VREF + 0.200 V), 4, 10 T35: TCK Fall Time T36: TRST# Pulse Width T37: TDI, TMS Setup Time T38: TDI, TMS Hold Time T39: TDO Valid Delay T40: TDO Float Delay T41: All Non-Test Outputs Valid Delay T42: All Non-Test Inputs Setup Time T43: All Non-Test Inputs Setup Time T44: All Non-Test Inputs Hold Time 5.0 13.0 2.0 40.0 5.0 14.0 1.0 10.0 25.0 25.0 25.0 5.0 ns ns ns ns ns ns ns ns ns ns 3 10 9 9 9 9 9 9 9 9 (VREF + 0.200 V) – (VREF – 0.200 V), 4, 10 Asynchronous, 10 5 5 6, 7 6, 7, 10 6, 8, 9 6, 8, 9, 10 5, 8, 9 5, 8, 9 Figure Notes NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processors frequencies. 2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.75 V at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor pins. 3. These specifications are tested during manufacturing, unless otherwise noted. 4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz. 5. Referenced to TCK rising edge. 6. Referenced to TCK falling edge. 7. Valid delay timing for this signal is specified to 1.5 V (1.25 V for AGTL platforms). 8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These timings correspond to the response of these signals due to TAP operations. 9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings. 10.Not 100% tested. Specified by design characterization. Datasheet 47 Intel® Celeron® Processor up to 1.10 GHz Note: For Figure 3 through Figure 10, the following apply: 1. Figure 3 through Figure 10 are to be used in conjunction with Table 9 through Table 26. 2. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor edge fingers. 3. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK rising edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core pins. 4. All AC timings for the CMOS signals at the processor edge fingers are referenced to the BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor edge fingers. 5. All AC timings for the APIC I/O signals at the processor edge fingers are referenced to the PICCLK rising edge at: 0.7 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA/ FC-PGA2 packages. All APIC I/O signal timings are referenced at 1.25 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA/FC-PGA2 packages at the processor edge fingers. 6. All AC timings for the TAP signals at the processor edge fingers are referenced to the TCK rising edge at 0.70 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA/FC-PGA2 packages. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA/FC-PGA2 packages at the processor edge fingers. Figure 2. BCLK to Core Logic Offset BCLK at Edge Fingers T1B' BCLK at Core Logic 1.25V 0.5V 48 Datasheet Intel® Celeron® Processor up to 1.10 GHz Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform th tr 1.7V (2.0V*) CLK 0.7V (0.5V*) tf tl tp 1.25V Tr Tf Th Tl Tp = = = = = T5, T6, T3, T4, T1, T25, T26, T23, T24, T22, T34 T35 T32 T33 T31 (Rise Tim e) (Fall Tim e) (High Tim e) (Low Time) (BLCK, TCK, PICCLK Period) Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK is referenced to 0.7 V and 1.7 V. For S.E.P. and PPGA packages, TCK is referenced to 0.7 V and 1.7 V. For the FC-PGA package, TCK is referenced to V REF ± 200m V. Figure 4. System Bus Valid Delay Timings CLK Tx V Valid Tpw Tx = T7, T11, T29a, T29b (Valid Delay) Tpw = T14, T14B, T15 (Pulse Width) V = 1.0V for AGTL+ signal group; For S.E.P and PPGA packages, 1.25V for CMOS, APIC and JTAG signal groups For FC-PGA package, 0.75V for CMOS, APIC and TAP signal groups Valid Tx Signal Figure 5. System Bus Setup and Hold Timings CLK Ts V Th Valid Signal Ts = T8, T12, T27 (Setup Time) Th = T9, T13, T28 (Hold Time) V = 1.0V for AGTL+ signal group; For S.E.P. and PPGA packages, 1.25V for APIC and JTAG signal groups For the FC-PGA package, 0.75V for APIC and TAP signal groups Datasheet 49 Intel® Celeron® Processor up to 1.10 GHz Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages) BCLK Tu Tt RESET# Tv Tw Valid Tt Tu Tv Tw Tx = T9 (AGTL+ Input Hold Time) = T8 (AGTL+ Input Setup Time) = T10 (RESET# Pulse Width) = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) Tx Configuration (A[14:5]#, BR0#, FLUSH#, INT#) Figure 7. System Bus Reset and Configuration Timings (For the FC-PGA/FC-PGA2 Package) BCLK Tu Tt RESET# Tv Configuration (A20M#, IGNNE#, LINT[1:0]) Configuration (A[14:5]#, BR0#, FLUSH#, INT#) Tt Tu Tv Tw Tx Ty Safe Tw Valid = T9 (AGTL+ Input Hold Time) = T8 (AGTL+ Input Setup Time) = T10 (RESET# Pulse Width) = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time) Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time) Tz Valid Tx 50 Datasheet Intel® Celeron® Processor up to 1.10 GHz Figure 8. Power-On Reset and Configuration Timings BCLK VccCORE, VTT, VREF PWRGOOD Ta RESET# VIL, max VIH, min Tb TC Configuration (A20M#, IGNNE#, INTR, NMI) Ta Tb Tc Valid Ratio = T15 (PWRGOOD Inactive Pulse) = T10 (RESET# Pulse Width) = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) (FC-PGA) Figure 9. Test Timings (TAP Connection) TCK 1.25V Tv Tw TDI, TMS 1.25V Tr Ts Input Signals Tx TDO Tu Ty Output Signals Tz Tr = T43 (All Non-Test Inputs Setup Time) Ts = T44 (All Non-Test Inputs Hold Time) Tu = T40 (TDO Float Delay) Tv = T37 (TDI, TMS Setup Time) Tw = T38 (TDI, TMS Hold Time) Tx = T39 (TDO Valid Delay) Ty = T41 (All Non-Test Outputs Valid Delay) Tz = T42 (All Non-Test Outputs Float Delay) Figure 10. Test Reset Timings TRST# 1.25V Tq Tq = T37 (TRST# Pulse Width) C Datasheet 51 Intel® Celeron® Processor up to 1.10 GHz 3.0 System Bus Signal Simulations Signals driven on the Celeron processor system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component. Specifications are provided for simulation at the processor core; guidelines are provided for correlation to the processor edge fingers. These edge finger guidelines are intended for use during testing and measurement of system signal integrity. Violations of these guidelines are permitted, but if they occur, simulation of signal quality at the processor core should be performed to ensure that no violations of signal quality specifications occur. Meeting the specifications at the processor core in Table 28, Table 31, and Table 34 ensures that signal quality effects will not adversely affect processor operation, but does not necessarily guarantee that the guidelines in Table 30, Table 33, and Table 35 will be met. 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines Table 28 describes the BCLK signal quality specifications at the processor core for both S.E.P. and PPGA Packages. Table 29 shows the BCLK and PICCLK signal quality specifications at the processor core for the FC-PGA/FC-PGA2 packages. Table 30 describes guidelines for signal quality measurement at the processor edge fingers. Figure 11 describes the signal quality waveform for the system bus clock at the processor core pins; Figure 12 describes the signal quality waveform for the system bus clock at the processor edge fingers. Table 28. BCLK Signal Quality Specifications for Simulation at the Processor Core (for Both S.E.P. and PPGA Packages) T# Parameter Min Nom Max Unit Figure Notes V1: BCLK VIL V2: BCLK VIH V3: VIN Absolute Voltage Range V4: Rising Edge Ringback V5: Falling Edge Ringback 2.0 –0.7 1.7 0.5 V V 11 11 11 11 11 2 2 3 3 3.5 V V 0.7 V NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. This is the Intel Celeron processor system bus clock overshoot and undershoot specification for 66 MHz system bus operation. 3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value. 52 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 29. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins (for the FC-PGA/FC-PGA2 Packages) T# Parameter Min Nom Max Unit Figure Notes V1: BCLK VIL V1: PICCLK VIL V2: BCLK VIH V2: PICCLK VIH V3: VIN Absolute Voltage Range V4: BCLK Rising Edge Ringback V4: PICCLK Rising Edge Ringback V5: BCLK Falling Edge Ringback V5: PICCLK Falling Edge Ringback 2.00 2.00 –0.58 2.00 2.00 0.50 0.70 V V V V 11 11 11 11 11 11 11 11 11 2 2 2 2 3.18 V V V 0.50 0.70 V V NOTES: 1. Unless otherwise noted, all specifications in this table apply to FC-PGA/FC-PGA2 processors frequencies and cache sizes. 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value. Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins T3 V3 V4 V2 V1 V5 V3 T6 T4 T5 Datasheet 53 Intel® Celeron® Processor up to 1.10 GHz Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement (for the S.E.P. Package) T# Parameter Min Nom Max Unit Figure Notes V1’: BCLK VIL V2’: BCLK VIH V3’: VIN Absolute Voltage Range V4’: Rising Edge Ringback V5’: Falling Edge Ringback V6’: Tline Ledge Voltage V7’: Tline Ledge Oscillation 1.0 2.0 –0.5 2.0 0.5 V V 12 12 12 12 12 12 12 2 3 3 At Ledge Midpoint 4 Peak-to-Peak 5 3.3 V V 0.5 1.7 0.2 V V V NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. This is the Intel Celeron processor system bus clock overshoot and undershoot measurement guideline. 3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal may dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This guideline is an absolute value. 4. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The midpoint voltage level of this ledge should be within the range of the guideline. 5. The ledge (V7) is allowed to have peak-to-peak oscillation as given in the guideline. Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers T3 V3 V2 V4 V7 V6 V1 V5 V3 T6 T4 T5 54 Datasheet Intel® Celeron® Processor up to 1.10 GHz 3.2 AGTL+ Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330). Refer to the Pentium® II Processor Developer's Manual (Order Number 243502) for the AGTL+ buffer specification. Table 31 provides the AGTL+ signal quality specifications (for both the S.E.P. and PPGA Packages) for use in simulating signal quality at the processor core. Table 32 provides the AGTL+ signal quality specifications (for the FC-PGA/FC-PGA2 packages) for use in simulating signal quality at the processor core. Table 33 provides AGTL+ signal quality guidelines for measuring and testing signal quality at the processor edge fingers. Figure 13 describes the signal quality waveform for AGTL+ signals at the processor core and edge fingers. For more information on the AGTL+ interface, see the Pentium® II Processor Developer's Manual (Order Number 243502). Table 31. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core (For Both the S.E.P. and PPGA Packages) T# Parameter α: Overshoot τ: Minimum Time at High ρ: Amplitude of Ringback φ: Final Settling Voltage δ: Duration of Squarewave Ringback Min Unit Figure Notes 100 1.00 –100 100 N/A mV ns mV mV ns 13 13 13 13 13 4 4 4, 5 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. Specifications are for the edge rate of 0.3 – 0.8 V/ns. See Figure 13 for the generic waveform. 3. All values specified by design characterization. 4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor system bus only. 5. Ringback below VREF + 20 mV is not supported. Table 32. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins (For FC-PGA/FC-PGA2 Packages) T# Parameter α: Overshoot τ: Minimum Time at High ρ: Amplitude of Ringback φ: Final Settling Voltage δ: Duration of Squarewave Ringback Min Unit Figure Notes 100 0.50 –200 200 N/A mV ns mV mV ns 13 13 13 13 13 4, 8, 9, 10 9 5, 6, 7, 8 8 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. Specifications are for the edge rate of 0.3 – 0.8V/ns. See Figure 13 for the generic waveform. 3. All values specified by design characterization. 4. See Table 36 for maximum allowable overshoot. 5. Ringback between VREF + 100 mV and VREF + 200 mV or VREF – 200 mV and VREF – 100 mVs requires the flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (Intel®Pentium®II Developers Manual). Ringback below VREF + 100 mV or above VREF – 100 mV is not supported. 6. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other sources of system noise. 7. A negative value for ρ indicates that the amplitude of ringback is above VREF. (i.e., φ = –100 mV specifies the signal cannot ringback below VREF + 100 mV). 8. φ and ρ: are measured relative to VREF. α: is measured relative to VREF + 200 mV. 9. All Ringback entering the Overdrive Region must have flight time correction. 10.Overshoot specifications for Ringback do not correspond to Overshoot specifications in Section 3.4. Datasheet 55 Intel® Celeron® Processor up to 1.10 GHz Table 33. AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement on the S.E.P. Package T# Parameter α’: Overshoot τ’: Minimum Time at High ρ ’: Amplitude of Ringback φ’: Final Settling Voltage δ’: Duration of Squarewave Ringback Min Unit Figure Notes 100 1.5 –250 250 N/A mV ns mV mV ns 13 13 13 13 13 4 4, 5 4 NOTES: 1. Unless otherwise noted, all guidelines in this table apply to all Celeron processor frequencies. 2. Guidelines are for the edge rate of 0.3 – 0.8 V/ns. See Figure 13 for the generic waveform. 3. All values specified by design characterization. 4. This guideline applies to Intel Celeron processors operating with a 66 MHz system bus only. 5. Ringback below VREF + 250 mV is not supported. Figure 13. Low to High AGTL+ Receiver Ringback Tolerance τ α VREF +0.2 VREF φ ρ VREF –0.2 δ 0.7V Clk Ref Vstart Clock Time Note: High to Low case is analogous. 56 Datasheet Intel® Celeron® Processor up to 1.10 GHz 3.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot, ringback, and settling limit. All three signal quality parameters are shown in Figure 14 for the nonAGTL+ signal group. Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback Overshoot V HI Settling Limit Rising-Edge Ringback Falling-Edge Ringback Settling Limit VLO VSS Time Undershoot NOTES: 1. For the FC-PGA/FC-PGA2 packages, VHI = 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD. VHI = 2.5 V for BCLK, PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1. 3.3.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below VSS. The overshoot/undershoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates. (See Figure 14 for non-AGTL+ signals.) The processor can be damaged by repeated overshoot events on the voltage tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). The PPGA and S.E.P. packages have 2.5 V tolerant buffers and the FC-PGA/FC-PGA2 packages has 1.5 V or 2.5 V tolerant buffers. However, excessive ringback is the dominant detrimental system timing effect resulting from overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make satisfying the ringback specification difficult). The overshoot/undershoot guideline is 0.7 V for the PPGA and S.E.P. packages and 0.3 V for the FC-PGA/FC-PGA2 packages and assumes the absence of diodes on the input. These guidelines should be verified in simulations without the on-chip ESD protection diodes present because the diodes will begin clamping the signals (2.5 V tolerant signals for the S.E.P. and PPGA packages, and 2.5 V or 1.5 V tolerant signals for the FC-PGA/ FC-PGA2 packages) beginning at approximately 0.7 V above the appropriate supply and 0.7 V below VSS. If signals are not reaching the clamping voltage, this will not be an issue. A system should not rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult. Datasheet 57 Intel® Celeron® Processor up to 1.10 GHz 3.3.2 Ringback Specification Ringback refers to the amount of reflection seen after a signal has switched. The ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value. (See Figure 14 for an illustration of ringback.) Excessive ringback can cause false signal detection or extend the propagation delay. The ringback specification applies to the input pin of each receiving agent. Violations of the signal ringback specification are not allowed under any circumstances for non-AGTL+ signals. Ringback can be simulated with or without the input protection diodes that can be added to the input buffer model. However, signals that reach the clamping voltage should be evaluated further. See Table 34 for the signal ringback specifications for non-AGTL+ signals for simulations at the processor core, and Table 35 for guidelines on measuring ringback at the edge fingers. Table 36 lists the ringback specifications for the FC-PGA/FC-PGA2 packages. Table 34. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Core (S.E.P. and PPGA Packages) Input Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure Notes Non-AGTL+ Signals Non-AGTL+ Signals 0→1 1→0 1.7 0.7 V V 14 14 NOTE: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. Table 35. Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement (S.E.P. Package) Input Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure Notes Non-AGTL+ Signals Non-AGTL+ Signals 0→1 1→0 2.0 0.7 V V 14 14 NOTE: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. Table 36. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Pins (FC-PGA/FC-PGA2 Packages) Input Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure Non-AGTL+ Signals PWRGOOD Non-AGTL+ Signals 0→1 0→1 1→0 VREF + 0.200 2.0 VREF – 0.200 V V V 16 16 16 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all FC-PGA/FC-PGA2 processor frequencies and cache sizes. 58 Datasheet Intel® Celeron® Processor up to 1.10 GHz 3.3.3 Settling Limit Guideline Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. The amount allowed is 10 percent of the total signal swing (VHI – VLO) above and below its final value. A signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again. Signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be done either with or without the input protection diodes present. Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions. 3.4 AGTL+ Signal Quality Specifications and Measurement Guidelines (FC-PGA/FC-PGA2 Packages) Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages) Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make satisfying the ringback specification difficult. When performing simulations to determine impact of overshoot and overshoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models are being used to characterize the FC-PGA/FC-PGA2 processor performance, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer model will impact results and may yield excessive overshoot/undershoot. 3.4.1 3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages) Magnitude describes the maximum potential difference between a signal and its voltage reference level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to VTT. This can be accomplished by simultaneously measuring the VTT plane while measuring the signal undershoot. Today’s oscilloscopes can easily calculate the true undershoot waveform using a Math function where the Signal waveform is subtracted from the VTT waveform. The true undershoot waveform can also be obtained with the following oscilloscope data file analysis: Converted Undershoot Waveform = VTT– Signal_measured Note: Note: The converted undershoot waveform appears as a positive (overshoot) signal. Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact must be determined independently. Datasheet 59 Intel® Celeron® Processor up to 1.10 GHz After the true waveform conversion, the undershoot/overshoot specifications shown in Table 38 and Table 39 can be applied to the converted undershoot waveform using the same magnitude and pulse duration specifications used with an overshoot waveform. Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed in Table 38 and Table 39. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the Absolute Maximum Specifications (2.18V), the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications. 3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2 Packages) Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage (Vos_ref = 1.635 V). The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration. Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration. Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the individual Pulse Durations to determine the total Overshoot/Undershoot Pulse Duration for that total event. Note: 3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages) Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. The specifications provided in Table 38 and Table 39 show the Maximum Pulse Duration allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each table entry is independent of all others, meaning that the Pulse Duration reflects the existence of overshoot/ undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). Note: Note: Activity factor for AGTL+ signals is referenced to BCLK frequency. Activity factor for CMOS signals is referenced to PICCLK frequency. 60 Datasheet Intel® Celeron® Processor up to 1.10 GHz 3.4.5 Reading Overshoot/Undershoot Specification Tables (FC-PGA/ FC-PGA2 Packages) The overshoot/undershoot specification for the FC-PGA/FC-PGA2 packages processor is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification. In addition to the magnitude of the overshoot, the following parameters must also be known: the junction temperature the processor will be operating, the width of the overshoot (as measured above 1.635 V) and the Activity Factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the signal group that particular signal falls into. If the signal is an AGTL+ signal operating with a 66 MHz system bus, use Table 38 (66 MHz AGTL+ signal group). If the signal is a CMOS signal, use Table 39 (33 MHz CMOS signal group). 2. Determine the maximum junction temperature (Tj) for the range of processors that the system will support (80oC or 90oC). 3. Determine the Magnitude of the overshoot (relative to VSS) 4. Determine the Activity Factor (how often does this overshoot occur?) 5. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns) allowed. 6. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse Duration measured is less than the Pulse Duration shown in the table, then the signal meets the specifications. The above procedure is similar for undershoots after the undershoot waveform has been converted to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events as they are mutually exclusive. Table 37 shows an example of how the maximum pulse duration is determined for a given waveform. Table 37. Example Platform Information Required Information Maximum Platform Support Notes FSB Signal Group Max Tj Overshoot Magnitude Activity Factor (AF) 66 MHz AGTL+ 90 °C 2.13V 0.1 Measured Value Measured overshoot occurs on average every 20 clocks NOTES: 1. Corresponding Maximum Pulse Duration Specification – 3.2 ns 2. Pulse Duration (measured) – 2.0 ns Given the above parameters, and using Table 38 (90oC/AF=0.1 column) the maximum allowed pulse duration is 3.2 ns. Since the measured pulse duration is 2.0ns, this particular overshoot event passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/ undershoot events meet the specifications. Datasheet 61 Intel® Celeron® Processor up to 1.10 GHz 3.4.6 Determining if a System meets the Overshoot/Undershoot Specifications (FC-PGA/FC-PGA2 Packages) The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet the overshoot specification, when the total impact of all overshoot events is accounted for, the system may fail. A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. It is important to meet these guidelines; otherwise, contact your Intel field representative. 1. Insure no signal (CMOS or AGTL+) ever exceed the 1.635 V; OR 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables; OR 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where AF=1), then the system passes. The following notes apply to Table 38 and Table 39. NOTES: 1. Overshoot/Undershoot Magnitude = 2.18 V is an Absolute value and should never be exceeded 2. Overshoot is measured relative to VSS 3. Undershoot is measured relative to VTT 4. Overshoot/Undershoot Pulse Duration is measured relative to 1.635 V. 5. Ringbacks below VTT can not be subtracted from Overshoots/Undershoots. 6. Lesser Undershoot does not allocate longer or larger Overshoot. 7. Consult the appropriate layout guidelines provided in the specific platform design guide. 8. All values specified by design characterization. Table 38. 66 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages) Overshoot/ Undershoot Magnitude Maximum Pulse Duration at Tj = 80 °C (ns) AF = 0.01 AF = 0.1 AF = 1 Maximum Pulse Duration at Tj = 90 °C (ns) AF = 0.01 AF = 0.1 AF = 1 2.18 V 2.13 V 2.08 V 2.03 V 1.98 V 1.93 V 1.88 V 30 30 30 30 30 30 30 3.8 7.4 13.6 25 30 30 30 0.38 0.74 1.36 2.5 4.56 8.2 15 18 30 30 30 30 30 30 1.8 3.2 6.4 12 22 30 30 0.18 0.32 0.64 1.1 2 3.8 6.8 NOTES: 1. BCLK period is 30.0 ns. 2. Measurements taken at the processor socket pins on the solder-side of the motherboard. 62 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 39. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages) Overshoot/ Undershoot Magnitude Maximum Pulse Duration at Tj = 80 °C (ns) AF = 0.01 AF = 0.1 AF = 1 Maximum Pulse Duration at Tj = 90 °C (ns) AF = 0.01 AF = 0.1 AF = 1 2.18 V 2.13 V 2.08 V 2.03 V 1.98 V 1.93 V 1.88 V 60 60 60 60 60 60 60 7.6 14.8 27.2 50 60 60 60 0.76 1.48 2.7 5 9.1 16.4 30 36 60 60 60 60 60 60 3.6 6.4 12.8 24 44 60 60 0.36 0.64 1.2 2.2 4 7.6 13.6 NOTES: 1. PICCLK period is 30 ns. 2. Measurements taken at the processor socket pins on the solder-side of the motherboard. Figure 15. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform (FC-PGA/FC-PGA2 Packages) Time Dependent Overshoot 2.18V 2.08V 1.98V 1.88V 1.635V VTT Max Converted Undershoot Waveform Overshoot Magnitude Undershoot Magnitude Vss Overshoot = Signal - Vss Magnitude Undershoot = VTT - Signal Magnitude Time Dependent Undershoot Datasheet 63 Intel® Celeron® Processor up to 1.10 GHz 3.5 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot, ringback, and settling limit. All three signal quality parameters are shown in Figure 16 for the nonAGTL+ signal group. Figure 16. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1 Overshoot VHI Settling Limit Rising-Edge Ringback Falling-Edge Ringback Settling Limit VLO VSS Time Undershoot NOTES: 1. VHI = 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD. VHI = 2.5 V for BCLK, PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1. 64 Datasheet Intel® Celeron® Processor up to 1.10 GHz 4.0 Thermal Specifications and Design Considerations This section provides needed data for designing a thermal solution. However, for the correct thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design Guidelines (Order Number 245087). For the FC-PGA/FC-PGA2 using flip chip pin grid array packaging technology, Intel specifies the junction temperature (Tjunction). For the S.E.P. package and PPGA package, Intel specifies the case temperature (Tcase). 4.1 Thermal Specifications Table 40 provides both the Processor Power and Heatsink Design Target for Celeron processors. Processor Power is defined as the total power dissipated by the processor core and its package. Therefore, the S.E.P. Package’s Processor Power would also include power dissipated by the AGTL+ termination resistors. The overall system chassis thermal design must comprehend the entire Processor Power. The Heatsink Design Target consists of only the processor core, which dissipates the majority of the thermal power. Systems should design for the highest possible thermal power, even if a processor with a lower thermal dissipation is planned. The processor’s heatslug is the attach location for all thermal solutions. The maximum and minimum case temperatures are also specified in Table 40. A thermal solution should be designed to ensure the temperature of the case never exceeds these specifications. Refer to the Intel developer Web site at http://developer.intel.com for more information. Datasheet 65 Intel® Celeron® Processor up to 1.10 GHz Table 40. Processor Power for the PPGA and FC-PGA Packages Processor Core Frequency L2 Cache Size (KB) Processor Thermal Design Power2,3 (W) up to CPUID 0686h Processor Thermal Design Power2,3 (W) for CPUID 068Ah Power Density 5 (W/cm2) For CPUID 0686h Power Density 5 (W/cm2) For CPUID 068Ah Min TCASE (°C) Max TCASE (°C) Max10 TJUNCTION (°C) TJUNCTION Offset 6 (°C) 333 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533A MHz 5663 MHz 6003 MHz 633 MHz 667 MHz 700 MHz 733 MHz 766 MHz 800 MHz 850 MHz 900 MHz 950 MHz 1 GHz 1.10 GHz 3 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 19.7 21.7 23.7 24.1 25.6 27.0 28.3 14.0 4,7 NA NA NA NA NA NA NA NA 19.2 19.64 20.24 21.14 21.94 22.8 4 NA NA NA NA NA NA NA 17.5 4 NA NA NA NA NA NA NA NA 304 30.54 31.54 32.94 34.14 35.5 4 5 5 5 5 5 5 5 NA NA NA NA NA NA NA NA NA NA NA NA NA NA 85 85 85 85 70 70 70 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 90 90 90 82 82 80 80 80 80 80 77 79 75 77 NA NA NA NA NA NA NA 2.6 2.6 2.6 2.6 2.6 2.7 2.8 3.0 3.0 3.3 3.6 3.8 3.8 4.4 14.94,8 15.84,9 16.54 17.54 18.34 19.1 4 18.54 19.74 25.84 27.34 28.64 29.8 4 20.04 20.8 4 23.64 24.5 4 31.34 32.6 4 36.84 38.2 4 22.54 NA NA NA NA 25.74 26.74 28.0 29.0 33.0 35.24 NA NA NA NA 40.04 41.64 43.64 45.24 51.44 NOTES: 1. These values are specified at nominal VCCCORE for the processor core. 2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the maximum TJUNCTION specification. 3. FC-PGA package only. 4. The Thermal Design Power (TDP) Celeron® processors in production has been redefined. The updated TDP values are based on device characterization and do not reflect any silicon design changes to lower processor power consumption. The TDP values represent the thermal design point required to cool Celeron® processors in the platform environment while executing thermal validation type software. 5. Power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the die area over which the power is generated. Power for these processors is generated from the core area shown in Figure 17. 6. Tjunctionoffset is the worst-case difference between the thermal reading from the on-die thermal diode and the hottest location on the processor’s core. Tjunctionoffset values do not include any thermal diode kit measurement error. Diode kit measurement error must be added to the Tjunctionoffset value from the table. Intel has characterized the use of the Analog Devices AD1021 diode measurement kit and found its measurement error to be ±1 oC. 7. For processors with a CPUID of 0683h, the TDP number is 11.2 W. 8. For processors with a CPUID of 0683h, the TDP number is 11.9 W. 9. For processors with a CPUID of 0683h, the TDP number is 12.6 W. 10.The Tj min for processors with a CPUID of 068x is 0 oC with a 3 oC– 5 oC margin error. 66 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 41. Intel® Celeron® Processor for the FC-PGA2 Package Thermal Design Power 1 Processor Processor Core Frequency (MHz) System Bus Frequency (MHz) Processor Thermal Design Power 2,3 CPUID 068Ah (W) Maximum Tcase4 (°C) Additional Notes 900 950 1 GHz 900 950 1000 100 100 100 30.0 32.0 33.9 72 72 69 5 5 5 NOTES: 1. These values are specified at nominal VCCCORE for the processor pins. 2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the maximum Tcase specification. 3. TDP does not represent the power delivery and voltage regulation requirements for the processor. Refer to Table 5 for voltage regulation and electrical specifications. 4. TCaseOffset is the worst-case difference between the maximum case temperature and the thermal diode temperature on the processor’s core. For more information refer to the document, Intel® Pentium® III Processor in the FC-PGA2 Package Thermal Design Guide. 5. This processor exists in both FC-PGA and FC-PGA2 packages. Figure 17 is a block diagram of the Intel Celeron FC-PGA/FC-PGA2 processor die layout. The layout differentiates the processor core from the cache die area. In effect, the thermal design power identified in Table 40 is dissipated entirely from the processor core area. Thermal solution designs should compensate for this smaller heat flux area and not assume that the power is uniformly distributed across the entire die area. Figure 17. Processor Functional Die Layout (CPUID 0686h)(1) 0.337” 0.275” Die Area = 0.90 cm2 Cache Area = 0.26 cm2 Core Area = 0.64 cm2 0.146” 0.414” Cache Area 0.04 in2 Core Area 0.10 in2 Die Area 0.14 in2 1. For CPUID 0x68A, the die area is 0.94 cm2, the cache area is 0.30 cm2, and the core area is 0.64 cm2. Figure 18. Processor Functional Die Layout (up to CPUID 0683h) 0.362” 0.292” Die Area = 1.05 cm2 Cache Area = 0.32 cm2 Core Area = 0.73 cm2 0.170” 0.448” Cache Area 0.05 in2 Core Area 0.11 in2 Die Area 0.16 in2 Datasheet 67 Intel® Celeron® Processor up to 1.10 GHz 4.1.1 Thermal Diode The Celeron processor incorporates an on-die diode that can be used to monitor the die temperature. A thermal sensor located on the motherboard or a standalone measurement kit may monitor the die temperature of the Intel Celeron processor for thermal management purposes. Table 42 to Table 44 provide the diode parameter and interface specifications. Note: The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, ondie temperature gradients between the location of the thermal diode and the hottest location on the die at a given point in time, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the Tjunction temperature can change. Table 42. Thermal Diode Parameters (S.E.P. and PPGA Packages) Symbol Min Typ Max Unit Notes Iforward bias n_ideality 5 1.0000 1.0065 500 1.0173 uA 1 2,3 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. At room temperature with a forward bias of 630 mV. 3. n_ideality is the diode ideality factor parameter, as represented by the diode equation: I-Io(e (Vd*q)/(nkT) – 1). 4. Not 100% tested. Specified by design characterization. Table 43. Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages) Symbol Min Typ Max Unit Notes Iforward bias n_ideality 5 1.0057 1.0080 300 1.0125 uA 1 2, 3 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized at 100° C with a forward bias current of 5–300 µA. 3. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: Ifw=Is(e^ ((Vd*q)/(nkT)) – 1), where Is = saturation current, q = electronic charge, Vd = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 4. Not 100% tested. Specified by design characterization. Table 44. Thermal Diode Interface Pin Name SC242 Connector Signal # 370-Pin Socket Pin # Pin Description THERMDP THERMDN B14 B15 AL31 AL29 diode anode (p junction) diode cathode (n junction) 68 Datasheet Intel® Celeron® Processor up to 1.10 GHz 5.0 Mechanical Specifications There are three package technologies which Celeron processors use. They are the S.E.P. Package, the PPGA package, and the FC-PGA/FC-PGA2 packages. The S.E.P. Package and FC-PGA/ FC-PGA2 packages contain the processor core and passive components, while the PPGA package does not have passive components. The processor edge connector defined in this document is referred to as the “SC242 connector.” See the SC242 Design Guidelines (Order Number 243397) for further details on the edge connector. The processor socket connector is defined in this document is referred to as the “370-pin socket.” See the 370-Pin Socket (PGA370) Design Guidelines (Order Number 244410) for further details on the socket. 5.1 S.E.P. Package This section defines the mechanical specifications and signal definitions for the Celeron processor in the S.E.P. Package. 5.1.1 Materials Information The Celeron processor requires a retention mechanism. This retention mechanism may require motherboard holes to be 0.159" diameter if low cost plastic fasteners are used to secure the retention mechanisms. The larger diameter holes are necessary to provide a robust structural design that can shock and vibe testing. If captive nuts are used in place of the plastic fasteners, then either the 0.159" or the 0.140" diameter holes will suffice as long as the attach mount is used. Figure 19 with substrate dimensions is provided to aid in the design of a heatsink and clip. In Figure 20 all area on the secondary side of the substrate is zoned “keepout”, except for 25 mils around the tooling holes and the top and side edges of the substrate. Datasheet 69 Intel® Celeron® Processor up to 1.10 GHz Figure 19. Processor Substrate Dimensions (S.E.P. Package) -Y+.007 .062 -.005 -Z- 2.608 27.4 mm SR Opening Square 25.4 mm Copper Slug Square 1.660 1.370 -Y.615 .323 .814 3.804 -Y1.196 Figure 20. Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package) .025 Typ Max. Non-Keepout Area Secondary Side .025 Typ Max. Non-Keepout Area -D- There Will be No Components on Secodonary Side -G-E-H- .025 Typ Max. Non-Keepout Area Primary Side .025 Typ Max. Non-Keepout Are -D-G-H-E- 5.1.2 Signal Listing (S.E.P. Package) Table 45 and Table 46 provide the processor edge finger and SC242 connector signal definitions for Celeron processor. The signal locations on the SC242 edge connector are to be used for signal routing, simulation, and component placement on the motherboard. 70 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 VTT VSS VTT IERR# A20M# VSS FERR# IGNNE# TDI VSS TDO PWRGOOD TESTHI VSS THERMTRIP# Reserved LINT0/INTR VSS PICD0 PREQ# BP3# VSS BPM0# Reserved Reserved VSS Reserved Reserved Reserved VSS Reserved D61# D55# VSS Power/Other Power/Other Power/Other CMOS Output CMOS Input Power/Other CMOS Output CMOS Input TAP Input Power/Other TAP Output CMOS Input CMOS Test Input Power/Other CMOS Output Reserved for Future Use CMOS Input Power/Other APIC I/O CMOS Input AGTL+ I/O Power/Other AGTL+ I/O Reserved for Pentium II processor Reserved for Pentium II processor Power/Other Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Power/Other Reserved for Pentium II processor AGTL+ I/O AGTL+ I/O Power/Other A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 D60# D53# D57# VSS D46# D49# D51# VSS D42# D45# D39# VSS Reserved D43# D37# VSS D33# D35# D31# VSS D30# D27# D24# VSS D23# D21# D16# VSS D13# D11# D10# VSS D14# D9# D8# VSS D5# AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other Reserved for Future Use AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O Datasheet 71 Intel® Celeron® Processor up to 1.10 GHz Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 D3# D1# VSS BCLK Reserved Reserved VSS Reserved Reserved A30# VSS A31# A27# A22# VSS A23# Reserved A19# VSS A18# A16# A13# VSS A14# A10# A5# VSS A9# A4# BNR# VSS BPRI# TRDY# DEFER# VSS AGTL+ I/O AGTL+ I/O Power/Other System Bus Clock Input Reserved for Pentium II processor Reserved for Pentium II processor Power/Other Reserved for Pentium II processor Reserved for Pentium II processor AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O Reserved for Future Use AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ Input AGTL+ Input AGTL+ Input Power/Other A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 REQ2# REQ3# HITM# VSS DBSY# RS1# Reserved VSS ADS# Reserved Reserved VSS VID2 VID1 VID4 EMI FLUSH# SMI# INIT# VTT STPCLK# TCK SLP# VTT TMS VCCCORE THERMDP THERMDN LINT1/NMI VCCCORE PICCLK BP2# Reserved BSEL PICD1 PRDY# BPM1# AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ Input Reserved for Future Use Power/Other AGTL+ I/O Reserved for Future Use Reserved for Pentium II processor Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Input CMOS Input CMOS Input Power/Other CMOS Input TAP Input CMOS Input Power/Other TAP Input Power/Other Power/Other Power/Other CMOS Input Power/Other APIC Clock Input AGTL+ I/O Reserved for Future Use Power/Other APIC I/O AGTL+ Output AGTL+ I/O 72 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 VCCCORE Reserved Reserved Reserved VCCCORE D62# D58# D63# VCCCORE D56# D50# D54# VCCCORE D59# D48# D52# EMI D41# D47# D44# VCCCORE D36# D40# D34# VCCCORE D38# D32# D28# VCCCORE D29# D26# D25# VCCCORE D22# D19# D18# Power/Other Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 EMI D20# D17# D15# VCCCORE D12# D7# D6# VCCCORE D4# D2# D0# VCCCORE RESET# Reserved Reserved VCCCORE Reserved Reserved A29# EMI A26# A24# A28# VCCCORE A20# A21# A25# VCCCORE A15# A17# A11# VCCCORE A12# A8# A7# Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ Input Reserved for Future Use Reserved for Future Use Power/Other Reserved for Pentium II processor Reserved for Pentium II processor AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 Datasheet 73 Intel® Celeron® Processor up to 1.10 GHz Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B11 B110 B111 VCCCORE A3# A6# EMI SLOTOCC# REQ0# REQ1# REQ4# VCCCORE LOCK# DRDY# RS0# VCC5 TRST# HIT# RS2# Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other B112 B113 B114 B115 Reserved VCCL2 Reserved Reserved Reserved VCCL2 Reserved VID3 Reserved VID0 VCCL2 Reserved for Future Use Power/Other. Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Power/Other. Reserved for Pentium II processor Reserved for Pentium II processor Power/Other Reserved for Future Use Power/Other Power/Other. Reserved for Pentium II processor AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ Input Power/Other TAP Input AGTL+ I/O AGTL+ Input B119 B12 B120 B121 B117 B118 B116 74 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No. Signal Buffer Type Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No. Signal Buffer Type A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADS# BCLK BNR# BP2# BP3# BPM0# BPM1# B98 A100 A97 B99 B96 B95 A99 A96 B92 B94 A93 A95 B90 A92 B91 A91 A89 B86 A5 B87 A85 A87 B83 B88 B82 A84 B84 B80 A81 A83 A115 A75 A101 B19 A21 A23 B24 AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O CMOS Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O System Bus Clock Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O BPRI# BSEL D00# D1# D2# D3# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# A103 B21 B72 A73 B71 A72 A71 B68 B67 A69 A68 A65 A64 B66 A63 A67 B64 A61 B63 B60 B59 B62 A60 B58 A59 A57 B56 B55 A56 B52 B54 A55 A53 B51 A51 B48 A52 AGTL+ Input Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Datasheet 75 Intel® Celeron® Processor up to 1.10 GHz Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No. Signal Buffer Type Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No. Signal Buffer Type D36# D37# D38# D39# D4# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DRDY# EMI EMI EMI EMI EMI B46 A49 B50 A45 B70 B47 B42 A43 A48 B44 A44 A39 B43 B39 A40 B35 A41 B40 A36 B36 A33 B34 A37 B31 B38 A35 A32 B30 B32 A111 A105 B107 B1 B41 B61 B81 B100 AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other FERR# FLUSH# HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# PICCLK PICD0 PICD1 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved A7 B2 B110 A109 A4 A8 B4 A17 B16 B106 B18 A19 B22 B23 A20 A12 B102 B103 A107 A108 B104 A16 A47 A77 A88 A116 B12 A113 B20 B76 B112 B79 B114 B115 CMOS Output CMOS Input AGTL+ I/O AGTL+ I/O CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input AGTL+ I/O APIC Clock Input APIC I/O APIC I/O AGTL+ Output CMOS Input CMOS Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use Reserved for Pentium II processor Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor 76 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No. Signal Buffer Type Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No. Signal Buffer Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET# RS0# RS1# RS2# SLOTOCC# SLP# SMI# STPCLK# TCK TDI TDO A117 B116 A24 A76 B75 A79 A80 B78 B118 A25 A27 B26 A28 B27 A29 A31 B28 B74 B108 A112 B111 B101 B8 B3 B6 B7 A9 A11 Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Future Use Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor Reserved for Pentium II processor AGTL+ Input AGTL+ Input AGTL+ Input AGTL+ Input Power/Other CMOS Input CMOS Input CMOS Input TAP Input TAP Input TAP Output TESTHI THERMDN THERMDP THERMTRIP# TMS TRDY# TRST# VCC5 VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCL2 VCCL2 VCCL2 VID0 VID1 VID2 VID3 VID4 VSS A13 B15 B14 A15 B10 A104 B11 B109 B13 B17 B25 B29 B33 B37 B45 B49 B53 B57 B65 B69 B73 B77 B85 B89 B93 B97 B105 B113 B117 B121 B120 A120 A119 B119 A121 A114 CMOS Test Input Power/Other Power/Other CMOS Output TAP Input AGTL+ Input TAP Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other. Reserved for Pentium II processor Power/Other. Reserved for Pentium II processor Power/Other. Reserved for Pentium II processor Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 77 Intel® Celeron® Processor up to 1.10 GHz Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No. Signal Buffer Type Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No. Signal Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A118 A46 A38 A42 A50 A54 A58 A62 A66 A70 A74 A78 A82 A86 A2 A6 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT VTT VTT A10 A14 A18 A22 A26 A30 A34 A98 A102 A106 A110 A1 A3 B5 B9 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 78 Datasheet Intel® Celeron® Processor up to 1.10 GHz 5.2 PPGA Package This section defines the mechanical specifications and signal definitions for the Celeron processor in the PPGA packages. 5.2.1 PPGA Package Materials Information Figure 21 and Table 47 are provided to aid in the design of a heatsink and clip. Figure 21. Package Dimensions (PPGA Package) Bottom View D D1 S1 Heat Slug Top View Solder Resist D 45° x 0.085 B1 B2 Side View Seating Plane A1 L D2 A2 A e1 φB Datasheet 79 Intel® Celeron® Processor up to 1.10 GHz Table 47. Package Dimensions (PPGA Package) Millimeters Symbol Min Max Notes Min Inches Max Notes A A1 A2 B D D1 D2 e1 L N S1 1.83 1.00 2.72 0.40 49.43 45.59 25.15 2.29 3.05 370 1.52 2.23 0.072 0.039 0.088 3.33 0.51 49.63 45.85 25.65 2.79 3.30 Lead Count 2.54 0.107 0.016 1.946 1.795 0.099 0.090 0.120 370 0.060 0.131 0.020 1.954 1.805 1.010 0.110 0.130 Lead Count 0.100 Table 48. Information Summary (PPGA Package) Package Type Total Pins Pin Array Package Size Plastic Staggered Pin Grid Array (PPGA) 370 37 x 37 1.95" x 1.95" 4.95 cm x 4.95 cm 80 Datasheet Intel® Celeron® Processor up to 1.10 GHz 5.2.2 PPGA Package Signal Listing Figure 22. PPGA Package (Pin Side View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 AN AM AL AK AJ AH AG AF AE AD AC AB AA Z Y X W V U T S R Q P N D2# M VSS L D13# K J H G F E D C B A D7# VSS D21# D11# D20# VSS D24# VCC D3# D8# Rsvd D12# D4# A17# VSS VCC A21# VSS EDGCTRL VCC VSS Rsvd A19# Rsvd VSS A25# VCC A31# VSS A23# VREF5 VSS VSS VSS VSS VCC A12# VSS A15# A16# VCC A13# A3# VSS A5# A9# A6# Rsvd VSS VCC Rsvd A14# VSS Rsvd Rsvd VSS A7# BPRI# DEFER# VSS Rsvd Rsvd VSS Rsvd TRDY# VCC HIT# DRDY# BR0# ADS# VSS TRST# VSS TDI VID1 VID0 VSS SMI# VID3 VID2 TDO AN AM AL AK AJ AH AG AF AE AD AC Rsvd AB AA Z Y VSS X W V U Rsvd VSS Rsvd T S R Q Rsvd VSS Rsvd Rsvd P N M L K J H G Rsvd VSS BP3# F E D C B A VSS 37 VCC VCC VSS VCC VCC Rsvd A11# REQ4# Rsvd REQ3# HITM# DBSY# THRMDN THRMDP TCK Rsvd VSS TMS VCC A28# VCC VREF6 REQ0# LOCK# VSS Rsvd VREF7 VSS Rsvd PWRGD RS2# VCC VSS VCC VCC A8# VSS A4# VCC VCC VCC BSEL# VCC INIT# VSS VSS A10# BNR# REQ1# REQ2# RS1# VCC RS0# THERMTRIP# SLP# VCC STPCLK# IGNNE# VCC VSS FLUSH# A22# VSS A20M# VCC VSS VSS Rsvd IERR# VSS V1.5 Rsvd A20# FERR# VCC Rsvd VCC A27# VSS Rsvd A24# VCC VCMOS VCC V2.5 VCC A30# A29# A26# A18# VSS Rsvd VCC VSS VSS VSS Rsvd D0# VSS RESET# VCC VCC Rsvd VSS Rsvd VCC Rsvd VSS BCLK VCC Rsvd Rsvd PLL1 VREF4 VCC PLL2 D6# VSS D15# VCC D5# D1# VSS VCC D17# VSS D9# VCC VREF3 VCC Rsvd VCC Rsvd VSS Rsvd D10# D18# D14# VCC VSS VCC Rsvd VCC VSS LINT0 PICD1 LINT1 Rsvd VCC VCC VREF2 VSS PREQ# D30# VCC D19# PICCLK VCC PICD0 D16# D23# VCC VSS VSS Rsvd VCC VCC BP2# D22# Rsvd D27# VSS VCC VCC D42# D45# VCC D44# 10 11 12 VSS D41# D63# VSS VREF1 VSS VSS D59# VSS VCC VSS Rsvd VCC VSS Rsvd VSS Rsvd VCC Rsvd 28 29 30 VSS Rsvd 31 32 VCC VSS VCC D26# VSS D33# D35# VCC D32# VCC VCC VSS D25# VSS VCC D39# VCC VCOREDET VCC VSS D54# D62# VSS Rsvd VCC Rsvd VREF0 VCC BPM1# D38# D52# D40# VCC VSS VCC D31# VSS D28# 4 5 6 VCC D34# D36# D49# D55# VCC VSS D58# D50# VSS D56# Rsvd Rsvd BPM0# CPUPRES# Rsvd VSS D37# 8 9 VCC D51# 13 VSS D48# 16 17 VCC D46# D53# 22 23 VCC VSS VCC Rsvd 33 D29# 1 2 3 D43# 7 D47# 14 15 D57# 18 19 20 D60# 24 25 26 D61# 27 PRDY# 34 35 36 21 Datasheet 81 Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 AA1 AA3 AA5 AA33 AA35 AA37 AB2 AB4 AB6 AB32 AB34 AB36 AC1 AC3 AC5 AC33 AC35 AC37 AD2 D29# D28# D43# D37# D44# D51# D47# D48# D57# D46# D53# D60# D61# Reserved Reserved Reserved PRDY# VSS A27# A30# VCCCORE Reserved Reserved VCCCORE VCCCORE A24# A23# VSS VCCCORE VCCCMOS Reserved A20# VSS VSS FERR# Reserved VSS AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use Reserved for Future Use AGTL+ Output Power/Other AGTL+ I/O AGTL+ I/O Power/Other Reserved for Future Use Reserved for Future Use Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other Reserved for Future Use AGTL+ I/O Power/Other Power/Other CMOS Output Reserved for Future Use Power/Other AD4 AD6 AD32 AD34 AD36 AE1 AE3 AE5 AE33 AE35 AE37 AF2 AF4 AF6 AF32 AF34 AF36 AG1 AG3 AG5 AG33 AG35 AG37 AH2 AH4 AH6 AH8 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 A31# VREF5 VCCCORE VSS VCC1.5 A17# A22# VCCCORE A20M# IERR# FLUSH# VCCCORE Reserved A25# VSS VCCCORE VSS EDGCTRL A19# VSS INIT# STPCLK# IGNNE# VSS Reserved A10# A5# A8# A4# BNR# REQ1# REQ2# Reserved RS1# VCCCORE RS0# THERMTRIP# SLP# AGTL+ I/O Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other CMOS Input CMOS Output CMOS Input Power/Other Reserved for Future Use AGTL+ I/O Power/Other Power/Other Power/Other Power/Other AGTL+ I/O Power/Other CMOS Input CMOS Input CMOS Input Power/Other Reserved for Future Use AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use AGTL+ Input Power/Other AGTL+ Input CMOS Output CMOS Input 82 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type AH32 AH34 AH36 AJ01 AJ03 AJ05 AJ07 AJ09 AJ11 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AK02 AK04 AK06 AK08 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 VCCCORE VSS VCCCORE A21# VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS BSEL SMI# VID3 VCCCORE VSS A28# A3# A11# VREF6 A14# Reserved REQ0# LOCK# VREF7 Reserved PWRGOOD RS2# Reserved TMS Power/Other Power/Other Power/Other AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Input Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O Reserved for Future Use AGTL+ I/O AGTL+ I/O Power/Other Reserved for Future Use CMOS Input AGTL+ Input Reserved for Future Use TAP Input AK34 AK36 AL01 AL03 AL05 AL07 AL09 AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM04 AM06 AM08 AM10 AM12 AM14 AM16 AM18 AM2 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 VCCCORE VSS VSS VSS A15# A13# A9# Reserved Reserved A7# REQ4# REQ3# Reserved HITM# HIT# DBSY# THERMDN THERMDP TCK VID0 VID2 VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other Power/Other TAP Input Voltage Identification Voltage Identification Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 83 Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type AM36 AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 C1 VID1 VSS A12# A16# A6# Reserved Reserved Reserved BPRI# DEFER# Reserved Reserved TRDY# DRDY# BR0# ADS# TRST# TDI TDO D35# VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE Reserved D33# Voltage Identification Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use Reserved for Future Use AGTL+ Input AGTL+ Input Reserved for Future Use Reserved for Future Use AGTL+ Input AGTL+ I/O AGTL+ I/O AGTL+ I/O TAP Input TAP Input TAP Output AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved for Future Use AGTL+ I/O C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 E1 E3 VCCCORE D31# D34# D36# D45# D49# D40# D59# D55# D54# D58# D50# D56# Reserved Reserved Reserved BPM0# CPUPRES# VSS VSS VCCCORE D38# D39# D42# D41# D52# VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE D26# D25# Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use Reserved for Future Use AGTL+ I/O Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O 84 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type E5 E7 E9 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E31 E33 E35 E37 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 F32 F34 F36 G1 G3 G5 VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCOREDET Reserved D62# Reserved Reserved Reserved VREF0 BPM1# BP3# VCCCORE VCCCORE D32# D22# Reserved D27# VCCCORE D63# VREF1 VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS D21# D23# VSS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved for Future Use Power/Other Reserved for Future Use Reserved for Future Use Reserved for Future Use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other AGTL+ I/O AGTL+ I/O Reserved for Future Use AGTL+ I/O Power/Other AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other G33 G35 G37 H2 H4 H6 H32 H34 H36 J1 J3 J5 J33 J35 J37 K2 K4 K6 K32 K34 K36 L1 L3 L5 L33 L35 L37 M2 M4 M6 M32 M34 M36 N1 N3 N5 N33 N35 BP2# Reserved Reserved VSS D16# D19# VCCCORE VSS VCCCORE D7# D30# VCCCORE PICCLK PICD0 PREQ# VCCCORE VREF2 D24# VCCCORE VCCCORE VSS D13# D20# VSS Reserved PICD1 LINT1/NMI VSS D11# D3# VCCCORE VSS LINT0/INTR D2# D14# VCCCORE Reserved Reserved AGTL+ I/O Reserved for Future Use Reserved for Future Use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other APIC Clock Input APIC I/O CMOS Input Power/Other Power/Other AGTL+ I/O Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Reserved for Future Use APIC I/O CMOS Input Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other CMOS Input AGTL+ I/O AGTL+ I/O Power/Other Reserved for Future Use Reserved for Future Use Datasheet 85 Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type N37 P2 P4 P6 P32 P34 P36 Q1 Q3 Q5 Q33 Q35 Q37 R2 R4 R6 R32 R34 R36 S1 S3 S5 S33 S35 S37 T2 T4 T6 T32 T34 T36 U1 U3 Reserved VCCCORE D18# D9# VSS VCCCORE VSS D12# D10# VSS Reserved Reserved Reserved Reserved D17# VREF3 VCCCORE VSS VCCCORE D8# D5# VCCCORE Reserved Reserved Reserved VCCCORE D1# D6# VSS VCCCORE VSS D4# D15# Reserved for Future Use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use AGTL+ I/O Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Reserved for Future Use Reserved for Future Use Reserved for Future Use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O U5 U33 U35 U37 V2 V4 V6 V32 V34 V36 W1 W3 W5 W33 W35 W37 X2 X4 X6 X32 X34 X36 Y1 Y3 Y5 Y33 Y35 Y37 Z2 Z4 Z6 Z32 Z34 Z36 VSS PLL2 Reserved Reserved VSS Reserved VREF4 VCCCORE VSS VCCCORE D0# Reserved VCCCORE PLL1 Reserved BCLK Reserved RESET# Reserved VSS VCCCORE VSS Reserved A26# VSS VSS VCCCORE VSS VSS A29# A18# VCCCORE VSS VCC2.5 Power/Other Power/Other Reserved for Future Use Reserved for Future Use Power/Other Reserved for Future Use Power/Other Power/Other Power/Other Power/Other AGTL+ I/O Reserved for Future Use Power/Other Power/Other Reserved for Future Use System Bus Clock Input Reserved for Future Use AGTL+ Input Reserved for Future Use Power/Other Power/Other Power/Other Reserved for Future Use AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other 86 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A20M# ADS# BCLK BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BSEL AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 AE33 AN31 W37 AH14 G33 E37 C35 E35 AN17 AN29 AJ33 AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O CMOS Input AGTL+ I/O System Bus Clock Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O Power/Other CPUPRES# D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# C37 W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 C9 A9 D8 Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Datasheet 87 Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DRDY# EDGCTRL FERR# FLUSH# HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# PICCLK D10 C15 D14 D12 A7 A11 C11 A21 A15 A17 C13 C25 A13 D16 A23 C21 C19 C27 A19 C23 C17 A25 A27 E25 F16 AL27 AN19 AN27 AG1 AC35 AE37 AL25 AL23 AE35 AG37 AG33 M36 L37 AK20 J33 AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O Power/Other CMOS Output CMOS Input AGTL+ I/O AGTL+ I/O CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input AGTL+ I/O APIC Clock Input PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved J35 L35 W33 U33 A35 J37 AK26 AK18 AH16 AH18 AL19 AL17 AC1 AC37 AF4 AK16 AK24 AK30 AL11 AL13 AL21 AN11 AN13 AN15 AN21 AN23 B36 C29 C31 C33 E23 E29 E31 F10 G35 G37 L33 N33 N35 N37 APIC I/O APIC I/O Power/Other Power/Other AGTL+ Output CMOS Input CMOS Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use 88 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET# RS0# RS1# RS2# SLP# SMI# STPCLK# TCK TDI TDO THERMDN THERMDP THERMTRIP# TMS TRDY# TRST# VCC1.5 Q33 Q35 Q37 S33 S37 U35 U37 V4 W3 W35 AH20 AH4 A29 A31 A33 AA33 AA35 X6 Y1 E27 R2 S35 X2 X4 AH26 AH22 AK28 AH30 AJ35 AG35 AL33 AN35 AN37 AL29 AL31 AH28 AK32 AN25 AN33 AD36 Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use AGTL+ Input AGTL+ Input AGTL+ Input AGTL+ Input CMOS Input CMOS Input CMOS Input TAP Input TAP Input TAP Output Power/Other Power/Other CMOS Output TAP Input AGTL+ Input TAP Input Power/Other VCC2.5 VCCCMOS VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE Z36 AB36 AJ25 AJ29 AJ5 AJ9 AK2 AK34 AM12 AM16 AM20 AM24 AM28 AM32 AM4 AM8 B10 B14 B18 B22 B26 B30 B34 B6 C3 D20 D24 D28 D32 D36 D6 E13 E17 E5 E9 F14 F2 F22 F26 AA37 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 89 Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCOREDET VID0 VID1 AA5 AB2 AB34 AD32 AE5 AF2 AF34 AH24 AH32 AH36 AJ13 AJ17 AJ21 F30 F34 F4 H32 H36 J5 K2 K32 K34 M32 N5 P2 P34 R32 R36 S5 T2 T34 V32 V36 W5 X34 Y35 Z32 E21 AL35 AM36 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VID2 VID3 VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AL37 AJ37 E33 F18 K4 R6 V6 AD6 AK12 AK22 B16 B20 B24 B28 B32 B4 B8 D18 D2 D22 D26 D30 D34 D4 E11 E15 E19 E7 F20 F24 F28 F32 F36 G5 H2 H34 K36 L5 M2 M34 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 90 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P32 P36 Q5 R34 T32 T36 U5 V2 A37 AB32 AC33 AC5 AD2 AD34 AF32 AF36 AG5 AH2 AH34 AJ11 AJ15 AJ19 AJ23 AJ27 AJ3 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AJ7 AK36 AK4 AL1 AL3 AM10 AM14 AM18 AM2 AM22 AM26 AM30 AM34 AM6 AN3 B12 V34 X32 X36 Y37 Y5 Z2 Z34 AJ31 Y33 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 91 Intel® Celeron® Processor up to 1.10 GHz 5.3 FC-PGA/FC-PGA2 Packages This section defines the mechanical specifications and signal definitions for the Intel Celeron processor in the FC-PGA and FC-PGA2 packages. 5.3.1 FC-PGA Mechanical Specifications Figure 23 is provided to aid in the design of heatsink and clip solutions as well as demonstrate where pin-side capacitors will be located on the processor. Table 51 provides the measurements for these dimensions in both inches and millimeters. Figure 23. Package Dimensions (FC-PGA Package) NOTES: 1. Unless otherwise specified, the following drawings are dimensioned in inches. 2. All dimensions provided with tolerances are guaranteed to be met for all normal production product. 3. Figures and drawings labeled as “Reference Dimensions” are provided for informational purposes only. Reference dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. Reference dimensions are NOT checked as part of the processor manufacturing. Unless noted as such, dimensions in parentheses without tolerances are reference dimensions. 4. Drawing not to scale. 92 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 51. Package Dimensions (FC-PGA Package) Millimeters Symbol Min Max Notes Min Inches Max Notes A1 A2 B1 B2 C1 C2 D D1 G1 G2 G3 H L ϕP Pin TP 0.787 1.000 11.183 9.225 0.889 1.200 11.285 9.327 0.031 0.039 0.440 0.363 0.035 0.047 0.445 0.368 23.495 max 21.590 max 49.428 45.466 0.000 0.000 0.000 2.540 3.048 0.431 3.302 0.483 49.632 45.947 17.780 17.780 0.889 1 1 1 Nominal 0.925 max 0.850 max 1.946 1.790 0.000 0.000 0.000 0.100 0.120 0.017 0.130 0.019 1.954 1.810 0.700 0.700 0.035 Nominal 0.508 Diametric True Position (Pin-to-Pin) 0.020 Diametric True Position (Pin-to-Pin) NOTES: 1. Capacitors and resistors may be placed on the pin-side of the FC-PGA package in the area defined by G1, G2, and G3. This area is a keepout zone for motherboard designers. The bare processor die has mechanical load limits that should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach solution must not induce permanent stress into the processor substrate with the exception of a uniform load to maintain the heatsink to the processor thermal interface. The package dynamic and static loading parameters are listed in Table 52. For Table 52, the following apply: 1. It is not recommended to use any portion of the processor substrate as a mechanical reference or load bearing surface for thermal solutions. 2. Parameters assume uniformly applied loads Table 52. Processor Die Loading Parameters (FC-PGA Package) Parameter Dynamic (max)1 Static (max)2 Unit Silicon Die Surface Silicon Die Edge 200 100 50 12 lbf lbf NOTES: 1. This specification applies to a uniform and a non-uniform load. 2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface. Datasheet 93 Intel® Celeron® Processor up to 1.10 GHz 5.3.2 Mechanical Specifications (FC-PGA2 Package) Figure 24 is provided to aid in the design of heatsink and clip solutions as well as demonstrate where pin-side capacitors will be located on the processor. Table 53 lists the measurements for these dimensions in both inches and millimeters. Figure 24. Package Dimensions (FC-PGA2 Package) 94 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 53. Package Dimensions (FC-PGA2 Package) Millimeters Symbol Minimum Maximum Notes Minimum Maximum Notes Inches A1 A2 B1 B2 C1 C2 D D1 G1 G2 G3 H L ΦP Pin TP 2.266 0.980 30.800 30.800 2.690 1.180 31.200 31.200 0.089 0.038 1.212 1.212 1.299 max 1.299 max 1.946 1.790 0.000 0.000 0.000 Nominal 0.100 0.120 0.017 0.106 0.047 1.229 1.229 33.000 max 33.000 max 49.428 45.466 0.000 0.000 0.000 2.540 3.048 0.431 3.302 0.483 49.632 45.974 17.780 17.780 0.889 1.954 1.810 0.700 0.700 0.035 Nominal 0.130 0.019 0.508 Diametric True Position (Pin-to-Pin) 0.020 Diametric True Position (Pin-to-Pin) NOTE: Capacitors will be placed on the pin-side of the FC-PGA2 package in the area defined by G1, G2, and G3. This area is a keepout zone for motherboard designers. For Table 52, the following apply: 1. It is not recommended to use any portion of the processor substrate as a mechanical reference or load bearing surface for thermal solutions. 2. Parameters assume uniformly applied loads. Table 54. Processor Case Loading Parameters (FC-PGA2 Package) Parameter Dynamic (max)1 Static (max)2,3 Unit IHS Surface IHS Edge IHS Corner 200 125 75 100 N/A N/A lbf lbf ibf NOTES: 1. This specification applies to a uniform and a non-uniform load. 2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface. 3. See socket manufacturer’s force loading specification also to ensure compliance. Maximum static loading listed here does not account for the maximum reaction forces on the socket tabs or pins. Datasheet 95 Intel® Celeron® Processor up to 1.10 GHz 5.3.2.1 Recommended Mechanical Keep-Out Zones (FC-PGA2 Package) Figure 25. Volumetric Keep-Out Figure 26. Component Keep-Out 96 Datasheet Intel® Celeron® Processor up to 1.10 GHz 5.3.3 FC-PGA/FC-PGA2 Package Signal List Figure 27. Package Dimensions (FC-PGA/FC-PGA2 Packages) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 AN VSS AM AL VSS AK VCC AJ A21 AH VSS AG AF AE A17 AD VSS AC RSV AB VCC AA Z Y RSV X RSV W D0 V VSS U D4 T VCC S D8 R RSV Q D12 P VCC N D2 M VSS L D13 K VCC J D7 H VSS G D21 F VCC E D26 D VSS C D33 B D35 A D29 D28 D43 D37 D44 D51 D47 D48 D57 D46 D53 D60 D61 RSV RSV RSV PRDY VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC D31 D34 D36 D45 D49 D40 D59 D55 D54 D58 D50 D56 RSV RSV RSV BPM0 CPUPRES EDGCTRL AN A12 VCC VSS A15 VSS VSS RSV A19 VSS RSV A22 A31 A20 A24 A30 VSS A26 A29 VSS RSV VCC A18 VSS A23 VCC VREF5 A25 VCC A10 A28 VSS A5 A16 VSS A13 A3 VCC A9 A11 VCC A8 A6 VSS RSV RSV VCC RSV A14 VCC A4 BNR RSV VSS A7 RSV BPRI DEFER VSS VCC RSV RSV VSS RSV TRDY DRDY VCC BR0 VSS ADS TRST VCC VSS TCK TDI VID1 VID0 VCC SMI VCC AG INIT VSS STPCLK VCC A20M VCC VSS VSS RSV VCC RSV VSS PLL1 VREF4 VSS D1 D5 D17 D10 D18 D14 D11 D20 VSS D24 VCC PICCLK D19 VSS VCC D25 VSS VCC VCC D32 VSS D38 D22 RSV VCC D39 VSS D42 D27 VCC VCC D41 VSS D63 VREF1 VSS VSS VSS RSV VCC VSS VCC VSS RSV VCC D62 VSS VCC VSS RSV VSS VCC VCC BP2 VSS VCC D3 VSS D9 VCC VREF3 D6 VSS VCC VCC RSV VSS RSV VCC VSS S RSV VCC RSV VSS RSV VCC RSV VSS VSS RSV VCC VSS N RSV LINT0 L PICD1 VCC VSS J D30 D16 VCC PICD0 VSS RSV VCC VSS E BPM1 VSS VCC C B A RSV BP3 D VCC PREQ H VCC G D23 RSV F VCC D52 SLEW CTRL RTT CTRL TDO AM AL VID2 AK VSS AJ VID3 AH RSV VCC VCC HITM RSV VSS VCC HIT VSS DBSY PWRGD VCC RS0 VSS REQ4 RSV REQ3 LOCK VSS THRMDN RS2 VCC THRMDP RSV BSEL1 VREF6 VSS REQ0 VCC VREF7 VCC TMS VSS BSEL0 VCC VSS REQ1 REQ2 RSV RS1 THERM TRIP SLP IGNNE AF AE VCC VSS FLUSH AD AC IERR V_1.5 VSS FERR VCC RSV RSV AB V_CMOS AA VCC V_2.5 Y VSS VSS W BCLK V X Z A27 RESET RSV RSV D15 VCC PIN SIDE VIEW VCC PLL2 VSS VCC U RSV T RSV R Q RSV P RSV M VCC LINT1 K VREF2 RSV VREF0 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Table 55 and Table 56 provide the processor pin definitions. The signal locations on the PGA370 socket are to be used for signal routing, simulation, and component placement on the baseboard. Figure 27 provides a pin-side view of the Intel Celeron FC-PGA/FC-PGA2 processor pin-out. Datasheet 97 Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A20M# ADS# BCLK BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 AE33 AN31 W37 AH14 G33 E37 C35 E35 AN17 AN29 AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O CMOS Input AGTL+ I/O System Bus Clock AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O BSEL0 BSEL15 CPUPRES# D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# AJ33 AJ31 C37 W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 CMOS I/O Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O 98 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DRDY# EDGCTRL 2,8 FERR# FLUSH# GND GND GND GND GND C9 A9 D8 D10 C15 D14 D12 A7 A11 C11 A21 A15 A17 C13 C25 A13 D16 A23 C21 C19 C27 A19 C23 C17 A25 A27 E25 F16 AL27 AN19 AN27 AG1 AC35 AE37 A37 AB32 AC5 AC33 AD2 AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O Power/Other CMOS Output CMOS Input Power/Other Power/Other Power/Other Power/Other Power/Other GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AD34 AF32 AF36 AG5 AH2 AH34 AJ3 AJ7 AJ11 AJ15 AJ19 AJ23 AJ27 AK4 AK36 AL1 AL3 AM6 AM10 AM14 AM18 AM22 AM26 AM30 AM34 AN3 B4 B8 B12 B16 B20 B24 B28 B32 D2 D4 D18 D22 D26 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 99 Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Reserved GND GND GND GND GND HIT# HITM# IERR# IGNNE# INIT# D30 D34 E7 E11 E15 E19 F20 F24 F28 F32 F36 G5 H2 H34 K36 L5 M2 M34 P32 P36 Q5 R34 T32 T36 U5 V2 V34 X32 X34 X36 Y5 Y37 Z2 Z34 AL25 AL23 AE35 AG37 AG33 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved for future use Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O CMOS Output CMOS Input CMOS Input LINT0/INTR LINT1/NMI LOCK# PICCLK PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved M36 L37 AK20 J33 J35 L35 W33 U33 A35 J37 AK26 AK18 AH16 AH18 AL19 AL17 A29 A31 A33 AC1 AC37 AF4 AH20 AK16 AK24 AK30 AL11 AL13 AL21 AN11 AN13 AN15 AN21 AN23 B36 C29 C31 C33 E23 CMOS Input CMOS Input AGTL+ I/O APIC Clock Input APIC I/O APIC I/O Power/Other Power/Other AGTL+ Output CMOS Input CMOS Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use 100 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3 E29 E31 F10 G35 G37 L33 N33 N35 N37 Q33 Q35 Q37 R2 S33 S37 U35 U37 V4 W3 W35 X6 X20 Y1 AA33 AA35 AM2 Y33 AH4 X4 AH26 AH22 AK28 S35 E27 AH30 AJ35 AG35 AL33 AN35 Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Power/Other Power/Other AGTL+ Input AGTL+ Input AGTL+ Input Power/Other Power/Other CMOS Input CMOS Input CMOS Input TAP Input TAP Input TDO THERMDN THERMDP THERMTRIP# TMS TRDY# TRST# VCC1.5 1 Vcc2.5 VCCCMOS VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE AN37 AL29 AL31 AH28 AK32 AN25 AN33 AD36 Z36 AB36 AA5 AA37 AB2 AB34 AD32 AE5 AF2 AF34 AH24 AH32 AH36 AJ5 AJ9 AJ13 AJ17 AJ21 AJ25 AJ29 AK2 AK34 AM4 AM8 AM12 AM16 AM20 AM24 AM28 AM32 B6 TAP Output Power/Other Power/Other CMOS Output TAP Input AGTL+ Input TAP Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved4 RESET# RESET# RS0# RS1# RS2# RTTCTRL SLEWCTRL SLP# SMI# STPCLK# TCK TDI 6 7 Datasheet 101 Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Pin Signal Group VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE B10 B14 B18 B22 B26 B30 B34 C3 D6 D20 D24 D28 D32 D36 E5 E9 E13 E17 F2 F4 F14 F22 F26 F30 F34 H32 H36 J5 K2 K32 K34 M32 N5 P2 P34 R32 R36 S5 T2 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCORE_DET VID0 VID1 VID2 VID3 VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7 T34 V32 V36 W5 X34 Y35 Z32 E21 AL35 AM36 AL37 AJ37 E33 F18 K4 R6 V6 AD6 AK12 AK22 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other NOTES: 1. VCC1.5 must be supplied by the same voltage source supplying VTT on the motherboard. 2. Previously this pin functioned as the EDGCTRL signal. 3. Previously, PGA370 designs defined this pin as a GND. For flexible PGA370 designs, it must be left unconnected (NC). 4. Previously, PGA370 designs defined this pin as a GND. 5. Intel Celeron processor in the FC-PGA/FC-PGA2 packages do not use this pin. 6. This pin is only reset for processors with a CPUID of 0686h. For previous Celeron processors prior to 0686h (not including 0686h) this pin is reserved. 7. This pin is reserved for Intel Celeron processors with a CPUID of 0686h. 8. For CPUID of 0681h, this is a VSS. For other 068xh processors, this pin is a No Connect (NC). 102 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 AA1 AA3 AA5 AA33 AA35 AA37 AB2 AB4 AB6 AB32 AB34 AB36 AC1 AC3 AC5 AC33 AC35 AC37 AD2 AD4 AD6 D29# D28# D43# D37# D44# D51# D47# D48# D57# D46# D53# D60# D61# Reserved Reserved Reserved PRDY# GND A27# A30# VCCCORE Reserved Reserved VCCCORE VCCCORE A24# A23# GND VCCCORE VCCCMOS Reserved A20# GND GND FERR# Reserved GND A31# VREF5 AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for future use Reserved for future use Reserved for future use AGTL+ Output Power/Other AGTL+ I/O AGTL+ I/O Power/Other Reserved for future use Reserved for future use Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other Reserved for future use AGTL+ I/O Power/Other Power/Other CMOS Output Reserved for future use Power/Other AGTL+ I/O Power/Other AD32 AD34 AD36 AE1 AE3 AE5 AE33 AE35 AE37 AF2 AF4 AF6 AF32 AF34 AF36 AG1 AG3 AG5 AG33 AG35 AG37 AH2 AH4 AH6 AH8 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AH32 AH34 AH36 VCCCORE GND VCC1.5 1 A17# A22# VCCCORE A20M# IERR# FLUSH# VCCCORE Reserved A25# GND VCCCORE GND EDGCTRL A19# GND INIT# STPCLK# IGNNE# GND RESET# A10# A5# A8# A4# BNR# REQ1# REQ2# Reserved RS1# VCCCORE RS0# THERMTRIP# SLP# VCCCORE GND VCCCORE 6 2,8 Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other CMOS Input CMOS Output CMOS Input Power/Other Reserved for future use AGTL+ I/O Power/Other Power/Other Power/Other Power/Other AGTL+ I/O Power/Other CMOS Input CMOS Input CMOS Input Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for future use AGTL+ Input Power/Other AGTL+ Input CMOS Output CMOS Input Power/Other Power/Other Power/Other Datasheet 103 Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group AJ1 AJ3 AJ5 AJ7 AJ9 AJ11 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AK2 AK4 AK6 AK8 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 AK34 AK36 AL1 AL3 A21# GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE BSEL1 BSEL0 SMI# VID3 VCCCORE GND A28# A3# A11# VREF6 A14# Reserved REQ0# LOCK# VREF7 Reserved PWRGOOD RS2# Reserved TMS VCCCORE GND GND GND 5 AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS I/O CMOS Input Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O Reserved for future use AGTL+ I/O AGTL+ I/O Power/Other Reserved for future use CMOS Input AGTL+ Input Reserved for future use TAP Input Power/Other Power/Other Power/Other Power/Other AL5 AL7 AL9 AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM2 AM4 AM6 AM8 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 AM36 AN3 AN5 AN7 AN9 A15# A13# A9# Reserved Reserved A7# REQ4# REQ3# Reserved HITM# HIT# DBSY# THERMDN THERMDP TCK VID0 VID2 Reserved VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VID1 GND A12# A16# A6# 3 AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for future use Reserved for future use AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for future use AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other Power/Other TAP Input Power/Other Power/Other Reserved for future use Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O 104 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 C1 C3 C5 C7 C9 C11 C13 Reserved Reserved Reserved BPRI# DEFER# Reserved Reserved TRDY# DRDY# BR0# ADS# TRST# TDI TDO D35# GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE Reserved D33# VCCCORE D31# D34# D36# D45# D49# Reserved for future use Reserved for future use Reserved for future use AGTL+ Input AGTL+ Input Reserved for future use Reserved for future use AGTL+ Input AGTL+ I/O AGTL+ I/O AGTL+ I/O TAP Input TAP Input TAP Output AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved for future use AGTL+ I/O Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 E1 E5 E7 E9 E11 E13 E15 E17 E19 D40# D59# D55# D54# D58# D50# D56# Reserved Reserved Reserved BPM0# CPUPRES# GND GND VCCCORE D38# D39# D42# D41# D52# GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE D26# VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for future use Reserved for future use Reserved for future use AGTL+ I/O Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 105 Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group E21 E23 E25 E27 E29 E3 E31 E33 E35 E37 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 F32 F34 F36 G1 G3 G5 G33 G35 G37 H2 H4 H6 H32 H34 VCORE_DET Reserved D62# SLEWCTRL Reserved D25# Reserved VREF0 BPM1# BP3# VCCCORE VCCCORE D32# D22# Reserved D27# VCCCORE D63# VREF1 GND VCCCORE GND VCCCORE GND VCCCORE GND VCCCORE GND D21# D23# GND BP2# Reserved Reserved GND D16# D19# VCCCORE GND Power/Other Reserved for future use AGTL+ I/O Power/Other Reserved for future use AGTL+ I/O Reserved for future use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other AGTL+ I/O AGTL+ I/O Reserved for future use AGTL+ I/O Power/Other AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other AGTL+ I/O Reserved for future use Reserved for future use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other H36 J1 J3 J5 J33 J35 J37 K2 K4 K6 K32 K34 K36 L1 L3 L5 L33 L35 L37 M2 M4 M6 M32 M34 M36 N1 N3 N5 N33 N35 N37 P2 P4 P6 P32 P34 P36 Q1 Q3 VCCCORE D7# D30# VCCCORE PICCLK PICD0 PREQ# VCCCORE VREF2 D24# VCCCORE VCCCORE GND D13# D20# GND Reserved PICD1 LINT1/NMI GND D11# D3# VCCCORE GND LINT0/INTR D2# D14# VCCCORE Reserved Reserved Reserved VCCCORE D18# D9# GND VCCCORE GND D12# D10# Power/Other AGTL+ I/O AGTL+ I/O Power/Other APIC Clock Input APIC I/O CMOS Input Power/Other Power/Other AGTL+ I/O Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Reserved for future use APIC I/O CMOS Input Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other CMOS Input AGTL+ I/O AGTL+ I/O Power/Other Reserved for future use Reserved for future use Reserved for future use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O 106 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group Q5 Q33 Q35 Q37 R2 R4 R6 R32 R34 R36 S1 S3 S5 S33 S35 S37 T2 T4 T6 T32 T34 T36 U1 U3 U5 U33 U35 U37 V2 V4 V6 V32 V34 V36 W1 W3 W5 W33 W35 GND Reserved Reserved Reserved Reserved D17# VREF3 VCCCORE GND VCCCORE D8# D5# VCCCORE Reserved RTTCTRL Reserved VCCCORE D1# D6# GND VCCCORE GND D4# D15# GND PLL2 Reserved Reserved GND Reserved VREF4 VCCCORE GND VCCCORE D0# Reserved VCCCORE PLL1 Reserved Power/Other Reserved for future use Reserved for future use Reserved for future use Reserved for future use AGTL+ I/O Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Reserved for future use Power/Other Reserved for future use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Reserved for future use Reserved for future use Power/Other Reserved for future use Power/Other Power/Other Power/Other Power/Other AGTL+ I/O Reserved for future use Power/Other Power/Other Reserved for future use W37 X4 X6 X20 X32 X34 X36 Y1 Y3 Y5 Y33 Y35 Y37 Z2 Z4 Z6 Z32 Z34 Z36 BCLK RESET#7 Reserved Reserved GND Reserved GND Reserved A26# GND Reserved4 VCCCORE GND GND A29# A18# VCCCORE GND Vcc2.5 System Bus Clock Power/Other Reserved for future use Reserved for future use Power/Other Reserved for future use Power/Other Reserved for future use AGTL+ I/O Power/Other Reserved for future use Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other NOTES: 1. VCC1.5 must be supplied by the same voltage source supplying VTT on the motherboard. 2. Previously this pin functioned as the EDGCTRL signal. 3. Previously, PGA370 designs defined this pin as a GND. For flexible PGA370 designs, it must be left unconnected (NC). 4. Previously, PGA370 designs defined this pin as a GND. 5. Celeron processor in the FC-PGA/FC-PGA2 packages does not make use of this pin. 6. This pin is only reset for processors with a CPUID of 0686h. For previous Celeron processors prior to 0686h (not including 0686h) this pin is reserved. 7. This pin is reserved for Celeron processors with a CPUID of 0686h. 8. For CPUID of 0681h, this is a VSS. For other 068xh processors, this pin is a No Connect (NC). Datasheet 107 Intel® Celeron® Processor up to 1.10 GHz 5.4 Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages) Figure 28 through Figure 30 show processor top-side markings; the markings aid in the identification of a Celeron processor for the PGA370 socket. Package dimension measurements are provided in Table 47 for the PPGA package, Table 51 for the FC-PGA package, and Table 53 for the FC-PGA2 package. Figure 28. Top Side Processor Markings (PPGA Package) Celeron logo Product Code Country of Origin Celeron ® RB80526RX566128 FFFFFFFF-0001 SSSSS M ALAY FPO # - S/N S-Spec# Figure 29. Top Side Processor Markings (FC-PGA Package) GRP1LINE1 GRP1LINE2 GRP1LN1: Intel (m )(c) '01__-__(Country Of Origin) GRP1LN2: (Core Freq)/(Cache)/(Bus Freq)/(Voltage) GRP2LINE1 GRP2LINE2 GRP2LN1: (FPO)-(S/N) GRP2LN2: Celeron (S-Spec) 2D M atrix M ark Figure 30. Top Side Processor Markings (FC-PGA2 Package) GRP1LN1 GRP1LN2 GRP1LN1: Intel (m )(c) '01__-__(Country Of Origin) GRP1LN2: (Core Freq)/(Cache)/(Bus Freq)/(Voltage) GRP2LN1 GRP2LN2 GRP2LN1: (FPO)-(S/N) GRP2LN2: Celeron (S-Spec) 108 Datasheet Intel® Celeron® Processor up to 1.10 GHz 5.5 Heatsink Volumetric Keepout Zone Guidelines When designing a system platform it is necessary to ensure sufficient space is left for a heatsink to be installed without mechanical interference. Due to the large number of proprietary heatsink designs, Intel cannot specify a keepout zone that covers all passive and active-fan heatsinks. It is the system designer’s responsibility to consider their own proprietary solution when designing the desired keepout zone in their system platform. Please refer to the Intel® Celeron® Processor (PPGA) at 466 MHz Thermal Solutions Guidelines (Order Number 245156) for further guidance. Note: The heatsink keepout zones found in Section 6.0, “Boxed Processor Specifications” on page 110 refer specifically to the Boxed Processor’s active-fan heatsink. This does not reflect the worst-case dimensions that may exist with other third party passive or active-fan heatsinks. Contact your vendor of choice for their passive or active-fan heatsink dimensions to ensure that mechanical interference with system platform components does not occur. Datasheet 109 Intel® Celeron® Processor up to 1.10 GHz 6.0 Boxed Processor Specifications The Celeron processor is also offered as an Intel boxed processor in the FC-PGA/FC-PGA2, PPGA, and S.E.P. Packages. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed Celeron processor in the S.E.P. Package is supplied with an attached fan heatsink. The boxed Celeron processors in FC-PGA/ FC-PGA2 and PPGA packages are supplied with unattached fan heatsinks. This section documents motherboard and system requirements for the fan heatsink that is supplied with the boxed Intel Celeron processor. This section is particularly important for OEMs that manufacture motherboards for system integrators. Unless otherwise noted, all figures in this section are dimensioned in inches. Note: Drawings in this section reflect only the specifications of the Intel boxed processor product. These dimensions should not be used as a generic keepout zone for all heatsinks. It is the system designer’s responsibility to consider their proprietary solution when designing to the required keepout zone on their system platform and chassis. Refer to the package specific Thermal / Mechanical Solution Functional Specifications for further guidance. Contact your local Intel Sales Representative for these documents. 6.1 Mechanical Specifications for the Boxed Intel® Celeron® Processor Mechanical Specifications for the S.E.P. Package This section documents the mechanical specifications of the boxed Celeron processor fan heatsink in the S.E.P. Package. The boxed processor in the S.E.P. Package ships with an attached fan heatsink. Figure 31 shows a mechanical representation of the boxed Intel Celeron processor in a S.E.P. Package in the retention mechanism, which is not shipped with the boxed Intel Celeron processor. The space requirements and dimensions for the boxed processor in the S.E.P. Package are shown in Figure 32 and Figure 33. Also, a conceptual attachment interface to low profile retention mechanism is shown in Figure 38. Note: The heatsink airflow keepout zones found in Table 57 and Figure 38 refer specifically to the boxed processor’s active fan heatsink. This does not reflect the worst-case dimensions that may exist with other third party passive or active fan heatsinks. 6.1.1 110 Datasheet Intel® Celeron® Processor up to 1.10 GHz Figure 31. Retention Mechanism for the Boxed Intel® Celeron® Processor in the S.E.P. Package Figure 32. Side View Space Requirements for the Boxed Processor in the S.E.P. Package 1.386 (A) S.E.P.P. Fan Heatsink 242-Contact Slot Connector 0.576 (B) Datasheet 111 Intel® Celeron® Processor up to 1.10 GHz Figure 33. Front View Space Requirements for the Boxed Processor in the S.E.P. Package 5.40 (E) 4.74 (D) 2.02 (C) Table 57. Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package Fig. Ref. Label Dimensions (Inches) Min Typ Max A B C D E F G Fan Heatsink Depth (see Figure 27) Fan Heatsink Height from Motherboard (see Figure 27) Fan Heatsink Height (see Figure 31) Fan Heatsink Width (see Figure 31) Fan Heatsink Base Width (see Figure 31) Airflow Keepout Zones from end of Fan Heatsink Airflow Keepout Zones from face of Fan Heatsink 0.4 0.2 5.4 0.58 1.40 2.00 4.80 6.1.1.1 Boxed Processor Heatsink Weight The heatsink for the boxed Intel Celeron processor in the S.E.P. Package will not weigh more than 225 grams. 6.1.1.2 Boxed Processor Retention Mechanism The boxed Intel Celeron processor requires a S.E.P. Package retention mechanism to secure the processor in the 242-contact slot connector. A S.E.P. Package retention mechanism are provided with the boxed processor. Motherboards designed for use by system integrators should include a retention mechanism and appropriate installation instructions. The boxed Intel Celeron processor does not require additional fan heatsink supports. Fan heatsink supports are not shipped with the boxed Intel Celeron processor. Motherboards designed for flexible use by system integrators must still recognize the boxed Pentium II processor’s fan heatsink clearance requirements, which are described in the Pentium® II Processor at 233, 266, 300, and 333 MHz Datasheet (Order Number 243335). 112 Datasheet Intel® Celeron® Processor up to 1.10 GHz 6.1.2 Mechanical Specifications for the PPGA Package This section documents the mechanical specifications for the fan heatsink of the boxed Celeron processor in the PPGA package. The boxed processor in the PPGA package ships with an unattached fan heatsink which has an integrated clip. Figure 34 shows a mechanical representation of the boxed Intel Celeron processor in the PPGA package. Note that the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The space requirements and dimensions for the boxed processor with an integrated fan heatsink are shown in Figure 35. All dimensions are in inches. Note: The heatsink airflow keepout zones found in Figure 39 refer specifically to the boxed processor’s active fan heatsink. This does not reflect the worst-case dimensions that may exist with other third party passive or active fan heatsinks. Figure 34. Boxed Intel® Celeron® Processor in the PPGA Package Figure 35. Side View Space Requirements for the Boxed Processor in the PPGA Package Datasheet 113 Intel® Celeron® Processor up to 1.10 GHz 6.1.2.1 Boxed Processor Heatsink Weight The heatsink for the boxed Intel Celeron processor in the PPGA package will not weigh more than 180 grams. 6.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages This section documents the mechanical specifications of the fan heatsink for the boxed Intel Celeron processor in the FC-PGA/FC-PGA2 (Flip-Chip Pin Grid Array) packages. The boxed processor in the FC-PGA/FC-PGA2 packages ships with a fan heatsink which has an integrated clip. Figure 36 shows a mechanical representation of the boxed Intel Celeron processor in the FC-PGA/FC-PGA2 packages. Figure 39 and Figure 41 show the REQUIRED keepout dimensions for the boxed processor thermal solution. The cooling fin orientation on the heatsink relative to the PGA-370 socket is subject to change. Contact your local Intel sales representative for documentation specific to the boxed fan heatsink orientation relative to the PGA-370 socket. The boxed processor fan heatsink is also asymmetrical in that the mechanical step feature (specified in Figure 37) must sit over the socket’s cam. The step allows the heatsink to securely interface with the processor in order to meet the processors thermal requirements. Figure 36. Conceptual Drawing of the Boxed Intel® Celeron® Processor in the 370-Pin Socket (FC-PGA/FC-PGA2 Packages) Figure 37. Dimensions of Mechanical Step Feature in Heatsink Base for the FC-PGA/ FC-PGA2 Packages 0.043 0.472 U nits = inches 114 Datasheet Intel® Celeron® Processor up to 1.10 GHz 6.1.3.1 Boxed Processor Heatsink Weight The heatsink for the boxed Intel Celeron processor in the FC-PGA/FC-PGA2 packages will not weigh more than 180 grams. 6.2 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processors. 6.2.1 6.2.1.1 Thermal Requirements for the Boxed Intel® Celeron® Processor Boxed Processor Cooling Requirements The boxed processor is directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is found in Section 4.0 of this document. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Section 4.0) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 38 and Figure 39 illustrate an acceptable airspace clearance for the fan heatsink. It is also recommended that the air temperature entering the fan be kept below 45 °C. Again, meeting the processor's temperature specification is the responsibility of the system integrator. The processor temperature specification is found in Section 4.0 of this document. Figure 38. Top View Airspace Requirements for the Boxed Processor in the S.E.P. Package Fan Heatsink Processor Airspace 0.20 Min Air Space (G) Measure ambient temperature 0.3" above center of fan inlet 0.40 Min Air Space (F) (both ends) Datasheet 115 Intel® Celeron® Processor up to 1.10 GHz Figure 39. Side View Airspace Requirements for the Boxed Intel® Celeron® Processor in the FC-PGA/FC-PGA2 and PPGA Packages Measure ambient temperature 0.3" above center of fan inlet 0.20 Min Air Space 0.20 Min Air Space Fan Heatsink Processor Figure 40. Volumetric Keepout Requirements for The Boxed Fan Heatsink 116 Datasheet Intel® Celeron® Processor up to 1.10 GHz 6.2.1.2 Boxed Processor Thermal Cooling Solution Clip The boxed processor thermal solution requires installation by a system integrator to secure the thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket. Motherboards designed for use by system integrators should take care to consider the implications of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket attach tabs. Motherboard components should not be placed too close to the 370-pin socket attach tabs in a way that interferes with the installation of the boxed processor thermal cooling solution (see Figure 41 for specifications). Figure 41. Clip Keepout Requirements for the 370-Pin (Top View) 6.3 Electrical Requirements for the Boxed Intel® Celeron® Processor Electrical Requirements The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable is shipped with the boxed processor to draw power from a power header on the motherboard. The power cable connector and pin-out are shown in Figure 42. Motherboards must provide a matched power header to support the boxed processor. Table 58 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal (an open-collector output) that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides VOH to match the motherboard-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. 6.3.1 Datasheet 117 Intel® Celeron® Processor up to 1.10 GHz The boxed Intel Celeron processors in the PPGA package at 500 MHz and below are shipped with an unattached fan heatsink with two wire power-supply cables. These two wire fans do NOT support the motherboard-mounted fan speed monitor feature. The Intel Celeron processor at 533 MHz and above ship with unattached fan heatsinks that have three power-supply cables. These three wire fans DO support the motherboard-mounted fan speed monitor feature. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the motherboard documentation or on the motherboard. Figure 43 shows the recommended location of the fan power connector relative to the 242-contact slot connector. Figure 44 shows the recommended location of the fan power connector relative to the 370-pin socket. For the S.E.P. Package, the motherboard power header should be positioned within 4.75 inches (lateral) of the fan power connector. The motherboard power header should be positioned within 4.00 inches (lateral) of the fan power connector for the PPGA and FC-PGA/FC-PGA2 packages. Figure 42. Boxed Processor Fan Heatsink Power Cable Connector Description Pin 1 2 3 Signal GND +12V SENSE Straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. Waldom*/Molex* P/N 22-01-3037 or equivalent. Match with straight pin, friction lock header on motherboard Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3, or equivalent. 1 2 3 Table 58. Fan Heatsink Power and Signal Specifications Description Min Typ Max +12V: 12 volt fan power supply IC: Fan current draw SENSE: SENSE frequency (motherboard should pull this pin up to appropriate Vcc with resistor) 10.2V 12V 13.8V 100 mA 2 pulses per fan revolution 118 Datasheet Intel® Celeron® Processor up to 1.10 GHz Figure 43. Motherboard Power Header Placement for the S.E.P. Package 242-Contact Slot Connector 1.428" Fan power connector location (1.56 inches above motherboard 1.449" r = 4.75" Motherboard fan power header should be positioned within 4.75 inches of the fan power connector (lateral distance). Figure 44. Motherboard Power Header Placement Relative to the 370-pin Socket R = 4.00" PGA370 ppga1.vsd Datasheet 119 Intel® Celeron® Processor up to 1.10 GHz 7.0 Processor Signal Description Table 59 provides an alphabetical listing of all Celeron processor signals. The tables at the end of this section summarize the signals by direction (output, input, and I/O). Note: Unless otherwise noted, the signals apply to S.E.P., PPGA, and FC-PGA/FC-PGA2 Packages. Table 59. Alphabetical Signal Reference (Sheet 1 of 7) Signal Type Description A[31:3]# I/O The A[31:3]# (Address) signals define a 232-byte physical memory address space. When ADS# is active, these pins transmit the address of a transaction; when ADS# is inactive, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Intel® Celeron® processor system bus. The A[31:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]# signals are parity-protected by the AP0# parity signal. On the active-to-inactive transition of RESET#, the processors sample the A[31:3]# pins to determine their power-on configuration. See the Pentium® II Processor Developer’s Manual (Order Number 243502) for details. If the A20M# (Address-20 Mask) input signal is asserted, the Intel Celeron processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction. The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction address on the A[31:3]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must connect the appropriate pins on all Intel Celeron processor system bus agents. The BCLK (Bus Clock) signal determines the bus frequency. All Intel Celeron processor system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters are specified with respect to the BCLK signal. The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must connect the appropriate pins of all Intel Celeron processor system bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges. The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the status of breakpoints. The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. A20M# I ADS# I/O BCLK I BNR# I/O BP[3:2]# I/O BPM[1:0]# I/O 120 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 2 of 7) Signal Type Description BPRI# I The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Intel Celeron processor system bus. It must connect the appropriate pins of all Intel Celeron processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. These signals are used to select the system bus frequency. The frequency is determined by the processor(s), chipset, and frequency synthesizer capabilities. All system bus agents must operate at the same frequency. Individual processors will only operate at their specified front side bus (FSB) frequency. On motherboards which support operation at either 66 MHz or 100 MHz, a BSEL[1:0] = “x1” will select a 100 MHz system bus frequency and a BSEL[1:0] = “x0” will select a 66 MHz system bus frequency. These signals must be pulled up to 2.5 V or 3.3 V with 1 KΩ resistor and provided as a frequency selection signal to the clock driver/synthesizer. See Section 2.7.2 for implementation examples. note: BSEL1 is not used by the Celeron processor. The BR0# (Bus Request) pin drives the BREQ[0]# signal in the system. During power-up configuration, the central agent asserts the BREQ0# bus signal in the system to assign the symmetric agent ID to the processor. The processor samples it’s BR0# pin on the active-to-inactive transition of RESET# to obtain it’s symmetric agent ID. The processor asserts BR0# to request the system bus. The CPUPRES# signal provides the ability for a system board to detect the presence of a processor. This pin is a ground on the processor indicating to the system that a processor is installed. Combined with the VID combination of VID[3:0]= 1111 (see Section 2.5), a system can determine if a socket is occupied, and whether a processor core is present. See the table below for states and values for determining the presence of a device. BSEL[1:0] I/O BR0# I/O CPUPRES# (PPGA, FC-PGA/ FC-PGA2 only) PGA370 Socket Occupation Truth Table O Signal Value Status CPUPRES# VID[3:0] CPUPRES# VID[3:0] 0 Anything other than ‘1111’ 1 Any value Processor core installed in the PGA370 socket. PGA370 socket not occupied. D[63:0]# I/O The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between the Intel Celeron processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the Intel Celeron processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all Intel Celeron processor system bus agents. The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the appropriate pins of all Intel Celeron processor system bus agents. The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multicycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all Intel Celeron processor system bus agents. DBSY# I/O DEFER# I DRDY# I/O Datasheet 121 Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 3 of 7) Signal Type Description EDGCTRL I The EDGCTRL input provides AGTL+ edge control and should be pulled up to VCCCORE with a 51 Ω ± 5% resistor. NOTE: This signal is NOT used on the FC-PGA/FC-PGA2 packages. EMI pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0 Ω) resistors. The zero ohm resistors should be placed in close proximity to the Intel Celeron processor connector. The path to chassis ground should be short in length and have a low impedance. These pins are used for EMI management purposes. The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*-type floating-point error reporting. When the FLUSH# input signal is asserted, the processor writes back all data in the Modified state from the internal cache and invalidates all internal cache lines. At the completion of this operation, the processor issues a Flush Acknowledge transaction. The processor does not cache any new data while the FLUSH# signal remains asserted. FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction. On the active-to-inactive transition of RESET#, the processor samples FLUSH# to determine its power-on configuration. See Pentium® Pro Family Developer’s Manual, Volume 1: Specifications (Order Number 242690) for details. The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, and must connect the appropriate pins of all Intel Celeron processor system bus agents. Any such agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the Intel Celeron processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction. The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal (L1) caches or floating-point registers. Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). EMI (S.E.P.P. only) I FERR# O FLUSH# I HIT#, HITM# I/O IERR# O IGNNE# I INIT# I 122 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 4 of 7) Signal Type Description LINT[1:0] I The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium® processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. The LOCK# signal indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the system bus throughout the bus locked operation and ensure the atomicity of lock. The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or I/O APIC which is required for operation of all processors, core logic, and I/O APIC components on the APIC bus. The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing on the APIC bus, and must connect the appropriate pins of the Intel Celeron processor for proper initialization. All Intel Celeron processors have internal analog PLL clock generators that require quiet power supplies. PLL1 and PLL2 are inputs to the internal PLL and should be connected to VCCCORE through a low-pass filter that minimizes jitter. See the platform design guide for implementation details. The PRDY (Probe Ready) signal is a processor output used by debug tools to determine processor debug readiness. The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processors. The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The processor requires this signal to be a clean indication that the clocks and power supplies (VCCCORE, etc.) are stable and within their specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high (2.5 V) state. Figure 43 illustrates the relationship of PWRGOOD to other system signals. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 17 and Table 18, and be followed by a 1 ms RESET# pulse. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. PWRGOOD Relationship at Power-On BCLK LOCK# I/O PICCLK I PICD[1:0] I/O PLL1, PLL2 (PGA packages only) PRDY# PREQ# I O I PWRGOOD I VCC , CORE VREF PWRGOOD 1 ms RESET# Datasheet 123 Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 5 of 7) Signal Type Description REQ[4:0]# I/O The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all processor system bus agents. They are asserted by the current bus owner over two clock cycles to define the currently active transaction type. Asserting the RESET# signal resets the processor to a known state and invalidates the L1 cache without writing back any of the contents. RESET# must stay active for at least one millisecond after VCCCORE and CLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Pentium® Pro Family Developer’s Manual, Volume 1: Specifications (Order Number 242690). The processor may have its outputs tristated via power-on configuration. Otherwise, if INIT# is sampled active during the active-to-inactive transition of RESET#, the processor will execute its Built-in Self-Test (BIST). Whether or not BIST is executed, the processor will begin program execution at the power on Reset vector (default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of all processor system bus agents. The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. The RTTCTRL input signal provides AGTL+ termination control. The Celeron FC-PGA/FC-PGA2 processor samples this input to sense the presence of motherboard AGTL+ termination. See the platform design guide for implementation details. The SLEWCTRL input signal provides AGTL+ slew rate control. The Celeron FC-PGA/FC-PGA2 processor samples this input to determine the slew rate for AGTL+ signals when it is the driving agent. See the platform design guide for implementation details. SLOTOCC# is defined to allow a system design to detect the presence of a terminator card or processor in a SC242 connector. This pin is not a signal; rather, it is a short to VSS. Combined with the VID combination of VID[4:0]= 11111 (see Section 2.5), a system can determine if a SC242 connector is occupied, and whether a processor core is present. The states and values for determining the type of cartridge in the SC242 connector is shown below. SC242 Occupation Truth Table RESET# I RS[2:0]# I RTTCTRL I SLEWCTRL I SLOTOCC# (S.E.P.P. only) O Signal Value Status SLOTOCC# VID[4:0] SLOTOCC# VID[4:0] SLOTOCC# VID[4:0] 0 Anything other than ‘11111’ 0 11111 1 Any value Processor with core in SC242 connector. Terminator cartridge in SC242 connector (i.e., no core present). SC242 connector not occupied. SLP# I The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and APIC processor core units. 124 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 6 of 7) Signal Type Description SMI# I The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and APIC units. The processor continues to snoop bus transactions and may latch interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units, resumes execution, and services any pending interrupt. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. The TCK (Test Clock) signal provides the clock input for the Intel Celeron processor Test Access Port. The TDI (Test Data In) signal transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Refer to Section 2.6 for implementation details. Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1. Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1. The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 135 °C. This is signaled to the system by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched, and the processor stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a RESET# pulse will reset the processor and execution will continue. If the temperature has not dropped below the trip level, the processor will reassert THERMTRIP# and remain stopped. The system designer should not act upon THERMTRIP# until after the RESET# input is deasserted. Until this time, the THERMTRIP# is indeterminate. The TMS (Test Mode Select) signal is a JTAG specification support signal used by debug tools. The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Intel Celeron processors require this signal to be driven low during power on Reset. A 680 ohm resistor is the suggested value for a pull down resistor on TRST#. The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input. The processor re-routes the 1.5 V input to the VCCCMOS output via the package. The supply for VCC1.5 must be the same one used to supply VTT. The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input. The processor re-routes the 2.5 V input to the VCCCMOS output via the package. The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input. STPCLK# I TCK TDI TDO TESTHI (S.E.P.P. only) THERMDN THERMDP I I O I O I THERMTRIP# O TMS I TRDY# I TRST# I VCC1.5 (PGA packages only) VCC2.5 (PGA packages only) VCCCMOS (PGA packages only) I I O Datasheet 125 Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 7 of 7) Signal Type Description VCOREDET (PGA packages only) VID[4:0] (S.E.P.P.) VID[3:0] (PGA packages only) O The VCOREDET signal will float for 2.0 V core processors and will be grounded for the Celeron® FC-PGA/FC-PGA2 processor with a 1.5V core voltage. The VID (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification variations on Intel Celeron processors. See Table 2 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself. These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+ inputs are differential receivers and will use this voltage to determine whether the signal is a logic high or logic low. For the FC-PGA/FC-PGA2 packages, VREF is typically 2/3 of VTT O VREF[7:0] (PGA packages only) I 7.1 Signal Summaries Table 60 through Table 63 list attributes of the Celeron processor output, input, and I/O signals. Table 60. Output Signals Name Active Level Clock Signal Group CPUPRES# (PGA packages only) FERR# IERR# PRDY# SLOTOCC# (S.E.P.P. only) TDO THERMDN THERMTRIP# VCOREDET (PGA packages only) VID[4:0] (S.E.P.P.) VID[3:0] (PGA packages) Low Low Low Low Low High N/A Low High Asynch Asynch Asynch BCLK Asynch TCK Asynch Asynch Asynch Power/Other CMOS Output CMOS Output AGTL+ Output Power/Other TAP Output Power/Other CMOS Output Power/Other High Asynch Power/Other 126 Datasheet Intel® Celeron® Processor up to 1.10 GHz Table 61. Input Signals Name Active Level Clock Signal Group Qualified 1 A20M# BPRI# BCLK DEFER# FLUSH# IGNNE# INIT# INTR LINT[1:0] NMI PICCLK PREQ# PWRGOOD RESET# RS[2:0]# RTTCTRL SLEWCTRL SLP# SMI# STPCLK# TCK TDI TESTHI (S.E.P.P. only) THERMDP TMS TRST# TRDY# Low Low High Low Low Low Low High High High High Low High Low Low N/A N/A Low Low Low High High High N/A High Low Low Asynch BCLK — BCLK Asynch Asynch Asynch Asynch Asynch Asynch — Asynch Asynch BCLK BCLK Asynch Asynch Asynch Asynch Asynch — TCK Asynch Asynch TCK Asynch BCLK CMOS Input AGTL+ Input System Bus Clock AGTL+ Input CMOS Input CMOS Input CMOS Input CMOS Input CMOS Input CMOS Input APIC Clock CMOS Input CMOS Input AGTL+ Input AGTL+ Input Power/Other Power/Other CMOS Input CMOS Input CMOS Input TAP Input TAP Input Power/Other Power/Other TAP Input TAP Input AGTL+ Input Always Always Always Always Always 1 Always 1 Always 1 APIC disabled mode APIC enabled mode APIC disabled mode Always Always Always Always Always During Stop-Grant state Always NOTE: 1. Synchronous assertion with active TRDY# ensures synchronization. Datasheet 127 Intel® Celeron® Processor up to 1.10 GHz Table 62. Input/Output Signals (Single Driver) Name Active Level Clock Signal Group Qualified BSEL[1:0] BP[3:2] BR0# A[31:3]# ADS# BPM[1:0]# D[63:0]# DBSY# DRDY# LOCK# REQ[4:0]# Low Low Low Low Low Low Low Low Low Low Low Asynch BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK Power/Other AGTL+ I/O AGTL+I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Always Always Always ADS#, ADS#+1 Always Always DRDY# Always Always Always ADS#, ADS#+1 Table 63. Input/Output Signals (Multiple Driver) Name Active Level Clock Signal Group Qualified BNR# HIT# HITM# PICD[1:0] Low Low Low High BCLK BCLK BCLK PICCLK AGTL+ I/O AGTL+ I/O AGTL+ I/O APIC I/O Always Always Always Always 128 Datasheet