273943-004US

Intel® 80331 I/O Processor Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data Cache with cache locking. Supports write through or write back — 2 KByte, 2-way Set Associative Mini-Data Cache — 128-Entry Branch Target Buffer — 8-Entry Write Buffer — 4-Entry Fill and Pend Buffer — Performance Monitor Unit Internal Bus 266 MHz/64-bit — 333 MHz on D-0 stepping. PCI-X to PCI-X Bridge — Primary and Secondary 133MHz/64-bit PCI-X Interfaces — 8K byte Data Buffers — Four Secondary PCI Output Clocks — Secondary Bus Arbitration — Private Device and Private Memory Address Translation Unit — 2 KB or 4 KB Outbound Read Queue — 4 KB Outbound Write Queue — 4 KB Inbound Read and Write Queue — Connects Internal Bus to PCI/X Bus A — Messaging Unit and Expansion ROM Two Programmable 32-bit Timers and Watchdog Timer Eight General Purpose I/O Pins Two I2C Bus Interface Units Warning: ■ ■ ■ ■ ■ ■ ■ Memory Controller — PC2700 Double Data Rate (DDR333) SDRAM — DDRII 400 SDRAM — Up to 2 GB of 64-bit DDR333 — Up to 1 GB of 64-bit DDRII400 — Optional Single-bit Error Correction, Multi-bit Detection Support (ECC) — Supports Unbuffered or Registered DIMMs and Discrete SDRAM — 32-bit memory support DMA Controller — Two Independent Channels Connected to Internal Bus — Two 1KB Queues in Ch0 and Ch1 — CRC-32C Calculation Application Accelerator UnitRAID 6 support on D-0 stepping — Performs optional XOR on Read Data — Compute Parity Across Local Memory Blocks — 1 KB/512-byte Store Queue Two UART (16550) Units — 64-byte Receive and Transmit FIFOs — 4-pin, Master/Slave Capable Peripheral Bus Interface — 8-/16-bit Data Bus with Two Chip Selects Interrupt Controller Unit — Four Priority Levels — Vector Generation — Twelve External Interrupt Pins with High Priority Interrupt (HPI#) 829-Ball, Flip Chip Ball Grid Array (FCBGA) — 37.5 mm2and 1.27 mm ball pitch Intel Corporation products are not intended for use in life support appliances, devices or systems. Use of a Intel products in such applications without written consent is prohibited. Document Number: 273943-004US August 2005 Intel® 80331 I/O Processor Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright© Intel Corporation, 2005 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 2 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Contents 1.0 Introduction......................................................................................................................... 7 1.1 About This Document............................................................................................ 7 1.1.1 Terminology.............................................................................................. 7 1.1.2 Other Relevant Documents ...................................................................... 8 About the Intel® 80331 I/O Processor ................................................................... 9 Intel XScale® Core ..............................................................................................11 PCI-to-PCI Bridge Unit ........................................................................................11 Address Translation Unit .....................................................................................12 Memory Controller...............................................................................................12 Application Accelerator Unit ................................................................................12 Peripheral Bus Interface......................................................................................12 DMA Controller....................................................................................................13 I2C Bus Interface Unit..........................................................................................13 Messaging Unit....................................................................................................13 Internal Bus .........................................................................................................13 UART Units .........................................................................................................13 Interrupt Controller Unit .......................................................................................14 GPIO ...................................................................................................................14 Functional Signal Descriptions ............................................................................15 Package Thermal Specifications .........................................................................52 Absolute Maximum Ratings.................................................................................53 VCCPLL Pin Requirements ...................................................................................53 Targeted DC Specifications.................................................................................54 Targeted AC Specifications.................................................................................56 4.4.1 Clock Signal Timings..............................................................................56 4.4.2 DDR/DDR-II SDRAM Interface Signal Timings ......................................57 4.4.3 Peripheral Bus Interface Signal Timings ................................................59 4.4.4 I2C Interface Signal Timings...................................................................61 4.4.5 UART Interface Signal Timings ..............................................................61 4.4.6 Boundary Scan Test Signal Timings ......................................................62 AC Timing Waveforms ........................................................................................63 AC Test Conditions .............................................................................................67 1.2 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3.0 3.1 3.2 4.0 4.1 4.2 4.3 4.4 Features ...........................................................................................................................11 Package Information ........................................................................................................15 Electrical Specifications....................................................................................................53 4.5 4.6 Document Number: 273943-004US August 2005 3 Intel® 80331 I/O Processor Datasheet Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Intel® 80331 I/O Processor I/O Processor Functional Block Diagram ................ 10 829-Ball FCBGA Package Diagram .................................................................... 34 Intel® 80331 I/O Processor Ballout (Bottom View) .............................................. 35 Intel® 80331 I/O Processor Ballout - Left Side (Bottom View) ............................ 36 Intel® 80331 I/O Processor Ballout - Right Side (Bottom View) .......................... 37 Clock Timing Measurement Waveforms ............................................................. 63 Output Timing Measurement Waveforms ........................................................... 63 Input Timing Measurement Waveforms .............................................................. 64 I2C/SMBus Interface Signal Timings ................................................................... 64 UART Transmitter Receiver Timing .................................................................... 64 DDR SDRAM Write Timings ............................................................................... 65 DDR SDRAM Read Timings ............................................................................... 65 Write PreAmble/PostAmble Durations ................................................................ 66 AC Test Load for All Signals Except PCI and DDR SDRAM .............................. 67 AC Test Load for DDR SDRAM Signals ............................................................. 67 PCI/PCI-X TOV(max) Rising Edge AC Test Load............................................... 67 PCI/PCI-X TOV(max) Falling Edge AC Test Load .............................................. 68 PCI/PCI-X TOV(min) AC Test Load .................................................................... 68 4 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Tables 1 2 4 3 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Description Nomenclature.............................................................................15 DDR SDRAM Signals..........................................................................................16 MISC SDRAM Signals.........................................................................................17 DDR-II SDRAM Signals.......................................................................................17 Peripheral Bus Interface Signals .........................................................................18 Primary PCI Bus Signals .....................................................................................19 Secondary PCI Bus Signals ................................................................................21 I2C Signals ..........................................................................................................23 Interrupt Signals ..................................................................................................23 UART Signals......................................................................................................24 Test and Miscellaneous Signals..........................................................................26 Reset Strap Signals.............................................................................................27 Power and Ground Pins ......................................................................................29 Pin Mode Behavior ..............................................................................................30 Pin Multiplexing for Functional Modes.................................................................33 FC-style, H-PBGA Package Dimensions ............................................................34 829-Lead Package - Alphabetical Ball Listings ...................................................38 829-Lead Package - Alphabetical Signal Listings ...............................................45 Absolute Maximum Ratings.................................................................................53 Operating Conditions...........................................................................................53 DC Characteristics ..............................................................................................54 ICC Characteristics ..............................................................................................55 PCI Clock Timings...............................................................................................56 DDR Clock Timings .............................................................................................56 DDR SDRAM Signal Timings ..............................................................................57 DDR-II SDRAM Signal Timings...........................................................................58 Peripheral Bus Signal Timings ............................................................................59 PCI Signal Timings..............................................................................................60 I2C Signal Timings...............................................................................................61 UART Signal Timings ..........................................................................................61 Boundary Scan Test Signal Timings ...................................................................62 AC Measurement Conditions ..............................................................................67 Document Number: 273943-004US August 2005 5 Intel® 80331 I/O Processor Datasheet Revision History Date August 2005 March 2005 Revision # 004 003 Updated voltages in Section 4.3. Revised: Table 14, modified pin mode behavior for DQ[63:32] for 32-bit DDR. Table 19, modified Case Temperature Under Bias to 95o C Max Table 20, modified Case Temperature Under Bias to 95o C Max Table 21, modified Vol1 and Voh1 parameters Table 23, added note 4. Table 24, added note 2. Table 25, modified Tvb4 and Tva4. Figure 12, removed Tvb6 parameter. November 2004 002 Added D-0 text to Product Features and body text. Revised Ball Maps and Signal designations for intel® 80331 I/O processor design. Added ICC numbers to Table 22. September 2003 001 Initial Release. Description 6 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Introduction 1.0 1.1 Introduction About This Document This is the Intel® 80331 I/O Processor Datasheet. This document contains a functional overview, package signal locations, targeted electrical specifications, and bus functional waveforms. Detailed functional descriptions other than parametric performance are published in the Intel® 80331 I/O Processor Developer’s Manual. Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. In particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. In fact, this specification does not imply a commitment by Intel to design, manufacture, or sell the product described herein. 1.1.1 Terminology To aid the discussion of the Intel® 80331 I/O processor (80331) architecture, the following terminology is used: Core processor Local processor Host processor Local bus Local memory Inbound Outbound Downstream Upstream QWORD DWORD word Intel XScale® core within the 80331 Intel XScale® core within the 80331 Processor located upstream from the 80331 80331 Internal Bus Memory subsystem on the Intel XScale® core, Memory Controller or Peripheral Bus Interface busses. At or toward the Internal Bus of the 80331 from the PCI interface of the ATU. At or toward the PCI interface of the 80331 ATU from the Internal Bus. At or toward the Secondary PCI interface from the Primary PCI interface. At or toward the Primary PCI interface from the Secondary PCI interface. 64-bit data quantity (8 bytes). 32-bit data quantity (4 bytes). 16-bit data quantity (2 bytes). Document Number: 273943-004US August 2005 7 Intel® 80331 I/O Processor Datasheet Introduction 1.1.2 Other Relevant Documents 1. Intel XScale® Core Developer’s Manual (273473), Intel Corporation. 2. Intel® 80331 I/O Processor Developer’s Manual (273942), Intel Corporationl. 3. Intel® 80331 I/O Processor Design Guide (273823), Intel Corporationl. 4. Intel® 80331 I/O Processor Specification Update (273930), Intel Corporationl. 5. PCI-to-PCI Bridge Architecture Specification, Revision 1.1 - PCI Special Interest Group. 6. PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group. 7. PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a - PCI Special Interest Group. 8. PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Special Interest Group. 8 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Introduction 1.2 About the Intel® 80331 I/O Processor The 80331 is a multi-function device that integrates the Intel XScale® core (ARM* architecture compliant) with intelligent peripherals and PCI-X to PCI-X Bridge. The 80331 consolidates, into a single system: • Intel XScale® core. • PCI-to-PCI Bridge supporting PCI-X interfaces on the Primary and Secondary bus. • Address Translation Unit (PCI-to-Internal Bus Application Bridge) interfaced to the Secondary Bus. • • • • • • • • • High-Performance Memory Controller. Interrupt Controller with up to 12 external interrupt inputs. Two Direct Memory Access (DMA) Controllers. Application Accelerator. Messaging Unit. Peripheral Bus Interface Unit. Two I2C Bus Interface Units. Two 16550 compatible UARTs with flow control (four pins). Eight General Purpose Input Output (GPIO) ports. It is an integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. Document Number: 273943-004US August 2005 9 Intel® 80331 I/O Processor Datasheet Introduction Figure 1 is a functional block diagram of the 80331. Figure 1. Intel® 80331 I/O Processor I/O Processor Functional Block Diagram Intel XScale® Core Interrupt Controller & Timers Bus Interface Unit 32/64-bit DDR Interface Memory Controller 16-bit PBI UART Units 2 - 1²C Units GPIO Internal Bus BRG Application Accelerator 2 Channel DMA Controller Message Unit ATU Arbiter Primary PCI Bus PCI-to-PCI Bridge Secondary PCI Bus B2472-02 10 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Features 2.0 Features The 80331 combines the Intel XScale® core with powerful new features to create an intelligent I/O processor. This multi-device I/O Processor is fully compliant with the PCI Local Bus Specification, Revision 2.3 and the PCI-to-PCI Bridge Architecture Specification, Revision 1.1. The 80331-specific features include: • • • • • • • Intel XScale® core Application Accelerator Unit Address Translation Unit Memory Controller Peripheral Bus Interface Two I2C Bus Interface Units PCI-X to PCI-X Bridge with Primary and Secondary 133 MHz/64-bit PCI-X Interfaces • • • • • • Interrupt Controller Unit Messaging Unit Internal Bus Two DMA Controllers Two UART Units Eight GPIOs The subsections that follow briefly overview each feature. Refer to the Intel® 80331 I/O Processor Developer’s Manual for full technical descriptions. 2.1 Intel XScale® Core The 80331 is based upon the Intel XScale® core. The core processor operates at a maximum frequency of 800 MHz. The instruction cache is 32 Kbytes in size and is 32-way set associative. Also, the core processor includes a data cache that is 32 Kbytes and is 32-way set associative, and a mini data cache that is 2 Kbytes and is two-way set associative. 2.2 PCI-to-PCI Bridge Unit The 80331 provides a PCI-X to PCI-X Bridge unit. The bridge Primary and Secondary PCI-X support 64-bit 133 MHz interfaces compliant to the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. Document Number: 273943-004US August 2005 11 Intel® 80331 I/O Processor Datasheet Features 2.3 Address Translation Unit An Address Translation Unit (ATU) allows PCI transactions direct access to the 80331 local memory. The ATU supports transactions between PCI address space and 80331 address space. Address translation for the ATU is controlled through programmable registers accessible from both the PCI interface and the Intel XScale® core. The PCI interface of the ATU is connected to the 80331 Secondary PCI interface of the bridge. Upstream access to the Primary PCI interface is controlled by inverse decode with the address windows of the bridge. Dual access to registers allows flexibility in mapping the two address spaces. The ATU also supports the power management extended capability configuration header that as defined by the PCI Bus Power Management Interface Specification, Revision 1.1. 2.4 Memory Controller The Memory Controller allows direct control of a DDR SDRAM memory subsystem. It features programmable chip selects and support for error correction codes (ECC). The memory controller may be configured for DDR SDRAM at 333 MHz (with 500 MHz and 667 MHz processors) or DDR-II SDRAM at 400 MHz (with 500 MHz and 800 MHz processors). The memory controller interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete DDR SDRAM devices. The memory contoller is dual-ported, with a dedicated interface for the Intel XScale® core Bus Interface Unit and a second interface to the Internal Bus. External memory may be configured as host addressable memory or private 80331 memory utilizing the Address Translation Unit and Bridge. 2.5 Application Accelerator Unit The Application Accelerator Unit (AA) provides low-latency, high-throughput data transfer capability between the AA unit, the 80331 local memory and the PCI bus. It executes data transfers from and to the 80331 local memory, from the PCI bus to the 80331 local memory, or from the 80331 local memory to the PCI bus. The AA unit performs XOR operations, computes parity, generates and verifies an eight byte data integrity field, performs memory block fills, and provides the necessary programming interface. The AAU has been enhanced to support RAID 6 in the D-0 stepping of the 80331. 2.6 Peripheral Bus Interface The Peripheral Bus Interface Unit is a data communication path to the flash memory components or other peripherals of an 80331 hardware system. The PBI includes support for either 8/16 bit devices. To perform these tasks at high bandwidth, the bus features a burst transfer capability which allows successive 8/16-bit data transfers. 12 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Features 2.7 DMA Controller The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents and the local memory. Two separate DMA channels accommodate data transfers to the PCI bus. Both channels include a local memory to local memory transfer mode. The DMA Controller supports chaining and unaligned data transfers. It is programmable through the Intel XScale® core only. 2.8 I2C Bus Interface Unit The I2C (Inter-Integrated Circuit) Bus Interface Unit allows the Intel XScale® core to serve as a master and slave device residing on the I2C bus. The I2C unit uses a serial bus developed by Philips Semiconductor*, consisting of a two-pin interface. The bus allows the 80331 to interface to other I2C peripherals and microcontrollers for system management functions. It requires a minimum of hardware components for an economical system to relay status and reliability information on the I/O subsystem to an external device. Also refer to I2C Peripherals for Microcontrollers (Philips Semiconductor). The 80331 includes two I2C bus interface units. 2.9 Messaging Unit The Messaging Unit (MU) provides data transfer between the PCI system and the 80331. It uses interrupts to notify each system when new data arrives. The MU has four messaging mechanisms: • • • • Message Registers Doorbell Registers Circular Queues Index Registers Each messaging mechanism allows a host processor or external PCI device and the 80331 to communicate through message passing and interrupt generation. 2.10 Internal Bus The Internal Bus is a high-speed interconnect between internal units and Intel XScale® core processor. The Internal Bus operates at 266 MHz and is 64 bits wide. The internal bus on the D-0 stepping of the 80331 operates at 333MHz. 2.11 UART Units The 80331 includes two UART units. The UART units allow the Intel XScale® core to serve as a master and slave device residing on the UART bus. The UART units use a serial bus consisting of a four-pin interface. The bus allows the 80331 to interface to other peripherals and microcontrollers. Also refer to 16550 Device Specification (National Semiconductor*). Document Number: 273943-004US August 2005 13 Intel® 80331 I/O Processor Datasheet Features 2.12 Interrupt Controller Unit The Interrupt Controller Unit (ICU) aggregates interrupt sources both external and internal of the 80331 to the Intel XScale® core processor. The ICU supports high performance interrupt processing with direct interrupt service routine vector generation on a per source basis. Each source has programmability for masking, core processor interrupt input, and priority. 2.13 GPIO The 80331 includes eight General Purpose I/O (GPIO) pins which can also be used as external interrupt inputs. 14 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information 3.0 Package Information The 80331 is offered in a Flip Chip Ball Grid Array (FCBGA) package. This is a full grid array package with 829 ball connections. 3.1 Table 1. Functional Signal Descriptions Pin Description Nomenclature Symbol C I O I/O OD PWR GND Sync(...) Configuration Input pin only Output pin only Pin may be either an input or output. Open Drain pin Power pin Ground pin Pin must be connected as described. Synchronous. Signal meets timings relative to a clock. Sync(P) Synchronous to P_CLK Sync(M) Synchronous to M_CK[2:0] Sync(S) Synchronous to S_CLKIN Sync(T) Synchronous to TCK Async Rst(P) Rst(S) Rst(M) Rst(T) Asynchronous. Inputs may be asynchronous relative to all clocks. All asynchronous signals are level-sensitive. The pin is reset with P_RST# The pin is reset with S_RST#. Note that S_RST# is asserted when P_RST# is asserted. The pin is reset with M_RST#. Note that M_RST# is asserted when P_RST#is asserted or is asserted with software. The pin is reset with TRST#. Description Document Number: 273943-004US August 2005 15 Intel® 80331 I/O Processor Datasheet Package Information Table 2. DDR SDRAM Signals Name M_CK[2:0] M_CK[2:0]# M_RST# MA[13:0] BA[1:0] Count 3 3 1 14 2 Type O O O Async O Sync(M), Rst(M) O Sync(M), Rst(M) RAS# CAS# 1 1 O Sync(M), Rst(M) O Sync(M), Rst(M) WE# CS[1:0]# CKE[1:0] 1 2 2 O Sync(M), Rst(M) O Sync(M), Rst(M) O Sync(M), Rst(M) DQ[63:0] 64 I/O Sync(M), Rst(M) Description Memory Clocks are used to provide the positive differential clocks to the external SDRAM memory subsystem. Memory Clocks are used to provide the negative differential clocks to the external SDRAM memory subsystem. Memory Reset indicates when the memory subsystem has been reset with P_RST# or a software reset. Memory Address Bus carries the multiplexed row and column addresses to the SDRAM memory banks. SDRAM Bank Address indicates which of the SDRAM internal banks are read or written during the current transaction. SDRAM Row Address Strobe indicates the presence of a valid row address on the Multiplexed Address Bus MA[12:0]. SDRAM Column Address Strobe indicates the presence of a valid column address on the Multiplexed Address Bus MA[12:0]. SDRAM Write Enable indicates that the current memory transaction is a write operation. SDRAM Chip Select enables the SDRAM devices for a memory access (Physical banks 0 and 1). SDRAM Clock Enable enables the clocks for the SDRAM memory. Deasserting will place the SDRAM in self-refresh mode. SDRAM Data Bus carries 64-bit data to and from memory. During a data cycle, read or write data is present on one or more contiguous bytes. During write operations, unused pins are driven to determinate values. SDRAM ECC Check Bits carry the 8-bit ECC code to and from memory during data cycles. SDRAM Data Strobes carry the strobe signals, output in write mode and input in read mode for source synchronous data transfer. SDRAM Data Mask controls which bytes on the data bus should be written. When DM[8:0] is asserted, the SDRAM devices do not accept valid data from the byte lanes. CB[7:0] DQS[8:0] 8 9 I/O Sync(M), Rst(M) I/O Sync(M), Rst(M) DM[8:0] 9 O Sync(M), Rst(M) Total 120 16 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 3. DDR-II SDRAM Signals Name DQS[8:0]# Count 9 Type I/O Sync(M) Rst(M) ODT[1:0] 2 O Sync(M) Rst(M) DDRRES[2:1] Total 2 13 I/O Compensation For DDR OCD (analog) DDR-II mode only. Description SDRAM Data Strobes carry the differential strobe signals in DDR-II mode, output in write mode and input in read mode for source synchronous data transfer. On Die Termination Control, turns on SDRAM termination during writes. Table 4. MISC SDRAM Signals Name DDRCRES0 Count 1 Type O Description Analog VSS Ref Pin (analog) both DDRSLWCRES and DDRIMPCRES signals connect to this pin through a reference resistor. Compensation Voltage Reference (analog) for DDR driver slew rate control connected through a resistor to DDRCRES0. Compensation Voltage Reference (analog) for DDR driver impedance control connected through a resistor to DDRCRES0. DDRSLWCRES DDRIMPCRES Total 1 1 3 I/O I/O Document Number: 273943-004US August 2005 17 Intel® 80331 I/O Processor Datasheet Package Information Table 5. Peripheral Bus Interface Signals Name A[22:16] Count 7 Type O Rst(M) Description Address Bus 22:16 carries a demultiplexed version of address bits A22:16. During address (Ta), wait state (Tw) and data cycles (Td) cycles, A22:16 represents the upper seven address bits for the current access. A22:16 allows the PBI interface to address up to 8 Mbytes per peripheral device. See “Table 12, “Reset Strap Signals” on page 27” for a functional description. AD[15:0] 16 I/O Rst(M) Address/Data Bus carries 16-bit physical addresses and 8-, or 16-bit data to and from memory. During an address (Ta) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, bits 0-7, or 0-15 contain read or write data, depending on the corresponding bus width. During write operations to 8-bit wide memory regions, the PBI drives unused bus pins high or low. SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the number of data transfers during the bus transaction. AD1 AD0 0 0 0 1 1 0 1 1 1 Transfer 2 Transfers 3 Transfers 4 Transfers See “Table 12, “Reset Strap Signals” on page 27” for a functional description. A[2:0] 3 O Rst(M) Address Bus 2:0 carries a demultiplexed version of bits 2:0 of the AD[15:0] bus. During an address (Ta) cycle, bits A[2:0] matches AD[2:0]. During a bursted read data (Td) cycle, A[2:0] will represent the current byte address in the bursted transaction. A[2:1] are used for an 16-bit wide peripheral while A[1:0] are used for an 8-bit wide peripheral. See “Table 12, “Reset Strap Signals” on page 27” for a functional description. ALE 1 O Rst(M) POE# 1 O Rst(M) Address Latch Enable indicates the transfer of a physical address. The pin is asserted during the first address cycle and deasserted during the second address cycle. Peripheral Output Enable Indicates whether the bus access is a write or a read with respect to the I/O processor and is valid during the entire bus access. This pin may be used to control the OE# input on peripheral devices. 0 = Read 1 = Write PWE# 1 O Rst(M) Peripheral Write Enable indicates whether the bus access is a write or a read with respect to the I/O processor and is valid during the entire bus access. This pin is use for flash memory accesses and controls the WE# input on the ROM. 0 = Write 1 = Read PCE[1]# 1 O Rst(M) PCE[0]# 1 O Rst(M) Total 31 Peripheral Chip Enables specify which of the two memory address ranges are associated with current bus access. The pin remains valid during the entire bus access. Peripheral Chip Enables specify which of the two memory address ranges are associated with current bus access. The pin remains valid during the entire bus access. 18 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 6. Primary PCI Bus Signals (Sheet 1 of 2) Name P_AD[31:0] Count 32 Type I/O Sync(P) Rst(P) P_AD[63:32] 32 I/O Sync(P) Rst(P) P_PAR 1 I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) O Sync(P) Rst(P) P_REQ64# 1 I/O Sync(P) Rst(P) I Sync(P) I Sync(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) P_DEVSEL# 1 I/O Sync(P) Rst(P) I/O OD Sync(P) Rst(P) Primary PCI Bus Device Select is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. Primary PCI Bus System Error is driven for address parity errors on the PCI bus. Description Primary PCI Address/Data is the multiplexed PCI address and lower 32 bits of the data bus. Primary PCI Address/Data is the upper 32 bits of the PCI data bus driven during the data phase. Primary PCI Bus Parity is even parity across P_AD[31:0] and P_C/BE[3:0]#. Primary PCI Bus Upper DWORD Parity is even parity across P_AD[63:32] and P_C/BE[7:4]# Primary PCI Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase, they define the bus command. During the data phase, they are used as byte enables for P_AD[63:0]. Primary PCI Bus Request indicates to the PCI bus arbiter that the I/O processor desires use of the PCI bus. Primary PCI Bus Request 64-Bit Transfer indicates the attempt of a 64-bit transaction on the PCI bus. When the target is 64-bit capable, the target acknowledges the attempt with the assertion of P_ACK64#. Primary PCI Bus Initialization Device Select is used to select the 80331 during a Configuration Read or Write command on the PCI bus. Primary PCI Bus Grant indicates that access to the PCI bus has been granted. Primary PCI Bus Acknowledge 64-Bit Transfer indicates that the device has positively decoded its address as the target of the current access and the target is willing to transfer data using the full 64-bit data bus. Primary PCI Bus Cycle Frame is asserted to indicate the beginning and duration of an access. Primary PCI Bus Initiator Ready indicates the initiating agent’s ability to complete the current data phase of the transaction. During a write, it indicates that valid data is present on the Address/Data bus. During a read, it indicates the processor is ready to accept the data. Primary PCI Bus Target Ready indicates the target agent’s ability to complete the current data phase of the transaction. During a read, it indicates that valid data is present on the Address/Data bus. During a write, it indicates the target is ready to accept the data. Primary PCI Bus Stop indicates a request to stop the current transaction on the PCI bus. P_PAR64 1 P_C/BE[7:0]# 8 P_REQ# 1 P_IDSEL 1 P_GNT# P_ACK64# 1 1 P_FRAME# 1 P_IRDY# 1 P_TRDY# 1 P_STOP# 1 P_SERR# 1 Document Number: 273943-004US August 2005 19 Intel® 80331 I/O Processor Datasheet Package Information Table 6. Primary PCI Bus Signals (Sheet 2 of 2) Name P_PERR# Count 1 Type I/O Sync(P) Rst(P) I/O Description Primary PCI Bus Parity Error is asserted when a data parity error occurs during a PCI bus transaction. Primary PCI Bus 66 MHz Enable indicates the speed of the PCI bus. When this signal is sampled high the PCI bus speed is 66 MHz, when low, the bus speed is 33 MHz. Primary PCI Bus Input Clock provides the timing for all PCI transactions and is the clock source for most internal 80331 units. RESET brings PCI-specific registers, sequencers, and signals to a consistent state. When P_RST# is asserted: • PCI output signals are driven to a known consistent state. • PCI bus interface output signals are three-stated. Async • Open drain signals such as P_SERR# are floated. P_RST# may be asynchronous to P_CLK when asserted or deasserted. Although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. P_RCOMP Total 1 90 I/O PCI Resistor Compensation Pin is an analog pad that connects to the board resistor to control all pci output driver strengths (analog). P_M66EN 1 P_CLK P_RST# 1 1 I I NOTE: When the PCI bridge is disabled (BRG_EN = 0), all primary PCI interface signals become inactive, and the secondary interface becomes a primary PCI interface. 20 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 7. Secondary PCI Bus Signals (Sheet 1 of 2) Name S_AD[31:0] Count 32 Type I/O Sync(S) Rst(S) S_AD[63:32] 32 I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) S_PAR64 1 I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) I/O Sync(S) Rst(S) S_DEVSEL# 1 I/O Sync(S) Rst(S) I/O OD Sync(S) Rst(S) S_RST# 1 O Async Secondary PCI Bus Device Select is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. Secondary PCI Bus System Error is driven for address parity errors on the secondary PCI bus. Description Secondary PCI Address/Data is the multiplexed PCI address and lower 32 bits of the data bus. Secondary PCI Address/Data is the upper 32 bits of the PCI data bus. Secondary PCI Bus Parity is even parity across S_AD[31:0] and S_C/BE[3:0]#. Secondary PCI Bus Upper DWORD Parity is even parity across S_AD[63:32] and S_C/BE[7:4]#. Secondary PCI Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase, they define the bus command. During the data phase, they are used as the byte enables for S_AD[31:0]. Secondary PCI Byte Enables are used as byte enables for S_AD[63:32] during secondary PCI data phases. Secondary PCI Bus Request 64-Bit Transfer indicates the attempt of a 64-bit transaction on the secondary PCI bus. When the target is 64-bit capable, the target acknowledges the attempt with the assertion of S_ACK64#. Secondary PCI Bus Acknowledge 64-Bit Transfer indicates the device has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64 bits. Secondary PCI Bus Cycle Frame is asserted to indicate the beginning and duration of an access. Secondary PCI Bus Initiator Ready indicates the initiating agent ability to complete current data phase of transaction. During a write, it indicates valid data is present on the secondary Address/Data bus. During a read, it indicates the processor is ready to accept the data. Secondary PCI Bus Target Ready indicates the target agent ability to complete the current data phase of the transaction. During a read, it indicates that valid data is present on the secondary Address/Data bus. During a write, it indicates the target is ready to accept the data. Secondary PCI Bus Stop indicates a request to stop the current transaction on the secondary PCI bus. S_PAR 1 S_C/BE[3:0]# 4 S_C/BE[7:4]# 4 S_REQ64# 1 S_ACK64# 1 S_FRAME# 1 S_IRDY# 1 S_TRDY# 1 S_STOP# 1 S_SERR# 1 Secondary PCI Bus Reset is an output based on P_RST#. It brings PCI-specific registers, sequencers, and signals to a consistent state. When P_RST# is asserted, it causes S_RST# to assert and: • PCI output signals are driven to a known consistent state. • PCI bus interface output signals are three-stated. • Open drain signals such as S_SERR# are floated. S_RST# may be asynchronous to S_CLKIN when asserted or deasserted. Although asynchronous, deassertion must be ensured to be a clean, bounce-free edge. Document Number: 273943-004US August 2005 21 Intel® 80331 I/O Processor Datasheet Package Information Table 7. Secondary PCI Bus Signals (Sheet 2 of 2) Name S_PERR# Count 1 Type I/O Sync(S) Rst(S) O O I Description Secondary PCI Bus Parity Error is asserted when a data parity error during a secondary PCI bus transaction. Secondary PCI Bus Output Clocks are used to drive external logic on the secondary PCI bus. Secondary PCI Bus Output Clock is used to drive S_CLKIN when the IO processor provides secondary bus clocks. Secondary PCI Bus Input Clock provides the timing for all PCI transactions. Typically connected on the board to S_CLKOUT. Provides the timing clock for all secondary PCI interfaces. When the PCI Bridge is disabled (BRG_EN=0), this is the Primary PCI Input Clock, driven by an external device. S_M66EN 1 I/O Secondary PCI Bus 66 MHz Enable indicates the speed of the secondary PCI bus. When this signal is high, the bus speed is 66 MHz and when it is low, the bus speed is 33 MHz. Secondary PCI Bus Request is the request signal from device 3 on the secondary PCI bus. When the PCI Bridge is disabled (BRG_EN=0), this pin functions as PCI Bus Initialization Device Select and is used to select the 80331 during a Configuration Read or Write command on the PCI bus. S_REQ[1]# P_GNT#1 1 I Sync(S) Secondary PCI Bus Request is the request signal from device 1 on the secondary PCI bus. When the PCI Bridge is disabled (BRG_EN=0), this pin functions as Primary PCI Bus Grant indicating that access to the PCI bus has been granted. S_REQ[2,0]# S_GNT[3,2]# 2 2 I Sync(S) O Sync(A) Rst(A) S_GNT[1]#/ P_REQ#1 1 O Sync(S) Rst(S) Secondary PCI Bus Grant is a grant signal sent to device 1 on the secondary PCI bus. When the PCI Bridge is disabled (BRG_EN=0), this pin functions as Primary PCI Bus Request and indicates to the PCI bus arbiter that the I/O processor desires use of the PCI bus. Secondary PCI Bus Grant is a grant signal sent to device 0 on the secondary PCI bus. When the PCI Bridge is disabled (BRG_EN=0), this pin functions as PCI Bus Master Indicator to be used with external RAIDIOS logic for private device control. Secondary PCI-X Capability is an analog pad that selects PCI/X mode and frequency capabilities. Non-standard, special purpose analog pin. PCI Resistor Compensation Pin is an analog pad that connects to the board resistor to control all PCI output driver strengths (analog). Secondary PCI Bus Requests are the request signals from devices 2 and 0 on the secondary PCI bus. Secondary PCI Bus Grants are grant signals sent to devices 3 and 2 on the secondary PCI bus. S_CLKO[3:0] S_CLKOUT S_CLKIN/ P_CLK1 4 1 1 S_REQ[3]#/ P_IDSEL1 1 I Sync(S) S_GNT[0]#/ P_BMI1 1 O/OD Sync(S) Rst(S) S_PCIXCAP 1 I S_RCOMP Total 1 101 I/O NOTE: When the PCI Bridge is disabled (BRG_EN=0), all secondary PCI interface signals become primary interface signals. 1. These signal functions are only valid when BRG_EN=0 and ARB_EN=0. 22 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 8. Interrupt Signals Name P_INT[D:A]# Count 4 Type O OD Async Rst(P) S_INT[D:A]# 4 I Async Rst(S) Description Primary PCI Bus Interrupt requests an interrupt. The assertion and deassertion of P_INT[D:A]# is asynchronous to P_CLK. A device asserts its P_INT[D:A]# line when requesting attention from its device driver. Once the P_INT[D:A]# signal is asserted, it remains asserted until the device driver clears the pending request. P_INT[D:A]# interrupts are level sensitive. Secondary PCI Bus Interrupt requests an interrupt. The assertion and deassertion of S_INT[D:A]# is asynchronous to S_CLKIN. A device asserts its S_INT[D:A]# line when requesting attention from its device driver. Once the S_INT[D:A]# signal is asserted, it remains asserted until the device driver clears the pending request. S_INT[D:A]# interrupts are level sensitive. High Priority Interrupt causes a high priority interrupt to the I/O processor. This pin is level-detect only and is internally synchronized. HPI# 1 I Async Total 9 Table 9. I2C Signals Name SCL0 SCD0 SCL1 SCD1 Total Count 1 1 1 1 4 Type I/O I/O I/O I/O Description I2C Clock provides synchronous operation of the I2C bus zero. I2C Data is used for data transfer and arbitration of the I2C bus zero. I2C Clock provides synchronous operation of the I2C bus one. I2C Data is used for data transfer and arbitration of the I2C bus one. Document Number: 273943-004US August 2005 23 Intel® 80331 I/O Processor Datasheet Package Information Table 10. UART Signals (Sheet 1 of 2) Name GPIO[0]/ U0_RXD Count 1 Type I/O Description General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Serial Input: Serial data input from device pin to receive shift register. GPIO[1]/ U0_TXD 1 I/O General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Serial Output: Composite serial data output to the communications link-peripheral, modem, or data set. The TXD signal is set to the MARKING (logic 1) state upon a Reset operation. GPIO[2]/ U0_CTS# 1 I/O General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Clear To Send: When low, this pin indicates that the receiving UART is ready to receive data. When the receiving UART deasserts CTS# high, the transmitting UART should stop transmission to prevent overflow of the receiving UARTs buffer. The CTS# signal is a modem-status input whose condition may be tested by the host processor or by the UART when in Autoflow mode as described below: Non-Autoflow Mode: When not in Autoflow mode, bit 4 (CTS) of the Modem Status register (MSR) indicates the state of CTS#. Bit 4 is the complement of the CTS# signal. Bit 0 (DCTS) of the Modem Status register indicates whether the CTS# input has changed state since the previous reading of the Modem Status register. CTS# has no effect on the transmitter. The user may program the UART to interrupt the processor when DCTS changes state. The programmer may then stall the outgoing data stream by starving the transmit FIFO or disabling the UART with the IER register. NOTE: When UART transmission is stalled by disabling the UART, the user may not receive an MSR interrupt when CTS# reasserts. This occurs because disabling the UART also disables interrupts. As a workaround, the user may use Auto CTS in Autoflow Mode, or program the CTS# pin to interrupt. Autoflow Mode: NOTE: In Autoflow mode, the UART Transmit circuitry will check the state of CTS# before transmitting each byte. When CTS# is high, no data is transmitted. GPIO[3]/ U0_RTS# 1 I/O General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Request To Send: When low, this informs the remote device that the UART is ready to receive data. A reset operation sets this signal to its Inactive (high) state. LOOP mode operation holds this signal in its Inactive state. Non-Autoflow Mode: The RTS# output signal may be asserted by setting bit 1 (RTS) of the Modem Control register to a 1. The RTS bit is the complement of the RTS# signal. Autoflow Mode: RTS# is automatically asserted by the autoflow circuitry when the Receive buffer exceeds its programmed threshold. It is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. 24 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 10. UART Signals (Sheet 2 of 2) Name GPIO[4]/ U1_RXD Count 1 Type I/O Description General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Serial Input: Serial data input from device pin to receive shift register. GPIO[5]/ U1_TXD 1 I/O General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Serial Output: Composite serial data output to the communications link-peripheral, modem, or data set. The TXD signal is set to the MARKING (logic 1) state upon a Reset operation. GPIO[6]/ U1_CTS# 1 I/O General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Clear To Send: When low, this pin indicates that the receiving UART is ready to receive data. When the receiving UART deasserts CTS# high, the transmitting UART should stop transmission to prevent overflow of the receiving UARTs buffer. The CTS# signal is a modem-status input whose condition may be tested by the host processor or by the UART when in Autoflow mode as described below: Non-Autoflow Mode: When not in Autoflow mode, bit 4 (CTS) of the Modem Status register (MSR) indicates the state of CTS#. Bit 4 is the complement of the CTS# signal. Bit 0 (DCTS) of the Modem Status register indicates whether the CTS# input has changed state since the previous reading of the Modem Status register. CTS# has no effect on the transmitter. The user may program the UART to interrupt the processor when DCTS changes state. The programmer may then stall the outgoing data stream by starving the transmit FIFO or disabling the UART with the IER register. NOTE: When UART transmission is stalled by disabling the UART, the user may not receive an MSR interrupt when CTS# reasserts. This occurs because disabling the UART also disables interrupts. As a workaround, the user may use Auto CTS in Autoflow Mode, or program the CTS# pin to interrupt. Autoflow Mode: NOTE: In Autoflow mode, the UART Transmit circuitry will check the state of CTS# before transmitting each byte. When CTS# is high, no data is transmitted. GPIO[7]/ U1_RTS# 1 I/O General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Request To Send: When low, this informs the remote device that the UART is ready to receive data. A reset operation sets this signal to its Inactive (high) state. LOOP mode operation holds this signal in its Inactive state. Non-Autoflow Mode: The RTS# output signal may be asserted by setting bit 1 (RTS) of the Modem Control register to a 1. The RTS bit is the complement of the RTS# signal. Autoflow Mode: RTS# is automatically asserted by the autoflow circuitry when the Receive buffer exceeds its programmed threshold. It is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. Total 8 Document Number: 273943-004US August 2005 25 Intel® 80331 I/O Processor Datasheet Package Information Table 11. Test and Miscellaneous Signals Name TCK Count 1 Type I Description Test Clock provides clock input for IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the device on the rising clock edge and data is clocked out on the falling clock edge. Test Data Input is the JTAG serial input pin. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. This signal has a weak internal pull-up to ensure proper operation when this pin is not being driven. Test Data Output is the serial output pin for the JTAG feature. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At other times, TDO floats. The behavior of TDO is independent of P_RST#. Test Reset asynchronously resets the Test Access Port controller function of IEEE 1149 Boundary Scan Testing (JTAG). This pin has a weak internal pull-up. Test Mode Select is sampled on the rising edge of TCK to select the operation of the test logic for IEEE 1149 Boundary Scan testing. This pin has a weak internal pull-up. No Connect. Do not connect to any signal, power or ground. Pullup 1 must be pulled high. NOTE: This signal was formerly known as P_LOCK#. Pullup 2 must be pulled high. Is controlled by PCIODT_EN. NOTE: This signal was formerly known as S_LOCK#. Power Fail Delay is used to delay the reset of the memory controller in a power-fail condition. This allows the self-refresh command to be sent to the DDR SDRAM array. TDI 1 I Sync(T) TDO 1 O Sync(T) Rst(T) TRST# 1 I Async TMS 1 I Sync(T) N/C PU1 PU2 PWRDELAY 64 1 1 1 I I I Async Total 72 26 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 12. Reset Strap Signals (Sheet 1 of 2) Name RETRY Count 1 Type C Description Configuration Retry Mode: RETRY is latched on the rising (deasserting) edge of P_RST# and determines when the PCI interface of the ATU will disable PCI configuration cycles by signaling a retry until the configuration cycle retry bit is cleared in the PCI configuration and status register. 0 = Configuration Cycles enabled (Requires pull down resistor.) 1 = Configuration Retry enabled in the ATU (Default mode) NOTE: Muxed onto signal AD[6], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. CORE_RST# 1 C Core Reset Mode is latched on the rising (deasserting) edge of P_RST# and determines when the Intel XScale® core is held in reset until the processor reset bit is cleared in PCI configuration and status register. 0 = Hold in reset. (Requires pull-down resistor.) 1 = Do not hold in reset. (Default mode) NOTE: Muxed onto signal AD[5], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. P_BOOT16# 1 C Bus Width is latched on the rising (deasserting) edge of P_RST#, it sets the default bus width for the PBI Memory Boot window. 0 = 16 bits wide (Requires a pull-down resistor.) 1 = 8 bits wide (Default mode) NOTE: Muxed onto signal AD[4], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. MEM_TYPE 1 C Memory Type: MEM_TYPE is latched on the rising (deasserting) edge of P_RST# and it defines the speed of the DDR SDRAM interface. 0 = DDR-II SDRAM at 400 MHz (Required pull-down resistor.) 1 = DDR SDRAM at 333 MHz (Default mode) NOTE: Muxed onto signal AD[2], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. S_PCIX133EN 1 Config Secondary PCI Bus 133 MHz Enable: S_PCIX133EN latched on rising (deasserting) edge of P_RST# and determines maximum PCI-X mode operating frequency. 0 = 100 MHz enabled (Requires pull down resistor.) 1 = 133 MHz enabled (Default mode) NOTE: Muxed onto signal AD[3], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. PRIVMEM 1 Config Private Memory Enable: PRIVMEM latched at rising (deasserting) edge of P_RST# and determines if 80331 operates with Private Memory Space on the secondary PCI bus of the PCI-to-PCI Bridge. 0 = Normal addressing mode (Requires pull-down resistor) 1 = Private Addressing enable in PCI-to-PCI Bridge. (Default mode). NOTE: Muxed onto signal A[1], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. PRIVDEV 1 Config Private Device Enable: PRIVDEV latched at rising (deasserting) edge of P_RST# and determines if 80331 operates with Private Device enabled on the secondary PCI bus of the PCI-to-PCI Bridge. 0 = All Secondary PCI devices are accessible to Primary PCI config cycles. (Requires pull-down resistor) 1 = Private Devices enabled in PCI-to-PCI Bridge. (Default mode) NOTE: Muxed onto signal A[0], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. Document Number: 273943-004US August 2005 27 Intel® 80331 I/O Processor Datasheet Package Information Table 12. Reset Strap Signals (Sheet 2 of 2) Name BRG_EN Count 1 Type Config Description Bridge Enable: BRG_EN latched at rising (deasserting) edge of P_RST# and determines if 80331 operates with PCI-to-PCI Bridge. 0 = Disable Bridge, enable P_CLK input on S_CLKIN input. (Requires pull-down resistor) 1 = Enabled Bridge. (Default mode) NOTE: Muxed onto signal AD[0], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. ARB_EN 1 Config Internal Arbiter Enable: ARB_EN is latched on the rising (deasserting) edge of P_RST# and it determines if the PCI interface will enable the integrated arbiter, or use an external arbiter. NOTE: ARB_EN only valid when PCI bridge disabled (BRG_EN=0). 0 = Internal Arbiter disabled (Requires pull-down resistor). 1 = Internal Arbiter enabled (Default mode). NOTE: Muxed onto signal AD[1], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. P_32BITPCI# 1 Config Primary PCI-X Bus Width: P_32BITPCI# is latched on the rising (deasserting) edge of P_RST#, and by default, identifies 80331 subsystem as 64-bit unless the appropriate pull-down resistor is used. This strap sets bit 16 in the PCI-X Bridge status register. 0 = 32 bit wide bus. (Requires pull-down resistor). 1 = 64 bit wide bus. (Default mode). NOTE: Muxed onto signal A[2], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. PCIODT_EN 1 C PCI Bus ODT Enable: PCIODT_EN is latched on the rising (deasserting) edge of P_RST#, and determines when the PCI-X interface will have On Die Termination enabled. PCI ODT enable is valid for the secondary PCI bus only. The following signals are affected by PCIODT_EN: S_AD[63:32], S_C/BE[7:4]#, S_PAR64, S_REQ64#, S_REQ[3:0]#, S_ACK64#, S_FRAME#, S_IRDY#, S_DEVSEL#, S_TRDY#, S_STOP#, S_PERR#, S_LOCK#, S_M66EN, S_SERR#, S_INT[D:A]# 0 = ODT disabled on the secondary PCI bus. (Requires pull-down resistor). 1 = ODT enabled on the secondary PCI bus. (Default mode). NOTE: Muxed onto signal A[20], see Table 15, “Pin Multiplexing for Functional Modes” on page 33. Total 11 28 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 13. Power and Ground Pins Name VCCPLL[1-5] Count 4 Type PWR Description PLL 1-5 Power is a separate VCC15 supply ball for the phase lock loop clock generator. It is to be connected to the board VCC15 plane. Each VCCPLL requires a lowpass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. See the Intel® 80331 I/O Processor Design Guide for more information. Note: There is no VCCPLL3 signal. VCC33 VCC25/18 VCC15 VCC13 DDR_VREF VSS VSSA[1-5] 49 29 58 7 1 226 4 PWR PWR PWR PWR I GND GND 3.3 V Power balls to be connected to a 3.3 V power board plane. 2.5 V/1.8 V Power balls to be connected to a 2.5 V or 1.8 V power board plane, dependent on DDR or DDRII mode. 1.5 V Power balls to be connected to a 1.5 V power board plane. 1.3 V Power balls to be connected to a 1.35 V power board plane. SDRAM Voltage Reference is used to supply the reference voltage to the differential inputs of the memory controller pins. Ground balls to be connected to a ground board plane. Analog Ground balls need to be connected to the appropriate VCCPLL filter, and not to board ground. Note: There is no VSSA3 signal. Document Number: 273943-004US August 2005 29 Intel® 80331 I/O Processor Datasheet Package Information Table 14. Pin Mode Behavior (Sheet 1 of 3) Pin M_CK[2:0] M_CK[2:0]# M_RST# MA[13:0] BA[1:0] RAS# CAS# WE# CS[1:0]# CKE[1:0] DQ[63:32] DQ[31:0] CB[7:0] DQS[8] DQS[7:4] DQS[3:0] DQS[8]# DQS[7:4]# DQS[3:0]# DM[8] DM[7:4] DM[3:0] DDR_VREF ODT[1:0] (2) DDRRES[2:1] DDRCRES0 DDRSLWCRES DDRIMPCRES A[22:16] AD[15:0] A[2:0] ALE POE# PWE# PCE[1]# PCE[0]# P_AD[63:32] P_AD[31:0] P_PAR Reset Lind X (1) X (1) 0 0* 0* 1* 1* 1* 1* 0* Z* Z* Z* Z* Z* Z* Z* Z* Z* Z* Z* Z* VI 0 Z* 0 VB VB H H H 0 1 1 H H Z 0 Z Reset Lind nobrg X (1) X (1) 0 0* 0* 1* 1* 1* 1* 0* Z* Z* Z* Z* Z* Z* Z* Z* Z* Z* Z* Z* VI 0 Z* 0 VB VB H H H 0 1 1 H H Z Z Z Norm Lind VO VO VO VO VO VO VO VO VO VO VB VB VB VB VB VB VB VB VB VO VO VO VI VO VB 0 VB VB VO VB VO VO VO VO VO VO VB VB VB Norm Lind nobrg VO VO VO VO VO VO VO VO VO VO VB VB VB VB VB VB VB VB VB VO VO VO VI VO VB 0 VB VB VO VB VO VO VO VO VO VO H H H ECC off DDR VO VO VO VO VO VO VO VO VO VO VB VB VB ID,Z VB VB ID,Z VB VB Z VO VO VI VO VB 0 VB VB 32Bit DDR VO VO VO VO VO VO VO VO VO VO ID,Z VB VB VB ID,Z VB VB ID,Z VB VO Z VO VI VO VB 0 VB VB 32Bit P_PCI H VB VB 32Bit S_PCI - 30 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 14. Pin Mode Behavior (Sheet 2 of 3) Pin P_PAR64 P_C/BE[7:4]# P_C/BE[3:0]# P_REQ# P_REQ64# P_IDSEL P_GNT# P_ACK64# P_FRAME# P_IRDY# P_TRDY# P_STOP# P_DEVSEL# P_LOCK# P_SERR# P_CLK P_RST# P_PERR# P_M66EN S_AD[63:32] S_AD[31:0] S_PAR S_PAR64 S_C/BE[3:0]# S_C/BE[7:4]# S_REQ64# S_ACK64# S_FRAME# S_IRDY# S_TRDY# S_STOP# S_DEVSEL# S_SERR# S_RST# S_PERR# S_LOCK# S_CLKO[3:0] S_CLKOUT Reset Lind Z Z Z 1 VI VI VI Z Z Z VI VI VI Z Z VI VI Z VB Z 0 0 Z 0 Z VO Z Z Z VO VO VO Z VO Z Z VO VO Reset Lind nobrg Z Z Z Z H H H H H H H H H H H H VI H H Z Z Z Z Z Z VI Z Z Z VI VI VI Z Z Z Z Z Z Norm Lind VB VB VB VO VB VI VI VB VB VB VB VB VB VB VB VI VI VB VB VB VB VB VB VB VB VB VB VB VB VB VB VB VB VO VB VB VO VO Norm Lind nobrg H H H Z H H H H H H H H H H H H VI H H VB VB VB VB VB VB VB VB VB VB VB VB VB VB Z VB VB Z Z ECC off DDR 32Bit DDR 32Bit P_PCI H H VB 32Bit S_PCI H H H - Document Number: 273943-004US August 2005 31 Intel® 80331 I/O Processor Datasheet Package Information Table 14. Pin Mode Behavior (Sheet 3 of 3) Pin S_CLKIN S_M66EN S_REQ[3]#/ P_IDSEL S_REQ[1]#/ P_GNT# S_REQ[2,0]# S_GNT[3,2]#, S_GNT[1]#/ P_REQ# S_GNT[0]#/ P_BMI S_PCIXCAP P_RCOMP S_RCOMP P_INT[D:A]# S_INT[D:A]# HPI# SCL0, SCD0, SCL1, SCD1 GPIO[3:0]/ U0_RTS#, U0_CTS#, U0_TXD, U0_RXD, GPIO[7:4]/ U1_RTS#, U1_CTS#, U1_TXD, U1_RXD TCK TDI TDO (4) Reset Lind VI VB VI VI VI H H H VI AO AO Z VI VI H VI Reset Lind nobrg VI VB VI VI H H H H VSS AO AO Z (3) ID VI H VI Norm Lind VI VB VI VI VI VO VO VO VI AO AO Z/0 VI VI VB VB Norm Lind nobrg VI VB VI H H H VO VO VSS AO AO Z (3) ID VI VB VB ECC off DDR - 32Bit DDR - 32Bit P_PCI - 32Bit S_PCI - VI VI VB VB - - - - VI H VO* H H VI H VI H VO* H H VI H VI H VO H H VI H VI H VO H H VI H - - - - TRST# TMS PWRDELAY NC[3:0] NOTES: 1 = driven to VCC 0 = driven to VSS X = driven to unknown state ID = The input is disabled. H = pulled up to VCC PD = pull-up disabled L = pulled down to VSS 1. 2. 3. 4. Z = output disabled (Floats) VB = acts like a Valid Bidirectional pin. VO = a Valid Output level is driven. VI = Need to drive a Valid Input level. * = After power fail sequence completes. ** = Caused by Hi-Z from mode pins only. AO = analog output level. Clocks become valid right before M_RST# deasserts. ODT signal to be low during power up and initialization per DDRII JEDEC specification. P_INT[A]# is the only active ouput in 80331 no bridge mode. Test inputs pulled up as noted in signal description table Table 11, “Test and Miscellaneous Signals” on page 26 and test outputs tristated during normal functional operation. 32 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 15. Pin Multiplexing for Functional Modes Pin A[20] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] A[2] A[1] A[0] S_REQ[3]# S_REQ[1]# S_GNT[1]# S_GNT[0]# S_CLKIN Bridge Disabled P_IDSEL P_GNT# P_REQ# P_BMI P_CLK Reset Straps PCIODT_EN RETRY CORE_RST# P_BOOT16# S_PCIX133EN MEM_TYPE ARB_EN BRG_EN P_32BITPCI# PRIVMEM PRIVDEV - Document Number: 273943-004US August 2005 33 Intel® 80331 I/O Processor Datasheet Package Information Figure 2. 829-Ball FCBGA Package Diagram S1 S2 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A E F1 F2 D Die Laser Mark Pin #1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 e øb Top View Bottom View A3 A Seating Plane A1 C Side View B1230-02 Table 16. FC-style, H-PBGA Package Dimensions 829-Pin BGA Symbol A A1 A3 b C D E F1 F2 e S1 S2 NOTE: Measurement in millimeters. 1.15 37.45 37.45 9.88 Ref. 10.16 Ref. 1.27 Ref. 0.97 Ref. 0.97 Ref. Minimum 2.392 0.50 0.742 0.61 Ref. 1.37 37.55 37.55 Maximum 2.942 0.70 0.872 34 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Figure 3. Intel® 80331 I/O Processor Ballout (Bottom View) 1 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 AJ AH AG DDRII/SDRAM JTAG GPIO PBI AF AE AD AC AB AA Y W V U T VCC/VSS R P N M L K J H Primary PCI-X Bus Secondary PCI-X Bus G F E D C B A B1210-01 Document Number: 273943-004US August 2005 35 Intel® 80331 I/O Processor Datasheet Package Information Figure 4. Intel® 80331 I/O Processor Ballout - Left Side (Bottom View) 1 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A NB 2 NB 3 VCC 25/18 4 DQS1# 5 DQS1 6 DQ15 7 DQ10 8 DQ17 9 DM2 10 MA8 11 DQ28 12 DQ25 13 DM3 14 M_CK1 15 M_ CK1# NB VSS M_RST# CKE1 VSS DQ14 DQ20 VSS MA6 MA5 VCC 25/18 DQ24 DQS3# VSS DM8 VSS DQ3 VSS CKE0 DM1 VSS DQ11 DQ16 VSS DQ18 MA4 VSS DQS3 DQ31 VSS DQ6 DQ7 DQ2 VCC 25/18 MA12 DQ9 VSS DQ21 DQS2 VCC 25/18 MA3 DQ29 VCC 25/18 DQ30 CB1 DM0 VSS DQS0# DQS0 VSS DQ13 DQ8 VSS DQS2# DQ23 VSS MA1 DQ26 VSS CB0 DQ5 DQ4 VSS DQ1 DQ0 VCC 25/18 MA7 DQ12 VSS DQ22 DQ19 VCC 25/18 BA1 DQ27 VSS DDR_ VREF VSS VSS VSS VSS VSS VSS MA11 MA9 VCC 25/18 VSS MA2 MA0 CB5 CB4 N/C VSS TDO TMS VSS VSS VCC 25/18 P_ RST# VSS VCC 25/18 VSS VCC 25/18 VSS VCC 25/18 VSS VCC 25/18 N/C N/C VSS N/C TRST# VSS HPI# VSS VCC 25/18 VSS VCC 25/18 VSS VCC 25/18 VSS VCC15 TCK VSS VSS N/C TDI VSS N/C VCC13 VSS VCC13 VSS VCC13 VSS VCC15 PWR DELAY P_ RCOMP P_ C/BE4# VSS P_ INTA# VSS VCC33 N/C N/C N/C VSS VCC13 VSS VCC13 VSS VCC15 VSS P_ INTD# P_ C/BE5# VCC33 P_ INTC# P_ INTB# VSS N/C N/C VCC15 VSS VCC15 VSS VCC13 VSS VCC15 P_ C/BE7# P_ C/BE6# VSS N/C N/C VCC33 N/C VSS VCC15 VSS VCC13 VSS VCC15 VSS N/C VSS N/C VSS N/C VSS N/C VCC15 VSS VCC15 VSS VCC15 VSS VCC15 P_ AD63 P_ AD60 P_ AD59 P_ AD56 P_ AD53 P_ AD50 P_ AD49 P_ AD0 P_ AD3 P_ AD6 P_ C/BE0# P_ AD10 P_ PAR64 VCC33 N/C P_ AD45 VCC33 P_ AD46 P_ AD43 P_ AD47 P_ AD42 P_ AD39 P_ AD36 P_ AD33 P_ AD32 VSS VCC15 VSS VCC15 VSS VCC15 VCC PLL4 VSS P_ AD61 P_ AD57 P_ AD62 VSS P_ AD44 P_ AD40 VCC15 VSS VCC15 VSS VCC PLL5 VSSA5 VCC15 P_ AD58 P_ AD55 VSS P_ AD41 P_ AD38 VSS VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC33 P_ AD54 P_ AD51 VCC33 P_ AD37 P_ AD34 VCC15 VSS VCC PLL2 VSSA2 VCC15 VSS VCC15 VSS P_ AD52 P_ IDSEL VCC33 P_ AD35 VSS VCC15 VSS VCC15 VSS VSS VSS N/C VSS N/C N/C VSS VCC15 VCC15 VCC15 VSS VCC15 VSS VSS P_ AD48 VCC33 P_ PERR# P_ AD2 P_ SERR# VSS PU1 N/C VSS VCC15 VSS VCC15 VSS VCC15 VSS VSS P_ AD1 P_ AD5 VCC33 P_ ACK64# N/C N/C N/C P_ TRDY# P_ REQ# N/C N/C VSS VCC15 P_ AD4 P_ AD7 VSS P_ P_ DEVSEL# STOP# P_ IRDY# VSS VSS P_ CLK VCC33 P_ P_GNT# REQ64# VSS N/C VSS VCC33 P_ AD8 P_ AD9 VCC33 N/C VSS VSS VSS N/C VSS N/C N/C VSS VSS P_ M66EN P_ AD12 P_ AD14 P_ AD15 VSS P_ FRAME# P_ AD19 N/C VSS VCC33 VSS VSS N/C N/C VCC15 N/C P_ AD11 P_ AD13 VCC33 P_ C/BE2# P_ AD17 VSS P_ AD24 P_ AD25 P_ AD27 VSS N/C N/C VSS N/C N/C VCC33 P_ PAR P_ C/BE1# P_ AD16 VCC33 P_ AD22 P_ AD23 P_ C/BE3# VCC33 P_ AD30 P_ AD31 N/C N/C VCC15 N/C VSS NB VSS VSS P_ AD20 P_ AD21 VSS P_ AD28 P_ AD29 VSS N/C VSS VSS VSS NB NB VSS P_ AD18 P_ AD26 VSS N/C N/C VCC15 VSS VCC15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B3969-01 36 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Figure 5. Intel® 80331 I/O Processor Ballout - Right Side (Bottom View) 16 M_CK0 17 M_CK0# 18 DQ36 19 DM4 20 DQ38 21 DQ35 22 DQ40 23 DQS5# 24 DQ46 25 DQS6# 26 DQS6 27 VSS 28 NB 29 NB AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A VCC 25/18 M_CK2 DQ37 VSS DQ39 DQ44 VSS DQS5 DQ47 VSS DQ54 DQ55 VSS NB DQS8 M_CK2# VSS DQS4# DQ34 VSS DQ41 DQ42 VSS DM6 DQ50 DQ51 DQ60 VSS DQS8# VCC 25/18 DQ32 DQS4 VCC 25/18 DQ45 VCC 25/18 DQ43 DQ48 DQ49 VCC 25/18 DQ61 DQ56 DQS7# VSS CB7 DQ33 VSS CS0# DM5 VSS DQ53 DQ52 VSS DQ57 DM7 VSS DQS7 CB6 CB2 BA0 VCC 25/18 WE# VSS MA13 CS1# VCC 25/18 DQ62 DQ63 VSS DQ59 DQ58 CB3 VSS MA10 RAS# VCC 25/18 CAS# ODT0 VSS SCD1 GPIO5/ GPIO4/ U1_TXD U1_RXD DDR DDRSLW DDRIMP CRES0 CRES CRES DDR RES1 DDR RES2 VSS VCC 25/18 VSS VCC 25/18 ODT1 SCD0 SCL1 GPIO6/ GPIO7/ U1_CTS# U1_RTS# VSS GPIO0/ GPIO1/ U0_RXD U0_TXD VCC 25/18 VSS VCC 25/18 VSS VCC 25/18 GPIO2/ GPIO3/ U0_CTS# U0_RTS# SCL0 VCC33 PCE1# PCE0# VSS ALE A1 VSS VCC15 VSS VCC15 VSS PWE# AD15 VSS AD11 A0 VCC33 A17 A21 A20 VCC15 VSS VCC15 VSS VCC33 A2 A22 AD7 AD2 VSS AD8 AD9 VSS A16 VSS VCC15 VSS VCC15 VSS POE# A19 AD3 VCC33 AD13 AD5 VSS AD1 AD0 VCC15 VSS VCC15 VSS VCC33 A18 AD14 VSS AD12 S_ GNT3# VCC33 S_ INTA# S_ AD50 S_ INTB# S_ AD48 S_ RCOMP S_ AD53 S_ AD56 S_ AD58 S_ AD60 S_ AD63 S_ PAR64 VSS VCC15 VSS VCC15 VSS AD10 AD6 AD4 S_ INTC# VSS S_ AD49 S_ AD51 S_ AD54 VSS VSSA4 VSS VCC15 VSS S_ S_RST# VCC33 PCIXCAP S_ GNT2# S_ AD35 S_ AD38 S_ AD41 S_ AD42 S_ AD47 S_ AD3 S_ AD4 S_ AD5 S_ INTD# S_ AD32 VCC33 N/C VCC33 S_ AD52 VSS VCC15 VSS VCC15 VSS VCC33 S_ AD33 S_ AD34 VSS S_ AD55 S_ AD59 VSS VCC15 VSS VCC15 VSS VCC33 VSS VCC33 S_ REQ0# S_ AD36 VCC33 S_ AD57 S_ AD61 VSS VCC15 VSSA1 VCC PLL1 VSS VCC33 S_ AD37 S_ AD39 VSS S_ AD62 S_ C/BE6# VCC33 VSS VSS VCC15 VSS VCC33 VSS S_ AD40 S_ AD43 VCC33 S_ C/BE7# S_ C/BE4# VSS VSS VCC33 VSS VCC33 VSS VCC33 VSS S_ REQ3# S_ AD45 VSS S_ C/BE5# VCC15 VSS VCC33 VSS VCC33 VSS S_ AD46 S_ CLKO3 VCC33 S_ AD44 VCC33 S_ S_ ACK64# REQ64# VSS S_ C/BE1# S_ AD14 S_ AD15 S_ AD11 S_ AD12 S_ AD13 S_ C/BE0# S_ AD6 S_ AD7 S_ CLKO0 S_ CLKO1 VSS VCC33 VSS VSS VSS N/C VSS VSS VCC33 S_ CLKOUT S_ CLKO2 VSS S_ CLKIN VSS S_ PERR# N/C N/C VSS S_ AD9 S_ AD10 VCC33 S_ AD1 S_ AD2 VSS S_PAR VSS S_ S_ REQ1# DEVSEL# S_ TRDY# S_ STOP# S_ FRAME# S_ IRDY# VCC15 N/C N/C VSS S_ REQ2# S_ AD8 VSS S_ AD0 S_ AD23 VSS S_ SERR# PU2 N/C VSS N/C N/C VSS S_ AD27 S_ AD28 VSS S_ AD20 S_ AD21 VCC33 S_ C/BE3# S_ C/BE2# S_ AD16 VSS N/C N/C VCC15 N/C S_ M66EN VCC33 S_ AD25 S_ AD26 S_ GNT0# VCC33 S_ AD17 S_ AD18 S_ AD19 VCC33 VSS N/C N/C VSS VSS S_ AD30 S_ AD31 VSS S_ GNT1# S_ AD24 VSS VSS NB VSS VSS N/C N/C N/C S_ AD29 S_ AD22 VSS NB NB 16 17 18 19 20 21 22 23 24 25 26 27 28 29 B3970-01 Document Number: 273943-004US August 2005 37 Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet 1 of 7) Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 Signal --VSS P_AD16 P_AD18 P_AD21 P_C/BE3# P_AD26 P_AD29 VSS N/C N/C VCC15 VSS VCC15 VSS VSS N/C N/C N/C S_AD31 S_AD29 S_GNT0# S_AD24 S_AD22 S_AD19 VSS ---VSS P_AD15 P_C/BE1# VSS P_AD20 P_AD23 VSS P_AD28 P_AD31 VSS N/C Ball B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 Signal VSS VSS VSS VSS N/C N/C VSS VSS S_AD30 VSS S_AD26 S_GNT1# VSS S_AD18 S_AD16 VSS -VCC33 P_AD13 P_AD14 P_PAR P_AD17 VCC33 P_AD22 P_AD25 VCC33 P_AD30 N/C N/C VCC15 N/C VSS N/C N/C VCC15 N/C S_M66EN VCC33 S_AD28 S_AD25 VCC33 Ball C25 C26 C27 C28 C29 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 E1 E2 E3 E4 E5 E6 E7 Signal S_AD21 S_AD17 S_C/BE2# S_FRAME# VCC33 P_AD10 P_AD11 P_AD12 VCC33 P_C/BE2# P_AD19 VSS P_AD24 P_AD27 VSS N/C N/C VSS N/C N/C N/C VSS N/C N/C VSS S_AD8 S_AD27 VSS S_AD23 S_AD20 VCC33 S_C/BE3# S_STOP# VSS P_C/BE0# VSS P_M66EN P_AD9 VSS P_FRAME# N/C 38 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet 2 of 7) Ball E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 Signal VSS VCC33 VSS VSS N/C N/C VCC15 N/C VCC15 N/C N/C VSS S_AD10 S_REQ2# VSS S_AD2 S_AD0 VSS S_SERR# PU2 S_TRDY# S_IRDY# P_AD6 P_AD7 VCC33 P_AD8 P_IRDY# VCC33 N/C VSS VSS VSS N/C VSS N/C N/C VSS N/C N/C VSS S_AD13 Ball F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 H1 H2 Signal S_AD9 VCC33 S_AD5 S_AD1 VSS S_CLKO2 S_PAR VSS S_REQ1# S_DEVSEL# P_AD3 P_AD4 P_AD5 VSS P_DEVSEL# P_STOP# VSS VSS P_CLK VCC33 P_REQ64# P_GNT# VSS N/C VSS N/C VSS S_AD15 S_AD12 VSS S_AD7 S_AD4 VCC33 S_CLKO1 S_CLKOUT VSS S_CLKIN VSS S_PERR# P_AD0 VSS Ball H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 Signal P_AD1 P_AD2 VCC33 P_ACK64# N/C N/C N/C P_TRDY# P_REQ# N/C N/C VSS VCC15 VSS S_C/BE1# S_AD14 S_AD11 S_C/BE0# S_AD6 S_AD3 S_CLKO3 S_CLKO0 VSS VCC33 VSS VSS VSS P_AD49 P_AD48 VCC33 P_PERR# P_SERR# VSS PU1 N/C VSS VCC15 VSS VCC15 VSS VCC15 Document Number: 273943-004US August 2005 39 Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet 3 of 7) Ball J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 Signal VSS VCC15 VSS VCC33 VSS VCC33 VSS S_AD47 S_AD46 VCC33 S_AD45 S_AD44 VCC33 S_ACK64# S_REQ64# P_AD50 N/C P_IDSEL VSS N/C N/C VSS P_AD32 VCC15 VCC15 VCC15 VSS VCC15 VSS VSS VSS VCC33 VSS VCC33 VSS VCC33 S_AD42 VSS S_AD43 S_REQ3# VSS Ball K27 K28 K29 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 M1 M2 M3 M4 M5 M6 M7 M8 M9 Signal S_C/BE4# S_C/BE5# S_PAR64 P_AD53 VSS P_AD52 P_AD51 VCC33 P_AD35 P_AD34 P_AD33 VSS VCC15 VSS VCC15 VSS VSS VSS VSS VSS VCC15 VSS VCC33 VSS S_AD41 S_AD39 S_AD40 VCC33 S_C/BE6# S_C/BE7# VSS S_AD63 P_AD56 P_AD55 VCC33 P_AD54 P_AD38 VCC33 P_AD37 P_AD36 VCC15 Ball M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 Signal VSS VCCPLL2 VSSA2 VCC15 VSS VCC15 VSS VCC15 VSSA1 VCCPLL1 VSS VCC33 S_AD38 S_AD37 VSS S_AD36 S_AD62 VCC33 S_AD61 S_AD60 P_AD59 P_AD58 P_AD57 VSS P_AD41 P_AD40 VSS P_AD39 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC33 VSS 40 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet 4 of 7) Ball N22 N23 N24 N25 N26 N27 N28 N29 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 R1 R2 R3 R4 Signal S_AD35 VCC33 S_AD34 S_REQ0# VCC33 S_AD59 S_AD57 S_AD58 P_AD60 VSS P_AD61 P_AD62 VSS P_AD44 P_AD43 P_AD42 VCC15 VSS VCC15 VSS VCCPLL5 VSSA5 VCC15 VSS VCC15 VSS VCC15 VSS VCC33 S_GNT2# S_AD32 S_AD33 VSS S_AD54 S_AD55 VSS S_AD56 P_AD63 P_PAR64 VCC33 N/C Ball R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Signal P_AD45 VCC33 P_AD46 P_AD47 VSS VCC15 VSS VCC15 VSS VCC15 VCCPLL4 VSSA4 VSS VCC15 VSS VCC33 S_PCIXCAP S_RST# S_INTD# VCC33 N/C S_AD51 VCC33 S_AD52 S_AD53 N/C VSS P_C/BE6# N/C VSS N/C VSS N/C VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VSS Ball T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 Signal VCC15 VSS VCC15 VSS AD10 AD6 AD4 S_INTC# VSS S_AD49 S_AD50 VSS S_RCOMP P_C/BE4# P_C/BE5# P_C/BE7# VSS N/C N/C VCC33 N/C VSS VCC15 VSS VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC33 A18 AD14 VSS AD12 S_GNT3# VCC33 S_INTA# S_INTB# Document Number: 273943-004US August 2005 41 Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet 5 of 7) Ball U29 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 Signal S_AD48 P_RCOMP P_INTD# VCC33 P_INTC# P_INTB# VSS N/C N/C VCC15 VSS VCC15 VSS VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS POE# A19 AD3 VCC33 AD13 AD5 VSS AD1 AD0 PWRDELAY VSS P_INTA# VSS VCC33 N/C N/C N/C VSS VCC13 VSS Ball W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Signal VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC33 A2 A22 AD7 AD2 VSS AD8 AD9 VSS A16 VCC15 TCK VSS VSS N/C TDI VSS N/C VCC13 VSS VCC13 VSS VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS PWE# AD15 VSS Ball Y24 Y25 Y26 Y27 Y28 Y29 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AB1 AB2 AB3 AB4 AB5 AB6 Signal AD11 A0 VCC33 A17 A21 A20 N/C N/C VSS N/C TRST# VSS P_RST# HPI# VSS VCC25/18 VSS VCC25/18 VSS VCC25/18 VSS VCC25/18 VSS VCC25/18 VSS VCC25/18 GPIO2/U0_CTS# GPIO3/U0_RTS# SCL0 VCC33 PCE1# PCE0# VSS ALE A1 N/C VSS TDO TMS VSS VSS 42 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet 6 of 7) Ball AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 Signal VCC25/18 VSS VCC25/18 VSS VCC25/18 VSS VCC25/18 VSS VCC25/18 VSS VCC25/18 VSS VCC25/18 ODT1 SCD0 SCL1 GPIO6/U1_CTS# GPIO7/U1_RTS# VSS GPIO0/U0_RXD GPIO1/U0_TXD DDRRES1 DDRRES2 DDR_VREF VSS VSS VSS VSS VSS VSS MA11 MA9 VCC25/18 VSS MA2 MA0 CB5 CB4 CB3 VSS MA10 Ball AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AE1 Signal RAS# VCC25/18 CAS# ODT0 VSS SCD1 GPIO5/U1_TXD GPIO4/U1_RXD DDRCRES0 DDRSLWCRES DDRIMPCRES DQ5 DQ4 VSS DQ1 DQ0 VCC25/18 MA7 DQ12 VSS DQ22 DQ19 VCC25/18 BA1 DQ27 VSS CB6 CB2 BA0 VCC25/18 WE# VSS MA13 CS1# VCC25/18 DQ62 DQ63 VSS DQ59 DQ58 DM0 Ball AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 Signal VSS DQS0# DQS0 VSS DQ13 DQ8 VSS DQS2# DQ23 VSS MA1 DQ26 VSS CB0 VSS CB7 DQ33 VSS CS0# DM5 VSS DQ53 DQ52 VSS DQ57 DM7 VSS DQS7 DQ6 DQ7 DQ2 VCC25/18 MA12 DQ9 VSS DQ21 DQS2 VCC25/18 MA3 DQ29 VCC25/18 Document Number: 273943-004US August 2005 43 Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet 7 of 7) Ball AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 Signal DQ30 CB1 DQS8# VCC25/18 DQ32 DQS4 VCC25/18 DQ45 VCC25/18 DQ43 DQ48 DQ49 VCC25/18 DQ61 DQ56 DQS7# VSS DQ3 VSS CKE0 DM1 VSS DQ11 DQ16 VSS DQ18 MA4 VSS DQS3 DQ31 VSS DQS8 M_CK2# VSS DQS4# DQ34 VSS DQ41 DQ42 VSS DM6 Ball AG26 AG27 AG28 AG29 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 Signal DQ50 DQ51 DQ60 VSS -VSS M_RST# CKE1 VSS DQ14 DQ20 VSS MA6 MA5 VCC25/18 DQ24 DQS3# VSS DM8 VCC25/18 M_CK2 DQ37 VSS DQ39 DQ44 VSS DQS5 DQ47 VSS DQ54 DQ55 VSS ---VCC25/18 DQS1# DQS1 DQ15 DQ10 DQ17 Ball AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 Signal DM2 MA8 DQ28 DQ25 DM3 M_CK1 M_CK1# M_CK0 M_CK0# DQ36 DM4 DQ38 DQ35 DQ40 DQS5# DQ46 DQS6# DQS6 VSS --- 44 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet 1 of 7) Signal ------------A0 A1 A16 A17 A18 A19 A2 A20 A21 A22 AD0 AD1 AD10 AD11 AD12 AD13 AD14 AD15 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 ALE BA0 BA1 Ball A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 Y25 AA29 W29 Y27 U21 V22 W21 Y29 Y28 W22 V29 V28 T21 Y24 U24 V25 U22 Y22 W24 V23 T23 V26 T22 W23 W26 W27 AA28 AD18 AD13 Signal CAS# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CKE0 CKE1 CS0# CS1# DDR_VREF DDRCRES0 DDRIMPCRES DDRRES1 DDRRES2 DDRSLWCRES DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DQ0 DQ1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ2 Ball AC21 AE15 AF15 AD17 AC16 AC15 AC14 AD16 AE17 AG4 AH4 AE20 AD23 AC1 AC27 AC29 AB28 AB29 AC28 AE1 AG5 AJ9 AJ13 AJ19 AE21 AG25 AE27 AH15 AD5 AD4 AJ7 AG7 AD8 AE6 AH6 AJ6 AG8 AJ8 AG10 AD11 AF3 Signal DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ3 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ4 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ5 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 Ball AH7 AF8 AD10 AE10 AH12 AJ12 AE13 AD14 AJ11 AF12 AG2 AF14 AG14 AF18 AE18 AG20 AJ21 AJ18 AH18 AJ20 AH20 AD2 AJ22 AG22 AG23 AF23 AH21 AF21 AJ24 AH24 AF24 AF25 AD1 AG26 AG27 AE24 AE23 AH26 AH27 AF28 AE26 Document Number: 273943-004US August 2005 45 Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet 2 of 7) Signal DQ58 DQ59 DQ6 DQ60 DQ61 DQ62 DQ63 DQ7 DQ8 DQ9 DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3# DQS4 DQS4# DQS5 DQS5# DQS6 DQS6# DQS7 DQS7# DQS8 DQS8# GPIO0/U0_RXD GPIO1/U0_TXD GPIO2/U0_CTS# GPIO3/U0_RTS# GPIO4/U1_RXD GPIO5/U1_TXD GPIO6/U1_CTS# GPIO7/U1_RTS# HPI# M_CK0 M_CK0# M_CK1 M_CK1# Ball AD29 AD28 AF1 AG28 AF27 AD25 AD26 AF2 AE7 AF6 AE4 AE3 AJ5 AJ4 AF9 AE9 AG13 AH13 AF19 AG19 AH23 AJ23 AJ26 AJ25 AE29 AF29 AG16 AF16 AB26 AB27 AA21 AA22 AC26 AC25 AB23 AB24 AA8 AJ16 AJ17 AJ14 AJ15 Signal M_CK2 M_CK2# M_RST# MA0 MA1 MA10 MA11 MA12 MA13 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C Ball AH17 AG17 AH3 AC13 AE12 AC18 AC8 AF5 AD22 AC12 AF11 AG11 AH10 AH9 AD7 AJ10 AC9 A11 A12 A18 A19 A20 AA1 AA2 AA4 AB1 B12 B17 B18 C11 C12 C14 C16 C17 C19 D11 D12 D14 D15 D16 D18 Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C P_GNT# N/C N/C P_REQ# N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C ODT0 Ball D19 E12 E13 E15 E17 E18 E7 F11 F13 F14 F16 F17 F7 G12 G14 G16 H11 H12 H13 H7 H8 H9 J8 K2 K5 K6 R25 T1 T4 T8 U5 U6 U8 V7 V8 W6 W7 W8 Y5 Y8 AC22 46 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet 3 of 7) Signal ODT1 P_ACK64# P_AD0 P_AD1 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD2 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD3 P_AD30 P_AD31 P_AD32 P_AD33 P_AD34 P_AD35 P_AD36 P_AD37 P_AD38 P_AD39 P_AD4 P_AD40 P_AD41 P_AD42 P_AD43 Ball AB20 H6 H1 H3 D1 D2 D3 C2 C3 B3 A4 C5 A5 D6 H4 B6 A6 C7 B7 D8 C8 A8 D9 B9 A9 G1 C10 B10 K8 L8 L7 L6 M8 M7 M5 N8 G2 N6 N5 P8 P7 Signal P_AD45 P_AD46 P_AD47 P_AD48 P_AD49 P_AD5 P_AD50 P_AD51 P_AD52 P_AD53 P_AD54 P_AD55 P_AD56 P_AD57 P_AD58 P_AD59 P_AD6 P_AD60 P_AD61 P_AD62 P_AD63 P_AD7 P_AD8 P_AD9 P_C/BE0# P_C/BE1# P_C/BE2# P_C/BE3# P_C/BE4# P_C/BE5# P_C/BE6# P_C/BE7# P_CLK P_DEVSEL# P_FRAME# N/C P_IDSEL P_INTA# P_INTB# P_INTC# P_AD45 Ball R5 R7 R8 J2 J1 G3 K1 L4 L3 L1 M4 M2 M1 N3 N2 N1 F1 P1 P3 P4 R1 F2 F4 E4 E1 B4 D5 A7 U1 U2 T3 U3 G9 G5 E6 R4 K3 W3 V5 V4 R5 Signal P_INTD# P_IRDY# PU1 P_M66EN P_PAR P_PAR64 P_PERR# P_RCOMP N/C P_REQ64# P_RST# P_SERR# P_STOP# P_TRDY# PCE0# PCE1# POE# PWE# PWRDELAY RAS# S_ACK64# S_AD0 S_AD1 S_AD10 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15 S_AD16 S_AD17 S_AD18 S_AD19 S_AD2 S_AD20 S_AD21 S_AD22 S_AD23 S_AD24 S_AD25 S_AD26 Ball V2 F5 J7 E3 C4 R2 J4 V1 T6 G11 AA7 J5 G6 H10 AA26 AA25 V21 Y21 W1 AC19 J28 E24 F23 E20 H19 G19 F19 H18 G18 B27 C26 B26 A26 E23 D25 C25 A25 D24 A24 C23 B23 Document Number: 273943-004US August 2005 47 Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet 4 of 7) Signal S_AD27 S_AD28 S_AD29 S_AD3 S_AD30 S_AD31 S_AD32 S_AD33 S_AD34 S_AD35 S_AD36 S_AD37 S_AD38 S_AD39 S_AD4 S_AD40 S_AD41 S_AD42 S_AD43 S_AD44 S_AD45 S_AD46 S_AD47 S_AD48 S_AD49 S_AD5 S_AD50 S_AD51 S_AD52 S_AD53 S_AD54 S_AD55 S_AD56 S_AD57 S_AD58 S_AD59 S_AD6 S_AD60 S_AD61 S_AD62 S_AD63 Ball D22 C22 A22 H22 B21 A21 P23 P24 N24 N22 M25 M23 M22 L23 G22 L24 L22 K22 K24 J26 J25 J23 J22 U29 T26 F22 T27 R26 R28 R29 P26 P27 P29 N28 N29 N27 H21 M29 M28 M26 L29 Signal S_AD7 S_AD8 S_AD9 S_C/BE0# S_C/BE1# S_C/BE2# S_C/BE3# S_C/BE4# S_C/BE5# S_C/BE6# S_C/BE7# S_CLKIN S_CLKO0 S_CLKO1 S_CLKO2 S_CLKO3 S_CLKOUT S_DEVSEL# S_FRAME# S_GNT0# S_GNT1# S_GNT2# S_GNT3# S_INTA# S_INTB# S_INTC# S_INTD# S_IRDY# PU2 S_M66EN S_PAR S_PAR64 S_PCIXCAP S_PERR# S_RCOMP S_REQ0# S_REQ1# S_REQ2# S_REQ3# S_REQ64# S_RST# Ball G21 D21 F20 H20 H17 C27 D27 K27 K28 L26 L27 G27 H24 G24 F25 H23 G25 F29 C28 A23 B24 P22 U25 U27 U28 T24 R23 E29 E27 C20 F26 K29 R21 G29 T29 N25 F28 E21 K25 J29 R22 Signal S_SERR# S_STOP# S_TRDY# SCD0 SCD1 SCL0 SCL1 TCK TDI TDO TMS TRST# VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 Ball E26 D28 E28 AB21 AC24 AA23 AB22 Y2 Y6 AB3 AB4 AA5 U12 V13 W10 W12 Y11 Y13 Y9 A13 A15 C13 C18 E14 E16 H15 J10 J12 J14 J16 K10 K11 K13 K9 L10 L12 L18 M13 M15 M17 M9 48 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet 5 of 7) Signal VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 Ball N10 N12 N14 N16 N18 P11 P15 P17 P19 P9 R10 R12 R14 R18 T11 T13 T15 T17 T19 T9 U10 U14 U16 U18 V11 V15 V17 V19 V9 W14 W16 W18 Y1 Y15 Y17 Y19 AA10 AA12 AA14 AA16 AA18 Signal VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 Ball AA20 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC20 AD12 AD19 AD24 AD6 AF10 AF13 AF17 AF20 AF22 AF26 AF4 AH11 AH16 AJ3 AA24 C1 C21 C24 C29 C6 C9 D26 D4 E9 F21 F3 F6 G10 G23 H26 H5 Signal VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCCPLL1 VCCPLL2 VCCPLL4 VCCPLL5 VSS VSS VSS VSS VSS Ball J18 J20 J24 J27 J3 K17 K19 K21 L20 L25 L5 M21 M27 M3 M6 N20 N23 N26 P21 R20 R24 R27 R3 R6 U20 U26 U7 V24 V3 W20 W5 Y26 M19 M11 R15 P13 A10 A14 A16 A17 A27 Document Number: 273943-004US August 2005 49 Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet 6 of 7) Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball A3 AA11 AA13 AA15 AA17 AA19 AA27 AA3 AA6 AA9 AB10 AB12 AB14 AB16 AB18 AB2 AB25 AB5 AB6 AB8 AC11 AC17 AC2 AC23 AC3 AC4 AC5 AC6 AC7 AD15 AD21 AD27 AD3 AD9 AE11 AE14 AE16 AE19 AE2 AE22 AE25 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball AE28 AE5 AE8 AF7 AG1 AG12 AG15 AG18 AG21 AG24 AG29 AG3 AG6 AG9 AH14 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ27 B11 B13 B14 B15 B16 B19 B2 B20 B22 B25 B28 B5 B8 C15 D10 D13 D17 D20 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball D23 D29 D7 E10 E11 E19 E2 E22 E25 E5 E8 F10 F12 F15 F18 F24 F27 F8 F9 G13 G15 G17 G20 G26 G28 G4 G7 G8 H14 H16 H2 H25 H27 H28 H29 J11 J13 J15 J17 J19 J21 50 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet 7 of 7) Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball J6 J9 K12 K14 K15 K16 K18 K20 K23 K26 K4 K7 L11 L13 L14 L15 L16 L17 L19 L2 L21 L28 L9 M10 M14 M16 M20 M24 N11 N13 N15 N17 N19 N21 N4 N7 N9 P10 P12 P16 P18 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball P2 P20 P25 P28 P5 R11 R13 R17 R19 R9 T10 T12 T14 T16 T18 T2 T20 T25 T28 T5 T7 U11 U13 U15 U17 U19 U23 U4 U9 V10 V12 V14 V16 V18 V20 V27 V6 W11 W13 W15 W17 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA1 VSSA2 VSSA4 VSSA5 WE# Ball W19 W2 W25 W28 W4 W9 Y10 Y12 Y14 Y16 Y18 Y20 Y23 Y3 Y4 Y7 M18 M12 R16 P14 AD20 Document Number: 273943-004US August 2005 51 Intel® 80331 I/O Processor Datasheet Package Information 3.2 Package Thermal Specifications See Intel® 80331 I/O Processor Thermal Design Guidelines Application Note (273980). 52 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.0 4.1 Table 19. Electrical Specifications Absolute Maximum Ratings Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Under Bias Supply Voltage VCC33 wrt. VSS Supply Voltage VCC25 wrt. VSS Supply Voltage VCC15 wrt. VSS Supply Voltage VCC13 wrt. VSS Voltage on Any Ball wrt. VSS Maximum Rating –55° C to +125°C 0°C to +95°C –0.5 V to +4.1 V –0.5 V to +3.2 V –0.5 V to +2.1 V –0.5 V to +2.1 V –0.5 V to VCCP + 0.5 V NOTE: This data sheet contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available. The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design. WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability. Table 20. Operating Conditions Symbol VCC33 VCC25/18 VCC15 VCC13 VCCPLL1-5 DDR_VREF P_CLK Parameter 3.3 V PCI/PCI-X Supply Voltage 2.5 V/1.8V DDR/DDR-II Supply Voltage 1.5 V IOP Core Supply Voltage 1.35 V Intel XScale® core Supply Voltage PLL Supply Voltage Memory I/O Reference Voltage Input Clock Frequency Case Temperature Under Bias Minimum 3.0 2.3/1.7 1.425 1.282 VCC15 0.49VCC25/18 16 0 Maximum 3.6 2.7/1.9 1.575 1.418 VCC15 0.51 VCC25/18 133 95 Units V V V V V V MHz °C Notes +/- 10% +/-8%, 5%1 +/- 5%1 +/- 5% TC 1. +/- 3% DC; additional +/- 2% for AC transients. Under no circumstance may the supply voltage go past the AC min/max window. The supply voltage window may go outside the DC min/max window for transient events. 4.2 VCCPLL Pin Requirements The VCCPLL[1-5] balls for the Phase Lock Loop (PLL) circuit must each have filters, and be connected to the appropriate VSSA ball. See the Intel® 80331 I/O Processor Design Guide for specific recommendations. NOTE: There are no VCCPLL3 or VSSA3 signals. Document Number: 273943-004US August 2005 53 Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.3 Table 21. Symbol VIL1 VIH1 VIL2 VIH2 VIL2 VIH2 VIL3 VIH3 VIL5 VOL2 VOH2 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 CIN CCLK LPIN Targeted DC Specifications DC Characteristics Parameter Input Low Voltage (DDR SDRAM) Input High Voltage (DDR SDRAM) Input Low Voltage (DDR-II SDRAM) Input High Voltage (DDR-II SDRAM) Input Low Voltage (Misc.) Input High Voltage (Misc.) Input Low Voltage (PCI-X) Input High Voltage (PCI-X/PCI) Input Low Voltage (PCI) Output Low Voltage (Misc.) Output High Voltage (Misc.) Output Low Voltage (DDR SDRAM) Output High Voltage (DDR SDRAM) Output Low Voltage (DDR-II SDRAM) Output High Voltage (DDR-II SDRAM) Output Low Voltage (PCI-X) Output High Voltage (PCI-X) Input pin Capacitance PCI clock pin Capacitance Ball Inductance 0.9 VCC33 8 8 15 1.314 0.1 VCC33 1.95 0.414 2.4 0.35 Minimum -0.3 DDR_VREF + 0.18 -0.2 DDR_VREF + 0.125 -0.3 2.0 -0.5 0.5 VCC33 -0.5 Maximum DDR_VREF - 0.18 VCC25 + 0.3 DDR_VREF - 0.125 VCC25 + 0.2 0.8 VCC33 + 0.3 0.35 VCC33 VCC33 + 0.5 0.3 VCC33 0.4 Units V V V V V V V V V V V V V V V V V pF pF nH IOL = 6 mA IOH = -2 mA IOL = 12.5 mA (1, 2) IOH = -12.5 mA (1, 2) IOL = 20.7mA (3) IOH = -18mA (3) IOL = 1500 µA IOH = -500 µA (5) (5) (1, 2, 5) Notes (1, 2) (1, 2) (1, 3) (1, 3) (4) (4) NOTES: 1. SDRAM signals include MA[12:0], BA[1:0], CAS#, CS[1:0]#, CKE[1:0], DM[8:0], RAS#, WE#,M_CK[2:0], M_CK[2:0]#, DQ[63:0], DQS[8:0] and CB[7:0]. 2. For 2.5 V DDR SDRAM support. 3. For 1.8 V DDR-II SDRAM support. 4. Miscellaneous signals include all signals that are not PCI-X or SDRAM signals. 5. Ensured by design. 54 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Electrical Specifications Table 22. ICC Characteristics Symbol ILI1 ILI2 Parameter Input Leakage Current for each signal except TCK, TMS, TRST#, TDI Input Leakage Current for TCK, TMS, TRST#, TDI -140 Typ Max ±2 -250 Units µA µA Notes 0 ≤ VIN ≤ VCC (4) VIN = 0.45 V (1, 4) (1, 2) 1.33 1.20 1.04 0.580 0.487 3.2 A ICC33 Active Power Supply Current - PCI-X interfaces (Power Supply) Both at 66 MHz Both at 100 MHz Both at 133 MHz Power Supply Current - DDR ICC25 Active (Power Supply) Power Supply Current - DDR-II ICC18 Active (Power Supply) ICC15 Active Power Supply Current - IOP/Bridge core (Power Supply) ICC13 Active Power Supply Current - Intel XScale® (Power Supply) core 800 MHz 667 MHz 500 MHz ICC33 Active (Thermal) Thermal Current - PCI-X interfaces Both at 66 MHz Both at 100 MHz Both at 133 MHz Thermal Current - DDR Thermal Current - DDR-II Thermal Current - IOP/Bridge core Thermal Current - Intel XScale® core 800 MHz 667 MHz 500 MHz 0.430 0.390 0.340 1.08 1.00 0.914 0.295 0.255 2.5 A A A (1, 2) (1, 2) (1, 2) (1, 2) 0.453 0.411 0.358 A (1, 3) A A A A (1, 3) (1, 3) (1, 3) (1, 3) A ICC25 Active (Thermal) ICC18 Active (Thermal) ICC15 Active (Thermal) ICC13 Active (Thermal) NOTES: 1. Measured with device operating and outputs loaded to the test condition in Figure 14 “AC Test Load for All Signals Except PCI and DDR SDRAM” on page 67. 2. ICC Active (Power Supply) value is provided for selecting the system power supply. This is based on the worst case data patterns and skew material at the following worst case voltages: VCC33 = 3.63 V, VCC25 = 2.7 V, Vcc18 = 1.9v, VCC15 = 1.575 V, VCC13 = 1.41 V. 3. ICC Active (Thermal) value is provided for selecting the system thermal design power (TDP). This is based on the following typical voltages: VCC33 = 3.3 V, VCC25 = 2.5 V, Vcc18 = 1.8v, VCC15 = 1.5 V, VCC13 = 1.35 V. 4. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. Document Number: 273943-004US August 2005 55 Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.4 4.4.1 Table 23. Symbol TF1 TC1 TCH1 TCL1 TSR1 Targeted AC Specifications Clock Signal Timings PCI Clock Timings PCI-X 133 Parameter Min. PCI clock Frequency PCI clock Cycle Time - Avg. PCI clock High Time PCI clock Low Time PCI clock Slew Rate 100 7.5 3 3 1.5 4 Max 133 10 Min. 66 10 9.875 PCI-X 100 Max 100 15 PCI-X 66 Min. 50 15 14.8 6 6 Max 66 20 PCI 66 Min. 33 15 14.8 6 6 Max 66 30 PCI 33 Units Min. 16 30 29.7 11 11 Max 33 60 MHz ns ns ns ns 4 V/ns 2 1 1 3, 4 Notes Absolute Minimum 7.375 3 3 1.5 4 1.5 4 1.5 4 1 PCI Spread Spectrum Requirements fmod fspread PCI clock modulation frequency PCI clock frequency spread 30 -1 33 0 30 -1 33 0 30 -1 33 0 30 -1 33 0 KHz % NOTES: 1. Clock frequency may not change beyond spread-spectrum limits except while is asserted. 2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform. 3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 4. Clock jitter class 2, per PCI-X Electrical and Mechanical Rev 2.0a specification Table 24. Symbol TF2 TC2 TCH2 TCL2 TCS2 Tskew2 Tskew3 DDR Clock Timings DDR-II 400 Parameter Minimum Maximum 200 5.0 2.15 2.15 350 100 -285 285 -285 6.0/7.5(1) 2.7/3.37 (1) DDR333 Units Minimum Maximum 167 MHz ns ns ns 350 100 285 ps ps ps 2 Notes DDR SDRAM clock Frequency DDR SDRAM clock Cycle Time DDR SDRAM clock High Time DDR SDRAM clock LowTime DDR SDRAM clock Period Stability DDR SDRAM clock skew for any differential clock pair (M_CK[2:0] - M_CK[2:0]#) DDR SDRAM clock skew for any clock pair and any system memory strobe (M_CK - DQS). 2.7/3.37(1) NOTES: 1. CL = 2.5/2.0. 2. This specification applies for writes only; that is, when the 80331 is driving the strobes as well as the clocks. Refer to the JEDEC specification for an explanation of strobe to clock timing for DDR reads. 56 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.4.2 Table 25. DDR/DDR-II SDRAM Interface Signal Timings DDR SDRAM Signal Timings Symbol TVB1 TVA1 TVB3 TVA3 TVB4 TVA4 TVB5 TVA5 TVB6 TVA6 Parameter DQ, CB and DM write output valid time before DQS. DQ, CB and DM write output valid time after DQS. Address and Command write output valid before M_CK rising edge. Address and Command write output valid after M_CK rising edge. DQ, CB and DM read input valid time before DQS rising or falling edges. DQ, CB and DM read input valid time after DQS rising or falling edges. CS[1:0]# control valid before M_CK rising edge. CS[1:0]# control valid after M_CK rising edge. DQS write preamble duration. DQS write postamble duration. Minimum 2.68 2.68 2.62 2.62 0.35 0.35 2.62 2.62 4.50 (nominal) 3.00 (nominal) Max. Units ns ns ns ns ns ns ns ns ns ns Notes (4) (4) (4,8) (4,8) (5) (5) (4) (4) (6) (6) NOTES: 1. See Figure 7 “Output Timing Measurement Waveforms” on page 63. 2. See Figure 8 “Input Timing Measurement Waveforms” on page 64. 3. Clock to output valid times are specified with a 0 pF loading. 4. See Figure 11 “DDR SDRAM Write Timings” on page 65. 5. See Figure 12 “DDR SDRAM Read Timings” on page 65. 6. See Figure 13 “Write PreAmble/PostAmble Durations” on page 66. 7. See Figure 15 “AC Test Load for DDR SDRAM Signals” on page 67. 8. Address/Command pin group; RAS#, CAS#, WE#, MA[12:0], BA[1:0]. Document Number: 273943-004US August 2005 57 Intel® 80331 I/O Processor Datasheet Electrical Specifications Table 26. DDR-II SDRAM Signal Timings Symbol TVB1 TVA1 TVB3 TVA3 TVB4 TVA4 TVB5 TVA5 TVB6 TVA6 Parameter DQ, CB and DM write output valid time before DQS crossing. DQ, CB and DM write output valid time after DQS crossing. Address and Command write output valid before M_CK rising edge Address and Command write output valid after M_CK rising edge DQ, CB and DM read input valid time before DQS rising or falling edges DQ, CB and DM read input valid time after DQS rising or falling edges CS[1:0]# control valid before M_CK rising edge. CS[1:0]# control valid after M_CK rising edge. DQS write preamble duration. DQS write postamble duration. Mini 2.12 2.12 2.12 2.12 0.35 0.35 2.12 2.12 3.75 (nom) 2.50 (nom) Max Units ns ns ns ns ns ns ns ns ns ns Notes 4 4 4 4,8 6 6 4 4 9 9 NOTES: 1. See Figure 7 “Output Timing Measurement Waveforms” on page 63. 2. See Figure 8 “Input Timing Measurement Waveforms” on page 64. 3. Clock to output valid times are specified with a 0 pF loading. 4. See Figure 11 “DDR SDRAM Write Timings” on page 65. 5. See Figure 13 “DQS falling edge output access time to M_CK rising edge. 6. See Figure 12 “DDR SDRAM Read Timings” on page 65. Data to strobe read setup and data from strobe read hold minimum requirements specified are determined with the DQS delay programmed for a 90 degree phase shift. 7. See Figure 15 “AC Test Load for DDR SDRAM Signals” on page 67. 8. Address/Command pin group: RAS#, CAS#, WE#, MA[12:0], BA[1:0], ODT[1:0]. 9. See Figure 13 “Write PreAmble/PostAmble Durations” on page 66. 58 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.4.3 Table 27. Peripheral Bus Interface Signal Timings Peripheral Bus Signal Timings Symbol TOV1 TOF TIS1 TIH1 Parameter Output Valid Delay from M_CK Output Float Delay from M_CK Input Setup to M_CK Input Hold from M_CK Min 1 1 4.5 2 Max 5 5 Units ns ns ns ns Notes (1, 3) (1, 3) (2) (2) TAH1 TAV1 TAH2 TAS1 TAO1 TAW1 TAH3 TAS2 TAC1 ALE High time ALE high to address Valid ALE low to address invalid Address valid to ALE low ALE low to POE# low ALE low to PWE# low PWE# high to Data Invalid Data valid to PWE# high ALE low to PCE[1:0]# low 15 0 15 15 0 15 15 60 15 ns ns ns ns ns ns ns ns ns NOTES: 1. See Figure 7 “Output Timing Measurement Waveforms” on page 63. 2. See Figure 8 “Input Timing Measurement Waveforms” on page 64. 3. See Figure 14 “AC Test Load for All Signals Except PCI and DDR SDRAM” on page 67. 4. See Table 32, AC Measurement Conditions. 5. All timing referenced to M_CK is for functional testing, for the cases where M_CK * N = IBCLK. 6. PBI Clock is internal only; 66 MHz with 266 MHz internal bus. Document Number: 273943-004US August 2005 59 Intel® 80331 I/O Processor Datasheet Electrical Specifications Table 28. PCI Signal Timings PCI-X 133 Symbol TOV1 Parameter Clock to Output Valid Delay for bused signals Clock to Output Valid Delay for point to point signals Clock to Output Float Delay Input Setup to clock for bused signals Input Setup to clock for point to point signals Input Hold time from clock Reset Active Time Reset Active to output float delay REQ64# to Reset setup time Reset to REQ64# hold time PCI-X initialization pattern to Reset setup time Reset to PCI-X initialization pattern hold time 10 0 10 50 1.2 1.2 PCI-X 100 Min. 0.7 Max 3.8 PCI-X 66 Min. 0.7 Max 3.8 PCI 66 Min. 1 Max 6 PCI 33 Min. 2 Max 11 ns (1,2,3) Units Notes TOV2 0.7 3.8 0.7 3.8 2 6 2 12 ns (1,2,3) TOF TIS1 TIS2 7 1.7 1.7 7 3 5 14 7 10, 12 0 1 40 10 10 50 0 28 ns ns ns (1,7) (3,4,8) (3,4) TIH1 TRST TRF TIS3 TIH2 TIS4 0.5 1 40 0.5 1 40 10 0 10 50 0 1 ns ms 40 ns clocks 50 ns clocks (4) (5,6) 0 TIH3 0 50 0 50 ns NOTES: 1. See the timing measurement conditions in; Figure 7 “Output Timing Measurement Waveforms” on page 63. 2. See Figure 16 “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 67, Figure 17 “PCI/PCI-X TOV(max) Falling Edge AC Test Load” on page 68, and Figure 18 “PCI/PCI-X TOV(min) AC Test Load” on page 68. 3. Setup time for point-to-point signals applies to REQ# and GNT# only. All other signals are bused. 4. See the timing measurement conditions in Figure 8 “Input Timing Measurement Waveforms” on page 64. 5. RST# is asserted and deasserted asynchronously with respect to CLK. 6. All output drivers must be floated when RST# is active. 7. For purposes of Active/Float timing measurements, the HI-Z or ‘off’ state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 60 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.4.4 Table 29. I2C Interface Signal Timings I2C Signal Timings Std. Mode Symbol FSCL TBUF THDSTA TLOW THIGH TSUSTA THDDAT TSUDAT TSR TSF TSUSTO Parameter Min. SCL Clock Frequency Bus Free Time Between STOP and START Condition Hold Time (repeated) START Condition SCL Clock Low Time SCL Clock High Time Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Setup Time for STOP Condition 4 0 4.7 4 4.7 4 4.7 0 250 1000 300 3.45 Max 100 Min. 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 20+0.1Cb 0.6 300 300 0.9 Max 400 KHz µs µs µs µs µs µs ns ns ns µs (1) (1, 3) (1, 2) (1, 2) (1) (1) (1) (1, 4) (1, 4) (1) Fast Mode Units Notes NOTES: 1. See Figure 9 “I2C/SMBus Interface Signal Timings” on page 64. 2. Not tested. 3. After this period, the first clock pulse is generated. 4. Cb = the total capacitance of one bus line, in pF.I2C 4.4.5 Table 30. UART Interface Signal Timings UART Signal Timings Std. Mode Symbol TXD1 TRXS1 TRXH1 TCTS1 TCTH1 TRTS1 TRTH1 Parameter Min. Ux_TXD output delay from M_CK rising edge Ux_RXD data setup time (to M_CK rising edge). Ux_RXD data hold time (to M_CK rising edge). Ux_CTS setup time (to M_CK rising edge). Ux_CTS hold time (to M_CK rising edge). Ux_RTS setup time (to M_CK rising edge). Ux_RTS hold time (to M_CK rising edge). 50 50 60 60 60 60 Max 60 ns ns ns ns ns ns ns 1 Units Notes 1. See Figure 10 “UART Transmitter Receiver Timing” on page 64. Document Number: 273943-004US August 2005 61 Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.4.6 Table 31. Boundary Scan Test Signal Timings Boundary Scan Test Signal Timings Symbol TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSOV1 TOF1 Parameter TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Input Setup to TCK — TDI, TMS Input Hold from TCK — TDI, TMS TDO Valid Delay TDO Float Delay 3 5 5 5 15 15 Min. 0 15 15 5 5 Max 0.5TF Units MHz ns ns ns ns ns ns ns ns Measured at 1.5 V (1). Measured at 1.5 V (1). 0.8 V to 2.0 V (1) 2.0 V to 0.8 V (1) (4) (4) Relative to falling edge of TCK (2, 3). Relative to falling edge of TCK (2, 5). Notes NOTES: 1. Not tested. 2. Outputs precharged to VCC5. 3. See Figure 7 “Output Timing Measurement Waveforms” on page 63. 4. See Figure 8 “Input Timing Measurement Waveforms” on page 64. 5. A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See Figure 7 “Output Timing Measurement Waveforms” on page 63. 62 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.5 Figure 6. AC Timing Waveforms Clock Timing Measurement Waveforms TCR Vih(min) Vtest Vil(max) Vtcl TCH TCL TCF Vtch TC Figure 7. Output Timing Measurement Waveforms Vth CLK Vtest Vtl TOV Vtfall OUTPUT DELAY FALL TOV OUTPUT DELAY RISE Vtrise TOF OUTPUT FLOAT Document Number: 273943-004US August 2005 63 Intel® 80331 I/O Processor Datasheet Electrical Specifications Figure 8. Input Timing Measurement Waveforms Vth CLK Vtest Vtl TIH TIS Vth INPUT Vtest Valid Vtest Vmax Vtl Figure 9. I2C/SMBus Interface Signal Timings SDA TBUF TLOW TSR TSF THDSTA TSP SCL THDSTA THDDAT Stop Start THIGH TSUSTO TSUDAT TSUSTA Repeated Start Stop Figure 10. UART Transmitter Receiver Timing M_CK TXD1 Ux_TXD TRXS1 TRXH1 Ux_RXD 64 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Electrical Specifications Figure 11. DDR SDRAM Write Timings ADDR/CTRL TVB3 TVA3 CS[1:0]# TVB5 TVA5 M_CK DQS DQS# TVB1 TVA1 DQ Figure 12. DDR SDRAM Read Timings DQS TVB4 TVA4 DQ Document Number: 273943-004US August 2005 65 Intel® 80331 I/O Processor Datasheet Electrical Specifications Figure 13. Write PreAmble/PostAmble Durations DQS TVB6 DQS TVA6 66 August 2005 Document Number: 273943-004US Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.6 Table 32. AC Test Conditions AC Measurement Conditions Symbol Vth Vtl Vtest Vtrise Vtfall Vmax Slew Rate (1) PCI-X 0.6 VCC33 0.25 VCC33 0.4 VCC33 0.285 VCC33 0.615 VCC33 0.4 VCC33 1.5 PCI 0.6 VCC33 0.2 VCC33 0.4 VCC33 0.285 VCC33 0.615 VCC33 0.4 VCC33 1.5 DDR 2.0 0.5 1.25 1.25 1.25 1.5 1.0 DDR-II 1.15 0.2 0.90 0.90 0.90 0.97 1.0 PBI 2.0 0.8 1.5 1.5 1.5 1.2 1.0 Units V V V V V V V/nS 1. Input signal slew rate is measured between Vil and Vih. Figure 14. AC Test Load for All Signals Except PCI and DDR SDRAM Test Point Output 50pF Figure 15. AC Test Load for DDR SDRAM Signals 1.25V 25Ω Output 25Ω 30pF Test Point Figure 16. PCI/PCI-X TOV(max) Rising Edge AC Test Load Test Point Output 25Ω 10pF Document Number: 273943-004US August 2005 67 Intel® 80331 I/O Processor Datasheet Electrical Specifications Figure 17. PCI/PCI-X TOV(max) Falling Edge AC Test Load VCC33 25Ω Output 10pF Test Point Figure 18. PCI/PCI-X TOV(min) AC Test Load VCC33 1KΩ Output 1KΩ 10pF Test Point 68 August 2005 Document Number: 273943-004US