28F256L30

1.8 Volt Intel StrataFlash® Wireless Memory with 3.0-Volt I/O (L30) 28F640L30, 28F128L30, 28F256L30 Datasheet Product Features ■ High performance Read-While-Write/Erase — 85 ns initial access — 52MHz with zero wait state, 17 ns clock-to-data output synchronous-burst mode — 25 ns asynchronous-page mode — 4-, 8-, 16-, and continuous-word burst mode — Burst suspend — Programmable WAIT configuration — Buffered Enhanced Factory Programming (Buffered EFP): 3.5 µs/byte (Typ) — 1.8 V low-power buffered and non-buffered programming @ 10 µs/byte (Typ) ■ Architecture — Asymmetrically-blocked architecture — Multiple 8-Mbit partitions: 64Mb and 128Mb devices — Multiple 16-Mbit partitions: 256Mb devices — Four 16-KWord parameter blocks: top or bottom configurations — 64K-Word main blocks — Dual-operation: Read-While-Write (RWW) or Read-While-Erase (RWE) — Status register for partition and device status ■ Power — 1.7 V - 2.0 V VCC operation — I/O voltage: 2.2 V - 3.3 V — Standby current: 30 µA (Typ) — 4-Word synchronous read current: 17 mA (Typ) @ 54 MHz — Automatic Power Savings (APS) mode ■ Software — 20 µs (Typ) program suspend — 20 µs (Typ) erase suspend — Intel® Flash Data Integrator (FDI) optimized — Basic Command Set (BCS) and Extended Command Set (ECS) compatible — Common Flash Interface (CFI) capable ■ Security — OTP space: — 64 unique device identifier bits — 64 user-programmable OTP bits — Additional 2048 user-programmable OTP bits — Absolute write protection: VPP = GND — Power-transition erase/program lockout — Individual zero-latency block locking — Individual block lock-down ■ Quality and Reliability — Expanded temperature: –25° C to +85° C — Minimum 100,000 erase cycles per block — ETOX™ VIII process technology (0.13 µm) ■ Density and Packaging — 64-, 128- and 256-Mbit density in VF BGA packages — 128/0, and 256/0 Density in Stacked-CSP — 16-bit wide data bus The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O product is the latest generation of Intel StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides high performance synchronous-burst read mode and asynchronous read mode using 1.8 volt low-voltage, multilevel cell (MLC) technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O device is manufactured using Intel 0.13 µm ETOX™ VIII process technology. It is available in industry-standard chip scale packaging. . Notice: This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Order Number: 251903-003 April 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. The 1.8 Volt Intel StrataFlash® Wireless Memory with 3.0 Volt I/O datasheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2003, Intel Corporation * Other names and brands may be claimed as the property of others. 2 28F640L30, 28F128L30, 28F256L30 Contents 1.0 Introduction ..................................................................................................................7 1.1 1.2 1.3 Nomenclature ........................................................................................................7 Acronyms ..............................................................................................................7 Conventions ..........................................................................................................8 Product Overview ..................................................................................................9 Ballout Diagrams for VF BGA Package...............................................................10 Ballout Diagrams for Intel® Stacked Chip Scale Package ..................................11 Signal Descriptions for VF BGA Package ...........................................................12 2.4.1 Signal Descriptions for 128/0 and 256/0 Stacked-CSP..........................13 Memory Map .......................................................................................................15 2.0 Device Description ....................................................................................................9 2.1 2.2 2.3 2.4 2.5 3.0 Device Operations ...................................................................................................17 3.1 Bus Operations....................................................................................................17 3.1.1 Reads .....................................................................................................17 3.1.2 Writes .....................................................................................................17 3.1.3 Output Disable........................................................................................17 3.1.4 Standby ..................................................................................................18 3.1.5 Reset ......................................................................................................18 Device Commands ..............................................................................................18 Command Definitions ..........................................................................................20 Asynchronous Page-Mode Read ........................................................................22 Synchronous Burst-Mode Read ..........................................................................22 4.2.1 Burst Suspend........................................................................................23 Read Configuration Register (RCR)....................................................................23 4.3.1 Read Mode .............................................................................................24 4.3.2 Latency Count ........................................................................................24 4.3.3 WAIT Polarity .........................................................................................26 4.3.3.1 WAIT Signal Function................................................................26 4.3.4 Data Hold ...............................................................................................27 4.3.5 WAIT Delay ............................................................................................28 4.3.6 Burst Sequence......................................................................................28 4.3.7 Clock Edge .............................................................................................28 4.3.8 Burst Wrap .............................................................................................28 4.3.9 Burst Length ...........................................................................................29 Word Programming .............................................................................................30 5.1.1 Factory Word Programming ...................................................................31 Buffered Programming ........................................................................................31 Buffered Enhanced Factory Programming ..........................................................32 5.3.1 Buffered EFP Requirements and Considerations ..................................32 5.3.2 Buffered EFP Setup Phase ....................................................................33 5.3.3 Buffered EFP Program/Verify Phase......................................................33 3.2 3.3 4.0 Read Operations .......................................................................................................22 4.1 4.2 4.3 5.0 Programming Operations .....................................................................................30 5.1 5.2 5.3 3 28F640L30, 28F128L30, 28F256L30 5.4 5.5 5.6 5.3.4 Buffered EFP Exit Phase ....................................................................... 34 Program Suspend ............................................................................................... 34 Program Resume ................................................................................................ 35 Program Protection ............................................................................................. 35 6.0 Erase Operations ..................................................................................................... 36 6.1 6.2 6.3 6.4 Block Erase ......................................................................................................... 36 Erase Suspend.................................................................................................... 36 Erase Resume .................................................................................................... 37 Erase Protection.................................................................................................. 37 Block Locking ...................................................................................................... 38 7.1.1 Lock Block .............................................................................................. 38 7.1.2 Unlock Block .......................................................................................... 38 7.1.3 Lock-Down Block ................................................................................... 38 7.1.4 Block Lock Status................................................................................... 39 7.1.5 Block Locking During Suspend .............................................................. 39 Protection Registers ............................................................................................ 40 7.2.1 Reading the Protection Registers .......................................................... 41 7.2.2 Programming the Protection Registers .................................................. 42 7.2.3 Locking the Protection Registers ........................................................... 42 Memory Partitioning ............................................................................................ 43 Read-While-Write Command Sequences ........................................................... 43 8.2.1 Simultaneous Operation Details............................................................. 44 8.2.2 Synchronous and Asynchronous Read-While-Write Characteristics and Waveforms ............................................................. 44 8.2.2.1 Write operation to asynchronous read transition....................... 44 8.2.2.2 Synchronous read to write operation transition ......................... 45 8.2.3 Read Operation During Buffered Programming Flowchart..................... 45 Simultaneous Operation Restrictions .................................................................. 46 Read Status Register .......................................................................................... 47 9.1.1 Clear Status Register ............................................................................. 48 Read Device Identifier ......................................................................................... 48 CFI Query............................................................................................................ 49 Power-Up/Down Characteristics ......................................................................... 50 Power Supply Decoupling ................................................................................... 50 Automatic Power Saving (APS) .......................................................................... 50 Reset Characteristics .......................................................................................... 50 Absolute Maximum Ratings ................................................................................ 52 Operating Conditions .......................................................................................... 52 DC Current Characteristics ................................................................................. 53 DC Voltage Characteristics ................................................................................. 54 7.0 Security Modes ......................................................................................................... 38 7.1 7.2 8.0 Dual-Operation Considerations ......................................................................... 43 8.1 8.2 8.3 9.0 Special Read States ................................................................................................ 47 9.1 9.2 9.3 10.0 Power and Reset ...................................................................................................... 50 10.1 10.2 10.3 10.4 11.0 Thermal and DC Characteristics ........................................................................ 52 11.1 11.2 11.3 11.4 4 28F640L30, 28F128L30, 28F256L30 12.0 AC Characteristics ...................................................................................................55 12.1 12.2 12.3 12.4 12.5 12.6 AC Read Specifications (VCCQ = 2.2 V – 3.3 V) ................................................55 AC Write Specifications.......................................................................................60 Program and Erase Characteristics ....................................................................64 Reset Specifications............................................................................................64 AC Test Conditions .............................................................................................65 Capacitance ........................................................................................................66 Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F Appendix G Write State Machine (WSM) ...........................................................................67 Flowcharts ............................................................................................................74 Common Flash Interface ................................................................................83 Mechanical Information...................................................................................93 Additional Information .....................................................................................97 Ordering Information for VF BGA Package ............................................98 Ordering Information for S-CSP Package ...............................................99 5 28F640L30, 28F128L30, 28F256L30 Revision History Revision Date 10/14/02 02/08/03 Revision -001 -002 Initial Release Revised 256Mb Partition Size Revised 256Mb Memory Map Changed WAIT function to de-assert during Asynchronous Operations (Asynchronous Reads and all Writes) Changed WAIT function to active during Synchronous Non-Array Read Updated all Waveforms to reflect new WAIT function Revised Section 8.2.2 Added Synchronous Read to Write transition Section Added new AC specs: R15, R16, R17, R111, R311, R312, W21, and W22 Various text edits Improved Bin 1 to 85ns from 90ns Improved Frequency to 52MHz from 50MHz Added Stacked-CSP for 128/0 and 256/0 Ball-out and Mechanical Drawing Description 04/11/03 -003 6 28F640L30, 28F128L30, 28F256L30 1.0 Introduction This document provides information about the 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O (L30) device. This document describes the L30 flash memory device features, operation, and specifications. 1.1 Nomenclature 1.8 V: VCC voltage range of 1.7 V – 2.0 V (except where noted) 3.0 V Range: VCCQ voltage range of 2.2 V – 3.3 V VPP = 9.0 V: VPP voltage range of 8.5 V – 9.5 V Block: A group of bits, bytes or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The L30 flash memory device has two block sizes: 16K-Word, and 64K-Word. Main block: An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. Parameter block: An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Top parameter device: Previously referred to as a top-boot device, a device with its parameter partition located at the highest physical address of its memory map. Parameter blocks within a parameter partition are located at the highest physical address of the parameter partition. Bottom parameter device: Previously referred to as a bottom-boot device, a device with its parameter partition located at the lowest physical address of its memory map. Parameter blocks within a parameter partition are located at the lowest physical address of the parameter partition. Partition: A group of blocks that share common program/erase circuitry. Blocks within a partition also share a common status register. If any block within a partition is being programmed or erased, only status register data (rather than array data) is available when any address within that partition is read. Main partition: A partition containing only main blocks. Parameter partition: A partition containing parameter blocks and main blocks. 1.2 Acronyms CUI: Command User Interface MLC: Multi-Level Cell OTP: One-Time Programmable PLR: Protection Lock Register PR: Protection Register RCR: Read Configuration Register RFU: Reserved for Future Use SR: Status Register WSM: Write State Machine Datasheet 7 28F640L30, 28F128L30, 28F256L30 1.3 Conventions VCC: signal or voltage connection VCC: signal or voltage level 0x: hexadecimal number prefix 0b: binary number prefix SR[4]: Denotes an individual register bit. A[15:0]: Denotes a group of similarly named signals, such as address or data bus. A5: Denotes one element of a signal group membership, such as an address. bit: binary unit byte: eight bits word: two bytes, or sixteen bits Kbit: 1024 bits KByte: 1024 bytes KWord: 1024 words Mbit: 1,048,576 bits MByte: 1,048,576 bytes MWord: 1,048,576 words 8 Datasheet 28F640L30, 28F128L30, 28F256L30 2.0 Device Description This section provides an overview of the features and capabilities of the 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O (L30) device. 2.1 Product Overview The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O (L30) device provides read-whilewrite and read-while-erase capability with density upgrades through 256-Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Each device density contains one parameter partition and several main partitions. The flash memory array is grouped into multiple 8-Mbit partitions. By dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations. Although each partition has write, erase and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. The L30 flash memory device allows burst reads that cross partition boundaries. User application code is responsible for ensuring that burst reads don’t cross into a partition that is programming or erasing. Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for low-voltage systems, the L30 flash memory device supports read operations with VCC at 1.8 V, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (Buffered EFP) provides the fastest flash array programming performance with VPP at 9.0 Volt, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the device. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (x16). The L30 flash memory device offers power savings through Automatic Power Savings (APS) mode and standby mode. The device automatically enters APS following read-cycle completion. Standby is initiated when the system deselects the device by deasserting CE# or by asserting RST#. Combined, these features can significantly reduce power consumption. The L30 flash memory device’s protection register allows unique flash device identification that can be used to increase system security. Also, the individual Block Lock feature provides zerolatency block locking and unlocking. Datasheet 9 28F640L30, 28F128L30, 28F256L30 2.2 Ballout Diagrams for VF BGA Package The L30 flash memory device is available in a VF BGA package with 0.75 mm ball-pitch. Figure 1 shows the ballout for the 64-Mbit and 128-Mbit devices in the 56-ball VF BGA package with a 7 x 8 active-ball matrix. Figure 2 shows the device ballout for the 256-Mbit device in the 63-ball VF BGA package with a 7 x 9 active-ball matrix. Both package densities are ideal for spaceconstrained board applications Figure 1. 7x8 Active-Ball Matrix for 64-, and 128-Mbit Densities in VF BGA Packages 1 A A11 B A12 C A13 D A15 E VCCQ F VSS G D7 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A8 VSS VCC VPP A18 A6 A4 A4 A6 A18 VPP VCC VSS A8 A11 B A9 A20 CLK RST# A17 A5 A3 A3 A5 A17 RST# CLK A20 A9 A12 C A10 A21 ADV# WE# A19 A7 A2 A2 A7 A19 WE# ADV# A21 A10 A13 D A14 WAIT A16 D12 WP# A22 A1 A1 A22 WP# D12 A16 WAIT A14 A15 E D15 D6 D4 D2 D1 CE# A0 A0 CE# D1 D2 D4 D6 D15 VCCQ F D14 D13 D11 D10 D9 D0 OE# OE# D0 D9 D10 D11 D13 D14 VSS G VSSQ D5 VCC D3 VCCQ D8 VSSQ VSSQ D8 VCCQ D3 VCC D5 VSSQ D7 VFBGA 7x8 Top View - Ball Side Down VFBGA 7x8 Bottom View - Ball Side Up NOTE: On lower-density devices, upper-address balls can be treated as NC. (e.g., for 64-Mbit density, A22 will be NC) Figure 2. 7x9 Active-Ball Matrix for 256-Mbit Density in VF BGA Package 1 2 3 4 5 6 7 8 9 10 11 12 13 13 12 11 10 9 8 7 6 5 4 3 2 1 A DU B DU C A13 D A15 E VCCQ F DU G DU DU D7 VSSQ D5 VCC D3 VCCQ Top View D8 VSSQ RFU DU DU DU DU RFU VSSQ D8 VCCQ D3 VCC D5 VSSQ D7 DU DU DU VSS D14 D13 D11 D10 D9 D0 OE# RFU DU DU DU DU RFU OE# D0 D9 D10 D11 D13 D14 VSS DU DU D15 D6 D4 D2 D1 CE# A0 A23 A23 A0 CE# D1 D2 D4 D6 D15 VCCQ A14 WAIT A16 D12 WP# A22 A1 A24 A24 A1 A22 WP# D12 A16 WAIT A14 A15 A10 A21 ADV# WE# A19 A7 A2 A25 A25 A2 A7 A19 WE# ADV# A21 A10 A13 DU A12 A9 A20 CLK RST# A17 A5 A3 RFU DU DU DU DU RFU A3 A5 A17 RST# CLK A20 A9 A12 DU DU DU A11 A8 VSS VCC VPP A18 A6 A4 RFU DU DU DU DU RFU A4 A6 A18 VPP VCC VSS A8 A11 DU DU A B C D E F G Ball Side Down- Bottom View Ball Side Up NOTE: On lower density devices upper address balls can be treated as RFUs. (A24 is for 512Mb and A25 is for 1Gb densities.) All ball locations are populated. 10 Datasheet 28F640L30, 28F128L30, 28F256L30 2.3 Ballout Diagrams for Intel® Stacked Chip Scale Package The 1.8 Volt Intel StrataFlash® wireless memory in Quad+ ballout device is available in an 88-ball (80-active ball) Intel® Stacked Chip Scale Package for the 128-Mbit device and in an 88-ball (80active ball) Intel® Ultra-Thin Stacked Chip Scale Package for the 256-Mbit device. Figure 3 shows the signal ballout. Refer to Section 5.0 for Mechanical Package Information. Figure 3. 88-Ball (80-Active Ball) Stacked-CSP Package Ballout 1 2 3 4 5 6 7 8 A DU DU DU DU B A4 A18 A19 VSS F1 -V CC F2 -V C C A2 1 A11 C A5 R -L B# A23 VSS S -CS 2 C LK A2 2 A12 D A3 A17 A24 F-V P P , F -V P E N R -W E # P 1 -CS # A9 A13 E A2 A7 A25 F-W P # A DV # A 20 A1 0 A15 F A1 A6 R -U B # F -R S T# F-W E # A8 A1 4 A16 G A0 D8 D2 D10 D5 D 13 W A IT F 2 -CE # H R -O E # D0 D1 D3 D1 2 D 14 D7 F2 - O E # J S -CS 1 # F1 -O E # D9 D11 D4 D6 D1 5 VCCQ K F1 -C E # P 2 -CS # F3 -C E # S -V CC P -V C C F2 -V C C V CC Q P - M o de L VSS VSS DU V CCQ F 1 -V C C VSS VSS VS S DU VSS DU M DU T o p V ie w - B a ll S id e D o w n Legend: G lo b a l S R A M /P S R A M s p e c ific F la s h s p e c ific Datasheet 11 28F640L30, 28F128L30, 28F256L30 2.4 Table 1. Symbol A[MAX:0] D[15:0] Signal Descriptions for VF BGA Package Table 1 describes the active signals used on the L30 flash memory device. Signal Descriptions Type In In/Out Name and Function ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0]. DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the CE# or OE# are de-asserted. Data is internally latched during writes. ADDRESS VALID: Active-low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. CHIP ENABLE: Active-low input. CE#-low selects the device. CE#-high deselects the device, placing it in standby, with D[15:0] and WAIT in High-Z. CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode and increments the internal address generator. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. OUTPUT ENABLE: Active-low input. OE#-low enables the device’s output data buffers during read cycles. OE#-high places the data outputs in High-Z and WAIT in High-Z. RESET: Active-low input. RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. RST#-high enables normal operation. Exit from reset places the device in asynchronous read array mode. WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration Register bit 10 (CR.10, WT) determines its polarity when asserted. With CE# and OE# at VIL, WAIT’s active output is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is VIH. • In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when de-asserted. • In asynchronous page mode, and all write modes, WAIT is de-asserted. WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on the rising edge of WE#. WRITE PROTECT: Active-low input. WP#-low enables the lock-down mechanism. Blocks in lock-down cannot be unlocked with the Unlock command. WP#-high overrides the lock-down function enabling blocks to be erased or programmed using software commands. ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages should not be attempted. ADV# In CE# In CLK In OE# In RST# In WAIT Out WE# In WP# In VPP Pwr/l Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain above VPP1 min to perform in-system flash modification. VPP may be 0 V during read operations. VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 12 V may reduce block cycling capability. VCC VCCQ VSS VSSQ DU NC RFU Pwr Pwr Pwr Pwr - DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted. OUTPUT POWER SUPPLY: Output-driver source voltage. GROUND: Ground reference for device logic voltages. Connect to system ground. GROUND: Ground reference for device output voltages. Connect to system ground. DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or other balls, and must be left floating. NO CONNECT: No internal connection; can be driven or floated. RESERVED for FUTURE USE: Reserved by Intel for future device functionality and enhancement. 12 Datasheet 28F640L30, 28F128L30, 28F256L30 2.4.1 Signal Descriptions for 128/0 and 256/0 Stacked-CSP Table 2 describes the active signals used on the 128/0 and 256/0-Mbit S-CSP. Table 2. Device Signal Descriptions for S-CSP (Sheet 1 of 2) Symbol Type Description ADDRESS INPUTS: Inputs for all die addresses during read and write operations. A[Max:0] Input • • 128-Mbit Die: A[Max] = A22 256-Mbit Die: A[Max] = A23 D[15:0] Input/ Output DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data is internally latched during writes. FLASH CHIP ENABLE: Low-true: CE#-low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. CE#1 selects flash die #1; CE#2 selects flash die #2. CE#2 is available on stacked combinations with two flash die and is RFU (Reserved For Future Use) on stacked combinations with only one flash die. SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/ both SRAM chip selects are deasserted (S-CS1# = VIH or S-CS2 = VIL), the SRAM is deselected and its power is reduced to standby levels. Treat this signal as NC (No Connect) for this device. PSRAM CHIP SELECT: Low-true; When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels. Treat this signal as NC (No Connect) for this device. FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables the flash output buffers, and places the flash outputs in High-Z. CE#1 CE#2 Input S-CS1# S-CS2 Input P-CS# Input OE#1 OE#2 Input OE#1 controls the outputs of flash die #1; OE#2 controls the outputs of flash die #2. OE#2 is available on stacked combinations with two flash die and is RFU on stacked combinations with only one flash die. RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the selected RAM output buffers. R-OE#-high disables the RAM output buffers, and places the selected RAM outputs in High-Z. Treat this signal as NC (No Connect) for this device. FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data are latched on the rising edge of WE#. RAM WRITE ENABLE: Low-true; R-WE# controls writes to the selected RAM die. Treat this signal as NC (No Connect) for this device. FLASH CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode and increments the internal address generator. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. FLASH WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration Register bit 10 (CR.10, WT) determines its polarity when asserted. With CE# and OE# at VIL, WAIT’s active output is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is VIH. • In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when de-asserted. • In asynchronous page mode, and all write modes, WAIT is de-asserted. R-OE# Input WE# R-WE# Input Input CLK Input WAIT Output Datasheet 13 28F640L30, 28F128L30, 28F256L30 Table 2. Device Signal Descriptions for S-CSP (Sheet 2 of 2) FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of the selected flash die. WP#-low enables the lock-down mechanism - locked down blocks cannot be unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. FLASH ADDRESS VALID: Active-low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. R-UB# R-LB# RAM UPPER / LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM high order bytes on D[15:8], and R-LB#-low enables the RAM loworder bytes on D[7:0]. Treat this signal as NC (No Connect) for this device. RST# Input FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations. RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode. PSRAM MODE: Low-true; P-MODE is used to program the configuration register, and enter/exit low power mode. Treat this signal as NC (No Connect) for this device. FLASH PROGRAM / ERASE POWER: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages should not be attempted. Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain above VPP1 min to perform in-system flash modification. VPP may be 0 V during read operations. VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 12 V may reduce block cycling capability VPEN ((Erase/Program/Block Lock Enables) is not available for L18/L30 products. VCC1 VCC2 FLASH LOGIC POWER: VCC1 supplies power to the core logic of flash die #1; VCC2 supplies power to the core logic of flash die #2. Write operations are inhibited when VCC < VLKO. Device operations at invalid VCC voltages should not be attempted. SRAM POWER SUPPLY: Supplies power for SRAM operations. Treat this signal as NC (No Connect) for this device. PSRAM POWER SUPPLY: Supplies power for PSRAM operations. Treat this signal as NC (No Connect) for this device. FLASH I/O POWER: Supply power for the input and output buffers. GROUND: Connect to system ground. Do not float any VSS connection. RESERVED for FUTURE USE: Reserve for future device functionality/ enhancements. Contact Intel regarding their future use. DON’T USE: Do not connect to any other signal, or power supply; must be left floating. NO CONNECT: No internal connection; can be driven or floated. WP# Input ADV# Input Input P-Mode Input VPP, VPEN Power Power S-VCC P-VCC VCCQ VSS RFU DU NC Power Power Power Power 14 Datasheet 28F640L30, 28F128L30, 28F256L30 2.5 Memory Map The 64Mb and 128Mb memory array is divided into multiple 8-Mbit partitions. Each device density contains one parameter partition and several main partitions. The 8-Mbit top or bottom parameter partition contains four 16K-Word blocks and seven 64K-Word blocks. There are multiple 8-Mbit main partitions. The 8-Mbit main partitions each contains eight 64K-Word blocks. The device multi-partition architecture is divided as follow: • The 64-Mbit device contains eight partitions: one 8-Mbit parameter partition, seven 8-Mbit main partitions. • The 128-Mbit device contains sixteen partitions: one 8-Mbit parameter partition, fifteen 8Mbit main partitions. • The 256Mb memory array is divided into multiple 16-Mbit partitions. Each device contains one parameter partition and fifteen main partitions. The 16-Mbit top or bottom parameter partition contains four 16K-Word blocks and fifteen 64K-Word blocks. There are fifteen 16Mbit main partitions. The 16-Mbit main partitions each contains sixteen 64K-Word blocks. Table 3 and Table 4 show the top and bottom parameter memory maps. Top Parameter Memory Map Size (KW) 8-Mbit Parameter Partition 16 16 16 16 64 … 64 Seven Partitions 64 … Blk 43 Table 3. 64-Mbit 8-Mbit Parameter Partition 3FC000-3FFFFF 3F8000-3FBFFF 3F4000-3F7FFF 3F0000-3F3FFF 3E0000-3EFFFF … 380000-38FFFF 370000-37FFFF … Size (KW) 16 16 16 16 64 … 64 Fifteen Partitions 64 … Blk 130 129 128 127 126 … 120 119 128-Mbit 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 780000-78FFFF 770000-77FFFF … 000000-00FFFF One Partition 56 55 … 8-Mbit Main Partition 64 0 000000-00FFFF 8-Mbit Main Partitions One Partition 66 65 64 63 62 … 64 0 Size (KW) 16-Mbit Parameter Partition 16 16 16 16 64 … 64 Seven Partitions 64 … Blk 258 257 256 255 254 … 256-Mbit FFC000-FFFFFF FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF … 000000-00FFFF One Partition 240 F00000-FFFFFF 239 EF0000-EFFFFF 16-Mbit Main Partitions 64 64 … 64 128 800000-80FFFF 127 7F0000-7FFFFF Eight Partitions 0 Datasheet 15 28F640L30, 28F128L30, 28F256L30 Table 4. Bottom Parameter Memory Map Size (KW) Blk 64-Mbit Size (KW) Blk 128-Mbit 8-Mbit Main Partitions Seven Partitions Fifteen Partitions 64 … 66 … 3F0000-3FFFFF … 8-Mbit Main Partitions 64 … 130 7F0000-7FFFFF … … 080000-08FFFF 070000-07FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF … 64 64 11 10 … 4 3 2 1 0 080000-08FFFF 070000-07FFFF 64 64 11 10 … 4 3 2 1 0 8-Mbit Parameter Partition 8-Mbit Parameter Partition … … One Partition 64 16 16 16 16 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF One Partition Size (KW) Blk 256-Mbit 16-Mbit Main Partitions Eight Partitions 64 … 258 FF0000-FFFFFF … … 64 64 … 131 100000-10FFFF 130 7F0000-7FFFFF … … Seven Partitions 64 64 19 18 … 4 3 2 1 0 100000-10FFFF 0F0000-0FFFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF … 16-Mbit Parameter Partition One Partition 64 16 16 16 16 … … 64 16 16 16 16 16 Datasheet 28F640L30, 28F128L30, 28F256L30 3.0 Device Operations This section provides an overview of device operations. The system CPU provides control of all insystem read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. 3.1 Bus Operations CE#-low and RST# high enable device read operations. The device internally decodes upper address inputs to determine the accessed partition. ADV#-low opens the internal address latches. OE#-low activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is latched when ADV# goes high or continuously flows through if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL). 3.1.1 Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. See Section 4.0, “Read Operations” on page 22 for details on the available read modes, and see Section 9.0, “Special Read States” on page 47 for details regarding the available read states. The Automatic Power Savings (APS) feature provides low power operation following reads during active mode. After data is read from the memory array and the address lines are quiescent, APS automatically places the device into standby. In APS, device current is reduced to ICCAPS (see Section 11.3, “DC Current Characteristics” on page 53). 3.1.2 Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 5, “Command Bus Cycles” on page 19 shows the bus cycle sequence for each of the supported device commands, while Table 6, “Command Codes and Definitions” on page 20 describes each command. See Section 12.0, “AC Characteristics” on page 55 for signaltiming details. Note: Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not be attempted. 3.1.3 Output Disable When OE# is deasserted, device outputs D[15:0] are disabled and placed in a high-impedance (High-Z) state, WAIT is also placed in High-Z. Datasheet 17 28F640L30, 28F128L30, 28F256L30 3.1.4 Standby When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 µs after CE# is deasserted. During standby, average current is measured over the same time interval 5 µs after CE# is deasserted. When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 3.1.5 Reset As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Intel® flash memory devices allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU. After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. When RST# has been deasserted, the device is reset to asynchronous Read Array state. Note: If RST# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. When returning from a reset (RST# deasserted), a minimum wait is required before the initial read access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can be initiated. After this wake-up interval passes, normal operation is restored. See Section 12.0, “AC Characteristics” on page 55 for details about signal-timing. 3.2 Device Commands Device operations are initiated by writing specific device commands to the Command User Interface (CUI). See Table 5, “Command Bus Cycles” on page 19. Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a sequence of internally-timed functions that culminate in the completion of the requested task. However, the operation can be aborted by either asserting RST# or by issuing an appropriate suspend command. 18 Datasheet 28F640L30, 28F128L30, 28F256L30 Table 5. Mode Command Bus Cycles Command Read Array Read Device Identifier Bus Cycles 1 ≥2 ≥2 2 1 2 ≥2 >2 2 1 1 2 2 2 2 2 2 First Bus Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr1 PnA PnA PnA PnA X WA WA WA BA X X BA BA BA PRA LRA RCD Data2 0xFF 0x90 0x98 0x70 0x50 0x40/ 0x10 0xE8 0x80 0x20 0xB0 0xD0 0x60 0x60 0x60 0xC0 0xC0 0x60 Write Write Write Write Write Write BA BA BA PRA LRA RCD 0x01 0xD0 0x2F PD LRD 0x03 Write Write Write Write WA WA WA BA WD N-1 0xD0 0xD0 Read Read Read PBA+IA ID Second Bus Cycle Oper Addr1 Data2 Read CFI Query Read Status Register Clear Status Register Word Program PnA+QA QD PnA SRD Program Buffered Program3 Buffered Enhanced Factory Program (Buffered EFP)4 Erase Suspend Block Erase Program/Erase Suspend Program/Erase Resume Block Locking/ Unlocking Lock Block Unlock Block Lock-down Block Program Protection Register Protection Program Lock Register Configuration Program Read Configuration Register NOTES: 1. First command cycle address should be the same as the operation’s target address. PnA = Address within the partition. PBA = Partition base address. IA = Identification code address offset. QA = CFI Query address offset. BA = Address within the block. WA = Word address of memory location to be written. PRA = Protection Register address. LRA = Lock Register address. X = Any valid address within the device. 2. ID = Identifier data. QD = Query data on D[15:0]. SRD = Status Register data. WD = Word data. N = Word count of data to be loaded into the write buffer. PD = Protection Register data. PD = Protection Register data. LRD = Lock Register data. RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition. 3. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming operation. 4. The confirm command (0xD0) is followed by the buffer data. Datasheet 19 28F640L30, 28F128L30, 28F256L30 3.3 Command Definitions Valid device command codes and descriptions are shown in Table 6. Table 6. Mode Command Codes and Definitions (Sheet 1 of 2) Description Places the addressed partition in Read Array mode. Array data is output on D[15:0]. Places the addressed partition in Read Status Register mode. The partition enters this mode after a program or erase command is issued. Status Register data is output on D[7:0]. Places the addressed partition in Read Device Identifier mode. Subsequent reads from addresses within the partition outputs manufacturer/device codes, Configuration Register data, Block Lock status, or Protection Register data on D[15:0]. Code Device Mode 0xFF Read Array Read Status 0x70 Register Read Device ID or 0x90 Configuration Register 0x98 Read Query 0x50 Read 0x40 0x10 Write 0xE8 0xD0 0x80 0xD0 0x20 Erase 0xD0 0xB0 Suspend 0xD0 Places the addressed partition in Read Query mode. Subsequent reads from the partition addresses output Common Flash Interface information on D[7:0]. Clear Status The WSM can only set Status Register error bits. The Clear Status Register command is used Register to clear the SR error bits. First cycle of a 2-cycle programming command; prepares the CUI for a write operation. On the next write cycle, the address and data are latched and the WSM executes the programming algorithm at the addressed location. During program operations, the partition responds only to Word Program Read Status Register and Program Suspend commands. CE# or OE# must be toggled to Setup update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array read. The Read Array command must be issued to read array data after programming has finished. Alternate Word Program Equivalent to the Word Program Setup command, 0x40. Setup Buffered This command loads a variable number of bytes up to the buffer size of 32 words onto the Program program buffer. Buffered The confirm command is Issued after the data streaming for writing into the buffer is done. This Program instructs the WSM to perform the Buffered Program algorithm, writing the data from the buffer Confirm to the flash memory array. Buffered First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode Enhanced (Buffered EFP). The CUI then waits for the Buffered EFP Confirm command, 0xD0, that Factory initiates the Buffered EFP algorithm. All other commands are ignored when Buffered EFP mode Programming begins. Setup Buffered EFP If the previous command was Buffered EFP Setup (0x80), the CUI latches the address and Confirm data, and prepares the device for Buffered EFP mode. First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The WSM Block Erase performs the erase algorithm on the block addressed by the Erase Confirm command. If the Setup next command is not the Erase Confirm (0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and places the addressed partition in read status register mode. If the first command was Block Erase Setup (0x20), the CUI latches the address and data, and the WSM erases the addressed block. During block-erase operations, the partition responds Block Erase only to Read Status Register and Erase Suspend commands. CE# or OE# must be toggled to Confirm update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array read. This command issued to any device address initiates a suspend of the currently-executing Program or program or block erase operation. The Status Register indicates successful suspend operation Erase by setting either SR[2] (program suspended) or SR[6] (erase suspended), along with SR[7] Suspend (ready). The Write State Machine remains in the suspend mode regardless of control signal states (except for RST# asserted). Suspend This command issued to any device address resumes the suspended program or block-erase Resume operation. 20 Datasheet 28F640L30, 28F128L30, 28F256L30 Table 6. Mode Command Codes and Definitions (Sheet 2 of 2) Description First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. If the previous command was Block Lock Setup (0x60), the addressed block is locked. If the previous command was Block Lock Setup (0x60), the addressed block is unlocked. If the addressed block is in a lock-down state, the operation has no effect. If the previous command was Block Lock Setup (0x60), the addressed block is locked down. First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock Register program operation. The second cycle latches the register address and data, and starts the programming algorithm First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the Set Read Configuration Register command (0x03) is not the next command, the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. If the previous command was Read Configuration Register Setup (0x60), the CUI latches the address and writes A[15:0] to the Read Configuration Register. Following a Configure Read Configuration Register command, subsequent read operations access array data. Code Device Mode 0x60 Lock Block Setup Block 0x01 Lock Block Locking/ Unlocking 0xD0 Unlock Block Lock-Down Block Program Protection Protection 0xC0 Register Setup Read Configuration 0x60 Register ConfiguSetup ration Read 0x03 Configuration Register 0x2F Datasheet 21 28F640L30, 28F128L30, 28F256L30 4.0 Read Operations The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power-up or a reset. The Read Configuration Register must be configured to enable synchronous burst reads of the flash memory array (see Section 4.3, “Read Configuration Register (RCR)” on page 23). Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read Status or Read Query. Upon power-up, or after a reset, all partitions of the device default to Read Array. To change a partition’s read state, the appropriate read command must be written to the device (see Section 3.2, “Device Commands” on page 18). See Section 9.0, “Special Read States” on page 47 for details regarding Read Status, Read ID, and CFI Query modes. The following sections describe read-mode operations in detail. 4.1 Asynchronous Page-Mode Read Following a device power-up or reset, asynchronous page mode is the default read mode and all partitions are set to Read Array. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array. Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit RCR[15] is set (see Section 4.3, “Read Configuration Register (RCR)” on page 23). To perform an asynchronous page-mode read, an address is driven onto A[MAX:0], and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is de-asserted during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated and ADV# must be tied to ground. Array data is driven onto D[15:0] after an initial access time tAVQV delay. (see Section 12.0, “AC Characteristics” on page 55). In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on A[MAX:0] is driven onto D[15:0] after the initial access delay. Address bits A[MAX:2] select the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the data buffer at any given time. 4.2 Synchronous Burst-Mode Read Read Configuration register bits CR[15:0] must be set before synchronous burst operation can be performed. Synchronous burst mode can be performed for both array and non-array reads such as Read ID, Read Status or Read Query. (See Section 4.3, “Read Configuration Register (RCR)” on page 23 for details). Synchronous burst mode outputs 4-, 8-, 16-, or continuous-words. To perform a synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access, in which case the address is latched on the next valid CLK edge while ADV# is asserted. 22 Datasheet 28F640L30, 28F128L30, 28F256L30 During synchronous array and non-array read modes, the first word is output from the data buffer on the next valid CLK edge after the initial access latency delay (see Section 4.3.2, “Latency Count” on page 24). Subsequent data is output on valid CLK edges following a minimum delay. However, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. During synchronous read operations, WAIT is driven with respect to OE# assertion. WAIT indicates invalid data when asserted, and valid data when de-asserted with respect to a valid clock edge. See Figure 16 through Figure 18 for additional details. 4.2.1 Burst Suspend The Burst Suspend feature of the device can reduce or eliminate the initial access latency incurred when system software needs to suspend a burst sequence that is in progress in order to retrieve data from another device on the same system bus. The system processor can resume the burst sequence later. Burst suspend provides maximum benefit in non-cache systems. Burst accesses can be suspended during the initial access latency (before data is received) or after the device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed without limit as long as device operation conditions are met. Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it is at VIH or VIL. WAIT is in High-Z during OE# de-assertion. To resume the burst access, OE# is reasserted, and CLK is restarted. Subsequent CLK edges resume the burst sequence. Within the device, CE# and OE# gate WAIT. Therefore, during Burst Suspend WAIT is placed in high-impedance state when OE# is de-asserted and resumed active when OE# is re-asserted. See Figure 19, “Burst Suspend Timing” on page 59. 4.3 Read Configuration Register (RCR) The RCR is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read Configuration Register command (see Section 3.2, “Device Commands” on page 18). RCR contents can be examined using the Read Device Identifier command, and then reading from + 0x05 (see Section 9.2, “Read Device Identifier” on page 48). The RCR is shown in Table 7. The following sections describe each RCR bit. Table 7. Read Configuration Register Description (Sheet 1 of 2) Read Configuration Register (RCR) Read Mode RES Latency Count WAIT Polarity Data Hold WAIT Delay Burst Seq CLK Edge RES RES Burst Wrap Burst Length RM 15 Bit R 14 13 LC[2:0] 12 11 WP 10 DH 9 WD 8 BS 7 CE 6 R 5 R 4 BW 3 2 BL[2:0] 1 0 Name Description Datasheet 23 28F640L30, 28F128L30, 28F256L30 Table 7. 15 14 Read Configuration Register Description (Sheet 2 of 2) Read Mode (RM) Reserved (R) Latency Count (LC[2:0]) 0 = Synchronous burst-mode read 1 = Asynchronous page-mode read (default) Reserved bits should be cleared (0) 010 =Code 2 011 =Code 3 100 =Code 4 101 =Code 5 110 =Code 6 111 =Code 7 (default) (Other bit settings are reserved) 0 =WAIT signal is active low 1 =WAIT signal is active high (default) 0 =Data held for a 1-clock data cycle 1 =Data held for a 2-clock data cycle (default) 0 =WAIT de-asserted with valid data 1 =WAIT de-asserted one data cycle before valid data (default) 0 =Reserved 1 =Linear (default) 0 = Falling edge 1 = Rising edge (default) Reserved bits should be cleared (0) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0] 1 =No Wrap; Burst accesses do not wrap within burst length (default) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =Continuous-word burst (default) (Other bit settings are reserved) 13:11 10 9 8 7 6 5:4 3 2:0 Wait Polarity (WP) Data Hold (DH) Wait Delay (WD) Burst Sequence (BS) Clock Edge (CE) Reserved (R) Burst Wrap (BW) Burst Length (BL[2:0]) NOTE: Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) Wait must be de-asserted with valid data (WD = 0). Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) Wait de-asserted one data cycle before valid data (WD = 1) combination is not supported. 4.3.1 Read Mode The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is cleared, synchronous burst mode is selected. 4.3.2 Latency Count The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data word is to be driven onto D[15:0]. The input clock frequency is used to determine this value. Figure 4 shows the data output latency for the different settings of LC[2:0]. Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however, a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word boundary is crossed. If CR.[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT states. 24 Datasheet 28F640L30, 28F128L30, 28F256L30 Refer to Table 8, “LC and Frequency Support for Bin 1 tAVQV/tCHQV (85ns / 17ns)” on page 25 and Table 9, “LC and Frequency Support for Bin 2 tAVQV/tCHQV (110ns / 20ns)” on page 26 for Latency Code Settings. Figure 4. First-Access Latency Count CLK[C] Valid Address Address [A] ADV#[V] Code0(Reserved) DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Code1 (Reserved Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Code2 Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Code3 Valid Output Valid Output Valid Output Valid Output Valid Output Code4 Valid Output Valid Output Valid Output Valid Output Code5 Valid Output Valid Output Valid Output Code6 Valid Output Valid Output Code7 Valid Output Table 8. LC and Frequency Support for Bin 1 tAVQV/tCHQV (85ns / 17ns) Latency Count Settings 2 3 4, 5, 6, or 7 Frequency Support (MHz) ≤ 27 ≤ 40 ≤ 52 Datasheet 25 28F640L30, 28F128L30, 28F256L30 Table 9. LC and Frequency Support for Bin 2 tAVQV/tCHQV (110ns / 20ns) Latency Count Settings 2 3 4, 5, 6, or 7 Frequency Support (MHz) ≤ 22 ≤ 33 ≤40 See Figure 5, “Example Latency Count Setting using Code 3. Figure 5. Example Latency Count Setting using Code 3 0 1 2 3 tData 4 CLK CE# ADV# A[MAX:0] Code 3 Address D[15:0] High-Z Data R103 4.3.3 WAIT Polarity The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT. When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is asserted-low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted, RST# deasserted). 4.3.3.1 WAIT Signal Function The WAIT signal indicates data valid when the device is operating in synchronous mode (CR[15]=0). The WAIT signal is only “de-asserted” when data is valid on the bus. When the device is operating in synchronous non-array read mode, such as read status, read ID, or read query. The WAIT signal is also “de-asserted” when data is valid on the bus. When the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, WAIT is set to a de-asserted state as determined by CR[10]. See Figure 14, “Asynchronous Single-Word Read (ADV# Latch)” on page 57, and Figure 15, “Asynchronous Page-Mode Read Timing” on page 57. 26 Datasheet 28F640L30, 28F128L30, 28F256L30 Table 10. WAIT Summary Table CONDITION WAIT CE# = VIH CE# = VIL OE# = VIH OE# = VIL Synchronous Array Reads Synchronous Non-Array Reads All Asynchronous Reads and all Writes High-Z Active High-Z Active Active Active De-asserted NOTE: Active: WAIT is asserted until data becomes valid, then de-asserts 4.3.4 Data Hold For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid on D[15:0] for one or two clock cycles. This period of time is called the “data cycle”. When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock (see Figure 6). The processor’s data setup time and the flash memory’s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for determining the Data Hold configuration is shown below: To set the device at one clock data hold for subsequent reads, the following condition must be satisfied: tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns) tDATA = Data set up to Clock (defined by CPU) For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming tCHQV = 20 ns and tDATA = 4ns. Applying these values to the formula above: 20 ns + 4 ns ≤ 25 ns The equation is satisfied and data will be available at every clock period with data hold setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods must be used. Figure 6. Data Hold Timing CLK [C] 1 CLK Data Hold 2 CLK Data Hold D[15:0] [Q] Valid Output Valid Output Valid Output D[15:0] [Q] Valid Output Valid Output Datasheet 27 28F640L30, 28F128L30, 28F256L30 4.3.5 WAIT Delay The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before valid data is output on DQ[15:0]. When WD is set, WAIT is de-asserted one data cycle before valid data (default). When WD is cleared, WAIT is de-asserted during valid data. 4.3.6 Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. Table 11 shows the synchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW) setting. Table 11. Burst Sequence Word Ordering Start Addr. (DEC) 0 1 2 3 4 5 6 7 14 15 … 0 1 2 3 4 5 6 7 14 15 … … Burst Addressing Sequence (DEC) Burst Wrap (RCR[3]) 0 0 0 0 0 0 0 0 … 0 0 … 1 1 1 1 1 1 1 1 … 1 1 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 … … 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 … … 4-Word Burst (BL[2:0] = 0b001) 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8-Word Burst (BL[2:0] = 0b010) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 … … 16-Word Burst (BL[2:0] = 0b011) 0-1-2-3-4…14-15 1-2-3-4-5…15-0 2-3-4-5-6…15-0-1 3-4-5-6-7…15-0-1-2 4-5-6-7-8…15-0-1-2-3 5-6-7-8-9…15-0-1-2-3-4 6-7-8-9-10…15-0-1-2-3-4-5 7-8-9-10…15-0-1-2-3-4-5-6 14-15-0-1-2…12-13 15-0-1-2-3…13-14 0-1-2-3-4…14-15 1-2-3-4-5…15-16 2-3-4-5-6…16-17 3-4-5-6-7…17-18 4-5-6-7-8…18-19 5-6-7-8-9…19-20 6-7-8-9-10…20-21 7-8-9-10-11…21-22 14-15-16-17-18…28-29 15-16-17-18-19…29-30 … … … Continuous Burst (BL[2:0] = 0b111) 0-1-2-3-4-5-6-… 1-2-3-4-5-6-7-… 2-3-4-5-6-7-8-… 3-4-5-6-7-8-9-… 4-5-6-7-8-9-10… 5-6-7-8-9-10-11… 6-7-8-9-10-11-12-… 7-8-9-10-11-12-13… 14-15-16-17-18-19-20-… 15-16-17-18-19-20-21-… 0-1-2-3-4-5-6-… 1-2-3-4-5-6-7-… 2-3-4-5-6-7-8-… 3-4-5-6-7-8-9-… 4-5-6-7-8-9-10… 5-6-7-8-9-10-11… 6-7-8-9-10-11-12-… 7-8-9-10-11-12-13… 14-15-16-17-18-19-20-… 15-16-17-18-19-20-21-… … … … 4.3.7 Clock Edge The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT. 4.3.8 Burst Wrap The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. When BW is set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence’s start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word 28 Datasheet 28F640L30, 28F128L30, 28F256L30 boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs. 4.3.9 Burst Length The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 11, “Burst Sequence Word Ordering” on page 28). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space. Datasheet 29 28F640L30, 28F128L30, 28F256L30 5.0 Programming Operations The device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (Buffered EFP) (80h, D0h). See Section 3.0, “Device Operations” on page 17 for details on the various programming commands issued to the device. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be deasserted and the block must be unlocked before attempting to program the block. Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and termination of the operation. See Section 7.0, “Security Modes” on page 38 for details on locking and unlocking blocks. The following sections describe device programming in detail. 5.1 Word Programming Word programming operations are initiated by writing the Word Program Setup command to the device (see Section 3.0, “Device Operations” on page 17). This is followed by a second write to the device with the address and data to be programmed. The partition accessed during both write cycles outputs Status Register data when read. The partition accessed during the second cycle (the data cycle) of the program command sequence is the location where the data is written. See Figure 30, “Word Program Flowchart” on page 74. Programming can occur in only one partition at a time; all other partitions must be in a read state or in erase suspend. VPP must be above VPPLK, and within the specified VPPL min/max values (nominally 1.8 V). During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.” Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 6.0, “Erase Operations” on page 36). The Status Register can be examined for programming progress and errors by reading any address within the partition that is being programmed. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing programming progress to be monitored at that partition’s address. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the programming partition during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed. 30 Datasheet 28F640L30, 28F128L30, 28F256L30 5.1.1 Factory Word Programming Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with VPP = VPPH. This can enable faster programming times during OEM manufacturing processes. Factory word programming is not intended for extended use. See Section 11.2, “Operating Conditions” on page 52 for limitations when VPP = VPPH. Note: When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH, the device draws programming current from the VPP supply. Figure 7, “Example VPP Supply Connections” on page 35 shows examples of device power supply configurations. 5.2 Buffered Programming The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 3.2, “Device Commands” on page 18), Status Register information is updated and reflects the availability of the buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 32, “Buffered Program Flowchart” on page 76). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). A misaligned starting address doubles the total program time. After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. Reading from another partition is allowed while data is being programmed into the array from the write buffer (see Figure 38, “Read While Buffered Programming Flowchart” on page 82). When Buffered Programming has completed, an additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with VPP = VPPL or VPPH (see Section 11.2, “Operating Conditions” on page 52 for limitations when operating the device with VPP = VPPH). When Status Register bits SR[5,4] are set, the device does not accept Buffered Program commands. If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. Datasheet 31 28F640L30, 28F128L30, 28F256L30 If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command. 5.3 Buffered Enhanced Factory Programming Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash programming for today's beat-rate-sensitive manufacturing environments. The enhanced programming algorithm used in Buffered EFP eliminates traditional programming elements that drive up overhead in device programmer systems. Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 33, “Buffered EFP Flowchart” on page 77). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of Buffered EFP saves host programming equipment the address-bus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM’s internal verification to ensure that the device has programmed properly. This eliminates the external postprogram verification and its associated overhead. 5.3.1 Buffered EFP Requirements and Considerations Buffered EFP requirements: • • • • • Ambient temperature: TA = 25°C, ±5°C VCC within specified operating range. VPP driven to VPPH. Target block unlocked before issuing the Buffered EFP Setup and Confirm commands. The first-word address (WA0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired. • WA0 must align with the start of an array buffer boundary1. Buffered EFP considerations: • • • • For optimum performance, cycling must be limited below 100 erase cycles per block2. Buffered EFP programs one block at a time; all buffer data must fall within a single block3. Buffered EFP cannot be suspended. Programming to the flash memory array can occur only when the buffer is full4. 32 Datasheet 28F640L30, 28F128L30, 28F256L30 • Read operation while performing Buffered EFP is not supported. NOTES: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF. 5.3.2 Buffered EFP Setup Phase After receiving the Buffered EFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and Buffered EFP operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect VPP level. Note: Reading from the device after the Buffered EFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer. 5.3.3 Buffered EFP Program/Verify Phase After the Buffered EFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the Buffered EFP program/verify phase is activated. SR[0] indicates the write buffer is available. Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For Buffered EFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm will be aborted and the program fail (SR[4]) flag will be set. Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is only necessary on a block basis after Buffered EFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR.0 = 0 and the device is ready for the next buffer fill. Datasheet 33 28F640L30, 28F128L30, 28F256L30 Note: Any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. The host programming system continues the Buffered EFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block’s range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the Buffered EFP Exit phase. 5.3.4 Buffered EFP Exit Phase When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed on the partition being programmed at this time to ensure the entire block programmed successfully. When exiting the Buffered EFP algorithm with a block address change, the read mode of both the programmed and the addressed partition will not change. After Buffered EFP exit, any valid command can be issued to the device. 5.4 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from memory locations other than the one being programmed. The Program Suspend command can be issued to any device address; the corresponding partition is not affected. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 31, “Program Suspend/Resume Flowchart” on page 75). When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 12.3, “Program and Erase Characteristics” on page 64. To read data from blocks within the suspended partition, the Read Array command must be issued to that partition. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Program Resume are valid commands during a program suspend. A program operation does not need to be suspended in order to read data from a block in another partition that is not programming. If the other partition is already in a Read Array, Read Device Identifier, or CFI Query state, issuing a valid address returns corresponding read data. If the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. During a program suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at its programming level, and WP# must remain unchanged while in program suspend. If RST# is asserted, the device is reset. 34 Datasheet 28F640L30, 28F128L30, 28F256L30 5.5 Program Resume The Resume command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any partition. When read at the partition that’s programming, the device outputs data corresponding to the partition’s last state. If error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 31, “Program Suspend/Resume Flowchart” on page 75). 5.6 Program Protection When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level error. Block lock registers are not affected by the voltage level on VPP; they may still be programmed and read, even if VPP is less than VPPLK. Figure 7. Example VPP Supply Connections VCC VPP 10 KΩ VCC VPP VCC PROT# VCC VPP Factory Word Programming with VPP = VPPH Complete Write/Erase Protection when VPP < VPPLK VCC VPP = VPPH VCC VPP Low Voltage Programming Only Logic Control of Device Protection VCC VCC VPP Low Voltage and Factory Word Programming Low Voltage Programming Only Full Device Protection Unavailable Datasheet 35 28F640L30, 28F128L30, 28F256L30 6.0 Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. 6.1 Block Erase Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 3.2, “Device Commands” on page 18). Next, the Block Erase Confirm command is written to the address of the block to be erased. Erasing can occur in only one partition at a time; all other partitions must be in a read state. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 34, “Block Erase Flowchart” on page 78). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones.” Memory array bits that are ones can be changed to zeros only by programming the block (see Section 5.0, “Programming Operations” on page 30). The Status Register can be examined for block erase progress and errors by reading any address within the partition that is being erased. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing erase progress to be monitored at that partition’s address. SR[0] indicates whether the addressed partition or another partition is erasing. The partition’s Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because VPP was outside of its acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed. 6.2 Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address; the corresponding partition is not affected. A block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 31, “Program Suspend/Resume Flowchart” on page 75). 36 Datasheet 28F640L30, 28F128L30, 28F256L30 When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 12.3, “Program and Erase Characteristics” on page 64. To read data from blocks within the suspended partition (other than an erase-suspended block), the Read Array command must be issued to that partition first. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. To read data from a block in a partition that is not erasing, the erase operation does not need to be suspended. If the other partition is already in Read Array, Read Device Identifier, or CFI Query, issuing a valid address returns corresponding data. If the other partition is not in a read state, one of the read commands must be issued to the partition before data can be read. During an erase suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If RST# is asserted, the device is reset. 6.3 Erase Resume The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any partition. When read at the partition that’s erasing, the device outputs data corresponding to the partition’s last state. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 31, “Program Suspend/Resume Flowchart” on page 75). 6.4 Erase Protection When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error. Datasheet 37 28F640L30, 28F128L30, 28F256L30 7.0 Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 7.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block Lock-Down command along with asserting WP#. Also, VPP data security can be used to inhibit program and erase operations (see Section 5.6, “Program Protection” on page 35 and Section 6.4, “Erase Protection” on page 37). 7.1.1 Lock Block To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block’s address (see Section 3.2, “Device Commands” on page 18 and Figure 36, “Block Lock Operations Flowchart” on page 80). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits may be modified and/or read even if VPP is below VPPLK. 7.1.2 Unlock Block The Unlock Block command is used to unlock blocks (see Section 3.2, “Device Commands” on page 18). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 8, “Block Locking State Diagram” on page 39). 7.1.3 Lock-Down Block A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 3.2, “Device Commands” on page 18). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to lockeddown state, a Lock-Down command must be issued prior to changing WP# to VIL. Locked-down blocks revert to the locked state upon reset or power up the device (see Figure 8, “Block Locking State Diagram” on page 39). 38 Datasheet 28F640L30, 28F128L30, 28F256L30 7.1.4 Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 9.2, “Read Device Identifier” on page 48). Data bits D[1:0] display the addressed block’s lock status; D0 is the addressed block’s lock bit, while D1 is the addressed block’s lock-down bit. Figure 8. Block Locking State Diagram UNLOCKED 60h/ D0h [000] 60 h/2 Fh LOCKED 60h/01h [001] WP# = VIL = 0 60h/ 2Fh Power-Up/Reset Default [011] Locked-down 60h/D0h [110] 60h/ 01h [111] Locked-down is disabled by WP# = VIH WP# = VIH = 1 60h/ D0h [100] 60h/ 2Fh 60h/ 2Fh Power-Up/Reset Default 60h/ 01h [101] 60h/D0h = Unlock Command 60h/01h = Lock Command 60h/2Fh = Lock-Down Command 7.1.5 Block Locking During Suspend Block lock and unlock changes can be performed during an erase suspend. To change block locking during an erase operation, first issue the Erase Suspend command. Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept another command. Next, write the desired lock command sequence to a block, which changes the lock state of that block. After completing block lock or unlock operations, resume the erase operation using the Erase Resume command. Datasheet 39 28F640L30, 28F128L30, 28F256L30 Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block, or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed. Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See Appendix A, “Write State Machine (WSM)” on page 67, which shows valid commands during an erase suspend. 7.2 Protection Registers The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64bit segment is pre-programmed at the factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 9, “Protection Register Map” on page 41). The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked 40 Datasheet 28F640L30, 28F128L30, 28F256L30 . Figure 9. Protection Register Map 0x109 128-bit Protection Register 16 (User-Programmable) 0x102 0x91 128-bit Protection Register 1 (User-Programmable) 0x8A Lock Register 1 0x89 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x88 64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0 0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-Bit Protection Register 0 64-bit Segment (Factory-Programmed) 7.2.1 Reading the Protection Registers The Protection Registers can be read from within any partition’s address space. To read the Protection Register, first issue the Read Device Identifier command at any partitions’ address to place that partition in the Read Device Identifier state (see Section 3.2, “Device Commands” on page 18). Next, perform a read operation at that partition’s base address plus the address offset corresponding to the register to be read. Table 14, “Device Identifier Information” on page 49 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time. Note: If a program or erase operation occurs within the device while it is reading a Protection Register, certain restrictions may apply. See Table 12, “Simultaneous Operation Restrictions” on page 46 for details. Datasheet 41 28F640L30, 28F128L30, 28F256L30 7.2.2 Programming the Protection Registers To program any of the Protection Registers, first issue the Program Protection Register command at the parameter partition’s base address plus the offset to the desired Protection Register (see Section 3.2, “Device Commands” on page 18). Next, write the desired Protection Register data to the same Protection Register address (see Figure 9, “Protection Register Map” on page 41). The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 37, “Protection Register Programming Flowchart” on page 81). Issuing the Program Protection Register command outside of the Protection Register’s address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set). Note: If a program or erase operation occurs when programming a Protection Register, certain restrictions may apply. See Table 12, “Simultaneous Operation Restrictions” on page 46 for details. 7.2.3 Locking the Protection Registers Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 3.2, “Device Commands” on page 18). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 14, “Device Identifier Information” on page 49). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. The other bits in Lock Register 0 are not used. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: After being locked, the Protection Registers cannot be unlocked. 42 Datasheet 28F640L30, 28F128L30, 28F256L30 8.0 Dual-Operation Considerations The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. 8.1 Memory Partitioning The L30 flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous read-while-write operations. Simultaneous program and erase is not allowed. Only one partition at a time can be in program or erase mode. The flash device supports read-while-write operations with bus cycle granularity and not command granularity. In other words, it is not assumed that both bus cycles of a two cycle command (an erase command for example) will always occur as back to back bus cycles to the flash device. In practice, code fetches (reads) may be interspersed between write cycles to the flash device, and they will likely be directed to a different partition than the one being written. This is especially true when a processor is executing code from one partition that instructs the processor to program or erase in another partition. 8.2 Read-While-Write Command Sequences When issuing commands to the device, a read operation can occur between 2-cycle Write command’s (Figure 10, and Figure 11). However, a write operation issued between a 2-cycle commands write sequence causes a command sequence error. (See Figure 12) When reading from the same partition after issuing a Setup command, Status Register data is returned, regardless of the read mode of the partition prior to issuing the Setup command. . Figure 10. Operating Mode with Correct Command Sequence Example A ddress [A] WE# [W] OE# [G] Data [D/Q] 0x20 0xD0 0xFF Partition A Partition A Partition B Datasheet 43 28F640L30, 28F128L30, 28F256L30 Figure 11. Operating Mode with Correct Command Sequence Example A ddress [A] WE# [W] OE# [G] Data [D/Q] 0x20 Valid Array Data 0xD0 Partition A Partition B Partition A Figure 12. Operating Mode with Illegal Command Sequence Example A ddress [A] WE# [W] OE# [G] Data [D/Q] 0x20 0xFF 0xD0 SR[7:0] Partition A Partition B Partition A Partition A 8.2.1 Simultaneous Operation Details The L30 flash memory device supports simultaneous read from one partition while programming or erasing in any other partition. Certain features like the Protection Registers and Query data have special requirements with respect to simultaneous operation capability. These will be detailed in the following sections. 8.2.2 Synchronous and Asynchronous Read-While-Write Characteristics and Waveforms This section describes the transitions of write operation to asynchronous read, and synchronous read to write operation. 8.2.2.1 Write operation to asynchronous read transition W18 - tWHAV The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when transitioning from a write cycle (WE# going high) to perform an asynchronous read (only address valid is required). W19 and W20 - tWHCV and tWHVH The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high to latch a new address must be met. 44 Datasheet 28F640L30, 28F128L30, 28F256L30 8.2.2.2 Synchronous read to write operation transition W21 - tVHWL W22 - tCHWL The AC parameters W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high to WE# low) are required when the device is in a synchronous mode and clock is active. A write bus cycle consists of two parts: • the host provides an address to the flash device; and • the host then provides data to the flash device. The flash device in turn binds the received data with the received address. When operating synchronously (RCR.15 = 0), the address of a write cycle may be provided to the flash by the first active clock edge with ADV# low, or rising edge of ADV# as long as the applicable cycle separation conditions are met between each cycle. If neither a clock edge nor a rising ADV# edge is used to provide a new address at the beginning of a write cycle (the clock is stopped and ADV# is low), the address may also be provided to the flash device by holding the address bus stable for the required amount of time (W5, tAVWH) before the rising WE# edge. Alternatively, the host may choose not to provide an address to the flash device during subsequent write cycles (if ADV# is high and only CE# or WE# is toggled to separate the prior cycle from the current write cycle). In this case, the flash device will use the most recently provided address from the host. Refer to Figure 22, “Write to Asynchronous Read Timing” on page 62, Figure 23, “Synchronous Read to Write Timing” on page 62, and Figure 24, “Write to Synchronous Read Timing” on page 63, for representation of these timings. 8.2.3 Read Operation During Buffered Programming Flowchart The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. To perform a read while buffered programming operation, first issue a Buffered Program set up command in a partition. When a read operation occurs in the same partition after issuing a setup command, Status Register data will be returned, regardless of the read mode of the partition prior to issuing the setup command. To read data from a block in other partition and the other partition already in read array mode, a new block address must be issued. However, if the other partition is not already in read array mode, issuing a read array command will cause the buffered program operation to abort and a command sequence error would be posted in the Status Register. See Figure 38, “Read While Buffered Programming Flowchart” on page 82 for more details. Note: Simultaneous read-while-Buffered EFP is not supported. Datasheet 45 28F640L30, 28F128L30, 28F256L30 8.3 Simultaneous Operation Restrictions Since the L30 flash memory device supports simultaneous read from one partition while programming or erasing in another partition, certain features like the Protection Registers and CFI Query data have special requirements with respect to simultaneous operation capability. (Table 12 provides details on restrictions during simultaneous operations.) Table 12. Simultaneous Operation Restrictions Protection Register or CFI data Parameter Partition Array Data Other Partitions Notes Read (See Notes) Read Write No Access Allowed While programming or erasing in a main partition, the Protection Register or CFI data may be read from any other partition. (See Notes) Write/Erase Reading the parameter partition array data is not allowed if the Protection Register or Query data is being read from addresses within the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Read Write/Erase Accessing the Protection Registers or CFI data from parameter partition addresses is not allowed when reading array data from the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Read Write/Erase Accessing the Protection Registers or CFI data in a partition that is different from the one being programed/erased, and also different from the parameter partition is allowed. While programming the Protection Register, reads are only allowed in the other main partitions. No Access Read Access to array data in the parameter partition is not allowed. Allowed Programming of the Protection Register can only occur in the parameter partition, which means this partition is in Read Status. While programming or erasing the parameter partition, reads of the Protection Registers or CFI data are not allowed in any partition. Write/Erase Read Reads in partitions other than the main partitions are supported. 46 Datasheet 28F640L30, 28F128L30, 28F256L30 9.0 Special Read States The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous single-word mode. When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. Each partition can be in one of its read states independent of other partitions’ modes. See Figure 13, “Asynchronous Single-Word Read (ADV# Low)” on page 56, Figure 14, “Asynchronous Single-Word Read (ADV# Latch)” on page 57, and Figure 16, “Synchronous Single-Word Array or Non-array Read Timing” on page 58 for details. 9.1 Read Status Register The status of any partition is determined by reading the Status Register from the address of that particular partition. To read the Status Register, issue the Read Status Register command within the desired partition’s address range. Status Register information is available at the partition address to which the Read Status Register, Word Program, or Block Erase command was issued. Status Register data is automatically made available following a Word Program, Block Erase, or Block Lock command sequence. Reads from a partition after any of these command sequences outputs that partition’s status until another valid command is written to that partition (e.g. Read Array command). The Status Register is read using single asynchronous-mode or synchronous burst mode reads. Status Register data is output on D[7:0], while 0x00 is output on D[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. The Status Register read operations do not affect the read state of the other partitions. The Device Write Status bit (SR[7]) provides overall status of the device. The Partition Status bit (SR[0]) indicates whether the addressed partition or some other partition is actively programming or erasing. Status register bits SR[6:1] present status and error information about the program, erase, suspend, VPP, and block-locked operations. Table 13. Status Register Description (Sheet 1 of 2) Status Register (SR) Device Write Status DWS 7 Default Value = 0x80 Erase Status ES 5 Erase Suspend Status ESS 6 Program Status PS 4 VPP Status VPPS 3 Program Suspend Status PSS 2 BlockLocked Status BLS 1 Partition Status PWS 0 Bit 7 6 Name Device Write Status (DWS) Erase Suspend Status (ESS) Description 0 = Device is busy; program or erase cycle in progress; SR[0] valid. 1 = Device is ready; SR[6:1] are valid. 0 = Erase suspend not in effect. 1 = Erase suspend in effect. Datasheet 47 28F640L30, 28F128L30, 28F256L30 Table 13. Status Register Description (Sheet 2 of 2) Status Register (SR) 5 4 3 2 1 Erase Status (ES) Program Status (PS) VPP Status (VPPS) Program Suspend Status (PSS) Block-Locked Status (BLS) Default Value = 0x80 0 = Erase successful. 1 = Erase fail or program sequence error when set with SR[4,7]. 0 = Program successful. 1 = Program fail or program sequence error when set with SR[5,7] 0 = VPP within acceptable limits during program or erase operation. 1 = VPP < VPPLK during program or erase operation. 0 = Program suspend not in effect. 1 = Program suspend in effect. 0 = Block not locked during program or erase. 1 = Block locked during program or erase; operation aborted. DWS PWS 0 0 = Program or erase operation in addressed partition. 0 1 = Program or erase operation in other partition. 1 0 = No active program or erase operations. 1 1 = Reserved. (Non-buffered EFP operation. For Buffered EFP operation, see Section 5.3, “Buffered Enhanced Factory Programming” on page 32). 0 Partition Write Status (PWS) Always clear the Status Register prior to resuming erase operations. Avoids Status Register ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status. 9.1.1 Clear Status Register The Clear Status Register command clears the status register, leaving all partition read states unchanged. It functions independent of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2,0], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting a command sequence to avoid any ambiguity. A device reset also clears the Status Register. 9.2 Read Device Identifier The Read Device Identifier command instructs the addressed partition to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data when that partition’s addresses are read (see Section 3.2, “Device Commands” on page 18 for details on issuing the Read Device Identifier command). Table 14, “Device Identifier Information” on page 49 and Table 15, “Device ID codes” on page 49 show the address offsets and data values for this device. Issuing a Read Device Identifier command to a partition that is programming or erasing places that partition in the Read Identifier state while the partition continues to program or erase in the background. 48 Datasheet 28F640L30, 28F128L30, 28F256L30 Table 14. Device Identifier Information Item Manufacturer Code Device ID Code Block Lock Configuration: • Block Is Unlocked • Block Is Locked • Block Is not Locked-Down • Block Is Locked-Down Address(1,2) PBA + 0x00 PBA + 0x01 Data 0089h ID (see Table 15) Lock Bit: DQ0 = 0b0 BBA + 0x02 DQ0 = 0b1 DQ1 = 0b0 DQ1 = 0b1 Configuration Register Lock Register 0 64-bit Factory-Programmed Protection Register 64-bit User-Programmable Protection Register Lock Register 1 128-bit User-Programmable Protection Registers NOTES: 1. PBA = Partition Base Address. 2. BBA = Block Base Address. PBA + 0x05 PBA + 0x80 PBA + 0x81–0x84 PBA + 0x85–0x88 PBA + 0x89 PBA + 0x8A–0x109 Configuration Register Data PR-LK0 Factory Protection Register Data User Protection Register Data Protection Register Data PR-LK1 Table 15. Device ID codes Device Identifier Codes ID Code Type Device Density 64 Mbit 128 Mbit 256 Mbit –T –B (Top Parameter) (Bottom Parameter) 8811 8812 8813 8814 8815 8816 Device Code 9.3 CFI Query The CFI Query command instructs the device to output Common Flash Interface (CFI) data when partition addresses are read. See Section 3.2, “Device Commands” on page 18 for details on issuing the CFI Query command. Appendix C, “Common Flash Interface” on page 83 shows CFI information and address offsets within the CFI database. Issuing the CFI Query command to a partition that is programming or erasing places that partition’s outputs in the CFI Query state, while the partition continues to program or erase in the background. The CFI Query command is subject to read restrictions dependent on parameter partition availability, as described in Table 12, “Simultaneous Operation Restrictions” on page 46. Datasheet 49 28F640L30, 28F128L30, 28F256L30 10.0 10.1 Power and Reset Power-Up/Down Characteristics Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN. Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions. 10.2 Power Supply Decoupling Flash memory devices require careful power supply de-coupling. Three basic power supply current considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks produced when CE# and OE# are asserted and deasserted. When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Intel® Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor connected to a corresponding ground connection (e.g.VCCQ to VSSQ). High-frequency, inherently lowinductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor should be placed between power and ground close to the devices. The bulk capacitor is meant to overcome voltage droop caused by PCB trace inductance. 10.3 Automatic Power Saving (APS) Automatic Power Saving (APS) provides low power operation during a read’s active state. ICCAPS is the average current measured over any 5 ms time interval, 5 µs after CE# is deasserted. During APS, average current is measured over the same time interval 5 µs after the following events happen: (1) there is no internal read, program or erase operations cease; (2) CE# is asserted; (3) the address lines are quiescent and at VSSQ or VCCQ. OE# may also be driven during APS. 10.4 Reset Characteristics Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active-low reset signal used for CPU initialization. 50 Datasheet 28F640L30, 28F128L30, 28F256L30 Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. System designers should guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be asserted for a write operation, deasserting either signal inhibits writes to the device. The Command User Interface (CUI) architecture provides additional protection because alteration of memory contents can only occur after successful completion of a two-step command sequence (see Section 3.2, “Device Commands” on page 18). Datasheet 51 28F640L30, 28F128L30, 28F256L30 11.0 11.1 Warning: Thermal and DC Characteristics Absolute Maximum Ratings Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Parameter Temperature under bias Storage temperature Voltage on any signal (except VCC, VPP) VPP voltage VCC voltage VCCQ voltage Output short circuit current Maximum Rating –25 °C to +85 °C –65 °C to +125 °C –0.5 V to +3.8 V –0.2 V to +10 V –0.2 V to +2.5 V –0.2 V to +3.8 V 100 mA 1 1,2,3 1 1 4 Notes NOTES: 1. Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for periods