305433

Intel® 80333 I/O Processor Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data Cache with cache locking. Supports write through or write back — 2 KByte, 2-way Set Associative MiniData Cache — 128-Entry Branch Target Buffer — 8-Entry Write Buffer — 4-Entry Fill and Pend Buffer — Performance Monitor Unit Internal Bus 333 MHz/64-bit PCI Express*-to-PCI Bridges — x8 PCI Express* Upstream Link — PCI Express* Specification 1.0a compliant — PCI-X Bus A (IOP bus - ATU interface) — PCI-X Bus B (Slot Expansion bus) supports standard PCI Hot-Plug Controller — Four output clocks per PCI-X bus Address Translation Unit — 2 KB or 4 KB Outbound Read Queue — 4 KB Outbound Write Queue — 4 KB Inbound Read and Write Queue — Connects Internal Bus to PCI/X Bus A — Messaging Unit and Expansion ROM Two Programmable 32-bit Timers and Watchdog Timer Eight General Purpose I/O Pins Two I2C Bus Interface Units ■ ■ ■ ■ ■ ■ ■ Dual-Ported Memory Controller — PC2700 Double Data Rate (DDR333) SDRAM — DDRII 400 SDRAM — Up to 2 GB of 64-bit DDR333 — Up to 1 GB of 64-bit DDRII400 — Optional Single-bit Error Correction, Multi-bit Detection Support (ECC) — Supports Unbuffered or Registered DIMMs and Discrete SDRAM — 32-bit memory support DMA Controller — Two Independent Channels Connected to Internal Bus — Two 1KB Queues in Ch0 and Ch1 — CRC-32C Calculation Application Accelerator Unit — RAID6 support — Performs optional XOR on Read Data — Compute Parity Across Local Memory Blocks — 1 KB/512 byte Store Queue Two UART (16550) Units — 64-byte Receive and Transmit FIFOs — 4-pin, Master/Slave Capable Peripheral Bus Interface — 8-/16-bit Data Bus with Two Chip Selects Interrupt Controller Unit — Four Priority Levels — Vector Generation — Sixteen External Interrupt Pins with High Priority Interrupt (HPI#) 829-Ball, Flip Chip Ball Grid Array (FCBGA) — 37.5 mm2 and 1.27 mm ball pitch Order Number: 305433, Revision: 003US July 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. 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Copyright © 2005, Intel Corporation. All Rights Reserved. July 2005 2 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 003US Datasheet 80333 Contents 1.0 Introduction .................................................................................................................................... 7 1.1 About This Document ........................................................................................................... 7 1.1.1 Terminology ............................................................................................................. 7 1.1.2 Other Relevant Documents ..................................................................................... 8 About the Intel® 80333 I/O Processor................................................................................... 9 Intel XScale® Core..............................................................................................................11 PCI Express*-to-PCI Bridge Units ......................................................................................11 Address Translation Unit ....................................................................................................12 Memory Controller ..............................................................................................................12 Application Accelerator Unit................................................................................................12 Peripheral Bus Interface .....................................................................................................12 DMA Controller ...................................................................................................................13 I2C Bus Interface Unit .........................................................................................................13 Messaging Unit ...................................................................................................................13 Internal Bus.........................................................................................................................13 UART Units .........................................................................................................................13 Interrupt Controller Unit ......................................................................................................14 GPIO ...................................................................................................................................14 SMBus Unit .........................................................................................................................14 Functional Signal Descriptions ...........................................................................................15 Package Thermal Specifications ........................................................................................55 Absolute Maximum Ratings ................................................................................................56 VCCPLL Pin Requirements...................................................................................................56 Targeted DC Specifications ................................................................................................57 Targeted AC Specifications ................................................................................................59 4.4.1 Clock Signal Timings .............................................................................................59 4.4.2 DDR/DDR-II SDRAM Interface Signal Timings......................................................61 4.4.3 Peripheral Bus Interface Signal Timings................................................................63 4.4.4 I2C/SMBus Interface Signal Timings......................................................................65 4.4.5 UART Interface Signal Timings..............................................................................65 4.4.6 PCI Express* Differential Transmitter (Tx) Output Specifications..........................66 4.4.7 PCI Express* Differential Receiver (Rx) Input Specifications ................................67 4.4.8 Boundary Scan Test Signal Timings......................................................................68 AC Timing Waveforms ........................................................................................................69 AC Test Conditions.............................................................................................................73 1.2 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 3.0 3.1 3.2 4.0 4.1 4.2 4.3 4.4 Features ........................................................................................................................................11 Package Information ...................................................................................................................15 Electrical Specifications .............................................................................................................56 4.5 4.6 Figures 1 2 Intel® 80333 I/O Processor Functional Block Diagram ...............................................................10 829-Ball FCBGA Package Diagram............................................................................................37 Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 003US July 2005 3 80333 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Intel® 80333 I/O Processor Signal Group Locations (Bottom View) ........................................... 38 Intel® 80333 I/O Processor Ballout — Left Side (Bottom View) ................................................. 39 Intel® 80333 I/O Processor Ballout — Right Side (Bottom View) ............................................... 40 Clock Timing Measurement Waveforms..................................................................................... 69 Output Timing Measurement Waveforms ................................................................................... 69 Input Timing Measurement Waveforms...................................................................................... 70 I2C/SMBus Interface Signal Timings .......................................................................................... 70 UART Transmitter Receiver Timing............................................................................................ 70 DDR SDRAM Write Timings ....................................................................................................... 71 DDR SDRAM Read Timings....................................................................................................... 71 Write PreAmble/PostAmble Durations........................................................................................ 72 AC Test Load for All Signals Except PCI and DDR SDRAM ...................................................... 73 AC Test Load for DDR SDRAM Signals ..................................................................................... 73 PCI/PCI-X TOV(max) Rising Edge AC Test Load ...................................................................... 73 PCI/PCI-X TOV(max) Falling Edge AC Test Load ..................................................................... 74 PCI/PCI-X TOV(min) AC Test Load ........................................................................................... 74 Transmitter Test Load (100 Ω differential load) .......................................................................... 74 Transmitter Eye Diagram............................................................................................................ 75 Receiver Eye Opening (Differential) ........................................................................................... 75 Tables 1 2 4 3 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Description Nomenclature .................................................................................................... 15 DDR SDRAM Signals ................................................................................................................. 16 MISC SDRAM Signals ................................................................................................................ 17 DDR-II SDRAM Signals .............................................................................................................. 17 Peripheral Bus Interface Signals ................................................................................................ 18 PCI Express* Signals ................................................................................................................. 19 B PCI (Slot Expansion) Bus Signals ........................................................................................... 20 A PCI (IOP) Bus Signals............................................................................................................. 22 I2C/SMBus Signals ..................................................................................................................... 24 Interrupt Signals ......................................................................................................................... 24 Hot-Plug Controller Signals for Parallel 1-slot, No-Glue ............................................................. 25 UART Signals ............................................................................................................................. 26 Test and Miscellaneous Signals ................................................................................................. 28 Reset Strap Signals .................................................................................................................... 29 Power and Ground Pins ............................................................................................................. 31 Pin Mode Behavior ..................................................................................................................... 32 Pin Multiplexing for Functional Modes ........................................................................................ 36 FC-style, H-PBGA Package Dimensions.................................................................................... 37 829-Lead Package — Alphabetical Ball Listings ........................................................................ 41 829-Lead Package — Alphabetical Signal Listings .................................................................... 48 Absolute Maximum Ratings ........................................................................................................ 56 Operating Conditions .................................................................................................................. 56 DC Characteristics...................................................................................................................... 57 ICC Characteristics...................................................................................................................... 58 PCI Clock Timings ...................................................................................................................... 59 DDR Clock Timings .................................................................................................................... 59 PCI Express* Clock Timings....................................................................................................... 60 DDR SDRAM Signal Timings ..................................................................................................... 61 July 2005 4 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 003US Datasheet 80333 29 30 31 32 33 34 35 36 37 DDR-II SDRAM Signal Timings ..................................................................................................62 Peripheral Bus Signal Timings....................................................................................................63 PCI Signal Timings .....................................................................................................................64 I2C/SMBus Signal Timings .........................................................................................................65 UART Signal Timings .................................................................................................................65 PCI Express* Tx Output Specifications ......................................................................................66 PCI Express* Rx Input Specifications.........................................................................................67 Boundary Scan Test Signal Timings...........................................................................................68 AC Measurement Conditions......................................................................................................73 Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 003US July 2005 5 80333 Revision History Date July 2005 Revision 003 Updated voltages in Section 4.3 Revised: Table 16, modified pin mode behavior for DQ[63:32] for 32-bit DDR. May 2005 002 Table 21, modified Case Temperature Under Bias to 95 C Max Table 22, modified Case Temperature Under Bias to 95 C Max Table 25, added note 4 March 2005 001 Initial release Description July 2005 6 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 003US Datasheet 80333 1.0 1.1 Introduction About This Document This document is the Intel® 80333 I/O Processor Datasheet. This document contains a functional overview, package signal locations, targeted electrical specifications, and bus functional waveforms. Detailed functional descriptions other than parametric performance are published in the Intel® 80333 I/O Processor Developer’s Manual. Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. In particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. In fact, this specification does not imply a commitment by Intel to design, manufacture, or sell the product described herein. 1.1.1 Terminology To aid the discussion of the Intel® 80333 I/O processor (80333) architecture, the following terminology is used: Core processor Local processor Host processor Local bus Local memory Inbound Outbound Downstream Upstream QWORD DWORD word Intel XScale® core within the 80333 Intel XScale® core within the 80333 Processor located upstream from the 80333 80333 Internal Bus Memory subsystem on the Intel XScale® core DDR SDRAM or Peripheral Bus Interface busses At or toward the Internal Bus of the 80333 from the PCI interface of the ATU At or toward the PCI interface of the 80333 ATU from the Internal Bus At or toward a PCI Express* port directed away from the root complex (to a bus with a higher number) At or toward a PCI Express* port directed to the PCI Express* root complex (to a bus with a lower number). 64-bit data quantity (8 bytes). 32-bit data quantity (4 bytes). 16-bit data quantity (2 bytes). Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 7 80333 1.1.2 Other Relevant Documents 1. Intel XScale® Core Developer’s Manual (273473) — Intel Corporation 2. PCI Hot-Plug Specification, Revision 1.1 — PCI Special Interest Group 3. PCI Express* Specification, Revision 1.0a — PCI Special Interest Group 4. Intel® 80333 I/O Processor Developer’s Manual (305432) — Intel Corporation 5. Intel® 80333 I/O Processor Design Guide (305434) — Intel Corporation 6. Intel® 80333 I/O Processor Specification Update (305435) — Intel Corporation 7. PCI Local Bus Specification, Revision 2.3 — PCI Special Interest Group 8. PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a — PCI Special Interest Group 9. PCI Bus Power Management Interface Specification, Revision 1.1 — PCI Special Interest Group May 2005 8 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 1.2 About the Intel® 80333 I/O Processor The 80333 is a multi-function device that integrates the Intel XScale® core (ARM* architecture compliant) with intelligent peripherals and PCI Express*-to-PCI Bridges. The 80333 consolidates, into a single system: • • • • • • • • • • • • • • Intel XScale® core ×8 PCI Express* Upstream Link Two PCI Express*-to-PCI Bridges supporting PCI-X interface on both segments PCI Standard Hot-Plug Controller (segment B) Address Translation Unit (PCI-to-Internal Bus Application Bridge) interfaced to the segment A High-Performance Memory Controller Interrupt Controller with up to 16 external interrupt inputs Two Direct Memory Access (DMA) Controllers Application Accelerator Messaging Unit Peripheral Bus Interface Unit Two I2C Bus Interface Units Two 16550 compatible UARTs with flow control (four pins) Eight General Purpose Input Output (GPIO) ports The 80333 is an integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. PCI Express* is an industry-standard, high-performance, low-latency system interconnect. The PCI Express* upstream link of the 80333 is capable of ×8 lane widths at 2.5 GHz operation, as defined by the PCI Express* Specification, Revision 1.0a. The addition of the Intel XScale® core brings intelligence to the PCI Express*-to-PCI Bridges. The 80333 integrates PCI Express*-to-PCI Bridges with the ATU as an integrated secondary PCI device. The Upstream PCI Express* port implements the PCI-to-PCI Bridge programming model according to the PCI Express* Specification, Revision 1.0a. The Primary Address Translation Unit is compliant with the definitions of an “application bridge” as found in the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. Figure 1 on page 10 is a functional block diagram of the 80333. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 9 80333 Figure 1. Intel® 80333 I/O Processor Functional Block Diagram Intel XScale® Core Bus Interface Unit 32-/64-bit DDR Interface Memory Controller UART Units 2 – I 2C Units 16-bit PBI Application Accelerator Unit 2.7 GB/s Internal Bus (333 MHz) Interrupt/ GPIO Unit SMBus 2-channel DMA Controller Timers PCIe to PCI-X* Bridge PCIe to PCI-X* Bridge ATU Message Unit Arbiter IOAPIC PCIe x8 A PCI-X IOP-Bus (133 MHz) IOAPIC Arbiter/SHPC B PCI-X Slot Bus (133 MHz) B4852-01 May 2005 10 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 2.0 Features The Intel® 80333 I/O processor combines the Intel XScale® core with powerful new features to create an intelligent I/O processor. This multi-device I/O processor is fully compliant with the PCI Local Bus Specification, Revision 2.3 and the PCI Express* Specification, Revision 1.0a. Features specific to the 80333 include the following: • • • • • • • Intel XScale® core Application Accelerator Unit Address Translation Unit Memory Controller Peripheral Bus Interface Two I2C Bus Interface Units PCI Express* 2.5 GHz ×8 link • • • • • • • Interrupt Controller Unit Messaging Unit Internal Bus Two DMA Controllers Two UART Units Eight GPIOs Two PCI Express*-to-PCI Bridges to secondary PCI-X 133 MHz Bus interfaces The subsections that follow briefly overview each feature. Refer to the Intel® 80333 I/O Processor Developer’s Manual for full technical descriptions. 2.1 Intel XScale® Core The 80333 is based upon the Intel XScale® core. The core processor operates at a maximum frequency of 800 MHz. The instruction cache is 32 Kbytes in size and is 32-way set associative. Also, the core processor includes a data cache that is 32 Kbytes and is 32-way set associative, and a mini data cache that is 2 Kbytes and is two-way set associative. 2.2 PCI Express*-to-PCI Bridge Units The 80333 provides PCI Express*-to-PCI Bridge units. These bridge units share a common upstream PCI Express* interface compliant with the PCI Express* Specification, Revision 1.0a. The PCI Express* interface supports a port lane width of eight, for up to 2 Gbytes/s per direction (4 Gbytes/s total) at 2.5 Gbits/s bit rate. The PCI-X secondary interfaces support 64-bit 133 MHz, compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. These two secondary PCI bus interfaces are referred to as the ‘A’ and ‘B’ segment, where the 80333 Address Translation Unit resides on ‘A’ segment. The ‘B’ PCI bus interface can be used for slot expansion. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 11 80333 2.3 Address Translation Unit An Address Translation Unit (ATU) allows PCI transactions direct access to the 80333 local memory. The ATU supports transactions between PCI address space and 80333 address space. Address translation for the ATU is controlled through programmable registers accessible from both the PCI interface and the Intel XScale® core. The PCI interface of the ATU is connected to the 80333 “A” Secondary PCI interface of the bridge. Upstream access to the PCI Express* interface is controlled by inverse decode with the address windows of the bridge. Dual access to registers allows flexibility in mapping the two address spaces. The ATU also supports the power management extended capability configuration header that as defined by the PCI Bus Power Management Interface Specification, Revision 1.1. 2.4 Memory Controller The Memory Controller allows direct control of a DDR SDRAM memory subsystem. It features programmable chip selects and support for error correction codes (ECC). The memory controller may be configured for DDR SDRAM at 333 MHz (with 500 MHz and 667 MHz processors) or DDR-II SDRAM at 400 MHz (with 500 MHz and 800 MHz processors). The memory controller is dual-ported, with a dedicated interface for the Intel XScale® core Bus Interface Unit and a second interface to the Internal Bus. The memory controller supports pipelined access and arbitration control to maximize performance. The memory controller interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete DDR SDRAM devices. External memory may be configured as host addressable memory or private 80333 memory utilizing the Address Translation Unit and Bridges. 2.5 Application Accelerator Unit The Application Accelerator Unit (AA) provides low-latency, high-throughput data transfer capability between the AA unit, the 80333 local memory and the PCI bus. It executes data transfers from and to the 80333 local memory, from the PCI bus to the 80333 local memory, or from the 80333 local memory to the PCI bus. The AA unit performs XOR operations, computes parity, generates and verifies an eight byte data integrity field, performs memory block fills, and provides the necessary programming interface. The AA unit in the 80333 has been enhanced to support RAID 6 functionality. 2.6 Peripheral Bus Interface The Peripheral Bus Interface Unit is a data communication path to the flash memory components or other peripherals of an 80333 hardware system. The PBI includes support for either 8/16 bit devices. To perform these tasks at high bandwidth, the bus features a burst transfer capability which allows successive 8/16-bit data transfers. May 2005 12 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 2.7 DMA Controller The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents and the local memory. Two separate DMA channels accommodate data transfers to the PCI bus. Both channels include a local memory to local memory transfer mode. The DMA Controller supports chaining and unaligned data transfers. It is programmable through the Intel XScale® core only. 2.8 I2C Bus Interface Unit The I2C (Inter-Integrated Circuit) Bus Interface Unit allows the Intel XScale® core to serve as a master and slave device residing on the I2C bus. The I2C unit uses a serial bus developed by Philips Semiconductor*, consisting of a two-pin interface. The bus allows the 80333 to interface to other I2C peripherals and microcontrollers for system management functions. It requires a minimum of hardware components for an economical system to relay status and reliability information on the I/O subsystem to an external device. Also refer to I2C Peripherals for Microcontrollers (Philips Semiconductor). The 80333 includes two I2C bus interface units. 2.9 Messaging Unit The Messaging Unit (MU) provides data transfer between the PCI system and the 80333. It uses interrupts to notify each system when new data arrives. The MU has four messaging mechanisms: • • • • Message Registers Doorbell Registers Circular Queues Index Registers Each messaging mechanism allows a host processor or external PCI device and the 80333 to communicate through message passing and interrupt generation. 2.10 Internal Bus The Internal Bus is a high-speed interconnect between internal units and Intel XScale® core processor. The Internal Bus operates at 333 MHz and is 64 bits wide. 2.11 UART Units The 80333 includes two UART unit. The UART units allow the Intel XScale® core to serve as a master and slave device residing on the UART bus. The UART units use a serial bus consisting of a four-pin interface. The bus allows the 80333 to interface to other peripherals and microcontrollers. Also refer to 16550 Device Specification (National Semiconductor*). Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 13 80333 2.12 Interrupt Controller Unit The Interrupt Controller Unit (ICU) aggregates interrupt sources both external and internal of the 80333 to the Intel XScale® core processor. The ICU supports high performance interrupt processing with direct interrupt service routine vector generation on a per source basis. Each source has programmability for masking, core processor interrupt input, and priority. 2.13 GPIO The 80333 includes eight General Purpose I/O (GPIO) pins which can also be used as external interrupt inputs. 2.14 SMBus Unit The SMBus (System Management Bus) Interface Unit allows the 80333 to serve as a slave device on the SMBus. SMBus is based on the principles of the I2C bus and allows the 80333 to interface to system SMBus for external access and control of internal registers. May 2005 14 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 3.0 Package Information The 80333 is offered in a Flip Chip Ball Grid Array (FCBGA) package. This is a full grid array package with 829 ball connections. 3.1 Table 1. Functional Signal Descriptions Pin Description Nomenclature Symbol C I O I/O OD PWR GND Configuration Input pin only Output pin only Pin may be either an input or output. Open Drain pin Power pin Ground pin Pin must be connected as described. Synchronous. Signal meets timings relative to a clock. Sync(B) Synchronous to B_CLKIN Sync(…) Sync(M) Synchronous to M_CK[2:0] Sync(A) Synchronous to A_CLKIN Sync(T) Synchronous to TCK Async Rst(R) Rst(A) Rst(B) Rst(M) Rst(T) Asynchronous. Inputs may be asynchronous relative to all clocks. All asynchronous signals are level-sensitive. The pin is reset with PWRGD or RSTIN#. The pin is reset with A_RST#. Note that A_RST# is asserted when RSTIN# or PWRGD is asserted. The pin is reset with B_RST#. Note that B_RST# is asserted when RSTIN# or PWRGD is asserted. The pin is reset with M_RST#. Note that M_RST# is asserted when RSTIN# or PWRGD is asserted or is asserted with software. The pin is reset with TRST#. Description Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 15 80333 Table 2. DDR SDRAM Signals Name M_CK[2:0] M_CK[2:0]# M_RST# MA[13:0] Count 3 3 1 14 Type O O O Async O Sync(M), Rst(M) O Sync(M), Rst(M) O Sync(M), Rst(M) O Sync(M), Rst(M) O Sync(M), Rst(M) O Sync(M), Rst(M) O Sync(M), Rst(M) Description Memory Clocks are used to provide the positive differential clocks to the external SDRAM memory subsystem. Memory Clocks are used to provide the negative differential clocks to the external SDRAM memory subsystem. Memory Reset indicates when the memory subsystem has been reset with RSTIN# or PWRGD or a software reset. Memory Address Bus carries the multiplexed row and column addresses to the SDRAM memory banks. SDRAM Bank Address indicates which of the SDRAM internal banks are read or written during the current transaction. SDRAM Row Address Strobe indicates the presence of a valid row address on the Multiplexed Address Bus MA[12:0]. SDRAM Column Address Strobe indicates the presence of a valid column address on the Multiplexed Address Bus MA[12:0]. SDRAM Write Enable indicates that the current memory transaction is a write operation. SDRAM Chip Select enables the SDRAM devices for a memory access (Physical banks 0 and 1). SDRAM Clock Enable enables the clocks for the SDRAM memory. Deasserting will place the SDRAM in self-refresh mode. SDRAM Data Bus carries 64-bit data to and from memory. During a data cycle, read or write data is present on one or more contiguous bytes. During write operations, unused pins are driven to determinate values. SDRAM ECC Check Bits carry the 8-bit ECC code to and from memory during data cycles. SDRAM Data Strobes carry the strobe signals, output in write mode and input in read mode for source synchronous data transfer. SDRAM Data Mask controls which bytes on the data bus should be written. When DM[8:0] is asserted, the SDRAM devices do not accept valid data from the byte lanes. BA[1:0] 2 RAS# 1 CAS# 1 WE# CS[1:0]# 1 2 CKE[1:0] 2 DQ[63:0] 64 I/O Sync(M), Rst(M) I/O Sync(M), Rst(M) I/O Sync(M), Rst(M) O Sync(M), Rst(M) CB[7:0] 8 DQS[8:0] 9 DM[8:0] Total 9 120 May 2005 16 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 3. DDR-II SDRAM Signals Name DQS[8:0]# Count 9 Type I/O Sync(M) Rst(M) O Sync(M) Rst(M) I/O Description SDRAM Data Strobes carry the differential strobe signals in DDR-II mode, output in write mode and input in read mode for source synchronous data transfer. On Die Termination Control, turns on SDRAM termination during writes. Compensation For DDR OCD (analog) DDR-II mode only. ODT[1:0] DDRRES[2:1] Total 2 2 13 Table 4. MISC SDRAM Signals Name DDRCRES0 Count 1 Type O Description Analog VSS Ref Pin (analog) both DDRSLWCRES and DDRIMPCRES signals connect to this pin through a reference resistor. Compensation Voltage Reference (analog) for DDR driver slew rate control connected through a resistor to DDRCRES0. Compensation Voltage Reference (analog) for DDR driver impedance control connected through a resistor to DDRCRES0. DDRSLWCRES DDRIMPCRES Total 1 1 3 I/O I/O Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 17 80333 Table 5. Peripheral Bus Interface Signals Name Count Type Description Address Bus 22:16 carries a demultiplexed version of address bits A22:16. During address (Ta), wait state (Tw) and data cycles (Td) cycles, A[22:16] represents the upper seven address bits for the current access. A[22:16] allows the PBI interface to address up to 8 Mbytes per peripheral device. See “Table 17, “Pin Multiplexing for Functional Modes” on page 36” for strap inputs which are muxed onto A[19:16], and “Table 14, “Reset Strap Signals” on page 29” for a functional description. Address/Data Bus carries 16-bit physical addresses and 8- or 16-bit data to and from memory. During an address (Ta) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, bits 0-7, or 0-15 contain read or write data, depending on the corresponding bus width. During write operations to 8-bit wide memory regions, the PBI drives unused bus pins high or low. AD[15:0] 16 I/O Rst(M) SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the number of data transfers during the bus transaction. AD1 AD0 0 0 0 1 1 0 1 1 1 Transfer 2 Transfers 3 Transfers 4 Transfers A[22:16] 7 O Rst(M) See “Table 17, “Pin Multiplexing for Functional Modes” on page 36” for strap inputs which are muxed onto AD[15:0], and “Table 14, “Reset Strap Signals” on page 29” for a functional description. Address Bus 2:0 carries a demultiplexed version of bits 2:0 of the AD[15:0] bus. During an address (Ta) cycle, bits A[2:0] matches AD[2:0]. During a bursted read data (Td) cycle, A[2:0] will represent the current byte address in the bursted transaction. A[2:0] 3 O Rst(M) A[2:1] are used for an 16-bit wide peripheral while A[1:0] are used for an 8-bit wide peripheral. See “Table 17, “Pin Multiplexing for Functional Modes” on page 36” for strap inputs which are muxed onto A[2:0], and “Table 14, “Reset Strap Signals” on page 29” for a functional description. ALE 1 O Rst(M) Address Latch Enable indicates the transfer of a physical address. The pin is asserted during the first address cycle and deasserted during the second address cycle. Peripheral Output Enable Indicates whether the bus access is a write or a read with respect to the I/O processor and is valid during the entire bus access. This pin may be used to control the OE# input on peripheral devices. 0 = Read 1 = Write Peripheral Write Enable indicates whether the bus access is a write or a read with respect to the I/O processor and is valid during the entire bus access. This pin is use for flash memory accesses and controls the WE# input on the ROM. 0 = Write 1 = Read PCE[1]# 1 O Rst(M) O Rst(M) Peripheral Chip Enables specify which of the two memory address ranges are associated with current bus access. The pin remains valid during the entire bus access. Peripheral Chip Enables specify which of the two memory address ranges are associated with current bus access. The pin remains valid during the entire bus access. POE# 1 O Rst(M) PWE# 1 O Rst(M) PCE[0]# Total 1 31 May 2005 18 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 6. PCI Express* Signals Name REFCLK+/ REFCLKCount Type Description PCI Express* Differential Clock In: These pins receive a 100 MHz differential clock input from an external source. This clock is used as the reference clock for the PCI Express* circuitry. PCI Express* Serial Data Transmit: These eight differential output pairs carry data and embedded clock for the PCI Express* port 0 interface. 16 O • ×8 Mode: All PE0Tp[7:0] and PE0Tn[7:0] signals are used. • ×4 Mode: Only PE0Tp[3:0] and PE0Tn[3:0] signals are used. PCI Express* Serial Data Receive: These eight differential input pairs receive data and embedded clock for port 0. PE0Rp[7:0]/ PE0Rn[7:0] 16 I • ×8 Mode: All PE0Rp[7:0] and PE0Rn[7:0] signals are used. • ×4 Mode: Only PE0Rp[3:0] and PE0Rn[3:0] signals are used. PE_RCOMPO 1 I PCI EXPRESS RCOMP: Connected to external reference resistor. Output current path, used to compensate PCI Express* driver and RX termination. PCI EXPRESS RCOMP IN: Connected to the same external resistor as PE_RCOMPO on the board, for input voltage sensing comparator. 2 I PE0Tp[7:0]/ PE0Tn[7:0] PE_ICOMPI Total 1 36 I Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 19 80333 Table 7. B PCI (Slot Expansion) Bus Signals (Sheet 1 of 2) Name B_AD[31:0] Count 32 Type I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) O Sync(B) Rst(B) O Sync(B) Rst(B) O Sync(B) Rst(B) O Sync(B) Rst(B) O Sync(B) Rst(B) I/O Sync(B) Rst(B) I Sync(B) I Sync(B) I Sync(B) I Sync(B) I Sync(B) I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) Description B PCI Address/Data is the multiplexed PCI address and lower 32 bits of the data bus. B PCI Address/Data is the upper 32 bits of the PCI data bus driven during the data phase. B PCI Bus Parity is even parity across B_AD[31:0] and B_C/BE[3:0]#. B PCI Bus Upper DWORD Parity is even parity across B_AD[63:32] and B_C/BE[7:4]#. B PCI Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase, they define the bus command. During the data phase, they are used as byte enables for B_AD[63:0]. B Secondary PCI Bus Grant signals sent to device 4 on the Bsegment PCI bus. B Secondary PCI Bus Grant signals sent to device 3 on the Bsegment PCI bus. B Secondary PCI Bus Grant signal sent to device 2 on the Bsegment PCI bus. B Secondary PCI Bus Grant signal sent to device 1 on the Bsegment PCI bus. B PCI Bus Grant is the grant signal sent to device 0 on the Bsegment PCI bus. B PCI Bus Request 64-Bit Transfer indicates the attempt of a 64bit transaction on the PCI bus. When the target is 64-bit capable, the target acknowledges the attempt with the assertion of B_ACK64#. B PCI Bus Requests is the request signal for device 4 on the Bsegment PCI bus. B PCI Bus Requests is the request signal for device 3 on the Bsegment PCI bus. B PCI Bus Requests is the request signal for device 2 on the Bsegment PCI bus. PCI 66 Enable is used to determine when the slot is PCI 66 MHz capable. This signal is only valid for Hot-Plug 1-slot mode. B PCI Bus Requests is the request signal for device 1 on the B-segment PCI bus. B PCI Bus Requests are the request signals from device 0 on the B-segment secondary PCI bus. B PCI Bus Acknowledge 64-Bit Transfer indicates that the device has positively decoded its address as the target of the current access and the target is willing to transfer data using the full 64-bit data bus. B PCI Bus Cycle Frame is asserted to indicate the beginning and duration of an access. B_AD[63:32] 32 B_PAR 1 B_PAR64 1 B_C/BE[7:0]# 8 B_GNT[4]# 1 B_GNT[3]# 1 B_GNT[2]# 1 B_GNT[1]# 1 B_GNT[0]# 1 B_REQ64# 1 B_REQ[4]# B_REQ[3]# 1 1 B_REQ[2]#/ B_HM66EN 1 B_REQ[1]# B_REQ[0]# 1 1 B_ACK64# 1 B_FRAME# 1 May 2005 20 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 7. B PCI (Slot Expansion) Bus Signals (Sheet 2 of 2) Name Count Type I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) I/O Sync(B) Rst(B) I/O OD Sync(B) Rst(B) I/O Sync(B) Rst(B) I/O I Sync(B) I O O I Description B PCI Bus Initiator Ready indicates the initiating agent’s ability to complete the current data phase of the transaction. During a write, it indicates that valid data is present on the Address/Data bus. During a read, it indicates the processor is ready to accept the data. B PCI Bus Target Ready indicates the target agent’s ability to complete the current data phase of the transaction. During a read, it indicates that valid data is present on the Address/Data bus. During a write, it indicates the target is ready to accept the data. B PCI Bus Stop indicates a request to stop the current transaction on the PCI bus. B PCI Bus Device Select is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. B PCI Bus Lock indicates whether or not a transaction is establishing a LOCK across the bridge. B PCI Bus System Error is driven for address parity errors on the PCI bus. B PCI Bus Parity Error is asserted when a data parity error occurs during a PCI bus transaction. B PCI Bus 66 MHz Enable indicates the speed of the PCI bus. When this signal is sampled high the PCI bus speed is 66 MHz, when low, the bus speed is 33 MHz. Power Management Event signal is used to request a change in the device or system power state. B PCI-X Capability Analog pad that selects PCI/X mode and frequency capabilities. Non-standard, special purpose analog pin. B PCI Bus Output Clocks are used to drive external logic on the secondary PCI bus. B PCI Bus Output Clock is used to drive B_CLKIN when secondary bus clocks are enabled. B PCI Bus Input Clock provides the timing for all PCI transactions. Typically connected on the board to B_CLKOUT. Provides timing clock for all B-segment PCI interfaces. B PCI BUS RESET is an output based on RSTIN# or PWRGD. It brings PCI-specific registers, sequencers, and signals to a consistent state. When RSTIN# is asserted or PWRGD is deasserted, or the secondary bridge reset bit is asserted, it causes B_RST# to assert and: B_RST# 1 O • PCI output signals are driven to a known consistent state. • PCI bus interface output signals are three-stated. • open drain signals such as B_SERR# are floated B_RST# may be asynchronous to B_CLKIN when asserted or deasserted. Although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. B_RCOMP Total 1 106 I/O PCI Resistor Compensation Pin is an analog pad that connects to a board resistor to control all B segment PCI output driver strengths (analog). B_IRDY# 1 B_TRDY# 1 B_STOP# 1 B_DEVSEL# 1 B_LOCK# 1 B_SERR# 1 B_PERR# 1 B_M66EN B_PME# B_PCIXCAP B_CLKO[4:0] B_CLKOUT B_CLKIN 1 1 1 5 1 1 Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 21 80333 Table 8. A PCI (IOP) Bus Signals (Sheet 1 of 2) Name A_AD[31:0] Count 32 Type I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) Description A PCI Address/Data is the multiplexed PCI address and lower 32 bits of the data bus. A_AD[63:32] 32 A PCI Address/Data is the upper 32 bits of the PCI data bus. A_PAR 1 A PCI Bus Parity is even parity across A_AD[31:0] and A_C/BE[3:0]#. A PCI Bus Upper DWORD Parity is even parity across A_AD[63:32] and A_C/BE[7:4]#. A PCI Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase, they define the bus command. During the data phase, they are used as the byte enables for A_AD[31:0]. A PCI Byte Enables are used as byte enables for A_AD[63:32] during secondary PCI data phases. A PCI Bus Request 64-Bit Transfer indicates the attempt of a 64-bit transaction on the secondary PCI bus. When the target is 64-bit capable, the target acknowledges the attempt with the assertion of A_ACK64#. A PCI Bus Acknowledge 64-Bit Transfer indicates that the device has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64 bits. A PCI Bus Cycle Frame is asserted to indicate the beginning and duration of an access. A PCI Bus Initiator Ready indicates the initiating agent’s ability to complete the current data phase of the transaction. During a write, it indicates that valid data is present on the secondary Address/Data bus. During a read, it indicates the processor is ready to accept the data. A PCI Bus Target Ready indicates the target agent’s ability to complete the current data phase of the transaction. During a read, it indicates that valid data is present on the secondary Address/Data bus. During a write, it indicates the target is ready to accept the data. A PCI Bus Stop indicates a request to stop the current transaction on the secondary PCI bus. A PCI Bus Device Select is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. A PCI Bus System Error is driven for address parity errors on the secondary PCI bus. A_PAR64 1 A_C/BE[3:0]# 4 A_C/BE[7:4]# 4 A_REQ64# 1 A_ACK64# 1 A_FRAME# 1 A_IRDY# 1 A_TRDY# 1 I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) I/O OD Sync(A) Rst(A) A_STOP# 1 A_DEVSEL# 1 A_SERR# 1 May 2005 22 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 8. A PCI (IOP) Bus Signals (Sheet 2 of 2) Name Count Type Description A PCI Bus Reset is an output based on RSTIN# or PWRGD. It brings PCI-specific registers, sequencers, and signals to a consistent state. When RSTIN# is asserted or PWRGD is deasserted, or the secondary bridge reset bit is asserted, it causes A_RST# to assert and: A_RST# 1 O Async • PCI output signals are driven to a known consistent state. • PCI bus interface output signals are three-stated. • Open drain signals such as A_SERR#are floated. A_RST# may be asynchronous to A_CLKIN when asserted or deasserted. Although asynchronous, deassertion must be ensured to be a clean, bounce-free edge. A_PERR# 1 I/O Sync(A) Rst(A) I/O Sync(A) Rst(A) O O A PCI Bus Parity Error is asserted when a data parity error during a secondary PCI bus transaction. A PCI Bus Lock indicates the need to perform an atomic operation on the secondary PCI bus. A PCI Bus Output Clocks are used to drive external logic on the secondary PCI bus. A PCI Bus Output Clock is used to drive A_CLKIN when the IO processor provides secondary bus clocks. A PCI Bus Input Clock provides the timing for all PCI transactions. Typically connected on the board to A_CLKOUT. Provides the timing clock for all A segment PCI interfaces. A PCI Bus 66 MHz Enable indicates the speed of the secondary PCI bus. When this signal is high, the bus speed is 66 MHz and when it is low, the bus speed is 33 MHz. Power Management Event signal is used to request a change in the device or system power state. A PCI Bus Requests are the request signals from devices 3 through 0 on the A PCI bus. A PCI Bus Grant are grant signals sent to devices 3 through 0 on the A PCI bus. A PCI-X Capability is an analog pad that selects PCI/X mode and frequency capabilities. Non-standard, special purpose analog pin. PCI Resistor Compensation Pin is an analog pad that connects to the board resistor to control all A segment PCI output driver strengths (analog). A_LOCK# 1 A_CLKO[3:0] A_CLKOUT 4 1 A_CLKIN 1 I A_M66EN 1 I/O I Sync(A) I Sync(A) O Sync(A) Rst(A) I A_PME# A_REQ[3:0]# 1 4 A_GNT[3:0]# 4 A_PCIXCAP 1 A_RCOMP Total 1 103 I/O Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 23 80333 Table 9. Interrupt Signals Name Count Type Description Interrupt Inputs: XINT[7:0]# interrupts are directed to the input of the IOAPIC, or the Interrupt Controller inputs. When directed to the Interrupt Controller inputs, then the inputs can be steered to either the FIQ or IRQ internal interrupt input of the core. By default, XINT[7:4]# interrupts are directed to the input of the B IOAPIC and XINT[3:0]# interrupts are directed to the input of the A IOAPIC. These interrupt pins are level sensitive. HPI# Total 1 9 I Async High Priority Interrupt causes a high priority interrupt to the I/O processor. This pin is level-detect only and is internally synchronized. XINT[7:0]# 8 I Async Table 10. I2C/SMBus Signals Name SCL0 SCD0 SCL1/SCLK SCD1/SDTA Total Count 1 1 1 1 4 Type I/O I/O I/O I/O Description I2C Clock provides synchronous operation of the I2C bus zero. I2C Data is used for data transfer and arbitration of the I2C bus zero. I2C Clock provides synchronous operation of the I2C bus zero. SM Bus Clock provides synchronous operation of the SM bus. I2C Data is used for data transfer and arbitration of the I2C bus zero. SM Bus Data is used for data transfer and arbitration of the SM bus. May 2005 24 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 11. Hot-Plug Controller Signals for Parallel 1-slot, No-Glue Name B_HPWRFLT# Count 1 Type Description I Parallel Mode Hot-Plug Power Controller Fault indication for overSync(B) current/under-volt status. When asserted, the device (when enabled) Rst(B) may assert a slot reset and disconnects the slot from the bus. Parallel Mode Hot-Plug Status of the slot 1 MRL sensor switch, I when asserted it indicates the MRL latch is closed. When a platform Sync(B) does not support MRL sensors, this must be wired to a logic low Rst(B) level. Parallel Mode Hot-Plug PRSNT2 signal is used to indicate whether I a card is installed in the slot and its power requirements. These Sync(B) signals are directly connected to the present bits on the PCI card. O Parallel Mode Hot-Plug Power Enable signal connected to onSync(B) board slot specific power controller to regulate current and voltage of Rst(B) the slot. I Parallel Mode Hot-Plug PRSNT1 signal is used to indicate whether Sync(B) a card is installed in the slot and its power requirements. These Rst(B) signals are directly connected to the present bits on the PCI card. O Parallel Mode Hot-Plug Attention indicator LED signal that is Sync(B) yellow or amber in color. Rst(B) O Parallel Mode Hot-Plug Power Indicator LED signal that is green Sync(B) in color. Rst(B) Parallel Mode Hot-Plug Attention Button input from the slot. When I low, this indicates that the operator has requested attention. When Sync(B) an attention button is not implemented, this input must be wired to a Rst(B) logic high level. O Parallel Mode Reset Output Signal. This output signal is always “on”, therefore, it does not tri-state during boundary scan. B_HMRL# 1 B_HPRSNT2# 1 B_HPWREN 1 B_HPRSNT1# 1 B_HATNLED# 1 B_HPWRLED# 1 B_HBUTTON# 1 B_HRESET# Total 1 9 Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 25 80333 Table 12. UART Signals (Sheet 1 of 2) Name Count Type Description General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Serial Input: Serial data input from device pin to receive shift register. General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Serial Output: Composite serial data output to the communications link-peripheral, modem, or data set. The TXD signal is set to the MARKING (logic 1) state upon a Reset operation. General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Clear To Send: When low, this pin indicates that the receiving UART is ready to receive data. When the receiving UART deasserts CTS# high, the transmitting UART should stop transmission to prevent overflow of the receiving UARTs buffer. The CTS# signal is a modemstatus input whose condition may be tested by the host processor or by the UART when in Autoflow Mode as described below: Non-Autoflow Mode: When not in Autoflow Mode, bit 4 (CTS) of the Modem Status register (MSR) indicates the state of CTS#. Bit 4 is the complement of the CTS# signal. Bit 0 (DCTS) of the Modem Status register indicates whether the CTS# input has changed state since the previous reading of the Modem Status register. CTS# has no effect on the transmitter. The user may program the UART to interrupt the processor when DCTS changes state. The programmer may then stall the outgoing data stream by starving the transmit FIFO or disabling the UART with the IER register. Note: When UART transmission is stalled by disabling the UART, the user may not receive an MSR interrupt when CTS# reasserts. This occurs because disabling the UART also disables interrupts. As a workaround, the user may use Auto CTS in Autoflow Mode, or program the CTS# pin to interrupt. In Autoflow Mode, the UART Transmit circuitry will check the state of CTS# before transmitting each byte. When CTS# is high, no data is transmitted. GPIO[0]/ U0_RXD 1 I/O GPIO[1]/ U0_TXD 1 I/O GPIO[2]/ U0_CTS# 1 I/O Autoflow Mode: Note: General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Request To Send: When low, this informs the remote device that the UART is ready to receive data. A reset operation sets this signal to its Inactive (high) state. LOOP mode operation holds this signal in its Inactive state. GPIO[3]/ U0_RTS# 1 I/O Non-Autoflow Mode: The RTS# output signal may be asserted by setting bit 1 (RTS) of the Modem Control register to a 1. The RTS bit is the complement of the RTS# signal. Autoflow Mode: RTS# is automatically asserted by the Autoflow circuitry when the Receive buffer exceeds its programmed threshold. It is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. May 2005 26 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 12. UART Signals (Sheet 2 of 2) Name GPIO[4]/ U1_RXD Count Type Description General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Serial Input: Serial data input from device pin to receive shift register. General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Serial Output: Composite serial data output to the communications link-peripheral, modem, or data set. The TXD signal is set to the MARKING (logic 1) state upon a Reset operation. General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Clear To Send: When low, this pin indicates that the receiving UART is ready to receive data. When the receiving UART deasserts CTS# high, the transmitting UART should stop transmission to prevent overflow of the receiving UARTs buffer. The CTS# signal is a modemstatus input whose condition may be tested by the host processor or by the UART when in Autoflow Mode as described below: Non-Autoflow Mode: When not in Autoflow Mode, bit 4 (CTS) of the Modem Status register (MSR) indicates the state of CTS#. Bit 4 is the complement of the CTS# signal. Bit 0 (DCTS) of the Modem Status register indicates whether the CTS# input has changed state since the previous reading of the Modem Status register. CTS# has no effect on the transmitter. The user may program the UART to interrupt the processor when DCTS changes state. The programmer may then stall the outgoing data stream by starving the transmit FIFO or disabling the UART with the IER register. Note: When UART transmission is stalled by disabling the UART, the user may not receive an MSR interrupt when CTS# reasserts. This occurs because disabling the UART also disables interrupts. As a workaround, the user may use Auto CTS in Autoflow Mode, or program the CTS# pin to interrupt. In Autoflow Mode, the UART Transmit circuitry will check the state of CTS# before transmitting each byte. When CTS# is high, no data is transmitted. 1 I/O GPIO[5]/ U1_TXD 1 I/O GPIO[6]/ U1_CTS# 1 I/O Autoflow Mode: Note: General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. Request To Send: When low, this informs the remote device that the UART is ready to receive data. A reset operation sets this signal to its Inactive (high) state. LOOP mode operation holds this signal in its Inactive state. GPIO[7]/ U1_RTS# 1 I/O Non-Autoflow Mode: The RTS# output signal may be asserted by setting bit 1 (RTS) of the Modem Control register to a 1. The RTS bit is the complement of the RTS# signal. Autoflow Mode: RTS# is automatically asserted by the Autoflow circuitry when the Receive buffer exceeds its programmed threshold. It is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. Total 8 Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 27 80333 Table 13. Test and Miscellaneous Signals Name Count Type Description Test Clock provides clock input for IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the device on the rising clock edge and data is clocked out on the falling clock edge. Test Data Input is the JTAG serial input pin. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. This signal has a weak internal pull-up to ensure proper operation when this pin is not being driven. Test Data Output is the serial output pin for the JTAG feature. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFTDR states of the Test Access Port. At other times, TDO floats. The behavior of TDO is independent of RSTIN# or PWRGD. Test Reset asynchronously resets the Test Access Port controller function of IEEE 1149 Boundary Scan Testing (JTAG). This pin has a weak internal pull-up. Test Mode Select is sampled on the rising edge of TCK to select the operation of the test logic for IEEE 1149 Boundary Scan testing. This pin has a weak internal pull-up. No Connect. Do not connect to any signal, power or ground. Power Fail Delay is used to delay the reset of the memory controller in a power-fail condition. This allows the self-refresh command to be sent to the DDR SDRAM array. Power Supply Good: Signal that specifies that the motherboard power supply has stabilized. This signal is used to asynchronously reset the 80333 when it is low. The low period of this signal must be long enough for the system power supply to stabilize and for the base PLLs to lock. Note: This is the same signal as PERST# which is described in the PCI Express* Card Electromechanical Specification, Revision 1.0a. TCK 1 I TDI 1 I Sync(T) TDO 1 O Sync(T) Rst(T) I Async I Sync(T) I Async TRST# 1 TMS N/C PWRDELAY 1 7 1 PWRGD 1 I Async Reset Input brings PCI-specific registers, sequencers, and signals to a consistent state. When RSTIN# is asserted: • PCI output signals are driven to a known consistent state. RSTIN# 1 I Async • PCI bus interface output signals are three-stated. • Open drain signals such as B_SERR# are floated. RSTIN# may be asynchronous to B_CLKIN when asserted or deasserted. Although asynchronous, deassertion must be ensured to be a clean, bounce-free edge. Total 15 May 2005 28 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 14. Reset Strap Signals (Sheet 1 of 2) Name Count Type Description Configuration Retry Mode: RETRY is latched on the rising (asserting) edge of PWRGD and determines when the PCI interface of the ATU will disable PCI configuration cycles by signaling a retry until the configuration cycle retry bit is cleared in the PCI configuration and status register. 0 = Configuration Cycles enabled (Requires pull down resistor.) 1 = Configuration Retry enabled in the ATU (Default mode) Note: Muxed onto signal AD[6], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. RETRY 1 C Core Reset Mode is latched on the rising (asserting) edge of PWRGD and determines when the Intel XScale® core is held in reset until the processor reset bit is cleared in PCI configuration and status register. CORE_RST# 1 C 0 = Hold in reset. (Requires pull-down resistor.) 1 = Do not hold in reset. (Default mode) Note: Muxed onto signal AD[5], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. Bus Width is latched on the rising (asserting) edge of PWRGD, it sets the default bus width for the PBI Memory Boot window. P_BOOT16# 1 C 0 = 16 bits wide (Requires a pull-down resistor.) 1 = 8 bits wide (Default mode) Note: Muxed onto signal AD[4], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. Memory Type: MEM_TYPE is latched on the rising (asserting) edge of PWRGD and it defines the speed of the DDR SDRAM interface. MEM_TYPE 1 C 0 = DDR-II SDRAM at 400 MHz (Required pull-down resistor.) 1 = DDR SDRAM at 333 MHz (Default mode) Note: Muxed onto signal AD[2], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. PCI Bus Segment ‘A’ 133 MHz Enable: A_PCIX133EN is latched on the rising (asserting) edge of PWRGD and it determines the maximum PCI-X mode operating frequency. A_PCIX133EN 1 C 0 = 100 MHz enabled (Requires pull down resistor). 1 = 133 MHz enabled (Default mode). Note: Muxed onto signal AD[3], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. PCI Bus Segment ‘B’ 133 MHz Enable: B_PCIX133EN latched on rising (asserting) edge of PWRGD and determines maximum PCI-X mode operating frequency. B_PCIX133EN 1 C 0 = 100 MHz enabled (Requires pull down resistor.) 1 = 133 MHz enabled (Default mode) Note: Muxed onto signal AD[10], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 29 80333 Table 14. Reset Strap Signals (Sheet 2 of 2) Name Count Type Description Number of Slots: B_HSLOT[3:0] latched on rising (asserting) edge of PWRGD and indicates when the ‘B’ PCI-X bus interface Standard Hot-Plug Controller is enabled, the total number of slots in both Hot-Plug enabled mode and disabled mode, and the HotPlug mode. B_HSLOT[3] enables Hot-Plug when high and disables Hot-Plug when low. Hot-Plug disabled 0000 = 1 slot 0001 = 2 slots 0010 = 3 slots 0011 = 4 slots 0100 = 5 slots 0101 = 6 slots 0110 = 7 slots 0111 = 8 slots Note: Note: Hot-Plug enabled 1000 = reserved 1001 = reserved 1010 = reserved 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = Parallel 1-slot-no-glue B_HSLOT[3:0] 4 C 1111 is Default mode. Muxed onto signal AD[15:12], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. SMB_MA5 SMB_MA3 SMB_MA2 SMB_MA1 Manageability Address (MA): latched on rising (asserting) edge of PWRGD and maps to MA bit 5, 3, 2, and 1, where MA bits[7:0] represent the address the SMBus slave port will respond to when access is attempted. 4 C 0 = (Requires pull down resistor.) 1 = (Default mode) Note: Muxed onto signal A[19:16], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. PCI Bus ODT Enable: PCIODT_EN is latched on the rising (asserting) edge of PWRGD, and determines when the PCI-X interface will have On-Die Termination enabled. PCIODT_EN is valid for both A and B segments. The following signals are affected by PCIODT_EN: A_ACK64#, A_AD[63:32], A_C/BE[7:4]#, A_DEVSEL#, A_FRAME#, A_IRDY#, A_LOCK#, A_M66EN, A_PAR64, A_PERR#, A_REQ[3:0]#, A_REQ64#, A_SERR#, A_STOP#, A_TRDY#, B_ACK64#, B_AD[63:32], B_C/BE[7:4]#, B_DEVSEL#, B_FRAME#, B_IRDY#, B_LOCK#, B_M66EN, B_PAR64, B_PERR#, B_REQ[4:0]#, B_REQ64#, B_SERR#, B_STOP#, B_TRDY#, XINT[7:0]# 0 = ODT disabled (Requires pull-down resistor). 1 = ODT enabled (Default mode). Note: Muxed onto signal A[20], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. Muxed onto signal AD[7], see Table 17, “Pin Multiplexing for Functional Modes” on page 36. PCIODT_EN 1 C Pull-down Resistor is required for default mode. PD1 Total 1 16 C Note: May 2005 30 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 15. Power and Ground Pins Name Count Type Description PLL 1-5 Power is a separate VCC15 supply ball for the phase lock loop clock generator. It is to be connected to the board VCC15 plane. Each VCCPLL requires a low-pass filter circuit to reduce noiseinduced clock jitter and its effects on timing relationships. See the Intel® 80333 I/O Processor Design Guide for more information. 3.3 V Power balls to be connected to a 3.3 V power board plane. 2.5 V/1.8 V Power balls to be connected to a 2.5 V or 1.8 V power board plane, dependent on DDR or DDRII mode. 1.5 V Power balls to be connected to a 1.5 V power board plane. VCC15 VCC13 PE_VCCBG 56 7 1 PWR PWR PWR VCC15 = core VCC15E = PCI Express* 1.3 V Power balls to be connected to a 1.35 V power board plane. PCI Express* Band Gap Analog Ref Power: 2.5 V power for analog reference circuit, separated from all other VCC signals. Requires a low-pass filter. SDRAM Voltage Reference is used to supply the reference voltage to the differential inputs of the memory controller pins. Ground balls to be connected to a ground board plane. Analog Ground balls need to be connected to the appropriate VCCPLL filter, and not to board ground. PCI Express* Band Gap Analog Ground: Ground for analog reference circuit, separated from all other VSS signals. VCCPLL[1-5] 5 PWR VCC33 VCC25/18 49 29 PWR PWR DDR_VREF VSS VSSA[1-5] PE_VSSBG 1 218 5 1 PWR GND GND GND Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 31 80333 Table 16. Pin Mode Behavior (Sheet 1 of 4) Pin M_CK[2:0] M_CK[2:0]# M_RST# MA[13:0] BA[1:0] RAS# CAS# WE# CS[1:0]# CKE[1:0] DQ[63:32] DQ[31:0] CB[7:0] DQS[8] DQS[7:4] DQS[3:0] DQS[8]# DQS[7:4]# DQS[3:0]# DM[8] DM[7:4] DM[3:0] DDR_VREF ODT[1:0]2 DDRRES[2:1] DDRCRES0 DDRSLWCRES DDRIMPCRES A[22:16] AD[15:0] A[2:0] ALE Notes: 1 = driven to VCC 0 = driven to VSS X = driven to unknown state ID = the input is disabled H = pulled up to VCC PD = pull-up disabled AO = analog output level 1. 2. 3. 4. 5. L = pulled down to VSS Z = output disabled (floats) VB = acts like a Valid Bidirectional pin VO = a Valid Output level is driven VI = Need to drive a Valid Input level † = After power fail sequence completes ‡ = Caused by Hi-Z from mode pins only Reset X1 X1 0 0† 0† 1† 1 † Norm VO VO VO VO VO VO VO VO VO VO VB VB VB VB VB VB VB VB VB VO VO VO VI VO VB VO VB VB VO VB VO VO ECC Off VO VO VO VO VO VO VO VO VO VO VB VB VB ID,Z VB VB ID,Z VB VB Z VO VO VI VO VB VO VB VB - 32-Bit DDR VO VO VO VO VO VO VO VO VO VO ID,Z VB VB VB ID,Z VB VB ID,Z VB VO Z VO VI VO VB VO VB VB - 32-Bit B_PCI - 32-Bit A_PCI - 1† 1† 0† Z † Z† Z† Z† Z † Z† Z† Z† Z † Z† Z† Z† VI 0 Z† VO VB VB H H H 0 Clocks become valid right before M_RST# deasserts. ODT signal to be low during power up and initialization per DDR-II JEDEC specification. High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0. Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of PWRGD.) May 2005 32 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 16. Pin Mode Behavior (Sheet 2 of 4) Pin POE# PWE# PCE[1]# PCE[0]# REFCLK+ REFCLKPE0Tp[7:0] PE0Tn[7:0] PE0Rp[7:0] PE0Rn[7:0] PE_RCOMPO PE_ICOMPI B_AD[63:32] B_AD[31:0] B_PAR B_PAR64 B_C/BE[7:4]# B_C/BE[3:0]# B_GNT[4:0]# B_REQ64# B_REQ[4:0]# B_ACK64# B_FRAME# B_IRDY# B_TRDY# B_STOP# B_DEVSEL# B_LOCK# B_SERR# B_CLKIN PWRGD RSTIN# B_RST# Notes: 1 = driven to VCC 0 = driven to VSS X = driven to unknown state ID = the input is disabled H = pulled up to VCC PD = pull-up disabled AO = analog output level 1. 2. 3. 4. 5. L = pulled down to VSS Z = output disabled (floats) VB = acts like a Valid Bidirectional pin VO = a Valid Output level is driven VI = Need to drive a Valid Input level † = After power fail sequence completes ‡ = Caused by Hi-Z from mode pins only Reset 1 1 H H VI Z3 ID4 VI VI 0 0 0 Z 0 0 H VO VI Z Z Z VO VO VO Z Z VI VI VI VO Norm VO VO VO VO VI VO VI VI VI VB VB VB VB VB VB VO VB VI VB VB VB VB VB VB VB VB VI VI VI VO H VB VB H H VB ECC Off 32-Bit DDR 32-Bit B_PCI 32-Bit A_PCI - Clocks become valid right before M_RST# deasserts. ODT signal to be low during power up and initialization per DDR-II JEDEC specification. High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0. Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of PWRGD.) Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 33 80333 Table 16. Pin Mode Behavior (Sheet 3 of 4) Pin B_PERR# B_M66EN B_PME# B_PCIXCAP B_CLKO[4:0] B_CLKOUT A_AD[63:32] A_AD[31:0] A_PAR A_PAR64 A_C/BE[3:0]# A_C/BE[7:4]# A_REQ64# A_ACK64# A_FRAME# A_IRDY# A_TRDY# A_STOP# A_DEVSEL# A_SERR# A_RST# A_PERR# A_LOCK# A_CLKO[3:0] A_CLKOUT A_CLKIN A_M66EN A_PME# A_REQ[3:0]# A_GNT[3:0]# A_PCIXCAP A_RCOMP Notes: 1 = driven to VCC 0 = driven to VSS X = driven to unknown state ID = the input is disabled H = pulled up to VCC PD = pull-up disabled AO = analog output level 1. 2. 3. 4. 5. L = pulled down to VSS Z = output disabled (floats) VB = acts like a Valid Bidirectional pin VO = a Valid Output level is driven VI = Need to drive a Valid Input level † = After power fail sequence completes ‡ = Caused by Hi-Z from mode pins only Reset Z VB VI VI VO VO Z 0 0 Z 0 Z VO Z Z Z VO VO VO Z VO Z Z VO VO VI VB VI VI H VI AO Norm VB VB VI VI VO VO VB VB VB VB VB VB VB VB VB VB VB VB VB VB VO VB VB VO VO VI VB VI VI VO VI AO H H H ECC Off 32-Bit DDR 32-Bit B_PCI 32-Bit A_PCI - Clocks become valid right before M_RST# deasserts. ODT signal to be low during power up and initialization per DDR-II JEDEC specification. High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0. Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of PWRGD.) May 2005 34 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 16. Pin Mode Behavior (Sheet 4 of 4) Pin B_RCOMP XINT[7:4]# XINT[3:0]# HPI# B_HPWRFLT# (5) B_HMRL# (5) B_HPRSNT2# (5) B_HPWREN (5) B_HPRSNT1# (5) B_HATNLED# (5) B_HPWRLED# (5) B_HBUTTON# (5) SCL0, SCD0, SCL1/ SCLK, SCD1/ SDTA GPIO[3:0]/ U0_RTS#, U0_CTS#, U0_TXD, U0_RXD, GPIO[7:4]/ U1_RTS#, U1_CTS#, U1_TXD, U1_RXD TCK TDI TDO TRST# TMS PWRDELAY PWRGD NC[3:0] Notes: 1 = driven to VCC 0 = driven to VSS X = driven to unknown state ID = the input is disabled H = pulled up to VCC PD = pull-up disabled AO = analog output level 1. 2. 3. 4. 5. L = pulled down to VSS Z = output disabled (floats) VB = acts like a Valid Bidirectional pin VO = a Valid Output level is driven VI = Need to drive a Valid Input level † = After power fail sequence completes ‡ = Caused by Hi-Z from mode pins only Reset AO VI VI VI VI VI VI Z VI Z Z VI H VI VI VI H VO† H H VI VI H Norm AO VI VI VI VI VI VI VO VI VO VO VI VB VB VB VI H VO H H VI VI H ECC Off 32-Bit DDR 32-Bit B_PCI 32-Bit A_PCI - Clocks become valid right before M_RST# deasserts. ODT signal to be low during power up and initialization per DDR-II JEDEC specification. High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0. Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of PWRGD.) Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 35 80333 Table 17. Pin Multiplexing for Functional Modes Pin A[20] AD[15] AD[14] AD[13] AD[12] AD[10] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] A[19] A[18] A[17] A[16] SCL1/SCLK SCD1/SDTA GPIO[0]/U0_RXD GPIO[1]/U0_TXD GPIO[2]/U0_CTS# GPIO[3]/U0_RTS# GPIO[4]/U1_RXD GPIO[5]/U1_TXD GPIO[6]/U1_CTS# GPIO[7]/U1_RTS# Reset Straps PCIODT_EN B_HSLOT[3] B_HSLOT[2] B_HSLOT[1] B_HSLOT[0] B_PCIX133EN PD1 RETRY CORE_RST# P_BOOT16# A_PCIX133EN MEM_TYPE SMB_MA5 SMB_MA3 SMB_MA2 SMB_MA1 - May 2005 36 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Figure 2. 829-Ball FCBGA Package Diagram S1 S2 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A E F1 F2 D Die Laser Mark Pin #1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 e øb Top View Bottom View A3 A Seating Plane A1 C Side View B1230-02 Table 18. FC-style, H-PBGA Package Dimensions 829-Pin BGA Symbol A A1 A3 b C D E F1 F2 e S1 S2 Measurement in millimeters. 1.15 37.45 37.45 9.88 Ref. 10.16 Ref. 1.27 Ref. 0.97 Ref. 0.97 Ref. Minimum 2.392 0.50 0.742 0.61 Ref. 1.37 37.55 37.55 Maximum 2.942 0.70 0.872 Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 37 80333 Figure 3. Intel® 80333 I/O Processor Signal Group Locations (Bottom View) 1 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 AJ AH AG DDR / DDRII SDRAM GPIO PBI VCC/VSS AF AE AD AC AB AA Y W V U T R P N M L K J SHPC PCI-X Bus B PCI-X Bus A H G F E PCI Express D C B A B1215-01 May 2005 38 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Figure 4. Intel® 80333 I/O Processor Ballout — Left Side (Bottom View) 1 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A NB NB VSS DQ[6] DM[0] DQ[5] DDR_ VREF N/C6 B_H BUTTON # VCC15 PWR DELAY 2 NB VSS DQ[3] DQ[7] VSS DQ[4] VSS VSS N/C4 TCK VSS 3 VCC25 M_RST# VSS DQ[2] DQS0# VSS VSS TDO VSS VSS XINT4# VCC33 4 DQS1# CKE1 CKE0 VCC25 DQS[0] DQ[1] VSS TMS N/C5 VSS 5 DQS[1] VSS DM[1] MA12 VSS DQ[0] VSS VSS TRST# N/C0 6 DQ[15] DQ[14] VSS DQ[9] DQ[13] VCC25 VSS RSTIN# VSS TDI 7 DQ[10] DQ[20] DQ[11] VSS DQ[8] MA7 VSS VCC25 PWRGD VSS 8 DQ[17] VSS DQ[16] DQ[21] VSS DQ[12] MA11 VSS HPI# N/C3 9 DM[2] MA6 VSS DQS2 DQS2# VSS MA9 VCC25 VSS VCC13 VSS 10 MA8 MA5 DQ[18] VCC25 DQ[23] DQ[22] VCC25 VSS VCC25 VSS VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VCC15 VCC15 11 DQ[28] VCC25 MA4 MA3 VSS DQ[19] VSS VCC25 VSS VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC PLL2 VSS VCC15 VSS B_ GNT2# 12 DQ[25] DQ[24] VSS DQ[29] MA1 VCC25 MA2 VSS VCC25 VSS VCC13 VSS VCC13 VSS VCC15 VSS VCC15 VSSA2 VCC15 VSS VCC15 13 DM[3] DQS3# DQS3 VCC25 DQ[26] BA1 MA0 VCC25 VSS VCC13 VSS VCC13 VSS VCC15 VSS VCC PLL5 VSS VCC15 VSS VCC15 VSS 14 M_CK1 VSS DQ[31] DQ[30] VSS DQ[27] CB[5] VSS VCC25 VSS VCC15 VSS VCC15 VSS VCC15 VSSA5 VCC15 VSS VSS VSS VCC15E VSS PE0RP0 15 M_ CK1# DM[8] VSS CB[1] CB[0] VSS CB[4] VCC25 VSS VCC15 VSS VCC15 VSS VCC15 VCC PLL4 VCC15 VSS VCC15 VCC PLL3 VSSA3 VSS REF_ CLKP REF CLKN VSS B_H B_ B_H B_ VCC33 RESET# HPWREN PRSNT2# PCIXCAP XINT6# VSS XINT5# VSS B_HP WRLED# B_ XINT7# RCOMP B_ C/BE4# N/C2 B_ AD63 B_ AD60 B_ AD59 B_ AD56 B_ AD53 B_ AD50 B_ AD49 B_ AD0 B_ AD3 B_ AD6 B_ C/BE0# B_ AD10 VCC33 NB NB B_RST# VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VSS B_ B_ C/BE5# C/BE7# VSS B_ PAR64 VSS B_ AD58 B_ AD55 VSS B_ REQ4# B_ AD48 VSS B_ AD4 B_ AD7 VSS B_ AD11 B_ AD13 VSS NB B_H B_HATN B_HP PRSNT1# LED# VCC33 WRFLT# VSS B_ AD45 VSS B_ AD41 B_ AD38 VCC33 B_ REQ1# B_ SERR# VCC33 DEV SEL# B_ IRDY# VSS B_ C/BE2# B_ AD17 VSS B_ AD18 B_ GNT0# VCC33 B_ AD44 B_ AD40 VCC33 B_ AD35 N/C7 VSS VSS B_ AD46 B_ AD43 VSS B_ AD37 B_ AD34 VSS B_ LOCK# B_ HMRL# B_ AD47 B_ AD42 B_ AD39 B_ AD36 B_ AD33 B_ AD32 B_ CLKO1 B_ B_ C/BE6# GNT1# VCC33 B_ AD61 B_ AD57 VCC33 B_ AD52 B_ REQ3# VCC33 B_ AD1 B_ AD5 VCC33 B_ M66EN B_ AD12 B_ AD14 B_ AD15 VSS B_ REQ0# B_ AD62 VSS B_ AD54 B_ AD51 VSS B_ PERR# B_ AD2 VSS B_ AD8 B_ AD9 VCC33 B_ PAR B_ CBE#1 B_ AD16 B_ B_ B_ B_ B_ ACK64# CLKO4 CLKO[2] CLKO3 TRDY# B_ STOP# VCC33 VSS B_ CLKO0 VSS VSS VSS B_ AD24 B_ AD25 VSS B_ AD26 B_ CLKIN VSS VCC33 B_ AD27 VSS33 B_ AD28 B_ AD29 VCC33 VSS VSS VSS B_ AD30 B_ AD31 VSS B_ B_PME# GNT4# VSS B_ B_ REQ64# REQ2# B_ GNT3# VSS VSS PE0TP0 PE0RN0 B_ B_ FRAME# CLKOUT B_ AD19 VCC33 B_ AD20 B_ AD21 VSS B_ AD22 B_ AD23 B_ C/BE3# PE0RP1 PE0TN0 VCC15E PE0TP3 VSS PE0RP3 PE0TN3 VSS PE_ RCOMPO PE0TN2 PE0RN1 PE0TP2 PE0TP1 VCC15E PE0RN3 VSS PE0TN1 VSS VSS PE0RP2 PE0RN2 VCC15E PE_ PE_ VSSBG VCCBG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B1239-03 Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 39 80333 Figure 5. Intel® 80333 I/O Processor Ballout — Right Side (Bottom View) 16 M_CK0 17 M_CK0# 18 DQ[36] 19 DM[4] 20 DQ[38] 21 DQ[35] 22 DQ[40] 23 DQS5# 24 DQ[46] 25 DQS#6 26 DQS6 27 VSS 28 NB 29 NB AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A VCC25 M_CK2 DQ[37] VSS DQ[39] DQ[44] VSS DQS5 DQ[47] VSS DQ[54] DQ[55] VSS NB DQS[8] M_CK2# VSS DQS4# DQ[34] VSS DQ[41] DQ[42] VSS DM[6] DQ[50] DQ[51] DQ[60] VSS DQS8# VCC25 DQ[32] DQS[4] VCC25 DQ[45] VCC25 DQ[43] DQ[48] DQ[49] VCC25 DQ[61] DQ[56] DQS7# VSS CB[7] DQ[33] VSS CS0# DM[5] VSS DQ[53] DQ[52] VSS DQ[57] DM[7] VSS DQS7 CB[6] CB[2] BA[0] VCC25 WE# VSS MA13 CS1# VCC25 DQ[62] DQ[63] VSS DQ[59] DQ[58] CB[3] VSS MA10 RAS# VCC25 CAS# ODT0 VSS SDTA GPIO [5] GPIO [4] GPIO [0] DDR DDRSLW DDRIMP CRES CRES CRES0 GPIO [1] DDR RES1 DDR RES2 VSS VCC25 VSS VCC25 ODT1 SCD0 SCLK GPIO [6] GPIO [7] VSS VCC25 VSS VCC25 VSS VCC25 GPIO [2] GPIO [3] SCL0 VCC33 PCE1# PCE0# VSS ALE A[1] VSS VCC15 VSS VCC15 VSS PWE# AD[15] VSS AD[11] A[0] VCC33 A[17] A[21] A[20] VCC15 VSS VCC15 VSS VCC33 A[2] A[22] AD[7] AD[2] VSS AD[8] AD[9] VSS A[16] VSS VCC15 VSS VCC15 VSS POE# A[19] AD[3] VCC33 AD[13] AD[5] VSS AD[1] AD[0] VCC15 VSS VCC15 VSS VCC33 A[18] AD[14] VSS AD[12] A_ GNT3# VCC33 XINT#0 XINT1# A_ AD48 A_ RCOMP A_ AD53 A_ AD56 A_ AD58 A_ AD60 A_ AD63 A_ PAR64 VSS VCC15 VSS VCC15 VSS AD[10] AD[6] AD[4] XINT2# VSS AD[49] A_ AD50 VSS VSSA4 VSS VCC15 VSS A_ VCC33 A_RST# PCIXCAP A_ GNT2# A_ AD35 A_ AD38 A_ AD41 A_ AD42 A_ AD47 A_ AD3 A_ AD4 A_ AD5 XINT3# VCC33 A_ PME# AD[51] VCC33 A_ AD52 VSS VCC15 VSS VCC15 VSS VCC33 A_ AD32 A_ AD33 A_ AD34 VSS AD[54] A_ AD55 A_ AD59 VSS VCC15 VSS VCC15 VSS VCC33 VSS VCC33 A_ REQ0# A_ AD36 VCC33 A_ AD57 A_ AD61 VSS VCC15 VSSA1 VCC PLL1 VSS VCC33 A_ AD37 A_ AD39 VSS A_ AD62 A_ C/BE6# VCC33 VSS VSS VCC15 VSS VCC33 VSS A_ AD40 A_ AD43 VCC33 A_ C/BE7# A_ C/BE4# VSS VSS VCC33 VSS VCC33 VSS VCC33 VSS A_ REQ3# A_ AD45 VSS A_ C/BE5# VCC15E VSS VCC33 VSS VCC33 VSS A_ AD46 A_ CLKO3 VCC33 A_ AD44 VCC33 A_ A_ ACK64# REQ64# VSS A_ C/BE1# A_ AD14 A_ AD15 A_ AD11 A_ AD12 A_ AD13 A_ C/BE0# A_ AD6 A_ AD7 A_ CLKO0 A_ CLKO1 VSS VCC33 VSS VSS VSS PE0TN7 VSS VSS VCC33 A_ CLKOUT A_ CLKO2 VSS A_ CLKIN VSS A_ PERR# PE0TP7 PE0RN7 VSS A_ AD9 A_ AD10 VCC33 A_ AD1 A_ AD2 VSS A_PAR VSS A_ A_ REQ1# DEVSEL# A_ TRDY# A_ STOP# A_ FRAME# A_ IRDY# VCC15E PE0RP7 PE0RP5 VSS A_ REQ2# A_ AD8 VSS A_AD0 VSS A_ SERR# A_ LOCK# A_ C/BE3# A_ C/BE2# A_ AD16 PE0RP4 VSS PE0RN5 PE0TP5 VSS A_ AD27 A_ AD28 VSS A_AD23 A_ AD20 A_ AD21 VCC33 VSS PE0RN4 PE0TP4 VCC15E PE0TN5 A_ M66EN VCC33 A_ AD25 A_ AD26 A_ GNT0# VCC33 A_ AD17 A_ AD18 A_ AD19 VCC33 VSS PE0TN4 PE0RN6 VSS VSS A_ AD30 A_ AD31 VSS A_ GNT1# A_ AD24 VSS VSS NB PE_ ICOMPI VSS PE0RP6 PE0TP6 PE0TN6 A_ AD29 A_ AD22 VSS NB NB 16 17 18 19 20 21 22 23 24 25 26 27 28 29 B1240-02 May 2005 40 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 19. Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 829-Lead Package — Alphabetical Ball Listings (Sheet 1 of 7) Signal --VSS B_AD16 B_AD18 B_AD21 B_C/BE3# B_AD26 B_AD29 VSS PE0RP2 PE0RN2 VCC15E PE_VSSBG PE_VCCBG PE_ICOMPI VSS PE0RP6 PE0TP6 PE0TN6 A_AD31 A_AD29 A_GNT0# A_AD24 A_AD22 A_AD19 VSS ---VSS B_AD15 B_C/BE1# VSS B_AD20 B_AD23 VSS B_AD28 B_AD31 VSS PE0TN1 Ball B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 Signal VSS VSS PE_RCOMPO VSS PE0TN4 PE0RN6 VSS VSS A_AD30 VSS A_AD26 A_GNT1# VSS A_AD18 A_AD16 VSS -VCC33 B_AD13 B_AD14 B_PAR B_AD17 VCC33 B_AD22 B_AD25 VCC33 B_AD30 PE0TP2 PE0TP1 VCC15E PE0RN3 VSS PE0RN4 PE0TP4 VCC15E PE0TN5 A_M66EN VCC33 A_AD28 A_AD25 VCC33 Ball C25 C26 C27 C28 C29 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 E1 E2 E3 E4 E5 E6 E7 Signal A_AD21 A_AD17 A_C/BE2# A_FRAME# VCC33 B_AD10 B_AD11 B_AD12 VCC33 B_C/BE2# B_AD19 VSS B_AD24 B_AD27 VSS PE0TN2 PE0RN1 VSS PE0RP3 PE0TN3 PE0RP4 VSS PE0RN5 PE0TP5 VSS A_AD8 A_AD27 VSS A_AD23 A_AD20 VCC33 A_C/BE3# A_STOP# VSS B_C/BE0# VSS B_M66EN B_AD9 VSS B_FRAME# B_CLKOUT Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 41 80333 Table 19. Ball E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 829-Lead Package — Alphabetical Ball Listings (Sheet 2 of 7) Signal VSS VCC33 VSS VSS PE0RP1 PE0TN0 VCC15E PE0TP3 VCC15E PE0RP7 PE0RP5 VSS A_AD10 A_REQ2# VSS A_AD2 A_AD0 VSS A_SERR# A_LOCK# A_TRDY# A_IRDY# B_AD6 B_AD7 VCC33 B_AD8 B_IRDY# VCC33 B_CLKO0 VSS VSS VSS B_GNT3# VSS PE0TP0 PE0RN0 VSS PE0TP7 PE0RN7 VSS A_AD13 Ball F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 H1 H2 Signal A_AD9 VCC33 A_AD5 A_AD1 VSS A_CLKO2 A_PAR VSS A_REQ1# A_DEVSEL# B_AD3 B_AD4 B_AD5 VSS B_DEVSEL# B_STOP# VSS VSS B_CLKIN VCC33 B_REQ64# B_REQ2# VSS PE0RP0 REFCLKPE0TN7 VSS A_AD15 A_AD12 VSS A_AD7 A_AD4 VCC33 A_CLKO1 A_CLKOUT VSS A_CLKIN VSS A_PERR# B_AD0 VSS Ball H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 Signal B_AD1 B_AD2 VCC33 B_ACK64# B_CLKO4 B_CLKO2 B_CLKO3 B_TRDY# B_GNT2# B_GNT4# B_PME# VSS REFCLK+ VSS A_C/BE1# A_AD14 A_AD11 A_C/BE0# A_AD6 A_AD3 A_CLKO3 A_CLKO0 VSS VCC33 VSS VSS VSS B_AD49 B_AD48 VCC33 B_PERR# B_SERR# VSS B_LOCK# B_CLKO1 VSS VCC15 VSS VCC15 VSS VCC15E May 2005 42 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 19. Ball J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 829-Lead Package — Alphabetical Ball Listings (Sheet 3 of 7) Signal VSS VCC15E VSS VCC33 VSS VCC33 VSS A_AD47 A_AD46 VCC33 A_AD45 A_AD44 VCC33 A_ACK64# A_REQ64# B_AD50 B_REQ4# B_REQ3# VSS B_REQ1# N/C7 VSS B_AD32 VCC15 VCC15 VCC15 VSS VCC15 VSS VSSA3 VSS VCC33 VSS VCC33 VSS VCC33 A_AD42 VSS A_AD43 A_REQ3# VSS Ball K27 K28 K29 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 M1 M2 M3 M4 M5 M6 M7 M8 M9 Signal A_C/BE4# A_C/BE5# A_PAR64 B_AD53 VSS B_AD52 B_AD51 VCC33 B_AD35 B_AD34 B_AD33 VSS VCC15 VSS VCC15 VSS VSS VCCPLL3 VSS VSS VCC15 VSS VCC33 VSS A_AD41 A_AD39 A_AD40 VCC33 A_C/BE6# A_C/BE7# VSS A_AD63 B_AD56 B_AD55 VCC33 B_AD54 B_AD38 VCC33 B_AD37 B_AD36 VCC15 Ball M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 Signal VSS VCCPLL2 VSSA2 VCC15 VSS VCC15 VSS VCC15 VSSA1 VCCPLL1 VSS VCC33 A_AD38 A_AD37 VSS A_AD36 A_AD62 VCC33 A_AD61 A_AD60 B_AD59 B_AD58 B_AD57 VSS B_AD41 B_AD40 VSS B_AD39 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC33 VSS Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 43 80333 Table 19. Ball N22 N23 N24 N25 N26 N27 N28 N29 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 R1 R2 R3 R4 829-Lead Package — Alphabetical Ball Listings (Sheet 4 of 7) Signal A_AD35 VCC33 A_AD34 A_REQ0# VCC33 A_AD59 A_AD57 A_AD58 B_AD60 VSS B_AD61 B_AD62 VSS B_AD44 B_AD43 B_AD42 VCC15 VSS VCC15 VSS VCCPLL5 VSSA5 VCC15 VSS VCC15 VSS VCC15 VSS VCC33 A_GNT2# A_AD32 A_AD33 VSS A_AD54 A_AD55 VSS A_AD56 B_AD63 B_PAR64 VCC33 B_REQ0# Ball R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Signal B_AD45 VCC33 B_AD46 B_AD47 VSS VCC15 VSS VCC15 VSS VCC15 VCCPLL4 VSSA4 VSS VCC15 VSS VCC33 A_PCIXCAP A_RST# XINT3# VCC33 A_PME# A_AD51 VCC33 A_AD52 A_AD53 N/C2 VSS B_C/BE6# B_GNT1# VSS B_GNT0# VSS B_HMRL# VCC15 VSS VCC15 VSS VCC15 VSS VCC15 VSS Ball T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 Signal VCC15 VSS VCC15 VSS AD10 AD6 AD4 XINT2# VSS A_AD49 A_AD50 VSS A_RCOMP B_C/BE4# B_C/BE5# B_C/BE7# VSS B_HPRSNT1# B_HATNLED# VCC33 B_HPWRFLT# VSS VCC15 VSS VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC33 A18 AD14 VSS AD12 A_GNT3# VCC33 XINT0# XINT1# May 2005 44 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 19. Ball U29 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 829-Lead Package — Alphabetical Ball Listings (Sheet 5 of 7) Signal A_AD48 B_RCOMP XINT7# VCC33 XINT6# XINT5# VSS B_HPWRLED# B_RST# VCC15 VSS VCC15 VSS VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS POE# A19 AD3 VCC33 AD13 AD5 VSS AD1 AD0 PWRDELAY VSS XINT4# B_PCIXCAP VCC33 B_HRESET# B_HPWREN B_HPRSNT2# VSS VCC13 VSS Ball W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Signal VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS VCC33 A2 A22 AD7 AD2 VSS AD8 AD9 VSS A16 VCC15 TCK VSS VSS N/C0 TDI VSS N/C3 VCC13 VSS VCC13 VSS VCC13 VSS VCC15 VSS VCC15 VSS VCC15 VSS PWE# AD15 VSS Ball Y24 Y25 Y26 Y27 Y28 Y29 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AB1 AB2 AB3 AB4 AB5 AB6 Signal AD11 A0 VCC33 A17 A21 A20 B_HBUTTON# N/C4 VSS N/C5 TRST# VSS PWRGD HPI# VSS VCC25 VSS VCC25 VSS VCC25 VSS VCC25 VSS VCC25 VSS VCC25 GPIO2/U0_CTS# GPIO3/U0_RTS# SCL0 VCC33 PCE1# PCE0# VSS ALE A1 N/C6 VSS TDO TMS VSS RSTIN# Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 45 80333 Table 19. Ball AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 829-Lead Package — Alphabetical Ball Listings (Sheet 6 of 7) Signal VCC25 VSS VCC25 VSS VCC25 VSS VCC25 VSS VCC25 VSS VCC25 VSS VCC25 ODT1 SCD0 SCLK/SCL1 GPIO6/U1_CTS# GPIO7/U1_RTS# VSS GPIO0/U0_RXD GPIO1/U0_TXD DDRRES1 DDRRES2 DDR_VREF VSS VSS VSS VSS VSS VSS MA11 MA9 VCC25 VSS MA2 MA0 CB5 CB4 CB3 VSS MA10 Ball AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AE1 Signal RAS# VCC25 CAS# ODT0 VSS SDTA/SCD1 GPIO5/U1_TXD GPIO4/U1_RXD DDRCRES0 DDRSLWCRES DDRIMPCRES DQ5 DQ4 VSS DQ1 DQ0 VCC25 MA7 DQ12 VSS DQ22 DQ19 VCC25 BA1 DQ27 VSS CB6 CB2 BA0 VCC25 WE# VSS MA13 CS1# VCC25 DQ62 DQ63 VSS DQ59 DQ58 DM0 Ball AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 Signal VSS DQS0# DQS0 VSS DQ13 DQ8 VSS DQS2# DQ23 VSS MA1 DQ26 VSS CB0 VSS CB7 DQ33 VSS CS0# DM5 VSS DQ53 DQ52 VSS DQ57 DM7 VSS DQS7 DQ6 DQ7 DQ2 VCC25 MA12 DQ9 VSS DQ21 DQS2 VCC25 MA3 DQ29 VCC25 May 2005 46 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 19. Ball AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 829-Lead Package — Alphabetical Ball Listings (Sheet 7 of 7) Signal DQ30 CB1 DQS_8# VCC25 DQ32 DQS4 VCC25 DQ45 VCC25 DQ43 DQ48 DQ49 VCC25 DQ61 DQ56 DQS7# VSS DQ3 VSS CKE0 DM1 VSS DQ11 DQ16 VSS DQ18 MA4 VSS DQS3 DQ31 VSS DQS8 M_CK2# VSS DQS4# DQ34 VSS DQ41 DQ42 VSS DM6 Ball AG26 AG27 AG28 AG29 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 Signal DQ50 DQ51 DQ60 VSS -VSS M_RST# CKE1 VSS DQ14 DQ20 VSS MA6 MA5 VCC25 DQ24 DQS3# VSS DM8 VCC25 M_CK2 DQ37 VSS DQ39 DQ44 VSS DQS5 DQ47 VSS DQ54 DQ55 VSS ---VCC25 DQS1# DQS1 DQ15 DQ10 DQ17 Ball AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 Signal DM2 MA8 DQ28 DQ25 DM3 M_CK1 M_CK1# M_CK0 M_CK0# DQ36 DM4 DQ38 DQ35 DQ40 DQS5# DQ46 DQS6# DQS6 VSS --- Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 47 80333 Table 20. ------------- 829-Lead Package — Alphabetical Signal Listings (Sheet 1 of 7) Ball A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 J28 E24 F23 E23 H22 G22 F22 H21 G21 D21 F20 E20 H19 G19 F19 H18 G18 B27 C26 B26 A26 D25 C25 A25 D24 A24 C23 B23 D22 Y28 W22 Signal A_AD28 A_AD29 A_AD30 A_AD31 A_AD32 A_AD33 A_AD34 A_AD35 A_AD36 A_AD37 A_AD38 A_AD39 A_AD40 A_AD41 A_AD42 A_AD43 A_AD44 A_AD45 A_AD46 A_AD47 A_AD48 A_AD49 A_AD50 A_AD51 A_AD52 A_AD53 A_AD54 A_AD55 A_AD56 A_AD57 A_AD58 A_AD59 A_AD60 A_AD61 A_AD62 A_AD63 A_C/BE0# A_C/BE1# A_C/BE2# A_C/BE3# A_C/BE4# B_AD21 B_AD22 Ball C22 A22 B21 A21 P23 P24 N24 N22 M25 M23 M22 L23 L24 L22 K22 K24 J26 J25 J23 J22 U29 T26 T27 R26 R28 R29 P26 P27 P29 N28 N29 N27 M29 M28 M26 L29 H20 H17 C27 D27 K27 A6 C7 Signal A_C/BE5# A_C/BE6# A_C/BE7# A_CLKIN A_CLKO0 A_CLKO1 A_CLKO2 A_CLKO3 A_CLKOUT A_DEVSEL# A_FRAME# A_GNT0# A_GNT1# A_GNT2# A_GNT3# A_IRDY# A_LOCK# A_M66EN A_PAR A_PAR64 A_PCIXCAP A_PERR# A_PME# A_RCOMP A_REQ0# A_REQ1# A_REQ2# A_REQ3# A_REQ64# A_RST# A_SERR# A_STOP# A_TRDY# A0 A1 A2 A16 A17 A18 A19 A20 B_AD62 B_AD63 Ball K28 L26 L27 G27 H24 G24 F25 H23 G25 F29 C28 A23 B24 P22 U25 E29 E27 C20 F26 K29 R21 G29 R25 T29 N25 F28 E21 K25 J29 R22 E26 D28 E28 Y25 AA29 W21 W29 Y27 U21 V22 Y29 P4 R1 Signal A_ACK64# A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A21 A22 May 2005 48 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 20. AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE 829-Lead Package — Alphabetical Signal Listings (Sheet 2 of 7) Ball V29 V28 W24 V23 T23 V26 T22 W23 W26 W27 T21 Y24 U24 V25 U22 Y22 AA28 H6 H1 H3 H4 G1 G2 G3 F1 F2 F4 E4 D1 D2 D3 C2 C3 B3 A4 C5 A5 D6 B6 Signal B_AD23 B_AD24 B_AD25 B_AD26 B_AD27 B_AD28 B_AD29 B_AD30 B_AD31 B_AD32 B_AD33 B_AD34 B_AD35 B_AD36 B_AD37 B_AD38 B_AD39 B_AD40 B_AD41 B_AD42 B_AD43 B_AD44 B_AD45 B_AD46 B_AD47 B_AD48 B_AD49 B_AD50 B_AD51 B_AD52 B_AD53 B_AD54 B_AD55 B_AD56 B_AD57 B_AD58 B_AD59 B_AD60 B_AD61 Ball B7 D8 C8 A8 D9 B9 A9 C10 B10 K8 L8 L7 L6 M8 M7 M5 N8 N6 N5 P8 P7 P6 R5 R7 R8 J2 J1 K1 L4 L3 L1 M4 M2 M1 N3 N2 N1 P1 P3 Signal B_C/BE0# B_C/BE1# B_C/BE2# B_C/BE3# B_C/BE4# B_C/BE5# B_C/BE6# B_C/BE7# B_CLKIN B_CLKO0 B_CLKO1 B_CLKO2 B_CLKO3 B_CLKO4 B_CLKOUT B_DEVSEL# B_FRAME# B_GNT0# B_GNT1# B_GNT2# B_GNT3# B_GNT4# B_HPWRFLT# B_HPRSNT2# B_HMRL# B_HPWREN B_HPWRLED# B_HPRSNT1# B_HATNLED# B_HBUTTON# B_IRDY# B_LOCK# B_M66EN B_PAR B_PAR64 B_PCIXCAP B_PERR# B_PME# B_RCOMP Ball E1 B4 D5 A7 U1 U2 T3 U3 G9 F7 J8 H8 H9 H7 E7 G5 E6 T6 T4 H11 F11 H12 U8 W8 T8 W7 V7 U5 U6 AA1 F5 J7 E3 C4 R2 W4 J4 H13 V1 Signal B_ACK64# B_AD0 B_AD1 B_AD2 B_AD3 B_AD4 B_AD5 B_AD6 B_AD7 B_AD8 B_AD9 B_AD10 B_AD11 B_AD12 B_AD13 B_AD14 B_AD15 B_AD16 B_AD17 B_AD18 B_AD19 B_AD20 Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 49 80333 Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 3 of 7) Ball R4 K5 G12 K3 K2 G11 V8 J5 G6 H10 AD18 AD13 AC21 AE15 AF15 AD17 AC16 AC15 AC14 AD16 AE17 AG4 AH4 AE20 AD23 AC1 AC27 AC29 AB28 AB29 AC28 AE1 AG5 AJ9 AJ13 AJ19 AE21 AG25 AE27 AH15 AD5 Signal DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 Ball AD4 AF3 AG2 AD2 AD1 AF1 AF2 AE7 AF6 AJ7 AG7 AD8 AE6 AH6 AJ6 AG8 AJ8 AG10 AD11 AH7 AF8 AD10 AE10 AH12 AJ12 AE13 AD14 AJ11 AF12 AF14 AG14 AF18 AE18 AG20 AJ21 AJ18 AH18 AJ20 AH20 AJ22 AG22 Signal DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0 DQS0# DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS_8# GPIO0/U0_RXD Ball AG23 AF23 AH21 AF21 AJ24 AH24 AF24 AF25 AG26 AG27 AE24 AE23 AH26 AH27 AF28 AE26 AD29 AD28 AG28 AF27 AD25 AD26 AE4 AE3 AJ5 AF9 AG13 AF19 AH23 AJ26 AE29 AG16 AJ4 AE9 AH13 AG19 AJ23 AJ25 AF29 AF16 AB26 Signal B_REQ0# B_REQ1# B_REQ2# B_REQ3# B_REQ4# B_REQ64# B_RST# B_SERR# B_STOP# B_TRDY# BA0 BA1 CAS# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CKE0 CKE1 CS0# CS1# DDR_VREF DDRCRES0 DDRIMPCRES DDRRES1 DDRRES2 DDRSLWCRES DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DQ0 May 2005 50 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 4 of 7) Ball AB27 AA21 AA22 AC26 AC25 AB23 AB24 AA8 AJ16 AJ14 AH17 AJ17 AJ15 AG17 AH3 AC13 AE12 AC12 AF11 AG11 AH10 AH9 AD7 AJ10 AC9 AC18 AC8 AF5 AD22 Y5 W6 T1 Y8 AA2 AA4 AB1 K6 AC22 AB20 AA26 AA25 Signal PE_ICOMPI PE_RCOMPO PE_VCCBG PE_VSSBG PE0RN0 PE0RN1 PE0RN2 PE0RN3 PE0RN4 PE0RN5 PE0RN6 PE0RN7 PE0RP0 PE0RP1 PE0RP2 PE0RP3 PE0RP4 PE0RP5 PE0RP6 PE0RP7 PE0TN0 PE0TN1 PE0TN2 PE0TN3 PE0TN4 PE0TN5 PE0TN6 PE0TN7 PE0TP0 PE0TP1 PE0TP2 PE0TP3 PE0TP4 PE0TP5 PE0TP6 PE0TP7 POE# PWE# PWRDELAY PWRGD RAS# Ball A16 B15 A15 A14 F14 D12 A12 C14 C16 D18 B18 F17 G14 E12 A11 D14 D16 E18 A18 E17 E13 B12 D11 D15 B17 C19 A20 G16 F13 C12 C11 E15 C17 D19 A19 F16 V21 Y21 W1 AA7 AC19 Signal REFCLKREFCLK+ RSTIN# SCD0 SCD1/SDTA SCL0 SCL1/SCLK TCK TDI TDO TMS TRST# VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC15E VCC15E VCC15E VCC15E VCC15E VCC15E VCC15E VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 Ball G15 H15 AB6 AB21 AC24 AA23 AB22 Y2 Y6 AB3 AB4 AA5 U12 V13 W10 W12 Y9 Y11 Y13 A13 C13 C18 E14 E16 J14 J16 J10 J12 K9 K10 K11 K13 L10 L12 L18 M9 M13 M15 M17 N10 N12 Signal GPIO1/U0_TXD GPIO2/U0_CTS# GPIO3/U0_RTS# GPIO4/U1_RXD GPIO5/U1_TXD GPIO6/U1_CTS# GPIO7/U1_RTS# HPI# M_CK0 M_CK1 M_CK2 M_CK0# M_CK1# M_CK2# M_RST# MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 N/C0 B_HRESET# N/C2 N/C3 N/C4 N/C5 N/C6 N/C7 ODT0 ODT1 PCE0# PCE1# Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 51 80333 Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 5 of 7) Ball N14 N16 N18 P9 P11 P15 P17 P19 R10 R12 R14 R18 T9 T11 T13 T15 T17 T19 U10 U14 U16 U18 V9 V11 V15 V17 V19 W14 W16 W18 Y1 Y15 Y17 Y19 AB7 AB9 AA10 AA12 AA14 AA16 AA18 Signal VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 Ball AA20 AB11 AB13 AB15 AB17 AB19 AC10 AC20 AD6 AD12 AD19 AD24 AF4 AF10 AF13 AF17 AF20 AF22 AF26 AH11 AH16 AJ3 C1 C6 C9 C21 C24 C29 D4 D26 E9 F3 F6 F21 G10 G23 H5 H26 J3 J18 J20 Signal VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCCPLL1 VCCPLL2 VCCPLL3 VCCPLL4 VCCPLL5 VSS VSS VSS VSS VSS VSS Ball J24 J27 K17 K19 K21 L5 L20 L25 M3 M6 M21 M27 N20 N23 N26 P21 R3 R6 R20 R24 R27 U7 U20 U26 V24 V3 W5 W20 Y26 AA24 M19 M11 L15 R15 P13 A3 A10 A17 A27 B2 B5 Signal VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 May 2005 52 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Table 20. VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 829-Lead Package — Alphabetical Signal Listings (Sheet 6 of 7) Ball B8 B11 B13 B14 B16 B19 B20 B22 B25 B28 C15 D7 D10 D13 D17 D20 D23 D29 E2 E5 E8 E10 E11 E19 E22 E25 F8 F9 F10 F12 F15 F18 F24 F27 G4 G7 G8 G13 G17 G20 G26 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball G28 H2 H14 H16 H25 H27 H28 H29 J6 J9 J11 J13 J15 J17 J19 J21 K4 K7 K12 K14 K16 K18 K20 K23 K26 L2 L9 L11 L13 L14 L16 L17 L19 L21 L28 M10 M14 M16 M20 M24 N4 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball N7 N9 N11 N13 N15 N17 N19 N21 P2 P5 P10 P12 P16 P18 P20 P25 P28 R9 R11 R13 R17 R19 T2 T5 T7 T10 T12 T14 T16 T18 T20 T25 T28 U4 U9 U11 U13 U15 U17 U19 U23 Signal Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 53 80333 Table 20. VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 829-Lead Package — Alphabetical Signal Listings (Sheet 7 of 7) Ball V6 V10 V12 V14 V16 V18 V20 V27 W2 W9 W11 W13 W15 W17 W19 W25 W28 Y3 Y4 Y7 Y10 Y12 Y14 Y16 Y18 Y20 Y23 AA3 AA6 AA9 AA11 AA13 AA15 AA17 AA19 AA27 AB2 AB5 AB8 AB10 AB12 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball AB14 AB16 AB18 AB25 AC2 AC3 AC4 AC5 AC6 AC7 AC11 AC17 AC23 AD3 AD9 AD15 AD21 AD27 AE2 AE5 AE8 AE11 AE14 AE16 AE19 AE22 AE25 AE28 AF7 AG1 AG3 AG6 AG9 AG12 AG15 AG18 AG21 AG24 AG29 AH2 AH5 Signal VSS VSS VSS VSS VSS VSS VSS VSSA1 VSSA2 VSSA3 VSSA4 VSSA5 WE# XINT0# XINT1# XINT2# XINT3# XINT4# XINT5# XINT6# XINT7# Ball AH8 AH14 AH19 AH22 AH25 AH28 AJ27 M18 M12 K15 R16 P14 AD20 U27 U28 T24 R23 W3 V5 V4 V2 Signal May 2005 54 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 3.2 Package Thermal Specifications See Intel® 80333 I/O Processor Thermal Design Guidelines Application Note (306630). Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 55 80333 4.0 4.1 Table 21. Electrical Specifications Absolute Maximum Ratings Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Under Bias Supply Voltage VCC33 wrt. VSS Supply Voltage VCC25 wrt. VSS Supply Voltage VCC15 wrt. VSS Supply Voltage VCC13 wrt. VSS Voltage on Any Ball wrt. VSS Maximum Rating –55° C to +125°C 0°C to +95°C –0.5 V to +4.1 V –0.5 V to +3.2 V –0.5 V to +2.1 V –0.5 V to +2.1 V –0.5 V to VCCP + 0.5 V NOTE: This data sheet contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available. The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design. WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability. Table 22. Operating Conditions Symbol VCC33 VCC25/18 VCC15 VCC13 VCCPLL1-5 Parameter 3.3 V PCI/PCI-X Supply Voltage 2.5 V/1.8V DDR/DDR-II Supply Voltage 1.5 V IOP Core Supply Voltage 1.35 V Intel XScale® core Supply Voltage PLL Supply Voltage Minimum 3.0 2.3/1.7 1.425 1.282 VCC15 0.49VCC25/18 2.375 100 -300 ppm 0 Maximum 3.6 2.7/1.9 1.575 1.418 VCC15 0.51 VCC25/18 2.625 100 + 300 ppm 95 MHz °C Units V V V V V V ±5% 100 MHz nominal Notes ±10% ±8%, 5%1 ±5%1 ±5% DDR_VREF Memory I/O Reference Voltage PE_VCCBG 2.5 V PCI Express* VCC Band Gap REFCLK Input Clock Frequency Case Temperature Under Bias TC Notes: 1. ±3% DC; additional ±2% for AC transients. Under no circumstance may the supply voltage go past the AC min./max. window. The supply voltage window may go outside the DC min./max. window for transient events. 4.2 VCCPLL Pin Requirements The VCCPLL[1-5] balls for the Phase Lock Loop (PLL) circuit must each have filters, and be connected to the appropriate VSSA ball. See the Intel® 80333 I/O Processor Design Guide for specific recommendations. May 2005 56 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 4.3 Table 23. Symbol VIL1 VIH1 VIL2 VIH2 VIL2 VIH2 VIL3 VIH3 VIL5 VOL2 VOH2 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 CIN CCLK LPIN Targeted DC Specifications DC Characteristics Parameter Input Low Voltage (DDR SDRAM) Input High Voltage (DDR SDRAM) Input Low Voltage (DDR-II SDRAM) Input High Voltage (DDR-II SDRAM) Input Low Voltage (Misc.) Input High Voltage (Misc.) Input Low Voltage (PCI-X) Input High Voltage (PCI-X/PCI) Input Low Voltage (PCI) Output Low Voltage (Misc.) Output High Voltage (Misc.) Output Low Voltage (DDR SDRAM) Output High Voltage (DDR SDRAM) Output Low Voltage (DDR-II SDRAM) Output High Voltage (DDR-II SDRAM) Output Low Voltage (PCI-X) Output High Voltage (PCI-X) Input pin Capacitance PCI clock pin Capacitance Ball Inductance 0.9 × VCC33 8 8 15 1.314 0.1 × VCC33 1.95 0.414 2.4 0.35 Minimum -0.3 DDR_VREF + 0.18 -0.2 DDR_VREF + 0.125 -0.3 2.0 -0.5 0.5 × VCC33 -0.5 Maximum DDR_VREF - 0.18 VCC25 + 0.3 DDR_VREF - 0.125 VCC25 + 0.2 0.8 VCC33 + 0.3 0.35 × VCC33 VCC33 + 0.5 0.3 × VCC33 0.4 Units V V V V V V V V V V V V V V V V V pF pF nH IOL = 6 mA IOH = -2 mA IOL = 12.5 mA (1, 2) IOH = -12.5 mA (1, 2) IOL = 20.7mA (3) IOH = -18mA (3) IOL = 1500 µA IOH = -500 µA (6) (6) (1, 2, 6) (1, 2) (1, 2) (1, 3) (1, 3) (4, 5) (4, 5) Notes Notes: 1. SDRAM signals include MA[12:0], BA[1:0], CAS#, CS[1:0]#, CKE[1:0], DM[8:0], RAS#, WE#,M_CK[2:0], M_CK[2:0]#, DQ[63:0], DQS[8:0] and CB[7:0]. 2. For 2.5 V DDR SDRAM support. 3. For 1.8 V DDR-II SDRAM support. 4. Miscellaneous signals include all signals that are not PCI-X or SDRAM signals. 5. Includes PCI-X Express Auxiliary signals; PWRGD 6. Ensured by design. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 57 80333 Table 24. ICC Characteristics Symbol ILI1 ILI2 Parameter Input Leakage Current for each signal except TCK, TMS, TRST#, TDI Input Leakage Current for TCK, TMS, TRST#, TDI -140 Typ. Max. ±2 -250 Units µA µA Notes 0 ≤ VIN ≤ VCC (4) VIN = 0.45 V (1, 4) Power Supply Current - PCI-X interfaces ICC33 Active Both at 66 MHz (Power Supply) Both at 100 MHz Both at 133 MHz ICC25 Active Power Supply Current - DDR (Power Supply) ICC18 Active Power Supply Current - DDR-II (Power Supply) ICC15 Active Power Supply Current - IOP/Bridge core (Power Supply) Power Supply Current - Intel XScale core ® 1.33 1.20 1.04 0.580 0.487 4.7 A A A A (1, 2) (1, 2) (1, 2) (1, 2) ICC13 Active (Power Supply) 800 MHz 667 MHz 500 MHz ICC33 Active (Thermal) ICC25 Active (Thermal) ICC18 Active (Thermal) ICC15 Active (Thermal) ICC13 Active (Thermal) 0.453 0.411 0.358 1.08 1.00 0.914 0.295 0.255 3.8 (1, 2) A Thermal Current - PCI-X interfaces Both at 66 MHz Both at 100 MHz Both at 133 MHz Thermal Current - DDR Thermal Current - DDR-II Thermal Current - IOP/Bridge core Thermal Current - Intel XScale® core 800 MHz 667 MHz 500 MHz 0.430 0.390 0.340 (1, 3) A (1, 3) A A A A (1, 3) (1, 3) (1, 3) Notes: 1. Measured with device operating and outputs loaded to the test condition in Figure 14, “AC Test Load for All Signals Except PCI and DDR SDRAM” on page 73. 2. ICC Active (Power Supply) value is provided for selecting the system power supply. This is based on the worst case data patterns and skew material at the following worst case voltages: VCC33 = 3.63 V, VCC25 = 2.7 V, Vcc18 = 1.9v, VCC15 = 1.575 V, VCC13 = 1.41 V. 3. ICC Active (Thermal) value is provided for selecting the system thermal design power (TDP). This is based on the following typical voltages: VCC33 = 3.3 V, VCC25 = 2.5 V, Vcc18 = 1.8v, VCC15 = 1.5 V, VCC13 = 1.35 V. 4. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. May 2005 58 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 4.4 4.4.1 Table 25. Symbol TF1 TC1 TCH1 TCL1 TSR1 Targeted AC Specifications Clock Signal Timings PCI Clock Timings PCI-X 133 Parameter Min. PCI clock Frequency PCI clock Cycle Time - Avg. PCI clock High Time PCI clock Low Time PCI clock Slew Rate 100 7.5 3 3 1.5 4 Max 133 10 Min. 66 10 9.875 PCI-X 100 Max 100 15 PCI-X 66 Min. 50 15 14.8 6 6 Max 66 20 PCI 66 Min. 33 15 14.8 6 6 Max 66 30 PCI 33 Units Min. 16 30 29.7 11 11 Max 33 60 MHz ns ns ns ns 4 V/ns 2 1 1 3,4 Notes Absolute Minimum 7.375 3 3 1.5 4 1.5 4 1.5 4 1 PCI Spread Spectrum Requirements fmod fspread PCI clock modulation frequency PCI clock frequency spread 30 -1 33 0 30 -1 33 0 30 -1 33 0 30 -1 33 0 KHz % Notes: 1. Clock frequency may not change beyond spread-spectrum limits except while RSTIN# is asserted or PWRGD deasserted. 2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform. 3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 4. Clock jitter class 2, per PCI-X Electrical and Mechanical Rev 2.0a specification Table 26. Symbol TF2 TC2 TCH2 TCL2 TCS2 Tskew2 Tskew3 DDR Clock Timings DDR-II 400 Parameter Minimum Maximum 200 5.0 2.15 2.15 350 100 -285 285 -285 6.0/7.5 (1) DDR333 Units Minimum Maximum 167 2.7/3.37(1) 2.7/3.37(1) 350 100 285 MHz ns ns ns ps ps ps 2 Notes DDR SDRAM clock Frequency DDR SDRAM clock Cycle Time DDR SDRAM clock High Time DDR SDRAM clock LowTime DDR SDRAM clock Period Stability DDR SDRAM clock skew for any differential clock pair (M_CK[2:0] - M_CK[2:0]#) DDR SDRAM clock skew for any clock pair and any system memory strobe (M_CK DQS). Notes: 1. CL = 2.5/2.0. 2. This specification applies for writes only; that is, when the 80333 is driving the strobes as well as the clocks. Refer to the JEDEC specification for an explanation of strobe to clock timing for DDR reads. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 59 80333 Table 27. Symbol TF2 TC2 TCCJ PCI Express* Clock Timings Parameter Minimum -300ppm 10 Nominal 100 Maximum +300 ppm 10.2 200 45 300 300 55 600 600 20 0.51 0.85 0.35 0.76 Units MHz ns ps % ps ps % V V V 3 3 3,4 Notes 1 2 PCI Express* clock frequency PCI Express* clock cycle time Cycle to Cycle Jitter Clock duty cycle REFCLK rise time across 600mV REFCLK fall time across 600mV Rise-Fall matching Cross point at 1V Rising edge ringback Falling edge ringback Trise Tfall Notes: 1. Spread spectrum clocking is allowed with the following three requirements; a. All device timings must be met including jitter, skew, min./max. clock period. Output rise/fall timing MUST meet the existing non-spread spectrum specifications. b. All non-spread Host and PCI functionality must be maintained in the spread-spectrum mode (includes all power management functions). c. The minimum clock period cannot be violated. The preferred method is to adjust the spread technique to allow for modulation above the nominal frequency. This technique is often called “down-spreading”. 2. Measured at crossing point. 3. Measured from VOL = 0.2 V to VOH = 0.8 V. 4. Determined as a fraction of 2 × (Trise - Tfall)/(Trise + Tfall). May 2005 60 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 4.4.2 Table 28. DDR/DDR-II SDRAM Interface Signal Timings DDR SDRAM Signal Timings Symbol TVB1 TVA1 TVB3 TVA3 TVB4 TVA4 TVB5 TVA5 TVB6 TVA6 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Parameter DQ, CB and DM write output valid time before DQS. DQ, CB and DM write output valid time after DQS. Address and Command write output valid before M_CK rising edge. Address and Command write output valid after M_CK rising edge. DQ, CB and DM read input valid time before DQS rising or falling edges. DQ, CB and DM read input valid time after DQS rising or falling edges. CS[1:0]# control valid before M_CK rising edge. CS[1:0]# control valid after M_CK rising edge. DQS write preamble duration. DQS write postamble duration. Minimum 2.68 2.68 2.62 2.62 0.35 0.35 2.62 2.62 4.50 (nominal) 3.00 (nominal) Max. Units ns ns ns ns ns ns ns ns ns ns Notes (4) (4) (4,9) (4,9) (6) (6) (4) (4) (7) (7) See Figure 7, “Output Timing Measurement Waveforms” on page 69. See Figure 8, “Input Timing Measurement Waveforms” on page 70. Clock to output valid times are specified with a 0 pF loading. See Figure 11, “DDR SDRAM Write Timings” on page 71. See Figure 13 “DQS falling edge output access time to M_CK rising edge. See Figure 12, “DDR SDRAM Read Timings” on page 71. Data to strobe read setup and data from strobe read hold minimum requirements specified are determined with the DQS delay programmed for a 90 degree phase shift. See Figure 13, “Write PreAmble/PostAmble Durations” on page 72. See Figure 15, “AC Test Load for DDR SDRAM Signals” on page 73. Address/Command pin group; RAS#, CAS#, WE#, MA[12:0], BA[1:0]. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 61 80333 Table 29. DDR-II SDRAM Signal Timings Symbol TVB1 TVA1 TVB3 TVA3 TVB4 TVA4 TVB5 TVA5 TVB6 TVA6 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Parameter DQ, CB and DM write output valid time before DQS crossing. DQ, CB and DM write output valid time after DQS crossing. Address and Command write output valid before M_CK rising edge Address and Command write output valid after M_CK rising edge DQ, CB and DM read input valid time before DQS rising or falling edges DQ, CB and DM read input valid time after DQS rising or falling edges CS[1:0]# control valid before M_CK rising edge. CS[1:0]# control valid after M_CK rising edge. DQS write preamble duration. DQS write postamble duration. Min. 2.12 2.12 2.12 2.12 0.35 0.35 2.12 2.12 3.75 (nom.) 2.50 (nom.) Max. Units ns ns ns ns ns ns ns ns ns ns Notes 4 4 4 4,8 6 6 4 4 9 9 See Figure 7, “Output Timing Measurement Waveforms” on page 69. See Figure 8, “Input Timing Measurement Waveforms” on page 70. Clock to output valid times are specified with a 0 pF loading. See Figure 11, “DDR SDRAM Write Timings” on page 71. See Figure 13 “DQS falling edge output access time to M_CK rising edge. See Figure 12, “DDR SDRAM Read Timings” on page 71. Data to strobe read setup and data from strobe read hold minimum requirements specified are determined with the DQS delay programmed for a 90 degree phase shift. See Figure 15, “AC Test Load for DDR SDRAM Signals” on page 73. Address/Command pin group: RAS#, CAS#, WE#, MA[12:0], BA[1:0], ODT[1:0]. See Figure 13, “Write PreAmble/PostAmble Durations” on page 72. May 2005 62 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 4.4.3 Table 30. Peripheral Bus Interface Signal Timings Peripheral Bus Signal Timings Symbol TOV1 TOF TIS1 TIH1 Parameter Output Valid Delay from M_CK Output Float Delay from M_CK Input Setup to M_CK Input Hold from M_CK Min. 1 1 4.5 2 Max. 5 5 Units ns ns ns ns Notes (1, 3) (1, 3) (2) (2) TAH1 TAV1 TAH2 TAS1 TAO1 TAW1 TAH3 TAS2 TAC1 Notes: 1. 2. 3. 4. 5. 6. ALE High time ALE high to address Valid ALE low to address invalid Address valid to ALE low ALE low to POE# low ALE low to PWE# low PWE# high to Data Invalid Data valid to PWE# high ALE low to PCE[1:0]# low 15 0 15 15 0 15 15 60 15 ns ns ns ns ns ns ns ns ns See Figure 7, “Output Timing Measurement Waveforms” on page 69. See Figure 8, “Input Timing Measurement Waveforms” on page 70. See Figure 14, “AC Test Load for All Signals Except PCI and DDR SDRAM” on page 73. See Table 32, AC Measurement Conditions. All timing referenced to M_CK is for functional testing, for the cases where M_CK × N = IBCLK. PBI Clock is internal only; 66 MHz with 333 MHz internal bus. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 63 80333 Table 31. PCI Signal Timings Symbol Parameter Clock to Output Valid Delay for bused signals Clock to Output Valid Delay for point to point signals Clock to Output Float Delay Input Setup to clock for bused signals Input Setup to clock for point to point signals Input Hold time from clock Reset Active Time Reset Active to output float delay REQ64# to Reset setup time Reset to REQ64# hold time PCI-X initialization pattern to Reset setup time Reset to PCI-X initialization pattern hold time 10 0 10 50 1.2 1.2 0.5 1 40 10 0 10 50 PCI-X 133 PCI-X 100 Min. Max. TOV1 0.7 3.8 PCI-X 66 Min. 0.7 Max. 3.8 PCI 66 Min. 1 Max. 6 PCI 33 Min. 2 Max. 11 ns (1,2,3) Units Notes TOV2 TOF TIS1 TIS2 TIH1 TRST TRF TIS3 TIH2 TIS4 0.7 3.8 7 0.7 3.8 7 2 6 14 2 12 28 ns ns ns ns ns ms (1,2,3) (1,7) (3,4,8) (3,4) (4) 1.7 1.7 0.5 1 40 3 5 0 1 40 10 0 50 7 10, 12 0 1 40 10 0 50 ns clocks ns clocks (5,6) TIH3 0 50 0 50 ns Notes: 1. See the timing measurement conditions in; Figure 7, “Output Timing Measurement Waveforms” on page 69. 2. See Figure 16, “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 73, Figure 17, “PCI/PCI-X TOV(max) Falling Edge AC Test Load” on page 74, and Figure 18, “PCI/PCI-X TOV(min) AC Test Load” on page 74. 3. Setup time for point-to-point signals applies to REQ# and GNT# only. All other signals are bused. 4. See the timing measurement conditions in Figure 8, “Input Timing Measurement Waveforms” on page 70. 5. RST# is asserted and deasserted asynchronously with respect to CLK. 6. All output drivers must be floated when RST# is active. 7. For purposes of Active/Float timing measurements, the HI-Z or ‘off’ state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. May 2005 64 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 4.4.4 Table 32. I2C/SMBus Interface Signal Timings I2C/SMBus Signal Timings Std. Mode Symbol FSCL TBUF THDSTA TLOW THIGH TSUSTA THDDAT TSUDAT TSR TSF TSUSTO Notes: 1. 2. 3. 4. 5. Parameter Min. SCL Clock Frequency Bus Free Time Between STOP and START Condition Hold Time (repeated) START Condition SCL Clock Low Time SCL Clock High Time Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Setup Time for STOP Condition 4 0 4.7 4 4.7 4 4.7 0 250 1000 300 3.45 Max 100 Min. 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 20 + 0.1Cb 0.6 300 300 0.9 Max 400 KHz µs µs µs µs µs µs ns ns ns µs (1) (1, 3) (1, 2) (1, 2) (1) (1) (1) (1, 4) (1, 4) (1) Fast Mode Units Notes See Figure 9, “I2C/SMBus Interface Signal Timings” on page 70. Not tested. After this period, the first clock pulse is generated. Cb = the total capacitance of one bus line, in pF. Std. Mode I2C signal timings apply for SMBus timing. 4.4.5 Table 33. UART Interface Signal Timings UART Signal Timings Std. Mode Symbol TXD1 TRXS1 TRXH1 TCTS1 TCTH1 TRTS1 TRTH1 Parameter Min. Ux_TXD output delay from M_CK rising edge Ux_RXD data setup time (to M_CK rising edge). Ux_RXD data hold time (to M_CK rising edge). Ux_CTS setup time (to M_CK rising edge). Ux_CTS hold time (to M_CK rising edge). Ux_RTS setup time (to M_CK rising edge). Ux_RTS hold time (to M_CK rising edge). 50 50 60 60 60 60 Max 60 ns ns ns ns ns ns ns 1 2 2 Units Notes Notes: 1. See Figure 10, “UART Transmitter Receiver Timing” on page 70. 2. All timings referenced to M_CK for functional testing, is for cases where M_CK × N = IBCLK. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 65 80333 4.4.6 Table 34. PCI Express* Differential Transmitter (Tx) Output Specifications PCI Express* Tx Output Specifications Symbol UI VDIFFp-p Trise, Tfall VTX-CM-AC VTX-CM-DC delta Parameter Unit Interval Differential output voltage Driver Rise/Fall Time AC Common Mode Common Mode Active to Sleep mode delta Differential Return Loss Common Mode Return Loss DC Differential Output Impedance D+/D- impedance matching Lane to Lane Skew at Tx Total Output Jitter. Minimum Transmitter eye opening. Short Circuit Current Sleep mode Voltage Output Min. Nom. 400 Max. Units ps Notes 1 2 3 4 .800 0.2 1.200 0.4 20 V UI mV mV dB dB -50 15 6 90 -5 100 +50 RL-DiffTX RL-CMTX ZTX-OUT-DC ZTX-Match-DC LSKEW-TX JTOTAL TDeye ITX-SHORT VTX-IDLE 5 5 6 7 8 9 10 11 12 110 +5 500 0.35 Ω % ps UI UI 0.65 -100 0 0 100 20 mA mV Notes: 1. ±300 ppm. UI does not account for SSC dictated variations. No test load is necessarily associated with this value. This UI spec is a ‘before transmission’ specification and represents the nominal time of each bit transmission or width. 2. Peak-Peak differential voltage. VDIFFp-p = 2 × VDMAx. Specified at the package pins into a 100 Ω test load as shown in Figure 19, “Transmitter Test Load (100 W differential load)” on page 74. Max level set by maximum single ended voltage after a reflection from an open. This value is for the first bit after a transition on the data lines. Subsequent bits of the same polarity shall have an amplitude of 6 dB (±0.5 dB) less as measured differentially peak to peak than the specified value. 3. 20–80% at Transmitter. Slower rise/fall times are better. 4. Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg). 5. 50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ω for common mode (i.e., as measured by a Vector Network Analyzer with 100 Ω differential probes). Note this is based on a nominal PCI Express* interconnect differential characteristic impedance of 100 Ω. Applicable during active (L0) and Align states only. 6. DC Differential Mode Impedance 100 Ω ±10% tolerance. All devices shall employ on-chip adaptive impedance matching circuits to ensure the best possible termination/Zout for its Transmitters (as well as Receivers). 7. DC impedance matching between two lanes of a port. 8. Between any two lanes within a single Transmitter. 9. Clock source PPM mismatch is in addition to this value. Measured over 250 UI. 10. See Figure 20, “Transmitter Eye Diagram” on page 75. 11. Between any voltage from max supply to gnd with power on or off. 12. Squelch condition. Both signals brought to VCM-DC-|VD+ - VD-|. May 2005 66 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 4.4.7 Table 35. PCI Express* Differential Receiver (Rx) Input Specifications PCI Express* Rx Input Specifications Symbol VDIFFp-p JTOTAL VCM-AC TReye RL-DiffRX RL-CMTX ZRX-OUT-DC ZRX-Match-DC VRX-SQUELCH CinRX LSKEW-RX Parameter Differential input voltage Total Output Jitter. AC Common Mode Receiver eye opening. Differential Return Loss Common Mode Return Loss DC Differential Output Impedance D+/D- impedance matching Squelch detect threshold AC coupled Lane to Lane Skew at Rx 0.35 15 6 90 -5 75 400 20 100 110 +5 175 Min. 0.175 Nom. Max. 1.200 0.65 100 Units V UI mV UI dB dB Ω % mV pF UI Notes 1 2 3 4 5 5 6 7 8 9 10 Notes: 1. Peak-Peak differential voltage. VDIFFp-p = 2 × VRMAx. Measured at the package pins of the receiver. See Figure 20, “Transmitter Eye Diagram” on page 75. 2. Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver device. A receiver must therefore tolerate any additional jitter generated by the package to the die. 3. Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg). 4. See Figure 21, “Receiver Eye Opening (Differential)” on page 75. 5. 50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ωs for common mode (i.e., as measured by a Vector Network Analyzer with 100 Ω differential probes). Note this is based on a nominal PCI Express* interconnect differential characteristic impedance of 100 Ω. Applicable during active (L0) and Align states only. 6. DC Differential Mode Impedance 100 Ω ±10% tolerance. 7. DC impedance matching between two lanes of a port. 8. Peak to Peak value. Measured at the pin of the receiver. Differential signal below this level will indicate a squelch condition. 9. All receivers shall be AC coupled to the media. 10. Lane skew at the Receiver that must be tolerated. Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 67 80333 4.4.8 Table 36. Boundary Scan Test Signal Timings Boundary Scan Test Signal Timings Symbol TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSOV1 TOF1 Notes: 1. 2. 3. 4. 5. Parameter TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Input Setup to TCK — TDI, TMS Input Hold from TCK — TDI, TMS TDO Valid Delay TDO Float Delay 3 5 5 5 15 15 Min. 0 15 15 5 5 Max 0.5TF Units MHz ns ns ns ns ns ns ns ns Measured at 1.5 V (1). Measured at 1.5 V (1). 0.8 V to 2.0 V (1) 2.0 V to 0.8 V (1) (4) (4) Relative to falling edge of TCK (2, 3). Relative to falling edge of TCK (2, 5). Notes Not tested. Outputs precharged to VCC5. See Figure 7, “Output Timing Measurement Waveforms” on page 69. See Figure 8, “Input Timing Measurement Waveforms” on page 70. A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See Figure 7, “Output Timing Measurement Waveforms” on page 69. May 2005 68 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 4.5 Figure 6. AC Timing Waveforms Clock Timing Measurement Waveforms TCR Vih(min) Vtest Vil(max) Vtcl TCH TCL TCF Vtch TC Figure 7. Output Timing Measurement Waveforms Vth CLK Vtest Vtl TOV Vtfall OUTPUT DELAY FALL TOV OUTPUT DELAY RISE Vtrise TOF OUTPUT FLOAT Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 69 80333 Figure 8. Input Timing Measurement Waveforms Vth CLK Vtest Vtl TIH TIS Vth INPUT Vtest Valid Vtest Vmax Vtl Figure 9. I2C/SMBus Interface Signal Timings SDA TBUF TLOW TSR TSF THDSTA TSP SCL THDSTA THDDAT Stop Start THIGH TSUSTO TSUDAT TSUSTA Repeated Start Stop Figure 10. UART Transmitter Receiver Timing M_CK TXD1 Ux_TXD TRXS1 TRXH1 Ux_RXD May 2005 70 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Figure 11. DDR SDRAM Write Timings ADDR/CTRL TVB3 TVA3 CS[1:0]# TVB5 TVA5 M_CK DQS DQS# TVB1 TVA1 DQ Figure 12. DDR SDRAM Read Timings DQS TVB4 TVA4 DQ Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 71 80333 Figure 13. Write PreAmble/PostAmble Durations DQS TVB6 DQS TVA6 May 2005 72 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 4.6 Table 37. AC Test Conditions AC Measurement Conditions Symbol Vth Vtl Vtest Vtrise Vtfall Vmax Slew Rate 1 PCI-X 0.6 VCC33 0.25 VCC33 0.4 VCC33 0.285 VCC33 0.615 VCC33 0.4 VCC33 1.5 PCI 0.6 VCC33 0.2 VCC33 0.4 VCC33 0.285 VCC33 0.615 VCC33 0.4 VCC33 1.5 DDR / DDR-II 2.0 / 1.15 0.5 / 0.2 1.25 / 0.90 1.25 / 0.90 1.25 / 0.90 1.5 / 0.97 1.0 DDR-II 1.15 0.2 0.90 0.90 0.90 0.97 1.0 PBI 2.0 0.8 1.5 1.5 1.5 1.2 1.0 Units V V V V V V V/nS Notes: 1. Input signal slew rate is measured between Vil and Vih. Figure 14. AC Test Load for All Signals Except PCI and DDR SDRAM Test Point Output 50pF Figure 15. AC Test Load for DDR SDRAM Signals 1.25V 25Ω Output 25Ω 30pF Test Point Figure 16. PCI/PCI-X TOV(max) Rising Edge AC Test Load Test Point Output 25Ω 10pF Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 73 80333 Figure 17. PCI/PCI-X TOV(max) Falling Edge AC Test Load VCC33 25Ω Output 10pF Test Point Figure 18. PCI/PCI-X TOV(min) AC Test Load VCC33 1KΩ Output 1KΩ 10pF Test Point Figure 19. Transmitter Test Load (100 Ω differential load) D+ D- 50 Ohm 50 Ohm + Vcm-dc - May 2005 74 Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 Datasheet 80333 Figure 20. Transmitter Eye Diagram UI VDmax TDeye VDmin Note: Transmitter Vdiffp-p = 2 × VDmax Figure 21. Receiver Eye Opening (Differential) UI VRmax TReye VRmin Note: Transmitter Vdiffp-p = 2 × VRmax Datasheet Intel® 80333 I/O Processor Datasheet Order Number: 305433, Revision: 002 May 2005 75