319973-003

Intel® I/O Controller Hub 10 (ICH10) Family Datasheet October 2008 Document Number: 319973-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines and Disclaimers UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The Intel® I/O Controller Hub 10 (ICH10) Family chipset component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel® Active Management Technology requires the computer system to have an Intel® AMT-enabled chipset, network hardware and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality. It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/technology/platform-technology/intel-amt/ Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, see http://www.intel.com/technology/security Home networking capability and many Intel® Viiv™ technology-based usage models will require additional hardware devices, software or services. Functionality of Intel® Viiv™ technology verified devices will vary; check product details for desired features. System and component performance and functionality will vary depending on your specific hardware and software configurations. See www.intel.com/go/viiv_info for more information. Intel® High Definition Audio requires a system with an appropriate Intel chipset and a motherboard with an appropriate codec and the necessary drivers installed. System sound quality will vary depending on actual implementation, controller, codec, drivers and speakers. For more information about Intel® HD audio, refer to http://www.intel.com/ Intel, Intel logo, Intel SpeedStep, Intel Viiv, and Intel vPro are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2008, Intel Corporation 2 Datasheet Contents 1 Introduction ............................................................................................................ 33 1.1 About This Manual ............................................................................................. 33 1.2 Overview ......................................................................................................... 37 1.2.1 Capability Overview ................................................................................ 39 1.3 Intel® ICH10 Family High-Level Component Differences ......................................... 44 Signal Description ................................................................................................... 45 2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 47 2.2 PCI Express* Interface....................................................................................... 48 2.3 LAN Connect Interface ....................................................................................... 48 2.4 Gigabit LAN Connect Interface ............................................................................ 49 2.5 Firmware Hub Interface...................................................................................... 50 2.6 PCI Interface .................................................................................................... 50 2.7 Serial ATA Interface........................................................................................... 52 2.8 LPC Interface.................................................................................................... 55 2.9 Interrupt Interface ............................................................................................ 55 2.10 USB Interface ................................................................................................... 56 2.11 Power Management Interface.............................................................................. 58 2.12 Processor Interface............................................................................................ 61 2.13 SMBus Interface................................................................................................ 62 2.14 System Management Interface............................................................................ 63 2.15 Real Time Clock Interface ................................................................................... 64 2.16 Other Clocks..................................................................................................... 65 2.17 Miscellaneous Signals ........................................................................................ 65 2.18 Intel® High Definition Audio Link ......................................................................... 66 2.19 Serial Peripheral Interface (SPI) .......................................................................... 67 2.20 Controller Link .................................................................................................. 68 2.21 Intel® Quiet System Technology ......................................................................... 68 2.22 JTAG Signals (Intel® ICH10 Corporate Family Only) ............................................... 69 2.23 General Purpose I/O Signals ............................................................................... 70 2.24 Power and Ground Signals .................................................................................. 73 2.25 Pin Straps ........................................................................................................ 75 2.25.1 Functional Straps ................................................................................... 75 2.25.2 External RTC Circuitry ............................................................................. 79 Intel® ICH10 Pin States ........................................................................................... 81 3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 81 3.2 Output and I/O Signals Planes and States............................................................. 83 3.3 Power Planes for Input Signals ............................................................................ 88 Intel® ICH10 and System Clock Domains ................................................................. 91 Functional Description ............................................................................................. 93 5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................... 93 5.1.1 PCI Bus Interface ................................................................................... 93 5.1.2 PCI Bridge As an Initiator ........................................................................ 93 5.1.3 Parity Error Detection and Generation ....................................................... 95 5.1.4 PCIRST# ............................................................................................... 96 5.1.5 Peer Cycles ........................................................................................... 96 5.1.6 PCI-to-PCI Bridge Model.......................................................................... 96 5.1.7 IDSEL to Device Number Mapping ............................................................ 97 5.1.8 Standard PCI Bus Configuration Mechanism ............................................... 97 5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5).................................................. 97 5.2.1 Interrupt Generation............................................................................... 97 5.2.2 Power Management ................................................................................ 98 5.2.3 SERR# Generation ................................................................................. 99 5.2.4 Hot-Plug ............................................................................................. 100 5.3 Gigabit Ethernet Controller (B0:D25:F0)............................................................. 101 5.3.1 Gigabit Ethernet PCI Bus Interface.......................................................... 102 5.3.2 Error Events and Error Reporting ............................................................ 103 5.3.3 Ethernet Interface ................................................................................ 103 5.3.4 PCI Power Management ........................................................................ 104 5.3.5 Configurable LEDs ................................................................................ 105 2 3 4 5 Datasheet 3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.3.6 Function Level Reset Support (FLR) ......................................................... 106 LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 107 5.4.1 LPC Interface ....................................................................................... 107 DMA Operation (D31:F0) .................................................................................. 112 5.5.1 Channel Priority.................................................................................... 113 5.5.2 Address Compatibility Mode ................................................................... 113 5.5.3 Summary of DMA Transfer Sizes ............................................................. 114 5.5.4 Autoinitialize ........................................................................................ 114 5.5.5 Software Commands ............................................................................. 115 LPC DMA ........................................................................................................ 115 5.6.1 Asserting DMA Requests ........................................................................ 115 5.6.2 Abandoning DMA Requests..................................................................... 116 5.6.3 General Flow of DMA Transfers ............................................................... 116 5.6.4 Terminal Count..................................................................................... 116 5.6.5 Verify Mode ......................................................................................... 117 5.6.6 DMA Request Deassertion ...................................................................... 117 5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 118 8254 Timers (D31:F0) ...................................................................................... 118 5.7.1 Timer Programming .............................................................................. 119 5.7.2 Reading from the Interval Timer ............................................................. 120 8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 121 5.8.1 Interrupt Handling ................................................................................ 122 5.8.2 Initialization Command Words (ICWx) ..................................................... 123 5.8.3 Operation Command Words (OCW) ......................................................... 124 5.8.4 Modes of Operation ............................................................................... 124 5.8.5 Masking Interrupts................................................................................ 127 5.8.6 Steering PCI Interrupts.......................................................................... 127 Advanced Programmable Interrupt Controller (APIC) (D31:F0)............................... 128 5.9.1 Interrupt Handling ................................................................................ 128 5.9.2 Interrupt Mapping................................................................................. 128 5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 129 5.9.4 Front Side Bus Interrupt Delivery ............................................................ 129 5.9.5 IOxAPIC Address Remapping .................................................................. 131 5.9.6 External Interrupt Controller Support ...................................................... 131 Serial Interrupt (D31:F0) .................................................................................. 132 5.10.1 Start Frame ......................................................................................... 132 5.10.2 Data Frames ........................................................................................ 133 5.10.3 Stop Frame.......................................................................................... 133 5.10.4 Specific Interrupts Not Supported via SERIRQ........................................... 133 5.10.5 Data Frame Format............................................................................... 134 Real Time Clock (D31:F0) ................................................................................. 135 5.11.1 Update Cycles ...................................................................................... 135 5.11.2 Interrupts ............................................................................................ 136 5.11.3 Lockable RAM Ranges............................................................................ 136 5.11.4 Century Rollover................................................................................... 136 5.11.5 Clearing Battery-Backed RTC RAM........................................................... 136 Processor Interface (D31:F0) ............................................................................ 138 5.12.1 Processor Interface Signals .................................................................... 138 5.12.2 Dual-Processor Issues ........................................................................... 141 Power Management (D31:F0) ............................................................................ 142 5.13.1 Features .............................................................................................. 142 5.13.2 Intel® ICH10 and System Power States ................................................... 142 5.13.3 System Power Planes ............................................................................ 145 5.13.4 SMI#/SCI Generation ............................................................................ 145 5.13.5 Dynamic Processor Clock Control ............................................................ 148 5.13.6 Sleep States ........................................................................................ 151 5.13.7 Thermal Management............................................................................ 154 5.13.8 Event Input Signals and Their Usage ....................................................... 155 5.13.9 ALT Access Mode .................................................................................. 158 5.13.10System Power Supplies, Planes, and Signals............................................. 162 5.13.11Clock Generators .................................................................................. 164 5.13.12Legacy Power Management Theory of Operation ....................................... 165 5.13.13Reset Behavior ..................................................................................... 165 System Management (D31:F0) .......................................................................... 167 5.14.1 Theory of Operation .............................................................................. 167 5.14.2 TCO Modes .......................................................................................... 169 General Purpose I/O (D31:F0) ........................................................................... 173 4 Datasheet 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.15.1 Power Wells......................................................................................... 173 5.15.2 SMI# and SCI Routing .......................................................................... 173 5.15.3 Triggering ........................................................................................... 173 5.15.4 GPIO Registers Lockdown ...................................................................... 173 5.15.5 Serial POST Codes Over GPIO ................................................................ 174 5.15.6 Intel Management Engine GPIOs ............................................................ 176 SATA Host Controller (D31:F2, F5) .................................................................... 176 5.16.1 SATA Feature Support........................................................................... 177 5.16.2 Theory of Operation.............................................................................. 178 5.16.3 SATA Swap Bay Support ....................................................................... 178 5.16.4 Hot Plug Operation ............................................................................... 178 5.16.5 Function Level Reset Support (FLR) ........................................................ 179 5.16.6 Intel® Matrix Storage Technology Configuration ....................................... 180 5.16.7 Power Management Operation................................................................ 181 5.16.8 SATA Device Presence........................................................................... 183 5.16.9 SATA LED............................................................................................ 184 5.16.10AHCI Operation.................................................................................... 184 5.16.11Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................ 184 5.16.12SGPIO Signals ..................................................................................... 185 5.16.13External SATA...................................................................................... 189 High Precision Event Timers.............................................................................. 189 5.17.1 Timer Accuracy .................................................................................... 189 5.17.2 Interrupt Mapping ................................................................................ 190 5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 190 5.17.4 Enabling the Timers.............................................................................. 191 5.17.5 Interrupt Levels ................................................................................... 191 5.17.6 Handling Interrupts .............................................................................. 192 5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 192 USB UHCI Host Controllers (D29:F0, F1, F2, F3 and D26:F0, F1 and F2) ................. 192 5.18.1 Data Structures in Main Memory............................................................. 193 5.18.2 Data Transfers to/from Main Memory ...................................................... 193 5.18.3 Data Encoding and Bit Stuffing ............................................................... 193 5.18.4 Bus Protocol ........................................................................................ 193 5.18.5 Packet Formats .................................................................................... 194 5.18.6 USB Interrupts..................................................................................... 194 5.18.7 USB Power Management ....................................................................... 197 5.18.8 USB Legacy Keyboard Operation ............................................................ 197 5.18.9 Function Level Reset Support (FLR) ........................................................ 200 USB EHCI Host Controllers (D29:F7 and D26:F7)................................................. 201 5.19.1 EHC Initialization.................................................................................. 201 5.19.2 Data Structures in Main Memory............................................................. 202 5.19.3 USB 2.0 Enhanced Host Controller DMA................................................... 202 5.19.4 Data Encoding and Bit Stuffing ............................................................... 202 5.19.5 Packet Formats .................................................................................... 203 5.19.6 USB 2.0 Interrupts and Error Conditions .................................................. 203 5.19.7 USB 2.0 Power Management .................................................................. 204 5.19.8 Interaction with UHCI Host Controllers .................................................... 205 5.19.9 USB 2.0 Legacy Keyboard Operation ....................................................... 208 5.19.10USB 2.0 Based Debug Port .................................................................... 209 5.19.11USB Pre-Fetch Based Pause ................................................................... 213 5.19.12Function Level Reset Support (FLR) ........................................................ 214 SMBus Controller (D31:F3) ............................................................................... 214 5.20.1 Host Controller..................................................................................... 215 5.20.2 Bus Arbitration..................................................................................... 219 5.20.3 Bus Timing .......................................................................................... 220 5.20.4 Interrupts / SMI#................................................................................. 221 5.20.5 SMBALERT# ........................................................................................ 222 5.20.6 SMBus CRC Generation and Checking...................................................... 222 5.20.7 SMBus Slave Interface .......................................................................... 222 Intel® High Definition Audio Overview ................................................................ 228 Intel® Active Management Technology (Intel® AMT) (Corporate Only).................... 228 5.22.1 Intel® AMT Features ............................................................................. 229 5.22.2 Intel® AMT Requirements ...................................................................... 229 Serial Peripheral Interface (SPI) ........................................................................ 229 5.23.1 SPI Supported Feature Overview ............................................................ 230 5.23.2 Flash Descriptor ................................................................................... 232 5.23.3 Flash Access ........................................................................................ 234 Datasheet 5 5.24 5.25 5.26 5.27 6 7 8 5.23.4 Serial Flash Device Compatibility Requirements ........................................ 235 5.23.5 Multiple Page Write Usage Model............................................................. 237 5.23.6 Flash Device Configurations ................................................................... 238 5.23.7 SPI Flash Device Recommended Pinout.................................................... 238 5.23.8 Serial Flash Device Package ................................................................... 239 Intel® Quiet System Technology (Intel® QST) ..................................................... 240 5.24.1 PWM Outputs ....................................................................................... 240 5.24.2 TACH Inputs ........................................................................................ 240 Thermal Sensors.............................................................................................. 240 Feature Capability Mechanism ........................................................................... 241 Integrated Trusted Platform Module (Corporate Only) ........................................... 241 5.27.1 Integrated TPM Hardware Requirements .................................................. 241 5.27.2 Enabling integrated TPM ........................................................................ 242 Ballout Definition ................................................................................................... 243 6.1 Intel® ICH10 Ballout ....................................................................................... 243 Package Information ............................................................................................. 253 7.1 Intel® ICH10 Package ...................................................................................... 253 Electrical Characteristics ........................................................................................ 255 8.1 Thermal Specifications...................................................................................... 255 8.2 Absolute Maximum Ratings ............................................................................... 255 8.3 DC Characteristics ........................................................................................... 255 8.4 AC Characteristics............................................................................................ 268 8.5 Timing Diagrams ............................................................................................. 280 Register and Memory Mapping ............................................................................... 293 9.1 PCI Devices and Functions ................................................................................ 294 9.2 PCI Configuration Map ...................................................................................... 295 9.3 I/O Map.......................................................................................................... 295 9.3.1 Fixed I/O Address Ranges ...................................................................... 295 9.3.2 Variable I/O Decode Ranges ................................................................... 298 9.4 Memory Map ................................................................................................... 299 9.4.1 Boot-Block Update Scheme .................................................................... 300 Chipset Configuration Registers ............................................................................. 303 10.1 Chipset Configuration Registers (Memory Space) ................................................. 303 10.1.1 VCH—Virtual Channel Capability Header Register ...................................... 306 10.1.2 VCAP1—Virtual Channel Capability #1 Register ......................................... 306 10.1.3 VCAP2—Virtual Channel Capability #2 Register ......................................... 307 10.1.4 PVC—Port Virtual Channel Control Register............................................... 307 10.1.5 PVS—Port Virtual Channel Status Register................................................ 307 10.1.6 V0CAP—Virtual Channel 0 Resource Capability Register.............................. 308 10.1.7 V0CTL—Virtual Channel 0 Resource Control Register ................................. 308 10.1.8 V0STS—Virtual Channel 0 Resource Status Register .................................. 309 10.1.9 V1CAP—Virtual Channel 1 Resource Capability Register.............................. 309 10.1.10V1CTL—Virtual Channel 1 Resource Control Register ................................. 310 10.1.11V1STS—Virtual Channel 1 Resource Status Register .................................. 310 10.1.12PAT—Port Arbitration Table (Consumer Only) ........................................... 311 10.1.13CIR1—Chipset Initialization Register 1 ..................................................... 311 10.1.14REC—Root Error Command Register ........................................................ 311 10.1.15RCTCL—Root Complex Topology Capabilities List Register .......................... 312 10.1.16ESD—Element Self Description Register ................................................... 312 10.1.17ULD—Upstream Link Descriptor Register .................................................. 312 10.1.18ULBA—Upstream Link Base Address Register ............................................ 313 10.1.19RP1D—Root Port 1 Descriptor Register..................................................... 313 10.1.20RP1BA—Root Port 1 Base Address Register............................................... 313 10.1.21RP2D—Root Port 2 Descriptor Register..................................................... 314 10.1.22RP2BA—Root Port 2 Base Address Register............................................... 314 10.1.23RP3D—Root Port 3 Descriptor Register..................................................... 314 10.1.24RP3BA—Root Port 3 Base Address Register............................................... 315 10.1.25RP4D—Root Port 4 Descriptor Register..................................................... 315 10.1.26RP4BA—Root Port 4 Base Address Register............................................... 315 10.1.27HDD—Intel® High Definition Audio Descriptor Register............................... 316 10.1.28HDBA—Intel® High Definition Audio Base Address Register......................... 316 10.1.29RP5D—Root Port 5 Descriptor Register..................................................... 316 10.1.30RP5BA—Root Port 5 Base Address Register............................................... 317 9 10 6 Datasheet 10.1.31RP6D—Root Port 6 Descriptor Register .................................................... 317 10.1.32RP6BA—Root Port 6 Base Address Register .............................................. 317 10.1.33ILCL—Internal Link Capabilities List Register ............................................ 318 10.1.34LCAP—Link Capabilities Register ............................................................. 318 10.1.35LCTL—Link Control Register ................................................................... 318 10.1.36LSTS—Link Status Register .................................................................... 319 10.1.37CIR2 — Chipset Initialization Register 2................................................... 319 10.1.38CIR3 — Chipset Initialization Register 3................................................... 319 10.1.39BCR — Backbone Configuration Register.................................................. 319 10.1.40RPC—Root Port Configuration Register .................................................... 320 10.1.41DMIC—DMI Control Register .................................................................. 321 10.1.42RPFN—Root Port Function Number and Hide for PCI Express* Root Ports ..... 321 10.1.43FLRSTAT—FLR Pending Status Register ................................................... 323 10.1.44CIR13—Chipset Initialization Register 13 ................................................. 324 10.1.45CIR5—Chipset Initialization Register 5..................................................... 324 10.1.46TRSR—Trap Status Register ................................................................... 324 10.1.47TRCR—Trapped Cycle Register ............................................................... 325 10.1.48TWDR—Trapped Write Data Register....................................................... 325 10.1.49IOTRn — I/O Trap Register (0-3)............................................................ 326 10.1.50DMC—DMI Miscellaneous Control Register ............................................... 327 10.1.51CIR6—Chipset Initialization Register 6..................................................... 327 10.1.52CIR7—Chipset Initialization Register 7..................................................... 327 10.1.53TCTL—TCO Configuration Register .......................................................... 328 10.1.54D31IP—Device 31 Interrupt Pin Register.................................................. 329 10.1.55D30IP—Device 30 Interrupt Pin Register.................................................. 330 10.1.56D29IP—Device 29 Interrupt Pin Register.................................................. 330 10.1.57D28IP—Device 28 Interrupt Pin Register.................................................. 331 10.1.58D27IP—Device 27 Interrupt Pin Register.................................................. 332 10.1.59D26IP—Device 26 Interrupt Pin Register.................................................. 333 10.1.60D25IP—Device 25 Interrupt Pin Register.................................................. 334 10.1.61D31IR—Device 31 Interrupt Route Register ............................................. 334 10.1.62D30IR—Device 30 Interrupt Route Register ............................................. 335 10.1.63D29IR—Device 29 Interrupt Route Register ............................................. 336 10.1.64D28IR—Device 28 Interrupt Route Register ............................................. 337 10.1.65D27IR—Device 27 Interrupt Route Register ............................................. 338 10.1.66D26IR—Device 26 Interrupt Route Register ............................................. 339 10.1.67D25IR—Device 25 Interrupt Route Register ............................................. 340 10.1.68OIC—Other Interrupt Control Register (Corporate Only) ............................ 341 10.1.69OIC—Other Interrupt Control Register (Consumer Only) ............................ 341 10.1.70SBEMC3—Scheduled Break Event C3 Exit Latency..................................... 342 10.1.71SBEMC4—Scheduled Break Event C4 Exit Latency..................................... 342 10.1.72PRSTS—Power and Reset Status (Corporate Only) .................................... 343 10.1.73RC—RTC Configuration Register ............................................................. 344 10.1.74HPTC—High Precision Timer Configuration Register ................................... 344 10.1.75GCS—General Control and Status Register............................................... 345 10.1.76BUC—Backed Up Control Register ........................................................... 347 10.1.77FD—Function Disable Register ................................................................ 348 10.1.78CG—Clock Gating ................................................................................. 350 10.1.79FDSW—Function Disable SUS Well .......................................................... 352 10.1.80CIR8—Chipset Initialization Register 8..................................................... 352 10.1.81CIR9—Chipset Initialization Register 9..................................................... 352 10.1.82PPO—Port Power Off ............................................................................. 352 10.1.83CIR10—Chipset Initialization Register 10 ................................................. 353 10.1.84MAP—Remap Control Register ................................................................ 353 11 PCI-to-PCI Bridge Registers (D30:F0) ................................................................... 355 11.1 PCI Configuration Registers (D30:F0)................................................................. 355 11.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0) ............................ 356 11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0)............................. 356 11.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0)............................................. 357 11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0) ......................................... 357 11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0) ........................... 359 11.1.6 CC—Class Code Register (PCI-PCI—D30:F0) ............................................ 359 11.1.7 PMLT—Primary Master Latency Timer Register (PCI-PCI—D30:F0) ............................................................................... 360 11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) ................................. 360 11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ...................................... 360 Datasheet 7 11.1.10SMLT—Secondary Master Latency Timer Register (PCI-PCI—D30:F0)................................................................................ 361 11.1.11IOBASE_LIMIT—I/O Base and Limit Register (PCI-PCI—D30:F0)................................................................................ 361 11.1.12SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................ 362 11.1.13MEMBASE_LIMIT—Memory Base and Limit Register (PCI-PCI—D30:F0)................................................................................ 363 11.1.14PREF_MEM_BASE_LIMIT—Prefetchable Memory Base and Limit Register (PCI-PCI—D30:F0) ..................................................... 363 11.1.15PMBU32—Prefetchable Memory Base Upper 32 Bits Register (PCI-PCI—D30:F0) ................................................................... 364 11.1.16PMLU32—Prefetchable Memory Limit Upper 32 Bits Register (PCI-PCI—D30:F0) ................................................................... 364 11.1.17CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) .......................... 364 11.1.18INTR—Interrupt Information Register (PCI-PCI—D30:F0) ........................... 364 11.1.19BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ................................... 365 11.1.20SPDH—Secondary PCI Device Hiding Register (PCI-PCI—D30:F0)................................................................................ 366 11.1.21DTC—Delayed Transaction Control Register (PCI-PCI—D30:F0)................................................................................ 367 11.1.22BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0)................................................................................ 368 11.1.23BPC—Bridge Policy Configuration Register (PCI-PCI—D30:F0)................................................................................ 369 11.1.24SVCAP—Subsystem Vendor Capability Register (PCI-PCI—D30:F0)................................................................................ 370 11.1.25SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) ......................... 370 12 Gigabit LAN Configuration Registers ...................................................................... 371 12.1 Gigabit LAN Configuration Registers (Gigabit LAN — D25:F0)................................. 371 12.1.1 VID—Vendor Identification Register (Gigabit LAN—D25:F0) .......................................................................... 372 12.1.2 DID—Device Identification Register (Gigabit LAN—D25:F0) .......................................................................... 372 12.1.3 PCICMD—PCI Command Register (Gigabit LAN—D25:F0) .......................................................................... 373 12.1.4 PCISTS—PCI Status Register (Gigabit LAN—D25:F0) .......................................................................... 374 12.1.5 RID—Revision Identification Register (Gigabit LAN—D25:F0) .......................................................................... 375 12.1.6 CC—Class Code Register (Gigabit LAN—D25:F0) .......................................................................... 375 12.1.7 CLS—Cache Line Size Register (Gigabit LAN—D25:F0) .......................................................................... 375 12.1.8 PLT—Primary Latency Timer Register (Gigabit LAN—D25:F0) .......................................................................... 375 12.1.9 HT—Header Type Register (Gigabit LAN—D25:F0) .......................................................................... 375 12.1.10MBARA—Memory Base Address Register A (Gigabit LAN—D25:F0) .......................................................................... 376 12.1.11MBARB—Memory Base Address Register B (Gigabit LAN—D25:F0) .......................................................................... 376 12.1.12MBARC—Memory Base Address Register C (Gigabit LAN—D25:F0) .......................................................................... 377 12.1.13SVID—Subsystem Vendor ID Register (Gigabit LAN—D25:F0) .......................................................................... 377 12.1.14SID—Subsystem ID Register (Gigabit LAN—D25:F0) .......................................................................... 377 12.1.15ERBA—Expansion ROM Base Address Register (Gigabit LAN—D25:F0) .......................................................................... 377 12.1.16CAPP—Capabilities List Pointer Register (Gigabit LAN—D25:F0) .......................................................................... 378 12.1.17INTR—Interrupt Information Register (Gigabit LAN—D25:F0) .......................................................................... 378 12.1.18MLMG—Maximum Latency/Minimum Grant Register (Gigabit LAN—D25:F0) .......................................................................... 378 8 Datasheet 12.2 12.1.19CLIST 1—Capabilities List Register 1 (Gigabit LAN—D25:F0).......................................................................... 378 12.1.20PMC—PCI Power Management Capabilities Register (Gigabit LAN—D25:F0).......................................................................... 379 12.1.21PMCS—PCI Power Management Control and Status Register (Gigabit LAN—D25:F0) ............................................................. 380 12.1.22DR—Data Register (Gigabit LAN—D25:F0).......................................................................... 381 12.1.23CLIST 2—Capabilities List Register 2 (Gigabit LAN—D25:F0).......................................................................... 381 12.1.24MCTL—Message Control Register (Gigabit LAN—D25:F0).......................................................................... 381 12.1.25MADDL—Message Address Low Register (Gigabit LAN—D25:F0).......................................................................... 382 12.1.26MADDH—Message Address High Register (Gigabit LAN—D25:F0).......................................................................... 382 12.1.27MDAT—Message Data Register (Gigabit LAN—D25:F0).......................................................................... 382 12.1.28FLRCAP—Function Level Reset Capability (Gigabit LAN—D25:F0).......................................................................... 382 12.1.29FLRCLV—Function Level Reset Capability Length and Version (Gigabit LAN—D25:F0).......................................................................... 383 12.1.30DEVCTRL—Device Control (Gigabit LAN—D25:F0) ..................................... 383 MBARA—Gigabit LAN Base Address A Registers ................................................... 384 12.2.1 LDR4—LAN Device Initialization Register 4 (Gigabit LAN Memory Mapped Base Address Register) ............................... 384 12.2.2 LDR3—LAN Device Initialization Register 3 (Gigabit LAN Memory Mapped Base Address Register) ............................... 384 12.2.3 LDCR2—LAN Device Control Register 2 (Gigabit LAN Memory Mapped Base Address Register) ............................... 385 12.2.4 LDCR4—LAN Device Control Register 4 (Gigabit LAN Memory Mapped Base Address Register) ............................... 385 12.2.5 LDR5—LAN Device Control Register 5 (Gigabit LAN Memory Mapped Base Address Register) ............................... 385 12.2.6 LDR1—LAN Device Initialization Register 1 (Gigabit LAN Memory Mapped Base Address Register) ............................... 385 13 LPC Interface Bridge Registers (D31:F0) ............................................................... 387 13.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 387 13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0).............................. 389 13.1.2 DID—Device Identification Register (LPC I/F—D31:F0) .............................. 389 13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ................................ 389 13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ....................................... 390 13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 391 13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 391 13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)..................................... 391 13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0) ................................... 391 13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)............................ 391 13.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0) ................................. 392 13.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0) ............................ 392 13.1.12PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .......................... 392 13.1.13ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)............................. 393 13.1.14GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0)..................... 393 13.1.15GC—GPIO Control Register (LPC I/F — D31:F0)........................................ 394 13.1.16PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register (LPC I/F—D31:F0) ................................................................................ 395 13.1.17SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0)....................... 396 13.1.18PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register (LPC I/F—D31:F0) ................................................................................ 397 13.1.19LPC_IBDF—IOxAPIC Bus:Device:Function (LPC I/F—D31:F0)...................... 398 13.1.20LPC_HnBDF – HPET n Bus:Device:Function (LPC I/F—D31:F0).................... 398 13.1.21LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0) .................. 399 13.1.22LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ............................... 400 13.1.23GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0) ................................................................................ 401 13.1.24GEN2_DEC—LPC I/F Generic Decode Range 2 Register (LPC I/F—D31:F0) ................................................................................ 401 Datasheet 9 13.2 13.3 13.4 13.5 13.1.25GEN3_DEC—LPC I/F Generic Decode Range 3 Register (LPC I/F—D31:F0) ................................................................................ 402 13.1.26GEN4_DEC—LPC I/F Generic Decode Range 4 Register (LPC I/F—D31:F0) ................................................................................ 403 13.1.27LGMR — LPC I/F Generic Memory Range (LPC I/F—D31:F0) (Corporate Only) .................................................................................. 403 13.1.28FWH_SEL1—Firmware Hub Select 1 Register (LPC I/F—D31:F0) .................. 404 13.1.29FWH_SEL2—Firmware Hub Select 2 Register (LPC I/F—D31:F0) .................. 405 13.1.30FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0) ................................................................................ 406 13.1.31BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) .............................. 408 13.1.32FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0) ........................ 409 13.1.33FDLEN—Feature Detection Capability Length (LPC I/F—D31:F0) .................. 409 13.1.34FDVER—Feature Detection Version (LPC I/F—D31:F0) ............................... 409 13.1.35FDVCT—Feature Vector (LPC I/F—D31:F0) ............................................... 410 13.1.36RCBA—Root Complex Base Address Register (LPC I/F—D31:F0) .................. 410 DMA I/O Registers (LPC I/F—D31:F0)................................................................. 411 13.2.1 DMABASE_CA—DMA Base and Current Address Registers (LPC I/F—D31:F0)................................................................... 412 13.2.2 DMABASE_CC—DMA Base and Current Count Registers (LPC I/F—D31:F0) ................................................................................ 413 13.2.3 DMAMEM_LP—DMA Memory Low Page Registers (LPC I/F—D31:F0) ................................................................................ 413 13.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) .............................. 414 13.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0) .................................... 414 13.2.6 DMA_WRSMSK—DMA Write Single Mask Register (LPC I/F—D31:F0) ................................................................................ 415 13.2.7 DMACH_MODE—DMA Channel Mode Register (LPC I/F—D31:F0) ................................................................................ 416 13.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)................................... 417 13.2.9 DMA Master Clear Register (LPC I/F—D31:F0) .......................................... 417 13.2.10DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) ........................ 417 13.2.11DMA_WRMSK—DMA Write All Mask Register (LPC I/F—D31:F0) ................................................................................ 418 Timer I/O Registers (LPC I/F—D31:F0) ............................................................... 419 13.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0) ............................... 420 13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register (LPC I/F—D31:F0) ................................................................................ 422 13.3.3 Counter Access Ports Register (LPC I/F—D31:F0) ...................................... 423 8259 Interrupt Controller (PIC) Registers (LPC I/F—D31:F0) ........................................................................................... 424 13.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0) ........................................ 424 13.4.2 ICW1—Initialization Command Word 1 Register (LPC I/F—D31:F0) ................................................................................ 425 13.4.3 ICW2—Initialization Command Word 2 Register (LPC I/F—D31:F0) ................................................................................ 426 13.4.4 ICW3—Master Controller Initialization Command Word 3 Register (LPC I/F—D31:F0) ......................................................... 427 13.4.5 ICW3—Slave Controller Initialization Command Word 3 Register (LPC I/F—D31:F0) ......................................................... 427 13.4.6 ICW4—Initialization Command Word 4 Register (LPC I/F—D31:F0) ................................................................................ 428 13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask) Register (LPC I/F—D31:F0) .................................................................... 428 13.4.8 OCW2—Operational Control Word 2 Register (LPC I/F—D31:F0) ................................................................................ 429 13.4.9 OCW3—Operational Control Word 3 Register (LPC I/F—D31:F0) ................................................................................ 430 13.4.10ELCR1—Master Controller Edge/Level Triggered Register (LPC I/F—D31:F0) ................................................................................ 431 13.4.11ELCR2—Slave Controller Edge/Level Triggered Register (LPC I/F—D31:F0) ................................................................................ 432 Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................ 433 13.5.1 APIC Register Map (LPC I/F—D31:F0)...................................................... 433 13.5.2 IND—Index Register (LPC I/F—D31:F0) ................................................... 434 13.5.3 DAT—Data Register (LPC I/F—D31:F0) .................................................... 434 13.5.4 EOIR—EOI Register (LPC I/F—D31:F0) .................................................... 435 10 Datasheet 13.5.5 ID—Identification Register (LPC I/F—D31:F0) .......................................... 436 13.5.6 VER—Version Register (LPC I/F—D31:F0) ................................................ 436 13.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0)..................................... 437 13.6 Real Time Clock Registers................................................................................. 439 13.6.1 I/O Register Address Map ...................................................................... 439 13.6.2 Indexed Registers ................................................................................ 440 13.7 Processor Interface Registers (LPC I/F—D31:F0) ................................................. 444 13.7.1 NMI_SC—NMI Status and Control Register (LPC I/F—D31:F0) ................................................................................ 444 13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) Register (LPC I/F—D31:F0).................................................................... 445 13.7.3 PORT92—Fast A20 and Init Register (LPC I/F—D31:F0) ............................. 445 13.7.4 COPROC_ERR—Coprocessor Error Register (LPC I/F—D31:F0) ................................................................................ 446 13.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0) ................................ 446 13.8 Power Management Registers (PM—D31:F0) ....................................................... 447 13.8.1 Power Management PCI Configuration Registers (PM—D31:F0) ...................................................................................... 447 13.8.2 APM I/O Decode................................................................................... 460 13.8.3 Power Management I/O Registers ........................................................... 461 13.9 System Management TCO Registers (D31:F0) ..................................................... 483 13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register .......................... 483 13.9.2 TCO_DAT_IN—TCO Data In Register ....................................................... 484 13.9.3 TCO_DAT_OUT—TCO Data Out Register .................................................. 484 13.9.4 TCO1_STS—TCO1 Status Register .......................................................... 484 13.9.5 TCO2_STS—TCO2 Status Register .......................................................... 486 13.9.6 TCO1_CNT—TCO1 Control Register ......................................................... 488 13.9.7 TCO2_CNT—TCO2 Control Register ......................................................... 489 13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................... 489 13.9.9 TCO_WDCNT—TCO Watchdog Control Register ......................................... 490 13.9.10SW_IRQ_GEN—Software IRQ Generation Register .................................... 490 13.9.11TCO_TMR—TCO Timer Initial Value Register............................................. 490 13.10 General Purpose I/O Registers (D31:F0)............................................................. 491 13.10.1GPIO_USE_SEL—GPIO Use Select Register .............................................. 492 13.10.2GP_IO_SEL—GPIO Input/Output Select Register ....................................... 492 13.10.3GP_LVL—GPIO Level for Input or Output Register ..................................... 493 13.10.4GPO_BLINK—GPO Blink Enable Register .................................................. 493 13.10.5GP_SER_BLINK—GP Serial Blink ............................................................. 494 13.10.6GP_SB_CMDSTS—GP Serial Blink Command Status................................... 495 13.10.7GP_SB_DATA—GP Serial Blink Data ........................................................ 495 13.10.8GPI_INV—GPIO Signal Invert Register..................................................... 496 13.10.9GPIO_USE_SEL2—GPIO Use Select 2 Register .......................................... 497 13.10.10GP_IO_SEL2—GPIO Input/Output Select 2 Register ................................. 498 13.10.11GP_LVL2—GPIO Level for Input or Output 2 Register ............................... 498 13.10.12GPIO_USE_SEL3—GPIO Use Select 3 Register (Corporate Only) ................ 499 13.10.13GP_IO_SEL3—GPIO Input/Output Select 3 Register (Corporate Only)......... 499 13.10.14GP_LVL3—GPIO Level for Input or Output 3 Register (Corporate Only)....... 500 13.10.15GP_RST_SEL — GPIO Reset Select ........................................................ 500 14 SATA Controller Registers (D31:F2) ....................................................................... 501 14.1 PCI Configuration Registers (SATA–D31:F2)........................................................ 501 14.1.1 VID—Vendor Identification Register (SATA—D31:F2) ................................ 503 14.1.2 DID—Device Identification Register (SATA—D31:F2) ................................. 503 14.1.3 PCICMD—PCI Command Register (SATA–D31:F2)..................................... 503 14.1.4 PCISTS — PCI Status Register (SATA–D31:F2) ......................................... 504 14.1.5 RID—Revision Identification Register (SATA—D31:F2)............................... 505 14.1.6 PI—Programming Interface Register (SATA–D31:F2)................................. 505 14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ........................................ 506 14.1.8 BCC—Base Class Code Register (SATA–D31:F2) ....................................... 506 14.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2) ................... 507 14.1.10HTYPE—Header Type (SATA–D31:F2) ..................................................... 507 14.1.11PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F2) ....................................................................... 507 14.1.12PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F2).................................................................................... 508 14.1.13SCMD_BAR—Secondary Command Block Base Address Register (IDE D31:F1) .......................................................................... 508 Datasheet 11 14.2 14.3 14.4 14.1.14SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) ........................................................................... 508 14.1.15BAR — Legacy Bus Master Base Address Register (SATA–D31:F2) .................................................................................... 509 14.1.16ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA Index Data Pair Base Address (SATA–D31:F2) ................................................... 509 14.1.17SVID—Subsystem Vendor Identification Register (SATA–D31:F2) .................................................................................... 510 14.1.18SID—Subsystem Identification Register (SATA–D31:F2)............................. 510 14.1.19CAP—Capabilities Pointer Register (SATA–D31:F2) .................................... 510 14.1.20INT_LN—Interrupt Line Register (SATA–D31:F2)....................................... 511 14.1.21INT_PN—Interrupt Pin Register (SATA–D31:F2) ........................................ 511 14.1.22IDE_TIM — IDE Timing Register (SATA–D31:F2) ....................................... 511 14.1.23PID—PCI Power Management Capability Identification Register (SATA–D31:F2)........................................................................ 511 14.1.24PC—PCI Power Management Capabilities Register (SATA–D31:F2) .................................................................................... 512 14.1.25PMCS—PCI Power Management Control and Status Register (SATA–D31:F2)........................................................................ 512 14.1.26MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) .................................................................................... 513 14.1.27MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2) ......... 514 14.1.28MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2) ....... 515 14.1.29MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ............ 515 14.1.30MAP—Address Map Register (SATA–D31:F2)............................................. 516 14.1.31PCS—Port Control and Status Register (SATA–D31:F2) .............................. 516 14.1.32SCLKCG—SATA Clock Gating Control Register........................................... 519 14.1.33SCLKGC—SATA Clock General Configuration Register................................. 520 14.1.34FLRCID—FLR Capability ID (SATA–D31:F2) .............................................. 522 14.1.35FLRCLV—FLR Capability Length and Version (SATA–D31:F2)....................... 522 14.1.36FLRC—FLR Control (SATA–D31:F2) ......................................................... 523 14.1.37ATC—APM Trapping Control Register (SATA–D31:F2)................................. 523 14.1.38ATS—APM Trapping Status Register (SATA–D31:F2).................................. 524 14.1.39SP Scratch Pad Register (SATA–D31:F2) .................................................. 524 14.1.40BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ........................... 525 14.1.41BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ........................ 527 14.1.42BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ........................ 527 Bus Master IDE I/O Registers (D31:F2)............................................................... 528 14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................... 529 14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)................................ 530 14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2)................................................................................. 531 14.2.4 AIR—AHCI Index Register (D31:F2) ........................................................ 531 14.2.5 AIDR—AHCI Index Data Register (D31:F2)............................................... 531 Serial ATA Index/Data Pair Superset Registers..................................................... 532 14.3.1 SINDX – Serial ATA Index (D31:F2) ........................................................ 532 14.3.2 SDATA – Serial ATA Data (D31:F2) ......................................................... 532 AHCI Registers (D31:F2) .................................................................................. 536 14.4.1 AHCI Generic Host Control Registers (D31:F2).......................................... 537 14.4.2 Vendor Specific Registers (D31:F2) ......................................................... 545 14.4.3 Port Registers (D31:F2) ......................................................................... 545 15 SATA Controller Registers (D31:F5) ....................................................................... 563 15.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ 563 15.1.1 VID—Vendor Identification Register (SATA—D31:F5) ................................. 564 15.1.2 DID—Device Identification Register (SATA—D31:F5) ................................. 565 15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) ..................................... 565 15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) ......................................... 566 15.1.5 RID—Revision Identification Register (SATA—D31:F5) ............................... 566 15.1.6 PI—Programming Interface Register (SATA–D31:F5) ................................. 567 15.1.7 SCC—Sub Class Code Register (SATA–D31:F5) ......................................... 567 15.1.8 BCC—Base Class Code Register (SATA–D31:F5)........................................ 567 15.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F5) .................................................................................... 568 15.1.10PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F5)........................................................................ 568 12 Datasheet 15.2 15.3 16 15.1.11PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F5).................................................................................... 568 15.1.12SCMD_BAR—Secondary Command Block Base Address Register (IDE D31:F1) .......................................................................... 569 15.1.13SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) .......................................................................... 569 15.1.14BAR — Legacy Bus Master Base Address Register (SATA–D31:F5).................................................................................... 570 15.1.15SIDPBA — SATA Index/Data Pair Base Address Register (SATA–D31:F5).................................................................................... 570 15.1.16SVID—Subsystem Vendor Identification Register (SATA–D31:F5).................................................................................... 571 15.1.17SID—Subsystem Identification Register (SATA–D31:F5) ............................ 571 15.1.18CAP—Capabilities Pointer Register (SATA–D31:F5).................................... 571 15.1.19INT_LN—Interrupt Line Register (SATA–D31:F5) ...................................... 571 15.1.20INT_PN—Interrupt Pin Register (SATA–D31:F5)........................................ 571 15.1.21IDE_TIM — IDE Timing Register (SATA–D31:F5) ...................................... 572 15.1.22PID—PCI Power Management Capability Identification Register (SATA–D31:F5) ....................................................................... 572 15.1.23PC—PCI Power Management Capabilities Register (SATA–D31:F5).................................................................................... 572 15.1.24PMCS—PCI Power Management Control and Status Register (SATA–D31:F5) ....................................................................... 573 15.1.25MID—Message Signal Interrupt Identifier (SATA–D31:F5) (Consumer Only).................................................................................. 573 15.1.26MC—Message Signal Interrupt Message Control (SATA–D31:F5) (Consumer Only).................................................................................. 574 15.1.27MA—Message Signal Interrupt Message Address (SATA–D31:F5) (Consumer Only).................................................................................. 574 15.1.28MD—Message Signal Interrupt Message Data (SATA–D31:F5) (Consumer Only).................................................................................. 574 15.1.29MAP—Address Map Register (SATA–D31:F5)16......................................... 575 15.1.30PCS—Port Control and Status Register (SATA–D31:F5).............................. 576 15.1.31SATACR0— SATA Capability Register 0 (SATA–D31:F5) ............................. 577 15.1.32SATACR1— SATA Capability Register 1 (SATA–D31:F5) ............................. 577 15.1.33FLRCID— FLR Capability ID (SATA–D31:F5) ............................................. 577 15.1.34FLRCLV— FLR Capability Length and Value (SATA–D31:F5) ........................ 578 15.1.35FLRCTRL— FLR Control (SATA–D31:F5) ................................................... 578 15.1.36ATC—APM Trapping Control Register (SATA–D31:F5) ................................ 579 15.1.37ATC—APM Trapping Control (SATA–D31:F5) ............................................ 579 Bus Master IDE I/O Registers (D31:F5) .............................................................. 580 15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) .......................... 581 15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) ............................... 582 15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F5) ................................................................................ 582 Serial ATA Index/Data Pair Superset Registers .................................................... 583 15.3.1 SINDX—SATA Index Register (D31:F5) ................................................... 583 15.3.2 SDATA—SATA Index Data Register (D31:F5)............................................ 583 UHCI Controllers Registers .................................................................................... 589 16.1 PCI Configuration Registers (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ..................... 589 16.1.1 VID—Vendor Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ................................................. 590 16.1.2 DID—Device Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ................................................. 590 16.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ................................................. 591 16.1.4 PCISTS—PCI Status Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ................................................. 592 16.1.5 RID—Revision Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ................................................. 592 16.1.6 PI—Programming Interface Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ................................................. 593 16.1.7 SCC—Sub Class Code Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ................................................. 593 16.1.8 BCC—Base Class Code Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ................................................. 593 Datasheet 13 16.2 16.1.9 MLT—Master Latency Timer Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 593 16.1.10HEADTYP—Header Type Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 594 16.1.11BASE—Base Address Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 594 16.1.12SVID — Subsystem Vendor Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 594 16.1.13SID — Subsystem Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 595 16.1.14CAP_PTR—Capabilities Pointer (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 595 16.1.15INT_LN—Interrupt Line Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 595 16.1.16INT_PN—Interrupt Pin Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 596 16.1.17FLRCID—Function Level Reset Capability ID (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 596 16.1.18FLRNCP—Function Level Reset Next Capability Pointer (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 596 16.1.19FLRCLV—Function Level Reset Capability Length and Version (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 597 16.1.20USB_FLRCTRL—FLR Control Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 597 16.1.21USB_FLRSTAT—FLR Status Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 598 16.1.22USB_RELNUM—Serial Bus Release Number Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 598 16.1.23USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) ..................................... 598 16.1.24USB_RES—USB Resume Enable Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 600 16.1.25CWP—Core Well Policy Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 601 16.1.26UCR1—UCHI Configuration Register 1 (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).................................................. 601 USB I/O Registers............................................................................................ 602 16.2.1 USBCMD—USB Command Register .......................................................... 603 16.2.2 USBSTS—USB Status Register ................................................................ 606 16.2.3 USBINTR—USB Interrupt Enable Register................................................. 607 16.2.4 FRNUM—Frame Number Register ............................................................ 607 16.2.5 FRBASEADD—Frame List Base Address Register........................................ 608 16.2.6 SOFMOD—Start of Frame Modify Register ................................................ 608 16.2.7 PORTSC[0,1]—Port Status and Control Register ........................................ 609 17 EHCI Controller Registers (D29:F7, D26:F7)........................................................... 611 17.1 USB EHCI Configuration Registers (USB EHCI—D29:F7, D26:F7)............................ 611 17.1.1 VID—Vendor Identification Register (USB EHCI—D29:F7, D26:F7)................................................................. 612 17.1.2 DID—Device Identification Register (USB EHCI—D29:F7, D26:F7)................................................................. 612 17.1.3 PCICMD—PCI Command Register (USB EHCI—D29:F7, D26:F7)................................................................. 613 17.1.4 PCISTS—PCI Status Register (USB EHCI—D29:F7, D26:F7) ........................ 614 17.1.5 RID—Revision Identification Register (USB EHCI—D29:F7, D26:F7)................................................................. 615 17.1.6 PI—Programming Interface Register (USB EHCI—D29:F7, D26:F7)................................................................. 615 17.1.7 SCC—Sub Class Code Register (USB EHCI—D29:F7, D26:F7)................................................................. 615 17.1.8 BCC—Base Class Code Register (USB EHCI—D29:F7, D26:F7)................................................................. 615 17.1.9 PMLT—Primary Master Latency Timer Register (USB EHCI—D29:F7, D26:F7)................................................................. 616 17.1.10MEM_BASE—Memory Base Address Register (USB EHCI—D29:F7, D26:F7)................................................................. 616 14 Datasheet 17.2 17.1.11SVID—USB EHCI Subsystem Vendor ID Register (USB EHCI—D29:F7, D26:F7) ................................................................ 616 17.1.12SID—USB EHCI Subsystem ID Register (USB EHCI—D29:F7, D26:F7) ................................................................ 617 17.1.13CAP_PTR—Capabilities Pointer Register (USB EHCI—D29:F7, D26:F7) ................................................................ 617 17.1.14INT_LN—Interrupt Line Register (USB EHCI—D29:F7, D26:F7) ................................................................ 617 17.1.15INT_PN—Interrupt Pin Register (USB EHCI—D29:F7, D26:F7) ................................................................ 617 17.1.16PWR_CAPID—PCI Power Management Capability ID Register (USB EHCI—D29:F7, D26:F7) .................................................... 618 17.1.17NXT_PTR1—Next Item Pointer #1 Register (USB EHCI—D29:F7, D26:F7) ................................................................ 618 17.1.18PWR_CAP—Power Management Capabilities Register (USB EHCI—D29:F7, D26:F7) ................................................................ 619 17.1.19PWR_CNTL_STS—Power Management Control/ Status Register (USB EHCI—D29:F7, D26:F7) .......................................... 620 17.1.20DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F7, D26:F7) ................................................................ 621 17.1.21NXT_PTR2—Next Item Pointer #2 Register (USB EHCI—D29:F7, D26:F7) ................................................................ 621 17.1.22DEBUG_BASE—Debug Port Base Offset Register (USB EHCI—D29:F7, D26:F7) ................................................................ 621 17.1.23USB_RELNUM—USB Release Number Register (USB EHCI—D29:F7, D26:F7) ................................................................ 621 17.1.24FL_ADJ—Frame Length Adjustment Register (USB EHCI—D29:F7, D26:F7) ................................................................ 622 17.1.25PWAKE_CAP—Port Wake Capability Register (USB EHCI—D29:F7, D26:F7) ................................................................ 623 17.1.26LEG_EXT_CAP—USB EHCI Legacy Support Extended Capability Register (USB EHCI—D29:F7, D26:F7) ..................................... 624 17.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F7, D26:F7) ............................. 624 17.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7, D26:F7) ................................................................ 626 17.1.29ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7, D26:F7) ................................................................ 628 17.1.30EHCIIR1—EHCI Initialization Register 1 (USB EHCI—D29:F7, D26:F7) ................................................................ 628 17.1.31FLR_CID—Function Level Reset Capability ID (USB EHCI—D29:F7, D26:F7) ................................................................ 628 17.1.32FLR_NEXT—Function Level Reset Next Capability Pointer (USB EHCI—D29:F7, D26:F7) ................................................................ 629 17.1.33FLR_CLV—Function Level Reset Capability Length and Version (USB EHCI—D29:F7, D26:F7) ................................................................ 629 17.1.34FLR_CTRL—Function Level Reset Control Register (USB EHCI—D29:F7, D26:F7) ................................................................ 630 17.1.35FLR_STS—Function Level Reset Status Register (USB EHCI—D29:F7, D26:F7) ................................................................ 630 17.1.36EHCIIR2—EHCI Initialization Register 2 (USB EHCI—D29:F7, D26:F7) ................................................................ 630 Memory-Mapped I/O Registers .......................................................................... 631 17.2.1 Host Controller Capability Registers ........................................................ 631 17.2.2 Host Controller Operational Registers ...................................................... 635 17.2.3 USB 2.0-Based Debug Port Register........................................................ 649 18 Intel® High Definition Audio Controller Registers (D27:F0) ................................... 653 18.1 Intel® High Definition Audio PCI Configuration Space (Intel® High Definition Audio— D27:F0) ............................................................. 653 18.1.1 VID—Vendor Identification Register (Intel® High Definition Audio Controller—D27:F0)..................................... 655 18.1.2 DID—Device Identification Register (Intel® High Definition Audio Controller—D27:F0)..................................... 655 18.1.3 PCICMD—PCI Command Register (Intel® High Definition Audio Controller—D27:F0)..................................... 655 Datasheet 15 18.1.4 PCISTS—PCI Status Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 656 18.1.5 RID—Revision Identification Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 657 18.1.6 PI—Programming Interface Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 657 18.1.7 SCC—Sub Class Code Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 657 18.1.8 BCC—Base Class Code Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 657 18.1.9 CLS—Cache Line Size Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 657 18.1.10LT—Latency Timer Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 658 18.1.11HEADTYP—Header Type Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 658 18.1.12HDBARL—Intel® High Definition Audio Lower Base Address Register (Intel® High Definition Audio—D27:F0).................................................... 658 18.1.13HDBARU—Intel® High Definition Audio Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 658 18.1.14SVID—Subsystem Vendor Identification Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 659 18.1.15SID—Subsystem Identification Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 659 18.1.16CAPPTR—Capabilities Pointer Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 659 18.1.17INTLN—Interrupt Line Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 660 18.1.18INTPN—Interrupt Pin Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 660 18.1.19HDCTL—Intel® High Definition Audio Control Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 660 18.1.20TCSEL—Traffic Class Select Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 661 18.1.21PID—PCI Power Management Capability ID Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 661 18.1.22PC—Power Management Capabilities Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 662 18.1.23PCS—Power Management Control and Status Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 663 18.1.24MID—MSI Capability ID Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 664 18.1.25MMC—MSI Message Control Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 664 18.1.26MMLA—MSI Message Lower Address Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 664 18.1.27MMUA—MSI Message Upper Address Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 664 18.1.28MMD—MSI Message Data Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 665 18.1.29PXID—PCI Express* Capability ID Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 665 18.1.30PXC—PCI Express* Capabilities Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 665 18.1.31DEVCAP—Device Capabilities Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 666 18.1.32DEVC—Device Control Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 667 18.1.33DEVS—Device Status Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 668 18.1.34VCCAP—Virtual Channel Enhanced Capability Header (Intel® High Definition Audio Controller—D27:F0) ..................................... 668 18.1.35PVCCAP1—Port VC Capability Register 1 (Intel® High Definition Audio Controller—D27:F0) ..................................... 669 18.1.36PVCCAP2 — Port VC Capability Register 2 (Intel® High Definition Audio Controller—D27:F0) ..................................... 669 16 Datasheet 18.2 18.1.37PVCCTL — Port VC Control Register (Intel® High Definition Audio Controller—D27:F0)..................................... 669 18.1.38PVCSTS—Port VC Status Register (Intel® High Definition Audio Controller—D27:F0)..................................... 670 18.1.39VC0CAP—VC0 Resource Capability Register (Intel® High Definition Audio Controller—D27:F0)..................................... 670 18.1.40VC0CTL—VC0 Resource Control Register (Intel® High Definition Audio Controller—D27:F0)..................................... 671 18.1.41VC0STS—VC0 Resource Status Register (Intel® High Definition Audio Controller—D27:F0)..................................... 671 18.1.42VCiCAP—VCi Resource Capability Register (Intel® High Definition Audio Controller—D27:F0)..................................... 672 18.1.43VCiCTL—VCi Resource Control Register (Intel® High Definition Audio Controller—D27:F0)..................................... 672 18.1.44VCiSTS—VCi Resource Status Register (Intel® High Definition Audio Controller—D27:F0)..................................... 673 18.1.45RCCAP—Root Complex Link Declaration Enhanced Capability Header Register (Intel® High Definition Audio Controller—D27:F0).............. 673 18.1.46ESD—Element Self Description Register (Intel® High Definition Audio Controller—D27:F0)..................................... 673 18.1.47L1DESC—Link 1 Description Register (Intel® High Definition Audio Controller—D27:F0)..................................... 674 18.1.48L1ADDL—Link 1 Lower Address Register (Intel® High Definition Audio Controller—D27:F0)..................................... 674 18.1.49L1ADDU—Link 1 Upper Address Register (Intel® High Definition Audio Controller—D27:F0)..................................... 674 Intel® High Definition Audio Memory Mapped Configuration Registers (Intel® High Definition Audio— D27:F0) ............................................................. 675 18.2.1 GCAP—Global Capabilities Register (Intel® High Definition Audio Controller—D27:F0)..................................... 679 18.2.2 VMIN—Minor Version Register (Intel® High Definition Audio Controller—D27:F0)..................................... 679 18.2.3 VMAJ—Major Version Register (Intel® High Definition Audio Controller—D27:F0)..................................... 679 18.2.4 OUTPAY—Output Payload Capability Register (Intel® High Definition Audio Controller—D27:F0)..................................... 680 18.2.5 INPAY—Input Payload Capability Register (Intel® High Definition Audio Controller—D27:F0)..................................... 680 18.2.6 GCTL—Global Control Register (Intel® High Definition Audio Controller—D27:F0)..................................... 681 18.2.7 WAKEEN—Wake Enable Register (Intel® High Definition Audio Controller—D27:F0)..................................... 682 18.2.8 STATESTS—State Change Status Register (Intel® High Definition Audio Controller—D27:F0)..................................... 682 18.2.9 GSTS—Global Status Register (Intel® High Definition Audio Controller—D27:F0)..................................... 683 18.2.10OUTSTRMPAY—Output Stream Payload Capability (Intel® High Definition Audio Controller—D27:F0)..................................... 683 18.2.11INSTRMPAY—Input Stream Payload Capability (Intel® High Definition Audio Controller—D27:F0)..................................... 684 18.2.12INTCTL—Interrupt Control Register (Intel® High Definition Audio Controller—D27:F0)..................................... 685 18.2.13INTSTS—Interrupt Status Register (Intel® High Definition Audio Controller—D27:F0)..................................... 686 18.2.14WALCLK—Wall Clock Counter Register (Intel® High Definition Audio Controller—D27:F0)..................................... 686 18.2.15SSYNC—Stream Synchronization Register (Intel® High Definition Audio Controller—D27:F0)..................................... 687 18.2.16CORBLBASE—CORB Lower Base Address Register (Intel® High Definition Audio Controller—D27:F0)..................................... 687 18.2.17CORBUBASE—CORB Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0)..................................... 688 18.2.18CORBWP—CORB Write Pointer Register (Intel® High Definition Audio Controller—D27:F0)..................................... 688 18.2.19CORBRP—CORB Read Pointer Register (Intel® High Definition Audio Controller—D27:F0)..................................... 688 Datasheet 17 18.2.20CORBCTL—CORB Control Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 689 18.2.21CORBST—CORB Status Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 689 18.2.22CORBSIZE—CORB Size Register Intel® High Definition Audio Controller—D27:F0) ...................................... 689 18.2.23RIRBLBASE—RIRB Lower Base Address Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 690 18.2.24RIRBUBASE—RIRB Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 690 18.2.25RIRBWP—RIRB Write Pointer Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 690 18.2.26RINTCNT—Response Interrupt Count Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 691 18.2.27RIRBCTL—RIRB Control Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 691 18.2.28RIRBSTS—RIRB Status Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 692 18.2.29RIRBSIZE—RIRB Size Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 692 18.2.30IC—Immediate Command Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 692 18.2.31IR—Immediate Response Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 693 18.2.32IRS—Immediate Command Status Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 693 18.2.33DPLBASE—DMA Position Lower Base Address Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 694 18.2.34DPUBASE—DMA Position Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 694 18.2.35SDCTL—Stream Descriptor Control Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 695 18.2.36SDSTS—Stream Descriptor Status Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 697 18.2.37SDLPIB—Stream Descriptor Link Position in Buffer Register (Intel® High Definition Audio Controller—D27:F0) ......................... 698 18.2.38SDCBL—Stream Descriptor Cyclic Buffer Length Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 698 18.2.39SDLVI—Stream Descriptor Last Valid Index Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 699 18.2.40SDFIFOW—Stream Descriptor FIFO Watermark Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 699 18.2.41SDFIFOS—Stream Descriptor FIFO Size Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 700 18.2.42SDFMT—Stream Descriptor Format Register (Intel® High Definition Audio Controller—D27:F0) ..................................... 701 18.2.43SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel® High Definition Audio Controller—D27:F0) ..... 702 18.2.44SDBDPU—Stream Descriptor Buffer Descriptor List Pointer Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) ............. 702 19 SMBus Controller Registers (D31:F3) ..................................................................... 703 19.1 PCI Configuration Registers (SMBus—D31:F3) ..................................................... 703 19.1.1 VID—Vendor Identification Register (SMBus—D31:F3) ............................... 703 19.1.2 DID—Device Identification Register (SMBus—D31:F3) ............................... 704 19.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) .................................. 704 19.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) ........................................ 705 19.1.5 RID—Revision Identification Register (SMBus—D31:F3) ............................. 705 19.1.6 PI—Programming Interface Register (SMBus—D31:F3) .............................. 706 19.1.7 SCC—Sub Class Code Register (SMBus—D31:F3) ...................................... 706 19.1.8 BCC—Base Class Code Register (SMBus—D31:F3)..................................... 706 19.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0 (SMBus—D31:F3) ................................................................................. 706 19.1.10SMBMBAR1—D31_F3_SMBus Memory Base Address 1 (SMBus—D31:F3) ................................................................................. 707 19.1.11SMB_BASE—SMBus Base Address Register (SMBus—D31:F3) ................................................................................. 707 18 Datasheet 19.2 19.1.12SVID—Subsystem Vendor Identification Register (SMBus—D31:F2/F4) ............................................................................ 707 19.1.13SID—Subsystem Identification Register (SMBus—D31:F2/F4)..................... 708 19.1.14INT_LN—Interrupt Line Register (SMBus—D31:F3) ................................... 708 19.1.15INT_PN—Interrupt Pin Register (SMBus—D31:F3)..................................... 708 19.1.16HOSTC—Host Configuration Register (SMBus—D31:F3) ............................. 709 SMBus I/O and Memory Mapped I/O Registers .................................................... 710 19.2.1 HST_STS—Host Status Register (SMBus—D31:F3).................................... 711 19.2.2 HST_CNT—Host Control Register (SMBus—D31:F3) .................................. 712 19.2.3 HST_CMD—Host Command Register (SMBus—D31:F3).............................. 714 19.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBus—D31:F3) ................ 714 19.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) ..................................... 714 19.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) ..................................... 714 19.2.7 Host_BLOCK_DB—Host Block Data Byte Register (SMBus—D31:F3) ............ 715 19.2.8 PEC—Packet Error Check (PEC) Register (SMBus—D31:F3) ........................ 715 19.2.9 RCV_SLVA—Receive Slave Address Register (SMBus—D31:F3) ................... 716 19.2.10SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) ....................... 716 19.2.11AUX_STS—Auxiliary Status Register (SMBus—D31:F3) .............................. 716 19.2.12AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) ............................. 717 19.2.13SMLINK_PIN_CTL—SMLink Pin Control Register (SMBus—D31:F3) .............. 717 19.2.14SMBus_PIN_CTL—SMBus Pin Control Register (SMBus—D31:F3)................. 718 19.2.15SLV_STS—Slave Status Register (SMBus—D31:F3)................................... 718 19.2.16SLV_CMD—Slave Command Register (SMBus—D31:F3)............................. 719 19.2.17NOTIFY_DADDR—Notify Device Address Register (SMBus—D31:F3) ............ 719 19.2.18NOTIFY_DLOW—Notify Data Low Byte Register (SMBus—D31:F3) ............... 720 19.2.19NOTIFY_DHIGH—Notify Data High Byte Register (SMBus—D31:F3) ............. 720 20 PCI Express* Configuration Registers.................................................................... 721 20.1 PCI Express* Configuration Registers (PCI Express—D28:F0/F1/F2/F3/F4/F5) ......... 721 20.1.1 VID—Vendor Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 724 20.1.2 DID—Device Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 724 20.1.3 PCICMD—PCI Command Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 725 20.1.4 PCISTS—PCI Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 726 20.1.5 RID—Revision Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 727 20.1.6 PI—Programming Interface Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 727 20.1.7 SCC—Sub Class Code Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 727 20.1.8 BCC—Base Class Code Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 727 20.1.9 CLS—Cache Line Size Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 728 20.1.10PLT—Primary Latency Timer Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 728 20.1.11HEADTYP—Header Type Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 728 20.1.12BNUM—Bus Number Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 728 20.1.13SLT—Secondary Latency Timer (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 729 20.1.14IOBL—I/O Base and Limit Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 729 20.1.15SSTS—Secondary Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 730 20.1.16MBL—Memory Base and Limit Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 731 20.1.17PMBL—Prefetchable Memory Base and Limit Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 731 20.1.18PMBU32—Prefetchable Memory Base Upper 32 Bits Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................... 731 20.1.19PMLU32—Prefetchable Memory Limit Upper 32 Bits Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................... 732 Datasheet 19 20.1.20CAPP—Capabilities List Pointer Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 732 20.1.21INTR—Interrupt Information Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 732 20.1.22BCTRL—Bridge Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 733 20.1.23CLIST—Capabilities List Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 734 20.1.24XCAP—PCI Express* Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 734 20.1.25DCAP—Device Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 735 20.1.26DCTL—Device Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 736 20.1.27DSTS—Device Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 737 20.1.28LCAP—Link Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 738 20.1.29LCTL—Link Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 740 20.1.30LSTS—Link Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 741 20.1.31SLCAP—Slot Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 742 20.1.32SLCTL—Slot Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 743 20.1.33SLSTS—Slot Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 744 20.1.34RCTL—Root Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 745 20.1.35RSTS—Root Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 745 20.1.36DCAP2—Device Capabilities 2 Register (Corporate Only) (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 746 20.1.37DCTL2—Device Control 2 Register (Corporate Only) (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 746 20.1.38LCTL2—Link Control 2 Register (Corporate Only) (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 747 20.1.39MID—Message Signaled Interrupt Identifiers Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 747 20.1.40MC—Message Signaled Interrupt Message Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 747 20.1.41MA—Message Signaled Interrupt Message Address Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)....................................... 748 20.1.42MD—Message Signaled Interrupt Message Data Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 748 20.1.43SVCAP—Subsystem Vendor Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 748 20.1.44SVID—Subsystem Vendor Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 748 20.1.45PMCAP—Power Management Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 749 20.1.46PMC—PCI Power Management Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 749 20.1.47PMCS—PCI Power Management Control and Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)....................................... 750 20.1.48MPC2—Miscellaneous Port Configuration Register 2 (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 751 20.1.49MPC—Miscellaneous Port Configuration Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 752 20.1.50SMSCS—SMI/SCI Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 754 20.1.51RPDCGEN—Root Port Dynamic Clock Gating Enable (PCI Express-D28:F0/F1/F2/F3/F4/F5)..................................................... 755 20.1.52PECR1—PCI Express* Configuration Register 1 (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 755 20 Datasheet 20.1.53VCH—Virtual Channel Capability Header Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 756 20.1.54VCAP2—Virtual Channel Capability 2 Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 756 20.1.55PVC—Port Virtual Channel Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 756 20.1.56PVS—Port Virtual Channel Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 757 20.1.57V0CAP—Virtual Channel 0 Resource Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 757 20.1.58V0CTL—Virtual Channel 0 Resource Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 758 20.1.59V0STS—Virtual Channel 0 Resource Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 758 20.1.60UES—Uncorrectable Error Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 759 20.1.61UEM—Uncorrectable Error Mask (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 760 20.1.62UEV — Uncorrectable Error Severity (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 761 20.1.63CES — Correctable Error Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 762 20.1.64CEM — Correctable Error Mask Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 762 20.1.65AECC — Advanced Error Capabilities and Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 763 20.1.66RES — Root Error Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 763 20.1.67RCTCL — Root Complex Topology Capability List Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 763 20.1.68ESD—Element Self Description Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 764 20.1.69ULD — Upstream Link Description Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 764 20.1.70ULBA — Upstream Link Base Address Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 765 20.1.71PECR2 — PCI Express* Configuration Register 2 (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 765 20.1.72PEETM — PCI Express* Extended Test Mode Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 765 20.1.73PEC1 — PCI Express* Configuration Register 1 (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 766 21 High Precision Event Timer Registers .................................................................... 767 21.1 Memory Mapped Registers................................................................................ 767 21.1.1 GCAP_ID—General Capabilities and Identification Register ......................... 769 21.1.2 GEN_CONF—General Configuration Register............................................. 770 21.1.3 GINTR_STA—General Interrupt Status Register ........................................ 770 21.1.4 MAIN_CNT—Main Counter Value Register ................................................ 771 21.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register ..................... 772 21.1.6 TIMn_COMP—Timer n Comparator Value Register ..................................... 775 Serial Peripheral Interface (SPI) ........................................................................... 777 22.1 Serial Peripheral Interface Memory Mapped Configuration Registers ....................... 777 22.1.1 BFPR –BIOS Flash Primary Region Register (SPI Memory Mapped Configuration Registers) ......................................... 779 22.1.2 HSFS—Hardware Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) ......................................... 779 22.1.3 HSFC—Hardware Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) ......................................... 781 22.1.4 FADDR—Flash Address Register (SPI Memory Mapped Configuration Registers) ......................................... 781 22.1.5 FDATA0—Flash Data 0 Register (SPI Memory Mapped Configuration Registers) ......................................... 782 22.1.6 FDATAN—Flash Data [N] Register (SPI Memory Mapped Configuration Registers) ......................................... 782 22 Datasheet 21 22.2 22.3 22.4 22.1.7 FRAP—Flash Regions Access Permissions Register (SPI Memory Mapped Configuration Registers).......................................... 783 22.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register (SPI Memory Mapped Configuration Registers).......................................... 784 22.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register (SPI Memory Mapped Configuration Registers).......................................... 784 22.1.10FREG2—Flash Region 2 (ME) Register (SPI Memory Mapped Configuration Registers).......................................... 785 22.1.11FREG3—Flash Region 3 (GbE) Register (SPI Memory Mapped Configuration Registers).......................................... 785 22.1.12FREG4—Flash Region 4 (Platform Data) Register (SPI Memory Mapped Configuration Registers).......................................... 786 22.1.13PR0—Protected Range 0 Register (SPI Memory Mapped Configuration Registers).......................................... 786 22.1.14PR1—Protected Range 1 Register (SPI Memory Mapped Configuration Registers).......................................... 787 22.1.15PR2—Protected Range 2 Register (SPI Memory Mapped Configuration Registers).......................................... 788 22.1.16PR3—Protected Range 3 Register (SPI Memory Mapped Configuration Registers).......................................... 788 22.1.17PR4—Protected Range 4 Register (SPI Memory Mapped Configuration Registers).......................................... 789 22.1.18SSFS—Software Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers).......................................... 790 22.1.19SSFC—Software Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers).......................................... 791 22.1.20PREOP—Prefix Opcode Configuration Register (SPI Memory Mapped Configuration Registers).......................................... 792 22.1.21OPTYPE—Opcode Type Configuration Register (SPI Memory Mapped Configuration Registers).......................................... 792 22.1.22OPMENU—Opcode Menu Configuration Register (SPI Memory Mapped Configuration Registers).......................................... 793 22.1.23BBAR—BIOS Base Address Configuration Register (SPI Memory Mapped Configuration Registers).......................................... 794 22.1.24FDOC—Flash Descriptor Observability Control Register (SPI Memory Mapped Configuration Registers).......................................... 794 22.1.25FDOD—Flash Descriptor Observability Data Register (SPI Memory Mapped Configuration Registers).......................................... 795 22.1.26AFC—Additional Flash Control Register (SPI Memory Mapped Configuration Registers).......................................... 795 22.1.27LVSCC— Host Lower Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers).......................................... 796 22.1.28UVSCC— Host Upper Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers).......................................... 797 22.1.29FPB — Flash Partition Boundary (SPI Memory Mapped Configuration Registers).......................................... 799 Flash Descriptor Registers................................................................................. 800 22.2.1 Flash Descriptor Content........................................................................ 800 22.2.2 Flash Descriptor Component Section ....................................................... 802 22.2.3 Flash Descriptor Region Section .............................................................. 805 22.2.4 Flash Descriptor Master Section .............................................................. 807 22.2.5 Descriptor Upper Map Section................................................................. 810 22.2.6 Intel ME Vendor Specific Component Capabilities Table .............................. 810 OEM Section ................................................................................................... 815 GbE SPI Flash Program Registers ....................................................................... 815 22.4.1 GLFPR –Gigabit LAN Flash Primary Region Register (GbE LAN Memory Mapped Configuration Registers) .................................. 816 22.4.2 HSFS—Hardware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) .................................. 817 22.4.3 HSFC—Hardware Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) .................................. 818 22.4.4 FADDR—Flash Address Register (GbE LAN Memory Mapped Configuration Registers) .................................. 818 22.4.5 FDATA0—Flash Data 0 Register (GbE LAN Memory Mapped Configuration Registers) .................................. 819 22.4.6 FRAP—Flash Regions Access Permissions Register (GbE LAN Memory Mapped Configuration Registers) .................................. 820 22 Datasheet 22.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) .................................. 821 22.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) .................................. 821 22.4.9 FREG2—Flash Region 2 (ME) Register (GbE LAN Memory Mapped Configuration Registers) .................................. 821 22.4.10FREG3—Flash Region 3 (GbE) Register (GbE LAN Memory Mapped Configuration Registers) .................................. 822 22.4.11FPR0—Flash Protected Range 0 Register (GbE LAN Memory Mapped Configuration Registers) .................................. 822 22.4.12FPR1—Flash Protected Range 1 Register (GbE LAN Memory Mapped Configuration Registers) .................................. 823 22.4.13SSFS—Software Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) .................................. 824 22.4.14SSFC—Software Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) .................................. 825 22.4.15PREOP—Prefix Opcode Configuration Register (GbE LAN Memory Mapped Configuration Registers) .................................. 826 22.4.16OPTYPE—Opcode Type Configuration Register (GbE LAN Memory Mapped Configuration Registers) .................................. 826 22.4.17OPMENU—Opcode Menu Configuration Register (GbE LAN Memory Mapped Configuration Registers) .................................. 827 23 Thermal Sensor Registers (D31:F6) ....................................................................... 829 23.1 PCI Bus Configuration Registers ........................................................................ 829 23.1.1 VID—Vendor Identification..................................................................... 830 23.1.2 DID—Device Identification ..................................................................... 830 23.1.3 CMD—Command .................................................................................. 830 23.1.4 STS—Status ........................................................................................ 831 23.1.5 RID—Revision Identification ................................................................... 831 23.1.6 PI— Programming Interface................................................................... 831 23.1.7 SCC—Sub Class Code ........................................................................... 832 23.1.8 BCC—Base Class Code .......................................................................... 832 23.1.9 CLS—Cache Line Size............................................................................ 832 23.1.10LT—Latency Timer................................................................................ 832 23.1.11BIST—Built-in Self Test ......................................................................... 833 23.1.12TBAR—Thermal Base ............................................................................ 833 23.1.13TBARH—Thermal Base High DWord......................................................... 833 23.1.14SVID—Subsystem Vendor ID ................................................................. 834 23.1.15SID—Subsystem ID .............................................................................. 834 23.1.16CAP_PTR —Capabilities Pointer............................................................... 834 23.1.17Offset 3Ch – INTLN—Interrupt Line......................................................... 834 23.1.18INTPN—Interrupt Pin ............................................................................ 835 23.1.19TBARB—BIOS Assigned Thermal Base Address ......................................... 835 23.1.20TBARBH—BIOS Assigned Thermal Base High DWord ................................. 835 23.1.21PID—PCI Power Management Capability ID .............................................. 836 23.1.22PC—Power Management Capabilities ....................................................... 836 23.1.23PCS—Power Management Control And Status ........................................... 837 23.2 Thermal Memory Mapped Configuration Registers (Thermal Sensor - D31:F26) ............................................................................. 838 23.2.1 TSxE—Thermal Sensor [1:0] Enable ....................................................... 838 23.2.2 TSxS—Thermal Sensor[1:0] Status......................................................... 839 23.2.3 TSxTTP—Thermal Sensor [1:0] Catastrophic Trip Point .............................. 839 23.2.4 TSxCO—Thermal Sensor [1:0] Catastrophic Lock-Down............................. 839 23.2.5 TSxPC—Thermal Sensor [1:0] Policy Control ............................................ 840 23.2.6 TSxLOCK—Thermal Sensor [1:0] Register Lock Control ............................. 840 Datasheet 23 Figures 2-1 2-1 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 6-1 6-2 7-1 7-2 7-3 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 Intel® ICH10 Interface Signals Block Diagram..........................................................46 Example External RTC Circuit.................................................................................79 ICH10 Conceptual System Clock Diagram ................................................................92 Generation of SERR# to Platform ...........................................................................99 LPC Interface Diagram ........................................................................................ 107 Intel® ICH10 DMA Controller ............................................................................... 112 DMA Request Assertion through LDRQ# ................................................................ 115 Coprocessor Error Timing Diagram ....................................................................... 140 TCO Legacy/Compatible Mode SMBus Configuration ................................................ 169 Advanced TCO Intel® ME SMBus/SMLink Configuration............................................ 171 Advanced TCO BMC Mode SMBus/SMLink Configuration ........................................... 172 Serial Post over GPIO Reference Circuit ................................................................. 174 SATA Power States ............................................................................................. 181 Flow for Port Enable / Device Present Bits.............................................................. 183 Serial Data transmitted over the SGPIO Interface ................................................... 188 USB Legacy Keyboard Flow Diagram ..................................................................... 198 Intel® ICH10-USB Port Connections Default Six and Six Configuration ...................... 206 Intel® ICH10-USB Port Connections Eight and Four Configuration ............................ 206 Flash Partition Boundary ..................................................................................... 231 Flash Descriptor Sections .................................................................................... 232 Intel® ICH10 Ballout (Top view–Left Side) ............................................................. 244 Intel® ICH10 Ballout (Top view–Right Side) ........................................................... 245 Intel® ICH10 Package (Top View)......................................................................... 253 Intel® ICH10 Package (Bottom View).................................................................... 254 Intel® ICH10 Package (Side View)........................................................................ 254 Clock Timing...................................................................................................... 280 Valid Delay from Rising Clock Edge ....................................................................... 280 Setup and Hold Times......................................................................................... 281 Float Delay........................................................................................................ 281 Pulse Width ....................................................................................................... 281 Output Enable Delay........................................................................................... 281 USB Rise and Fall Times ...................................................................................... 282 USB Jitter ......................................................................................................... 282 USB EOP Width .................................................................................................. 282 SMBus Transaction ............................................................................................. 283 SMBus Timeout.................................................................................................. 283 SPI Timings ....................................................................................................... 284 Intel® High Definition Audio Input and Output Timings ............................................ 284 Power Sequencing and Reset Signal Timings .......................................................... 285 G3 (Mechanical Off) to S0 Timings........................................................................ 286 S0 to S1 to S0 Timings ....................................................................................... 287 S0 to S5 to S0 Timings ....................................................................................... 287 C0 to C2 to C0 Timings ....................................................................................... 288 C0 to C3 to C0 Timings ....................................................................................... 288 C0 to C4 to C0 Timings ....................................................................................... 289 Sleep control signal relationship - Host boots and Intel Management Engine off .......... 290 Sleep control signal relationship - Host and Intel Management Engine boot after G3 ............................................................................................................ 290 Sleep control signal relationship - Host stays in S5 and Intel Management Engine boots after G3 ......................................................................................... 291 S4, S5/M1 to S0/M0 ........................................................................................... 291 S0 to S3/S4/S5 and G3 Timings ........................................................................... 291 24 Datasheet Tables 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 3-1 3-2 3-3 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 Industry Specifications ......................................................................................... 33 PCI Devices and Functions .................................................................................... 37 Intel® ICH10 Components .................................................................................... 44 Direct Media Interface Signals ............................................................................... 47 PCI Express* Signals............................................................................................ 48 LAN Connect Interface Signals ............................................................................... 48 Gigabit LAN Connect Interface Signals .................................................................... 49 Firmware Hub Interface Signals ............................................................................. 50 PCI Interface Signals............................................................................................ 50 Serial ATA Interface Signals .................................................................................. 52 LPC Interface Signals ........................................................................................... 55 Interrupt Signals ................................................................................................. 55 USB Interface Signals........................................................................................... 56 Power Management Interface Signals ..................................................................... 58 Processor Interface Signals ................................................................................... 61 SMBus Interface Signals ....................................................................................... 62 System Management Interface Signals ................................................................... 63 Real Time Clock Interface ..................................................................................... 64 Other Clocks ....................................................................................................... 65 Miscellaneous Signals ........................................................................................... 65 Intel® High Definition Audio Link Signals ................................................................ 66 Serial Peripheral Interface (SPI) Signals.................................................................. 67 Controller Link Signals.......................................................................................... 68 Intel® Quiet System Technology Signals ................................................................ 68 JTAG Signals ....................................................................................................... 69 General Purpose I/O Signals.................................................................................. 70 Power and Ground Signals .................................................................................... 73 Functional Strap Definitions................................................................................... 75 Integrated Pull-Up and Pull-Down Resistors ............................................................. 81 Power Plane and States for Output and I/O Signals for Configurations......................... 83 Power Plane for Input Signals for Configurations ...................................................... 88 Intel® ICH10 and System Clock Domains ................................................................ 91 PCI Bridge Initiator Cycle Types............................................................................. 93 Type 1 Address Format......................................................................................... 96 MSI versus PCI IRQ Actions................................................................................... 98 LAN Mode Support ............................................................................................. 103 LPC Cycle Types Supported ................................................................................. 108 Start Field Bit Definitions .................................................................................... 108 Cycle Type Bit Definitions ................................................................................... 109 Transfer Size Bit Definition.................................................................................. 109 SYNC Bit Definition ............................................................................................ 110 DMA Transfer Size ............................................................................................. 114 Address Shifting in 16-Bit I/O DMA Transfers......................................................... 114 Counter Operating Modes ................................................................................... 119 Interrupt Controller Core Connections................................................................... 121 Interrupt Status Registers................................................................................... 122 Content of Interrupt Vector Byte .......................................................................... 122 APIC Interrupt Mapping1 .................................................................................... 128 Interrupt Message Address Format....................................................................... 130 Interrupt Message Data Format ........................................................................... 131 Stop Frame Explanation...................................................................................... 133 Data Frame Format ............................................................................................ 134 Configuration Bits Reset by RTCRST# Assertion ..................................................... 137 INIT# Going Active ............................................................................................ 139 NMI Sources ..................................................................................................... 140 DP Signal Differences ......................................................................................... 141 General Power States for Systems Using Intel® ICH10............................................ 143 State Transition Rules for Intel® ICH10 ................................................................ 144 System Power Plane........................................................................................... 145 Causes of SMI# and SCI ..................................................................................... 146 Break Events..................................................................................................... 149 Sleep Types ...................................................................................................... 151 Causes of Wake Events....................................................................................... 152 GPI Wake Events ............................................................................................... 153 Transitions Due to Power Failure .......................................................................... 154 Datasheet 25 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 5-55 5-56 5-57 5-58 5-59 5-60 5-61 5-62 6-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 9-1 9-2 9-3 9-4 10-1 11-1 12-1 12-2 13-1 13-2 13-3 13-4 13-5 Transitions Due to Power Button .......................................................................... 155 Transitions Due to RI# Signal .............................................................................. 157 Write Only Registers with Read Paths in ALT Access Mode........................................ 159 PIC Reserved Bits Return Values .......................................................................... 161 Register Write Accesses in ALT Access Mode .......................................................... 161 Intel® ICH10 Clock Inputs ................................................................................... 164 Causes of Host and Global Resets ......................................................................... 166 Event Transitions that Cause Messages ................................................................. 170 Multi-activity LED message type ........................................................................... 187 Legacy Replacement Routing ............................................................................... 190 Bits Maintained in Low Power States ..................................................................... 197 USB Legacy Keyboard State Transitions ................................................................ 198 UHCI vs. EHCI ................................................................................................... 201 Debug Port Behavior........................................................................................... 210 I2C Block Read................................................................................................... 218 Enable for SMBALERT# ....................................................................................... 221 Enables for SMBus Slave Write and SMBus Host Events ........................................... 221 Enables for the Host Notify Command ................................................................... 221 Slave Write Registers.......................................................................................... 223 Command Types ................................................................................................ 223 Slave Read Cycle Format..................................................................................... 224 Data Values for Slave Read Registers.................................................................... 225 Host Notify Format ............................................................................................. 227 Region Size versus Erase Granularity of Flash Components ...................................... 231 Region Access Control Table ................................................................................ 233 Hardware Sequencing Commands and Opcode Requirements ................................... 236 Flash Protection Mechanism Summary .................................................................. 237 Recommended Pinout for 8-Pin Serial Flash Device ................................................. 238 Recommended Pinout for 16-Pin Serial Flash Device ............................................... 239 Intel® ICH10 Ballout by Signal Name ................................................................... 246 Intel® ICH10 Absolute Maximum Ratings............................................................... 255 DC Current Characteristics (Consumer Only)1 ........................................................ 255 DC Current Characteristics (Corporate Only) .......................................................... 257 DC Characteristic Input Signal Association ............................................................. 258 DC Input Characteristics ..................................................................................... 260 DC Characteristic Output Signal Association ........................................................... 262 DC Output Characteristics ................................................................................... 264 Other DC Characteristics ..................................................................................... 266 Clock Timings .................................................................................................... 268 PCI Interface Timing........................................................................................... 269 Universal Serial Bus Timing ................................................................................. 270 SATA Interface Timings....................................................................................... 271 SMBus Timing.................................................................................................... 272 Intel® High Definition Audio Timing ...................................................................... 272 LPC Timing ........................................................................................................ 273 Miscellaneous Timings......................................................................................... 273 SPI Timings (20 MHz) ......................................................................................... 273 SPI Timings (33 MHz) ......................................................................................... 274 SST Timings ...................................................................................................... 274 PECI Timings ..................................................................................................... 275 Power Sequencing and Reset Signal Timings .......................................................... 275 Power Management Timings ................................................................................ 277 PCI Devices and Functions................................................................................... 294 Fixed I/O Ranges Decoded by Intel® ICH10 ........................................................... 296 Variable I/O Decode Ranges ................................................................................ 298 Memory Decode Ranges from Processor Perspective ............................................... 299 Chipset Configuration Register Memory Map (Memory Space)................................... 303 PCI Bridge Register Address Map (PCI-PCI—D30:F0)............................................... 355 Gigabit LAN Configuration Registers Address Map (Gigabit LAN —D25:F0)....................................................................................... 371 Gigabit LAN Base Address A Registers Address Map (Gigabit LAN— D25:F0)....................................................................................... 384 LPC Interface PCI Register Address Map (LPC I/F—D31:F0)...................................... 387 DMA Registers ................................................................................................... 411 PIC Registers (LPC I/F—D31:F0) .......................................................................... 424 APIC Direct Registers (LPC I/F—D31:F0) ............................................................... 433 APIC Indirect Registers (LPC I/F—D31:F0)............................................................. 433 26 Datasheet 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 14-1 14-2 14-3 14-4 14-5 15-1 15-2 16-1 16-2 16-3 16-4 17-1 17-2 17-3 17-4 18-1 18-2 19-1 19-2 20-1 21-1 22-1 22-2 23-1 23-2 RTC I/O Registers .............................................................................................. 439 RTC (Standard) RAM Bank .................................................................................. 440 Processor Interface PCI Register Address Map (LPC I/F—D31:F0) ............................. 444 Power Management PCI Register Address Map (PM—D31:F0)................................... 447 APM Register Map .............................................................................................. 460 ACPI and Legacy I/O Register Map ....................................................................... 461 TCO I/O Register Address Map............................................................................. 483 Registers to Control GPIO Address Map................................................................. 491 SATA Controller PCI Register Address Map (SATA–D31:F2)...................................... 501 Bus Master IDE I/O Register Address Map ............................................................. 528 AHCI Register Address Map ................................................................................. 536 Generic Host Controller Register Address Map........................................................ 537 Port [5:0] DMA Register Address Map ................................................................... 545 SATA Controller PCI Register Address Map (SATA–D31:F5)...................................... 563 Bus Master IDE I/O Register Address Map ............................................................. 580 UHCI Controller PCI Configuration Map ................................................................. 589 UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)............................................................... 589 USB I/O Registers.............................................................................................. 602 Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation ............. 605 USB EHCI PCI Register Address Map (USB EHCI—D29:F7, D26:F7) .......................... 611 Enhanced Host Controller Capability Registers ....................................................... 631 Enhanced Host Controller Operational Register Address Map .................................... 635 Debug Port Register Address Map ........................................................................ 649 Intel® High Definition Audio PCI Register Address Map (Intel® High Definition Audio D27:F0) .................................................................. 653 Intel® High Definition Audio PCI Register Address Map (Intel® High Definition Audio D27:F0) .................................................................. 675 SMBus Controller PCI Register Address Map (SMBus—D31:F3)................................. 703 SMBus I/O and Memory Mapped I/O Register Address Map...................................... 710 PCI Express* Configuration Registers Address Map (PCI Express—D28:F0/F1/F2/F3/F4/F5) ............................................................... 721 Memory-Mapped Registers .................................................................................. 767 Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers)....................................................... 777 Gigabit LAN SPI Flash Program Register Address Map (GbE LAN Memory Mapped Configuration Registers) ............................................... 815 Thermal Sensor Register Address Map .................................................................. 829 Thermal Memory Mapped Configuration Register Address Map ................................. 838 Datasheet 27 Revision History Revision Number -001 • • • -002 • -003 • Initial release. Added Intel ICH10 corporate components Added Notes 12 and 13 to Table 2-23, updated signal description for VccGLAN1_5 and VccGLAN3_3 in Table 2-24, and updated GPIO33 and GPIO49 strap definitions in Table 2-25. Updated register descriptions for USBIR1 (Section 10.1.82), USBIR2 (Section 10.1.83), and EHCIIR1 (Section 17.1.30) Updated Intel ICH10 corporate components table Description Revision Date June 2008 September 2008 October 2008 28 Datasheet Intel® ICH10 Features Direct Media Interface — 10 Gb/s each direction, full duplex — Transparent to software PCI Express* — 6 PCI Express root ports — Supports PCI Express 1.1 — Ports 1-4 can be statically configured as 4x1, or 1x4 — Support for full 2.5 Gb/s bandwidth in each direction per x1 lane — Module based Hot-Plug supported (e.g., ExpressCard*) PCI Bus Interface — Supports PCI Rev 2.3 Specification at 33 MHz — Four available PCI REQ/GNT pairs — Support for 64-bit addressing on PCI using DAC protocol Integrated Serial ATA Host Controller — Up to six SATA ports — Data transfer rates up to 3.0 Gb/s (300 MB/s). — Integrated AHCI controller External SATA support — Port Disable Capability Intel® Matrix Storage Technology — Configures the ICH10 SATA controller as a RAID controller supporting RAID 0/1/5/10 Intel® High Definition Audio Interface — PCI Express endpoint — Independent Bus Master logic for eight general purpose streams: four input and four output — Support four external Codecs — Supports variable length stream slots — Supports multichannel, 32-bit sample depth, 192 kHz sample rate output — Provides mic array support — Allows for non-48 kHz sampling output — Support for ACPI Device States — Low Voltage Mode Intel® Quiet System Technology — Four TACH signals and three PWM signals — Improved algorithms for better performance Simple Serial Transport (SST) 1.0 Bus and Platform Environment Control Interface (PECI) USB 2.0 — Six UHCI Host Controllers, supporting up to twelve external ports — Two EHCI Host Controllers, supporting up to twelve external ports — Two Configuration Options for EHCI Controllers 6+6 and 8+4 — Per-Port-Disable Capability — Includes up to two USB 2.0 High-speed Debug Ports — Supports wake-up from sleeping states S1-S4 Supports legacy Keyboard/Mouse software Integrated Gigabit LAN Controller — Integrated ASF Management Controller — Network security with System Defense — Supports IEEE 802.3 — LAN Connect Interface (LCI) and Gigabit LAN Connect Interface (GLCI) — 10/100/1000 Mbps Ethernet Support — Jumbo Frame Support Intel® Active Management Technology with System Defense (Corporate Only) — Network Outbreak Containment Heuristics Intel® I/O Virtualization (VT-d) Support Intel® Trusted Execution Technology (Intel TXT) Support (Corporate Only) Power Management Logic — Supports ACPI 3.0b — ACPI-defined power states (C1, C2, C3, C4, S1, S3-S5) — ACPI Power Management Timer — SMI# generation — All registers readable/restorable for proper resume from 0 V suspend states — Support for APM-based legacy power management for non-ACPI implementations External Glue Integration — Integrated Pull-up, Pull-down and Series Termination resistors on processor I/F — Integrated Pull-down and Series resistors on USB Enhanced DMA Controller — Two cascaded 8237 DMA controllers — Supports LPC DMA Datasheet 29 SMBus — Faster speed, up to 100 kbps — Flexible SMBus/SMLink architecture to optimize for ASF — Provides independent manageability bus through SMLink interface — Supports SMBus 2.0 Specification — Host interface allows processor to communicate via SMBus — Slave interface allows an internal or external Microcontroller to access system resources — Compatible with most two-wire components that are also I2C compatible High Precision Event Timers — Advanced operating system interrupt scheduling Timers Based on 82C54 — System timer, Refresh request, Speaker tone output Real-Time Clock — 256 Byte battery-backed CMOS RAM — Integrated oscillator components — Lower Power DC/DC Converter implementation System TCO Reduction Circuits — Timers to generate SMI# and Reset upon detection of system hang — Timers to detect improper processor reset — Integrated processor frequency strap logic — Supports ability to disable external devices Interrupt Controller — Supports up to eight PCI interrupt pins — Supports PCI 2.3 Message Signaled Interrupts — Two cascaded 82C59 with 15 interrupts — Integrated I/O APIC capability with 24 interrupts — Supports Processor System Bus interrupt delivery 1.1 V operation with 1.5 and 3.3 V I/O — 5 V tolerant buffers on PCI, USB and selected Legacy signals 1.1 V Core Voltage Five Integrated Voltage Regulators for different power rails Firmware Hub I/F supports BIOS Memory size up to 8 MBytes Serial Peripheral Interface (SPI) — Supports up to two SPI devices — Supports 20 MHz and 33 MHz SPI devices — NEW: Dual erase support Low Pin Count (LPC) I/F — Supports two Master/DMA devices. — Support for Security Device (Trusted Platform Module) connected to LPC. GPIO — TTL, Open-Drain, Inversion — GPIO lock down NEW: JTAG (Corporate Only) — Boundary Scan for testing during board manufacturing Package 31x31 mm 676 mBGA Note: Not all features are available on all ICH10 components. See Section 1.3 for more details. 30 Datasheet Intel® ICH10 Configuration DMI (To (G)MCH) USB 2.0 (Supports 12 USB ports Dual EHCI Controller) Power Management Clock Generators SATA (6 ports) Intel® High Definition Audio Codec(s) Intel® ICH10 System Management (TCO) SMBus 2.0/I2C PCI Bus PCI Express* x1 Intel® Gigabit Ethernet Phy GLCI LCI SPI BIOS Flash S L O T JTAG* (Corporate Only) GPIO LPC I/F Other ASICs (Optional) S L O T ... Super I/O TPM (Optional) Firmware Hub §§ Datasheet 31 32 Datasheet Introduction 1 Introduction This document is intended for Original Equipment Manufacturers and BIOS vendors creating Intel® I/O Controller Hub 10 (ICH10) Family based products. This document is for the following components: Consumer Family • Intel® 82801JIB ICH10 Consumer Base (ICH10) • Intel® 82801JIR ICH10 RAID (ICH10R) Corporate Family • Intel® 82801JD ICH10 Corporate Base (ICH10D) • Intel® 82801JDO ICH10 Digital Office (ICH10DO) Section 1.3 provides high-level feature differences for the ICH10 Family components. Note: Throughout this document, ICH10 is used as a general ICH10 term and refers to the Intel 82801JIB ICH10, Intel 82801JIR ICH10R, Intel 82801JD ICH10D, Intel 82801JDO ICH10DO components, unless specifically noted otherwise. Throughout this document, the term “Consumer Only” refers to information that is for the Intel 82801JIB ICH10 and Intel 82801JIR ICH10R, unless specifically noted otherwise. The term “Corporate Only” refers to information that is for the Intel 82801JD ICH10D and 82801JDO ICH10DO, unless specifically noted otherwise. Note: 1.1 About This Manual This manual assumes a working knowledge of the vocabulary and principles of PCI Express*, USB, AHCI, SATA, Intel® High Definition Audio (Intel® HD Audio), SMBus, PCI, ACPI, and LPC. Although some details of these features are described within this manual, refer to the individual industry specifications listed in Table 1-1 for the complete details. Table 1-1. Industry Specifications Specification PCI Express* Base Specification, Revision 1.1 Low Pin Count Interface Specification, Revision 1.1 (LPC) System Management Bus Specification, Version 2.0 (SMBus) PCI Local Bus Specification, Revision 2.3 (PCI) PCI Power Management Specification, Revision 1.1 Universal Serial Bus Specification (USB), Revision 2.0 Advanced Configuration and Power Interface, Version 3.0b (ACPI) Universal Host Controller Interface, Revision 1.1 (UHCI) Location http://www.pcisig.com/specifications http://developer.intel.com/design/chipsets/ industry/lpc.htm http://www.smbus.org/specs/ http://www.pcisig.com/specifications http://www.pcisig.com/specifications http://www.usb.org/developers/docs http://www.acpi.info/spec.htm http://developer.intel.com/design/USB/ UHCI11D.htm DatasheetCDI / IBL #: 373635 33 Introduction Table 1-1. Industry Specifications Specification Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (EHCI) Serial ATA Specification, Revision 2.5 Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 Serial ATA II Cables and Connectors Volume 2 Gold Alert Standard Format Specification, Version 1.03 IEEE 802.3 Fast Ethernet AT Attachment - 6 with Packet Interface (ATA/ ATAPI - 6) IA-PC HPET (High Precision Event Timers) Specification, Revision 0.98a TPM Specification 1.02, Level 2 Revision 103 Intel® I/O Controller Hub 10 (ICH10) Family Specification Update Intel® I/O Controller Hub 10 (ICH10) Family Thermal and Mechanical Design Guidelines ® Location http://developer.intel.com/technology/usb/ ehcispec.htm http://www.serialata.org/specifications.asp http://www.serialata.org/specifications.asp http://www.serialata.org/specifications.asp http://www.dmtf.org/standards/asf http://standards.ieee.org/getieee802/ http://T13.org (T13 1410D) http://www.intel.com/hardwaredesign/ hpetspec.htm http://www.trustedcomputinggroup.org/specs/ TPM http://www.intel.com/design/chipsets/ specupdt/319974.pdf http://www.intel.com/design/chipsets/ designex/319975.pdf Intel Users: http://esales.intel.com Search for “ICH10” External Users: http://www.intel.com/ibl Chipsets > South Bridges/IO Controller Hub > ICH Family > ICH10 > Technical Intel Users: http://esales.intel.com Search for “ICH10” External Users: http://www.intel.com/ibl Chipsets > South Bridges/IO Controller Hub > ICH Family > ICH10 > Technical Intel ICH10 EDS Spec. Update, Latest Revision Intel® ICH10 Chipset Mechanical Ballout File, Latest Revision Intel® ICH10 Family XOR Chains In-Circuit Tester Package, Revision TBD Intel ICH10 IBIS Model, Revision Latest Revision ® 34 DatasheetCDI / IBL #: 373635 Introduction Chapter 1. Introduction Chapter 1 introduces the ICH10 and provides information on manual organization and gives a general overview of the ICH10. Chapter 2. Signal Description Chapter 2 provides a block diagram of the ICH10 and a detailed description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open-drain, etc.) of all signals. Chapter 3. Intel® ICH10 Pin States Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. Chapter 4. Intel® ICH10 and System Clock Domains Chapter 4 provides a list of each clock domain associated with the ICH10 in an ICH10 based system. Chapter 5. Functional Description Chapter 5 provides a detailed description of the functions in the ICH10. All PCI buses, devices and functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8, D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the ICH10’s external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration. Chapter 6. Ballout Definition Chapter 6 provides a table of each signal and its ball assignment in the 676-mBGA package. Chapter 7. Package Information Chapter 7 provides drawings of the physical dimensions and characteristics of the 676mBGA package. Chapter 8. Electrical Characteristics Chapter 8 provides all AC and DC characteristics including detailed timing diagrams. Chapter 9. Register and Memory Mappings Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory ranges decoded by the ICH10. Chapter 10. Chipset Configuration Registers Chapter 10 provides a detailed description of all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express*). It contains the root complex register block, which describes the behavior of the upstream internal link. Chapter 11. PCI-to-PCI Bridge Registers Chapter 11 provides a detailed description of all registers that reside in the PCI-to-PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0). Chapter 12. Integrated LAN Controller Registers Chapter 12 provides a detailed description of all registers that reside in the ICH10’s integrated LAN controller. The integrated LAN Controller resides at Device 25, Function 0 (D25:F0). DatasheetCDI / IBL #: 373635 35 Introduction Chapter 13. LPC Bridge Registers Chapter 13 provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the ICH10 including DMA, Timers, Interrupts, Processor Interface, GPIO, Power Management, System Management and RTC. Chapter 14. SATA Controller Registers Chapter 14 provides a detailed description of all registers that reside in the SATA controller #1. This controller resides at Device 31, Function 2 (D31:F2). Chapter 15. SATA Controller Registers Chapter 15 provides a detailed description of all registers that reside in the SATA controller #2. This controller resides at Device 31, Function 5 (D31:F5). Chapter 16. UHCI Controller Registers Chapter 16 provides a detailed description of all registers that reside in the six UHCI host controllers. These controllers reside at Device 29, Functions 0, 1, 2, and 3 (D29:F0/F1/F2/F3) and Device 26, Function 0, 1 and 2 (D26:F0/F1/F2). Chapter 17. EHCI Controller Registers Chapter 17 provides a detailed description of all registers that reside in the two EHCI host controllers. These controllers reside at Device 29, Function 7 (D29:F7) and Device 26, Function 7 (D26:F7). Chapter 18. SMBus Controller Registers Chapter 19 provides a detailed description of all registers that reside in the SMBus controller. This controller resides at Device 31, Function 3 (D31:F3). Chapter 19. Intel® High Definition Audio Controller Registers Chapter 18 provides a detailed description of all registers that reside in the Intel High Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 20. PCI Express* Port Controller Registers Chapter 20 provides a detailed description of all registers that reside in the PCI Express controller. This controller resides at Device 28, Functions 0 to 5 (D30:F0-F5). Chapter 21. High Precision Event Timers Registers Chapter 21 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. Chapter 22. Serial Peripheral Interface Registers Chapter 22 provides a detailed description of all registers that reside in the SPI memory mapped register space. Chapter 23. Thermal Sensors Chapter 23 provides a detailed description of all registers that reside in the thermal sensors PCI configuration space. The registers reside at Device 31, Function 6 (D31:F6). 36 DatasheetCDI / IBL #: 373635 Introduction 1.2 Overview The ICH10 provides extensive I/O support. Functions and capabilities include: • PCI Express* Base Specification, Revision 1.1 support • PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations (supports up to four Req/Gnt pairs). • ACPI Power Management Logic Support, Revision 3.0b • Enhanced DMA controller, interrupt controller, and timer functions • Integrated Serial ATA host controllers with independent DMA operation on up to six ports. • USB host interface with support for up to twelve USB ports; six UHCI host controllers; two EHCI high-speed USB 2.0 Host controllers • Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense • System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices • Supports Intel® High Definition Audio • Supports Intel® Matrix Storage Technology • Supports Intel® Active Management Technology (Corporate Only) • Supports Intel® Virtualization Technology for Directed I/O • Supports Intel® Trusted Execution Technology (Corporate Only) • Low Pin Count (LPC) interface • Firmware Hub (FWH) interface support • Serial Peripheral Interface (SPI) support • Intel® Quiet System Technology • Integrated TPM 1.2 (Corporate Only) • JTAG Boundary Scan support (Corporate Only) The Intel ICH10 incorporates a variety of PCI devices and functions, as shown in Table 1-2. They are divided into seven logical devices. The first is the DMI-To-PCI bridge (Device 30). The second device (Device 31) contains most of the standard PCI functions that always existed in the PCI-to-ISA bridges (South Bridges), such as the Intel PIIX4. The third and fourth (Device 29 and Device 26) are the USB host controller devices. The fifth (Device 28) is PCI Express device. The sixth (Device 27) is the HD Audio controller device, and the seventh (Device 25) is the Gigabit Ethernet controller device. Table 1-2. PCI Devices and Functions (Sheet 1 of 2) Bus:Device:Function Bus 0:Device 30:Function 0 Bus 0:Device 31:Function 0 Bus 0:Device 31:Function 2 Bus 0:Device 31:Function 5 Bus 0:Device 31:Function 6 Bus 0:Device 31:Function 3 Bus 0:Device 29:Function 0 DMI-to-PCI Bridge LPC Controller1 SATA Controller #1 SATA Controller #23 Thermal Subsystem SMBus Controller USB FS/LS UHCI Controller #1 Function Description DatasheetCDI / IBL #: 373635 37 Introduction Table 1-2. PCI Devices and Functions (Sheet 2 of 2) Bus:Device:Function Bus 0:Device 29:Function 1 Bus 0:Device 29:Function 2 Bus 0:Device 29:Function 3 Bus 0:Device 29:Function 7 Bus 0:Device 26:Function 0 Bus 0:Device 26:Function 1 Bus 0:Device 26:Function 2 Bus 0:Device 26:Fucntion 7 Bus 0:Device 28:Function 0 Bus 0:Device 28:Function 1 Bus 0:Device 28:Function 2 Bus 0:Device 28:Function 3 Bus 0:Device 28:Function 4 Bus 0:Device 28:Function 5 Bus 0:Device 27:Function 0 Bus 0:Device 25:Function 0 Function Description USB FS/LS UHCI Controller #2 USB FS/LS UHCI Controller #3 USB FS/LS UHCI Controller #62 USB HS EHCI Controller #1 USB FS/LS UHCI Controller #4 USB FS/LS UHCI Controller #5 USB FS/LS UHCI Controller #62 USB HS EHCI Controller #2 PCI Express* Port 1 PCI Express Port 2 PCI Express Port 3 PCI Express Port 4 PCI Express Port 5 PCI Express Port 6 Intel® High Definition Audio Controller Gigabit Ethernet Controller NOTES: 1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA 2. Device 26:Function 2 maybe configured as Device 29:Function 3 during BIOS Post. 3. SATA Controller 2 is only visible when D31:F2 CC.SCC=01h. 38 DatasheetCDI / IBL #: 373635 Introduction 1.2.1 Capability Overview The following sub-sections provide an overview of the ICH10 capabilities. Direct Media Interface (DMI) Direct Media Interface (DMI) is the chip-to-chip connection between the Memory Controller Hub / Graphics Memory Controller Hub ((G)MCH) and I/O Controller Hub 10 (ICH10). This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally. PCI Express* Interface The ICH10 provides up to 6 PCI Express Root Ports, supporting the PCI Express Base Specification, Revision 1.1. Each Root Port supports 2.5 GB/s bandwidth in each direction (5 GB/s concurrent). PCI Express Root Ports 1–4 can be statically configured as four x1 Ports or ganged together to form one x4 port. Ports 5 and 6 can only be used as two x1 ports. Note: The integrated Gigabit Ethernet controllers data lines for 1000 MB/s speed are multiplexed with PCI Express* Root Port 6 and therefore unavailable if a Gigabit Ethernet PHY is connected. The use of a 10/100 MB/s PHY does not consume PCI Express Root Port 6 and therefore the port is available to be utilized as a x1 Port. Serial ATA (SATA) Controller The ICH10 has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 3.0 GB/s (300 MB/s). The SATA controller contains two modes of operation – a legacy mode using I/O space, and an AHCI mode using memory space. Software that uses legacy mode will not have AHCI capabilities. The ICH10 supports the Serial ATA Specification, Revision 1.0a. The ICH10 also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements). AHCI The ICH10 provides hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. See Section 1.3 for details on component feature availability. Intel® Matrix Storage Technology The ICH10 provides support for Intel® Matrix Storage Technology, providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The industry-leading RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6 SATA ports of ICH10. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare support, SMART alerting, and RAID 0 auto replace. Software components include an Option ROM for pre-boot configuration and DatasheetCDI / IBL #: 373635 39 Introduction boot functionality, a Microsoft Windows* compatible driver, and a user interface for configuration and management of the RAID capability of ICH10. See Section 1.3 for details on component feature availability. PCI Interface The ICH10 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH10 integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal ICH10 requests. This allows for combinations of up to four PCI down devices and PCI slots. Low Pin Count (LPC) Interface The ICH10 implements an LPC Interface as described in the LPC 1.1 Specification. The Low Pin Count (LPC) bridge function of the ICH10 resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC. Serial Peripheral Interface (SPI) The ICH10 implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI flash device can be used as a replacement for the FWH, and is required to support Gigabit Ethernet, Intel® Active Management Technology, and integrated Intel® Quiet System Technology. The ICH10 supports up to two SPI flash devices with speed up to 33 MHz using two chip select pins. Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-bybyte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support fast Type-F transfers. Channel 4 is reserved as a generic bus master request. The ICH10 supports LPC DMA, which is similar to ISA DMA, through the ICH10’s DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for these three counters. The ICH10 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the ICH10 supports a serial interrupt scheme. All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform. Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in the previous section, the ICH10 incorporates the Advanced Programmable Interrupt Controller (APIC). 40 DatasheetCDI / IBL #: 373635 Introduction Universal Serial Bus (USB) Controllers The ICH10 contains up to two Enhanced Host Controller Interface (EHCI) host controllers that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The ICH10 also contains up to six Universal Host Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling. The ICH10 supports up to twelve USB 2.0 ports. All twelve ports are high-speed, fullspeed, and low-speed capable. ICH10’s port-routing logic determines whether a USB port is controlled by one of the UHCI or EHCI controllers. See Section 5.18 and Section 5.19 for details. Gigabit Ethernet Controller The Gigabit Ethernet Controller provides a system interface via a PCI function. The controller provides a full memory-mapped or IO mapped interface along with a 64 bit address master support for systems using more than 4 GB of physical memory and DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its bus master capabilities enable the component to process high-level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large configurable transmit and receive FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS). The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. See Section 5.3 for details. RTC The ICH10 contains a Motorola MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a 3 V battery. The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information. The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. GPIO Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on ICH10 configuration. Enhanced Power Management The ICH10’s power management functions include enhanced clock control and various low-power (suspend) states (e.g., Suspend-to-RAM and Suspend-to-Disk). A hardwarebased thermal management circuit permits software-independent entrance to lowpower states. The ICH10 contains full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 3.0a. DatasheetCDI / IBL #: 373635 41 Introduction Intel® Active Management Technology (Intel® AMT) (Not available on all ICH10 components) Intel® Active Management Technology is the next generation of client manageability via the wired network. Intel AMT is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research. With the new implementation of System Defense in ICH10, the advanced manageability feature set of Intel AMT is further enhanced. See Section 1.3 for details on component feature availability. Manageability In addition to Intel AMT, ICH10 integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller. • TCO Timer. The ICH10’s integrated programmable TCO timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock. • Processor Present Indicator. The ICH10 looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the ICH10 will reboot the system. • ECC Error Reporting. When detecting an ECC error, the host controller has the ability to send one of several messages to the ICH10. The host controller can instruct the ICH10 to generate either an SMI#, NMI, SERR#, or TCO interrupt. • Function Disable. The ICH10 provides the ability to disable the following integrated functions: LAN, USB, LPC, Intel HD Audio, SATA, PCI Express or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disabled functions. • Intruder Detect. The ICH10 provides an input signal (INTRUDER#) that can be attached to a switch that is activated by the system case being opened. The ICH10 can be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal. System Management Bus (SMBus 2.0) The ICH10 contains an SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented. The ICH10’s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the ICH10 supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. ICH10’s SMBus also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus devices. 42 DatasheetCDI / IBL #: 373635 Introduction Intel® High Definition Audio Controller The Intel® High Definition Audio Specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. The ICH10 Intel® HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V or 1.5 V. With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel® HD Audio controller provides audio quality that can deliver CE levels of audio experience. On the input side, the ICH10 adds support for an array of microphones. Intel® Quiet System Technology (Intel® QST) The ICH10 integrates four fan speed sensors (four TACH signals) and 3 fan speed controllers (three Pulse Width Modulator signals), which enables monitoring and controlling up to four fans on the system. With the new implementation of the singlewire Simple Serial Transport (SST) 1.0 bus and Platform Environmental Control Interface (PECI), the ICH10 provides an easy way to connect to SST-based thermal sensors and access the processor thermal data. In addition, coupled with the new sophisticated fan speed control algorithms, Intel® QST provides effective thermal and acoustic management for the platform. Note: Intel® Quiet System Technology functionality requires a correctly configured system, including an appropriate (G)MCH with Intel ME, Intel ME firmware, and system BIOS support. Intel® Trusted Platform Module (Corporate Only) The Intel Trusted Platform Module (Intel® TPM) implementation consists of firmware, Intel® Management Engine resources and dedicated hardware within the ICH and the (G)MCH. The Intel TPM supports all requirements of the TPM Specification Version 1.2, Revision 103, as published by the Trusted Computing Group. The Intel TPM behaves like a discrete TPM device, and can support third party applications, as well as Microsoft* specific functionality in the Windows Vista* OS. Note: Intel TPM functionality requires a correctly configured system, including an appropriate (G)MCH with Intel Management Engine firmware, ICH10 and SPI Flash. JTAG Boundary-Scan (Corporate Only) ICH10 adds the industry standard JTAG interface and enables Boundary-Scan in place of the XOR chains used in previous generations of the ICH. Boundary-Scan can be used to ensure device connectivity during the board manufacturing process. The JTAG interface allows system manufacturers to improve efficiency by using industry available tools to test the ICH on an assembled board. Since JTAG is a serial interface, it eliminates the need to create probe points for every pin in an XOR chain. This eases pin breakout and trace routing and simplifies the interface between the system and a bedof-nails tester. Note: Contact your local Intel Field Sales Representative for additional information about JTAG usage on ICH10. DatasheetCDI / IBL #: 373635 43 Introduction 1.3 Intel® ICH10 Family High-Level Component Differences Intel® ICH10 Components Feature Consumer ICH10 ICH10 Consumer Base No No 3 Table 1-3. Corporate ICH10D ICH10 Corporate Base No Yes No Yes No Yes No No ICH10DO ICH10 Digital Office No Yes Yes No Yes Yes No No ICH10R ICH10 RAID Yes Yes Yes No No No Yes4 Yes Component Name Intel® Turbo Memory Support Intel® Matrix Storage Technology Intel® Active Management Technology Release 5.0 AHCI RAID 0/1/5/10 Support Basic Professional No No No No Yes4 Yes Intel® Trusted Platform Module (Intel® TPM) Wake on VoIP Intel® Viiv™ Processor Technology Support Intel® Remote Wake Technology (Intel® RWT) Support JTAG Boundary Scan NOTES: 1. 2. Yes No Yes No No Yes No Yes 3. 4. 5. ICH10 Consumer Base provides hardware support for AHCI functionality when enabled by appropriate system configuration and software driver. Wake on VoIP support provided by Intel® Remote Wake Technology (Intel® RWT) Support. All components support 6 SATA, 6 PCIe*, and 14 USB ports. Contact your local Intel Field Sales Representative for currently available ICH10 components. Table above shows feature difference between ICH10 components. If a feature is not listed in the table it is considered a Base feature that is included in all components. §§ 44 DatasheetCDI / IBL #: 373635 Signal Description 2 Signal Description This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I O OD O I/OD I/O Input Pin Output Pin Open-drain Output Pin. Bi-directional Input/Open-drain Output Pin. Bi-directional Input / Output Pin. The “Type” for each signal is indicative of the functional operating mode of the signal. Unless otherwise noted in Section 3.2 or Section 3.3, a signal is considered to be in the functional operating mode after RTCRST# deasserts for signals in the RTC well, after RSMRST# deasserts for signals in the suspend well, after PWROK asserts for signals in the core well, and after LAN_RST# deasserts for signals in the LAN well. Datasheet 45 Signal Description Figure 2-1. Intel® ICH10 Interface Signals Block Diagram AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ0# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 GNT0# GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55 SERR# PME# PCICLK PCIRST# PLOCK# A20M# FERR# IGNNE# INIT# INIT3_3V# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD DPSLP# LAN_RSTSYNC GLAN_CLK GLAN_TXP/PETp6; GLAN_TXN/PETn6 GLAN_RXP/PERp6; GLAN_RXN/PERn6 GLAN_COMPO GLAN_COMPI CL_CLK0 ; CL_DATA0 CL_VREF0 CL_RST0# PETp[5:1], PETn[5:1] PERp[5:1], PERn[5:1] GLAN_TXP/PETp6; GLAN_TXN/PETn6 GLAN_RXP/PERp6; GLAN_RXN/PERn6 SATA[5:0]TXP, SATA[5:0]TXN SATA[5:0]RXP, SATA[5:0]RXN SATARBIAS SATARBIAS# SATALED# SATACLKREQ#/GPIO35 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 SATA4GP SATA5GP SCLOCK/GPIO22 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# SLP_S3# SLP_S4# SLP_S5#/GPIO63 † SLP_M# S4_STATE#/GPIO26 PWROK CLPWROK PWRBTN# RI# WAKE# SUS_STAT#/LPCPD/GPIO61† SUSCLK/GPIO62† LAN_RST# VRMPWRGD PLTRST# CK_PWRGD BMBUSY#/GPIO0 STP_PCI#/GPIO15 STP_CPU#/GPIO25 † DRAMPWROK † /GPIO8 DPRSTP# DPRSLPVR / GPIO16 Gigabit LAN Connect Interface Controller Link PCI Express* Interface PCI Interface Serial ATA Interface P rocessor Interface Power Mgnt. SPI_CS0# SPI_CS1#/GPIO58 § SPI_MISO SPI_MOSI SPI_CLK SPI SERIRQ PIRQ[D:A]# PIRQ[H:E]#/GPIO[5:2] USB[11:0]P; USB[11:0]N OC0#/GPIO59; OC1#/GPIO40 OC2#/GPIO41; OC3#/GPIO42 OC4#/GPIO43; OC5#/GPIO29 OC6#/GPIO30; OC7#/GPIO31 OC8#/GPIO44; OC9#/GPIO45 OC10#/GPIO46; OC11#/GPIO47 USBRBIAS USBRBIAS# RTCX1 RTCX2 CLK14 CLK48 SATA_CLKP, SATA_CLKN DMI_CLKP, DMI_CLKN INTVRMEN SPKR SRTCRST#; RTCRST# TP[5:4] TP7 TP6 GPIO72 † / TP0 § LAN100_SLP GPIO[72,49,34,33,32,28, 27,20,18,16,13,12,0] P WM[2:0] TACH0/GPIO17; TACH1/GPIO1 TACH2/GPIO6; TACH3/GPIO7 SST PECI Interrupt Interface Intel® High Definition Audio HDA_RST# HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDIN[3:0] DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP FWH[3:0]/LAD[3:0] FWH4/LFRAME# LAD[3:0]/FWH[3:0] LFRAME#/FWH4 LDRQ0# LDRQ1#/GPIO23 SMBDATA SMBCLK GPIO11/SMBALERT#/JTAGTDO † INTRUDER#; SMLINK[1:0] LINKALERT#/GPIO60 GPIO24/MEM_LED; GPIO10/CPU_MISSING/JTAGTMS † GPIO14/JTAGTDI† GPIO57/TPM_PP/JTAGTCK † SPI_CS1#/GPIO58 § ; WOL_EN/GPIO9 GLAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC GPIO57/TPM_PP/JTAGTCK † GPIO10/CPU_MISSING/JTAGTMS † GPIO14/JTAGTDI† GPIO11/SMBALERT#/JTAGTDO † GPIO60/LINKALERT#/JTAGRST# † USB Direct Media Interface Firmware Hub RTC LPC Interface SMBus Interface Clocks Misc. Signals System Mgnt. General Purpose I/O Fan Speed Control LAN Connect Interface JTAG (Corporate Only) NOTES: 1. § symbol indicates a particular use of a pin is Cunsumer Only. 2. † symbol indicates a particular use of a pin is Corporate Only. 46 Datasheet Signal Description 2.1 Table 2-1. Direct Media Interface (DMI) to Host Controller Direct Media Interface Signals Name DMI0TXP, DMI0TXN DMI0RXP, DMI0RXN DMI1TXP, DMI1TXN DMI1RXP, DMI1RXN DMI2TXP, DMI2TXN DMI2RXP, DMI2RXN DMI3TXP, DMI3TXN DMI3RXP, DMI3RXN DMI_ZCOMP DMI_IRCOMP Type O I O I O I O I I O Description Direct Media Interface Differential Transmit Pair 0 Direct Media Interface Differential Receive Pair 0 Direct Media Interface Differential Transmit Pair 1 Direct Media Interface Differential Receive Pair 1 Direct Media Interface Differential Transmit Pair 2 Direct Media Interface Differential Receive Pair 2 Direct Media Interface Differential Transmit Pair 3 Direct Media Interface Differential Receive Pair 3 Impedance Compensation Input: Determines DMI input impedance. Impedance/Current Compensation Output: Determines DMI output impedance and bias current. Datasheet 47 Signal Description 2.2 Table 2-2. PCI Express* Interface PCI Express* Signals Name PETp1, PETn1 PERp1, PERn1 PETp2, PETn2 PERp2, PERn2 PETp3, PETn3 PERp3, PERn3 PETp4, PETn4 PERp4, PERn4 PETp5, PETn5 PERp5, PERn5 PETp6/ GLAN_TXp, PETn6/ GLAN_TXn PERp6/ GLAN_RXp, PERn6/ GLAN_RXn Type O I O I O I O I O I Description PCI Express* Differential Transmit Pair 1 PCI Express Differential Receive Pair 1 PCI Express Differential Transmit Pair 2 PCI Express Differential Receive Pair 2 PCI Express Differential Transmit Pair 3 PCI Express Differential Receive Pair 3 PCI Express Differential Transmit Pair 4 PCI Express Differential Receive Pair 4 PCI Express Differential Transmit Pair 5 PCI Express Differential Receive Pair 5 PCI Express Differential Transmit Pair 6: The differential pair will function as the Gigabit LAN Connect Interface transmit pair when the integrated Gigabit LAN controller is enabled. PCI Express Differential Receive Pair 6: The differential pair will function as the Gigabit LAN Connect Interface receive pair when the integrated Gigabit LAN controller is enabled. O I 2.3 Table 2-3. LAN Connect Interface LAN Connect Interface Signals Name Type Description Gigabit LAN Input Clock: Clock driven by the Platform LAN Connect device. The frequency will vary depending on link speed. GLAN_CLK I NOTE: The clock is shared between the LAN Connect Interface and the Gigabit LAN Connect Interface. LAN_RXD[2:0] I Received Data: The Platform LAN Connect device uses these signals to transfer data and control information to the integrated LAN controller. These signals have integrated weak pull-up resistors. 48 Datasheet Signal Description Table 2-3. LAN Connect Interface Signals Name LAN_TXD[2:0] Type O Description Transmit Data: The integrated LAN controller uses these signals to transfer data and control information to the Platform LAN Connect component. LAN Reset/Sync: This is the reset/sync signal from the LAN Connect Interface to the physical device. The Platform LAN Connect device’s Reset and Sync signals are multiplexed onto this pin. NOTE: The signal is shared between LAN Connect Interface and Gigabit LAN Connect Interface. LAN PHY Power Control: This signal may optionally be connected to a switch to turn 3.3 V PHY power off when LAN is disabled for additional power savings. This capability is configured in the NVM. When using an 82567 PHY solution, the LAN_PHY_PWR_CTRL signal should be connected to the PHY’s LAN_DISABLE_N pin for a hardware based LAN disable mechanism. Signal can instead be used as GPIO12. LAN_RSTSYNC O LAN_PHY_PW R_CTRL / GPIO12 O 2.4 Table 2-4. Gigabit LAN Connect Interface Gigabit LAN Connect Interface Signals Name Type Description Gigabit LAN Input Clock: Clock driven by the Platform LAN Connect device. The frequency will vary depending on link speed. GLAN_CLK I NOTE: The clock is shared between the LAN Connect Interface and the Gigabit LAN Connect Interface. GLAN_TXp/PETp6; GLAN_TXn/PETn6 GLAN_RXp/PERp6; GLAN_RXn/PERn6 GLAN_COMPO GLAN_COMPI O I O I Gigabit LAN Differential Transmit Pair. Can be instead used as PCI Express port 6 differential transmit pair. Gigabit LAN Differential Receive Pair. Can be instead used as PCI Express port 6 differential receive pair. Impedance Compensation Output pad: Determines Gigabit LAN Connect Interface output impedance and bias current. Impedance Compensation Input pad: Determines Gigabit LAN Connect Interface input impedance. LAN Reset/Sync: This is the reset/sync signal from the Gigabit LAN interface to the physical device. The Platform LAN Connect device’s Reset and Sync signals are multiplexed onto this pin. NOTE: The signal is shared between LAN Connect Interface and Gigabit LAN Connect Interface. LAN_RSTSYNC O Datasheet 49 Signal Description 2.5 Table 2-5. Firmware Hub Interface Firmware Hub Interface Signals Name FWH[3:0] / LAD[3:0] FWH4 / LFRAME# INIT3_3V# Type I/O O O Description Firmware Hub Signals. These signals are multiplexed with the LPC address signals. Firmware Hub Signals. This signal is multiplexed with the LPC LFRAME# signal. Initialization 3.3 V: This is the identical 3.3 V copy of INIT# intended for Firmware Hub. 2.6 Table 2-6. PCI Interface PCI Interface Signals (Sheet 1 of 3) Name Type Description PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The Intel ICH10will drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# define the Byte Enables. C/BE[3:0]# 0000b 0001b 0010b C/BE[3:0]# I/O 0011b 0110b 0111b 1010b 1011b 1100b 1110b 1111b Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write and Invalidate AD[31:0] I/O All command encodings not shown are reserved. The ICH10 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. Device Select: The ICH10 asserts DEVSEL# to claim a PCI transaction. As an output, the ICH10 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH10 address or an address destined for DMI (main memory or graphics). As an input, DEVSEL# indicates the response to an ICH10-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PLTRST#. DEVSEL# remains tri-stated by the ICH10 until driven by a target device. DEVSEL# I/O 50 Datasheet Signal Description Table 2-6. PCI Interface Signals (Sheet 2 of 3) Name Type Description Cycle Frame: The current initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the ICH10 when the ICH10 is the target, and FRAME# is an output from the ICH10 when the ICH10 is the initiator. FRAME# remains tri-stated by the ICH10 until driven by an initiator. Initiator Ready: IRDY# indicates the ICH10's ability, as an initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the ICH10 has valid data present on AD[31:0]. During a read, it indicates the ICH10 is prepared to latch data. IRDY# is an input to the ICH10 when the ICH10 is the target and an output from the ICH10 when the ICH10 is an initiator. IRDY# remains tri-stated by the ICH10 until driven by an initiator. Target Ready: TRDY# indicates the ICH10's ability as a target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the ICH10, as a target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the ICH10, as a target is prepared to latch data. TRDY# is an input to the ICH10 when the ICH10 is the initiator and an output from the ICH10 when the ICH10 is a target. TRDY# is tri-stated from the leading edge of PLTRST#. TRDY# remains tri-stated by the ICH10 until driven by a target. Stop: STOP# indicates that the ICH10, as a target, is requesting the initiator to stop the current transaction. STOP# causes the ICH10, as an initiator, to stop the current transaction. STOP# is an output when the ICH10 is a target and an input when the ICH10 is an initiator. Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH10 counts the number of ones within the 36 bits plus PAR and the sum is always even. The ICH10 always calculates PAR on 36 bits regardless of the valid byte enables. The ICH10 generates PAR for address and data phases and only ensures PAR to be valid one PCI clock after the corresponding address or data phase. The ICH10 drives and tri-states PAR identically to the AD[31:0] lines except that the ICH10 delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all ICH10 initiated transactions. PAR is an output during the data phase (delayed one clock) when the ICH10 is the initiator of a PCI write transaction, and when it is the target of a read transaction. ICH10 checks parity when it is the target of a PCI write transaction. If a parity error is detected, the ICH10 will set the appropriate internal status bits, and has the option to generate an NMI# or SMI#. Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The ICH10 drives PERR# when it detects a parity error. The ICH10 can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). FRAME# I/O IRDY# I/O TRDY# I/O STOP# I/O PAR I/O PERR# I/O Datasheet 51 Signal Description Table 2-6. PCI Interface Signals (Sheet 3 of 3) Name REQ0# REQ1#/ GPIO50 REQ2#/ GPIO52 REQ3#/GPIO54 GNT0# GNT1#/ GPIO51 GNT2#/ GPIO53 GNT3#/GPIO55 O I Type Description PCI Requests: The ICH10 supports up to 4 masters on the PCI bus. REQ[3:1]# pins can instead be used as GPIO. PCI Grants: The ICH10 supports up to 4 masters on the PCI bus. GNT[3:1]# pins can instead be used as GPIO. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail. NOTE: GNT[3:0]# are sampled as a functional strap. See Section 2.25.1 for details. I PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of the primary interface PLTRST# signal and the state of the Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). PCI Lock: This signal indicates an exclusive bus operation and may require multiple transactions to complete. ICH10 asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. PLOCK# is ignored when PCI masters are granted the bus. System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the ICH10 has the ability to generate an NMI, SMI#, or interrupt. PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1–S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the ICH10 may drive PME# active due to an internal wake event. The ICH10 will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. PCICLK PCIRST# O PLOCK# I/O SERR# I/OD PME# I/OD 2.7 bh Serial ATA Interface Serial ATA Interface Signals (Sheet 1 of 3) Name SATA0TXP SATA0TXN Type Description Serial ATA 0 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 0. In compatible mode, SATA Port 0 is the primary master of SATA Controller 1. Serial ATA 0 Differential Receive Pair: These are inbound highspeed differential signals from Port 0. In compatible mode, SATA Port 0 is the primary master of SATA Controller 1. Serial ATA 1 Differential Transmit Pair: These are outbound high-speed differential signals to Port 1. In compatible mode, SATA Port 1 is the secondary master of SATA Controller 1. Table 2-7. O SATA0RXP SATA0RXN I SATA1TXP SATA1TXN O 52 Datasheet Signal Description Table 2-7. Serial ATA Interface Signals (Sheet 2 of 3) Name SATA1RXP SATA1RXN Type Description Serial ATA 1 Differential Receive Pair: These are inbound highspeed differential signals from Port 1. In compatible mode, SATA Port 1 is the secondary master of SATA Controller 1 Serial ATA 2 Differential Transmit Pair: These are outbound high-speed differential signals to Port 2. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1. Serial ATA 2 Differential Receive Pair: These are inbound highspeed differential signals from Port 2. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1 Serial ATA 3 Differential Transmit Pair: These are outbound high-speed differential signals to Port 3. In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1 Serial ATA 3 Differential Receive Pair: These are inbound highspeed differential signals from Port 3. In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1 Serial ATA 4 Differential Transmit Pair: These are outbound high-speed differential signals to Port 4. In compatible mode, SATA Port 4 is the primary master of SATA Controller 2 Serial ATA 4 Differential Receive Pair: These are inbound highspeed differential signals from Port 4. In compatible mode, SATA Port 4 is the primary master of SATA Controller 2 Serial ATA 5 Differential Transmit Pair: These are outbound high-speed differential signals to Port 5. In compatible mode, SATA Port 5 is the secondary master of SATA Controller 2 Serial ATA 5 Differential Receive Pair: These are inbound highspeed differential signals from Port 5. In compatible mode, SATA Port 5 is the secondary master of SATA Controller 2 Serial ATA Resistor Bias: This is an analog connection point for an external resistor to ground. Serial ATA Resistor Bias Complement: This is an analog connection point for an external resistor to ground. Serial ATA 0 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 0. When used as an interlock switch status indication, this signal should be drive to ‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. If interlock switches are not required, this pin can be configured as GPIO21. I SATA2TXP SATA2TXN O SATA2RXP SATA2RXN I SATA3TXP SATA3TXN O SATA3RXP SATA3RXN I SATA4TXP SATA4TXN O SATA4RXP SATA4RXN I SATA5TXP SATA5TXN O SATA5RXP SATA5RXN SATARBIAS SATARBIAS# I O I SATA0GP / GPIO21 I Datasheet 53 Signal Description Table 2-7. Serial ATA Interface Signals (Sheet 3 of 3) Name SATA1GP / GPIO19 Type Description Serial ATA 1 General Purpose: Same function as SATA0GP, except for SATA Port 1. If interlock switches are not required, this pin can be configured as GPIO19. Serial ATA 2 General Purpose: Same function as SATA0GP, except for SATA Port 2. SATA2GP / GPIO36 I If interlock switches are not required, this pin can be configured as GPIO36. NOTE: This signal can also be used as GPIO36. Serial ATA 3 General Purpose: Same function as SATA0GP, except for SATA Port 3. SATA3GP / GPIO37 I If interlock switches are not required, this pin can be configured as GPIO37. NOTE: This signal can also be used as GPIO37. SATA4GP SATA5GP I I Serial ATA 4 General Purpose: Same function as SATA0GP, except for SATA Port 4. Serial ATA 5 General Purpose: Same function as SATA0GP, except for SATA Port 5. Serial ATA LED: This signal is an open-drain output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is required. NOTE: This signal is sampled as a functional strap. See Section 2.25.1 for details. SATACLKREQ# /GPIO35 Serial ATA Clock Request: This signal is an open-drain output pin when configured as SATACLKREQ#. It is used to connect to the system clock chip. When active, request for SATA Clock running is asserted. When tri-stated, it tells the Clock Chip that SATA Clock can be stopped. An external pull-up resistor is required. SGPIO Reference Clock: The SATA controller uses rising edges of this clock to transmit serial data, and the target uses the falling edge of this clock to latch data. If SGPIO interface is not used, this signal can be used as a GPIO. SGPIO Load: The controller drives a ‘1’ at the rising edge of SCLOCK to indicate either the start or end of a bit stream. A 4-bit vendor specific pattern will be transmitted right after the signal assertion. If SGPIO interface is not used, this signal can be used as a GPIO. SDATAOUT0/ GPIO39 SDATAOUT1/ GPIO48 SGPIO Dataout: Driven by the controller to indicate the drive status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2... If SGPIO interface is not used, the signals can be used as GPIO. I SATALED# OD O OD O SCLOCK/ GPIO22 OD O SLOAD/GPIO38 OD O OD O 54 Datasheet Signal Description 2.8 Table 2-8. LPC Interface LPC Interface Signals Name LAD[3:0] / FWH[3:0] LFRAME# / FWH4 LDRQ0#, LDRQ1# / GPIO23 I Typ e I/O O Description LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pullups are provided. LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to an external Super I/O device. An internal pull-up resistor is provided on these signals. LDRQ1# may optionally be used as GPIO. 2.9 Table 2-9. Interrupt Interface Interrupt Signals Name SERIRQ Type I/OD Description Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 5.8.6. Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts. PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 5.8.6. Each PIRQx# line has a separate Route Control register. I/OD In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPIO. PIRQ[D:A]# I/OD PIRQ[H:E]# / GPIO[5:2] Datasheet 55 Signal Description 2.10 USB Interface Table 2-10. USB Interface Signals Name Typ e Description Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1. These ports can be routed to UHCI controller #1 or the EHCI controller #1. I/O NOTE: No external resistors are required on these signals. The Intel ICH10 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3. These ports can be routed to UHCI controller #2 or the EHCI controller #1. NOTE: No external resistors are required on these signals. The ICH10 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. Universal Serial Bus Port [5:4] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 4 and 5. These ports can be routed to UHCI controller #3 or the EHCI controller #1. NOTE: No external resistors are required on these signals. The ICH10 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. Universal Serial Bus Port [7:6] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 6 and 7. These ports can be routed to UHCI controller #4 or the EHCI controller #2. NOTE: No external resistors are required on these signals. The ICH10 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. Universal Serial Bus Port [9:8] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 8 and 9. These ports can be routed to UHCI controller #5 or the EHCI controller #2. NOTE: No external resistors are required on these signals. The ICH10 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP0P, USBP0N, USBP1P, USBP1N USBP2P, USBP2N, USBP3P, USBP3N I/O USBP4P, USBP4N, USBP5P, USBP5N I/O USBP6P, USBP6N, USBP7P, USBP7N I/O USBP8P, USBP8N, USBP9P, USBP9N I/O 56 Datasheet Signal Description Table 2-10. USB Interface Signals Name Typ e Description Universal Serial Bus Port [11:10] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 10 and 11. These ports can be routed to UHCI controller #6 or the EHCI controller #2. These ports can be optionally routed to EHCI Controller #1 when bit 0 RCBA 35F0h is set. NOTE: No external resistors are required on these signals. The ICH10 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. OC[11:0]# may optionally be used as GPIOs. NOTE: OC[11:0]# are not 5 V tolerant. I USBP10P, USBP10N, USBP11P, USBP11N I/O OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31 OC8# / GPIO44 OC9# / GPIO45 OC10# / GPIO46 OC11# / GPIO47 USBRBIAS O USB Resistor Bias: Analog connection point for an external resistor. Used to set transmit currents and internal load resistors. USB Resistor Bias Complement: Analog connection point for an external resistor. Used to set transmit currents and internal load resistors. USBRBIAS# I Datasheet 57 Signal Description 2.11 Power Management Interface Table 2-11. Power Management Interface Signals (Sheet 1 of 3) Name Type Description Platform Reset: The ICH10 asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, (G)MCH, TPM, etc.). The ICH10 asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h). The ICH10 drives PLTRST# inactive a minimum of 1 ms after both PWROK and VRMPWRGD are driven high. The ICH10 drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O Register CF9h). NOTE: PLTRST# is in the VccSus3_3 well. THRM# I Thermal Alarm: Active low signal generated by external hardware to generate an SMI# or SCI. Thermal Trip: When low, this signal indicates that a thermal trip from the processor occurred, and the ICH10 will immediately transition to a S5 state. The ICH10 will not wait for the processor stop grant cycle since the processor has overheated. S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. S4 Sleep Control: SLP_S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. NOTE: This pin must be used to control the DRAM power in order to use the ICH10’s DRAM power-cycling feature. Refer to Chapter 5.13.10.2 for details NOTE: In a system with Intel AMT support, this signal should be used to control the DRAM power. In M1 state (where the host platform is in S3-S5 states and the manageability sub-system is running) the signal is forced high along with SLP_M# in order to properly maintain power to the DIMM used for manageability sub-system. SLP_S5# / GPIO63 (Corporate Only) SLP_M# O S5 Sleep Control: SLP_S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states. ICH10 Corporate Family: pin may also be used as GPIO63. O Manageability Sleep State Control: This signal is used to control power planes to the Intel AMT sub-system. If no Intel Management Engine firmware is present, SLP_M# will have the same timings as SLP_S3#. S4 State Indication: This signal asserts low when the host platform is in S4 or S5 state. In platforms where the Intel Management Engine is forcing the SLP_S4# high along with SLP_M#, this signal can be used by other devices on the board to know when the host platform is below the S3 state. PLTRST# O THRMTRIP# I SLP_S3# O SLP_S4# O S4_STATE# / GPIO26 O 58 Datasheet Signal Description Table 2-11. Power Management Interface Signals (Sheet 2 of 3) Name Type Description Power OK: When asserted, PWROK is an indication to the ICH10 that all power rails have been stable for 99 ms and that PCICLK has been stable for 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the ICH10 asserts PLTRST#. PWROK I NOTE: 1. PWROK must deassert for a minimum of three RTC clock periods in order for the ICH10 to fully reset the power and properly generate the PLTRST# output. 2. PWROK must not glitch, even if RSMRST# is low. Controller Link Power OK: When asserted, indicates that power to the Controller Link subsystem (MCH, ICH, etc.) is stable and tells the ICH to de-assert CL_RST# to the (G)MCH. CLPWROK I NOTES: 1. CLPWROK must not assert before RSMRST# deasserts. 2. CLPWROK must not assert after PWROK asserts. Power Button: The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S1–S4 states. This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input. Ring Indicate: This signal is an input from a modem. It can be enabled as a wake event, and this is preserved across power failures. System Reset: This pin forces an internal reset after being debounced. The ICH10 will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system. Resume Well Reset: This signal is used for resetting the resume power plane logic. This signal must be asserted for at least 10 ms after the suspend power wells are valid. When deasserted, this signal is an indication that the suspend power wells are stable. LAN Reset: When asserted, the internal LAN controller is in reset. This signal must be asserted until the LAN power wells (VccLAN3_3 and VccLAN1_1) and VccCL3_3 power well are valid. When deasserted, this signal is an indication that the LAN power wells are stable. NOTES: 1. LAN_RST# must not deassert before RSMRST# deasserts 2. LAN_RST# must not deassert after PWROK asserts. 3. LAN_RST# must not deassert until 1ms after the LAN power wells (VccLAN3_3 and VccLAN1_1 and VccCL3_3 power well are valid. 4. If integrated LAN is not used LAN_RST# must be tied to Vss. 5. LAN_RST# must assert a minimum of 20 ns before LAN Power rails become inactive. PCI Express* Wake Event: Sideband wake signal on PCI Express asserted by components requesting wake up. MCH SYNC: This input is internally ANDed with the PWROK input. Connect to the ICH_SYNC# output of the (G)MCH. PWRBTN# I RI# I SYS_RESET# I RSMRST# I LAN_RST# I WAKE# MCH_SYNC# I I Datasheet 59 Signal Description Table 2-11. Power Management Interface Signals (Sheet 3 of 3) Name Type Description Suspend Status: This signal is asserted by the ICH10 to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC interface. ICH10 Corporate Family: pin may also be used as GPIO61. SUSCLK / GPIO62 (Corporate Only) VRMPWRGD O Suspend Clock: This clock is an output of the RTC generator circuit to use by other chips for refresh clock. ICH10 Corporate Family: pin may also be used as GPIO62. VRM Power Good: This signal should be connected to the processor’s VRM Power Good signifying the VRM is stable. This signal is internally ANDed with the PWROK input. This signal is in the suspend well. DRAMPWROK (Corporate Only) / GPIO8 CK_PWRGD OD O DRAM Power OK: This signal should connect to the (G)MCH’s DDR3_DRAM_PWROK pin. The ICH asserts this pin to indicate when DRAM power is off. An external pull-up resistor is required. This pin is not open-drain when operating in GPIO mode. O Clock Generator Power Good: This signal indicates to the clock generator when the main power well is valid. This signal is asserted high when both SLP_S3# and VRMPWRGD are high. Bus Master Busy: This signal is used to support the C3 state. It Indicates that a bus master device is busy. When this signal is asserted, the BM_STS bit will be set. If this signal goes active in a C3 state, it is treated as a break event. I NOTE: This signal is internally synchronized using the PCICLK and a two-stage synchronizer. It does not need to meet any particular setup or hold time. Signal may also be used as a GPIO. STP_PCI# / GPIO15 STP_CPU# / GPIO25 (Corporate Only) DPRSTP# DPRSLPVR / GPIO16 Stop PCI Clock: This signal is an output to the external clock generator for it to turn off the PCI clock. It is used to support the C3 state. This signal can instead be used as a GPIO. O O Stop CPU Clock: This signal is an output to the external clock generator for it to turn off the processor clock. Corporate Only: This signal can instead be used as a GPIO. Deeper Stop: This is a copy of the DPRSLPVR and it is active low. Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of the VRM during the C4 state. When the signal is high, the voltage regulator outputs the lower “Deeper Sleep” voltage. When low (default), the voltage regulator outputs the higher “Normal” voltage. This signal can instead be used as a GPIO. SUS_STAT# / LPCPD# / GPIO61 (Corporate Only) O I BMBUSY# / GPIO0 O O 60 Datasheet Signal Description 2.12 Processor Interface Table 2-12. Processor Interface Signals (Sheet 1 of 2) Name A20M# Type O Description Mask A20: A20M# will go active based on either setting the appropriate bit in the Port 92h register, or based on the A20GATE input being active. Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the ICH10 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset Config Registers:Offset 31FFh: bit 1 for Consumer Family and Offset 31FEh: bit 9 for Corporate family). If FERR# is asserted, the ICH10 generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. NOTE: FERR# can be used in some states for notification by the processor of pending interrupt events. This functionality is independent of the OIC register bit setting. Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the ICH10 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset Config Registers:Offset 31FFh: bit 1 for Consumer Family and Offset 31FEh: bit 9 for Corporate family). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error register (I/O register F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error register is written, the IGNNE# signal is not asserted. Initialization: INIT# is asserted by the ICH10 for 16 PCI clocks to reset the processor. ICH10 can be configured to support processor Built In Self Test (BIST). CPU Interrupt: INTR is asserted by the ICH10 to signal to the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt to the processor. The ICH10 can generate an NMI when either SERR# is asserted or IOCHK# goes active via the SERIRQ# stream. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/ disable bit in the NMI Status and Control register (I/O Register 61h). System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the ICH10 in response to one of many enabled hardware or software events. Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH10 in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. FERR# I IGNNE# O INIT# O INTR O NMI O SMI# O STPCLK# O Datasheet 61 Signal Description Table 2-12. Processor Interface Signals (Sheet 2 of 2) Name Type Description Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the ICH10’s other sources of INIT#. When the ICH10 detects the assertion of this signal, INIT# is generated for 16 PCI clocks. NOTE: The ICH10 will ignore RCIN# assertion during transitions to the S3, S4, and S5 states. A20GATE I A20 Gate: A20GATE is from the keyboard controller. The signal acts as an alternative method to force the A20M# signal active. It saves the external OR gate needed with various other chipsets. CPU Power Good: This signal should be connected to the processor’s PWRGOOD input to indicate when the processor power is valid. This is an output signal that represents a logical AND of the ICH10’s PWROK and VRMPWRGD signals. Deeper Sleep: DPSLP# is asserted by the ICH10 to the processor. DPSLP# O When the signal is low, the processor enters the deep sleep state by gating off the processor Core Clock inside the processor. When the signal is high (default), the processor is not in the deep sleep state. Deeper Sleep: DPSLP# is asserted by the ICH10 to the processor. When the signal is low, the processor enters the deep sleep state by gating off the processor Core Clock inside the processor. When the signal is high (default), the processor is not in the deep sleep state. RCIN# I CPUPWRGD O DPSLP# O 2.13 SMBus Interface Table 2-13. SMBus Interface Signals Name SMBDATA SMBCLK SMBALERT# / GPIO11 / JTAGTDO (Corporate Only) Type I/OD I/OD Description SMBus Data: External pull-up resistor is required. SMBus Clock: External pull-up resistor is required. SMBus Alert: This signal is used to wake the system or generate SMI#. I ICH10 Consumer Family: This signal may be used as GPIO11. ICH10 Corporate Family: This signal may be used as GPIO11 or JTAGTDO. 62 Datasheet Signal Description 2.14 System Management Interface Table 2-14. System Management Interface Signals (Sheet 1 of 2) Name INTRUDER# Type I Description Intruder Detect: This signal can be set to disable system if box detected open. This signal’s status is readable, so it can be used like a GPIO if the Intruder Detection is not needed. System Management Link: SMBus link to optional external system management ASIC or LAN controller. External pull-ups are required. Note that SMLINK0 corresponds to an SMBus Clock signal, and SMLINK1 corresponds to an SMBus Data signal. SMLink Alert: Output of the integrated LAN controller and input to either the integrated ASF, Intel AMT or an external management controller in order for the LAN’s SMLINK slave to be serviced. External pull-up resistor is required. ICH10 Consumer: This signal can instead be used as a GPIO60. ICH10 Corporate: This signal can instead be used as a GPIO60 or JTAGRST#. Memory LED: Provides DRAM-powered LED control. Allows for the blinking of an LED to indicate memory activity in all power states. This functionality is configured and controlled by the Intel Management Engine. This signal can instead be used as GPIO24. SMLINK[1:0] I/OD LINKALERT# / GPIO60 / JTAGRST# (Corporate Only) O OD MEM_LED / GPIO24 O OD Datasheet 63 Signal Description Table 2-14. System Management Interface Signals (Sheet 2 of 2) Name Type Description Wake On LAN Power Enable. In an Intel AMT or ASF enabled system, this output signal is driven high by the ICH to control the LAN subsystem power (VccLAN3_3, VccCL3_3, LAN PHY Power, and SPI device) to support Wake on LAN (WOL) when the Intel Management Engine is powered off. This functionality is configured and controlled by the Intel Management Engine prior to entering the powered off state. WOL_EN / GPIO9 NOTES: 1. This signal should be OR’d with the SLP_M# signal on the motherboard to determine when to power the LAN subsystem. 2. In order to support WOL out of a G3 state, the WOL_EN pin needs to be pulled high by an external resistor until the Intel Management Engine is initialized. If ASF or Intel AMT are disabled on a board that is configured for WOL_EN support, BIOS must utilize GPIO9 to control power to the LAN subsystem when entering S3-S5. In platforms that do not support Intel AMT or ASF, this signal is used as GPIO9. CPU Missing. This signal provides CPU Missing functionality and is configured and controlled by the Manageability Engine. CPU_MISSING / GPIO10 / JTAGTMS (Corporate Only) I This signal must be connected to the CPU SKTOCC# output to indicate to the Intel Manageability Engine that the CPU is not physically present when asserted. ICH10 Consumer Family: This signal may be used as GPIO10. ICH10 Corporate Family: This signal may be used as GPIO10 or JTAGTMS. TPM_PP / GPIO57 / JTAGTCK (Corporate Only) I TPM Physical Presence. This signal is asserted to indicate Physical Presence to the integrated TPM module. ICH10 Consumer Family: This signal may be used as GPIO57. ICH10 Corporate Family: This signal may be used as GPIO57 or JTAGTCK. O 2.15 Real Time Clock Interface Name RTCX1 RTCX2 Type Special Special Description Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX2 should be left floating. Table 2-15. Real Time Clock Interface 64 Datasheet Signal Description 2.16 Other Clocks Name CLK14 CLK48 SATA_CLKP SATA_CLKN DMI_CLKP, DMI_CLKN Type I I I I Description Oscillator Clock: Used for 8254 timers. Runs at 14.31818 MHz. This clock is permitted to stop during S3 (or lower) states. 48 MHz Clock: Used to run the USB controller. Runs at 48.000 MHz. This clock is permitted to stop during S3 (or lower) states. 100 MHz Differential Clock: These signals are used to run the SATA controller at 100 MHz. This clock is permitted to stop during S3/S4/S5 states. 100 MHz Differential Clock: These signals are used to run the Direct Media Interface. Runs at 100 MHz. Table 2-16. Other Clocks 2.17 Miscellaneous Signals Name INTVRMEN Type I Description Internal Voltage Regulator Enable: This signal enables the internal VccSus1_1, VccSus1_5 and VccCL1_5 regulators. This signal must be pulled-up to VccRTC. Internal Voltage Regulator Enable: When connected to VccRTC, this signal enables the internal voltage regulators powering VccLAN1_1 and VccCL1_1. This signal must be pulled-up to VccRTC. Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PLTRST#, its output state is 0. NOTE: SPKR is sampled as a functional strap. See Section 2.25.1 for more details. There is a weak integrated pull-down resistor on SPKR pin. RTC Reset: When asserted, this signal resets register bits in the RTC well. NOTES: 1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must always be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the RSMRST# pin. Table 2-17. Miscellaneous Signals (Sheet 1 of 2) LAN100_SLP I SPKR O RTCRST# I Datasheet 65 Signal Description Table 2-17. Miscellaneous Signals (Sheet 2 of 2) Name Type Description Secondary RTC Reset: This signal resets the manageability register bits in the RTC well when the RTC battery is removed. NOTES: 1. The SRTCRST# input must always be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the SRTCRST# pin must rise before the RSMRST# pin. Test Point 0: This signal must have an external pull-up to VccSus3_3. ICH10 Corporate: Pin can instead be used as GPIO72. I/O I/O I/O I O Test Point 3: Route signal to a test point. Test Point 4: Route signal to a test point. Test Point 5: Route signal to a test point. Test Point 6: Route signal to a test point. Test Point 7: Route signal to a test point. SRTCRST# I TP0 / GPIO72 (Corporate Only) TP3 TP4 TP5 TP6 TP7 I 2.18 Intel® High Definition Audio Link Table 2-18. Intel® High Definition Audio Link Signals Name HDA_RST# Type O Description Intel® High Definition Audio Reset: Master hardware reset to external codec(s). Intel High Definition Audio Sync: 48 kHz fixed rate sample sync to the codec(s). Also used to encode the stream number. HDA_SYNC O NOTE: This signal is sampled as a functional strap. See Section 2.25.1 for more details. There is a weak integrated pull-down resistor on this pin. 66 Datasheet Signal Description Table 2-18. Intel® High Definition Audio Link Signals Name Type Description Intel High Definition Audio Bit Clock Output: 24.000 MHz serial data clock generated by the Intel High Definition Audio controller (the Intel ICH10). This signal has a weak internal pulldown resistor. Intel High Definition Audio Serial Data Out: Serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel High Definition Audio. HDA_SDOUT O NOTE: This signal is sampled as a functional strap. See Section 2.25.1 for more details. There is a weak integrated pull-down resistor on this pin. Intel High Definition Audio Serial Data In [3:0]: Serial TDM data inputs from the codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel High Definition Audio. These signals have integrated pull-down resistors, which are always enabled. NOTE: During enumeration, the ICH will drive this signal. During normal operation, the CODEC will drive it. HDA_BIT_CLK O HDA_SDIN[3:0] I 2.19 Serial Peripheral Interface (SPI) Table 2-19. Serial Peripheral Interface (SPI) Signals Name Type Description SPI Chip Select 0: Used as the SPI bus request signal. SPI_CS0# O NOTE: This signal is sampled as a functional strap. See Section 2.25.1 for more details. SPI Chip Select 1: Used as the SPI bus request signal. SPI_CS1# O NOTE: This signal is sampled as a functional strap. See Section 2.25.1 for more details. There is a weak integrated pull-up resistor on this pin. SPI Master IN Slave OUT: Data input pin for ICH10. SPI Master OUT Slave IN: Data output pin for ICH10. SPI_MOSI O NOTE: This signal is sampled as a functional strap. See Section 2.25.1 for more details. There is a weak integrated pull-down resistor on this pin. SPI Clock: SPI clock signal, during idle the bus owner will drive the clock signal low. 17.86 MHz and 31.25 MHz. SPI_MISO I SPI_CLK O Datasheet 67 Signal Description 2.20 Controller Link Table 2-20. Controller Link Signals Signal Name CL_CLK0 CL_DATA0 Type I/O I/O Description Controller Link Clock 0: bi-directional clock that connects to the (G)MCH. Controller Link Data 0: bi-directional data that connects to the (G)MCH. Controller Link Reference Voltage 0: External reference voltage for Controller Link 0. CL_VREF0 I ICH10 Corporate: When using internal reference voltage as configured by CLINKVREFSEL (ICHSTRP0:bit 5), an external circuit is not required and pin is No Connect (Recommended Configuration). Optionally, an external reference voltage generation circuit may be used (requires CLINKVREFSEL = 1). Controller Link Reset 0: North Controller Link reset that connects to the (G)MCH. CL_RST0# O 2.21 Intel® Quiet System Technology Table 2-21. Intel® Quiet System Technology Signals Signal Name Type Description Fan Pulse Width Modulation Outputs: Pulse Width Modulated duty cycle output signal that is used for Intel® Quiet System Technology. PWM[2:0] OD O When controlling a 3-wire fan, this signal controls a power transistor that, in turn, controls power to the fan. When controlling a 4-wire fan, this signal is connected to the “Control” signal on the fan. The polarity of this signal is programmable. The output default is low. These signals are 5V tolerant. TACH0/GPIO17 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 I Fan Tachometer Inputs: Tachometer pulse input signal that is used to measure fan speed. This signal is connected to the “Sense” signal on the fan. Can instead be used as a GPIO. 68 Datasheet Signal Description Table 2-21. Intel® Quiet System Technology Signals Signal Name SST Type I/O Description Simple Serial Transport: Single-wire, serial bus. Connect to SST compliant devices such as SST thermal sensors or voltage sensors. Platform Environment Control Interface: Single-wire, serial bus. Connect to corresponding pin of the processor for accessing processor digital thermometer. Intel QST BMBUSY# Interconnect (Consumer Only): This signal is used for Intel ICH10 Consumer based platforms that support Intel QST and C3 and/or C4 processor states. QST_BMBUSY# is asserted by the ICH10 to ensure that Intel QST can read the processor thermal sensor since the sensor is inaccessible when the platform is in C3 or C4. QST_BMBUSY# must be externally tied to the BMBUSY# signal on the ICH10 to cause the platform to exit or prevent entry into C3 or C4. QST_BMBUSY# functionality is configured and controlled by the Intel Management Engine firmware. ICH10 Consumer: In non-Intel QST based platforms, this signal can instead be used as a GPIO14. ICH10 Corporate: This signal is instead used as a GPIO14 or JTAGTDI. PECI I/O QST_BMBUSY# (Consumer Only) / JTAGTDI (Corporate Only) / GPIO14 O 2.22 JTAG Signals (Intel® ICH10 Corporate Family Only) Table 2-22. JTAG Signals Name JTAGTCK (Corporate Only) / GPIO57 / TPM_PP JTAGTMS (Corporate Only) / GPIO10 / CPU_MISSING JTAGTDI (Corporate Only) / GPIO14 / QST_BMBUSY# JTAGTDO (Corporate Only) / GPIO11/ SMBALERT# JTAGRST# (Corporate Only) / LINKALERT# / GPIO60 Type I/O Description Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. I/O I/O Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI. I/O Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. Test Reset (RST): RST is an active low asynchronous signal that can reset the Test Access Port (TAP) controller. I/O NOTE: The RST signal is optional per the IEEE 114.1 specification, and is not functional for Boundary Scan Testing NOTE: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1-2001) Datasheet 69 Signal Description 2.23 General Purpose I/O Signals Table 2-23. General Purpose I/O Signals (Sheet 1 of 3) Name GPIO72 (Corporate Only) GPIO63 (Corporate Only) GPIO62 (Corporate Only) GPIO61 (Corporate Only) Type Tolerance Power Well Default Description ICH10 Consumer Family: Pin implemented as TP0 only. ICH10 Corporate Family: Pin is multiplexed with TP0. (NOTE 13) ICH10 Consumer Family: Pin may only be used as SLP_S5#. ICH10 Corporate Family: Pin is multiplexed with SLP_S5# (NOTE 13) ICH10 Consumer Family: Pin may only be used as SUSCLK ICH10 Corporate Family: Pin is multiplexed with SUSCLK (NOTE 13) ICH10 Consumer Family: Pin May only be used as SUS_STAT# / LPCPD# ICH10 Corporate Family: Pin is multiplexed with SUS_STAT# / LPCPD# (NOTE 13) ICH10 Consumer Family: Multiplexed with LINKALERT#. I/O 3.3 V Core Native I/O 3.3 V Suspend Native I/O 3.3 V Suspend Native I/O 3.3 V Suspend Native GPIO60 GPIO59 I/O I/O 3.3 V 3.3 V Suspend Suspend Native Native ICH10 Corporate Family: Multiplexed with LINKALERT# and JTAGRST#. (NOTE 13) Multiplexed with OC[0]#. (NOTE 13) ICH10 Consumer Family: Can be used as TPM_PP. ICH10 Corporate Family Can be used as TPM_PP or JTAGTCK. UnMultiplexed Multiplexed with GNT3# (Note 8). Multiplexed with REQ3#. (NOTE 13) Multiplexed with GNT2# (Note 8). Multiplexed with REQ2#. (NOTE 13) Multiplexed with GNT1# (Note 8). Multiplexed with REQ1#. (NOTE 13) UnMultiplexed (Note 8). Multiplexed with SDATAOUT1. Multiplexed with OC[11:8]#. (NOTE 13) Multiplexed with OC[4:1]#. (NOTE 13) Multiplexed with SDATAOUT0. Multiplexed with SLOAD. Multiplexed with SATA3GP. Multiplexed with SATA2GP. GPIO57 I/O 3.3 V Suspend GPI GPIO56 GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48 GPIO[47:44] GPIO[43:40] GPIO39 GPIO38 GPIO37 GPIO36 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 3.3 V 3.3 V 5.0 V 3.3 V 5.0 V 3.3 V 5.0 V 3.3V 3.3 V 3.3V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Suspend Core Core Core Core Core Core Core Core Suspend Suspend Core Core Core Core GPI Native Native Native Native Native Native GPO GPI Native Native GPI GPI GPI GPI 70 Datasheet Signal Description Table 2-23. General Purpose I/O Signals (Sheet 2 of 3) Name GPIO35 GPIO34 GPIO33 GPIO32 GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 (Corporate Only) GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Tolerance 3.3 V 1.5 V / 3.3 V (Note 12) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Power Well Core VccHDA Core Core Suspend Suspend Suspend Suspend Suspend Suspend Suspend Default GPO GPO GPO GPO Native Native Native GPO GPO Native Native Description Multiplexed with SATACLKREQ#. UnMultiplexed. UnMultiplexed. UnMultiplexed. Multiplexed with OC7#. (NOTE 13) Multiplexed with OC6#. (NOTE 13) Multiplexed with OC5#. (NOTE 13) UnMultiplexed. UnMultiplexed Multiplexed with S4_STATE#. (Note 9) Default as STP_CPU# (Note 3). Can be used as MEM_LED. GPIO24 configuration register bits are not cleared by CF9h reset event. Multiplexed with LDRQ1#. (NOTE 13) Multiplexed with SCLOCK. Multiplexed with SATA0GP. UnMultiplexed. (Note 8) Multiplexed with SATA1GP. UnMultiplexed. Multiplexed with TACH0. May also be used as DPRSLPVR default as STP_PCI#. (Note 3) ICH10 Consumer Family: Can be used as QST_BMBUSY#. ICH10 Corporate Family: Can be used as JTAGTD, or QST_BMBUSY#I. UnMultiplexed. Multiplexed with LAN_PHY_PWR_CTRL. (NOTE 13) ICH10 Consumer Family: Can be used as SMBALERT#. (NOTE 13) ICH10 Corporate Family Can be used as SMBALERT# or JTAGTDO. (NOTE 13) ICH10 Consumer Family: Can be used as CPU_MISSING. ICH10 Corporate Family: Can be used as CPU_MISSING or JTAGTMS. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Suspend Core Core Core Core Core Core Core Core Suspend GPO Native GPI GPI GPO GPI GPO (Note 11) GPI Native Native GPIO14 I/O 3.3 V Suspend GPI GPIO13 GPIO12 I/O I/O 3.3 V 3.3 V Suspend Suspend GPI GPO GPIO11 I/O 3.3 V Suspend Native GPIO10 I/O 3.3 V Suspend GPI Datasheet 71 Signal Description Table 2-23. General Purpose I/O Signals (Sheet 3 of 3) Name GPIO9 Type I/O Tolerance 3.3 V Power Well Suspend Default Native Corporate Only GPI Consumer Only Native GPI GPI GPI GPI Description Can be used as WOL_EN. ICH10 Corporate Family: Can be used as DRAMPWROK. ICH10 Consumer Family: Unmultiplexed Multiplexed with TACH[3:2]. Multiplexed with PIRQ[H:E]# (Note 6). Multiplexed with TACH1. Multiplexed with BMBUSY#. GPIO8 I/O 3.3 V Suspend GPIO[7:6] GPIO[5:2] GPIO1 GPIO0 I/O I/OD I/O I/O 3.3 V 5V 3.3 V 3.3 V Core Core Core Core NOTES: 1. All GPIOs can be configured as either input or output. 2. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI, but not both. 3. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Also, external devices should not be driving powered down GPIOs high. Some ICH10 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event will result in the Intel ICH10 driving a pin to a logic 1 to another device that is powered down. 4. The functionality that is multiplexed with the GPIO may not be utilized in desktop configuration. 5. This GPIO is not an open-drain when configured as an output. 6. SPI_CS1# is located in the VccCL3_3 well. 7. When this signal is configured as GPO the output stage is an open-drain. 8. This signal is sampled as a functional strap. See Section 2.25.1 for more details. 9. The GPIO_USE_SEL bit for this signal is overridden by bit 8 in the GEN_PMCON_3 Register (D31:F0). 10. The GPIO_USE_SEL bit for this is ignored. Functionality is set by bits 9:8 of FLMAP0 register. 11. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH10 comes out of reset. 12. The tolerance of this pin is determined by the voltage of VccHDA either 3.3 V or 1.5 V. 13. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the signal is stable in its inactive state of the native functionality, immediately after reset until it is initialized to GPIO functionality. 72 Datasheet Signal Description 2.24 Power and Ground Signals Table 2-24. Power and Ground Signals (Sheet 1 of 2) Name V5REF V5REF_Sus Vcc1_1 Vcc1_5_A Vcc1_5_B Vcc3_3 Description Reference for 5 V tolerance on core well inputs. This power may be shut off in S3, S4, S5 or G3 states. Reference for 5 V tolerance on suspend well inputs. This power is not expected to be shut off unless the system is unplugged. 1.1 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3 states. 1.5 V supply for Logic and I/O. This power may be shut off in S3, S4, S5 or G3 states. 1.5 V supply for Logic and I/O. This power may be shut off in S3, S4, S5 or G3 states. 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3 states. 1.1V supply for Controller Link. This plane must be on in S0 and other times Controller Link is used. This voltage is generated internally (see Section 2.25.1 for strapping option) and, this pin can be left as No Connect unless decoupling is required. 1.5V supply for Controller Link. This plane must be on in S0 and other times Controller Link is used. This voltage is generated internally (see Section 2.25.1 for strapping option), and this pin can be left as No Connect unless decoupling is required. 3.3V supply for Controller Link. This is a separate power plane that may or may not be powered in S3–S5 states. This plane must be on in S0 and other times Controller Link is used. NOTE: VccCL3_3 must always be powered when VccLAN3_3 is powered. Power supply for DMI. 1.05V, 1.25V or 1.5V depending on (G)MCH’s DMI voltage. 1.5 V supply for core well logic. This signal is used for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states. 1.5V supply for integrated Gigabit LAN I/O buffers. This power is on in S0 and is turned of in S3, S4, S5, even it integrated Gigabit LAN is not used. 3.3V supply for integrated Gigabit LAN logic and I/O. This power is on in S0 and is turned of in S3, S4, S5, even it integrated Gigabit LAN is not used. 1.5V supply for core well logic. This signal is used for the integrated Gigabit LAN PLL. This power is shut off in S3, S4, S5 and G3 states. Core supply for Intel High Definition Audio. This pin can be either 1.5 or 3.3 V. This power may be shut off in S3, S4, S5 or G3 states. NOTE: VccSusHDA and VccHDA can be connected to either 1.5 V or 3.3 V supplies, but both pins must be connected to supplies that are the same nominal value. 1.1 V supply for LAN controller logic. This is a separate power plane that may or may not be powered in S3–S5 states. This voltage is generated internally (see Section 2.25.1 for strapping option) and, these pins can be left as No Connect unless decoupling is required. VccCL1_1 VccCL1_5 VccCL3_3 VccDMI VccDMIPLL VccGLAN1_5 VccGLAN3_3 VccGLANPLL VccHDA VccLAN1_1 Datasheet 73 Signal Description Table 2-24. Power and Ground Signals (Sheet 2 of 2) Name Description 3.3 V supply for LAN Connect interface buffers. This is a separate power plane that may or may not be powered in S3–S5 states. This plane must be on in S0. NOTE: VccLAN3_3 must always be powered when VccCL3_3 or Vcc3_3 is powered. 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained. Note: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an Intel ICH10-based platform can be done by using a jumper on RTCRST# or GPI. 1.5 V supply for core well logic. This signal is used for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if SATA is not used. 1.1 V supply for suspend well logic. This power is not expected to be shut off unless the system is unplugged. VccSus1_1 This voltage is generated internally (see Section 2.25.1 for strapping option). These pins can be left as No Connects unless decoupling is required. 1.5V supply for the suspend well I/O. This power is not expected to be shut off unless the system is unplugged. This voltage is generated internally (see Section 2.25.1 for strapping option). These pins can be left as No Connects unless decoupling is required. 3.3 V supply for suspend well I/O buffers. This power is not expected to be shut off unless the system is unplugged. Suspend supply for Intel® High Definition Audio. This pin can be either 1.5 or 3.3 V. T NOTE: VccSusHDA and VccHDA can be connected to either 1.5 V or 3.3 V supplies, but both pins must be connected to supplies that are the same nominal value. 1.5 V supply for core well logic. This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB not used. Grounds. Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface signals listed in Table 2-12. VccLAN3_3 VccRTC VccSATAPLL VccSus1_5 VccSus3_3 VccSusHDA VccUSBPLL Vss V_CPU_IO 74 Datasheet Signal Description 2.25 2.25.1 Pin Straps Functional Straps The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations (except as noted), and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled. The ICH10 has implemented Soft Straps. Soft Straps are used to configure specific functions within the ICH and (G)MCH very early in the boot process before BIOS or SW intervention. When Descriptor Mode is enabled, the ICH will read Soft Strap data out of the SPI device prior to the de-assertion of reset to both the Intel Management Engine and the Host system. Refer to Section 5.23.2 for information on Descriptor Mode and Section for more information on Soft Straps and their settings. Table 2-25. Functional Strap Definitions (Sheet 1 of 4) Signal HDA_SDOUT Usage XOR Chain Entrance PCI Express* Port Config 1 bit 1 (Port 1-4) (Consumer Only) PCI Express Port Config 1 bit 0 (Port 1-4) PCI Express Port Config 2 bit 2 (Port 5-6) Reserved When Sampled Rising Edge of PWROK Comment Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK. When TP3 not pulled low at rising edge of PWROK, sets bit 1 of RPC.PC (Chipset Config Registers:Offset 224h).This signal has a weak internal pull-down. This signal has a weak internal pull-down. Sets bit 0 of RPC.PC (Chipset Config Registers:Offset 224h) This signal has a weak internal pull-up. Sets bit 2 of RPC.PC2 (Chipset Config Registers:Offset 0224h) when sampled low. This signal has a weak internal pull-down. NOTE: This signal should not be pulled high Tying this strap low configures DMI for ESIcompatible operation. This signal has a weak internal pull-up. NOTE: ESI compatible mode is for server platforms only. This signal should not be pulled low for desktop. The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the “topblock swap” mode (Intel ICH10 inverts A16 for all cycles targeting BIOS space). The status of this strap is readable via the Top Swap bit (Chipset Config Registers:Offset 3414h:bit 0). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. HDA_SDOUT Rising Edge of PWROK HDA_SYNC (Consumer Only) GNT2# / GPIO53 (Consumer Only) GPIO20 Rising Edge of PWROK Rising Edge of PWROK Rising Edge of PWROK GNT1#/GPIO51 ESI Strap (Server/ Workstation Only) Rising edge of PWROK GNT3# / GPIO55 Top-Block Swap Override Rising Edge of PWROK Datasheet 75 Signal Description Table 2-25. Functional Strap Definitions (Sheet 2 of 4) Signal Usage When Sampled Comment This field determines the destination of accesses to the BIOS memory range. Signals have weak internal pull-ups. Also controllable via Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 11). This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. Bit11 0 1 GNT0# Boot BIOS Destination Selection 0 Rising Edge of PWROK 1 0 Bit 10 1 0 1 0 Boot BIOS Destination SPI PCI LPC Reserved NOTE: If option 11 LPC is selected, BIOS may still be placed on LPC, but all platforms with ICH10 (Corporate Only) require SPI flash connected directly to the ICH's SPI bus with a valid descriptor in order to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel Management Engine or Integrated GbE LAN. 76 Datasheet Signal Description Table 2-25. Functional Strap Definitions (Sheet 3 of 4) Signal Usage When Sampled Comment This field determines the destination of accesses to the BIOS memory range. Signals have weak internal pull-ups. Also controllable via Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap. Bit11 0 1 SPI_CS1# Boot BIOS Destination Selection 1 Rising Edge of CLPWROK 1 0 Bit 10 1 0 1 0 Boot BIOS Destination SPI PCI LPC Reserved NOTE: If option 11 LPC is selected BIOS may still be placed on LPC, but all platforms with ICH10 (Corporate Only) require SPI flash connected directly to the ICH's SPI bus with a valid descriptor in order to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel Management Engine or Integrated GbE LAN. Signal has weak internal pull-up. Sets bit 27 of MPC.LR (Device 28: Function 0: Offset D8) The signal has a weak internal pull-down. If the signal is sampled high, this indicates that the system is strapped to the “No Reboot” mode (ICH10 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO REBOOT bit (Chipset Config Registers:Offset 3410h:bit 5). See Intel® ICH10 Family XOR Chains InCircuit Tester Package for functionality information. This signal has a weak internal pull-up. NOTE: This signal should not be pulled low unless using XOR Chain testing. SATALED# (Consumer Only) PCI Express Lane Reversal (Lanes 1-4) Rising Edge of PWROK SPKR No Reboot Rising Edge of PWROK TP3 XOR Chain Entrance Rising Edge of PWROK Datasheet 77 Signal Description Table 2-25. Functional Strap Definitions (Sheet 4 of 4) Signal Usage When Sampled Comment If sampled low, the Flash Descriptor Security will be overridden. If high, the security measures defined in the Flash Descriptor will be in effect. NOTE: This strap should only be enabled in manufacturing environments using an external pull-down resistor. NOTE: Asserting the GPIO33 low on the rising edge of PWROK will also disable Intel Management Engine and Intel Management Engine features. This signal has a weak internal pull-up. NOTE: When DMI is DC coupled this signal should not be pulled low during the time the strap is sampled. NOTE: When DMI is AC coupled, this signal should be pulled low during the time the strap is sampled. This signal has a weak internal pull-down resistor. When the signal is sampled low the Integrated TPM will be disabled. When the signal is sampled high, the (G)MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enabled. NOTE: For Consumer applications this signal is required to be floating or pulled low. GPIO33 / HDA_DOCK_EN# Flash Descriptor Security Override Strap Rising Edge of PWROK GPIO49 DMI Termination Voltage Rising Edge of PWROK SPI_MOSI (Corporate Only) Integrated TPM Enable Rising Edge of CLPWROK NOTE: See Section 3.1 for full details on pull-up/pull-down resistors. 78 Datasheet Signal Description 2.25.2 External RTC Circuitry The ICH10 implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC. Figure 2-1 shows an example schematic recommended to ensure correct operation of the ICH10 RTC. Figure 2-1. Example External RTC Circuit 3.3V Sus VCCRTC Schottky Diodes 1 KΩ Vbatt 20 KΩ 20 KΩ 1uF 0.1uF RTCX2 32.768 KHz Xtal R1 10MΩ RTCX1 1.0 uF 1.0 uF C1 C2 RTCRST# SRTCRST# NOTE: C1 and C2 depend on crystal load. §§ Datasheet 79 Signal Description 80 Datasheet Intel® ICH10 Pin States 3 3.1 Table 3-1. Intel® ICH10 Pin States Integrated Pull-Ups and Pull-Downs Integrated Pull-Up and Pull-Down Resistors Signal CL_CLK0 CL_DATA0 CL_RST0# DPRSLPVR/GPIO16 HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GLAN_DOCK# GNT0#, GNT[3:1]#/GPIO[55,53,51] GPIO20 GPIO49 LAD[3:0]# / FHW[3:0]# LAN_RXD[2:0] LDRQ0 LDRQ1 / GPIO23 PME# PWRBTN# SATALED# SPI_CS1# SPI_MOSI SPI_MISO SPKR TACH[3:0] TP3 USB[11:0] [P,N] Resistor Type Pull-up Pull-up Pull-up Pull-down Pull-down Pull-up Pull-down Pull-down Pull-down Pull-down Pull-up PUll-down Pull-up Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-down Pull-up Pull-down Pull-up Pull-up Pull-down Nominal Value 20 kΩ 20 kΩ 10 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 15 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ 15 kΩ Notes 13 13 4 2, 10 1, 9 3,7 2 2 2, 7 2, 7 3, 14 3, 11, 12 3, 7 3, 7 3 4 3 3 3 3 8 3, 10 3, 7 3 2 3 6 5 NOTES: 1. Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ. 2. Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ. Datasheet 81 Intel® ICH10 Pin States 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Simulation data shows that these resistor values can range from 15 kΩ to 35 kΩ. Simulation data shows that these resistor values can range from 7.5 kΩ to 16 kΩ. Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ Simulation data shows that these resistor values can range from 10 kΩ to 30 kΩ. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ. The internal pull-up is only enabled during PLTRST# assertion. The pull-down on this signal is only enabled when in S3. The pull-up or pull-down on this signal is only enabled during reset. The pull-up on this signal is not enabled when PCIRST# is high. The pull-up on this signal is not enabled when PWROK is low. Simulation data shows that these resistor values can range from 15 kΩ to 31 kΩ. The pull-up or pull-down on this pin is only active when configured for native GLAN_DOCK# functionality and is determined by the LAN controller. 82 Datasheet Intel® ICH10 Pin States 3.2 Output and I/O Signals Planes and States Table 3-2 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: “High-Z” “High” “Low” “Defined” “Undefined” “Running” “Off” “Input” Tri-state. ICH10 not driving the signal high or low. ICH10 is driving the signal to a logic 1. ICH10 is driving the signal to a logic 0. Driven to a level that is defined by the function or external pullup/pull-down resistor (will be high or low). ICH10 is driving the signal, but the value is indeterminate. Clock is toggling or signal is transitioning because function not stopping. The power plane is off; ICH10 is not driving when configured as an output or sampling when configured as an input. ICH10 is sampling and signal state determined by external driver. Note: Signal levels are the same in S4 and S5, except as noted. The ICH10 suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4#, S4_STATE# and SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion. The ICH10 core well signal states are indeterminate and undefined and may glitch prior to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK assertion. Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 1 of 5) Power Plane During Reset4 Immediately after Reset4 PCI Express* C3/C4 S1 S3 S4/S5 Signal Name PETp[5:1], PETn[5:1], PETp6 / GLANTXp, PETn6 / GLANTXn Core High High8 Defined Off Off DMI DMI[3:0]TXP, DMI[3:0]TXN Core High High PCI Bus AD[31:0] C/BE[3:0]# DEVSEL# FRAME# GNT0#11, GNT[3:1]#11/ GPIO[55, 53, 51] IRDY#, TRDY# Core Core Core Core Core Core Low Low High-Z High-Z High-Z High-Z Undefined Undefined High-Z High-Z High High-Z Defined Defined High-Z High-Z High High-Z Off Off Off Off Off Off Off Off Off Off Off Off Defined Off Off Datasheet 83 Intel® ICH10 Pin States Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 2 of 5) Power Plane Core Suspend Core Core Core During Reset4 Low Low High-Z High-Z High-Z Immediately after Reset4 Undefined High High-Z High-Z High-Z LPC Interface C3/C4 S1 Defined High High-Z High-Z High-Z S3 Off Low Off Off Off S4/S5 Off Low Off Off Off Signal Name PAR PCIRST# PERR# PLOCK# STOP# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LPCPD# / SUS_STAT# / GPIO61 (Corporate Only) Core Core Suspend High High Low High High High Firmware Hub High High High Off Off Low Off Off Low INIT3_3V# Core High High High Off Off LAN Connect Interface LAN_RSTSYNC LAN_TXD[2:0] LAN LAN High Low Low Low Defined Defined Defined Defined Defined Defined Gigabit LAN Connect Interface GLAN_TXp / PETp6, GLAN_TXn / PETn6 LAN_RSTSYNC GLAN LAN High High High Low SATA Interface SATA[5:0]TXP, SATA[5:0]TXN SATALED#11 SATARBIAS SATACLKREQ# / GPIO35 SCLOCK/GPIO22 SLOAD/GPIO38 SDATAOUT[1:0]/ GPIO[48,39] Core Core Core Core Core Core Core High-Z High-Z High-Z Low Input Input Input High-Z High-Z High-Z Low Input Input Input Interrupts PIRQ[A:D]#, PIRQ[H:E]# / GPIO[5:2] SERIRQ Core Core Core High-Z Input High-Z High-Z Input High-Z USB Interface USB[11:0][P,N] USBRBIAS Suspend Suspend Low High-Z Low High-Z Power Management DPRSLPVR Core Low Low High Off Off Defined Defined Defined Defined Defined Defined High-Z Defined High-Z Off Off Off Off Off Off Defined Defined Defined Defined Defined Defined Defined Off Off Off Off Off Off Off Off Off Off Off Off Off Off Defined Defined Off Defined Off Defined 84 Datasheet Intel® ICH10 Pin States Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 3 of 5) Power Plane CPU Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend During Reset4 High Low Low Low Low Low Low Low Low Low High High Low High High High Low Processor Interface Defined Immediately after Reset4 High High High High High Defined High High C3/C4 S1 High High High High High Defined High High Running High Defined Defined Defined Low Defined Defined Defined/ Low12 Low Defined Defined Defined/ Low12 S3 Off Low Defined Low High Defined High Low S4/S5 Off Low Defined Low Defined Defined Low6 Low Signal Name DPRSTP# PLTRST# SLP_M#9 SLP_S3# SLP_S4# S4_STATE# / GPIO26 SLP_S5#/ GPIO63 (Corporate Only) SUS_STAT# / LPCPD# / GPIO61 (Corporate Only) SUSCLK CK_PWRGD STP_PCI# / GPIO15 STP_CPU# / GPIO25 (Corporate Only) Corporate Only: DRAMPWROK / GPIO8 DPSLP# A20M# CPUPWRGD IGNNE# INIT# INTR NMI SMI# STPCLK# CPU CPU CPU CPU CPU CPU CPU CPU CPU High Dependant on A20GATE Signal Low3 High High See Note 5 See Note 5 High High High See Note 1 High See Note 1 High See Note 5 See Note 5 High High SMBus Interface High High High High High Low Low High Low Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined System Management Interface MEM_LED / GPIO24 CPU_MISSING / GPIO10 / JTAGTMS (Corporate Only) GPIO14 / JTAGTDI (Corporate Only) / QST_BMBUSY# WOL_EN / GPIO9 Suspend Suspend Low Input Low Input Defined Defined Defined Defined Defined Defined Suspend Suspend Input High-Z Input High-Z Defined Defined Defined Defined Defined Defined Datasheet 85 Intel® ICH10 Pin States Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 4 of 5) Power Plane Suspend During Reset4 High-Z Immediately after Reset4 High-Z C3/C4 S1 S3 S4/S5 Signal Name LINKALERT# / GPIO60 / JTAGRST# (Corporate Only) TPM_PP / GPIO57 / JTAGTCK (Corporate Only) SPI_CS[1]#11 SMLINK[1:0] 11 Defined Defined Defined Suspend Suspend Suspend Input High High-Z Input High High-Z Defined Defined Defined Defined Defined Defined Defined Defined Defined Miscellaneous Signals SPKR Core High-Z Intel® HDA_RST# HDA_SDOUT11 HDA_SYNC HDA_BIT_CLK HDA Suspend HDA HDA HDA Low Defined Off Off High Definition Audio Interface Low7 Low Low Low Defined Low Low Low Low Off Off Off Low Off Off Off Low Low Low Low UnMultiplexed GPIO Signals GPIO0 / BMBUSY# Consumer Only: GPIO8 GPIO12 / LAN_PHY_PWR_CTRL GPIO13 GPIO16/DPRSLPVR GPIO18 GPIO2011 GPIO[28:27] GPIO3311, GPIO32 GPIO34 GPIO49 11 Core Suspend Suspend Suspend Core Core Core Suspend Core HDA Core Suspend Input Input Low Input Low High Low Low High Low High Input Input Input Low Input Low See Note 2 High Low High Low High Input SPI Interface Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Off Defined Defined Defined Off Off Off Defined Off Off Off Defined Off Defined Defined Defined Off Off Off Defined Off Off Off Defined GPIO56 SPI_CS0# SPI_CS1#11 SPI_MOSI11 SPI_CLK Controller Link Controller Link Controller Link Controller Link High High Low Low High High Low Low Controller Link Defined Defined Defined Running Defined Defined Defined Defined Defined Defined Defined Defined CL_CLK0 Controller Link Low Low Defined10 Defined10 Defined10 86 Datasheet Intel® ICH10 Pin States Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 5 of 5) Power Plane Controller Link Suspend During Reset4 Low Low Intel ® Signal Name CL_DATA0 CL_RST0# Immediately after Reset4 Low High C3/C4 S1 Defined10 Defined10 S3 Defined10 Defined10 S4/S5 Defined10 Defined10 Quiet System Technology Low Low Low Defined Defined Defined Off Off Off Off Off Off PWM[2:0] SST PECI Core Controller Link CPU High-Z High-Z High-Z NOTES: 1. ICH10 drives these signals High after the processor Reset 2. GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH10 comes out of reset 3. CPUPWRGD represents a logical AND of the ICH10’s VRMPWRGD and PWROK signals, and thus will be driven low by ICH10 when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z. 4. The states of Core and processor signals are evaluated at the times During PLTRST# and Immediately after PLTRST#. The states of the LAN and GLAN signals are evaluated at the times During LAN_RST# and Immediately after LAN_RST#. The states of the Controller Link signals are taken at the times During CL_RST# and Immediately after CL_RST#. The states of the Suspend signals are evaluated at the times During RSMRST# and Immediately after RSMRST#. The states of the HDA signals are evaluated at the times During HDA_RST# and Immediately after HDA_RST#. 5. ICH10 drives these signals Low before PWROK rising and Low after the processor Reset. 6. SLP_S5# signals will be high in the S4 state. 7. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be Running. 8. PETp/n[6:1] high until port is enabled by software. 9. The SLP_M# state will be determined by Intel AMT Policies. 10. The state of signals in S3-5 will be defined by Intel AMT Policies. 11. This signal is sampled as a functional strap during reset. 12. The state of DRAMPWROK during S3/S4/S5 is dependent on the SLP_S4# and CLPWROK signals. Datasheet 87 Intel® ICH10 Pin States 3.3 Power Planes for Input Signals Table 3-3 shows the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include: High Low Static: Will be high or low, but will not change Driven: Will be high or low, and is allowed to change Running: For input clocks The ICH10 suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4#, S4_STATE# and SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion. The ICH10 core well signal states are indeterminate and undefined and may glitch prior to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK assertion. Table 3-3. Power Plane for Input Signals for Configurations (Sheet 1 of 3) Power Well Driver During Reset DMI C3/C4 S1 S3 S4/S5 Signal Name DMI_CLKP, DMI_CLKN DMI[3:0]RXP, DMI[3:0]RXN Core Core Clock Generator (G)MCH PCI Express* Running Driven Off Off Off Off PERp[5:1], PERn[5:1], PERp6 / GLAN_RXp, PERn6 / GLAN_RXn Core PCI Express* Device Driven Off Off PCI Bus REQ0#, REQ1# / GPIO501 REQ2# / GPIO521 REQ3# / GPIO541 PCICLK PME# SERR# Core Core Suspend Core External Pull-up Clock Generator Internal Pull-up PCI Bus Peripherals LPC Interface Driven Running Driven High Off Off Driven Off Off Off Driven Off LDRQ0# LDRQ1# / GPIO231 Core Core LPC Devices LPC Devices LAN Connect Interface High High Off Off Off Off GLAN_CLK LAN_RXD[2:0] Suspend Suspend LAN Connect Component LAN Connect Component Driven Driven Off Driven Off Driven 88 Datasheet Intel® ICH10 Pin States Table 3-3. Power Plane for Input Signals for Configurations (Sheet 2 of 3) Power Well Driver During Reset C3/C4 S1 S3 S4/S5 Signal Name Gigabit LAN Connect Interface GLAN_RXp / PERp6, GLAN_RXn / PERn6 Suspend Gigabit Lan Connect Component SATA Interface SATA_CLKP, SATA_CLKN SATA[5:0]RXP, SATA[5:0]RXN SATARBIAS# SATA[5:4]GP SATA[3:0]GP / GPIO[37, 36, 19, 21]1 Core Core Core Core Clock Generator SATA Drive External Pull-down External Device or External Pull-up/Pulldown USB Interface OC0# / GPIO59, OC[4:1]# / GPIO[43:40], OC[7:5]# / GPIO [31:29], OC[11:8]# / GPIO[47:44] USBRBIAS# Running Driven Driven Driven Off Off Off Off Off Off Off Off Driven Off Off Suspend External Pull-ups Driven Driven Driven Suspend External Pull-down Power Management Driven Driven Driven BMBUSY# /GPIO01 CLPWROK LAN_RST# MCH_SYNC# PWRBTN# PWROK RI# RSMRST# SYS_RESET# THRM# THRMTRIP# VRMPWRGD WAKE# Core Suspend Suspend Core Suspend RTC Suspend RTC Suspend Core CPU Suspend Suspend Graphics Component [(G)MCH] External Circuit External Circuit (G)MCH Internal Pull-up System Power Supply Serial Port Buffer External RC Circuit External Circuit Thermal Sensor Thermal Sensor Processor Voltage Regulator External Pull-up Processor Interface Driven Driven High Driven Driven Driven Driven High Driven Driven Driven High Driven High Driven High Off Driven Off Driven High Driven Off Off Low Driven Off Driven High Off Driven Off Driven High Driven Off Off Low Driven A20GATE FERR# RCIN# Core Core Core External Microcontroller Processor External Microcontroller Static Static High Off Off Off Off Off Off Datasheet 89 Intel® ICH10 Pin States Table 3-3. Power Plane for Input Signals for Configurations (Sheet 3 of 3) Power Well Driver During Reset SMBus Interface C3/C4 S1 S3 S4/S5 Signal Name SMBALERT# / GPIO11 / JTAGTDO1 (Corporate Only) Suspend External Pull-up System Management Interface Driven Driven Driven INTRUDER# RTC External Switch Miscellaneous Signals Driven High High INTVRMEN LAN100_SLP RTCRST# SRTCRST# RTC RTC RTC RTC Controller Link External Pull-up External Pull-up External RC Circuit External RC Circuit Consumer Only: External Circuit2 Corporate Only: Internal Circuit3 External Pull-up High High High High High High High High High High High High CL_VREF0 Driven Driven Driven TP0 / GPIO72 (Corporate Only) Suspend High High High Intel® High Definition Audio Interface HDA_SDIN[3:0] Suspend Intel High Definition Audio Codec SPI Interface SPI_MISO Controller Link Internal Pull-up Intel® Quiet System Technology TACH[3:0]/ GPIO[7,6,1,17]1 Core External Pull-up Clocks CLK14 CLK48 Core Core Clock Generator Clock Generator Running Running Off Off Off Off Driven Off Off Driven Driven Driven Low Low Low NOTES: 1. These signals can be configured as outputs in GPIO mode.The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled or low if it is disabled. 2. Consumer Only: CL_VREF0 is driven by an external circuit except on platforms where the MCH does not support Controller Link. In these platforms, the signal is not driven. 3. Corporate Only: CL_VREF0 may optionally be driven by an external circuit, as configured by CLINKVREFSEL (ICHSTRP0:bit 5). §§ 90 Datasheet Intel® ICH10 and System Clock Domains 4 Intel® ICH10 and System Clock Domains Table 4-1 shows the system clock domains. Figure 4-1 shows the assumed connection of the various system components, including the clock generator. For complete details of the system clocking solution, refer to the system’s clock generator component specification. Table 4-1. Intel® ICH10 and System Clock Domains Clock Domain ICH10 SATA_CLKP, SATA_CLKN ICH10 DMI_CLKP, DMI_CLKN ICH10 PCICLK System PCI ICH10 CLK48 ICH10 CLK14 GLAN_CLK SPI_CLK Frequency Source Main Clock Generator Main Clock Generator Main Clock Generator Main Clock Generator Main Clock Generator Main Clock Generator LAN Connect Component ICH Usage 100 MHz Differential clock pair used for SATA. 100 MHz Differential clock pair used for DMI. Free-running PCI Clock to Intel ICH10. This clock remains on during S0 and S1 state, and is expected to be shut off during S3 or below. PCI Bus, LPC I/F. These only go to external PCI and LPC devices. Super I/O, USB controllers. Expected to be shut off during S3. Used for ACPI timer and HPET timers. Expected to be shut off during S3. Generated by the LAN Connect component. Expected to be shut off during S3. Generated by the ICH. Expected to be shut off during S3. 33 MHz 33 MHz 48.000 MHz 14.31818 MHz 5 to 62.5 MHz 17.86 MHz/ 31.25 MHz Datasheet 91 Intel® ICH10 and System Clock Domains Figure 4-1. ICH10 Conceptual System Clock Diagram 33 MHz 14.31818 MHz 48.000 MHz STP_CPU# STP_PCI# PCI Clocks (33 MHz) Clock Gen. 14.31818 MHz 48 MHz Intel ICH10 ® SATA 100 MHz Diff. Pair DMI 100 MHz Diff. Pair 100 MHz Diff. Pair 1 to 6 Differential Clock Fan Out Device PCI Express 100 MHz Diff. Pairs 62.5 MHz 24 MHz 32 kHz XTAL SUSCLK# (32 kHz) §§ LAN Connect HD Audio Codec(s) §§ § 92 Datasheet Functional Description 5 5.1 Functional Description This chapter describes the functions and interfaces of the Intel ICH10 family. DMI-to-PCI Bridge (D30:F0) The DMI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH10 implements the buffering and control logic between PCI and Direct Media Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the DMI. All register contents are lost when core well power is removed. Direct Media Interface (DMI) is the chip-to-chip connection between the Memory Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub 10 (ICH10). This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally. To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions, the ICH10 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both ends of the DMI link (i.e., the ICH10 and (G)MCH). Configuration registers for DMI, virtual channel support, and DMI active state power management (ASPM) are in the RCRB space in the Chipset Config Registers (Chapter 10). DMI is also capable of operating in an Enterprise Southbridge Interface (ESI) compatible mode. ESI is a chip-to-chip connection for server chipsets. In this ESIcompatible mode, the DMI signals require AC coupling. A hardware strap is used to configure DMI in ESI-compatible mode see Section 2.25 for details. 5.1.1 PCI Bus Interface The ICH10 PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz. The ICH10 integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal ICH10 requests. 5.1.2 PCI Bridge As an Initiator The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge generates the cycle types listed in Table 5-1. Table 5-1. PCI Bridge Initiator Cycle Types Command I/O Read/Write Memory Read/Write Configuration Read/Write Special Cycles C/BE# 2h/3h 6h/7h Ah/Bh 1h Notes Non-posted Writes are posted Non-posted Posted Datasheet 93 Functional Description 5.1.2.1 Memory Reads and Writes The bridge bursts memory writes on PCI that are received as a single packet from DMI. 5.1.2.2 I/O Reads and Writes The bridge generates single DW I/O read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.3 Configuration Reads and Writes The bridge generates single DW configuration read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.4 Locked Cycles The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI bridge implements bus lock, which means the arbiter will not grant to any agent except DMI while locked. If a locked read results in a target or master abort, the lock is not established (as per the PCI Local Bus Specification). Agents north of the ICH10 must not forward a subsequent locked read to the bridge if they see the first one finish with a failed completion. 5.1.2.5 Target / Master Aborts When a cycle initiated by the bridge is master/target aborted, the bridge will not reattempt the same cycle. For multiple DW cycles, the bridge increments the address and attempts the next DW of the transaction. For all non-postable cycles, a target abort response packet is returned for each DW that was master or target aborted on PCI. The bridge drops posted writes that abort. 5.1.2.6 Secondary Master Latency Timer The bridge implements a Master Latency Timer via the SMLT register which, upon expiration, causes the de-assertion of FRAME# at the next legal clock edge when there is another active request to use the PCI bus. 5.1.2.7 Dual Address Cycle (DAC) The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4 GB. 94 Datasheet Functional Description 5.1.2.8 Memory and I/O Decode to PCI The PCI bridge in the ICH10 is a subtractive decode agent, which follows the following rules when forwarding a cycle from DMI to the PCI interface: • The PCI bridge will positively decode any memory/IO address within its window registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for IO windows. • The PCI bridge will subtractively decode any 64-bit memory address not claimed by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set. • The PCI bridge will subtractively decode any 16-bit I/O address not claimed by another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set. • If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively forward from primary to secondary called out ranges in the IO window per PCI Local Bus Specification (I/O transactions addressing the last 768 bytes in each, 1 KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively assuming the above rules. • If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively forward from primary to secondary I/O and memory ranges as called out in the PCI Bridge Specification, assuming the above rules are met. 5.1.3 Parity Error Detection and Generation PCI parity errors can be detected and reported. The following behavioral rules apply: • When a parity error is detected on PCI, the bridge sets the SECSTS.DPE (D30:F0:Offset 1Eh:bit 15). • If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) is set and one of the parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD (D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#. — During a write cycle, the PERR# signal is active, or — A data parity error is detected while performing a read cycle • If an address or command parity error is detected on PCI and PCICMD.SEE (D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1) are all set, the bridge will set PSTS.SSE (D30:F0:Offset 06h:bit 14) and generate an internal SERR#. • If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is set, the bridge will generate an internal SERR# • When bad parity is detected from DMI, bad parity will be driven on all data from the bridge. • When an address parity error is detected on PCI, the PCI bridge will never claim the cycle. This is a slight deviation from the PCI bridge specification, which says that a cycle should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction. Datasheet 95 Functional Description 5.1.4 PCIRST# The PCIRST# pin is generated under two conditions: • PLTRST# active • BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1 The PCIRST# pin is in the suspend well. PCIRST# should be tied to PCI bus agents, but not other agents in the system. 5.1.5 Peer Cycles The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, IO, and configuration cycle types. Peer cycles are only allowed through VC0, and are enabled with the following bits: • BPC.PDE (D30:F0:Offset 4Ch:bit 2) – Memory and I/O cycles • BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles When enabled for peer for one of the above cycle types, the PCI bridge will perform a peer decode to see if a peer agent can receive the cycle. When not enabled, memory cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles are not claimed. Configuration cycles have special considerations. Under the PCI Local Bus Specification, these cycles are not allowed to be forwarded upstream through a bridge. However, to enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are allowed into the part. The address format of the type 1 cycle is slightly different from a standard PCI configuration cycle to allow addressing of extended PCI space. The format is shown in Table 5-2. Table 5-2. Type 1 Address Format Bits 31:27 26:24 23:16 15:11 10:8 7:2 1 0 Definition Reserved (same as the PCI Local Bus Specification) Extended Configuration Address – allows addressing of up to 4K. These bits are combined with bits 7:2 to get the full register. Bus Number (same as the PCI Local Bus Specification) Device Number (same as the PCI Local Bus Specification) Function Number (same as the PCI Local Bus Specification) Register (same as the PCI Local Bus Specification) 0 Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded. Note: The ICH10’s USB controllers cannot perform peer-to-peer traffic. 5.1.6 PCI-to-PCI Bridge Model From a software perspective, the ICH10 contains a PCI-to-PCI bridge. This bridge connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH10 can have its decode ranges programmed by existing plug-and-play software such that PCI ranges do not conflict with graphics aperture ranges in the Host controller. 96 Datasheet Functional Description 5.1.7 IDSEL to Device Number Mapping When addressing devices on the external PCI bus (with the PCI slots), the ICH10 asserts one address signal as an IDSEL. When accessing device 0, the ICH10 asserts AD16. When accessing Device 1, the ICH10 asserts AD17. This mapping continues all the way up to device 15 where the ICH10 asserts AD31. Note that the ICH10’s internal functions (Intel High Definition Audio, USB, SATA and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus. 5.1.8 Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the ICH10. The PCI Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration space, Mechanism 1 and Mechanism 2. The ICH10 only supports Mechanism 1. Warning: Configuration writes to internal devices, when the devices are disabled, are invalid and may cause undefined results. 5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) There are six root ports available in ICH10. These all reside in device 28, and take function 0 – 5. Port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is function 3, port 5 is function 4, and port 6 is function 5. PCI Express Root Ports 1-4 can be statically configured as four x1 Ports or ganged together to form one x4 port. Ports 5 and 6 can only be used as two x1 ports. The port configuration is set by RCBA 224h [Bits 1:0] see Section 10.1.38 for more details. 5.2.1 Interrupt Generation The root port generates interrupts on behalf of Hot-Plug and power management events, when enabled. These interrupts can either be pin based, or can be MSIs, when enabled. When an interrupt is generated via the legacy pin, the pin is internally routed to the ICH10 interrupt controllers. The pin that is driven is based upon the setting of the chipset configuration registers. Specifically, the chipset configuration registers used are the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers. Datasheet 97 Functional Description Table 5-3 summarizes interrupt behavior for MSI and wire-modes. In the table “bits” refers to the Hot-Plug and PME interrupt bits. Table 5-3. MSI versus PCI IRQ Actions Interrupt Register All bits 0 One or more bits set to 1 One or more bits set to 1, new bit gets set to 1 One or more bits set to 1, software clears some (but not all) bits One or more bits set to 1, software clears all bits Software clears one or more bits, and one or more bits are set on the same clock Wire-Mode Action Wire inactive Wire active Wire active Wire active Wire inactive Wire active MSI Action No action Send message Send message Send message No action Send message 5.2.2 5.2.2.1 Power Management S3/S4/S5 Support Software initiates the transition to S3/S4/S5 by performing an IO write to the Power Management Control register in the ICH10. After the IO write completion has been returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction Layer Packet) message on its downstream link. The device attached to the link will eventually respond with a PME_TO_Ack TLP message followed by sending a PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state. When all of the ICH10 root ports links are in the L2/L3 Ready state, the ICH10 power management control logic will proceed with the entry into S3/S4/S5. Prior to entering S3, software is required to put each device into D3HOT. When a device is put into D3HOT it will initiate entry into a L1 link state by sending a PM_Enter_L1 DLLP. Thus under normal operating conditions when the root ports sends the PME_Turn_Off message the link will be in state L1. However, when the root port is instructed to send the PME_Turn_Off message, it will send it whether or not the link was in L1. Endpoints attached to ICH can make no assumptions about the state of the link prior to receiving a PME_Turn_Off message. 5.2.2.2 Resuming from Suspended State The root port contains enough circuitry in the suspend well to detect a wake event through the WAKE# signal and to wake the system. When WAKE# is detected asserted, an internal signal is sent to the power management controller of the ICH10 to cause the system to wake up. This internal message is not logged in any register, nor is an interrupt/GPE generated due to it. 5.2.2.3 Device Initiated PM_PME Message When the system has returned to a working state from a previous low power state, a device requesting service will send a PM_PME message continuously, until acknowledge by the root port. The root port will take different actions depending upon whether this is the first PM_PME has been received, or whether a previous message has been received but not yet serviced by the operating system. 98 Datasheet Functional Description If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into RSTS.RID (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bits 15:0). If an interrupt is enabled via RCTL.PIE (D28:F0/F1/F2/F3/F4/F5:Offset 5Ch:bit 3), an interrupt will be generated. This interrupt can be either a pin or an MSI if MSI is enabled via MC.MSIE (D28:F0/F1/ F2/F3/F4/F5:Offset 82h:bit 0). See Section 5.2.2.4 for SMI/SCI generation. If this is a subsequent message received (RSTS.PS is already set), the root port will set RSTS.PP (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 17) and log the PME Requester ID from the message in a hidden register. No other action will be taken. When the first PME event is cleared by software clearing RSTS.PS, the root port will set RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into RSTS.RID. If RCTL.PIE is set, an interrupt will be generated. If RCTL.PIE is not set, a message will be sent to the power management controller so that a GPE can be set. If messages have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt will be generated. This last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state. 5.2.2.4 SMI/SCI Generation Interrupts for power management events are not supported on legacy operating systems. To support power management on non-PCI Express aware operating systems, PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set. When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/ F5:Offset DCh:bit 31) to be set. Additionally, BIOS workarounds for power management can be supported by setting MPC.PMME (D28:F0/F1/F2/F3/F4/F5:Offset D8h:bit 0). When this bit is set, power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 0), and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI is enabled. The SMI# may occur concurrently with an interrupt or SCI. 5.2.3 SERR# Generation SERR# may be generated via two paths – through PCI mechanisms involving bits in the PCI header, or through PCI Express* mechanisms involving bits in the PCI Express capability structure. Figure 5-1. Generation of SERR# to Platform Secondary Parity Error PCI Primary Parity Error Secondary SERR# PCICMD.SEE Correctable SERR# PCI Express Fatal SERR# Non-Fatal SERR# PSTS.SSE SERR# Datasheet 99 Functional Description 5.2.4 Hot-Plug Each root port implements a Hot-Plug controller which performs the following: • Messages to turn on / off / blink LEDs • Presence and attention button detection • Interrupt generation The root port only allows Hot-Plug with modules (e.g., ExpressCard*). Edge-connector based Hot-Plug is not supported. 5.2.4.1 Presence Detection When a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/ F5:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3F4/ F5:Offset 58h:bit 5) are both set, the root port will also generate an interrupt. When a module is removed (via the physical layer detection), the root port clears SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an interrupt. 5.2.4.2 Message Generation When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits 7:6) or SLCTL.PIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits 9:8), the root port will send a message down the link to change the state of LEDs on the module. Writes to these fields are non-postable cycles, and the resulting message is a postable cycle. When receiving one of these writes, the root port performs the following: • Changes the state in the register. • Generates a completion into the upstream queue • Formulates a message for the downstream port if the field is written to regardless of if the field changed. • Generates the message on the downstream port • When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/ F2/F3F4/F5:Offset 58h:bit 4) to indicate the command has completed. If SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 5) are set, the root port generates an interrupt. The command completed register (SLSTS.CC) applies only to commands issued by software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC), or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control Register would invariably end up writing to the indicators, power controller fields; Hence, any write to the Slot Control Register is considered a command and if enabled, will result in a command complete interrupt. The only exception to this rule is a write to disable the command complete interrupt which will not result in a command complete interrupt. A single write to the Slot Control register is considered to be a single command, and hence receives a single command complete, even if the write affects more than one field in the Slot Control Register. 100 Datasheet Functional Description 5.2.4.3 Attention Button Detection When an attached device is ejected, an attention button could be pressed by the user. This attention button press will result in a the PCI Express message “Attention_Button_Pressed” from the device. Upon receiving this message, the root port will set SLSTS.ABP (D28:F0/F1/F2/F3F4/F5:Offset 5Ah:bit 0). If SLCTL.ABE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/ F3F4/F5:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is already set, a new interrupt will not be generated. 5.2.4.4 SMI/SCI Generation Interrupts for Hot-Plug events are not supported on legacy operating systems. To support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS (D28:F0/F1/F2/F3F4/F5:Offset DCh:bit 30) to be set. Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME (D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 1). When this bit is set, Hot-Plug events can cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their corresponding SMSCS bit are: • Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 3) • Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 1) • Attention Button Pressed - SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 2) • Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 4) When any of these bits are set, SMI # will be generated. These bits are set regardless of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur concurrently with an interrupt or SCI. 5.3 Gigabit Ethernet Controller (B0:D25:F0) The ICH10 integrates a Gigabit Ethernet Controller. The integrated Gigabit Ethernet controller is compatible with Gigabit Ethernet PHY (Intel® 82567 Gigabit Platform LAN Connect device). The integrated Gigabit Ethernet controller provides two interfaces: LAN Connect Interface (LCI) for 10/100 operation and Gigabit LAN Connect Interface (GLCI) for Gigabit Ethernet operation. The GLCI is shared with the ICH10’s PCI Express port 6 and can be enabled via a soft strap that is stored in system SPI flash, see Section for details. The ICH10 integrated Gigabit Ethernet controller supports multi speed operation, 10/100/1000 MB/s. The integrated Gigabit Ethernet can operate in full-duplex at all supported speeds or half-duplex at 10/100 MB/s, and adheres with the IEEE 802.3x Flow Control Specification. Note: Gigabit Ethernet (1000Mb/s) is only supported in S0. The controller provides a system interface via a PCI function. A full memory-mapped or IO-mapped interface is provided to the software, along with DMA mechanisms for high performance data transfer. Datasheet 101 Functional Description The following summarizes the ICH10 integrated Gigabit Ethernet controller features: • Configurable LED operation for customization of LED display. • IPv4 and IPv6 Checksum Offload support (receive, transmit, and large send). • 64-bit address master support for system using more than 4 GB of physical memory. • Configurable receive and transmit data FIFO, programmable in 1 KB increments. • Intelligent interrupt generation to enhance driver performance. • Compliance with Advanced Configuration and Power Interface and PCI Power Management standards. • ACPI register set and power down functionality supporting D0 and D3 states. • Full wake-up support (APM and ACPI). • Magic Packet wake-up enable with unique MAC address. • Fragmented UDP checksum off load for package reassembly. • Jumbo frames supported. • LinkSec support (802.3ae compliant) • TimeSync support (802.1as compliant) 5.3.1 Gigabit Ethernet PCI Bus Interface The Gigabit Ethernet controller has a PCI interface to the host processor and host memory. The following sections detail the transaction on the bus. 5.3.1.1 Transaction Layer The upper layer of the host architecture is the transaction layer. The transaction layer connects to the device core using an implementation specific protocol. Through this core-to-transaction-layer protocol, the application-specific parts of the device interact with the subsystem and transmit and receive requests to or from the remote agent, respectively. 5.3.1.2 5.3.1.2.1 Data Alignment 4 K Boundary PCI requests must never specify an Address/Length combination that causes a Memory Space access to cross a 4 K boundary. It is the HW responsibility to break requests into 4 K-aligned requests (if needed). This does not pose any requirement on SW. However, if SW allocates a buffer across a 4 K boundary, HW will issue multiple requests for the buffer. SW should consider aligning buffers to 4 KB boundary in cases where it improves performance. The alignment to the 4 K boundaries is done in the core. The Transaction layer will not do any alignment according to these boundaries. 5.3.1.2.2 64 Bytes PCI requests are multiples of 64 bytes and aligned to make better use of memory controller resources. Writes, however, can be on any boundary and can cross a 64 byte alignment boundary 5.3.1.3 Configuration Request Retry Status The LAN Controller might have a delay in initialization due to NVM read. If the NVM configuration read operation is not completed and the device receives a Configuration Request, the device will respond with a Configuration Request Retry Completion Status to terminate the Request, and thus effectively stall the Configuration Request until such time that the subsystem has completed local initialization and is ready to communicate with the host. 102 Datasheet Functional Description 5.3.2 5.3.2.1 Error Events and Error Reporting Data Parity Error The PCI Host bus does not provide parity protection, but it does forward parity errors from bridges. The LAN Controller recognizes parity errors through the internal bus interface and will set the Parity Error bit in PCI Configuration space. If parity errors are enabled in configuration space, a system error will be indicated on the PCI Host bus to the chipset. The offending cycle with a parity error will be dropped and not processed by the LAN Controller. 5.3.2.2 Completion with Unsuccessful Completion Status A completion with unsuccessful completion status (any status other than "000") will be dropped and not processed by the LAN Controller. Furthermore, the request that corresponds to the unsuccessful completion will not be retried. When this unsuccessful completion status is received, the System Error bit in the PCI Configuration space will be set. If the system errors are enabled in configuration space, a system error will be indicated on the PCI Host bus to the chipset. 5.3.3 Ethernet Interface The integrated LAN controller provides a complete CSMA/CD function supporting IEEE 802.3 (10Mb/s), 802.3u (100Mb/s) implementations. It also supports the IEEE 802.3z and 802.3ab (1000Mb/s) implementations. The device performs all of the functions required for transmission, reception and collision handling called out in the standards. The mode used to communicate between the LAN controller and the LAN connect device supports 10/100/1000 Mbps operation, with both half- and full-duplex operation at 10/100 Mbps, and full-duplex operation at 1000 Mbps. 5.3.3.1 MAC/LAN Connect Interface The integrated LAN controller and LAN Connect Device communicate through either the platform LAN connect interface (LCI) or Gigabit LAN connect interface (GLCI). All controller configuration is performed using device control registers mapped into system memory or I/O space. The LAN Connect Device is configured via the LCI or Gigabit Ethernet Lan connect interface. The integrated MAC supports various modes as summarized in the following table Table 5-4. LAN Mode Support Mode Normal 10/100/1000 LCI, GLCI Interface Active Connections Intel® 82567 Gigabit Platform LAN Connect Device Datasheet 103 Functional Description 5.3.4 PCI Power Management The LAN Controller supports the Advanced Configuration and Power Interface (ACPI) specification as well as Advanced Power Management (APM). This allows the host to be awoken (i.e., from Sx (S3-S5) to S0) by network-related activity via an internal host wake signal. The LAN controller contains power management registers for PCI, and supports D0 and D3 states. PCI transactions are only allowed in the D0 state, except for host accesses to the LAN controller’s PCI configuration registers. 5.3.4.1 Wake-Up The LAN Controller supports two types of wakeup mechanisms: 1. Advanced Power Management (APM) Wakeup 2. ACPI Power Management Wakeup Both mechanisms use an internal WAKE# signal to wake the system up. This signal is connected to the suspend wake logic in the ICH10. The wake-up steps are as follows: 1. Host Wake Event occurs (note that packet is not delivered to host) 2. PME_STATUS bit is set 3. Internal WAKE# signal asserted by Host LAN function 4. System wakes from Sx state to S0 state 5. The Host LAN function is transitioned to D0 6. The Host clears the PME_STATUS bit 7. Internal WAKE# signal is deasserted by Host LAN function 5.3.4.1.1 Advanced Power Management Wakeup Advanced Power Management Wakeup, or APM Wakeup, was previously known as Wake on LAN. It is a feature that has existed in the 10/100 Mbps NICs for several generations. The basic premise is to receive a broadcast or unicast packet with an explicit data pattern, and then to assert a signal to wake-up the system. In the earlier generations, this was accomplished by using a special signal that ran across a cable to a defined connector on the motherboard. The NIC would assert the signal for approximately 50ms to signal a wakeup. The LAN Controller uses (if configured to) an in-band PM_PME message for this. On power-up, the LAN Controller will read the APM Enable bits from the NVM PCI Init Control Word into the APM Enable (APME) bits of the Wakeup Control Register (WUC). These bits control enabling of APM Wakeup. When APM Wakeup is enabled, the LAN Controller checks all incoming packets for Magic Packets. Once the LAN Controller receives a matching magic packet, it will: • Set the Magic Packet Received bit in the Wake Up Status Register (WUS). • Set the PME_Status bit in the Power Management Control / Status Register (PMCSR) and assert the internal WAKE# signal. APM Wakeup is supported in all power states and only disabled if a subsequent NVM read results in the APM Wake Up bit being cleared or the software explicitly writes a 0 to the APM Wake Up (APM) bit of the WUC register. 104 Datasheet Functional Description 5.3.4.1.2 ACPI Power Management Wakeup The LAN Controller supports ACPI Power Management based Wakeups. It can generate system wake-up events from three sources: • Reception of a Magic Packet. • Reception of a Network Wakeup Packet. • Detection of a link change of state. Activating ACPI Power Management Wakeup requires the following steps: • The driver programs the Wake Up Filter Control Register (WUFC) to indicate the packets it wishes to wake up from and supplies the necessary data to the Ipv4 Address Table (IP4AT) and the Flexible Filter Mask Table (FFMT), Flexible Filter Length Table (FFLT), and the Flexible Filter Value Table (FFVT). It can also set the Link Status Change Wake Up Enable (LNKC) bit in the Wake Up Filter Control Register (WUFC) to cause wakeup when the link changes state. • The OS (at configuration time) writes a 1 to the PME_EN bit of the Power Management Control / Status Register (PMCSR.8). Normally, after enabling wakeup, the OS will write 11b to the lower two bits of the PMCSR to put the LAN Controller into low-power mode. Once Wakeup is enabled, the LAN Controller monitors incoming packets, first filtering them according to its standard address filtering method, then filtering them with all of the enabled wakeup filters. If a packet passes both the standard address filtering and at least one of the enabled wakeup filters, the LAN Controller will: • Set the PME_Status bit in the Power Management Control / Status Register (PMCSR) • If the PME_EN bit in the Power Management Control / Status Register (PMCSR) is set, assert the internal WAKE# signal. • Set one or more of the Received bits in the Wake Up Status Register (WUS). (More than one bit will be set if a packet matches more than one filter.) If enabled, a link state change wakeup will cause similar results, setting PME_Status, asserting the internal WAKE# signal and setting the Link Status Changed (LNKC) bit in the Wake Up Status Register (WUS) when the link goes up or down. The internal WAKE# signal will remain asserted until the OS either writes a 1 to the PME_Status bit of the PMCSR register or writes a 0 to the PME_En bit. After receiving a wakeup packet, the LAN Controller will ignore any subsequent wakeup packets until the driver clears all of the Received bits in the Wake Up Status Register (WUS). It will also ignore link change events until the driver clears the Link Status Changed (LNKC) bit in the Wake Up Status Register (WUS). 5.3.5 Configurable LEDs The LAN Controller supports 3 controllable and configurable LEDs that are driven from the LAN Connect Device. Each of the three LED outputs can be individually configured to select the particular event, state, or activity, which will be indicated on that output. In addition, each LED can be individually configured for output polarity as well as for blinking versus non-blinking (steady-state) indication. The configuration for LED outputs is specified via the LEDCTL register. Furthermore, the hardware-default configuration for all the LED outputs, can be specified via NVM fields, thereby supporting LED displays configurable to a particular OEM preference. Datasheet 105 Functional Description Each of the 3 LED's may be configured to use one of a variety of sources for output indication. The MODE bits control the LED source: • LINK_100/1000 is asserted when link is established at either 100 or 1000Mbps. • LINK_10/1000 is asserted when link is established at either 10 or 1000Mbps. • LINK_UP is asserted when any speed link is established and maintained. ACTIVITY is asserted when link is established and packets are being transmitted or received. • LINK/ACTIVITY is asserted when link is established AND there is NO transmit or receive activity • LINK_10 is asserted when a 10Mbps link is established and maintained. • LINK_100 is asserted when a 100Mbps link is established and maintained. • LINK_1000 is asserted when a 1000Mbps link is established and maintained. • FULL_DUPLEX is asserted when the link is configured for full duplex operation. • COLLISION is asserted when a collision is observed. • PAUSED is asserted when the device's transmitter is flow controlled. • LED_ON is always asserted; LED_OFF is always de-asserted. The IVRT bits allow the LED source to be inverted before being output or observed by the blink-control logic. LED outputs are assumed to normally be connected to the negative side (cathode) of an external LED. The BLINK bits control whether the LED should be blinked while the LED source is asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and 83 ms off). The blink control may be especially useful for ensuring that certain events, such as ACTIVITY indication, cause LED transitions, which are sufficiently visible to a human eye. The same blinking rate is shared by all LEDs. 5.3.6 Function Level Reset Support (FLR) The Gigabit LAN Controller supports the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an Operating System in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the Operating System to reset the whole device as if a PCI reset was asserted. 5.3.6.1 5.3.6.1.1 FLR Steps FLR Initialization 1. A FLR is initiated by software writing a 1 to the Initiate FLR bit. 2. All subsequent requests targeting the Function will not be claimed and will be Master Abort Immediate on the bus. This includes any configuration, I/O or Memory cycles, however, the Function shall continue to accept completions targeting the Function. 5.3.6.1.2 FLR Operation Function will Reset all configuration, I/O and memory registers of the Function except those indicated otherwise and reset all internal states of the Function to the default or initial condition. 106 Datasheet Functional Description 5.3.6.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: From the time Initiate FLR bit is written to 1 software must wait at least 100 ms before accessing the function. 5.4 LPC Bridge (w/ System and Management Functions) (D31:F0) The LPC bridge function of the ICH10 resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA, Interrupt controllers, Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and functions associated with other functional units (power management, GPIO, USB, etc.) are described in their respective sections. Note: The LPC bridge cannot be configured as a subtractive decode agent. 5.4.1 LPC Interface The ICH10 implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The LPC interface to the ICH10 is shown in Figure 5-2. Note that the ICH10 implements all of the signals that are shown as optional, but peripherals are not required to do so. Figure 5-2. LPC Interface Diagram PCI Bus PCI CLK LAD [3:0] LFRAME# LDRQ[1:0]# (Optional) LPCPD# (Optional) LSMI# (Optional) PCI RST# PCI SERIRQ PCI PME# Intel ® ICH10 LPC Device SUS_STAT# GPI Datasheet 107 Functional Description 5.4.1.1 LPC Cycle Types The ICH10 (Corporate only) implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.1. ICH10 Consumer does not provide a generic mechanism for decoding memory ranges and forwarding them as standard LPC Memory cycles on the LPC bus. Table 5-5 shows the cycle types supported by the ICH10. Table 5-5. LPC Cycle Types Supported Cycle Type Memory Read (Corporate only) Memory Write (Corporate only) I/O Read I/O Write DMA Read DMA Write Bus Master Read Bus Master Write Comment 1 byte only. (See Note 1 below) 1 byte only. (See Note 1 below) 1 byte only. Intel ICH10 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. 1 byte only. ICH10 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. Can be 1, or 2 bytes Can be 1, or 2 bytes Can be 1, 2, or 4 bytes. (See Note 2 below) Can be 1, 2, or 4 bytes. (See Note 2 below) NOTES: 1. ICH10 (Corporate only) provides a single generic memory range (LGMR) for decoding memory cycles and forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory decode range is 64 KB in size and can be defined as being anywhere in the 4 GB memory space. This range needs to be configured by BIOS during POST to provide the necessary memory resources. BIOS should advertise the LPC Generic Memory Range as Reserved to the OS in order to avoid resource conflict. For larger transfers, the ICH10 performs multiple 8-bit transfers. If the cycle is not claimed by any peripheral, it is subsequently aborted, and the ICH10 returns a value of all 1s to the processor. This is done to maintain compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds. 2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an address where A0=0). A dword transfer must be dword-aligned (i.e., with an address where A1 and A0 are both 0). 5.4.1.2 Table 5-6. Start Field Definition Start Field Bit Definitions Bits[3:0] Encoding 0000 0010 0011 1111 Definition Start of cycle for a generic target Grant for bus master 0 Grant for bus master 1 Stop/Abort: End of a cycle for a target. NOTE: All other encodings are RESERVED. 108 Datasheet Functional Description 5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR) The ICH10 always drives bit 0 of this field to 0. Peripherals running bus master cycles must also drive bit 0 to 0. Table 5-7 shows the valid bit encodings. Table 5-7. Cycle Type Bit Definitions Bits[3:2] 00 00 01 01 10 10 11 Bit1 0 1 0 1 0 1 x I/O Read I/O Write Memory Read Memory Read DMA Read DMA Write Reserved. If a peripheral performing a bus master cycle generates this value, the Intel ICH10 aborts the cycle. Definition 5.4.1.4 Size Bits[3:2] are reserved. The ICH10 always drives them to 00. Peripherals running bus master cycles are also supposed to drive 00 for bits 3:2; however, the ICH10 ignores those bits. Bits[1:0] are encoded as listed in Table 5-8. Table 5-8. Transfer Size Bit Definition Bits[1:0] 00 01 10 11 8-bit transfer (1 byte) 16-bit transfer (2 bytes) Reserved. The Intel ICH10 never drives this combination. If a peripheral running a bus master cycle drives this combination, the ICH10 may abort the transfer. 32-bit transfer (4 bytes) Size Datasheet 109 Functional Description 5.4.1.5 SYNC Valid values for the SYNC field are shown in Table 5-9. Table 5-9. SYNC Bit Definition Bits[3:0] 0000 Indication Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request deassertion and no more transfers desired for that channel. Short Wait: Part indicating wait-states. For bus master cycles, the Intel® ICH10 does not use this encoding. Instead, the ICH10 uses the Long Wait encoding (see next encoding below). Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding driven by the ICH10 for bus master cycles, rather than the Short Wait (0101). Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and more DMA transfers desired to continue after this transfer. This value is valid only on DMA transfers and is not allowed for any other type of cycle. Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this transfer. For DMA transfers, this not only indicates an error, but also indicates DMA request deassertion and no more transfers desired for that channel. 0101 0110 1001 1010 NOTES: 1. All other combinations are RESERVED. 2. If the LPC controller receives any SYNC returned from the device other than short (0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is not allowed to assert an Error SYNC. 5.4.1.6 SYNC Time-Out There are several error cases that can occur on the LPC interface. The ICH10 responds as defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to the stimuli described therein. There may be other peripheral failure conditions; however, these are not handled by the ICH10. 5.4.1.7 SYNC Error Indication The ICH10 responds as defined in section 4.2.1.10 of the Low Pin Count Interface Specification, Revision 1.1. Upon recognizing the SYNC field indicating an error, the ICH10 treats this as an SERR by reporting this into the Device 31 Error Reporting Logic. 110 Datasheet Functional Description 5.4.1.8 LFRAME# Usage The ICH10 follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification, Revision 1.1. The ICH10 performs an abort for the following cases (possible failure cases): • ICH10 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four consecutive clocks. • ICH10 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern. • A peripheral drives an invalid address when performing bus master cycles. • A peripheral drives an invalid value. 5.4.1.9 I/O Cycles For I/O cycles targeting registers specified in the ICH10’s decode ranges, the ICH10 performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the ICH10 breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses. Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH10 returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up resistors would keep the bus high if no device responds. 5.4.1.10 Bus Master Cycles The ICH10 supports Bus Master cycles and requests (using LDRQ#) as defined in the Low Pin Count Interface Specification, Revision 1.1. The ICH10 has two LDRQ# inputs, and thus supports two separate bus master devices. It uses the associated START fields for Bus Master 0 (0010b) or Bus Master 1 (0011b). Note: The ICH10 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only perform memory read or memory write cycles. 5.4.1.11 LPC Power Management LPCPD# Protocol Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive LDRQ# low or tri-state it. ICH10 shuts off the LDRQ# input buffers. After driving SUS_STAT# active, the ICH10 drives LFRAME# low, and tri-states (or drive low) LAD[3:0]. Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. The ICH10 asserts both SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol. Datasheet 111 Functional Description 5.4.1.12 Configuration and Intel® ICH10 Implications LPC I/F Decoders To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH10 includes several decoders. During configuration, the ICH10 must be programmed with the same decode ranges as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration space. Note: The ICH10 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures. Bus Master Device Mapping and START Fields Bus Masters must have a unique START field. In the case of the ICH10 that supports two LPC bus masters, it drives 0010 for the START field for grants to bus master #0 (requested via LDRQ0#) and 0011 for grants to bus master #1 (requested via LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular bus master. 5.5 DMA Operation (D31:F0) The ICH10 supports LPC DMA using the ICH10’s DMA controller. The DMA controller has registers that are fixed in the lower 64 KB of I/O space. The DMA controller is configured using registers in the PCI configuration space. These registers allow configuration of the channels for use by LPC DMA. The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven independently programmable channels (Figure 5-3). DMA controller 1 (DMA-1) corresponds to DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to channels 5–7. DMA channel 4 is used to cascade the two controllers and defaults to cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting requests from DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1. Figure 5-3. Intel® ICH10 DMA Controller Channel 0 Channel 1 DMA-1 Channel 2 Channel 3 Channel 6 Channel 7 Channel 4 Channel 5 DMA-2 Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. ICH10 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most significant bits of address. The DMA controller also features refresh address generation, and auto-initialization following a DMA termination. 112 Datasheet Functional Description 5.5.1 Channel Priority For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a software request for DMA service can be presented through each channel's DMA Request Register. A software request is subject to the same prioritization as any hardware request. See the detailed register description for Request Register programming information in Section 13.2. 5.5.1.1 Fixed Priority The initial fixed priority structure is as follows: High priority 0, 1, 2, 3 Low priority 5, 6, 7 The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority position of channel 4 in DMA-2, thus taking priority over channels 5, 6, and 7. 5.5.1.2 Rotating Priority Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7). Channels 0–3 rotate as a group of 4. They are always placed between channel 5 and channel 7 in the priority list. Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three positions in the rotation, while channel group (0–3) comprises the fourth position in the arbitration. 5.5.2 Address Compatibility Mode When the DMA is operating, the addresses do not increment or decrement through the High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments, the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is operating in 16-bit mode, the addresses still do not increment or decrement through the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a 24-bit address is 01FFFEh and increments, the next address is 000000h, not 0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. Datasheet 113 Functional Description 5.5.3 Summary of DMA Transfer Sizes Table 5-10 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word Count Register” indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. The column labeled “Current Address Increment/Decrement” indicates the number added to or taken from the Current Address register after each DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register will be incremented or decremented. 5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words Table 5-10. DMA Transfer Size DMA Device Date Size And Word Count 8-Bit I/O, Count By Bytes 16-Bit I/O, Count By Words (Address Shifted) Current Byte/Word Count Register Bytes Words Current Address Increment/ Decrement 1 1 The ICH10 maintains compatibility with the implementation of the DMA in the PC AT that used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When programming the Current Address Register (when the DMA channel is in this mode), the Current Address must be programmed to an even address with the address value shifted right by one bit. The address shifting is shown in Table 5-11. Table 5-11. Address Shifting in 16-Bit I/O DMA Transfers Output Address A0 A[16:1] A[23:17] 8-Bit I/O Programmed Address (Ch 0–3) A0 A[16:1] A[23:17] 16-Bit I/O Programmed Address (Ch 5–7) (Shifted) 0 A[15:0] A[23:17] NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode. 5.5.4 Autoinitialize By programming a bit in the DMA Channel Mode Register, a channel may be set up as an autoinitialize channel. When a channel undergoes autoinitialization, the original values of the Current Page, Current Address and Current Byte/Word Count Registers are automatically restored from the Base Page, Address, and Byte/Word Count Registers of that channel following TC. The Base Registers are loaded simultaneously with the Current Registers by the microprocessor when the DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to perform another DMA service, without processor intervention, as soon as a valid DREQ is detected. 114 Datasheet Functional Description 5.5.5 Software Commands There are three additional special software commands that the DMA controller can execute. The three software commands are: • Clear Byte Pointer Flip-Flop • Master Clear • Clear Mask Register They do not depend on any specific bit pattern on the data bus. 5.6 LPC DMA DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request. 5.6.1 Asserting DMA Requests Peripherals that need DMA service encode their requested channel number on the LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they may not be shared between two separate peripherals). The ICH10 has two LDRQ# inputs, allowing at least two devices to support DMA or bus mastering. LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-4, the peripheral uses the following serial encoding sequence: • Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle conditions. • The next three bits contain the encoded DMA channel number (MSB first). • The next bit (ACT) indicates whether the request for the indicated DMA channel is active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is inactive. The case where ACT is low is rare, and is only used to indicate that a previous request for that channel is being abandoned. • After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After that one clock, LDRQ# signal can be brought low to the next encoding sequence. If another DMA channel also needs to request a transfer, another sequence can be sent on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC interface, and the I/O device does not need to selfarbitrate before sending the message. Figure 5-4. DMA Request Assertion through LDRQ# LCLK LDRQ# Start MSB LSB ACT Start Datasheet 115 Functional Description 5.6.2 Abandoning DMA Requests DMA Requests can be deasserted in two fashions: on error conditions by sending an LDRQ# message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the DMA transfer. This section describes boundary conditions where the DMA request needs to be removed prior to a data transfer. There may be some special cases where the peripheral desires to abandon a DMA transfer. The most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its FIFO, or software stopping a device prematurely. In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the ICH10, there is no assurance that the cycle has not been granted and will shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle normally with any random data. This method of DMA deassertion should be prevented whenever possible, to limit boundary conditions both on the ICH10 and the peripheral. 5.6.3 General Flow of DMA Transfers Arbitration for DMA channels is performed through the 8237 within the host. Once the host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA transfer is as follows: 1. ICH10 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted. 2. ICH10 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction. 3. ICH10 asserts channel number and, if applicable, terminal count. 4. ICH10 indicates the size of the transfer: 8 or 16 bits. 5. If a DMA read… — The ICH10 drives the first 8 bits of data and turns the bus around. — The peripheral acknowledges the data with a valid SYNC. — If a 16-bit transfer, the process is repeated for the next 8 bits. 6. If a DMA write… — The ICH10 turns the bus around and waits for data. — The peripheral indicates data ready through SYNC and transfers the first byte. — If a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus. 5.6.4 Terminal Count Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size of the transfer. For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the second byte is the last byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is communicated, and only signal TC when the last byte of that transfer size has been transferred. 116 Datasheet Functional Description 5.6.5 Verify Mode Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a DMA write, where the peripheral is transferring data to main memory. The indication from the host is the same as a DMA write, so the peripheral will be driving data onto the LPC interface. However, the host will not transfer this data into main memory. 5.6.6 DMA Request Deassertion An end of transfer is communicated to the ICH10 through a special SYNC field transmitted by the peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting LDREQ#. If a DMA transfer is several bytes (e.g., a transfer from a demand mode device) the ICH10 needs to know when to deassert the DMA request based on the data currently being transferred. The DMA agent uses a SYNC encoding on each byte of data being transferred, which indicates to the ICH10 whether this is the last byte of transfer or if more bytes are requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of 0000b (ready with no error), or 1010b (ready with error). These encodings tell the ICH10 that this is the last piece of data transferred on a DMA read (ICH10 to peripheral), or the byte that follows is the last piece of data transferred on a DMA write (peripheral to ICH10). When the ICH10 sees one of these two encodings, it ends the DMA transfer after this byte and deasserts the DMA request to the 8237. Therefore, if the ICH10 indicated a 16-bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC value of 0000b or 1010b. The ICH10 does not attempt to transfer the second byte, and deasserts the DMA request internally. If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the indicated size, then the ICH10 only deasserts the DMA request to the 8237 since it does not need to end the transfer. If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of 1001b (ready plus more data). This indicates to the 8237 that more data bytes are requested after the current byte has been transferred, so the ICH10 keeps the DMA request active to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC value of 1001b to the ICH10, the data will be transferred and the DMA request will remain active to the 8237. At a later time, the ICH10 will then come back with another START–CYCTYPE–CHANNEL–SIZE etc. combination to initiate another transfer to the peripheral. The peripheral must not assume that the next START indication from the ICH10 is another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode DMA devices can be assured that they will receive the next START indication from the ICH10. Note: Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit channel (first byte of a 16-bit transfer) is an error condition. The host stops the transfer on the LPC bus as indicated, fills the upper byte with random data on DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred, incrementing the 8237’s address and decrementing its byte count. Datasheet 117 Functional Description 5.6.7 SYNC Field / LDRQ# Rules Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended through a SYNC field during the DMA transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a DMA channel. The peripheral must not assert another message for eight LCLKs after a deassertion is indicated through the SYNC field. This is needed to allow the 8237, that typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next agent. Under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. The method by which this communication between host and peripheral through system BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are motherboard devices, no “plug-n-play” registry is required. The peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the DMA channel, and be willing to accept a SIZE field that is smaller than what it may currently have buffered. To that end, it is recommended that future devices that may appear on the LPC bus, that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus mastering interface and not rely on the 8237. 5.7 8254 Timers (D31:F0) The ICH10 contains three counters that have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. Counter 0, System Timer This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode 3 operation. The counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. The counter loads the initial count value 1 counter period after software writes the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by two each counter period. The counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and again decrements the initial count value by two each counter period. The counter then asserts IRQ0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating IRQ0. Counter 1, Refresh Request Signal This counter provides the refresh request signal and is typically programmed for Mode 2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial count value is loaded one counter period after being written to the counter I/O address. The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. Programming the counter to anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit. Counter 2, Speaker Tone This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and Control ports). 118 Datasheet Functional Description 5.7.1 Timer Programming The counter/timers are programmed in the following fashion: 1. Write a control word to select a counter. 2. Write an initial count for that counter. 3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of the 16-bit counter. 4. Repeat with other counters. Only two conventions need to be observed when programming the counters. First, for each counter, the control word must be written before the initial count is written. Second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting is affected as described in the mode definitions. The new count must follow the programmed count format. If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the counter will be loaded with an incorrect count. The Control Word Register at port 43h controls the operation of all three counters. Several commands are available: • Control Word Command. Specifies which counter to read or write, the operating mode, and the count format (binary or BCD). • Counter Latch Command. Latches the current count so that it can be read by the system. The countdown process continues. • Read Back Command. Reads the count value, programmed mode, the current state of the OUT pins, and the state of the Null Count Flag of the selected counter. Table 5-12 lists the six operating modes for the interval counters. Table 5-12. Counter Operating Modes Mode 0 1 2 Function Out signal on end of count (=0) Hardware retriggerable one-shot Rate generator (divide by n counter) Description Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. Output is 0. When count goes to 0, output goes to 1 for one clock time. Output is 1. Output goes to 0 for one clock time, then back to 1 and counter is reloaded. Output is 1. Output goes to 0 when counter rolls over, and counter is reloaded. Output goes to 1 when counter rolls over, and counter is reloaded, etc. Output is 1. Output goes to 0 when count expires for one clock time. Output is 1. Output goes to 0 when count expires for one clock time. 3 Square wave output 4 5 Software triggered strobe Hardware triggered strobe Datasheet 119 Functional Description 5.7.2 Reading from the Interval Timer It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters: a simple read operation, counter Latch command, and the Read-Back command. Each is explained below. With the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them. 5.7.2.1 Simple Read The first method is to perform a simple read operation. The counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). Note: Performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. However, in the case of counter 2, the count can be stopped by writing to the GATE bit in port 61h. 5.7.2.2 Counter Latch Command The Counter Latch command, written to port 43h, latches the count of a specific counter at the time the command is received. This command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. The count value is then read from each counter’s Count register as was programmed by the Control register. The count is held in the latch until it is read or the counter is reprogrammed. The count is then unlatched. This allows reading the contents of the counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter Latch commands do not affect the programmed mode of the counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch command is ignored. The count read is the count at the time the first Counter Latch command was issued. 5.7.2.3 Read Back Command The Read Back command, written to port 43h, latches the count value, programmed mode, and current states of the OUT pin and Null Count flag of the selected counter or counters. The value of the counter and its status may then be read by I/O access to the counter address. The Read Back command may be used to latch multiple counter outputs at one time. This single command is functionally equivalent to several counter latch commands, one for each counter latched. Each counter's latched count is held until it is read or reprogrammed. Once read, a counter is unlatched. The other counters remain latched until they are read. If multiple count Read Back commands are issued to the same counter without reading the count, all but the first are ignored. The Read Back command may additionally be used to latch status information of selected counters. The status of a counter is accessed by a read from that counter's I/O port address. If multiple counter status latch operations are performed without reading the status, all but the first are ignored. 120 Datasheet Functional Description Both count and status of the selected counters may be latched simultaneously. This is functionally the same as issuing two consecutive, separate Read Back commands. If multiple count and/or status Read Back commands are issued to the same counters without any intervening reads, all but the first are ignored. If both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. The next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. Subsequent reads return unlatched count. 5.8 8259 Interrupt Controllers (PIC) (D31:F0) The ICH10 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and DMA channels. In addition, this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 core supports eight interrupts, numbered 0–7. Table 5-13 shows how the cores are connected. . Table 5-13. Interrupt Controller Core Connections 8259 8259 Input 0 1 2 Master 3 4 5 6 7 0 1 2 3 Slave 4 Typical Interrupt Source Internal Keyboard Internal Serial Port A Serial Port B Parallel Port / Generic Floppy Disk Parallel Port / Generic Internal Real Time Clock Generic Generic Generic PS/2 Mouse Connected Pin / Function Internal Timer / Counter 0 output / HPET #0 IRQ1 via SERIRQ Slave controller INTR output IRQ3 via SERIRQ, PIRQ# IRQ4 via SERIRQ, PIRQ# IRQ5 via SERIRQ, PIRQ# IRQ6 via SERIRQ, PIRQ# IRQ7 via SERIRQ, PIRQ# Internal RTC / HPET #1 IRQ9 via SERIRQ, SCI, TCO, or PIRQ# IRQ10 via SERIRQ, SCI, TCO, or PIRQ# IRQ11 via SERIRQ, SCI, TCO, or PIRQ#, or HPET #2 IRQ12 via SERIRQ, SCI, TCO, or PIRQ#, or HPET #3 State Machine output based on processor FERR# assertion. May optionally be used for SCI or TCO interrupt if FERR# not needed. SATA Primary (legacy mode), or via SERIRQ or PIRQ# SATA Secondary (legacy mode) or via SERIRQ or PIRQ# 5 Internal 6 7 SATA SATA The ICH10 cascades the slave controller onto the master controller through master controller interrupt input 2. This means there are only 15 possible interrupts for the ICH10 PIC. Datasheet 121 Functional Description Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and IRQ13. Note: Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH10. In the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. Therefore, the term “high” indicates “active,” which means “low” on an originating PIRQ#. 5.8.1 5.8.1.1 Interrupt Handling Generating Interrupts The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other pending interrupts. Table 5-14 defines the IRR, ISR, and IMR. Table 5-14. Interrupt Status Registers Bit IRR Description Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. This bit is set whether or not the interrupt is masked. However, a masked interrupt will not generate INTR. Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will not generate INTR. ISR IMR 5.8.1.2 Acknowledging Interrupts The processor generates an interrupt acknowledge cycle that is translated by the host bridge into a PCI Interrupt Acknowledge Cycle to the ICH10. The PIC translates this command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code. This code is based upon bits [7:3] of the corresponding ICW2 register, combined with three bits representing the interrupt within that controller. Table 5-15. Content of Interrupt Vector Byte Master, Slave Interrupt IRQ7,15 IRQ6,14 IRQ5,13 IRQ4,12 IRQ3,11 IRQ2,10 IRQ1,9 IRQ0,8 ICW2[7:3] Bits [7:3] Bits [2:0] 111 110 101 100 011 010 001 000 122 Datasheet Functional Description 5.8.1.3 Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to the processor if an asserted interrupt is not masked. 3. The processor acknowledges the INTR and responds with an interrupt acknowledge cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is broadcast over PCI by the ICH10. 4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH10 converts it into the two cycles that the internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers. 5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA# pulse. 6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt vector. If no interrupt request is present because the request was too short in duration, the PIC returns vector 7 from the master controller. 7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. 5.8.2 Initialization Command Words (ICWx) Before operation can begin, each 8259 must be initialized. In the ICH10, this is a four byte sequence. The four initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and ICW4. The base address for each 8259 initialization command word is a fixed location in the I/O memory space: 20h for the master controller, and A0h for the slave controller. 5.8.2.1 ICW1 An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to ICW1. Upon sensing this write, the ICH10 PIC expects three more byte writes to 21h for the master controller, or A1h for the slave controller, to complete the ICW sequence. A write to ICW1 starts the initialization sequence during which the following automatically occur: 1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set to 7. 5. Special mask mode is cleared and Status Read is set to IRR. Datasheet 123 Functional Description 5.8.2.2 ICW2 The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller. 5.8.2.3 ICW3 The third write in the sequence (ICW3) has a different meaning for each controller. • For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the slave controller. Within the ICH10, IRQ2 is used. Therefore, bit 2 of ICW3 on the master controller is set to a 1, and the other bits are set to 0s. • For the slave controller, ICW3 is the slave identification code used during an interrupt acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. The slave controller compares this identification code to the value stored in its ICW3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 5.8.2.4 ICW4 The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based system. 5.8.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes. • OCW1 masks and unmasks interrupt lines. • OCW2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the EOI function. • OCW3 sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and enables/disables polled interrupt mode. 5.8.4 5.8.4.1 Modes of Operation Fully Nested Mode In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. When an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the processor issues an EOI command immediately before returning from the service routine; or if in AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels generate another interrupt. Interrupt priorities can be changed in the rotating priority mode. 124 Datasheet Functional Description 5.8.4.2 Special Fully-Nested Mode This mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode is programmed to the master controller. This mode is similar to the fully-nested mode with the following exceptions: • When an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor. In the normal-nested mode, a slave is masked out when its request is in service. • When exiting the Interrupt Service routine, software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a NonSpecific EOI command to the slave and then reading its ISR. If it is 0, a nonspecific EOI can also be sent to the master. 5.8.4.3 Automatic Rotation Mode (Equal Priority Devices) In some applications, there are a number of interrupting devices of equal priority. Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a device receives the lowest priority after being serviced. In the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode which is set by (R=1, SL=0, EOI=0). 5.8.4.4 Specific Rotation Mode (Specific Priority) Software can change interrupt priorities by programming the bottom priority. For example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest priority device. The Set Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device. In this mode, internal status is updated by software control during OCW2. However, it is independent of the EOI command. Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1, and LO–L2=IRQ level to receive bottom priority. 5.8.4.5 Poll Mode Poll mode can be used to conserve space in the interrupt vector table. Multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. Poll mode can also be used to expand the number of interrupts. The polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. In this mode, the INTR output is not used and the microprocessor internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. Datasheet 125 Functional Description 5.8.4.6 Cascade Mode The PIC in the ICH10 has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration can handle up to 15 separate priority levels. The master controls the slaves through a three bit internal bus. In the ICH10, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. An EOI command must be issued twice: once for the master and once for the slave. 5.8.4.7 Edge and Level Triggered Mode In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the entire controller. In the ICH10, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/ Level control Registers ELCR1 and ELCR2. If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition on the corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection. The interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring. In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7 vector is returned. 5.8.4.8 End of Interrupt (EOI) Operations An EOI can occur in one of two fashions: by a command word write issued to the PIC before returning from a service routine, the EOI command; or automatically when AEOI bit in ICW4 is set to 1. 5.8.4.9 Normal End of Interrupt In normal EOI, software writes an EOI command before leaving the interrupt service routine to mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the ICH10, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When the PIC is operated in modes that preserve the fully nested structure, software can determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is in the special mask mode. An EOI command must be issued for both the master and slave controller. 5.8.4.10 Automatic End of Interrupt Mode In this mode, the PIC automatically performs a Non-Specific EOI operation at the trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller. 126 Datasheet Functional Description 5.8.5 5.8.5.1 Masking Interrupts Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 on the master controller masks all requests for service from the slave controller. 5.8.5.2 Special Mask Mode Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. The special mask mode enables all interrupts not masked by a bit set in the Mask register. Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the special mask mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. The special mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0. 5.8.6 Steering PCI Interrupts The ICH10 can be programmed to allow PIRQA#-PIRQH# to be routed internally to interrupts 3–7, 9–12, 14 or 15. The assignment is programmable through the PIRQx Route Control registers, located at 60–63h and 68–6Bh in Device 31:Function 0. One or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not required, the Route registers can be programmed to disable steering. The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line, software must change the IRQ's corresponding ELCR bit to level sensitive mode. The ICH10 internally inverts the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer be used by an active high device (through SERIRQ). However, active low interrupts can share their interrupt with PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH10 receives the PIRQ input, like all of the other external sources, and routes it accordingly. Datasheet 127 Functional Description 5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) In addition to the standard ISA-compatible PIC described in the previous chapter, the ICH10 incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in either a uni-processor or multiprocessor system. 5.9.1 Interrupt Handling The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are: • Method of Interrupt Transmission. The I/O APIC transmits interrupts through memory writes on the normal datapath to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. • Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt number. For example, interrupt 10 can be given a higher priority than interrupt 3. • More Interrupts. The I/O APIC in the ICH10 supports a total of 24 interrupts. • Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O APIC devices in the system with their own interrupt vectors. 5.9.2 Interrupt Mapping The I/O APIC within the ICH10 supports 24 APIC interrupts. Each interrupt has its own unique vector assigned by software. The interrupt vectors are mapped as follows, and match “Config 6” of the Multi-Processor Specification. Table 5-16. APIC Interrupt Mapping1 (Sheet 1 of 2) IRQ # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Via SERIRQ No Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes No Yes Yes Direct from Pin No No No No No No No No No No No No No No No No Via PCI Message No Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes No Yes Yes RTC, HPET #1 (legacy mode) Option for SCI, TCO Option for SCI, TCO HPET #2, Option for SCI, TCO (Note2) HPET #3 (Note 3) FERR# logic SATA Primary (legacy mode) SATA Secondary (legacy mode) 8254 Counter 0, HPET #0 (legacy mode) Internal Modules Cascade from 8259 #1 128 Datasheet Functional Description Table 5-16. APIC Interrupt Mapping1 (Sheet 2 of 2) IRQ # 16 17 18 19 20 21 22 23 Via SERIRQ PIRQA# PIRQB# PIRQC# PIRQD# N/A N/A N/A N/A Direct from Pin PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#4 PIRQF#4 PIRQG#4 PIRQH#4 Yes Option for SCI, TCO, HPET #0,1,2, 3. Other internal devices are routable; see Section 10.1.54 through Section 10.1.60. Yes Internal devices are routable; see Section 10.1.54 though Section 10.1.60. Via PCI Message Internal Modules NOTES: 1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15 receive active-high internal interrupt sources, while interrupts 16 through 23 receive active-low internal interrupt sources. 2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to ensure the proper operation of HPET #2. ICH10 hardware does not prevent sharing of IRQ 11. 3. If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other devices to ensure the proper operation of HPET #3. ICH10 hardware does not prevent sharing of IRQ 12. 4. PIRQ[E:H] are Multiplexed with GPIO pins. Interrupts PIRQ[E:H] will not be exposed if they are configured as GPIOs. 5.9.3 PCI / PCI Express* Message-Based Interrupts When external devices through PCI / PCI Express wish to generate an interrupt, they will send the message defined in the PCI Express* Base Specification, Revision 1.0a for generating INTA# - INTD#. These will be translated internal assertions/de-assertions of INTA# – INTD#. 5.9.4 Front Side Bus Interrupt Delivery For processors that support Front Side Bus (FSB) interrupt delivery, the ICH10 requires that the I/O APIC deliver interrupt messages to the processor in a parallel manner, rather than using the I/O APIC serial scheme. This is done by the ICH10 writing (via DMI) to a memory location that is snooped by the processor(s). The processor(s) snoop the cycle to know which interrupt goes active. The following sequence is used: 1. When the ICH10 detects an interrupt event (active edge for edge-triggered mode or a change for level-triggered mode), it sets or resets the internal IRR bit associated with that interrupt. 2. Internally, the ICH10 requests to use the bus in a way that automatically flushes upstream buffers. This can be internally implemented similar to a DMA device request. 3. The ICH10 then delivers the message by performing a write cycle to the appropriate address with the appropriate data. The address and data formats are described below in Section 5.9.4.4. Note: FSB Interrupt Delivery compatibility with processor clock control depends on the processor, not the ICH10. Datasheet 129 Functional Description 5.9.4.1 Edge-Triggered Operation In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt. 5.9.4.2 Level-Triggered Operation In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt. If after the EOI the interrupt is still active, then another “Assert Message” is sent to indicate that the interrupt is still active. 5.9.4.3 Registers Associated with Front Side Bus Interrupt Delivery Capabilities Indication: The capability to support Front Side Bus interrupt delivery is indicated via ACPI configuration techniques. This involves the BIOS creating a data structure that gets reported to the ACPI configuration software. 5.9.4.4 Interrupt Message Format The ICH10 writes the message to PCI (and to the Host controller) as a 32-bit memory write cycle. It uses the formats shown in Table 5-17 and Table 5-18 for the address and data. The local APIC (in the processor) has a delivery mode option to interpret Front Side Bus messages as a SMI in which case the processor treats the incoming interrupt as a SMI instead of as an interrupt. This does not mean that the ICH10 has any way to have a SMI source from ICH10 power management logic cause the I/O APIC to send an SMI message (there is no way to do this). The ICH10’s I/O APIC can only send interrupts due to interrupts which do not include SMI, NMI or INIT. This means that in IA-32/ Intel® 64 based platforms, Front Side Bus interrupt message format delivery modes 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not be used and is not supported. Only the hardware pin connection is supported by ICH10. : Table 5-17. Interrupt Message Address Format Bit 31:20 19:12 11:4 Will always be FEEh Destination ID: This is the same as bits 63:56 of the I/O Redirection Table entry for the interrupt associated with this message. Extended Destination ID: This is the same as bits 55:48 of the I/O Redirection Table entry for the interrupt associated with this message. Redirection Hint: This bit is used by the processor host bridge to allow the interrupt message to be redirected. 0 = The message will be delivered to the agent (processor) listed in bits 19:12. 3 1 = The message will be delivered to an agent with a lower interrupt priority This can be derived from bits 10:8 in the Data Field (see below). The Redirection Hint bit will be a 1 if bits 10:8 in the delivery mode field associated with corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit will be 0 Destination Mode: This bit is used only the Redirection Hint bit is set to 1. If the Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical ID. Will always be 00. Description 2 1:0 130 Datasheet Functional Description Table 5-18. Interrupt Message Data Format Bit 31:16 15 14 13:12 11 Will always be 0000h. Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table for that interrupt. Delivery Status: 1 = Assert, 0 = Deassert. Only Assert messages are sent. This bit is always 1. Will always be 00 Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the I/O Redirection Table for that interrupt. Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt. 10:8 000 = Fixed 100 = NMI 001 = Lowest Priority 101 = INIT 010 = SMI/PMI 110 = Reserved 011 = Reserved 111 = ExtINT 7:0 Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt. Description 5.9.5 IOxAPIC Address Remapping To support Intel® Virtualization Technology, interrupt messages are required to go through similar address remapping as any other memory request. Address remapping allows for domain isolation for interrupts, so a device assigned in one domain is not allowed to generate an interrupt to another domain. The address remapping is based on the Bus: Device: Function field associated with the requests. The internal APIC is required to initiate the interrupt message using a unique Bus: Device: function. ICH10 allows BIOS to program the unique Bus: Device: Function address for the internal APIC. This address field does not change the APIC functionality and the APIC is not promoted as a stand-alone PCI device. See Device 31: Function 0 Offset 6Ch for additional information. 5.9.6 External Interrupt Controller Support The ICH10 supports external APICs off of PCI Express ports, and does not support APICs on the PCI bus. The EOI special cycle is only forwarded to PCI Express ports. Datasheet 131 Functional Description 5.10 Serial Interrupt (D31:F0) The ICH10 supports a serial IRQ scheme. This allows a single signal to be used to report interrupt requests. The signal used to transmit this information is shared between the host, the ICH10, and all peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the following fashion: • S – Sample Phase. Signal driven low • R – Recovery Phase. Signal driven high • T – Turn-around Phase. Signal released The ICH10 supports a message for 21 serial interrupts. These represent the 15 ISA interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts (20– 23). Note: When the SATA controller is configured for legacy IDE mode, IRQ14 and IRQ15 are expected to behave as ISA legacy interrupts, which cannot be shared (i.e., through the Serial Interrupt pin). If IRQ14 and IRQ15 are shared with Serial Interrupt pin, then abnormal system behavior may occur. For example, IRQ14/15 may not be detected by ICH10's interrupt controller. When the SATA controller is not running in Native IDE mode, IRQ14 and IRQ15 are used as special interrupts. If the SATA controller is in native modes, these interrupts can be mapped to other devices accordingly. 5.10.1 Start Frame The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the ICH10 is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start frame. The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In this mode, the ICH10 asserts the start frame. This start frame is 4, 6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This is a polling mode. When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the SERIRQ signal low. The ICH10 senses the line low and continues to drive it low for the remainder of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this mode, the ICH10 drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet, and therefore, lower power operation. 132 Datasheet Functional Description 5.10.2 Data Frames Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1 clock each: • Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the corresponding interrupt signal is low. If the corresponding interrupt is high, then the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames indicates that an active-high ISA interrupt is not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low interrupt is being requested. • Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase. • Turn-around Phase. The device tri-states the SERIRQ line. 5.10.3 Stop Frame After all data frames, a Stop Frame is driven by the ICH10. The SERIRQ signal is driven low by the ICH10 for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration register. The number of clocks determines the next mode (see Table 5-19). Table 5-19. Stop Frame Explanation Stop Frame Width 2 PCI clocks 3 PCI clocks Next Mode Quiet Mode. Any SERIRQ device may initiate a Start Frame Continuous Mode. Only the host (Intel® ICH10) may initiate a Start Frame 5.10.4 Specific Interrupts Not Supported via SERIRQ There are three interrupts seen through the serial stream that are not supported by the ICH10. These interrupts are generated internally, and are not sharable with other devices within the system. These interrupts are: • IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0. • IRQ8#. RTC interrupt can only be generated internally. • IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#. The ICH10 ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. Datasheet 133 Functional Description 5.10.5 Data Frame Format Table 5-20 shows the format of the data frames. For the PCI interrupts (A–D), the output from the ICH10 is AND’d with the PCI input signal. This way, the interrupt can be signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are shared). Table 5-20. Data Frame Format Data Frame # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Interrupt Clocks Past Start Frame 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 Ignored. IRQ13 can only be generated from FERR# Not attached to SATA logic Not attached to SATA logic Same as ISA IOCHCK# going active. Drive PIRQA# Drive PIRQB# Drive PIRQC# Drive PIRQD# Ignored. IRQ8# can only be generated internally. Causes SMI# if low. Will set the SERIRQ_SMI_STS bit. Comment Ignored. IRQ0 can only be generated via the internal 8524 IRQ0 IRQ1 SMI# IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK# PCI INTA# PCI INTB# PCI INTC# PCI INTD# 134 Datasheet Functional Description 5.11 Real Time Clock (D31:F0) The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose usage. Three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 µs to 500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week, month, and year are counted. Daylight savings compensation is no longer supported. The hour is represented in twelve or twenty-four hour format, and data can be represented in BCD or binary format. The design is functionally compatible with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is divided to achieve an update every second. The lower 14 bytes on the lower RAM block has very specific functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC functions. The time and calendar data should match the data mode (BCD or binary) and hour mode (12 or 24 hour) as selected in register B. It is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. The exception to these ranges is to store a value of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled. The SET bit must be 1 while programming these locations to avoid clashes with an update cycle. Access to time and date information is done through the RAM locations. If a RAM read from the ten time and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. Any RAM writes under the same conditions are ignored. Note: The leap year determination for adding a 29th day to February does not take into account the end-of-the-century exceptions. The logic simply assumes that all years divisible by 4 are leap years. According to the Royal Observatory Greenwich, years that are divisible by 100 are typically not leap years. In every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note that the year 2100 will be the first time in which the current RTC implementation would incorrectly calculate the leap-year. The ICH10 does not implement month/year alarms. 5.11.1 Update Cycles An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide chain is properly configured. During this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the RAM locations. The update cycle will start at least 488 µs after the UIP bit of register A is asserted, and the entire cycle does not take more than 1984 µs to complete. The time and date RAM locations (0–9) are disconnected from the external bus during this time. To avoid update and data corruption conditions, external RAM access to these locations can safely occur at two times. When a updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date data. If the UIP bit of Register A is detected to be low, there is at least 488 µs before the update cycle begins. Warning: The overflow conditions for leap years adjustments are based on more than one date or time item. To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before leap year occurs. Datasheet 135 Functional Description 5.11.2 Interrupts The real-time clock interrupt is internally routed within the ICH10 both to the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the ICH10, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored. However, the High Performance Event Timers can also be mapped to IRQ8#; in this case, the RTC interrupt is blocked. 5.11.3 Lockable RAM Ranges The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the configuration space. If the locking bits are set, the corresponding range in the RAM will not be readable or writable. A write cycle to those locations will have no effect. A read cycle to those locations will not return the location’s actual value (resultant value is undefined). Once a range is locked, the range can be unlocked only by a hard reset, which will invoke the BIOS and allow it to relock the RAM range. 5.11.4 Century Rollover The ICH10 detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form 99 to 00. Upon detecting the rollover, the ICH10 sets the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler can update registers in the RTC RAM that are associated with century value. If the system is in a sleep state (S1–S5) when the century rollover occurs, the ICH10 also sets the NEWCENTURY_STS bit, but no SMI# is generated. When the system resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and update the century value in the RTC RAM. 5.11.5 Clearing Battery-Backed RTC RAM Clearing CMOS RAM in an ICH10-based platform can be done by using a jumper on RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Using RTCRST# to Clear CMOS A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set and those configuration bits in the RTC power well will be set to their default state. BIOS can monitor the state of this bit, and manually clear the RTC CMOS array once the system is booted. The normal position would cause RTCRST# to be pulled up through a weak pull-up resistor. Table 5-21 shows which bits are set to their default state when RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved and then replaced—all while the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state. 136 Datasheet Functional Description Table 5-21. Configuration Bits Reset by RTCRST# Assertion Bit Name Alarm Interrupt Enable (AIE) Alarm Flag (AF) Register Register B (General Configuration) (RTC_REGB) Register C (Flag Register) (RTC_REGC) General PM Configuration 3 Register GEN_PMCON_3 General PM Configuration 3 Register GEN_PMCON_3 General PM Configuration 3 Register GEN_PMCON_3 General PM Configuration 3 Register GEN_PMCON_3 General PM Configuration 3 Register (GEN_PMCON_3) General PM Configuration 3 Register GEN_PMCON_3 Power Management 1 Status Register (PM1_STS) Power Management 1 Enable Register (PM1_EN) Power Management 1 Control (PM1_CNT) General Purpose Event 0 Enables Register (GPE0_EN) General Purpose Event 0 Enables Register (GPE0_EN) General Purpose Event 0 Enables Register (GPE0_EN) TCO1 Status Register (TCO1_STS) TCO2 Status Register (TCO2_STS) Backed Up Control Register (BUC) Location I/O space (RTC Index + 0Bh) I/O space (RTC Index + 0Ch) D31:F0:A4h Bit(s) Default State X 5 5 X SWSMI_RATE_SEL 7:6 0 SLP_S4# Minimum Assertion Width SLP_S4# Assertion Stretch Enable RTC Power Status (RTC_PWR_STS) Power Failure (PWR_FLR) D31:F0:A4h 5:4 0 D31:F0:A4h 3 0 D31:F0:A4h 2 0 D31:F0:A4h 1 0 AFTERG3_EN Power Button Override Status (PRBTNOR_STS) RTC Event Enable (RTC_EN) Sleep Type (SLP_TYP) PME_EN D31:F0:A4h 0 0 PMBase + 00h 11 0 PMBase + 02h 10 0 PMBase + 04h 12:10 0 PMBase + 2Ch 11 0 BATLOW_EN PMBase + 2Ch 10 0 RI_EN PMBase + 2Ch 8 0 NEWCENTURY_STS Intruder Detect (INTRD_DET) Top Swap (TS) TCOBase + 04h TCOBase + 06h Chipset Config Registers:Offset 3414h 7 0 0 0 0 X Datasheet 137 Functional Description Using a GPI to Clear CMOS A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this GPI on system boot-up, and manually clear the CMOS array. Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The system is booted with the jumper in new position, then powered back down. The jumper is replaced back to the normal position, then the system is rebooted again. Do not implement a jumper on VccRTC to clear CMOS. Warning: 5.12 Processor Interface (D31:F0) The ICH10 interfaces to the processor with a variety of signals • Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUPWRGD, DPSLP# • Standard Input from processor: FERR#, THRMTRIP# Most ICH10 outputs to the processor use standard buffers. The ICH10 has separate V_CPU_IO signals that are pulled up at the system level to the processor voltage, and thus determines VOH for the outputs to the processor. 5.12.1 Processor Interface Signals This section describes each of the signals that interface between the ICH10 and the processor(s). Note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping. 5.12.1.1 A20M# (Mask A20) The A20M# signal is active (low) when both of the following conditions are true: • The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0 • The A20GATE input signal is a 0 The A20GATE input signal is expected to be generated by the external microcontroller (KBC). 138 Datasheet Functional Description 5.12.1.2 INIT# (Initialization) The INIT# signal is active (driven low) based on any one of several events described in Table 5-22. When any of these events occur, INIT# is driven low for 16 PCI clocks, then driven high. Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after STPCLK# goes inactive. This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#, as INIT3_3V# is functionally identical to INIT#, but signaling at 3.3 V. Table 5-22. INIT# Going Active Cause of INIT# Going Active Shutdown special cycle from processor observed on ICH-(G)MCH interconnect (from (G)MCH). PORT92 write, where INIT_NOW (bit 0) transitions from 0-to-1. PORTCF9 write, where SYS_RST (bit 1) was a 0 and RST_CPU (bit 2) transitions from 0-to-1. 0-to-1 transition on RCIN# must occur before the Intel® ICH10 will arm INIT# to be generated again. NOTE: RCIN# signal is expected to be low during S3, S4, and S5 states. Transition on the RCIN# signal in those states (or the transition to those states) may not necessarily cause the INIT# signal to be generated to the processor. To enter BIST, software sets CPU_BIST_EN bit and then does a full processor reset using the CF9 register. Comment INIT# assertion based on value of Shutdown Policy Select register (SPS) RCIN# input signal goes low. RCIN# is expected to be driven by the external microcontroller (KBC). CPU BIST 5.12.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric Error) The ICH10 supports the coprocessor error function with the FERR#/IGNNE# pins. The function is enabled via the COPROC_ERR_EN bit (Chipset Config Registers:Offset 31FFh: bit 1 for Consumer Family and Offset 31FEh: bit 9 for Corporate family). FERR# is tied directly to the Coprocessor Error signal of the processor. If FERR# is driven active by the processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register (I/O Register F0h), the ICH10 negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active. Datasheet 139 Functional Description Figure 5-5. Coprocessor Error Timing Diagram FERR# Internal IRQ13 I/O Write to F0h IGNNE# If COPROC_ERR_EN is not set, the assertion of FERR# will not generate an internal IRQ13, nor will the write to F0h generate IGNNE#. 5.12.1.4 NMI (Non-Maskable Interrupt) Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-23. Table 5-23. NMI Sources Cause of NMI SERR# goes active (either internally, externally via SERR# signal, or via message from (G)MCH) IOCHK# goes active via SERIRQ# stream (ISA system Error) Comment Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). 5.12.1.5 Stop Clock Request (STPCLK#) The ICH10 power management logic controls this active-low signal. Refer to Section 5.13 for more information on the functionality of this signal. 5.12.1.6 CPU Power Good (CPUPWRGD) This signal is connected to the processor’s PWRGOOD input. This signal represents a logical AND of the ICH10’s PWROK and VRMPWRGD signals. 5.12.1.7 Deeper Sleep (DPSLP#) This active-low signal controls the internal gating of the processor’s core clock. This signal asserts before and deasserts after the STP_CPU# signal to effectively stop the processor’s clock (internally) in the states in which STP_CPU# can be used to stop the processor’s clock externally. 140 Datasheet Functional Description 5.12.2 5.12.2.1 Dual-Processor Issues Signal Differences In dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. Table 5-24. DP Signal Differences Signal A20M# / A20GATE STPCLK# FERR# / IGNNE# Difference Generally not used, but still supported by Intel® ICH10. Used for S1 State as well as preparation for entry to S3–S5 Also allows for THRM# based throttling (not via ACPI control methods). Should be connected to both processors. Generally not used, but still supported by ICH10. 5.12.2.2 Power Management For multiple-processor (or Multiple-core) configurations in which more than one Stop Grant cycle may be generated, the (G)MCH is expected to count Stop Grant cycles and only pass the last one through to the ICH10. This prevents the ICH10 from getting out of sync with the processor on multiple STPCLK# assertions. Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected to both processors. However, for ACPI implementations, the BIOS must indicate that the ICH10 only supports the C1 state for dual-processor designs. In going to the S1 state, multiple Stop-Grant cycles will be generated by the processors. It is assumed that prior to setting the SLP_EN bit (which causes the transition to the S1 state), the processors will not be executing code that is likely to delay the Stop-Grant cycles. In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose power. Upon exit from those states, the processors will have their power restored. Datasheet 141 Functional Description 5.13 5.13.1 Power Management (D31:F0) Features • Support for Advanced Configuration and Power Interface, Version 3.0a (ACPI) providing power and thermal management — ACPI 24-Bit Timer — Software initiated throttling of processor performance for Thermal and Power Reduction — Hardware Override to throttle processor performance if system too hot — SCI and SMI# Generation — ACPI C2 state Stop-Grant state (using STPCLK# signal) halts processor’s instruction stream • PCI PME# signal for Wake Up from Low-Power states • System Clock Control — ACPI C3 State: Ability to halt processor clock (but not memory clock) — ACPI C4 State: Ability to lower processor voltage. • System Sleep State Control — ACPI S1 state: Stop Grant (using STPCLK# signal) halts processor’s instruction stream (only STPCLK# active) — ACPI S3 state — Suspend to RAM (STR) — ACPI S4 state — Suspend-to-Disk (STD) — ACPI G2/S5 state — Soft Off (SOFF) — Power Failure Detection and Recovery • Intel Management Engine Power Management Support — New Wake events from the Intel Management Engine (enabled from all SStates including Catastrophic S5 conditions) • Streamlined Legacy Power Management for APM-Based Systems 5.13.2 Intel® ICH10 and System Power States Table 5-25 shows the power states defined for ICH10-based platforms. The state names generally match the corresponding ACPI states. 142 Datasheet Functional Description Table 5-25. General Power States for Systems Using Intel® ICH10 State/ Substates Legacy Name / Description Full On: Processor operating. Individual devices may be shut down to save power. The different processor operating levels are defined by Cx states, as shown in Table 5-26. Within the C0 state, the Intel® ICH10 can throttle the processor using the STPCLK# signal to reduce power consumption. The throttling can be initiated by software or by the operating system or BIOS. Auto-Halt: Processor has executed an AutoHalt instruction and is not executing code. The processor snoops the bus and maintains cache coherency. Stop-Grant: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts its instruction stream, and remains in that state until the STPCLK# signal goes inactive. In the Stop-Grant state, the processor snoops the bus and maintains cache coherency. Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts its instruction stream. ICH10 then asserts DPSLP# followed by STP_CPU#, which forces the clock generator to stop the processor clock. Accesses to memory (by graphics, PCI, or internal units) is not permitted while in a C3 state. Stop-Clock with Lower Processor Voltage: This closely resembles the G0/ S0/C3 state. However, after the ICH10 has asserted STP_CPU#, it then lowers the voltage to the processor. This reduces the leakage on the processor. Prior to exiting the C4 state, the ICH10 increases the voltage to the processor. Stop-Grant: Similar to G0/S0/C2 state. G1/S1 Note: The behavior for this state is slightly different when supporting Intel 64 processors. Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except RTC clock. Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking. Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC. No “Wake” events are possible, because the system does not have any power. This state occurs if the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the “waking” logic. When system power returns, transition will depend on the state just prior to the entry to G3 and the AFTERG3 bit in the GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-33 for more details. G0/S0/C0 G0/S0/C1 G0/S0/C2 G0/S0/C3 G0/S0/C4 G1/S3 G1/S4 G2/S5 G3 Table 5-26 shows the transitions rules among the various states. Note that transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S1, it may appear to pass through the G0/S0 states. These intermediate transitions and states are not listed in the table. Datasheet 143 Functional Description Table 5-26. State Transition Rules for Intel® ICH10 Present State Transition Trigger • Processor halt instruction • Level 2 Read • Level 3 Read G0/S0/C0 • Level 4 Read • SLP_EN bit set • Power Button Override • Mechanical Off/Power Failure • G0/S0/C1 • G0/S0/C2 • G0/S0/C3 or G0/S0/C4 - depending on C4onC3_EN bit (D31:F0:Offset A0h:bit 7) and BM_STS_ZERO_EN bit (D31:F0:Offset A9h:bit 2) • G1/Sx or G2/S5 state • G2/S5 • G3 • Any Enabled Break Event G0/S0/C1 • STPCLK# goes active • Power Button Override • Power Failure • Any Enabled Break Event G0/S0/C2 • Power Button Override • Power Failure • Previously in C3/C4 and bus masters idle • Any Enabled Break Event • Any Bus Master Event G0/S0/C3 • Power Button Override • Power Failure • Previously in C4 and bus masters idle • Any Enabled Break Event G0/S0/C4 • Any Bus Master Event • Power Button Override • Power Failure G1/S1, G1/S3, or G1/S4 G2/S5 • Any Enabled Wake Event • Power Button Override • Power Failure • Any Enabled Wake Event • Power Failure • Power Returns G3 • G0/S0/C0 • G0/S0/C2 • G2/S5 • G3 • G0/S0/C0 • G2/S5 • G3 • C3 or C4 - depending on PDME bit (D31:F0: Offset A9h: bit 4) • G0/S0/C0 • G0/S0/C2 - if PUME bit (D31:F0: Offset A9h: bit 3) is set, else G0/S0/C0 • G2/S5 • G3 • C4 - depending on PDME bit (D31:F0: Offset A9h: bit 4 • G0/S0/C0 • G0/S0/C2 - if PUME bit (D31:F0: Offset A9h: bit 3) is set, else G0/S0/C0 • G2/S5 • G3 • G0/S0/C0 • G2/S5 • G3 • G0/S0/C0 • G3 • Optional to go to S0/C0 (reboot) or G2/ S5 (stay off until power button pressed or other wake event). (See Note 1) Next State NOTES: 1. Some wake events can be preserved through power failure. 144 Datasheet Functional Description 5.13.3 System Power Planes The system has several independent power planes, as described in Table 5-27. Note that when a particular power plane is shut off, it should go to a 0 V level. s Table 5-27. System Power Plane Plane Controlled By SLP_S3# signal Description The SLP_S3# signal can be used to cut the power to the processor completely. The DPRSLPVR support allows lowering the processor’s voltage during the C4 state. When SLP_S3# goes active, power can be shut off to any circuit not required to wake the system from the S3 state. Since the S3 state requires that the memory context be preserved, power must be retained to the main memory. The processor, devices on the PCI bus, LPC I/F, and graphics will typically be shut off when the Main power plane is shut, although there may be small subsections powered. When the SLP_S4# goes active, power can be shut off to any circuit not required to wake the system from the S4. Since the memory context does not need to be preserved in the S4 state, the power to the memory can also be shut down. When SLP_S5# goes active, power can be shut to any circuit not required to wake the system from the S5 state. Since the memory context does not need to be preserved in the S5 state, the power to the memory can also be shut. This pin is asserted when the manageability platform goes to MOff. Depending on the platform, this pin may be used to control the (G)MCH, ICH controller link power planes, the clock chip power, and the SPI flash power. Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen. CPU MAIN SLP_S3# signal MEMORY SLP_S4# signal SLP_S5# signal Link Controller SLP_M# DEVICE[n] GPIO 5.13.4 SMI#/SCI Generation On any SMI# event taking place, ICH10 asserts SMI# to the processor, which causes it to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# goes inactive for a minimum of 4 PCI clocks. If another SMI event occurs, SMI# is driven active again. The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that interrupt. In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not (see Section 13.1.3). The interrupt remains asserted until all SCI sources are removed. Table 5-28 shows which events can cause an SMI# and SCI. Note that some events can be programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is typically associated with an ACPI-based system. Each SMI# or SCI source has a corresponding enable and status bit. Datasheet 145 Functional Description Table 5-28. Causes of SMI# and SCI (Sheet 1 of 2) Cause PME# PME_B0 (Internal, Bus 0, PME-Capable Agents) PCI Express* PME Messages PCI Express Hot Plug Message Power Button Press Power Button Override (Note 7) RTC Alarm Ring Indicate USB#1 wakes USB#2 wakes USB#3 wakes USB#4 wakes USB#5 wakes USB#6 wakes THRM# pin active ACPI Timer overflow (2.34 sec.) SCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes SMI Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Additional Enables PME_EN=1 PME_B0_EN=1 PCI_EXP_EN=1 (Not enabled for SMI) HOT_PLUG_EN=1 (Not enabled for SMI) PWRBTN_EN=1 None RTC_EN=1 RI_EN=1 USB1_EN=1 USB2_EN=1 USB3_EN=1 USB4_EN=1 USB5_EN=1 USB6_EN=1 THRM_EN=1 TMROF_EN=1 GPI[x]_Route=10 (SCI) GPI[x]_Route=01 (SMI) GPE0[x]_EN=1 TCOSCI_EN=1 none TCO_EN=1 none none none none NMI2SMI_EN=1 INTRD_SEL=10 BC.LE=1 Where Reported PME_STS PME_B0_STS PCI_EXP_STS HOT_PLUG_STS PWRBTN_STS PRBTNOR_STS RTC_STS RI_STS USB1_STS USB2_STS USB3_STS USB4_STS USB5_STS USB6_STS THRM_STS TMROF_STS Any GPI Yes Yes GPI[x]_STS GPE0_STS TCOSCI_STS MCHSCI_STS TCO_STS NEWCENTURY_STS TIMEOUT OS_TCO_SMI MCHSMI_STS NMI2SMI_STS INTRD_DET BIOSWR_STS TCO SCI Logic TCO SCI message from (G)MCH TCO SMI Logic TCO SMI — Year 2000 Rollover TCO SMI — TCO TIMEROUT TCO SMI — OS writes to TCO_DAT_IN register TCO SMI — Message from (G)MCH TCO SMI — NMI occurred (and NMIs mapped to SMI) TCO SMI — INTRUDER# signal goes active TCO SMI8 — Change of the BIOSWP bit from 0 to 1 Yes Yes No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes 146 Datasheet Functional Description Table 5-28. Causes of SMI# and SCI (Sheet 2 of 2) Cause TCO SMI — Write attempted to BIOS BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event UHCI USB Legacy logic Serial IRQ SMI reported Device monitors match address in its range SMBus Host Controller SMBus Slave SMI message SMBus SMBALERT# signal active SMBus Host Notify message received Access microcontroller 62h/ 66h SLP_EN bit written to 1 USB Per-Port Registers Write Enable bit changes to 1. Write attempted to BIOS GPIO Lockdown Enable bit changes from ‘1’ to ‘0’. SCI No Yes No No No No No No No No No SMI Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Additional Enables BIOSWP=1 GBL_EN=1 BIOS_EN=1 APMC_EN = 1 PERIODIC_EN=1 SWSMI_TMR_EN=1 LEGACY_USB2_EN = 1 INTEL_USB2_EN = 1 LEGACY_USB_EN=1 none none SMB_SMI_EN Host Controller Enabled none none HOST_NOTIFY_INTRE N MCSMI_EN SMI_ON_SLP_EN=1 USB2_EN=1, Write_Enable_SMI_En able=1 BIOSWPD = 0 GPIO_UNLOCK_SMI_E N=1 Where Reported BIOSWR_STS GBL_STS BIOS_STS APM_STS PERIODIC_STS SWSMI_TMR_STS LEGACY_USB2_STS INTEL_USB2_STS LEGACY_USB_STS SERIRQ_SMI_STS DEVTRAP_STS No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes SMBus host status reg. SMBUS_SMI_STS SMBUS_SMI_STS SMBUS_SMI_STS HOST_NOTIFY_STS MCSMI_STS SMI_ON_SLP_EN_STS USB2_STS, Write Enable Status BIOSWR_STS GPIO_UNLOCK_SMI_S TS NOTES: 1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI. 2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode). 3. GBL_SMI_EN must be 1 to enable SMI. 4. EOS must be written to 1 to re-enable SMI for the next 1. 5. ICH10 must have SMI# fully enabled when ICH10 is also enabled to trap cycles. If SMI# is not enabled in conjunction with the trap enabling, then hardware behavior is undefined. 6. Only GPI[15:0] may generate an SMI# or SCI. 7. When a power button override first occurs, the system will transition immediately to S5. The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting SCI_EN. 8. This SMI is a synchronous event. Datasheet 147 Functional Description PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages. When a PME message is received, ICH10 will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is also set, the ICH10 can cause an SCI via the GPE1_STS register. PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1 register. It is also capable of generating an SMI. However, it is not capable of generating a wake event. 5.13.5 Dynamic Processor Clock Control The ICH10 has extensive control for dynamically starting and stopping system clocks. The clock control is used for transitions among the various S0/Cx states, and processor throttling. Each dynamic clock control method is described in this section. The various sleep states may also perform types of non-dynamic clock control. The ICH10 supports the ACPI C0, C1, C2, C3, and C4 states. The Dynamic Processor Clock control is handled using the following signals: • STPCLK#: Used to halt processor instruction stream. • STP_CPU#: Used to stop processor’s clock • DPSLP#: Used to force Deeper Sleep for processor. • DPRSLPVR: Used to lower voltage of VRM during C4 state. • DPRSTP#: Used to alert the processor of C4 state. Also works in conjunction with DPRSLPVR to communicate to the VRM whether a slow or fast voltage ramp should be used. The C1 state is entered based on the processor performing an auto halt instruction. The C2 state is entered based on the processor reading the Level 2 register in the ICH10. The C2 state can also be entered from C3 or C4 states if bus masters require snoops and the PUME bit (D31:F0: Offset A9h: bit 3) is set. The C3 state is entered based on the processor reading the Level 3 register in the ICH10 and when the C4onC3_EN bit is clear (D31:F0:Offset A0:bit 7). This state can also be entered after a temporary return to C2 from a prior C3 or C4 state. The C4 state is entered based on the processor reading the Level 4 register in the ICH10, or by reading the Level 3 register when the C4onC3_EN bit is set. This state can also be entered after a temporary return to C2 from a prior C4 state. A C1, C2, C3, or C4 state ends due to a Break event. Based on the break event, the ICH10 returns the system to C0 state. Table 5-29 lists the possible break events from C2, C3, or C4. The break events from C1 are indicated in the processor’s datasheet. 148 Datasheet Functional Description Table 5-29. Break Events Event Any unmasked interrupt goes active Any internal event that cause an NMI or SMI# Any internal event that cause INIT# to go active Any bus master request (internal, external or DMA, or BMBUSY#) goes active and BM_RLD=1 (D31:F0:Offset PMBASE+04h: bit 1) Processor Pending Break Event Indication Breaks from C2 Comment IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O APIC. Since SCI is an interrupt, any SCI will also be a break event. Many possible sources Could be indicated by the keyboard controller via the RCIN input signal. Need to wake up processor so it can do snoops C3, C4 Note: If the PUME bit (D31:F0: Offset A9h: bit 3) is set, then bus master activity will NOT be treated as a break event. Instead, there will be a return only to the C2 state. Only available if FERR# enabled for break event indication (See FERR# Mux Enable in GCS, Chipset Config Registers:Offset 3410h:bit 6) Can be sent at any time after the Ack-C2 message and before the Ack-C0 message, when not in C0 state. C2 C2 C2 REQ-C0 Message from (G)MCH C2 5.13.5.1 Slow C4 Exit In order to eliminate the audible noise caused by aggressive voltage ramps when exiting C4 the states at a regular, periodic frequency, the ICH10 supports a method to slow down the voltage ramp at the processor VR for certain break events. If enabled for this behavior, the ICH10 treats IRQ0 and IRQ8 as “slow” break events since both of these can be the system timer tick interrupt. Rather than carefully tracking the interrupt and timer configuration information to track the one correct interrupt, it was deemed acceptable to simplify the logic and slow the break exit sequence for both interrupts. Other break event sources invoke the normal exit timings. The ICH10 indicates that a slow voltage ramp is desired by deasserting DPRSTP# (high) and leaving DPRSLPVR asserted (high). The normal voltage ramp rate is communicated by deasserting DPRSTP# (high) and deasserting DPRSLPVR (low). The ICH10 waits an additional delay before starting the normal voltage ramp timer during the C4 or C5 exit sequence. If a “fast” break event occurs during the additional, slow-Exit time delay, the ICH10 quickly deasserts DPRSLPVR (low), thereby speeding up the voltage ramp and reducing the delay to a value that is typically seen by the device in the past. In the event that a fast break event and a slow break event occur together, the fast flow is taken. Datasheet 149 Functional Description 5.13.5.2 Transition Rules among S0/Cx and Throttling States The following priority rules and assumptions apply among the various S0/Cx and throttling states: • Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because the processor can only perform one register access at a time and Sleep states have higher priority than thermal throttling. • When the SLP_EN bit is set (system going to a S1 - S5 sleep state), the THTL_EN and FORCE_THTL bits can be internally treated as being disabled (no throttling while going to sleep state). • If the THTL_EN or FORCE_THTL bits are set, and a Level 2, Level 3 or Level 4 read then occurs, the system should immediately go and stay in a C2, C3 or C4 state until a break event occurs. A Level 2, Level 3 or Level 4 read has higher priority than the software initiated throttling. • After an exit from a C2, C3 or C4 state (due to a Break event), and if the THTL_EN or FORCE_THTL bits are still set the system will continue to throttle STPCLK#. Depending on the time of break event, the first transition on STPCLK# active can be delayed by up to one THRM period (1024 PCI clocks = 30.72 µs). • The Host controller must post Stop-Grant cycles in such a way that the processor gets an indication of the end of the special cycle prior to the ICH10 observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a sufficient period after the processor observes the response phase. • If in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop-Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should return to the C1 state. 5.13.5.3 Deferred C3/C4 Due to the new DMI protocol, if there is any bus master activity (other than true isochronous), then the C0 to C3 transition will pause at the C2 state. ICH10 will keep the processor in a C2 state until: • ICH10 sees no bus master activity. • A break event occurs. In this case, the ICH10 will perform the C2 to C0 sequence. Note that bus master traffic is not a break event in this case. To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be set. This will cause the BM_STS bit to read as 0 even if some bus master activity is present. If this is not done, then the software may avoid even attempting to go to the C3 or C4 state if it sees the BM_STS bit as 1. If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH10 will treat bus master activity as a break event. When reaching the C2 state, if there is any bus master activity, the ICH10 will return the processor to a C0 state. 5.13.5.4 POPUP (Auto C3/C4 to C2) When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH10 enables a mode of operation where standard (non-isochronous) bus master activity will not be treated as a full break event from the C3 or C4 states. Instead, these will be treated merely as bus master events and return the platform to a C2 state, and thus allow snoops to be performed. After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even if the ARB_DIS bit is set. 150 Datasheet Functional Description 5.13.5.5 POPDOWN (Auto C2 to C3/C4) After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4) is set, the platform can return to a C3 or C4 state (depending on where it was prior to going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will keep the processor in a C2 state until: • Bus masters are no longer active. • A break event occurs. Note: Bus master traffic is not a break event in this case. 5.13.6 5.13.6.1 Sleep States Sleep State Overview The ICH10 directly supports different sleep states (S1–S5), which are entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states is based on several assumptions: • Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the processor can only perform one register access at a time. A request to Sleep always has higher priority than throttling. • Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN bit disables thermal throttling (since S1–S5 sleep state has higher priority). • The G3 state cannot be entered via any software mechanism. The G3 state indicates a complete loss of power. 5.13.6.2 Initiating Sleep State Sleep states (S1–S5) are initiated by: • Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts to gracefully put the system into the corresponding Sleep state. • Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override event. In this case the transition to the S5 state is less graceful, since there are no dependencies on observing Stop-Grant cycles from the processor or on clocks other than the RTC clock. • Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can occur when system is in S0 or S1 state. Table 5-30. Sleep Types Sleep Type S1 Comment Intel ICH10 asserts the STPCLK# signal. This lowers the processor’s power consumption. No snooping is possible in this state. ICH10 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is only retained to devices needed to wake from this sleeping state, as well as to the memory. ICH10 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to the memory subsystem. Only devices needed to wake from this state should be powered. Same power state as S4. ICH10 asserts SLP_S3#, SLP_S4# and SLP_S5#. S3 S4 S5 Datasheet 151 Functional Description 5.13.6.3 Exiting Sleep States Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the hard disk may be shut off during a sleep state, and have to be enabled via a GPIO pin before it can be used. Upon exit from the ICH10-controlled Sleep states, the WAK_STS bit is set. The possible causes of Wake Events (and their restrictions) are shown in Table 5-31. Table 5-31. Causes of Wake Events Cause RTC Alarm Power Button GPI[0:15] States Can Wake From S1–S5 (Note 1) S1–S5 S1–S5 (Note 1) S1–S4 S1–S5 S1–S5 (Note 1) S1–S5 S1–S5 (Note 1) S1–S5 S1–S5 S1 S1 S1–S5 S1–S5 How Enabled Set RTC_EN bit in PM1_EN register Always enabled as Wake event. (Note 2). GPE0_EN register NOTE: GPIs that are in the core well are not capable of waking the system from sleep states when the core well is not powered. Set USB1_EN, USB 2_EN, USB3_EN, USB4_EN, USB5_EN, and USB6_EN bits in GPE0_EN register Will use PME#. Wake enable set with LAN logic. Set RI_EN bit in GPE0_EN register Event sets PME_B0_STS bit; PM_B0_EN must be enabled. Can not wake from S5 state if it was entered due to power failure or power button override. PME_B0_EN bit in GPE0_EN register Set PME_EN bit in GPE0_EN register. PCI_EXP_WAKE bit (Note 3) Set PME_EN bit in GPE0_EN register. (Note 4) Must use the PCI Express* WAKE# pin rather than messages for wake from S3,S4, or S5. Always enabled as Wake event Wake/SMI# command always enabled as a Wake event. NOTE: SMBus Slave Message can wake the system from S1–S5, as well as from S5 due to Power Button Override. (Note 2). HOST_NOTIFY_WKEN bit SMBus Slave Command register. Reported in the SMB_WAK_STS bit in the GPEO_STS register. Always enabled as Wake event. (Note 2). Classic USB LAN RI# Intel® High Definition Audio Primary PME# Secondary PME# PCI_EXP_WAKE# SATA PCI_EXP PME Message SMBALERT# SMBus Slave Wake Message (01h) SMBus Host Notify message received ME Non-Maskable Wake S1–S5 S1–S5 NOTES: 1. This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP bits via software, or if there is a power failure. 2. If in the S5 state due to a power button override or THRMTRIP#, the possible wake events are due to Power Button, Hard Reset Without Cycling (See Command Type 3 in Table 5-53), Hard Reset System (See Command Type 4 in Table 5-53), Wake SMBus Slave Message (01h), and ME initiated non-maskable wake. 152 Datasheet Functional Description 3. 4. When the WAKE# pin is active and the PCI Express device is enabled to wake the system, the ICH10 will wake the platform. SATA can only trigger a wake event in S1, but if PME is asserted prior to S3/S4/S5 entry and software does not clear the PME_B0_STS, a wake event would still result. It is important to understand that the various GPIs have different levels of functionality when used as wake events. The GPIs that reside in the core power well can only generate wake events from sleep states where the core well is powered. Also, only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in ACPI I/O space. Table 5-32 summarizes the use of GPIs as wake events. Table 5-32. GPI Wake Events GPI GPI[7:0] GPI[15:8] Power Well Core Suspend Wake From S1 S1–S5 Notes ACPI Compliant ACPI Compliant The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the ICH10 are insignificant. 5.13.6.4 PCI Express* WAKE# Signal and PME Event Message PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go active in the GPE_STS register. PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages. When a PME message is received, ICH10 will set the PCI_EXP_STS bit. 5.13.6.5 Sx-G3-Sx, Handling Power Failures Depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. The AFTER_G3 bit provides the ability to program whether or not the system should boot once power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state (unless previously in S4). There are only three possible events that will wake the system after a power failure. 1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3 state), the PWRBTN_STS bit is reset. When the ICH10 exits G3 after power returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCCstandby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0. 2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. If this signal goes low (active), when power returns the RI_STS bit is set and the system interprets that as a wake event. 3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low. The ICH10 monitors both PWROK and RSMRST# to detect for power failures. If PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set. Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. Datasheet 153 Functional Description Table 5-33. Transitions Due to Power Failure State at Power Failure S0, S1, S3 S4 S5 AFTERG3_EN bit 1 0 1 0 1 0 Transition When Power Returns S5 S0 S4 S0 S5 S0 5.13.7 Thermal Management The ICH10 has mechanisms to assist with managing thermal problems in the system. 5.13.7.1 THRM# Signal The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal going active, the ICH10 generates an SMI# or SCI (depending on SCI_EN). If the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS bit will be set. This is an indicator that the thermal threshold has been exceeded. If the THRM_EN bit is set, then when THRM_STS goes active, either an SMI# or SCI will be generated (depending on the SCI_EN bit being set). The power management software (BIOS or ACPI) can then take measures to start reducing the temperature. Examples include shutting off unwanted subsystems, or halting the processor. By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated when the THRM# signal goes back high. This allows the software (BIOS or ACPI) to turn off the cooling methods. Note: THRM# assertion does not cause a TCO event message in S3 or S4. The level of the signal is not reported in the heartbeat message. 5.13.7.2 Software Initiated Passive Cooling This mode is initiated by software setting the THTL_EN or FORCE_THTL bits. Software sets the THTL_DTY or THRM_DTY bits to select throttle ratio and THTL_EN or FORCE_THTL bit to enable the throttling. Throttling results in STPCLK# active for a minimum time of 12.5% and a maximum of 87.5%. The period is 1024 PCI clocks. Thus, the STPCLK# signal can be active for as little as 128 PCI clocks or as much as 896 PCI clocks. The actual slowdown (and cooling) of the processor depends on the instruction stream, because the processor is allowed to finish the current instruction. Furthermore, the ICH10 waits for the STOPGRANT cycle before starting the count of the time the STPCLK# signal is active. 154 Datasheet Functional Description 5.13.7.3 THRM# Override Software Bit The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI software (which uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH10 starts throttling using the ratio in the THRM_DTY field. When this bit is cleared the ICH10 stops throttling, unless the THTL_EN bit is set (indicating that ACPI software is attempting throttling). If both the THTL_EN and FORCE_THTL bits are set, then the ICH should use the duty cycle defined by the THRM_DTY field, not the THTL_DTY field. 5.13.7.4 Active Cooling Active cooling involves fans. The GPIO signals from the ICH10 can be used to turn on/ off a fan. 5.13.8 Event Input Signals and Their Usage The ICH10 has various input signals that trigger specific events. This section describes those signals and how they should be used. 5.13.8.1 PWRBTN# (Power Button) The ICH10 PWRBTN# signal operates as a “Fixed Power Button” as described in the Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition descriptions are included in Table 5-34. Note that the transitions start as soon as the PWRBTN# is pressed (but after the debounce logic), and does not depend on when the Power Button is released. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled), the Power Button is not a wake event. Refer to Power Button Override Function section below for further detail. Table 5-34. Transitions Due to Power Button Present State Event Transition/Action SMI# or SCI generated (depending on SCI_EN, PWRBTN_INIT_EN, PWRBTN_EN and GLB_SMI_EN) Wake Event. Transitions to S0 state None Unconditional transition to S5 state Comment S0/Cx PWRBTN# goes low Software typically initiates a Sleep state S1–S5 G3 PWRBTN# goes low PWRBTN# pressed PWRBTN# held low for at least 4 consecutive seconds Standard wakeup No effect since no power Not latched nor detected No dependence on processor (e.g., Stop-Grant cycles) or any other subsystem S0–S4 Datasheet 155 Functional Description Power Button Override Function (ICH10 Consumer Only) If PWRBTN# is observed active for at least four consecutive seconds, the state machine unconditionally transitions to the G2/S5 state, regardless of present state (S0-S4), even if PWROK is not active. In this case, the transition to the G2/S5 state does not depend on any particular response from the processor (e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem. The PWRBTN# status is readable to check if the button is currently being pressed or has been released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit. Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The 4-second timer starts counting when the ICH10 is in a S0 state. If the PWRBTN# signal is asserted and held active when the system is in a suspend state (S1-S5), the assertion causes a wake event. Once the system has resumed to the S0 state, the 4second timer starts. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. Power Button Override Function (ICH10 Corporate Only) If PWRBTN# is observed active for at least four consecutive seconds when in S0/1 or at least nine consecutive seconds when in S3-S4, the state machine unconditionally transitions to the G2/S5 state, even if PWROK is not active. In this case, the transition to the G2/S5 state does not depend on any particular response from the processor (e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem. The PWRBTN# status is readable to check if the button is currently being pressed or has been released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit. Note: A 4 to 9 second PWRBTN# assertion should only be used if a system lock-up has occurred. The power button override timer starts counting when PWRBTN# is asserted and will be set to 4 seconds when the platform is in S0/S1 and 9 seconds when the platform is in S3-S4 in order to trigger a power button override event. Note: During the time that the SLP_S3#/SLP_S4# signal is stretched for the minimum assertion width (if enabled in D31:F0:A4h), a Power Button is not wake event. For this reason, the ICH10 Corporate will always extend the power button override timer to 9 seconds when in S3/S4 to allow for a wake event that is delayed by SLP_S3#/SLP_S4# stretching to be observed before accidentaly triggering a power button override event. Sleep Button The Advanced Configuration and Power Interface, Version 2.0b defines an optional Sleep button. It differs from the power button in that it only is a request to go from S0 to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the Sleep Button cannot. Although the ICH10 does not include a specific signal designated as a Sleep Button, one of the GPIO signals can be used to create a “Control Method” Sleep Button. See the Advanced Configuration and Power Interface, Version 2.0b for implementation details. 156 Datasheet Functional Description 5.13.8.2 RI# (Ring Indicator) The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states. Table 5-35 shows when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the ICH10 generates an interrupt based on RI# active, and the interrupt will be set up as a Break event. Table 5-35. Transitions Due to RI# Signal Present State S0 S1–S5 Event RI# Active RI# Active RI_EN X 0 1 Event Ignored Ignored Wake Event Note: Filtering/Debounce on RI# will not be done in ICH10. Can be in modem or external. 5.13.8.3 PME# (PCI Power Management Event) The PME# signal comes from a PCI device to request that the system be restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME# signal goes from high to low. No event is caused when it goes from low to high. There is also an internal PME_B0 bit. This is separate from the external PME# signal and can cause the same effect. 5.13.8.4 SYS_RESET# Signal When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the ICH10 attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter starts. If at any point during the count the SMBus goes idle the reset occurs. If, however, the counter expires and the SMBus is still active, a reset is forced upon the system even though activity is still occurring. Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the SYSRESET# input remains asserted or not. It cannot occur again until SYS_RESET# has been detected inactive after the debounce logic, and the system is back to a full S0 state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle reset. 5.13.8.5 THRMTRIP# Signal If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH10 immediately transitions to an S5 state. However, since the processor has overheated, it does not respond to the ICH10’s STPCLK# pin with a stop grant special cycle. Therefore, the ICH10 does not wait for one. Immediately upon seeing THRMTRIP# low, the ICH10 initiates a transition to the S5 state, drive SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit. The transition looks like a power button override. When a THRMTRIP# event occurs, the ICH10 will power down immediately without following the normal S0 -> S5 path. The ICH10 will immediately drive SLP_S3#, SLP_S4#, and SLP_S5# low after sampling THRMTRIP# active. If the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the ICH10, are no longer executing cycles properly. Therefore, if THRMTRIP# goes active, and the ICH10 is relying on state machine logic to perform the power down, the state machine may not be working, and the system will not power down. Datasheet 157 Functional Description The ICH provides filtering for short low glitches on the THRMTRIP# signal in order to prevent erroneous system shut downs from noise. Glitches shorter than 25nsec are ignored. During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PWROK = 0, or VRMPWRGD/VGATE = 0. Note: A thermal trip event will: • • • • Set the AFTERG3_EN bit Clear the PWRBTN_STS bit Clear all the GPE0_EN register bits Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave receiving message and not set due to SMBAlert 5.13.8.6 BMBUSY# The BMBUSY# signal is an input from a graphics component to indicate if it is busy. If prior to going to the C3 state, the BMBUSY# signal is active, then the BM_STS bit will be set. If after going to the C3 state, the BMBUSY# signal goes back active, the ICH10 will treat this as if one of the PCI REQ# signals went active. This is treated as a break event. 5.13.9 ALT Access Mode Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the ICH10 implements an ALT access mode. If the ALT access mode is entered and exited after reading the registers of the ICH10 timer (8254), the timer starts counting faster (13.5 ms). The following steps listed below can cause problems: 1. BIOS enters ALT access mode for reading the ICH10 timer related registers. 2. BIOS exits ALT access mode. 3. BIOS continues through the execution of other needed steps and passes control to the operating system. After getting control in step #3, if the operating system does not reprogram the system timer again, the timer ticks may be happening faster than expected. For example DOS and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. Operating systems (e.g., Microsoft Windows* 98, Windows* 2000, and Windows NT*) reprogram the system timer and therefore do not encounter this problem. For some other operating systems (e.g., Microsoft MS-DOS*) the BIOS should restore the timer back to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from ALT access mode. 158 Datasheet Functional Description 5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode The registers described in Table 5-36 have read paths in ALT access mode. The access number field in the table indicates which register will be returned per access to that port. Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2) Restore Data I/O Addr # of Rds Access 1 00h 2 2 1 01h 2 2 1 02h 2 2 1 03h 2 2 1 04h 2 2 1 05h 2 2 1 06h 2 2 1 07h 2 2 Data DMA Chan 0 base address low byte DMA Chan 0 base address high byte DMA Chan 0 base count low byte DMA Chan 0 base count high byte DMA Chan 1 base address low byte DMA Chan 1 base address high byte DMA Chan 1 base count low byte DMA Chan 1 base count high byte DMA Chan 2 base address low byte DMA Chan 2 base address high byte DMA Chan 2 base count low byte DMA Chan 2 base count high byte DMA Chan 3 base address low byte DMA Chan 3 base address high byte DMA Chan 3 base count low byte DMA Chan 3 base count high byte 41h 42h 70h 1 1 1 1 C4h 2 2 1 C6h 2 2 1 C8h 2 2 40h 7 I/O Addr # of Rds Restore Data Access 1 2 3 4 5 6 7 Data Timer Counter 0 status, bits [5:0] Timer Counter 0 base count low byte Timer Counter 0 base count high byte Timer Counter 1 base count low byte Timer Counter 1 base count high byte Timer Counter 2 base count low byte Timer Counter 2 base count high byte Timer Counter 1 status, bits [5:0] Timer Counter 2 status, bits [5:0] Bit 7 = NMI Enable, Bits [6:0] = RTC Address DMA Chan 5 base address low byte DMA Chan 5 base address high byte DMA Chan 5 base count low byte DMA Chan 5 base count high byte DMA Chan 6 base address low byte DMA Chan 6 base address high byte Datasheet 159 Functional Description Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2) Restore Data I/O Addr # of Rds Access 1 2 3 08h 6 4 5 6 1 2 3 4 5 20h 12 6 7 8 9 10 11 12 Data DMA Chan 0–3 Command2 CAh DMA Chan 0–3 Request DMA Chan 0 Mode: Bits(1:0) = 00 DMA Chan 1 Mode: Bits(1:0) = 01 DMA Chan 2 Mode: Bits(1:0) = 10 DMA Chan 3 Mode: Bits(1:0) = 11. PIC ICW2 of Master controller PIC ICW3 of Master controller PIC ICW4 of Master controller PIC OCW1 of Master controller1 PIC OCW2 of Master controller PIC OCW3 of Master controller PIC ICW2 of Slave controller PIC ICW3 of Slave controller PIC ICW4 of Slave controller PIC OCW1 of Slave controller1 PIC OCW2 of Slave controller PIC OCW3 of Slave controller D0h 6 2 2 1 CCh 2 2 1 CEh 2 2 1 2 3 4 5 6 I/O Addr # of Rds Restore Data Access 1 Data DMA Chan 6 base count low byte DMA Chan 6 base count high byte DMA Chan 7 base address low byte DMA Chan 7 base address high byte DMA Chan 7 base count low byte DMA Chan 7 base count high byte DMA Chan 4–7 Command2 DMA Chan 4–7 Request DMA Chan 4 Mode: Bits(1:0) = 00 DMA Chan 5 Mode: Bits(1:0) = 01 DMA Chan 6 Mode: Bits(1:0) = 10 DMA Chan 7 Mode: Bits(1:0) = 11. NOTES: 1. The OCW1 register must be read before entering ALT access mode. 2. Bits 5, 3, 1, and 0 return 0. 160 Datasheet Functional Description 5.13.9.2 PIC Reserved Bits Many bits within the PIC are reserved, and must have certain values written in order for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. When reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-37. Table 5-37. PIC Reserved Bits Return Values PIC Reserved Bits ICW2(2:0) ICW4(7:5) ICW4(3:2) ICW4(0) OCW2(4:3) OCW3(7) OCW3(5) OCW3(4:3) Value Returned 000 000 00 0 00 0 Reflects bit 6 01 5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode The registers described in Table 5-38 have write paths to them in ALT access mode. Software restores these values after returning from a powered down state. These registers must be handled special by software. When in normal mode, writing to the base address/count register also writes to the current address/count register. Therefore, the base address/count must be written first, then the part is put into ALT access mode and the current address/count register is written. Table 5-38. Register Write Accesses in ALT Access Mode I/O Address 08h D0h Register Write Value DMA Status Register for channels 0–3. DMA Status Register for channels 4–7. Datasheet 161 Functional Description 5.13.10 5.13.10.1 System Power Supplies, Planes, and Signals Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5# and SLP_M# The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power must be maintained to the ICH10 suspend well, and to any other circuits that need to generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM) all signals attached to powered down plans will be tri-stated or driven low, unless they are pulled via a pull-up resistor. Cutting power to the core may be done via the power supply, or by external FETs on the motherboard. The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done via the power supply, or by external FETs on the motherboard. The SLP_S4# output signal is used to remove power to additional subsystems that are powered during SLP_S3#. SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done via the power supply, or by external FETs on the motherboard. SLP_M# output signal can be used to cut power to the Controller Link, Clock chip and SPI flash on a platform that supports Intel AMT. 5.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4# logic in the ICH10 provides a mechanism to fully cycle the power to the DRAM and/or detect if the power is not cycled for a minimum time. Note: To use the minimum DRAM power-down feature that is enabled by the SLP_S4# Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled by the SLP_S4# signal. 162 Datasheet Functional Description 5.13.10.3 PWROK Signal The PWROK input should go active based on the core supply voltages becoming valid. PWROK should go active no sooner than 99 ms after Vcc3_3 and Vcc1_5 have reached their nominal values. PWROK must not glitch, even if RSMRST# is low. Note: 1. SYSRESET# is recommended for implementing the system reset button. This saves external logic that is needed if the PWROK input is used. Additionally, it allows for better handling of the SMBus and processor resets, and avoids improperly reporting power failures. 2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH10. 3. In the case of true PWROK failure, PWROK will go low before VRMPWRGD. 4. When PWROK goes inactive, a host power cycle reset will occur. A host power cycle is the assertion of SLP_S3#, SLP_S4#, and SLP_S5#, and the deassertion of these signals 3-5 seconds later. The Intel Management Engine remains powered throughout this cycle. 5.13.10.4 CPUPWRGD Signal This signal is connected to the processor’s VRM via the VRMPWRGD signal and is internally AND’d with the PWROK signal that comes from the system power supply. 5.13.10.5 VRMPWRGD Signal VRMPWRGD is an input from the regulator indicating that all of the outputs from the regulator are on and within specification. Platforms that use the VRMPWRGD signal to start the clock chip PLLs assume that it asserts milliseconds before PWROK in order to provide valid clocks in time for the PWROK rising. Note: When VRMPWRGD goes inactive, a host power cycle reset will occur. A host power cycle is the assertion of SLP_S3#, SLP_S4#, and SLP_S5#, and the deassertion of these signals 3-5 seconds later. The Intel Management Engine remains powered throughout this cycle. 5.13.10.6 DRAMPWROK Signal (Corporate Only) The DRAMPWROK output is sent to the (G)MCH as an indication of when DRAM power is turned off. The (G)MCH uses this information as one of the conditions for asserting the DDR3 Reset signal. The ICH10’s open-drain buffer pulls the signal low when SLP_S4# is asserted and CLPWROK deasserted. Datasheet 163 Functional Description 5.13.11 Clock Generators The clock generator is expected to provide the frequencies shown in Table 5-39. Table 5-39. Intel® ICH10 Clock Inputs Clock Domain SATA_CLK DMI_CLK PCICLK Frequency 100 MHz Differential 100 MHz Differential 33 MHz Source Main Clock Generator Main Clock Generator Main Clock Generator Main Clock Generator Main Clock Generator Platform LAN Connect Usage Used by SATA controller. Stopped in S3 – S based on SLP_S3# assertion. Used by DMI and PCI Express*. Stopped in S3 – S5 based on SLP_S3# assertion. Free-running PCI Clock to ICH10. Stopped in S3 – S5 based on SLP_S3# assertion. Used by USB controllers and Intel High Definition Audio controller. Stopped in S3 – S5 based on SLP_S3# assertion. Used by ACPI timers. Stopped in S3 – S5 based on SLP_S3# assertion. LAN Connect Interface and Gigabit LAN Connect Interface. Control policy is determined by the clock source. CLK48 48.000 MHz CLK14 14.318 MHz 5 to 62.5 MHz GLAN_CLK 5.13.11.1 Clock Control Signals from Intel® ICH10 to Clock Synthesizer The clock generator is assumed to have direct connect from the following ICH10 signals: • STP_CPU#: Stops processor clocks in C3 and C4 states • STP_PCI#: Stops system PCI clocks (not the ICH10 free-running 33 MHz clock) due to CLKRUN# protocol • SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop clocks in S3 to S5. 164 Datasheet Functional Description 5.13.12 Legacy Power Management Theory of Operation Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. The scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. However, the operating system is assumed to be at least APM enabled. Without APM calls, there is no quick way to know when the system is idle between keystrokes. The ICH10 does not support burst modes. 5.13.12.1 APM Power Management The ICH10 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable register, generates an SMI# once per minute. The SMI handler can check for system activity by reading the DEVACT_STS register. If none of the system bits are set, the SMI handler can increment a software counter. When the counter reaches a sufficient number of consecutive minutes with no activity, the SMI handler can then put the system into a lower power state. If there is activity, various bits in the DEVACT_STS register will be set. Software clears the bits by writing a 1 to the bit position. The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts. 5.13.13 Reset Behavior When a reset is triggered, the ICH10 will send a warning message to the (G)MCH to allow the (G)MCH to attempt to complete any outstanding memory cycles and put memory into a safe state before the platform is reset. When the (G)MCH is ready, it will send an acknowledge message to the ICH10. Once the message is received the ICH10 asserts PLTRST#. The ICH10 does not require an acknowledge message from the (G)MCH to trigger PLTRST#. A global reset will occur after 4 seconds if an acknowledge from the (G)MCH is not received. Note: When the ICH10 causes a reset by asserting PLTRST# its output signals will go to their reset states as defined in Chapter 3. A reset in which the host platform is reset and PLTRST# is asserted is called a Host Reset or Host Partition Reset. Depending on the trigger a host reset may also result in power cycling see Chapter 5-40 for details. If a host reset is triggered and the ICH10 times out before receiving an acknowledge message from the (G)MCH a Global Reset with power cycle will occur. A reset in which the host and ME partitions of the platform are reset is called a Global Reset. Datasheet 165 Functional Description Table 5-40 shows the various reset triggers. Table 5-40. Causes of Host and Global Resets Host Reset without Power Cycle No Yes No Yes No No Yes Yes No No No Yes Yes No No No No No Host Reset with Power Cycle Yes No No No Yes Yes No No No No Yes No No Yes No Yes (Note 3) Yes (Note 4) Yes (Note 4) Global Reset with Power Cycle No (Note 1) No (Note 1) Yes No (Note 1) No (Note 1) No (Note 1) No (Note 1) No (Note 1) Yes (Note 2) Yes No (Note 2) No (Note 1) No (Note 1) No (Note 1) Yes No (Note 1) No (Note 1) No (note 1) Trigger Write of 0Eh to CF9h Register when Global Reset bit = 0b (D31:F0:ACh:20) Write of 06h to CF9h Register when Global Reset bit = 0b Write of 06h or 0Eh to CF9h register when Global Reset bit = 1b SYS_RESET# Asserted and CF9h bit 3 = 0 SYS_RESET# Asserted and CF9h bit 3 = 1 SMBus Slave Message received for Reset with Power Cycle SMBus Slave Message received for Reset without Power Cycle TCO Watchdog timer reaches zero two times Power Failure: PWROK signal or VRMPWRGD signal goes inactive or RSMRST# asserts Special shutdown cycle from CPU causes CF9h-like PLTRST# and CF9h Global Reset bit = 1 Special shutdown cycle from CPU causes CF9h-like PLTRST# and CF9h bit 3 = 1 Special Shutdown Cycle from CPU causes CF9hlike PLTRST# and CF9h Global Reset bit = 0 Intel® Management Engine Triggered Host Reset without power cycle Intel Management Engine Triggered Host Reset with power cycle Intel Management Engine Triggered Global Reset Intel Management Engine Initiated Host Reset with power down Intel Management Engine Watchdog Timer Power Management Watchdog Timer NOTES: 1. Trigger will result in Global Reset with power cycle if the acknowledge message is not received by the ICH10. 2. ICH10 does not send warning message to (G)MCH, reset occurs without delay. 3. ICH10 waits for enabled wake event to complete reset. 4. System stays in S5 state. 166 Datasheet Functional Description 5.14 System Management (D31:F0) The ICH10 provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. In addition, ICH10 provides integrated ASF Management support, requires use of SPI Flash and Intel Management Engine firmware. Features and functions can be augmented via external A/D converters and GPIO, as well as an external microcontroller. The following features and functions are supported by the ICH10: • Processor present detection — Detects if processor fails to fetch the first instruction after reset • Various Error detection (such as ECC Errors) indicated by host controller — Can generate SMI#, SCI, SERR, NMI, or TCO interrupt • Intruder Detect input — Can generate TCO interrupt or SMI# when the system cover is removed — INTRUDER# allowed to go active in any power state, including G3 • Detection of bad BIOS Flash (FWH or Flash on SPI) programming — Detects if data on first read is FFh (indicates that BIOS flash is not programmed) • Ability to hide a PCI device — Allows software to hide a PCI device in terms of configuration space through the use of a device hide register (See Section 10.1.75) Note: Voltage ID from the processor can be read via GPI signals. ASF functionality with the integrated ICH10 ASF controller requires a correctly configured system, including an appropriate SKU of the ICH10 (see Section 1.3), (G)MCH with Intel Management Engine, Intel Management Engine Firmware, system BIOS support, and appropriate Platform LAN Connect Device. 5.14.1 Theory of Operation The System Management functions are designed to allow the system to diagnose failing subsystems. The intent of this logic is that some of the system management functionality can be provided without the aid of an external microcontroller. 5.14.1.1 Detecting a System Lockup When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch the first instruction after reset, the TCO timer times out twice and the ICH10 asserts PLTRST#. Datasheet 167 Functional Description 5.14.1.2 Handling an Intruder The ICH10 has an input signal, INTRUDER#, that can be attached to a switch that is activated by the system’s case being open. This input has a two RTC clock debounce. If INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the TCO_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the ICH10 to cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN bit. The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. Note: The INTRD_DET bit resides in the ICH10’s RTC well, and is set and cleared synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65 µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to ensure that the INTRD_DET bit will be set. If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the bit remains set and the SMI is generated again immediately. The SMI handler can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal goes inactive and then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no SMI# be generated. Note: 5.14.1.3 Detecting Improper Firmware Hub Programming The ICH10 can detect the case where the BIOS flash is not programmed. This results in the first instruction fetched to have a value of FFh. If this occurs, the ICH10 sets the BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus. 5.14.1.4 Heartbeat and Event Reporting via SMLink/SMBus Heartbeat and event reporting via SMLink/SMBus is no longer supported. The Intel AMT logic in ICH10 can be programmed to generate an interrupt to the Intel Management Engine when an event occurs. The Intel Management Engine will poll the TCO registers to gather appropriate bits to send the event message to the Gigabit Ethernet controller, if Intel Management Engine is programmed to do so. The Intel Management Engine is responsible for sending ASF 2.0 messages if programmed to do so. In Advanced TCO BMC mode, the external micro-controller (BMC) accesses the TCO info through SMBus. 168 Datasheet Functional Description 5.14.2 5.14.2.1 TCO Modes TCO Legacy/Compatible Mode In TCO Legacy/Compatible mode the Intel Management Engine and Intel AMT logic and SMBus controllers are disabled. To enable Legacy/Compatible TCO mode the TCOMODE bit 7 in the ICHSTRP0 register in the SPI device must be 0. Note: . SMBus and SMLink may be tied together externally, if a device has a single SMBus interface and needs access to the TCO slave and be visisble to the host SMBus controller. TCO Legacy/Compatible Mode SMBus Configuration Figure 5-6. Intel® ICH10 TCO Compatible Mode Intel ME SMBus Controller 2 Intel® ME SMBus Controller 1 ® X X SPD (Slave) SMBus uCtrl Host SMBus Legacy Sensors (Master or Slave with ALERT) TCO Slave SMLink ASF Sensors (Master or Slave) Datasheet 169 Functional Description In TCO Legacy/Compatible mode the Intel ICH10 can function directly with the integrated Gigabit Ethernet controller or equivalent external LAN controller to report messages to a network management console without the aid of the system processor. This is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. Table 5-41 includes a list of events that will report messages to the network management console. Table 5-41. Event Transitions that Cause Messages Event INTRUDER# pin Assertion? yes Deassertion? no Comments Must be in “S1 or hung S0” state Must be in “S1 or hung S0” state. Note that the THRM# pin is isolated when the core power is off, thus preventing this event in S3-S5. “S1 or hung S0” state entered Must be in “S1 or hung S0” state Must be in “S1 or hung S0” state “S1 or hung S0” state entered THRM# pin yes yes Watchdog Timer Expired GPIO[11]/ SMBALERT# pin BATLOW# CPU_PWR_FLR yes yes yes yes no (NA) yes yes no NOTE: The GPIO11/SMBALERT#/JTAGTDO pin will trigger an event message (when enabled by the GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not. 5.14.2.2 Advanced TCO Mode Intel ICH10 supports two modes of Advanced TCO. Intel Manageability Engine (Intel ME) mode and BMC mode. To enable Advance TCO mode (Intel ME or BMC mode) the TCOMODE bit 7 in the ICHSTRP0 register in the SPI device must be 1. 170 Datasheet Functional Description 5.14.2.2.1 Advanced TCO Intel® Manageability Engine Mode In this mode, Intel ME SMBus Controller 1, Host SMBus and SMLink are connected together internally. See Figure 5-7. This mode is enabled when the BMCMODE bit 15 in the ICHSTRP0 register in the SPI device is 0. The Intel ME SMBus Controller 2 can be connected to either the SMBus pins or the SMLink pins by the MESM2SEL bit 23 in the ICHSTRP0 register in the SPI device. The default is to have the Intel ME SMBus Controller 2 connected to SMLink. The Intel ME SMBus Controller 2 has no connection to LINKALERT#. Figure 5-7. Advanced TCO Intel® ME SMBus/SMLink Configuration Intel® ICH10 Intel® ME AMT SMBus SMBus Controller 2 Controller 2 Intel® ME AMT SMBus SMBus Controller 1 Controller 1 Advanced TCO AMT Mode Embedded Controller SMLink SPD (Slave) uCtrl Host SMBus SMBus Legacy Sensors (Master or Slave with ALERT) ASF Sensors (Master or Slave) TCO Slave Datasheet 171 Functional Description 5.14.2.2.2 Advanced TCO BMC Mode In this mode, the external microcontroller (BMC) is connected to both SMLink and SMBus. The BMC communicates with Intel Management Engine through Intel ME SMBus connected to SMLink. The host and TCO slave communicated with BMC through SMBus. See Figure 5-8. This mode is enabled when the BMCMODE bit 15 in the ICHSTRP0 register in the SPI device is 1. Figure 5-8. Advanced TCO BMC Mode SMBus/SMLink Configuration Intel® ICH10 Intel® ME SMBus Controller 2 Intel® ME SMBus Controller 1 SMLink Advanced TCO BMC Mode BMC SPD (Slave) Host SMBus SMBus Legacy Sensors (Master or Slave with ALERT) ASF Sensors (Master or Slave) TCO Slave 172 Datasheet Functional Description 5.15 General Purpose I/O (D31:F0) The ICH10 contains up to 61 General Purpose Input/Output (GPIO) signals. Each GPIO can be configured as an input or output signal. The number of inputs and outputs varies depending on ICH10 configuration. 5.15.1 Power Wells Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some ICH10 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event results in the ICH10 driving a pin to a logic 1 to another device that is powered down. 5.15.2 SMI# and SCI Routing The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither. Note that a bit can be routed to either an SMI# or an SCI, but not both. 5.15.3 Triggering GPIO[1:15] have “sticky” bits on the input. Refer to the GPE0_STS register. As long as the signal goes active for at least 2 clock cycles, the ICH10 keeps the sticky status bit active. The active level can be selected in the GP_LVL register. If the system is in an S0 or an S1 state, the GPI inputs are sampled at 33 MHz, so the signal only needs to be active for about 60 ns to be latched. In the S3–S5 states, the GPI inputs are sampled at 32.768 kHz, and thus must be active for at least 61 microseconds to be latched. If the input signal is still active when the latch is cleared, it will again be set. Another edge trigger is not required. This makes these signals “level” triggered inputs. 5.15.4 GPIO Registers Lockdown The following GPIO registers are locked down when the GPIO Lockdown Enable (GLE) bit is set. The GLE bit resides in D31:F0:GPIO Control (GC) register. • Offset 00h: GPIO_USE_SEL • Offset 04h: GP_IO_SEL • Offset 0Ch: GP_LVL • Offset 30h: GPIO_USE_SEL2 • Offset 34h: GPI_IO_SEL2 • Offset 38h: GP_LVL2 • Offset 40h: GPIO_USE_SEL3 (Corporate Only) • Offset 44h: GPI_IO_SEL3 (Corporate Only) • Offset 48h: GP_LVL3 (Corporate Only) • Offset 60h: GP_RST_SEL Once these registers are locked down, they become Read-Only registers and any software writes to these registers will have no effect. To unlock the registers, the GPIO Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes from a ‘1’ to a ‘0’ a System Management Interrupt (SMI#) is generated if enabled. Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs. Datasheet 173 Functional Description This ensures that only BIOS can change the GPIO configuration. If the GLE bit is cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is triggered and these registers will continue to be locked down. 5.15.5 Serial POST Codes Over GPIO ICH10 adds the extended capability allowing system software to serialize POST or other messages on GPIO. This capability negates the requirement for dedicated diagnostic LEDs on the platform. Additionally, based on the newer BTX form factors, the PCI bus as a target for POST codes is increasingly difficult to support as the total number of PCI devices supported are decreasing. 5.15.5.1 Theory of operation For the ICH10 generation POST code serialization logic will be shared with GPIO. These GPIOs will likely be shared with LED control offered by the Super I/O (SIO) component. The following reference diagram shows a likely configuration. Figure 5-9. Serial Post over GPIO Reference Circuit V_3P3_STBY R ICH LED SIO Note: The pull-up value is based on the brightness required. The anticipated usage model is that either the ICH10 or the SIO can drive a pin low to turn off an LED. In the case of the power LED, the SIO would normally leave its corresponding pin in a high-Z state to allow the LED to turn on. In this state, the ICH10 can blink the LED by driving its corresponding pin low and subsequently tri-stating the buffer. An external optical sensing device can detect the on/off state of the LED. By externally post-processing the information from the optical device, the serial bit stream can be recovered. The hardware will supply a ‘sync’ byte before the actual data transmission to allow external detection of the transmit frequency. The frequency of transmission should be limited to 1 transition every 1μs to ensure the detector can reliably sample the on/off state of the LED. To allow flexibility in pull-up resistor values for power optimization, the frequency of the transmission is programmable via the DRS field in the GP_SB_CMDSTS register (Section 13.10.6). The serial bit stream is Manchester encoded. This choice of transmission ensures that a transition will be seen on every clock. The 1 or 0 data is based on the transmission happening during the high or low phase of the clock. 174 Datasheet Functional Description A simplified hardware/software register interface provides control and status information to track the activity of this block. Software enabling the serial blink capability should implement an algorithm referenced below to send the serialized message on the enabled GPIO. 1. Read the Go/Busy status bit in the GP_SB_CMDSTS register and verify it is cleared. This will ensure that the GPIO is idled and a previously requested message is still not in progress. 2. Write the data to serialize into the GP_SB_DATA register (Section 13.10.7). 3. Write the DLS and DRS values into the GP_SB_CMDSTS register and set the Go bit. This may be accomplished using a single write. The reference diagram shows the LEDs being powered from the suspend supply. By providing a generic capability that can be used both in the main and the suspend power planes maximum flexibility can be achieved. A key point to make is that the ICH will not unintentionally drive the LED control pin low unless a serialization is in progress. System board connections utilizing this serialization capability are required to use the same power plane controlling the LED as the ICH10 GPIO pin. Otherwise, the ICH10 GPIO may float low during the message and prevent the LED from being controlled from the SIO. The hardware will only be serializing messages when the core power well is powered and the processor is operational. Care should be taken to prevent the ICH10 from driving an active ‘1’ on a pin sharing the serial LED capability. Since the SIO could be driving the line to 0, having the ICH drive a 1 would create a high current path. A recommendation to avoid this condition involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register (Section 13.10.7) should be set first before changing the direction of the pin to an output. This sequence ensures the open-drain capability of the buffer is properly configured before enabling the pin as an output. 5.15.5.2 Serial Message Format In order to serialize the data onto the GPIO, an initial state of high-Z is assumed. The SIO is required to have its LED control pin in a high-Z state as well to allow ICH10 to blink the LED (refer to the reference diagram). The three components of the serial message include the sync, data, and idle fields. The sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the high-Z state (LED on) provides external hardware a known initial condition and a known pattern. In case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling logic to the encoded clock. The data field is shifted out with the highest byte first (MSB). Within each byte, the most significant bit is shifted first (MSb). The idle field is enforced by the hardware and is at least 2 bit times long. The hardware will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in hardware prevents time-based counting in BIOS as the hardware is immediately ready for the next serial code when the Go bit is cleared. Note that the idle state is represented as a high-Z condition on the pin. If the last transmitted bit is a 1, returning to the idle state will result in a final 0-1 transition on the output Manchester data. Two full bit times of idle correspond to a count of 4 time intervals (the width of the time interval is controlled by the DRS field). Datasheet 175 Functional Description The following waveform shows a 1-byte serial write with a data byte of 5Ah. The internal clock and bit position are for reference purposes only. The Manchester D is the resultant data generated and serialized onto the GPIO. Since the buffer is operating in open-drain mode the transitions are from high-Z to 0 and back. Bit Internal Clock Manchester D 76543210 8-bit sync field (1111_1110) 5A data byte 2 clk idle 5.15.6 Intel Management Engine GPIOs The following GPIOs can be used as Controller Link GPIOs: GPIO9/WOL_EN, GPIO10/ CPU_MISSING/JTAGTMS (Corporate Only), GPIO24/MEM_LED, and GPIO57/TPM_PP/ JTAGTCK (Corporate Only). Controller Link GPIOs are only available on Intel AMT or ASF enabled platforms with supporting Intel Management Engine firmware. Controller Link GPIOs are owned by the Intel Management Engine and are configured by Intel Management Engine firmware. When configured a a Controller Link GPIO the GPIO_USE_SEL bit is ignored. If the Controller Link GPIO is utilized in a platform, its associated GPIO functionality is no longer available to the host. If the Controller Link GPIO is not utilized in a platform, the signal can instead be used as its associated General Purpose I/O. 5.16 SATA Host Controller (D31:F2, F5) The SATA function in the ICH10 has three modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the ICH10 utilizes two controllers to enable all six ports of the bus. The first controller (Device 31: Function 2) supports ports 0–3 and the second controller (Device 31: Function 5) supports ports 4 and 5. When using a legacy operating system, only one controller (Device 31: Function 2) is available that supports ports 0 - 3. In AHCI or RAID mode, only one controller (Device 31: Function 2) is used enabling all six ports. The MAP register, Section 15.1.29, provides the ability to share PCI functions. When sharing is enabled, all decode of I/O is done through the SATA registers. Device 31, Function 1 (IDE controller) is hidden by software writing to the Function Disable Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used. The ICH10 SATA controllers feature six sets of interface signals (ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). Each interface is supported by an independent DMA controller. The ICH10 SATA controllers interact with an attached mass storage device through a register interface that is equivalent to that presented by a traditional IDE host adapter. The host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by the SATA device or the system BIOS. 176 Datasheet Functional Description 5.16.1 SATA Feature Support ICH10 (AHCI/RAID Disabled) N/A N/A N/A N/A Supported N/A N/A Supported N/A N/A ICH10 (AHCI/RAID Enabled) Supported Supported Supported Supported Supported Supported Supported Supported N/A Supported Feature Native Command Queuing (NCQ) Auto Activate for DMA Hot Plug Support Asynchronous Signal Recovery 3 Gb/s Transfer Rate ATAPI Asynchronous Notification Host & Link Initiated Power Management Staggered Spin-Up Command Completion Coalescing External SATA Feature Native Command Queuing (NCQ) Auto Activate for DMA Description Allows the device to reorder commands for more efficient data transfers Collapses a DMA Setup then DMA Activate sequence into a DMA Setup only Allows for device detection without power being applied and ability to connect and disconnect devices without prior notification to the system Provides a recovery from a loss of signal or establishing communication after hot plug Capable of data transfers up to 3Gb/s A mechanism for a device to send a notification to the host that the device requires attention Capability for the host controller or device to request Partial and Slumber interface power states Enables the host the ability to spin up hard drives sequentially to prevent power load problems on boot Reduces interrupt and completion overhead by allowing a specified number of commands to complete and then generating an interrupt to process the commands Technology that allows for an outside the box connection of up to 2 meters (when using the cable defined in SATA-IO) Hot Plug Support Asynchronous Signal Recovery 3 Gb/s Transfer Rate ATAPI Asynchronous Notification Host & Link Initiated Power Management Staggered Spin-Up Command Completion Coalescing External SATA Datasheet 177 Functional Description 5.16.2 5.16.2.1 Theory of Operation Standard ATA Emulation The ICH10 contains a set of registers that shadow the contents of the legacy IDE registers. The behavior of the Command and Control Block registers, PIO, and DMA data transfers, resets, and interrupts are all emulated. Note: The ICH10 will assert INTR when the master device completes the EDD command regardless of the command completion status of the slave device. If the master completes EDD first, an INTR is generated and BSY will remain '1' until the slave completes the command. If the slave completes EDD first, BSY will be '0' when the master completes the EDD command and asserts INTR. Software must wait for busy to clear (0) before completing an EDD command, as required by the ATA5 through ATA7 (T13) industry standards. 5.16.2.2 48-Bit LBA Operation The SATA host controller supports 48-bit LBA through the host-to-device register FIS when accesses are performed via writes to the task file. The SATA host controller will ensure that the correct data is put into the correct byte of the host-to-device FIS. There are special considerations when reading from the task file to support 48-bit LBA operation. Software may need to read all 16-bits. Since the registers are only 8-bits wide and act as a FIFO, a bit must be set in the device/control register, which is at offset 3F6h for primary and 376h for secondary (or their native counterparts). If software clears bit 7 of the control register before performing a read, the last item written will be returned from the FIFO. If software sets bit 7 of the control register before performing a read, the first item written will be returned from the FIFO. 5.16.3 SATA Swap Bay Support The ICH10 provides for basic SATA swap bay support using the PSC register configuration bits and power management flows. A device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. Note: This SATA swap bay operation requires board hardware (implementation specific), BIOS, and operating system support. 5.16.4 Hot Plug Operation ICH10 supports Hot Plug Surprise removal and Insertion Notification in the PARTIAL, SLUMBER and Listen Mode states when used with Low Power Device Presence Detection. Software can take advantage of power savings in the low power states while enabling hot plug operation. Refer to chapter 7 of the AHCI specification for details. 5.16.4.1 Low Power Device Presence Detection Low Power Device Presence Detection enables SATA Link Power Management to coexist with hot plug (insertion and removal) without interlock switch or cold presence detect. The detection mechanism allows Hot Plug events to be detectable by hardware across all link power states (Active, PARTIAL, SLUMBER) as well as AHCI Listen Mode. If the Low Power Device Presence Detection circuit is disabled the ICH10 reverts to Hot Plug Surprise Removal Notification (without an interlock switch) mode that is mutually exclusive of the PARTIAL and SLUMBER power management states. 178 Datasheet Functional Description 5.16.5 Function Level Reset Support (FLR) The SATA Host Controller supports the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an Operating System in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the Operating System to reset the whole device as if a PCI reset was asserted. 5.16.5.1 5.16.5.1.1 FLR Steps FLR Initialization 1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit. 2. All subsequent requests targeting the Function will not be claimed and will be Master Abort Immediate on the bus. This includes any configuration, I/O or Memory cycles, however, the Function shall continue to accept completions targeting the Function. 5.16.5.1.2 FLR Operation The Function will Reset all configuration, I/O and memory registers of the Function except those indicated otherwise and reset all internal states of the Function to the default or initial condition. 5.16.5.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: From the time Initiate FLR bit is written to '1' software must wait at least 100 ms before accessing the function. Datasheet 179 Functional Description 5.16.6 Intel® Matrix Storage Technology Configuration The Intel® Matrix Storage Technology offers several diverse options for RAID (redundant array of independent disks) to meet the needs of the end user. AHCI support provides higher performance and alleviates disk bottlenecks by taking advantage of the independent DMA engines that each SATA port offers in ICH10. • RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for data intensive applications such as video editing. • Data security is offered through RAID Level 1, which performs mirroring. • RAID Level 10 provides high levels of storage performance with data protection, combining the fault-tolerance of RAID Level 1 with the performance of RAID Level 0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems that require both performance and fault-tolerance. RAID Level 10 requires 4 hard drives, and provides the capacity of two drives. • RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on 3 or more drives. By striping parity, and rotating it across all disks, fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity. That is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write rate. RAID 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance. By using the ICH10’s built-in Intel Matrix Storage Technology, there is no loss of PCI resources (request/grant pair) or add-in card slot. Intel Matrix Storage Technology functionality requires the following items: 1. ICH10 component enabled for Intel Matrix Storage Technology (see Section 1.3) 2. Intel Matrix Storage Manager RAID Option ROM must be on the platform 3. Intel Matrix Storage Manager drivers, most recent revision. 4. At least two SATA hard disk drives (minimum depends on RAID configuration). Intel Matrix Storage Technology is not available in the following configurations: 1. The SATA controller is in compatible mode. 5.16.6.1 Intel® Matrix Storage Manager RAID Option ROM The Intel Matrix Storage Manager RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions: • Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows the user to create & delete RAID volumes and select recovery options when problems occur. • Provides boot support when using a RAID volume as a boot disk. It does this by providing Int13 services when a RAID volume needs to be accessed by DOS applications (such as NTLDR) and by exporting the RAID volumes to the System BIOS for selection in the boot order. • At each boot up, provides the user with a status of the RAID volumes and the option to enter the user interface by pressing CTRL-I. 180 Datasheet Functional Description 5.16.7 Power Management Operation Power management of the ICH10 SATA controller and ports will cover operations of the host controller and the SATA wire. 5.16.7.1 Power State Mappings The D0 PCI power management state for device is supported by the ICH10 SATA controller. SATA devices may also have multiple power states. From parallel ATA, three device states are supported through ACPI. They are: • D0 – Device is working and instantly available. • D1 – device enters when it receives a STANDBY IMMEDIATE command. Exit latency from this state is in seconds • D3 – from the SATA device’s perspective, no different than a D1 state, in that it is entered via the STANDBY IMMEDIATE command. However, an ACPI method is also called which will reset the device and then cut its power. Each of these device states are subsets of the host controller’s D0 state. Finally, SATA defines three PHY layer power states, which have no equivalent mappings to parallel ATA. They are: • PHY READY – PHY logic and PLL are both on and active • Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer than 10 ns • Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to 10 ms. Since these states have much lower exit latency than the ACPI D1 and D3 states, the SATA controller defines these states as sub-states of the device D0 state. Figure 5-10. SATA Power States Power Intel® ICH SATA Controller = D0 Device = D0 PHY = Ready PHY = Partial PHY = Slumber PHY = Off (port disabled) Device = D1 PHY = Slumber PHY = Off (port disabled) Device = D3 PHY = Slumber PHY = Off (port disabled) Resume Latency Datasheet 181 Functional Description 5.16.7.2 5.16.7.2.1 Power State Transitions Partial and Slumber State Entry/Exit The partial and slumber states save interface power when the interface is idle. The SATA controller defines PHY layer power management (as performed via primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. The SATA controller accepts device transition types, but does not issue any transitions as a host. All received requests from a SATA device will be ACKed. When an operation is performed to the SATA controller such that it needs to use the SATA cable, the controller must check whether the link is in the Partial or Slumber states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the SATA device must perform the same action. 5.16.7.2.2 Device D1, D3 States These states are entered after some period of time when software has determined that no commands will be sent to this device for some time. The mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. The command most likely to be used in ATA/ATAPI is the “STANDBY IMMEDIATE” command. 5.16.7.2.3 Host Controller D3HOT State After the interface and device have been put into a low power state, the SATA host controller may be put into a low power state. This is performed via the PCI power management registers in configuration space. There are two very important aspects to note when using PCI power management. 1. When the power state is D3, only accesses to configuration space are allowed. Any attempt to access the memory or I/O spaces will result in master abort. 2. When the power state is D3, no interrupts may be generated, even if they are enabled. If an interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated. When the controller is put into D3, it is assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will be treated as if no device is present on the cable, and power will be minimized. When returning from a D3 state, an internal reset will not be performed. 5.16.7.2.4 Non-AHCI Mode PME# Generation When in non-AHCI mode (legacy mode) of operation, the SATA controller does not generate PME#. This includes attach events (since the port must be disabled), or interlock switch events (via the SATAGP pins). 5.16.7.3 SMI Trapping (APM) Device 31:Function2:Offset C0h (see Section 14.1.37) contain control for generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0– 1F7h, 3F6h, 170–177h, and 376h) and native IDE ranges defined by PCMDBA, PCTLBA, SCMDBA an SCTLBA. If the SATA controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated. If an access to the Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Section 14.1.38) are updated indicating that a trap occurred. 182 Datasheet Functional Description 5.16.8 SATA Device Presence In legacy mode, the SATA controller does not generate interrupts based on hot plug/ unplug events. However, the SATA PHY does know when a device is connected (if not in a partial or slumber state), and it s beneficial to communicate this information to host software as this will greatly reduce boot times and resume times. The flow used to indicate SATA device presence is shown in Figure 5-11. The ‘PxE’ bit refers to PCS.P[3:0]E bits, depending on the port being checked and the ‘PxP’ bits refer to the PCS.P[3:0]P bits, depending on the port being checked. If the PCS/PxP bit is set a device is present, if the bit is cleared a device is not present. If a port is disabled, software can check to see if a new device is connected by periodically reenabling the port and observing if a device is present, if a device is not present it can disable the port and check again later. If a port remains enabled, software can periodically poll PCS.PxP to see if a new device is connected. Figure 5-11. Flow for Port Enable / Device Present Bits Datasheet 183 Functional Description 5.16.9 SATA LED The SATALED# output is driven whenever the BSY bit is set in any SATA port. The SATALED# is an active-low open-drain output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive. 5.16.10 AHCI Operation The ICH10 provides hardware support for Advanced Host Controller Interface (AHCI), a programming interface for SATA host controllers developed through a joint industry effort. AHCI defines transactions between the SATA controller and software and enables advanced performance and usability with SATA. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. The ICH10 supports all of the mandatory features of the Serial ATA Advanced Host Controller Interface Specification, Revision 1.2 and many optional features, such as hardware assisted native command queuing, aggressive power management, LED indicator support, and Hot-Plug through the use of interlock switch support (additional platform hardware and software may be required depending upon the implementation). Note: For reliable device removal notification while in AHCI operation without the use of interlock switches (surprise removal), interface power management should be disabled for the associated port. See Section 7.3.1 of the AHCI Specification for more information. 5.16.11 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) The 100 MHz Serial ATA Reference Clock (SATACLKP, SATACLKN) is implemented on the system as a ground-terminated low-voltage differential signal pair driven by the system Clock Chip. When all the SATA links are in Slumber or disabled, the SATA Reference Clock is not needed and may be stopped and tri-stated at the clock chip allowing system-level power reductions. The ICH10 uses the SATACLKREQ# output signal to communicate with the system Clock Chip to request either SATA clock running or to tell the system clock chip that it can stop the SATA Reference Clock. ICH10 drives this signal low to request clock running, and tristates the signal to indicate that the SATA Reference Clock may be stopped (the ICH10 never drives the pin high). When the SATACLKREQ# is tristated by the ICH10, the clock chip may stop the SATA Reference Clock within 100 ns, anytime after 100 ns, or not at all. If the SATA Reference Clock is not already running, it will start within 100 ns after a SATACLKREQ# is driven low by the ICH10. To enable SATA Reference Clock Low Power Request: 1. Configure GPIO35 to native function 2. Set SATA Clock Request Enable (SCRE) bit to ‘1’ (Dev 31:F2:Offset 94h:bit 28). Note: The reset default for SATACLKREQ# is low to insure that the SATA Reference Clock is running after system reset. 184 Datasheet Functional Description 5.16.12 SGPIO Signals The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED signaling. These signals are not related to SATALED#, which allows for simplified indication of SATA command activity. The SGPIO group interfaces with an external controller chip that fetches and serializes the data for driving across the SGPIO bus. The output signals then control the LEDs. This feature is only valid in AHCI/RAID mode. 5.16.12.1 Mechanism The enclosure management for SATA Controller 1 (Device 31: Function 2) involves sending messages that control LEDs in the enclosure. The messages for this function are stored after the normal registers in the AHCI BAR, at Offset 400h bytes for ICH10 from the beginning of the AHCI BAR as specified by the EM_LOC global register (Section 14.4.1.8). Software creates messages for transmission in the enclosure management message buffer. The data in the message buffer should not be changed if CTL.TM bit is set by software to transmit an update message. Software should only update the message buffer when CTL.TM bit is cleared by hardware otherwise the message transmitted will be indeterminate. Software then writes a register to cause hardware to transmit the message or take appropriate action based on the message content. The software should only create message types supported by the controller, which is LED messages for ICH10. If the software creates other non LED message types (e.g. SAF-TE, SES-2), the SGPIO interface may hang and the result is indeterminate. During reset all SGPIO pins will be in tri-state state. The interface will continue to be in tri-state state after reset until the first transmission occurs when software programs the message buffer and sets the transmit bit CTL.TM. The SATA Host controller will initiate the transmission by driving SCLOCK and at the same time drive the SLOAD to ‘0’ prior to the actual bit stream transmission. The Host will drive SLOAD low for at least 5 SCLOCK then only start the bit stream by driving the SLOAD to high. SLOAD will be driven high for 1 SCLOCK follow by vendor specific pattern that is default to “0000” if software has yet to program the value. A total of 18-bit stream from 6 ports (Port0, Port1, Port2, Port3, Port4 and Port5) of 3-bit per port LED message will be transmitted on SDATAOUT0 pin after the SLOAD is driven high for 1 SCLOCK. Only 2 ports (port4 and port5) of 6 bit total LED message follow by 12 bits of tri-state value will be transmitted out on SDATAOUT1 pin. All the default LED message values will be high prior to software setting them, except the Activity LED message that is configured to be hardware driven that will be generated based on the activity from the respective port. All the LED message values will be driven to ‘1’ for the port that is unimplemented as indicated in the Port Implemented register regardless of the software programmed value through the message buffer. There are 2 different ways of resetting ICH SGPIO interface, asynchronous reset and synchronous reset. Asynchronous reset is caused by platform reset to cause the SGPIO interface to be tri-state asynchronously. Synchronous reset is caused by setting the CTL.RESET bit, clearing the GHC.AE bit or HBA reset, where Host Controller will complete the existing full bit stream transmission then only tri-state all the SGPIO pins. After the reset, both synchronous and asynchronous, the SGPIO pins will stay tristated. Note: ICH Host Controller does not ensure to cause the target SGPIO device or controller to be reset. Software is responsible to keep ICH SGPIO interface in tri-state stated for 2 second in order to cause a reset on the target of the SGPIO interface. Datasheet 185 Functional Description 5.16.12.2 Message Format Messages shall be constructed with a one Dword header that describes the message to be sent followed by the actual message contents. The first Dword shall be constructed as follows: Bit 31:28 Reserved Message Type (MTYPE): Specifies the type of the message. The message types are: 0h = LED 27:24 1h = SAF-TE 2h = SES-2 3h = SGPIO (register based interface) All other values reserved Data Size (DSIZE): Specifies the data size in bytes. If the message (enclosure services command) has a data buffer that is associated with it that is transferred, the size of that data buffer is specified in this field. If there is no separate data buffer, this field shall have a value of ‘0’. The data directly follows the message in the message buffer. For ICH10, this value should always be ‘0’. Message Size (MSIZE): Specifies the size of the message in bytes. The message size does not include the one Dword header. A value of ‘0’ is invalid. For ICH10, the message size is always 4 bytes. Reserved Description 23:16 15:8 7:0 The SAF-TE, SES-2, and SGPIO message formats are defined in the corresponding specifications, respectively. The LED message type is defined in Section 5.16.12.3. It is the responsibility of software to ensure the content of the message format is correct. If the message type is not programmed as 'LED' for this controller, the controller shall not take any action to update its LEDs. Note that for LED message type, the message size is always consisted of 4 bytes. 5.16.12.3 LED Message Type The LED message type specifies the status of up to three LEDs. Typically, the usage for these LEDs is activity, fault, and locate. Not all implementations necessarily contain all LEDs (for example, some implementations may not have a locate LED). The message identifies the HBA port number that the slot status applies to. The format of the LED message type is defined in Table 5-42. The LEDs shall retain their values until there is a following update for that particular slot. 186 Datasheet Functional Description Table 5-42. Multi-activity LED message type Byte Description Value (VAL): This field describes the state of each LED for a particular location. There are three LEDs that may be supported by the HBA. Each LED has 3 bits of control. LED values are: 000b - LED shall be off 001b - LED shall be solid on as perceived by human eye All other values reserved The LED bit locations are: Bits 2:0 - Activity LED (may be driven by hardware) Bits 5:3 - Vendor Specific LED (e.g. locate) 3-2 Bits 8:6 - Vendor Specific LED (e.g. fault) Bits 15:9 - Reserved Vendor specific message is: Bit 3:0 - Vendor Specific Pattern Bit 15:4 - Reserved Note: If Activity LED Hardware Driven (ATTR.ALHD) bit is set, host will output the hardware LED value sampled internally and will ignore software written activity value on bit [2:0]. Since ICH10 Enclosure Management does not support port multiplier based LED message, the LED message will be generated independently based on respective port’s operation activity. Vendor specific LED values Locate (Bits 5:3) and Fault (Bits 8:6) always are driven by software. Port Multiplier Information: Specifies slot specific information related to Port Multiplier. 1 Bits 3:0 specify the Port Multiplier port number for the slot that requires the status update. If a Port Multiplier is not attached to the device in the affected slot, the Port Multiplier port number shall be '0'. Bits 7:4 are reserved. ICH10 does not support LED messages for devices behind a Port Multiplier. This byte should be 0. HBA Information: Specifies slot specific information related to the HBA. Bits 4:0 - HBA port number for the slot that requires the status update. 0 Bit 5 - If set to '1', Value is a vendor specific message that applies to the entire enclosure. If cleared to '0', Value applies to the port specified in bits 4:0. Bits 7:6 - Reserved Datasheet 187 Functional Description 5.16.12.4 SGPIO Waveform Figure 5-12. Serial Data transmitted over the SGPIO Interface 188 Datasheet Functional Description 5.16.13 External SATA ICH10 supports external SATA. External SATA utilizes the SATA interface outside of the system box. The usage model for this feature must comply with the Serial ATA II Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates two configurations: 1. The cable-up solution involves an internal SATA cable that connects to the SATA motherboard connector and spans to a back panel PCI bracket with an e-SATA connector. A separate e-SATA cable is required to connect an e-SATA device. 2. The back-panel solution involves running a trace to the I/O back panel and connecting a device via an external SATA connector on the board. 5.17 High Precision Event Timers This function provides a set of timers that can be used by the operating system. The timers are defined such that in the future, the operating system may be able to assign specific timers to used directly by specific applications. Each timer can be configured to cause a separate interrupt. ICH10 provides eight (Corporate Family) or four (Consumer Family) timers. The timers are implemented as a single counter each with its own comparator and value register. This counter increases monotonically. Each individual timer can generate an interrupt when the value in its value register matches the value in the main counter. The registers associated with these timers are mapped to a memory space (much like the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS reports to the operating system the location of the register space. The hardware can support an assignable decode space; however, the BIOS sets this space prior to handing it over to the operating system (See Section 9.4). It is not expected that the operating system will move the location of these timers once it is set by the BIOS. 5.17.1 Timer Accuracy 1. The timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. 2. Within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. Each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. The timer is monotonic. It does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. The accuracy of the main counter is as accurate as the 14.31818 MHz clock. Datasheet 189 Functional Description 5.17.2 Interrupt Mapping Mapping Option #1 (Legacy Replacement Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the mapping found in Table 5-43. Table 5-43. Legacy Replacement Routing Timer 0 1 2&3 4, 5, 6, 7 (Corporate Only) 8259 Mapping IRQ0 IRQ8 Per IRQ Routing Field. not available APIC Mapping IRQ2 IRQ8 Per IRQ Routing Field not available Comment In this case, the 8254 timer will not cause any interrupts In this case, the RTC will not cause any interrupts. NOTE: (Corporate Only) The Legacy Option does not preclude delivery of IRQ0/IRQ8 via direct FSB interrupt messages. Mapping Option #2 (Standard Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its own routing control. The interrupts can be routed to various interrupts in the 8259 or I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a timer is set for edge-triggered mode, the timers should not be share with any PCI interrupts. For the Intel ICH10, the only supported interrupt values are as follows: Timer 0 and 1: IRQ20, 21, 22 & 23 (I/O APIC only). Timer 2: IRQ11 (8259 or I/O APIC) and IRQ20, 21, 22, and 23 (I/O APIC only). Timer 3: IRQ12 (8259 or I/O APIC) and IRQ 20, 21, 22, and 23 (I/O APIC only). Interrupts from Timer 4, 5, 6, 7 (Corporate Only) can only be delivered via direct FSB interrupt messages. 5.17.3 Periodic vs. Non-Periodic Modes Non-Periodic Mode Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1, 2 and 3 only support 32-bit mode (See Section 21.1.5). All of the timers support non-periodic mode. Consult Section 2.3.9.2.1 of the IA-PC HPET Specification for a description of this mode. Periodic Mode Timer 0 is the only timer that supports periodic mode. Consult Section 2.3.9.2.2 of the IA-PC HPET Specification for a description of this mode. 190 Datasheet Functional Description The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts 2. Software Clears the main counter by writing a value of 00h to it. 3. Software sets the TIMER0_VAL_SET_CNF bit. 4. Software writes the new value in the TIMER0_COMPARATOR_VAL register 5. Software sets the ENABLE_CNF bit to enable interrupts. The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. Set TIMER0_VAL_SET_CNF bit 2. Set the lower 32 bits of the Timer0 Comparator Value register 3. Set TIMER0_VAL_SET_CNF bit 4. Set the upper 32 bits of the Timer0 Comparator Value register 5.17.4 Enabling the Timers The BIOS or operating system PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge or level type for each timer) The Device Driver code should do the following for an available timer: 1. Set the Overall Enable bit (Offset 10h, bit 0). 2. Set the timer type field (selects one-shot or periodic). 3. Set the interrupt enable 4. Set the comparator value 5.17.5 Interrupt Levels Interrupts directed to the internal 8259s are active high. See Section 5.9 for information regarding the polarity programming of the I/O APIC for detecting internal interrupts. If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode, they can be shared with PCI interrupts. They may be shared although it’s unlikely for the operating system to attempt to do this. If more than one timer is configured to share the same IRQ (using the TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to leveltriggered mode. Edge-triggered interrupts cannot be shared. Datasheet 191 Functional Description 5.17.6 Handling Interrupts If each timer has a unique interrupt and the timer has been configured for edgetriggered mode, then there are no specific steps required. No read is required to process the interrupt. If a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software. This is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. Independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. If Timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register. 5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions. However, a 32-bit processor may not be able to directly read 64-bit timer. A race condition comes up if a 32-bit processor reads the 64-bit register using two separate 32-bit reads. The danger is that just after reading one half, the other half rolls over and changes the first half. If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper 32-bits are always 0. Alternatively, software may do a multiple read of the counter while it is running. Software can read the high 32 bits, then the low 32 bits, the high 32 bits again. If the high 32 bits have not changed between the two reads, then a rollover has not happened and the low 32 bits are valid. If the high 32 bits have changed between reads, then the multiple reads are repeated until a valid read is performed. Note: On a 64-bit platform, if software attempts a 64 bit read of the 64-bit counter, software must be aware that some platforms may split the 64 bit read into two 32 bit reads. The read maybe inaccurate if the low 32 bits roll over between the high and low reads. 5.18 USB UHCI Host Controllers (D29:F0, F1, F2, F3 and D26:F0, F1 and F2) The ICH10 contains six USB full/low-speed host controllers that support the standard Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller (UHC) includes a root hub with two separate USB ports each, for a total of twelve USB ports. • Overcurrent detection on all twelve USB ports is supported. The overcurrent inputs are not 5 V tolerant, and can be used as GPIs if not needed. • The ICH10’s UHCI host controllers are arbitrated differently than standard PCI devices to improve arbitration latency. • The UHCI controllers use the Analog Front End (AFE) embedded cell that allows support for USB full-speed signaling rates, instead of USB I/O buffers. Note: D26:F2 can be configured as D29:F3 during BIOS Post. 192 Datasheet Functional Description 5.18.1 Data Structures in Main Memory Section 3.1 - 3.3 of the Universal Host Controller Interface Specification, Revision 1.1 details the data structures used to communicate control, status, and data between software and the ICH10. 5.18.2 Data Transfers to/from Main Memory Section 3.4 of the Universal Host Controller Interface Specification, Revision 1.1 describes the details on how HCD and the ICH10 communicate via the Schedule data structures. 5.18.3 Data Encoding and Bit Stuffing The ICH10 USB employs NRZI data encoding (Non-Return to Zero Inverted) when transmitting packets. Full details on this implementation are given in the Universal Serial Bus Specification, Revision 2.0. 5.18.4 5.18.4.1 Bus Protocol Bit Ordering Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb, through to the most significant bit (MSb) last. 5.18.4.2 SYNC Field All packets begin with a synchronization (SYNC) field, which is a coded sequence that generates a maximum edge transition density. The SYNC field appears on the bus as IDLE followed by the binary string “KJKJKJKK,” in its NRZI encoding. It is used by the input circuitry to align incoming data with the local clock and is defined to be 8 bits in length. SYNC serves only as a synchronization mechanism. The last two bits in the SYNC field are a marker that is used to identify the first bit of the PID. All subsequent bits in the packet must be indexed from this point. 5.18.4.3 Packet Field Formats All packets have distinct start and end of packet delimiters. Full details are given in the Universal Serial Bus Specification, Revision 2.0, in Section 8.3.1. 5.18.4.4 Address Fields Function endpoints are addressed using the function address field and the endpoint field. Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in Section 8.3.2. 5.18.4.5 Frame Number Field The frame number field is an 11-bit field that is incremented by the host on a per frame basis. The frame number field rolls over upon reaching its maximum value of 7FFh, and is sent only for SOF tokens at the start of each frame. 5.18.4.6 Data Field The data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. Data bits within each byte are shifted out LSB first. Datasheet 193 Functional Description 5.18.4.7 Cyclic Redundancy Check (CRC) CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields are considered to be protected fields. Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in Section 8.3.5. 5.18.5 Packet Formats The USB protocol calls out several packet types: token, data, and handshake packets. Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in Section 8.4. 5.18.6 USB Interrupts There are two general groups of USB interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from an ICH10 operation error. All transaction-based sources can be masked by software through the ICH10’s Interrupt Enable register. Additionally, individual transfer descriptors can be marked to generate an interrupt on completion. When the ICH10 drives an interrupt for USB, it internally drives the PIRQA# pin for USB function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC# pin for USB function #2, until all sources of the interrupt are cleared. In order to accommodate some operating systems, the Interrupt Pin register must contain a different value for each function of this new multi-function device. 5.18.6.1 Transaction-Based Interrupts These interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. This ensures that software can safely process through (Frame List Current Index -1) when it is servicing an interrupt. CRC Error / Time-Out A CRC/Time-Out error occurs when a packet transmitted from the ICH10 to a USB device or a packet transmitted from a USB device to the ICH10 generates a CRC error. The ICH10 is informed of this event by a time-out from the USB device or by the ICH10’s CRC checker generating an error on reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not respond to a transaction phase within 19-bit times of an EOP. Either of these conditions causes the C_ERR field of the TD to decrement. When the C_ERR field decrements to 0, the following occurs: • The Active bit in the TD is cleared • The Stalled bit in the TD is set • The CRC/Time-out bit in the TD is set. • At the end of the frame, the USB Error Interrupt bit is set in the HC status register. If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware interrupt will be signaled to the system. 194 Datasheet Functional Description Interrupt on Completion Transfer Descriptors contain a bit that can be set to cause an interrupt on their completion. The completion of the transaction associated with that block causes the USB Interrupt bit in the HC Status Register to be set at the end of the frame in which the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit in the HC Status register is set to 1 at the end of the frame if the active bit in the TD is set to 0 (even if it was set to 0 when initially read). If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status register is set either when the TD completes successfully or because of errors. If the completion is because of errors, the USB Error bit in the HC status register is also set. Short Packet Detect A transfer set is a collection of data which requires more than one USB transaction to completely move the data across the USB. An example might be a large print file which requires numerous TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion of the transfer set, even if there are active TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to set the USB Interrupt bit in the HC status register at the end of the frame in which this event occurs. This feature streamlines the processing of input on these transfer types. If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred. Serial Bus Babble When a device transmits on the USB for a time greater than its assigned Max Length, it is said to be babbling. Since isochrony can be destroyed by a babbling device, this error results in the Active bit in the TD being cleared to 0 and the Stalled and Babble bits being set to 1. The C_ERR field is not decremented for a babble. The USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware interrupt is signaled to the system. If an EOF babble was caused by the ICH10 (due to incorrect schedule for instance), the ICH10 forces a bit stuff error followed by an EOP and the start of the next frame. Stalled This event indicates that a device/endpoint returned a STALL handshake during a transaction or that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is signaled to the system. Data Buffer Error This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. This would generally be caused by the ICH10 not being able to access required data buffers in memory within necessary latency requirements. Either of these conditions causes the C_ERR field of the TD to be decremented. When C_ERR decrements to 0, the Active bit in the TD is cleared, the Stalled bit is set, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. Datasheet 195 Functional Description Bit Stuff Error A bit stuff error results from the detection of a sequence of more that six 1s in a row within the incoming data stream. This causes the C_ERR field of the TD to be decremented. When the C_ERR field decrements to 0, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. 5.18.6.2 Non-Transaction Based Interrupts If an ICH10 process error or system error occurs, the ICH10 halts and immediately issues a hardware interrupt to the system. Resume Received This event indicates that the ICH10 received a RESUME signal from a device on the USB bus during a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware interrupt is signaled to the system allowing the USB to be brought out of the suspend state and returned to normal operation. ICH10 Process Error The HC monitors certain critical fields during operation to ensure that it does not process corrupted data structures. These include checking for a valid PID and verifying that the MaxLength field is less than 1280. If it detects a condition that would indicate that it is processing corrupted data structures, it immediately halts processing, sets the HC Process Error bit in the HC Status register and signals a hardware interrupt to the system. This interrupt cannot be disabled through the Interrupt Enable register. Host System Error The ICH10 sets this bit to 1 when a Parity error, Master Abort, or Target Abort occurs. When this error occurs, the ICH10 clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt Enable register. 196 Datasheet Functional Description 5.18.7 USB Power Management The Host controller can be put into a suspended state and its power can be removed. This requires that certain bits of information are retained in the suspend power plane of the ICH10 so that a device on a port may wake the system. Such a device may be a fax-modem, which will wake up the machine to receive a fax or take a voice message. The settings of the following bits in I/O space will be maintained when the ICH10 enters the S3, S4, or S5 states. Table 5-44. Bits Maintained in Low Power States Register Command Status Offset 00h 02h Bit 3 2 2 Port Status and Control 10h & 12h 6 8 12 Description Enter Global Suspend Mode (EGSM) Resume Detect Port Enabled/Disabled Resume Detect Low-speed Device Attached Suspend When the ICH10 detects a resume event on any of its ports, it sets the corresponding USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system wakes up and an SCI generated. 5.18.8 USB Legacy Keyboard Operation When a USB keyboard is plugged into the system, and a standard keyboard is not, the system may not boot, and MS-DOS legacy software will not run, because the keyboard will not be identified. The ICH10 implements a series of trapping operations which will snoop accesses that go to the keyboard controller, and put the expected data from the USB keyboard into the keyboard controller. Note: The scheme described below assumes that the keyboard controller (8042 or equivalent) is on the LPC bus. This legacy operation is performed through SMM space. Figure 5-13 shows the Enable and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the Status Register. Because the enable is after the latch, it is possible to check for other events that didn't necessarily cause an SMI. It is the software's responsibility to logically AND the value with the appropriate enable bits. Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY# goes active) to ensure that the processor doesn't complete the cycle before the SMI is observed. The logic also needs to block the accesses to the 8042. If there is an external 8042, then this is simply accomplished by not activating the 8042 CS. This is done by logically ANDing the four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to determine if 8042CS should go active. An additional term is required for the “passthrough” case. The state table for Figure 5-13 is shown in Table 5-45. Datasheet 197 Functional Description Figure 5-13. USB Legacy Keyboard Flow Diagram To Individual "Caused By" "Bits" S D PCI Config Read, Write Comb. Decoder Clear SMI_60_R R AND SMI Same for 60W, 64R, 64W OR EN_SMI_ON_60R KBC Accesses 60 READ EN_PIRQD# AND To PIRQD# To "Caused By" Bit USB_IRQ Clear USB_IRQ S R D AND EN_SMI_ON_IRQ Table 5-45. USB Legacy Keyboard State Transitions (Sheet 1 of 2) Current State IDLE Action 64h / Write 64h / Write Data Value D1h Next State GateState1 Comment Standard D1 command. Cycle passed through to 8042. SMI# doesn't go active. PSTATE (offset C0, bit 6) goes to 1. Bit 3 in Config Register determines if cycle passed through to 8042 and if SMI# generated. Bit 2 in Config Register determines if cycle passed through to 8042 and if SMI# generated. Bit 1 in Config Register determines if cycle passed through to 8042 and if SMI# generated. Bit 0 in Config Register determines if cycle passed through to 8042 and if SMI# generated. Cycle passed through to 8042, even if trap enabled in Bit 1 in Config Register. No SMI# generated. PSTATE remains 1. If data value is not DFh or DDh then the 8042 may chose to ignore it. IDLE Not D1h IDLE IDLE 64h / Read N/A IDLE IDLE 60h / Write Don't Care IDLE IDLE 60h / Read N/A IDLE GateState1 60h / Write XXh GateState2 198 Datasheet Functional Description Table 5-45. USB Legacy Keyboard State Transitions (Sheet 2 of 2) Current State Action Data Value Next State Comment Cycle passed through to 8042, even if trap enabled via Bit 3 in Config Register. No SMI# generated. PSTATE remains 1. Stay in GateState1 because this is part of the double-trigger sequence. Bit 3 in Config space determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. This is an invalid sequence. Bit 0 in Config Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. Just stay in same state. Generate an SMI# if enabled in Bit 2 of Config Register. PSTATE remains 1. Standard end of sequence. Cycle passed through to 8042. PSTATE goes to 0. Bit 7 in Config Space determines if SMI# should be generated. Improper end of sequence. Bit 3 in Config Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. Just stay in same state. Generate an SMI# if enabled in Bit 2 of Config Register. PSTATE remains 1. Improper end of sequence. Bit 1 in Config Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. Improper end of sequence. Bit 0 in Config Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. GateState1 64h / Write D1h GateState1 GateState1 64h / Write Not D1h ILDE GateState1 60h / Read N/A IDLE GateState1 64h / Read N/A GateState1 GateState2 64 / Write FFh IDLE GateState2 64h / Write Not FFh IDLE GateState2 64h / Read N/A GateState2 GateState2 60h / Write XXh IDLE GateState2 60h / Read N/A IDLE Datasheet 199 Functional Description 5.18.9 Function Level Reset Support (FLR) The USB UHCI Controllers support the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an Operating System in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the Operating System to reset the whole device as if a PCI reset was asserted. 5.18.9.1 5.18.9.1.1 FLR Steps FLR Initialization 1. A FLR is initiated by software writing a 1 to the Initiate FLR bit. 2. All subsequent requests targeting the Function will not be claimed and will be Master Abort Immediate on the bus. This includes any configuration, I/O or Memory cycles, however, the Function shall continue to accept completions targeting the Function. 5.18.9.1.2 FLR Operation The Function will Reset all configuration, I/O and memory registers of the Function except those indicated otherwise and reset all internal states of the Function to the default or initial condition. 5.18.9.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before accessing the function. 200 Datasheet Functional Description 5.19 USB EHCI Host Controllers (D29:F7 and D26:F7) The ICH10 contains two Enhanced Host Controller Interface (EHCI) host controllers which support up to twelve USB 2.0 high-speed root ports. USB 2.0 allows data transfers up to 480 Mb/s using the same pins as the twelve USB full-speed/low-speed ports. The ICH10 contains port-routing logic that determines whether a USB port is controlled by one of the UHCI controllers or by one of the EHCI controllers. USB 2.0 based Debug Port is also implemented in the ICH10. A summary of the key architectural differences between the USB UHCI host controllers and the EHCI host controller are shown in Table 5-46. Table 5-46. UHCI vs. EHCI Parameter Accessible by Memory Data Structure Differential Signaling Voltage Ports per Controller USB UHCI I/O space Single linked list 3.3 V 2 Memory Space Separated into Periodic and Asynchronous lists 400 mV 6 or 8 (controller #1) and 6 or 4 (Controller #2) USB EHCI 5.19.1 EHC Initialization The following descriptions step through the expected ICH10 Enhanced Host Controller (EHC) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off. 5.19.1.1 BIOS Initialization BIOS performs a number of platform customization steps after the core well has powered up. Contact your Intel Field Representative for additional ICH10 BIOS information. 5.19.1.2 Driver Initialization See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0. Datasheet 201 Functional Description 5.19.1.3 EHC Resets In addition to the standard ICH10 hardware resets, portions of the EHC are reset by the HCRESET bit and the transition from the D3HOT device power management state to the D0 state. The effects of each of these resets are: Reset Does Reset Memory space registers except Structural Parameters (which is written by BIOS). Does not Reset Comments The HCRESET must only affect registers that the EHCI driver controls. PCI Configuration space and BIOS-programmed parameters can not be reset. The D3-to-D0 transition must not cause wake information (suspend well) to be lost. It also must not clear BIOSprogrammed registers because BIOS may not be invoked following the D3-to-D0 transition. HCRESET bit set. Configuration registers. Software writes the Device Power State from D3HOT (11b) to D0 (00b). Core well registers (except BIOSprogrammed registers). Suspend well registers; BIOSprogrammed core well registers. If the detailed register descriptions give exceptions to these rules, those exceptions override these rules. This summary is provided to help explain the reasons for the reset policies. 5.19.2 Data Structures in Main Memory See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 for details. 5.19.3 USB 2.0 Enhanced Host Controller DMA The ICH10 USB 2.0 EHC implements three sources of USB packets. They are, in order of priority on USB during each microframe: 1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port), 2. The Periodic DMA engine, and 3. The Asynchronous DMA engine. The ICH10 always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. If there is time left in the microframe, then the EHC performs any pending asynchronous traffic until the end of the microframe (EOF1). Note that the debug port traffic is only presented on one port (Port #0), while the other ports are idle during this time. 5.19.4 Data Encoding and Bit Stuffing See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0. 202 Datasheet Functional Description 5.19.5 Packet Formats See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0. The ICH10 EHCI allows entrance to USB test modes, as defined in the USB 2.0 specification, including Test J, Test Packet, etc. However note that the ICH10 Test Packet test mode interpacket gap timing may not meet the USB 2.0 specification. 5.19.6 USB 2.0 Interrupts and Error Conditions Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that cause them. All error conditions that the EHC detects can be reported through the EHCI Interrupt status bits. Only ICH10-specific interrupt and error-reporting behavior is documented in this section. The EHCI Interrupts Section must be read first, followed by this section of the datasheet to fully comprehend the EHC interrupt and error-reporting functionality. • Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer Error can never occur on the ICH10. • Master Abort and Target Abort responses from hub interface on EHC-initiated read packets will be treated as Fatal Host Errors. The EHC halts when these conditions are encountered. • The ICH10 may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. The requirement in the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on DMI before the interrupt is asserted. • Since the ICH10 supports the 1024-element Frame List size, the Frame List Rollover interrupt occurs every 1024 milliseconds. • The ICH10 delivers interrupts using PIRQH#. • The ICH10 does not modify the CERR count on an Interrupt IN when the “Do Complete-Split” execution criteria are not met. • For complete-split transactions in the Periodic list, the “Missed Microframe” bit does not get set on a control-structure-fetch that fails the late-start test. If subsequent accesses to that control structure do not fail the late-start test, then the “Missed Microframe” bit will get set and written back. 5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following actions are taken when this occurs: • The Host System Error status bit is set • The DMA engines are halted after completing up to one more transaction on the USB interface • If enabled (by the Host System Error Enable), then an interrupt is generated • If the status is Master Abort, then the Received Master Abort bit in configuration space is set • If the status is Target Abort, then the Received Target Abort bit in configuration space is set • If enabled (by the SERR Enable bit in the function’s configuration space), then the Signaled System Error bit in configuration bit is set. Datasheet 203 Functional Description 5.19.7 5.19.7.1 USB 2.0 Power Management Pause Feature This feature allows platforms to dynamically enter low-power states during brief periods when the system is idle (i.e., between keystrokes). This is useful for enabling power management features in the ICH10. The policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. Normally, when the EHC is enabled, it regularly accesses main memory while traversing the DMA schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. Suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the USB ports that makes this unacceptable for the purpose of dynamic power management. As a result, the EHCI software drivers are allowed to pause the EHC’s DMA engines when it knows that the traffic patterns of the attached devices can afford the delay. The pause only prevents the EHC from generating memory accesses; the SOF packets continue to be generated on the USB ports (unlike the suspended state). 5.19.7.2 Suspend Feature The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification, Section 4.3 describes the details of Port Suspend and Resume. 5.19.7.3 ACPI Device States The USB 2.0 function only supports the D0 and D3 PCI Power Management states. Notes regarding the ICH10 implementation of the Device States: 1. The EHC hardware does not inherently consume any more power when it is in the D0 state than it does in the D3 state. However, software is required to suspend or disable all ports prior to entering the D3 state such that the maximum power consumption is reduced. 2. In the D0 state, all implemented EHC features are enabled. 3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort. Note that, since the Debug Port uses the same memory range, the Debug Port is only operational when the EHC is in the D0 state. 4. In the D3 state, the EHC interrupt must never assert for any reason. The internal PME# signal is used to signal wake events, etc. 5. When the Device Power State field is written to D0 from D3, an internal reset is generated. See section EHC Resets for general rules on the effects of this reset. 6. Attempts to write any other value into the Device Power State field other than 00b (D0 state) and 11b (D3 state) will complete normally without changing the current value in this field. 204 Datasheet Functional Description 5.19.7.4 ACPI System States The EHC behavior as it relates to other power management states in the system is summarized in the following list: — The System is always in the S0 state when the EHC is in the D0 state. However, when the EHC is in the D3 state, the system may be in any power management state (including S0). — When in D0, the Pause feature (See Section 5.19.7.1) enables dynamic processor low-power states to be entered. — The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power turns off). — All core well logic is reset in the S3/S4/S5 states. 5.19.8 Interaction with UHCI Host Controllers The Enhanced Host controllers share its ports with UHCI Host controllers in the ICH10. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1 shares ports 2 and 3; the UHC at D29:F2 shares ports 4 and 5 with the EHC at D29:F7, while the UHC at D26:F0 shares ports 6 and 7, the UHC at D26:F1 shares ports 8 and 9, and the UHC at D26:F2 shares ports 10 and 11 with EHC at D26:F7. There is very little interaction between the Enhanced and the UHCI controllers other than the muxing control which is provided as part of the EHC. Figure 5-14 shows the USB Port Connections at a conceptual level. Note: D26:F2 can be configured as D29:F3 during BIOS post. Datasheet 205 Functional Description 5.19.8.1 Port-Routing Logic Integrated into the EHC functionality is port-routing logic, which performs the muxing between the UHCI and EHCI host controllers. The ICH10 conceptually implements this logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of USB 2.0’s high-speed signaling protocol or if the EHCI software drivers are not present as indicated by the Configured Flag, then the UHCI controller owns the port. Owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. The host controller that is not the owner of the port internally sees a disconnected port. Figure 5-14. Intel® ICH10-USB Port Connections Default Six and Six Configuration EHCI #1 UHCI UHCI UHCI UHCI UHCI EHCI #2 UHCI UHCI UHCI Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Figure 5-15. Intel® ICH10-USB Port Connections Eight and Four Configuration EHCI #1 UHCI UHCI UHCI UHCI UHCI EHCI #2 UHCI UHCI UHCI Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 10 Port 11 Port 6 Port 7 Port 8 Port 9 Note that the port-routing logic is the only block of logic within the ICH10 that observes the physical (real) connect/disconnect information. The port status logic inside each of the host controllers observes the electrical connect/disconnect information that is generated by the port-routing logic. Only the differential signal pairs are multiplexed/de-multiplexed between the UHCI and EHCI host controllers. The other USB functional signals are handled as follows: • The Overcurrent inputs (OC[11:0]#) are directly routed to both controllers. An overcurrent event is recorded in both controllers’ status registers. 206 Datasheet Functional Description The Port-Routing logic is implemented in the Suspend power well so that reenumeration and re-mapping of the USB ports is not required following entering and exiting a system sleep state in which the core power is turned off. The ICH10 also allows the USB Debug Port traffic to be routed in and out of Port #0 and Port #6. When in this mode, the Enhanced Host controller is the owner of Port #0 and Port #6. 5.19.8.2 Device Connects The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 describes the details of handling Device Connects in Section 4.2. There are four general scenarios that are summarized below. 1. Configure Flag = 0 and a full-speed/low-speed-only Device is connected — In this case, the UHC is the owner of the port both before and after the connect occurs. The EHC (except for the port-routing logic) never sees the connect occur. The UHCI driver handles the connection and initialization process. 2. Configure Flag = 0 and a high-speed-capable Device is connected — In this case, the UHC is the owner of the port both before and after the connect occurs. The EHC (except for the port-routing logic) never sees the connect occur. The UHCI driver handles the connection and initialization process. Since the UHC does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. Configure Flag = 1 and a full-speed/low-speed-only Device is connected — In this case, the EHC is the owner of the port before the connect occurs. The EHCI driver handles the connection and performs the port reset. After the reset process completes, the EHC hardware has cleared (not set) the Port Enable bit in the EHC’s PORTSC register. The EHCI driver then writes a 1 to the Port Owner bit in the same register, causing the UHC to see a connect event and the EHC to see an “electrical” disconnect event. The UHCI driver and hardware handle the connection and initialization process from that point on. The EHCI driver and hardware handle the perceived disconnect. 4. Configure Flag = 1 and a high-speed-capable Device is connected — In this case, the EHC is the owner of the port before, and remains the owner after, the connect occurs. The EHCI driver handles the connection and performs the port reset. After the reset process completes, the EHC hardware has set the Port Enable bit in the EHC’s PORTSC register. The port is functional at this point. The UHC continues to see an unconnected port. Datasheet 207 Functional Description 5.19.8.3 Device Disconnects The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 describes the details of handling Device Connects in Section 4.2. There are three general scenarios that are summarized below. 1. Configure Flag = 0 and the device is disconnected — In this case, the UHC is the owner of the port both before and after the disconnect occurs. The EHC (except for the port-routing logic) never sees a device attached. The UHCI driver handles disconnection process. 2. Configure Flag = 1 and a full-speed/low-speed-capable Device is disconnected — In this case, the UHC is the owner of the port before the disconnect occurs. The disconnect is reported by the UHC and serviced by the associated UHCI driver. The port-routing logic in the EHC cluster forces the Port Owner bit to 0, indicating that the EHC owns the unconnected port. 3. Configure Flag = 1 and a high-speed-capable Device is disconnected — In this case, the EHC is the owner of the port before, and remains the owner after, the disconnect occurs. The EHCI hardware and driver handle the disconnection process. The UHC never sees a device attached. 5.19.8.4 Effect of Resets on Port-Routing Logic As mentioned above, the Port Routing logic is implemented in the suspend power well so that remuneration and re-mapping of the USB ports is not required following entering and exiting a system sleep state in which the core power is turned off. Reset Event Suspend Well Reset Core Well Reset D3-to-D0 Reset HCRESET Effect on Configure Flag cleared (0) no effect no effect cleared (0) Effect on Port Owner Bits set (1) no effect no effect set (1) 5.19.9 USB 2.0 Legacy Keyboard Operation The ICH10 must support the possibility of a keyboard downstream from either a fullspeed/low-speed or a high-speed port. The description of the legacy keyboard support is unchanged from USB 1.1 (See Section 5.18.8). The EHC provides the basic ability to generate SMIs on an interrupt event, along with more sophisticated control of the generation of SMIs. 208 Datasheet Functional Description 5.19.10 USB 2.0 Based Debug Port The ICH10 supports the elimination of the legacy COM ports by providing the ability for new debugger software to interact with devices on a USB 2.0 port. High-level restrictions and features are: • Operational before USB 2.0 drivers are loaded. • Functions even when the port is disabled. • Works even though non-configured port is default-routed to the UHCI. Note that the Debug Port can not be used to debug an issue that requires a full-speed/lowspeed device on Port #0 using the UHCI drivers. • Allows normal system USB 2.0 traffic in a system that may only have one USB port. • Debug Port device (DPD) must be high-speed capable and connect directly to Port #0 and Port #6 on ICH10 systems (e.g., the DPD cannot be connected to Port #0/Port #6 through a hub). • Debug Port FIFO always makes forward progress (a bad status on USB is simply presented back to software). • The Debug Port FIFO is only given one USB access per microframe. The Debug port facilitates operating system and device driver debug. It allows the software to communicate with an external console using a USB 2.0 connection. Because the interface to this link does not go through the normal USB 2.0 stack, it allows communication with the external console during cases where the operating system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is being debugged. Specific features of this implementation of a debug port are: • Only works with an external USB 2.0 debug device (console) • Implemented for a specific port on the host controller • Operational anytime the port is not suspended AND the host controller is in D0 power state. • Capability is interrupted when port is driving USB RESET 5.19.10.1 Theory of Operation There are two operational modes for the USB debug port: 1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host controller driver. In Mode 1, the Debug Port controller is required to generate a “keepalive” packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive packet should be a standalone 32-bit SYNC field. 2. Mode 2 is when the host controller is running (i.e., host controller’s Run/Stop# bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug device from suspending. Behavioral Rules 1. In both modes 1 and 2, the Debug Port controller must check for software requested debug transactions at least every 125 microseconds. 2. If the debug port is enabled by the debug driver, and the standard host controller driver resets the USB port, USB debug transactions are held off for the duration of the reset and until after the first SOF is sent. 3. If the standard host controller driver suspends the USB port, then USB debug transactions are held off for the duration of the suspend/resume sequence and until after the first SOF is sent. 4. The ENABLED_CNT bit in the debug register space is independent of the similar port control bit in the associated Port Status and Control register. Datasheet 209 Functional Description Table 5-47 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated Port Status and Control register. Table 5-47. Debug Port Behavior OWNER_CNT 0 1 ENABLED_CT X 0 Port Enable X X Run / Stop X X Suspend X X Debug Port Behavior Debug port is not being used. Normal operation. Debug port is not being used. Normal operation. Debug port in Mode 1. SYNC keepalives sent plus debug traffic Debug port in Mode 2. SOF (and only SOF) is sent as keepalive. Debug traffic is also sent. Note that no other normal traffic is sent out this port, because the port is not enabled. invalid. Host controller driver should never put controller into this state (enabled, not running and not suspended). Port is suspended. No debug traffic sent. Debug port in Mode 2. Debug traffic is interspersed with normal traffic. Port is suspended. No debug traffic sent. 1 1 0 0 X 1 1 0 1 X 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 5.19.10.1.1 OUT Transactions An Out transaction sends data to the debug device. It can occur only when the following are true: • The debug port is enabled • The debug software sets the GO_CNT bit • The WRITE_READ#_CNT bit is set The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: — — — — — — — — USB_ADDRESS_CNF USB_ENDPOINT_CNF DATA_BUFFER[63:0] TOKEN_PID_CNT[7:0] SEND_PID_CNT[15:8] DATA_LEN_CNT WRITE_READ#_CNT: (note: this will always be 1 for OUT transactions) GO_CNT: (note: this will always be 1 to initiate the transaction) 210 Datasheet Functional Description 2. The debug port controller sends a token packet consisting of: — — — — — SYNC TOKEN_PID_CNT field USB_ADDRESS_CNT field USB_ENDPOINT_CNT field 5-bit CRC field 3. After sending the token packet, the debug port controller sends a data packet consisting of: — — — — SYNC SEND_PID_CNT field The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER 16-bit CRC NOTE: ‘A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be included in the packet. 4. After sending the data packet, the controller waits for a handshake response from the debug device. • If a handshake is received, the debug port controller: — a. Places the received PID in the RECEIVED_PID_STS field — b. Resets the ERROR_GOOD#_STS bit — c. Sets the DONE_STS bit • If no handshake PID is received, the debug port controller: — a. Sets the EXCEPTION_STS field to 001b — b. Sets the ERROR_GOOD#_STS bit — c. Sets the DONE_STS bit 5.19.10.1.2 IN Transactions An IN transaction receives data from the debug device. It can occur only when the following are true: • The debug port is enabled • The debug software sets the GO_CNT bit • The WRITE_READ#_CNT bit is reset The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: — — — — — — USB_ADDRESS_CNF USB_ENDPOINT_CNF TOKEN_PID_CNT[7:0] DATA_LEN_CNT WRITE_READ#_CNT: (Note: This will always be 0 for IN transactions.) GO_CNT: (Note: This will always be 1 to initiate the transaction.) Datasheet 211 Functional Description 2. The debug port controller sends a token packet consisting of: — — — — — SYNC TOKEN_PID_CNT field USB_ADDRESS_CNT field USB_ENDPOINT_CNT field 5-bit CRC field. 3. After sending the token packet, the debug port controller waits for a response from the debug device. If a response is received: — The received PID is placed into the RECEIVED_PID_STS field — Any subsequent bytes are placed into the DATA_BUFFER — The DATA_LEN_CNT field is updated to show the number of bytes that were received after the PID. 4. If a valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: — Resets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit 5. If a valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: — Transmits an ACK handshake packet — Resets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit 6. If no valid packet is received, then the debug port controller: — Sets the EXCEPTION_STS field to 001b — Sets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit. 5.19.10.1.3 Debug Software Enabling the Debug Port There are two mutually exclusive conditions that debug software must address as part of its startup processing: • The EHCI has been initialized by system software • The EHCI has not been initialized by system software Debug software can determine the current ‘initialized’ state of the EHCI by examining the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then system software has initialized the EHCI. Otherwise the EHCI should not be considered initialized. Debug software will initialize the debug port registers depending on the state of the EHCI. However, before this can be accomplished, debug software must determine which root USB port is designated as the debug port. Determining the Debug Port Debug software can easily determine which USB root port has been designated as the debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters register. This 4-bit field represents the numeric value assigned to the debug port (i.e., 0000 = port 0). 212 Datasheet Functional Description Debug Software Startup with Non-Initialized EHCI Debug software can attempt to use the debug port if after setting the OWNER_CNT bit, the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected to the port, then debug software must reset/enable the port. Debug software does this by setting and then clearing the Port Reset bit the PORTSC register. To ensure a successful reset, debug software should wait at least 50 ms before clearing the Port Reset bit. Due to possible delays, this bit may not change to 0 immediately; reset is complete when this bit reads as 0. Software must not continue until this bit reads 0. If a high-speed device is attached, the EHCI will automatically set the Port Enabled/ Disabled bit in the PORTSC register and the debug software can proceed. Debug software should set the ENABLED_CNT bit in the Debug Port Control/Status register, and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the system host controller driver does not see an enabled port when it is first loaded). Debug Software Startup with Initialized EHCI Debug software can attempt to use the debug port if the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected, then debug software must set the OWNER_CNT bit and then the ENABLED_CNT bit in the Debug Port Control/Status register. Determining Debug Peripheral Presence After enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. If all attempts result in an error (Exception bits in the Debug Port Control/Status register indicates a Transaction Error), then the attached device is not a debug peripheral. If the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected. 5.19.11 USB Pre-Fetch Based Pause The Pre-Fetch Based Pause is a power management feature in USB (EHCI) host controllers to ensure maximum C3/C4 processor power state time with C2 popup. This feature applies to the period schedule, and works by allowing the DMA engine to identify periods of idleness and preventing the DMA engine from accessing memory when the periodic schedule is idle. Typically in the presence of periodic devices with multiple millisecond poll periods, the periodic schedule will be idle for several frames between polls. The USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI Configuration Register Section 17.1.30. Datasheet 213 Functional Description 5.19.12 Function Level Reset Support (FLR) The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an Operating System in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the Operating System to reset the whole device as if a PCI reset was asserted. 5.19.12.1 FLR Steps 5.19.12.1.1 FLR Initialization 1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit. 2. All subsequent requests targeting the Function will not be claimed and will be Master Abort Immediate on the bus. This includes any configuration, I/O or Memory cycles, however, the Function shall continue to accept completions targeting the Function. 5.19.12.1.2 FLR Operation The Function will Reset all configuration, I/O and memory registers of the Function except those indicated otherwise and reset all internal states of the Function to the default or initial condition. 5.19.12.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before accessing the function. 5.20 SMBus Controller (D31:F3) The ICH10 provides an System Management Bus (SMBus) 2.0 host controller as well as an SMBus Slave Interface. The host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The ICH10 is also capable of operating in a mode in which it can communicate with I2C compatible devices. The ICH10 can perform SMBus messages with either packet error checking (PEC) enabled or disabled. The actual PEC calculation and checking is performed in hardware by the ICH10. The Slave Interface allows an external master to read from or write to the ICH10. Write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. The ICH10’s internal host controller cannot access the ICH10’s internal Slave Interface. The ICH10 SMBus logic exists in Device 31:Function 3 configuration space, and consists of a transmit data path, and host controller. The transmit data path provides the data flow logic needed to implement the seven different SMBus command protocols and is controlled by the host controller. The ICH10 SMBus controller logic is clocked by RTC clock. The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller commands through software, except for the new Host Notify command (which is actually a received message). 214 Datasheet Functional Description The programming model of the host controller is combined into two portions: a PCI configuration portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is done via the PCI configuration space. Real-time programming of the Host interface is done in system I/O space. The ICH10 SMBus host controller checks for parity errors as a target. If an error is detected, the detected parity error bit in the PCI Status Register (Device 31:Function 3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device 31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit in the PCI Status Register (bit 14) is set. 5.20.1 Host Controller The SMBus host controller is used to send commands to other SMBus slave devices. Software sets up the host controller with an address, command, and, for writes, data and optional PEC; and then tells the controller to start. When the controller has finished transmitting data on writes, or receiving data on reads, it generates an SMI# or interrupt, if enabled. The host controller supports 8 command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block Write–Block Read Process Call, and Host Notify. The SMBus host controller requires that the various data and command fields be setup for the type of command to be sent. When software sets the START bit, the SMBus Host controller performs the requested transaction, and interrupts the processor (or generates an SMI#) when the transaction is completed. Once a START command has been issued, the values of the “active registers” (Host Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read until the interrupt status bit (INTR) has been set (indicating the completion of the command). Any register values needed for computation purposes should be saved prior to issuing of a new command, as the SMBus host controller updates all registers while completing the new command. The ICH10 supports the System Management Bus (SMBus) Specification, Version 2.0. Slave functionality, including the Host Notify protocol, is available on the SMBus pins. The SMLink and SMBus signals can be tied together externally depending on TCO mode used. Refer to Section 5.14.2 for more details. Using the SMB host controller to send commands to the ICH10’s SMB slave port is not supported. 5.20.1.1 Command Protocols In all of the following commands, the Host Status Register (offset 00h) is used to determine the progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set in the Host Status Register. If the device does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the Host Control Register while the command is running, the transaction will stop and the FAILED bit will be set. Quick Command When programmed for a Quick Command, the Transmit Slave Address Register is sent. The PEC byte is never appended to the Quick Protocol. Software should force the PEC_EN bit to 0 when performing the Quick Command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.1 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Datasheet 215 Functional Description Send Byte / Receive Byte For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent. For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when running this command. The Receive Byte is similar to a Send Byte, the only difference is the direction of data transfer. See sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Write Byte/Word The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data to be written. When programmed for a Write Byte/Word command, the Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition, the Data1 Register is sent on a Write Word command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.4 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Read Byte/Word Reading data is slightly more complicated than writing data. First the ICH10 must write a command to the slave device. Then it must follow that command with a repeated start condition to denote a read from that device's address. The slave then returns 1 or 2 bytes of data. Software must force the I2C_EN bit to 0 when running this command. When programmed for the read byte/word command, the Transmit Slave Address and Device Command Registers are sent. Data is received into the DATA0 on the read byte, and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Process Call The process call is so named because a command sends data and waits for the slave to return a value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition. When programmed for the Process Call command, the ICH10 transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers. The Process Call command with I2C_EN set and the PEC_EN bit set produces undefined results. Software must force either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: Note: For process call command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code (bits 18:11 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 19 in the sequence). 216 Datasheet Functional Description Block Read/Write The ICH10 contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32-byte buffer is filled with write data before transmission, and filled with read data on reception. In the ICH10, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. The byte count field is transmitted but ignored by the ICH10 as software will end the transfer after all bytes it cares about have been sent or received. For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and AAC bits to 0 when running this command. The block write begins with a slave address and a write condition. After the command code the ICH10 issues a byte count describing how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes. When programmed for a block write command, the Transmit Slave Address, Device Command, and Data0 (count) registers are sent. Data is then sent from the Block Data Byte register; the total data sent being the value stored in the Data0 Register. On block read commands, the first byte received is stored in the Data0 register, and the remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly. The ICH10 will still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the DATA0 register. However, it will not send the contents of the DATA0 register as part of the message. Also, the Block Write protocol sequence changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 28 in the sequence). Datasheet 217 Functional Description I2C Read This command allows the ICH10 to perform block reads to certain I2C devices, such as serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only. However, this does not allow access to devices using the I2C “Combined Format” that has data bytes after the address. Typically these data bytes correspond to an offset (address) within the serial memory chips. Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read command with the PEC_EN bit set produces undefined results. Software must force both the PEC_EN and AAC bit to 0 when running this command. For I2C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. The format that is used for the command is shown in Table 5-48. Table 5-48. I2C Block Read Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 – – – – Start Slave Address — 7 bits Write Acknowledge from slave Send DATA1 register Acknowledge from slave Repeated Start Slave Address — 7 bits Read Acknowledge from slave Data byte 1 from slave — 8 bits Acknowledge Data byte 2 from slave — 8 bits Acknowledge Data bytes from slave / Acknowledge Data byte N from slave — 8 bits NOT Acknowledge Stop Description The ICH10 will continue reading data from the peripheral until the NAK is received. 218 Datasheet Functional Description Block Write–Block Read Process Call The block write-block read process call is a two-part message. The call begins with a slave address and a write condition. After the command code the host issues a write byte count (M) that describes how many more bytes will be written in the first part of the message. If a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0. The second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a Read bit. The next byte is the read byte count (N), which may differ from the write byte count (M). The read byte count (N) cannot be 0. The combined data payload must not exceed 32 bytes. The byte length restrictions of this process call are summarized as follows: • M ≥ 1 byte • N ≥ 1 byte • M + N ≤ 32 bytes The read byte count does not include the PEC byte. The PEC is computed on the total message beginning with the first slave address and using the normal PEC computational rules. It is highly recommended that a PEC byte be used with the Block Write-Block Read Process Call. Software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. Note that there is no STOP condition before the repeated START condition, and that a NACK signifies the end of the read transfer. Note: E32B bit in the Auxiliary Control register must be set when using this protocol. See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. 5.20.2 Bus Arbitration Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low to signal a start condition. The ICH10 continuously monitors the SMBDATA line. When the ICH10 is attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus and the ICH10 will stop transferring data. If the ICH10 sees that it has lost arbitration, the condition is called a collision. The ICH10 will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an interrupt or SMI#. The processor is responsible for restarting the transaction. When the ICH10 is a SMBus master, it drives the clock. When the ICH10 is sending address or command as an SMBus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. It will not start toggling the clock until the start or stop condition meets proper setup and hold time. The ICH10 will also ensure minimum time between SMBus transactions as a master. Note: The ICH10 supports the same arbitration protocol for both the SMBus and the System Management (SMLINK) interfaces. Datasheet 219 Functional Description 5.20.3 5.20.3.1 Bus Timing Clock Stretching Some devices may not be able to handle their clock toggling at the rate that the ICH10 as an SMBus master would like. They have the capability of stretching the low time of the clock. When the ICH10 attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. The ICH10 monitors the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. While the bus is still low, the high time counter must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data. 5.20.3.2 Bus Time Out (Intel® ICH10 as SMBus Master) If there is an error in the transaction, such that an SMBus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. The ICH10 will discard the cycle and set the DEV_ERR bit. The time out minimum is 25 ms (800 RTC clocks). The time-out counter inside the ICH10 will start after the last bit of data is transferred by the ICH10 and it is waiting for a response. The 25 ms timeout counter will not count under the following conditions: 1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set 2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that the system has not locked up). 220 Datasheet Functional Description 5.20.4 Interrupts / SMI# The ICH10 SMBus controller uses PIRQB# as its interrupt pin. However, the system can alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1). Table 5-50 and Table 5-51 specify how the various enable bits in the SMBus function control the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables are additive, which means that if more than one row is true for a particular scenario then the Results for all of the activated rows will occur. Table 5-49. Enable for SMBALERT# INTREN (Host Control I/O Register, Offset 02h, Bit 0) X X 1 SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit 1) X 1 0 SMBALERT_DIS (Slave Command I/O Register, Offset 11h, Bit 2) X 0 0 Event Result SMBALERT# asserted low (always reported in Host Status Register, Bit 5) Wake generated Slave SMI# generated (SMBUS_SMI_STS) Interrupt generated Table 5-50. Enables for SMBus Slave Write and SMBus Host Events Event INTREN (Host Control I/O Register, Offset 02h, Bit 0) X SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit1) X Event Wake generated when asleep. Slave SMI# generated when awake (SMBUS_SMI_STS). Slave SMI# generated when in the S0 state (SMBUS_SMI_STS) None Interrupt generated Host SMI# generated Slave Write to Wake/ SMI# Command Slave Write to SMLINK_SLAVE_SMI Command Any combination of Host Status Register [4:1] asserted X 0 1 1 X X 0 1 Table 5-51. Enables for the Host Notify Command HOST_NOTIFY_INTREN (Slave Control I/O Register, Offset 11h, bit 0) 0 X 1 1 SMB_SMI_EN (Host Config Register, D31:F3:Off40h, Bit 1) X X 0 1 HOST_NOTIFY_WKEN (Slave Control I/O Register, Offset 11h, bit 1) 0 1 X X None Wake generated Interrupt generated Slave SMI# generated (SMBUS_SMI_STS) Result Datasheet 221 Functional Description 5.20.5 SMBALERT# SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, The ICH10 can generate an interrupt, an SMI#, or a wake event from S1–S5. 5.20.6 SMBus CRC Generation and Checking If the AAC bit is set in the Auxiliary Control register, the ICH10 automatically calculates and drives CRC at the end of the transmitted packet for write cycles, and will check the CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The PEC bit must not be set in the Host Control register if this bit is set, or unspecified behavior will result. If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the Auxiliary Status register at offset 0Ch will be set. 5.20.7 SMBus Slave Interface The ICH10’s SMBus Slave interface is accessed via the SMBus. The SMBus slave logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting Protocol device. The slave interface allows the ICH10 to decode cycles, and allows an external microcontroller to perform specific actions. Key features and capabilities include: • Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify. • Receive Slave Address register: This is the address that the ICH10 decodes. A default value is provided so that the slave interface can be used without the processor having to program this register. • Receive Slave Data register in the SMBus I/O space that includes the data written by the external microcontroller. • Registers that the external microcontroller can read to get the state of the ICH10. • Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due to the reception of a message that matched the slave address. — Bit 0 of the Slave Status Register for the Host Notify command — Bit 16 of the SMI Status Register (Section 13.8.3.13) for all others Note: The external microcontroller should not attempt to access the Intel ICH10’s SMBus slave logic until either: — 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR — The PLTRST# deasserts If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more in the middle of a cycle, the ICH10 slave logic's behavior is undefined. This is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus a translation in the address is needed to accommodate the least significant bit used for read/write control. For example, if the ICH10 slave address (RCV_SLVA) is left at 44h (default), the external micro controller would use an address of 88h/89h (write/read). 222 Datasheet Functional Description 5.20.7.1 Format of Slave Write Cycle The external master performs Byte Write commands to the ICH10 SMBus Slave I/F. The “Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 20:27) indicate the value that should be written to that register. Table 5-52 has the values associated with the registers. Table 5-52. Slave Write Registers Register 0 1–3 4 5 6–7 8 9–FFh Function Command Register. See Table 5-53 below for legal values written to this register. Reserved Data Message Byte 0 Data Message Byte 1 Reserved Reserved Reserved NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. The ICH10 overwrites the old value with any new value received. A race condition is possible where the new value is being written to the register just at the time it is being read. ICH10 will not attempt to cover this race condition (i.e., unpredictable results in this case). . Table 5-53. Command Types (Sheet 1 of 2) Command Type 0 Reserved WAKE/SMI#. This command wakes the system if it is not already awake. If system is already awake, an SMI# is generated. NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is already awake. The SMI handler should then clear this bit. Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same effect as the Powerbutton Override occurring. HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system (does not include cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0. HARD RESET SYSTEM. This command causes a hard reset of the system (including cycling of the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1. Disable the TCO Messages. This command will disable the Intel ICH10 from sending Heartbeat and Event messages (as described in Section 5.14). Once this command has been executed, Heartbeat and Event message reporting can only be re-enabled by assertion and deassertion of the RSMRST# signal. WD RELOAD: Reload watchdog timer. Reserved Description 1 2 3 4 5 6 7 Datasheet 223 Functional Description Table 5-53. Command Types (Sheet 2 of 2) Command Type Description SMLINK_SLV_SMI. When ICH10 detects this command type while in the S0 state, it sets the SMLINK_SLV_SMI_STS bit (see Section 13.9.5). This command should only be used if the system is in an S0 state. If the message is received during S1–S5 states, the ICH10 acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set. NOTE: It is possible that the system transitions out of the S0 state at the same time that the SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes to sleep. Once the system returns to S0, the SMI associated with this bit would then be generated. Software must be able to handle this scenario. Reserved. 8 9-FFh 5.20.7.2 Format of Read Command The external master performs Byte Read commands to the ICH10 SMBus Slave interface. The “Command” field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register. Table 5-54. Slave Read Cycle Format Bit 1 2-8 9 10 11-18 19 20 21-27 28 29 30-37 38 39 Start Slave Address - 7 bits Write ACK Command code – 8 bits ACK Repeated Start Slave Address - 7 bits Read ACK Data Byte NOT ACK Stop Description Driven by External Microcontroller External Microcontroller External Microcontroller Intel ICH10 External Microcontroller Intel ICH10 External Microcontroller External Microcontroller External Microcontroller Intel ICH10 Intel ICH10 External Microcontroller External Microcontroller Value depends on register being accessed. Table 5-55 below for list of implemented registers. Must match value in Receive Slave Address register Always 1 Indicates which register is being accessed. See Table 5-55 below for list of implemented registers. Must match value in Receive Slave Address register Always 0 Comment 224 Datasheet Functional Description Table 5-55. Data Values for Slave Read Registers (Sheet 1 of 2) Register 0 Bits 7:0 Description Reserved for capabilities indication. Should always return 00h. Future chips may return another value to indicate different capabilities. System Power State 1 2:0 7:3 2 3:0 7:4 3 5:0 7:6 4 0 1 (Consumer Only) 1 (Corporate Only) 2 3 6:4 000 = S0 001 = S1 010 = Reserved 011 = S3 100 = S4 101 = S5 110 = Reserved 111 = Reserved Reserved Reserved Reserved Watchdog Timer current value Note that Watchdog Timer has 10 bits, but this field is only 6 bits. If the current value is greater than 3Fh, ICH10 will always report 3Fh in this field. Reserved 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. 1 = BTI Temperature Event occurred. This bit will be set if the Intel ICH10’s THRM# input signal is at a valid low voltage state. This bit will be clear if the THRM# input signal is at a valid high voltage state. NOTE: This bit interprets the behavior if the THRM# pin as active low. This bit is set independent of the TRM#_POL bit setting. 1 = BTI Temperature Event occurred. This bit will be set if the Intel ICH10’s THRM# input signal is active. Else this bit will read 0. NOTE: The THRM# pin is in core well and accurate reflection of the THRM# pin is dependent on the platform being in S0. DOA CPU Status. This bit will be 1 to indicate that the processor is dead 1 = SECOND_TO_STS bit set. This bit will be set after the second time-out (SECOND_TO_STS bit) of the Watchdog Timer occurs. Reserved. Will always be 0, but software should ignore. Reflects the value of the GPIO[11]/SMBALERT# pin (and is dependent upon the value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then the value in this bit equals the level of the GPI[11]/SMBALERT# pin (high = 1, low = 0). If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse of the level of the GPIO[11]/SMBALERT# pin (high = 0, low = 1). 5 0 1 2 FWH bad bit. This bit will be 1 to indicate that the FWH read returned FFh, which indicates that it is probably blank. Reserved CPU Power Failure Status: ‘1’ if the CPUPWR_FLR bit in the GEN_PMCON_2 register is set. INIT# due to receiving Shutdown message: This event is visible from the reception of the shutdown message until a platform reset is done if the Shutdown Policy Select bit (SPS) is configured to drive INIT#. When the SPS bit is configured to generate PLTRST# based on shutdown, this register bit will always return 0. Events on signal will not create a event message 4 Reserved 7 3 Datasheet 225 Functional Description Table 5-55. Data Values for Slave Read Registers (Sheet 2 of 2) Register Bits 5 Description POWER_OK_BAD: Indicates the failure core power well ramp during boot/resume. This bit will be active if the SLP_S3# pin is de-asserted and PWROK pin is not asserted. Thermal Trip: This bit will shadow the state of processor Thermal Trip status bit (CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will not create a event message Reserved: Default value is “X” 7 6 7 8 9 A B C D E F 10h–FFh 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 Note: Software should not expect a consistent value when this bit is read through SMBUS/SMLINK Contents of the Message 1 register. Refer to Section 13.9.8 for the description of this register. Contents of the Message 2 register. Refer to Section 13.9.8 for the description of this register. Contents of the TCO_WDCNT register. Refer to Section 13.9.9 for the description of this register. Seconds of the RTC Minutes of the RTC Hours of the RTC “Day of Week” of the RTC “Day of Month” of the RTC Month of the RTC Year of the RTC Reserved 6 5.20.7.2.1 Behavioral Notes According to SMBus protocol, Read and Write messages always begin with a Start bit – Address– Write bit sequence. When the ICH10 detects that the address matches the value in the Receive Slave Address register, it will assume that the protocol is always followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In other words, if a Start –Address–Read occurs (which is invalid for SMBus Read or Write protocol), and the address matches the ICH10’s Slave Address, the ICH10 will still grab the cycle. Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address– Read sequence beginning at bit 20. Once again, if the Address matches the ICH10’s Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Slave Read cycle. Note: An external microcontroller must not attempt to access the ICH10’s SMBus Slave logic until at least 1 second after both RTCRST# and RSMRST# are deasserted (high). 5.20.7.3 Slave Read of RTC Time Bytes The ICH10 SMBus slave interface allows external SMBus master to read the internal RTC’s time byte registers. The RTC time bytes are internally latched by the ICH10’s hardware whenever RTC time is not changing and SMBus is idle. This ensures that the time byte delivered to the slave read is always valid and it does not change when the read is still in progress on the bus. The RTC time will change whenever hardware update is in progress, or there is a software write to the RTC time bytes. 226 Datasheet Functional Description The ICH10 SMBus slave interface only supports Byte Read operation. The external SMBus master will read the RTC time bytes one after another. It is software’s responsibility to check and manage the possible time rollover when subsequent time bytes are read. For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the external SMBus master reads the hour as 11, then proceeds to read the minute, it is possible that the rollover happens between the reads and the minute is read as 0. This results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless it is certain that rollover will not occur, software is required to detect the possible time rollover by reading multiple times such that the read time bytes can be adjusted accordingly if needed. 5.20.7.4 Format of Host Notify Command The ICH10 tracks and responds to the standard Host Notify command as specified in the System Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed to 0001000b. If the ICH10 already has data for a previouslyreceived host notify command which has not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address byte of the protocol. This allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary reads of the address and data registers. Table 5-56 shows the Host Notify format. Table 5-56. Host Notify Format Bit 1 8:2 9 10 Start SMB Host Address — 7 bits Write ACK (or NACK) Description Driven By External Master External Master External Master Intel® ICH10 Always 0001_000 Always 0 ICH10 NACKs if HOST_NOTIFY_STS is 1 Indicates the address of the master; loaded into the Notify Device Address Register 7-bit-only address; this bit is inserted to complete the byte Comment 17:11 Device Address – 7 bits External Master 18 19 27:20 28 36:29 37 38 Unused — Always 0 ACK Data Byte Low — 8 bits ACK Data Byte High — 8 bits ACK Stop External Master ICH10 External Master ICH10 External Master ICH10 External Master Loaded into the Notify Data Low Byte Register Loaded into the Notify Data High Byte Register Datasheet 227 Functional Description 5.21 Intel® High Definition Audio Overview The ICH10’s High Definition Audio (HDA) controller communicates with the external codec(s) over the Intel High Definition Audio serial link. The controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and an external codec(s). The ICH10 implements four output DMA engines and 4 input DMA engines. The output DMA engines move digital data from system memory to a D-A converter in a codec. ICH10 implements a single Serial Data Output signal (HDA_SDOUT) that is connected to all external codecs. The input DMA engines move digital data from the A-D converter in the codec to system memory. The ICH10 implements four Serial Digital Input signals (HDA_SDI[3:0]) supporting up to four codecs. Audio software renders outbound and processes inbound data to/from buffers in system memory. The location of individual buffers is described by a Buffer Descriptor List (BDL) that is fetched and processed by the controller. The data in the buffers is arranged in a predefined format. The output DMA engines fetch the digital data from memory and reformat it based on the programmed sample rate, bit/sample and number of channels. The data from the output DMA engines is then combined and serially sent to the external codecs over the Intel High Definition Audio link. The input DMA engines receive data from the codecs over the Intel High Definition Audio link and format the data based on the programmable attributes for that stream. The data is then written to memory in the predefined format for software to process. Each DMA engine moves one stream of data. A single codec can accept or generate multiple streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can accept the same output stream processed by a single DMA engine. Codec commands and responses are also transported to and from the codecs using DMA engines. 5.22 Intel® Active Management Technology (Intel® AMT) (Corporate Only) Intel Active Management Technology is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research. Reducing the Total Cost of Ownership (TCO) through improved asset tracking, remote manageability, and fewer desk-side visits were identified as key IT priorities. Intel AMT extends the capabilities of existing management solutions by making the asset information, remote diagnostics, recovery and contain capabilities always available, or Out of Band (OOB), even when the system is in a low-power “off” state or the OS is hung. Another feature of Intel AMT is System Defense. System Defense is used to stop the propagation of worms and viruses. Programmable packet filters in the integrated LAN Controller are used to accomplish this. These filters inspect all incoming and all outgoing packets and decide whether to block or pass the packets as configured. There is no indication to the host that a packet has been blocked or accepted. The logic can be used to accept or block reception to host or transmission to network paths. Additionally, counter logic can be used to count the number or filter matches for a given filter. This feature allows for statistical sampling of connections as well as rate limiting of connections. 228 Datasheet Functional Description 5.22.1 Intel® AMT Features • E-Asset Tag • OOB HW and SW Inventory Logs • OOB Alerts • IDE Redirect • Serial over LAN for Remote Control • Remote Diagnostics Execution • OS Lock-Up Alert • OS Repair • Remote BIOS Recovery and Update 5.22.2 Intel® AMT Requirements Intel AMT is a platform-level solution that utilizes multiple system components including: • Intel AMT-Ready ICH10 SKU • Intel Gigabit Ethernet PHY (Intel® 82567 Gigabit Platform LAN Connect device) with Intel Active Management Technology for remote access • SPI flash memory with 4KB or 8KB sector erase that meets requirements set in Section 5.23.4 (32 Mb minimum for Intel AMT) to store asset information, management software code, and logs • BIOS to provide asset detection and POST diagnostics (BIOS and Intel AMT can optionally share same flash memory device) • Familiar ISV software packages to take advantage of Intel AMT’s platform management capabilities 5.23 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost alternative for system flash versus the Firmware Hub on the LPC bus. The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In (MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select (SPI_CS[1:0]#). The ICH10 supports up to two SPI flash devices using two separate Chip Select pins. Each SPI flash device can be up to 16 MBytes. The ICH10 SPI interface supports 20 MHz and 33 MHz SPI devices. Communication on the SPI bus is done with a Master – Slave protocol. The Slave is connected to the ICH10 and is implemented as a tri-state bus. Note: If option 11 LPC is selected BIOS may still be placed on LPC, but all platforms with ICH10 (Corporate Only) require SPI flash connected directly to the ICH's SPI bus with a valid descriptor in order to boot. When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected by the ICH10, LPC based BIOS flash is disabled. Note: Datasheet 229 Functional Description 5.23.1 SPI Supported Feature Overview SPI Flash on the ICH10 has two operational modes, descriptor and non-descriptor. 5.23.1.1 Non-Descriptor Mode Non-descriptor mode is similar to the flash functionality of ICH7. In this mode, SPI Flash can only be used for BIOS. Direct read and writes are not supported. BIOS has read/write access only through register accesses. Through those register accesses BIOS can read and write to the entire flash without security checking. There is also no support for the integrated Gigabit Ethernet, Intel Management Engine, chipset soft straps, as well multiple SPI Flash components. 5.23.1.2 Descriptor Mode Descriptor Mode enables many new features of the chipset: • Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software • Intel Active Management Technology • Intel Quiet System Technology • Supports two SPI Flash components using two separate chip select pins • Hardware enforced security restricting master accesses to different regions • Chipset Soft Strap region provides the ability to use Flash NVM as an alternative to hardware pull-up/pull-down resistors for both ICH and (G)MCH • Supports the SPI Fast Read instruction and frequencies of 33 MHz • Uses standardized Flash Instruction Set 5.23.1.2.1 SPI Flash Regions In Descriptor Mode the Flash is divided into five separate regions: Region 0 1 2 3 4 Content Flash Descriptor BIOS Intel Management Engine Gigabit Ethernet Platform Data Only three masters can access the four regions: Host processor running BIOS code, Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and Intel Management Engine. The only required region is Region 0, the Flash Descriptor. Region 0 must be located in the first sector of device 0 (offset 0). Flash Region Sizes SPI flash space requirements differ by platform and configuration. The Flash Descriptor requires one 4 KB or larger block. GbE requires two 4 KB or larger blocks. The Platform Data Region is 32 KB. The amount of flash space consumed is dependent on the erase granularity of the flash part and the platform requirements for the Intel ME and BIOS regions. The Intel ME region will contain firmware to support Intel Quiet System Technology, Intel Active Management Technology, ASF 2.0 and Intel Trusted Platform Module. 230 Datasheet Functional Description Table 5-57. Region Size versus Erase Granularity of Flash Components Region Descriptor GbE Platform Data Region BIOS Intel ME Size with 4 KB Blocks 4 KB 8 KB 32 KB Varies by Platform Varies by Platform Size with 64 KB Blocks 64 KB 128 KB Not Supported Varies by Platform Varies by Platform 5.23.1.3 Device Partitioning The ICH10 SPI Flash controller supports two sets of attributes in SPI flash space. This allows for supporting an asymmetric flash component that has two separate sets of attributes in the upper and lower part of the memory array. An example of this is a flash part that has different erase granularities in two different parts of the memory array. This allows for the usage of two separate flash vendors if using two different flash parts. Figure 5-16. Flash Partition Boundary U p r F sh p e la Pr a titio n … F shP r la a titio n Bu dr o n ay L wr oe F sh la Pr a titio n … Datasheet 231 Functional Description 5.23.2 Flash Descriptor The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the first block. The flash descriptor requires its own block at the bottom of memory (0x00h). The information stored in the Flash Descriptor can only be written during the manufacturing process as its read/write permissions must be set to Read only when the computer leaves the manufacturing floor. The Flash Descriptor is made up of eleven sections: Figure 5-17. Flash Descriptor Sections 4KB OEM Section Descriptor Upper MAP Management Engine VSCC Table Reserved MCH Soft Straps ICH Soft Straps Master Region Component Descriptor MAP Signature 0 1. The Flash signature selects Descriptor Mode as well as verifies if the flash is programmed and functioning. The data at the bottom of the flash (offset 0) must be 0FF0A55Ah in order to be in Descriptor mode. 2. The Descriptor map has pointers to the other five descriptor sections as well as the size of each. 232 Datasheet Functional Description 3. The component section has information about the SPI flash in the system including: the number of components, density of each, invalid instructions (such as chip erase), and frequencies for read, fast read and write/erase instructions. 4. The Region section points to the three other regions as well as the size of each region. 5. The master region contains the security settings for the flash, granting read/write permissions for each region and identifying each master by a requestor ID. See Section 5.23.2.1 for more information. 6 & 7. The (G)MCH and ICH chipset soft strap sections contain (G)MCH and ICH configurable parameters. 8. The Reserved region between the top of the (G)MCH strap section and the bottom of the OEM Section is reserved for future chipset usages. 9. The Descriptor Upper MAP determines the length and base address of the Intel Management Engine VSCC Table. 10. The Intel Management Engine VSCC Table holds the JEDEC ID and the VSCC information of the entire SPI Flash supported by the NVM image. 11. OEM Section is 256 Bytes reserved at the top of the Flash Descriptor for use by OEM. 5.23.2.1 Descriptor Master Region The master region defines read and write access setting for each region of the SPI device. The master region recognizes three masters: BIOS, Gigabit Ethernet, and Intel Management Engine. Each master is only allowed to do direct reads of its primary regions. Table 5-58. Region Access Control Table Master Read/Write Access Region Descriptor BIOS CPU and BIOS N/A CPU and BIOS can always read from and write to BIOS Region Read / Write Intel ME/(G)MCH N/A Read / Write Intel ME can always read from and write to Intel ME Region Read / Write N/A GbE Controller N/A Read / Write Intel Management Engine Read / Write GbE software can always read from and write to GbE region N/A Gigabit Ethernet Platform Data Region Read / Write N/A Datasheet 233 Functional Description 5.23.3 Flash Access There are two types of flash accesses: Direct Access: • Masters are allowed to do direct read only of their primary region — Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet controller. Gigabit Ethernet software must use Program Registers to access the Gigabit Ethernet region. • Master's Host or Intel Management Engine virtual read address is converted into the SPI Flash Linear Address (FLA) using the Flash Descriptor Region Base/Limit registers Program Register Access: • Program Register Accesses are not allowed to cross a 4 KB boundary and can not issue a command that might extend across two components • Software programs the FLA corresponding to the region desired — Software must read the devices Primary Region Base/Limit address to create a FLA. 5.23.3.1 Direct Access Security • Requester ID of the device must match that of the primary Requester ID in the Master Section • Calculated Flash Linear Address must fall between primary region base/limit • Direct Write not allowed • Direct Read Cache contents are reset to 0s on a read from a different master — Supports the same cache flush mechanism in the ICH7, which includes Program Register Writes 5.23.3.2 Register Access Security • Only primary region masters can access the registers Note: Processor running Gigabit Ethernet software can access Gigabit Ethernet registers • Masters are only allowed to read or write those regions they have read/write permission • Using the Flash Region Access Permissions, one master can give another master read/write permissions to their area • Using the five Protected Range registers, each master can add separate read/write protection above that granted in the Flash Descriptor for their own accesses — Example: BIOS may want to protect different regions of BIOS from being erased — Ranges can extend across region boundaries 234 Datasheet Functional Description 5.23.4 Serial Flash Device Compatibility Requirements A variety of serial flash devices exist in the market. For a serial flash device to be compatible with the Intel ICH10 SPI bus, it must meet the minimum requirements detailed in the following sections. 5.23.4.1 Intel® ICH10 SPI Based BIOS Requirements A serial flash device must meet the following minimum requirements when used explicitly for system BIOS storage. • Erase size capability of at least one of the following: 64 KB, 8 KB, 4 KB, or 256 bytes. • Device must support multiple writes to a page without requiring a preceding erase cycle (Refer to Section 5.23.5) • Serial flash device must ignore the upper address bits such that an address of FFFFFFh aliases to the top of the flash memory. • SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising edge of the clock). • If the device receives a command that is not supported or incomplete (less than 8 bits), the device must complete the cycle gracefully without any impact on the flash content. • An erase command (page, sector, block, chip, etc.) must set all bits inside the designated area (page, sector, block, chip, etc.) to 1 (Fh). • Status Register bit 0 must be set to 1 when a write, erase or write to status register is in progress and cleared to 0 when a write or erase is NOT in progress. • Devices requiring the Write Enable command mst automatically clear the Write Enable Latch at the end of Data Program instructions. • Byte write must be supported. The flexibility to perform a write between 1 byte to 64 bytes is recommended. • Hardware Sequencing requirements are optional in BIOS only platforms. • SPI flash parts that do not meet Hardware sequencing command set requirements may work in BIOS only platforms via software sequencing. 5.23.4.2 Integrated LAN Firmware SPI Flash Requirements A serial flash device that will be used for system BIOS and Integrated LAN or Integrated LAN only must meet all the SPI Based BIOS Requirements plus: • Hardware sequencing • 4, 8 or 64 KBytes erase capability must be supported. 5.23.4.2.1 SPI Flash Unlocking Requirements for Integrated LAN BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE region. GbE firmware and drivers for the integrated LAN need to be able to read, write and erase the GbE region at all times. 5.23.4.3 Intel® Management Engine Firmware SPI Flash Requirements Intel Management Engine Firmware must meet the SPI flash based BIOS Requirements plus: • Hardware Sequencing. • Flash part must be uniform 4 KB erasable block throughout the entire device. • Write protection scheme must meet SPI flash unlocking requirements for Intel Management Engine. Datasheet 235 Functional Description 5.23.4.3.1 SPI Flash Unlocking Requirements for Intel Management Engine Flash devices must be globally unlocked (read, write and erase access on the Intel ME region) from power on by writing 00h to the flash’s status register to disable write protection. If the status register must be unprotected, it must use the enable write status register command 50h or write enable 06h. Opcode 01h (write to status register) must then be used to write a single byte of 00h into the status register. This must unlock the entire part. If the SPI flash’s status register has non-volatile bits that must be written to, bits [5:2] of the flash’s status register must be all 0h to indicate that the flash is unlocked. If there is no need to execute a write enable on the status register, then opcodes 06h and 50h must be ignored. After global unlock, BIOS has the ability to lock down small sections of the flash as long as they do not involve the Intel ME or GbE region. 5.23.4.4 Hardware Sequencing Requirements Table 5-59 contains a list of commands and the associated opcodes that a SPI-based serial flash device must support in order to be compatible with hardware sequencing. Table 5-59. Hardware Sequencing Commands and Opcode Requirements Commands Write to Status Register Opcode 01h Notes Writes a byte to SPI flash’s status register. Enable Write to Status Register command must be run prior to this command. Single byte or 64 byte write as determined by flash part capabilities and software. Program Data Read Data Write Disable Read Status Write Enable Fast Read Enable Write to Status Register Erase Full Chip Erase JEDEC ID 02h 03h 04h 05h 06h 0Bh 50h or 60h Program mable C7h 9Fh Outputs contents of SPI flash’s status register Enables a bit in the status register to allow an update to the status register 256B, 4 Kbyte, 8 Kbyte or 64 Kbyte See Section . 5.23.4.4.1 JEDEC ID Since each serial flash device may have unique capabilities and commands, the JEDEC ID is the necessary mechanism for identifying the device so the uniqueness of the device can be comprehended by the controller (master). The JEDEC ID uses the opcode 9Fh and a specified implementation and usage model. This JEDEC Standard Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV. 236 Datasheet Functional Description 5.23.5 Multiple Page Write Usage Model The system BIOS and Intel Active Management Technology firmware usage models require that the serial flash device support multiple writes to a page (minimum of 512 writes) without requiring a preceding erase command. BIOS commonly uses capabilities such as counters that are used for error logging and system boot progress logging. These counters are typically implemented by using byte-writes to ‘increment’ the bits within a page that have been designated as the counter. The Intel AMT firmware usage model requires the capability for multiple data updates within any given page. These data updates occur via byte-writes without executing a preceding erase to the given page. Both the BIOS and Intel AMT firmware multiple page write usage models apply to sequential and non-sequential data writes. Note: This usage model requirement is based on any given bit only being written once from a 1-to-0 without requiring the preceding erase. An erase would be required to change bits back to the 1 state. 5.23.5.1 Soft Flash Protection There are two types of flash protection that are not defined in the flash descriptor supported by ICH10: 1. BIOS Range Write Protection 2. SMI#-Based Global Write Protection Both mechanisms are logically OR’d together such that if any of the mechanisms indicate that the access should be blocked, then it is blocked. Table 5-60 provides a summary of the mechanisms. Table 5-60. Flash Protection Mechanism Summary Mechanism BIOS Range Write Protection Write Protect Accesses Blocked Range Specific? Reset-Override or SMI#Override? Reset Override Equivalent Function on FWH Writes Yes FWH Sector Protection Same as Write Protect in previous ICHs for FWH Writes No SMI# Override A blocked command will appear to software to finish, except that the Blocked Access status bit is set in this case. 5.23.5.2 BIOS Range Write Protection The ICH10 provides a method for blocking writes to specific ranges in the SPI flash when the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type information (which can be locked down by the initial Boot BIOS) and the address of the requested command against the base and limit fields of a Write Protected BIOS range. Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism remains in place until the next system reset. Datasheet 237 Functional Description 5.23.5.3 SMI# Based Global Write Protection The ICH provides a method for blocking writes to the SPI flash when the Write Protected bit is cleared (i.e., protected). This is achieved by checking the Opcode type information (which can be locked down by the initial Boot BIOS) of the requested command. The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as they do for the FWH BIOS. 5.23.6 Flash Device Configurations The ICH10-based platform may use the serial flash in multiple configurations. The following table focuses on the supported configurations involving the ICH10 and Intel Active Management Technology. Configuration 1 2 3 4 System BIOS Storage SPI Non-SPI SPI Non-SPI Intel® ICH10 Firmware No Yes Yes No Minimum Number of SPI Device(s) 1 1 1 0 Note: Note: When SPI is selected for BIOS and a SPI device is detected by the ICH10, LPC based BIOS flash is disabled. Firmware includes Intel Active Management Technology, ASF, Intel Quiet System Technology and Gigabit Ethernet. 5.23.7 SPI Flash Device Recommended Pinout The table below contains the recommended serial flash device pin-out for an 8-pin device. Use of the recommended pin-out on an 8-pin device reduces complexities involved with designing the serial flash device onto a motherboard and allows for support of a common footprint usage model (refer to Section 5.23.8.1). Table 5-61. Recommended Pinout for 8-Pin Serial Flash Device Pin # 1 2 3 4 5 6 7 8 Signal Chips Select Data Output Write Protect Ground Data Input Serial Clock Hold / Reset Supply Voltage Although an 8-pin device is preferred over a 16-pin device due to footprint compatibility, the following table contains the recommended serial flash device pin-out for a 16-pin SOIC. 238 Datasheet Functional Description 5.23.8 Serial Flash Device Package Table 5-62. Recommended Pinout for 16-Pin Serial Flash Device Pin # 1 2 3 4 5 6 7 8 Signal Hold / Reset Supply Voltage No Connect No Connect No Connect No Connect Chip Select Serial Data Out Pin # 9 10 11 12 13 14 15 16 Signal Write Protect Ground No Connect No Connect No Connect No Connect Serial Data In Serial Clock 5.23.8.1 Common Footprint Usage Model To minimize platform motherboard redesign and to enable platform Bill of Material (BOM) selectability, many PC System OEM’s design their motherboard with a single common footprint. This common footprint allows population of a soldered down device or a socket that accepts a leadless device. This enables the board manufacturer to support, via selection of the appropriate BOM, either of these solutions on the same system without requiring any board redesign. The common footprint usage model is desirable during system debug and by flash content developers since the leadless device can be easily removed and reprogrammed without damage to device leads. When the board and flash content is mature for highvolume production, both the socketed leadless solution and the soldered down leaded solution are available through BOM selection. 5.23.8.2 Serial Flash Device Package Recommendations It is highly recommended that the common footprint usage model be supported. An example of how this can be accomplished is as follows: • The recommended pinout for 8-pin serial flash devices is used (refer to Section 5.23.7). • The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket that is land pattern compatible with the wide body SO8 package. • The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8 (200 mil) packages. The 16-pin device is supported in the SO16 (300 mil) package. Datasheet 239 Functional Description 5.24 Intel® Quiet System Technology (Intel® QST) The ICH10 implements three PWM and 4 TACH signals for Intel Quiet System Technology (QST). Note: Intel Quiet System Technology functionality requires a correctly configured system, including an appropriate (G)MCH with Intel ME, Intel ME Firmware, and system BIOS support. 5.24.1 PWM Outputs This signal is driven as open-drain. An external pull-up resistor is integrated into the fan to provide the rising edge of the PWM output signal. The PWM output is driven low during reset, which represents 0% duty cycle to the fans. After reset de-assertion, the PWM output will continue to be driven low until one of the following occurs: • The internal PWM control register is programmed to a non-zero value by the Intel QST firmware. • The watchdog timer expires (enabled and set at 4 seconds by default). • The polarity of the signal is inverted by the Intel QST firmware. Note that if a PWM output will be programmed to inverted polarity for a particular fan, then the low voltage driven during reset represents 100% duty cycle to the fan. 5.24.2 TACH Inputs This signal is driven as an open-collector or open-drain output from the fan. An external pull-up is expected to be implemented on the motherboard to provide the rising edge of the TACH input. This signal has analog hysteresis and digital filtering due to the potentially slow rise and fall times. This signal has a weak internal pull-up resistor to keep the input buffer from floating if the TACH input is not connected to a fan. 5.25 Thermal Sensors ICH10 integrates two thermal sensors that monitor the temperature within its die. The thermal sensors are used for Intel Quiet System Technology (Intel QST). The Intel QST firmware can internally access the temperature measured by the sensors and use the data as a factor to determine how to control the fans. The ICH10 thermal sensors also provide the capability to protect the ICH10 under a catastrophic thermal situation. When the sensors are enabled and correctly programmed by the system BIOS, the ICH10 will shut down the system when the ICH10 thermal limit is reached. Refer to the Thermal Memory Mapped Configuration Registers Section 23.2 for more info on the catastrophic settings. 240 Datasheet Functional Description 5.26 Feature Capability Mechanism A set of registers is included in the ICH10 LPC Interface (Device 31, Function 0, offset E0h - EBh) that allows the system software or BIOS to easily determine the features supported by ICH10. These registers can be accessed through LPC PCI configuration space, thus allowing for convenient single point access mechanism for chipset feature detection. This set of registers consists of: Capability ID (FDCAP) Capability Length (FDLEN) Capability Version and Vendor-Specific Capability ID (FDVER) Feature Vector (FVECT) 5.27 Integrated Trusted Platform Module (Corporate Only) The integrated Trusted Platform Module (TPM) implementation consists of firmware, Intel Management Engine resources and dedicated hardware within the ICH and the (G)MCH. The integrated TPM supports all requirements of the TPM Specification Version 1.2, Level 2 Revision 103, as published by the Trusted Computing Group. Note: Integrated TPM functionality requires a correctly configured system, including an appropriate (G)MCH with Intel Management Engine firmware, ICH10 and SPI Flash. 5.27.1 Integrated TPM Hardware Requirements The following hardware components are required for TPM 1.2 functionality: 1. SPI Flash Memory: The SPI flash component connected to the ICH (SPI interface) provides non-volatile storage requirement for the integrated TPM. It contains the FW code which is loaded by the Intel Management Engine upon power on. 2. Monotonic Counters: The ICH10 contains four TPM 1.2 compliant monotonic counters that reside in the RTC well which maintains values programmed by the integrated TPM across power cycles. The counters are only incremented by TPM software (host or Intel ME) and are not controlled by the ICH hardware. 3. Physical Presence: Physical presence indication is required in order to enable certain TPM commands. These commands are generally used to bypass owner authorized commands when the authorization data is unavailable or to set the integrated TPM to a non-owner state. The Intel Management Engine Firmware uses the TPM_PP pin on the ICH10 to indicate Physical Presence to the platform when pulled high. In addition, Physical Presence flags can be set to force Physical Presence by firmware. 4. Chipset: An ICH10 and (G)MCH with Intel Management Engine enabled is required for integrated TPM support. Datasheet 241 Functional Description 5.27.2 Enabling integrated TPM The integrated TPM is enabled based on the combination of a functional straps on both the ICH and the (G)MCH and a soft strap bit found in the SPI Descriptor. When the integrated TPM is enabled, Front Side Bus cycles that would otherwise propagate to the LPC bus will be routed by the Config Bus Decoder to the integrated TPM Host Decoder. Either Functional strap or the soft strap bit may be used to disable the integrated TPM. • ICH Functional Strap: The ICH10 enables Integrated TPM when SPI_MOSI is sampled high on the rising edge of CLPWROK and disabled if the SPI_MOSI signal is sampled low. See Section 2.25.1 for details. The SPI_MOSI signal requires an external pull-up resistor to enable the integrated TPM. SPI_MOSI has an integrated pull-down resistor enabled at reset only and does not require an external pull-down resistor to disable integrated TPM. • Soft Strap: The integrated TPM Disable bit (bit 2) in the (G)MCHSTRP0 register (FSMBA + 0h) within the flash descriptor can act as an override to the functional straps on both the ICH and (G)MCH. When set, the integrated TPM will be disabled regardless of the values of the functional straps on the ICH and/or (G)MCH. This bit along with both functional straps must be appropriately configured to enable integrated TPM. • (G)MCH Functional Strap: For (G)MCH functional strap information, consult the appropriate (G)MCH documentation. §§ 242 Datasheet Ballout Definition 6 6.1 Ballout Definition This chapter contains the Intel® ICH10 ballout information. Intel® ICH10 Ballout This section contains the ICH10 ballout. Figure 6-1 and Figure 6-2 show the ballout from a top of the package view. Table 6-1 is the BGA ball list, sorted alphabetically by signal name. Note: Notes for Figure 6-1, Figure 6-2, and Table 6-1 1. § symbol indicates a particular use of a pin is Cunsumer Only. 2. † symbol indicates a particular use of a pin is Corporate Only. Datasheet 243 Ballout Definition Figure 6-1. 1 Intel® ICH10 Ballout (Top view–Left Side) 2 3 4 5 6 7 8 9 GPIO14 / 10 11 12 13 14 15 A Vss Vcc3_3 PIRQD# AD11 AD4 V5REF GNT1# / GPIO51 GPIO12 JTAGDI / VccLAN1_1 QST_BMBU SY# † GPIO27 VccLAN3_3 SLP_S3# GPIO24 / MEM_LED SMLINK0 A § B Vcc3_3 Vss PCICLK AD9 Vss AD8 AD7 Vss Vcc3_3 VccLAN1_1 Vss VccLAN3_3 SLP_S4# Vss SMLINK1 B C AD24 AD25 AD26 C/BE2# AD14 DEVSEL# GNT2# / GPIO53 AD1 AD3 AD0 GPIO57 / S4_STATE# TPM_PP / GPIO72† / / GPIO26 † TP0 JTAGTCK PLTRST# STP_PCI# / GPIO15 C D E AD27 PIRQB# AD15 Vss PIRQG# / GPIO4 PIRQH# / GPIO5 Vss AD21 PAR AD16 TRDY# AD10 GNT3# / GPIO55 AD17 C/BE3# AD2 AD6 AD18 AD5 LAN_RSTS LAN_RXD2 YNC REQ2# / GPIO52 REQ1# / GPIO50 Vss Vss D E F PIRQC# AD29 PERR# Vss AD13 REQ3# / GPIO54 PLOCK# Vss STOP# C/BE0# Vss LAN_TXD1 LAN_TXD0 F G AD30 FWH1 / LAD1 FWH3 / LAD3 GPIO18 SATACLKR EQ# / GPIO35 OC7# / GPIO31 OC5# / GPIO29 OC11# / GPIO47 Vcc3_3 AD23 AD20 C/BE1# AD19 Vcc3_3 FRAME# LAN_TXD2 LAN_RXD0 G H AD31 LDRQ1# / GPIO23 FWH0 / LAD0 GNT0# AD22 Vcc3_3 Vss Vcc1_5_A Vcc1_5_A AD12 LAN_RXD1 VccSus3_3 H J Vcc3_3 PIRQA# Vss PIRQE# / GPIO2 AD28 IRDY# J K GPIO32 SERR# REQ0# Vcc3_3 K L Vss RCIN# FWH4 / LFRAME# LDRQ0# PIRQF# / GPIO3 FWH2 / LAD2 GPIO0 / BMBUSY# OC2# / GPIO41 Vcc3_3 L M GPIO16 / INIT3_3V# DPRSLPVR OC4# / GPIO43 Vss OC1# / GPIO40 OC8# / GPIO44 CLK14 OC6# / GPIO30 OC0# / GPIO59 SUSCLK / Vss Vss Vcc1_1 Vcc1_1 Vss Vcc1_1 M N SERIRQ SPKR Vcc1_1 Vss Vss Vss N P Vss A20GATE Vss Vss Vss Vss P R SUS_STAT# / LPCPD / PCIRST# † GPIO61 PME# GPIO62 † OC9# / GPIO45 OC3# / GPIO42 OC10# / GPIO46 Vss Vcc1_1 Vss Vss Vss R T U V W Y AA AB AC AD Vcc1_5_A Vss PWRBTN# Vss CLPWROK CK_PWRG D Vss Vcc1_1 Vcc1_1 Vcc1_1 Vss Vss Vss Vcc1_1 Vss Vss Vss Vss Vss Vss Vss Vcc1_1 T U V W Y AA AB VccSus3_3 VccSus3_3 VccSus3_3 USBP11N Vss USBP8N Vss USBP5N Vss USBP2N USBP11P USBP10N USBP8P USBP7P USBP5P USBP4P USBP2P Vss USBP10P Vss USBP7N Vss USBP4N Vss VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 USBP9P Vss USBP6P Vss USBP3P Vss USBP0P USBP9N Vss USBP6N Vss USBP3N Vss USBP0N Vss VccSus3_3 VccSus3_3 VccSus3_3 Vss Vcc1_5_A Vcc1_5_A VccSus1_1 Vss VccSus3_3 Vcc1_5_A Vcc1_5_A Vss VccSus1_5 VccSusHDA Vss VccHDA Vcc3_3 Vcc1_5_A Vcc1_5_A Vss Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vss Vcc1_5_A Vss AC AD AE AF AG Vss USBP1P USBP1N Vss CLK48 HDA_BIT_C HDA_SDIN1 LK Vss Vss GPIO20 Vss GPIO33 SATALED# Vss Vss SATA5TXN Vss Vss Vss SATA4TXN Vcc1_5_A Vcc1_5_A Vss SATA3TXN Vss Vss Vss SATA2TXP Vss Vss AE AF AG V5REF_Sus VccSus3_3 USBRBIAS# USBRBIAS AH HDA_SDIN2 Vss GPIO34 Vss SATA5TXP Vss SATA4TXP Vcc1_5_A Vcc1_5_A SATA3TXP Vss SATA2TXN Vss AH AJ HDA_SDOU HDA_RST# HDA_SDIN3 T HDA_SYNC 1 Vss 2 HDA_SDIN0 3 Vss SATARBIAS SATA5RXN SATARBIAS SATA5RXP # 6 7 Vss SATA4RXN Vcc1_5_A SATA3RXN Vss SATA2RXN Vss SATA1RXN AJ AK Vcc3_3 4 VccUSBPLL 5 Vss 8 SATA4RXP 9 Vcc1_5_A 10 SATA3RXP 11 Vss 12 SATA2RXP 13 Vss 14 SATA1RXP 15 AK 244 Datasheet Ballout Definition Figure 6-2. 16 Intel® ICH10 Ballout (Top view–Right Side) 17 18 19 20 DRAMPWR 21 22 23 24 25 26 27 28 29 30 A TP6 VccSus3_3 GPIO9 GPIO13 OK / GPIO8 VccSus3_3 † RTCX1 VccRTC VccCL1_1 Vcc1_1 RTCRST# VccCL1_5 VccGLAN VccGLANPL GLAN_COM 3_3 L PO Vss A STP_CPU# / B TP7 Vss GPIO25 GPIO10 / SMBALERT# CPU_MISSI / GPIO11 / NG / † † JTAGTDO JTAGTMS † Vss RTCX2 Vss VccCL3_3 Vcc1_1 Vss SPI_MISO Vss Vss GLAN_COM VccGLAN1_ PI 5 B C TP5 SST VccSus3_3 LAN_RST# VRMPWRG VccCL3_3 D Vcc1_1 PWROK SPI_MOSI CL_VREF VccGLAN1_ VccGLAN1_ VccGLAN1_ 0 5 5 5 C D LAN100_SL P PETn6 / GLAN_TXN Vss PETp6 / GLAN_TXP PERn6 / PERp6 / GLAN_RXN GLAN_RXP Vss Vss D E SMBDATA VccSus3_3 Vss TP4 WAKE# Vss INTVRMEN Vcc1_1 SPI_CS0# E F GPIO56 SLP_M# LINKALERT# / GPIO60 / SYS_RESE T# † JTAGRST# GPIO28 RI# TP3 Vss RSMRST# SPI_CS1# Vcc1_1 GLAN_CLK Vss Vss PERp5 PERn5 F SLP_S5# / G Vss GPIO63 H J SMBCLK † CL_RST0# INTRUDER# CL_CLK0 SPI_CLK Vcc1_1 Vss PETn5 PETp5 Vss Vss G VccSus1_1 VccSus1_5 Vss SRTCRST# CL_DATA0 Vss Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_5_B Vss Vcc1_5_B Vss PETn4 Vss PETp4 PERp4 Vss PERn4 Vss H J K Vcc1_5_B Vcc1_5_B Vcc1_5_B Vss Vss PERp3 PERn3 K L Vss Vcc1_5_B Vcc1_5_B PETn3 PETp3 Vss Vss L M Vss Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_5_B Vcc1_5_B Vcc1_5_B Vss Vss PERp2 PERn2 M N Vss Vss Vss Vcc1_1 Vss Vcc1_5_B Vcc1_5_B PETn2 PETp2 Vss Vss N P Vss Vss Vss Vss Vcc1_5_B Vcc1_5_B Vcc1_5_B Vss Vss PERp1 PERn1 P R T U V W Y AA AB AC AD Vss Vss Vss Vss Vss Vss Vss Vss Vss Vcc1_1 Vss Vss Vss Vss Vcc1_1 Vcc1_1 Vss Vcc1_1 Vcc1_1 Vcc1_1 Vss Vcc1_5_B Vss Vcc1_5_B Vss Vcc1_5_B Vcc1_5_B Vcc1_5_A Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vss Vcc1_5_B Vcc1_5_B DMI_CLKP Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B PETn1 Vcc1_5_B DMI_CLKN Vss DMI0RXP Vss DMI1RXN Vss DMI2RXN Vcc1_5_B PETp1 Vcc1_5_B Vcc1_5_B Vss DMI0RXN Vss DMI1RXP Vss DMI2RXP Vcc1_5_B Vss Vss Vcc1_5_B DMI0TXP Vss DMI1TXP Vss DMI2TXP Vss DMI3TXN Vss VccDMIPLL Vcc1_5_B DMI0TXN Vss DMI1TXN Vss DMI2TXN Vss DMI3TXP R T U V W Y AA AB AC AD Vcc1_5_A Vss Vcc1_5_A Vcc1_5_A Vcc1_5_A Vss Vcc3_3 Vss Vcc1_5_A SDATAOUT 1 / GPIO48 Vcc3_3 SATA5GP IGNNE# Vss PECI CPUPWRG THRMTRIP# D INIT# DPSLP# AE Vss Vcc1_5_A Vss Vss SATA_CLK P SATA1GP / SATA2GP / SATA3GP / GPIO19 GPIO36 GPIO37 Vss Vcc3_3 SATA4GP Vss DMI3RXP Vcc1_5_B DMI_IRCO MP Vss Vcc1_5_B Vcc1_5_B DMI_ZCOM P VccDMI Vcc3_3 AE AF AG AH SATA1TXP Vcc1_5_A SATA_CLKN Vss NMI Vss DMI3RXN Vss VccDMI Vss AF AG AH SATA1TXN Vcc1_5_A Vcc1_5_A Vss Vss TACH0 / GPIO17 PWM0 TACH1 / GPIO1 21 TACH2 / GPIO6 PWM1 SDATAOUT 0 / GPIO39 Vss TACH3 / GPIO7 23 Vcc3_3 SCLOCK / GPIO22 SLOAD / GPIO38 24 MCH_SYNC# SMI# INTR V_CPU_IO AJ Vss SATA0RXP Vcc1_5_A SATA0TXP Vss VccSATAPL L 20 GPIO49 SATA0GP / GPIO21 25 Vss FERR# A20M# STPCLK# V_CPU_IO AJ AK Vss 16 SATA0RXN 17 Vcc1_5_A 18 SATA0TXN 19 PWM2 22 THRM# 26 Vss 27 DPRSTP# 28 Vss 29 Vss 30 AK Datasheet 245 Ballout Definition Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name A20GATE A20M# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# CK_PWRGD Ball # P8 AJ28 C10 C8 E9 C9 A5 E12 E10 B7 B6 B4 E7 A4 H12 F8 C5 D2 E5 G7 E11 G10 G6 D3 H6 G5 C1 C2 C3 D1 J7 F3 G1 H3 F11 G9 C4 E8 T8 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name CL_CLK0 CL_DATA0 CL_RST0# CL_VREF0 CLK14 CLK48 CLPWROK CPUPWRGD DEVSEL# DMI_CLKN DMI_CLKP DMI_IRCOMP DMI_ZCOMP DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DRAMPWROK† / GPIO8 FERR# FRAME# FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 FWH4 / LFRAME# GLAN_CLK Ball # G22 H21 G20 C27 M5 AG3 T6 AD23 C6 U26 U25 AF28 AF30 W28 W26 V30 V29 AA26 AA28 Y30 Y29 AC26 AC28 AB30 AB29 AF26 AE26 AD29 AD30 A20 AJ27 G12 K3 H1 M7 J1 L5 F25 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name GLAN_COMPI GLAN_COMPO GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 GPIO0 GPIO10 / CPU_MISSING / JTAGTMS† GPIO12 GPIO13 GPIO14 / JTAGTDI† / QST_BMBUSY#§ GPIO16 / DPRSLPVR GPIO18 GPIO20 GPIO24 GPIO27 GPIO28 GPIO32 GPIO33 GPIO34 GPIO49 GPIO56 GPIO57 / TPM_PP / JTAGTCK† GPIO72† / TP0 GPIO9 HDA_BIT_CLK HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT HDA_SYNC IGNNE# INIT# INIT3_3V# Ball # B29 A29 H5 A7 C7 F7 N7 C17 A8 A19 A9 M2 K1 AF5 A14 A11 G18 K2 AF6 AH5 AJ25 F16 C12 C13 A18 AH3 AJ1 AK3 AH4 AH1 AJ3 AJ2 AK1 AC22 AE23 M3 246 Datasheet Ballout Definition Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name INTR INTRUDER# INTVRMEN IRDY# LAN_RST# LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LAN100_SLP LDRQ0# LDRQ1# / GPIO23 LINKALERT# / GPIO60 / JTAGRST#† MCH_SYNC# NMI OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31 OC8# / GPIO44 OC9# / GPIO45 OC10# / GPIO46 OC11# / GPIO47 PAR PCICLK PCIRST# PECI PERn1 PERn2 PERn3 PERn4 Ball # AH27 G21 E23 J8 C21 E14 G15 H14 E13 F15 F14 G14 E21 L6 J3 F18 AH25 AF24 P5 N3 P7 R7 N2 N1 N5 M1 P3 R6 T7 P1 E3 B3 R2 AC23 P30 M30 K30 H30 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name PERn5 PERn6 / GLAN_RXN PERp1 PERp2 PERp3 PERp4 PERp5 PERp6 / GLAN_RXP PERR# PETn1 PETn2 PETn3 PETn4 PETn5 PETn6 / GLAN_TXN PETp1 PETp2 PETp3 PETp4 PETp5 PETp6 / GLAN_TXP PIRQA# PIRQB# PIRQC# PIRQD# PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 PLOCK# PLTRST# PME# PWM0 PWM1 PWM2 PWRBTN# PWROK RCIN# REQ0# Ball # F30 D29 P29 M29 K29 H29 F29 D30 F5 R26 N26 L26 J26 G26 E26 R28 N28 L28 J28 G28 E28 J5 E1 F1 A3 K6 L7 F2 G2 H8 C14 R3 AJ21 AJ22 AK22 T3 C25 L3 K7 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 RI# RSMRST# RTCRST# RTCX1 RTCX2 S4_STATE# / GPIO26 SATA_CLKN SATA_CLKP SATA0GP / GPIO21 SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1GP / GPIO19 SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2GP / GPIO36 SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3GP / GPIO37 SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4GP SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5GP SATA5RXN Ball # G13 F13 G8 G19 F22 A25 A21 B21 C11 AF18 AF19 AK25 AK17 AJ17 AK19 AJ19 AE20 AJ15 AK15 AH16 AF16 AE21 AJ13 AK13 AH14 AF14 AE22 AJ11 AK11 AF12 AH12 AF22 AJ9 AK9 AF10 AH9 AD21 AJ7 Datasheet 247 Ballout Definition Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name SATA5RXP SATA5TXN SATA5TXP SATACLKREQ# / GPIO35 SATALED# SATARBIAS SATARBIAS# SCLOCK / GPIO22 SDATAOUT0 / GPIO39 SDATAOUT1 / GPIO48 SERIRQ SERR# SLOAD / GPIO38 SLP_M# SLP_S3# SLP_S4# SLP_S5# / GPIO63 † Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name SUS_STAT# / LPCPD / GPIO61† SUSCLK / GPIO62† SYS_RESET# TACH0 / GPIO17 TACH1 / GPIO1 TACH2 / GPIO6 TACH3 / GPIO7 THRM# THRMTRIP# DPRSTP# DPSLP# TP3 TP4 TP5 TP6 TP7 TRDY# USBP0N USBP0P USBP10N USBP10P USBP11N USBP11P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N Ball # R1 R5 F19 AH21 AK21 AH22 AK23 AK26 AD24 AK28 AE24 F20 E19 C18 A16 B16 E6 AD6 AD5 W2 W3 V1 V2 AE3 AE2 AD1 AD2 AB6 AB5 AC3 AC2 AB1 AB2 Y6 Y5 AA3 AA2 Y1 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name USBP8P USBP9N USBP9P USBRBIAS USBRBIAS# V_CPU_IO V_CPU_IO V5REF V5REF_Sus Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_1 Vcc1_5_A Ball # Y2 V6 V5 AG2 AG1 AH28 AJ30 A6 AF1 A24 B24 C24 E24 F24 G24 H23 H24 J23 M12 M13 M15 M17 M18 M19 N12 N19 R12 R19 U12 U19 V12 V19 W12 W13 W15 W17 W18 W19 AA7 Ball # AK7 AF8 AH7 L1 AE7 AJ6 AK6 AJ24 AH23 AD20 N6 K5 AK24 F17 A13 B13 G17 C16 H16 E16 AH26 A15 B15 G23 E25 F23 B26 C26 N8 H20 C19 F10 B18 C15 AJ29 SMBALERT# / GPIO11 / JTAGTDO† SMBCLK SMBDATA SMI# SMLINK0 SMLINK1 SPI_CLK SPI_CS0# SPI_CS1# SPI_MISO SPI_MOSI SPKR SRTCRST# SST STOP# STP_CPU# / GPIO25† STP_PCI# / GPIO15 STPCLK# 248 Datasheet Ballout Definition Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Ball # AA8 AB7 AB8 AB23 AC11 AC13 AC14 AC15 AC16 AC17 AC18 AC20 AD11 AD12 AD13 AD17 AE11 AE17 AF11 AF17 AH10 AH11 AH17 AH18 AJ10 AJ18 AK10 AK18 H10 H11 T1 AA23 AA24 AA25 AB24 AB25 AC25 AD25 AD26 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc3_3 Ball # AD28 AE28 AE29 AE30 J24 J25 K23 K24 K25 L24 L25 M23 M24 M25 N24 N25 P23 P24 P25 R24 R25 T23 T24 T25 T26 T28 U24 U28 U29 U30 V23 V24 V25 W24 W25 Y23 Y24 Y25 AC19 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 VccCL1_1 VccCL1_5 VccCL3_3 VccCL3_3 VccDMI VccDMI VccDMIPLL VccGLAN1_5 VccGLAN1_5 VccGLAN1_5 VccGLAN1_5 VccGLAN3_3 VccGLANPLL VccHDA VccLAN1_1 VccLAN1_1 VccLAN3_3 VccLAN3_3 VccRTC VccSATAPLL VccSus1_1 VccSus1_1 VccSus1_5 VccSus1_5 Ball # AC21 AD10 AF21 AH24 AH30 AK4 A2 B1 B9 G3 G11 H7 J2 K8 L8 A23 A26 B23 C23 AG29 AG30 T30 B30 C28 C29 C30 A27 A28 AC10 A10 B10 A12 B12 A22 AK20 AC7 H17 AD8 H18 Datasheet 249 Ballout Definition Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSusHDA VccUSBPLL VRMPWRGD Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # AF2 A17 B20 C20 E17 H15 U1 U2 U3 U5 U6 U7 U8 V8 W7 W8 Y8 AC9 AK5 C22 AA1 AA5 AA6 AA29 AA30 AB3 AB26 AB28 AC1 AC5 AC6 AC8 AC12 AC24 AC29 AC30 AD3 AD7 AD9 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # AD14 AD15 AD16 AD18 AD19 AD22 AE1 AE5 AE6 AE8 AE9 AE10 AE12 AE13 AE14 AE15 AE16 AE18 AE19 AE25 AF3 AF7 AF9 AF13 AF15 AF20 AF23 AF25 AF29 AG28 AH2 AH6 AH8 AH13 AH15 AH19 AH20 AH29 AJ4 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # AJ5 AJ8 AJ12 AJ14 AJ16 AJ20 AJ23 AJ26 AK2 AK8 AK12 AK14 AK16 AK27 AK29 AK30 A1 A30 B2 B5 B8 B11 B14 B17 B19 B22 B25 B27 B28 D28 E2 E15 E18 E22 E29 E30 F6 F9 F12 250 Datasheet Ballout Definition Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # F21 F26 F28 G16 G25 G29 G30 H2 H9 H13 H19 H22 H25 H26 H28 J6 J29 J30 K26 K28 L2 L23 L29 L30 M6 M8 M14 M16 M26 M28 N13 N14 N15 N16 N17 N18 N23 N29 N30 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # P2 P6 P12 P13 P14 P15 P16 P17 P18 P19 P26 P28 R8 R13 R14 R15 R16 R17 R18 R23 R29 R30 T2 T5 T12 T13 T14 T15 T16 T17 T18 T19 T29 U13 U14 U15 U16 U17 U18 Table 6-1. Intel® ICH10 Ballout by Signal Name Ball Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss WAKE# Ball # U23 V3 V7 V13 V14 V15 V16 V17 V18 V26 V28 W1 W5 W6 W14 W16 W23 W29 W30 Y3 Y7 Y26 Y28 E20 Datasheet 251 Ballout Definition 252 Datasheet Package Information 7 7.1 Note: Figure 7-1. Package Information Intel® ICH10 Package The ICH10 package information is shown in Figure 7-1, Figure 7-2, and Figure 7-3. All dimensions, unless otherwise specified, are in millimeters. Intel® ICH10 Package (Top View) -A// 0.127 A PIN #1 I.D (SHINY) 1.0 DIA X 0.15 DEPTH 9.0 X 9.0 FROM CENTER LINE -B- 22.10 REF 0.127 A 4 X 45° TOP VIEW Datasheet 253 Package Information Figure 7-2. Intel® ICH10 Package (Bottom View) Figure 7-3. Intel® ICH10 Package (Side View) // 0.15 0.20 C -C- 3 SEATING PLANE SIDE VIEW § §§ 254 Datasheet Electrical Characteristics 8 Electrical Characteristics This chapter contains the DC and AC characteristics for the ICH10. AC timing diagrams are included. 8.1 Thermal Specifications Refer to the Intel® I/O Controller Hub (ICH10) Thermal Design Guidelines document for ICH10 thermal information. 8.2 Table 8-1. Absolute Maximum Ratings Intel® ICH10 Absolute Maximum Ratings Parameter Voltage on any 3.3 V Pin with respect to Ground Voltage on any 5 V Tolerant Pin with respect to Ground (V5REF = 5 V) 1.1 V Supply Voltage with respect to VSS 1.25 V Supply Voltage with respect to VSS 1.5 V Supply Voltage with respect to VSS 3.3 V Supply Voltage with respect to VSS 5.0 V Supply Voltage with respect to VSS V_CPU_IO Supply Voltage with respect to VSS Maximum Limits -0.5 to Vcc3_3 + 0.5 V -0.5 to V5REF + 0.5 V -0.5 to 2.1 V -0.5V to 2.1V -0.5 to 2.1 V -0.5 to 4.6 V -0.5 to 5.5 V -0.5 to 2.1 V 8.3 Table 8-2. DC Characteristics DC Current Characteristics (Consumer Only)1 Power Plane Symbol V5REF V5REF_Sus Vcc3_3 VccSus3_3 VccHDA6 VccSusHDA6 VccGLAN3_3 VccGLAN1_5 VccLAN3_35 S0 2 mA 2 mA 308 mA 212 mA 32mA 32 mA 1 mA 80 mA 19 mA Maximum Power Consumption S3 N/A 1 mA N/A 53 mA N/A 1 mA N/A N/A 78 mA S4/S5 N/A 1 mA N/A 53 mA N/A 1 mA N/A N/A 78 mA G3 N/A N/A N/A N/A N/A N/A N/A N/A N/A Datasheet 255 Electrical Characteristics Table 8-2. DC Current Characteristics (Consumer Only)1 Power Plane Symbol VccLAN1_12, 5 VccCL3_3 VccCL1_52 VccCL1_12 Vcc1_5_A Vcc1_5_B VccSus1_52 Vcc1_1 VccSus1_12 VccRTC3, 4 VccDMI 7 Maximum Power Consumption S0 Powered by Vcc1_1 in S0 19 mA Powered by Vcc1_5_A in S0 Powered by Vcc1_1 in S0 1.644 A 646 mA Powered by Vcc1_5_A in S0 1.634 A Powered by Vcc1_1 in S0 N/A 50 mA 2 mA 23 mA 11 mA 23 mA 47 mA S3 Powered by VccLAN3_3 in S3 73 mA Powered by VccCL3_3 in S3 Powered by VccCL3_3 in S3 N/A N/A Powered by VccSus3_3 in S3 N/A Powered by VccSus3_3 in S3 N/A N/A N/A N/A N/A N/A N/A S4/S5 Powered by VccLAN3_3 in S4/ S5 73 mA Powered by VccCL3_3 in S4/S5 Powered by VccCL3_3 in S4/S5 N/A N/A Powered by VccSus3_3 in S4/S5 N/A Powered by VccSus3_3 in S4/S5 N/A N/A N/A N/A N/A N/A N/A G3 N/A N/A N/A N/A N/A N/A N/A N/A N/A 6 μA N/A N/A N/A N/A N/A N/A V_CPU_IO VccGLANPLL VccUSBPLL VccDMIPLL 7 VccSATAPLL NOTES: 1. These are estimated DC current numbers. 2. Internal voltage regulators power these wells inside the Intel ICH10 and current for these rails are accounted for in the sourcing voltage rail current requirements. 3. Only the G3 state of this rail is shown to provide an estimate of battery life. 4. Icc (RTC) data is taken with VccRTC at 3.0 V while the system is in a mechanical off (G3) state at room temperature. 5. The current for this rail in S3 and S4/S5 is based on the integrated LAN running at 10/100. 6. The current for this rail was measured with VccHDA and VccSusHDA set to 3.3 V. 7. The current for this rail was measured with VccDMI set to 1.5 V. 256 Datasheet Electrical Characteristics Table 8-3. DC Current Characteristics (Corporate Only) Power Plane Symbol V5REF V5REF_Sus Vcc3_3 VccSus3_3 VccHDA6 VccSusHDA6 VccHDA8 VccSusHDA8 VccGLAN3_3 VccGLAN1_5 VccLAN3_35 VccLAN1_12, 5 VccCL3_3 VccCL1_52 VccCL1_12 Vcc1_5_A Vcc1_5_B VccSus1_52 Vcc1_1 VccSus1_12 VccRTC3, 4 VccDMI7 V_CPU_IO VccGLANPLL VccUSBPLL VccDMIPLL7 VccSATAPLL NOTES: Maximum Power Consumption S0 1 mA 2 mA 273 mA 212 mA 30 mA 31 mA 10 mA 11 mA 1 mA 62 mA 17 mA Powered by Vcc1_1 in S0 16 mA Powered by Vcc1_5_A in S0 Powered by Vcc1_1 in S0 1.390 A 591 mA Powered by Vcc1_5_A in S0 2.553 A Powered by Vcc1_1 in S0 N/A 55 mA 1 mA 23 mA 10 mA 22 mA 42 mA S3 N/A 1 mA N/A 95 mA N/A 1 mA N/A 1 mA N/A N/A 77 mA Powered by VccLAN3_3 in S3 70 mA Powered by VccCL3_3 in S3 Powered by VccCL3_3 in S3 N/A N/A Powered by VccSus3_3 in S3 N/A Powered by VccSus3_3 in S3 N/A N/A N/A N/A N/A N/A N/A S4/S5 N/A 1 mA N/A 95 mA N/A 1 mA N/A 1 mA N/A N/A 77 mA Powered by VccLAN3_3 in S3 70 mA Powered by VccCL3_3 in S3 Powered by VccCL3_3 in S3 N/A N/A Powered by VccSus3_3 in S3 N/A Powered by VccSus3_3 in S3 N/A N/A N/A N/A N/A N/A N/A G3 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 6 μA N/A N/A N/A N/A N/A N/A 1. 2. 3. 4. 5. 6. 7. 8. These are estimated DC current numbers. Internal voltage regulators power these wells inside the Intel ICH10 and current for these rails are accounted for in the sourcing voltage rail current requirements. Only the G3 state of this rail is shown to provide an estimate of battery life. Icc (RTC) data is taken with VccRTC at 3.0 V while the system is in a mechanical off (G3) state at room temperature. The current for this rail in S3 and S4/S5 is based on the integrated LAN running at 10/100. The current for this rail was measured with VccHDA and VccSusHDA set to 3.3 V. The current for this rail was measured with VccDMI set to 1.5 V. The current for this rail was measured with VccHDA and VccSusHDA set to 1.5 V. Datasheet 257 Electrical Characteristics Table 8-4. DC Characteristic Input Signal Association (Sheet 1 of 2) Symbol VIH1/VIL1 (5V Tolerant) VIH2/VIL2 Associated Signals PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, PAR, PERR#, PLOCK#, REQ[3:0]#, SERR#, STOP#, TRDY# Interrupt Signals: PIRQ[D:A]#, PIRQ[H:E]# GPIO Signals: GPIO[54, 52, 50, 5:2] Gigabit LAN Connect Signals: GLAN_RX[p,n] Clock Signals: CLK48 Power Management Signals: MCH_SYNC#, THRM#, VRMPWRGD, LAN_RST#, CLPWROK SATA Signals: SATAGP[5:4, 1:0]SATAGP[3:2] Interrupt Signals: SERIRQ VIH3/VIL3 Processor Signals: RCIN#, A20GATE USB Signals: OC[11:0]# GPIO Signals: GPIO[59, 55, 53, 51, 49:36, 35, 31:29, 22:16, 7:6, 1, 0], GPIO32 Intel® Quiet System Technology Signals: TACH[3:0] Strap Signals: GNT[3:0]#,SPKR, SATALED# (Strap purposes only) Clock Signals: CLK14, PCICLK LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LDRQ0#, LDRQ1# VIH4/VIL4 PCI Signals: PME# SPI Signals: SPI_MISO GPIO Signals: GPIO[33, 23] Strap Signals: SPI_MOSI, GNT0# (Strap purposes only) SMBus Signals: SMBCLK, SMBDATA, SMBALERT# VIH5/VIL5 VIH6/VIL6 VIH7/VIL7 VIMIN8/VIMAX8 VIH9/VIL9 VIMIN10/VIMAX10 System Management Signals: SMLINK[1:0], LINKALERT# GPIO Signals: GPIO[60, 11] LAN Signals: GLAN_CLK, LAN_RXD[2:0] Processor Signals: FERR#, THRMTRIP# PCI Express* Data RX Signals: PER[p,n][6:1] Real Time Clock Signals: RTCX1 SATA Signals: SATA[3:0]RX[P,N], SATA[5:4]RX[P,N] Intel® High Definition Audio Signals: HDA_SDIN[3:0] Strap Signals: HDA_SDOUT, HDA_SYNC (Strap purposes only) VIH11/VIL11 GPIO Signals: GPIO34 NOTE: See VIL_HDA/VIH_HDA for High Definition Audio Low Voltage Mode VIH12/VIL12/ Vcross(abs) VIH13/VIL13 Clock Signals: DMI_CLKN, DMI_CLKP, SATA_CLKN, SATA_CLKP Power Management Signals: PWRBTN#, RI#, SYS_RESET#, WAKE# GPIO Signals: GPIO[60, 57:56, 28:26, 24, 14:12, 10:8], GPIO[25, 15] Power Management Signals: PWROK, RSMRST# VIH14/VIL14 System Management Signals: INTRUDER# Miscellaneous Signals: INTVRMEN, LAN100_SLP, RTCRST#, SRTCRST# 258 Datasheet Electrical Characteristics Table 8-4. DC Characteristic Input Signal Association (Sheet 2 of 2) Symbol VIH_CL/VIL_CL VDI / VCM / VSE (5 V Tolerant) VHSSQ / VHSDSC / (5 V Tolerant) Intel® High Definition Audio Signals: HDA_SDIN[3:0] VIH_HDA / VIL_HDA Strap Signals: HDA_SDOUT, HDA_SYNC (Strap purposes only) NOTE: Only applies when running in Low Voltage Mode (1.5 V) VIH_SST/VIL_SST VIH_PECI/VIL_PECI 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Intel® Quiet System Technology Signals: SST Intel® Quiet System Technology Signals: PECI VHSCM Associated Signals Controller Link: CL_CLK0, CL_DATA0 USB Signals: USBP[11:0][P,N] (Low-speed and Full-speed) USB Signals: USBP[11:0][P,N] (in High-speed Mode) VDI = | USBPx[P] – USBPx[N] Includes VDI range Applies to Low-Speed/High-Speed USB PCI Express mVdiff p-p = 2*|PETp[x] – PETn[x]| GLAN mVdiff p-p = 2* |GLAN_RXp – GLAN_RXn| SATA Vdiff, RX (VIMAX10/MIN10) is measured at the SATA connector on the receiver side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP – SATA[x]RXN| VccRTC is the voltage applied to the VccRTC well of the ICH10. When the system is in a G3 state, this is generally supplied by the coin cell battery, but for S5 and greater, this is generally VccSus3_3. CL_Vref = 0.27 (VccCL1_5). CL_VREF0 applies to all configurations. Applies to Ultra DMA Modes greater than Ultra DMA Mode 4. This is an AC Characteristic that represents transient values for these signals. Applies to Hogh-Speed USB 2.0. Datasheet 259 Electrical Characteristics Table 8-5. Symbol VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VIL4 VIH4 VIL5 VIH5 VIL6 VIH6 VIL7 VIH7 VIMIN8 VIMAX8 VIL9 VIH9 VIMIN10- Gen1i VIMAX10-Gen1i VIMIN10-Gen1m VIMAX10-Gen1m VIMIN10-Gen2i VIMAX10-Gen2i VIMIN10-Gen2m DC Input Characteristics (Sheet 1 of 2) Parameter Input Low Voltage Input High Voltage Minimum Input Voltage Maximum Input Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Minimum Input Voltage Maximum Input Voltage Input Low Voltage Input High Voltage Minimum Input Voltage - 1.5 Gb/s internal SATA Maximum Input Voltage - 1.5 Gb/s internal SATA Minimum Input Voltage - 1.5 Gb/s eSATA Maximum Input Voltage - 1.5 Gb/s eSATA Minimum Input Voltage - 3.0 Gb/s internal SATA Maximum Input Voltage - 3.0 Gb/s internal SATA Minimum Input Voltage - 3.0 Gb/s eSATA Min –0.5 0.5(Vcc3_3) 200 — –0.5 2.0 –0.5 0.5(3.3 V) –0.5 2.1 -0.5 0.6(3.3 V) –0.5 0.73(V_CPU_IO) 175 — –0.5 0.40 325 — 240 — 275 — 240 Max 0.3(Vcc3_3) V5REF + 0.5 — 1350 0.8 3.3 V + 0.5 0.3(3.3 V) 3.3 V + 0.5 0.8 3.3 V + 0.5 0.3(3.3 V) 3.3 V + 0.5 0.58(V_CPU_IO) V_CPU_IO + 0.5 — 1200 0.10 1.2 — 600 — 600 — 750 — Unit V V mVdiff p-p mVdiff p-p V V V V V V V V V V mVdiff p-p mVdiff p-p V V mVdiff p-p mVdiff p-p mVdiff p-p mVdiff p-p mVdiff p-p mVdiff p-p mVdiff p-p 6 6 6 6 6 6 6 Note 4 Note 4 Note 12 Note 12 Note 12 Note 12 Note 12 Note 12 Note 5 Note 5 Notes 260 Datasheet Electrical Characteristics Table 8-5. Symbol VIMAX10-Gen2m VIL11 VIH11 VIL12 VIH12 VIL13 VIH13 VIL14 VIH14 VIL_CL VIH_CL VIL_CL2 VIH_CL2 Vcross(abs) VDI VCM VSE VHSSQ VHSDSC VHSCM VIL_HDA VIH_HDA VIL_SST VIH_SST VIL_PECI VIH_PECI DC Input Characteristics (Sheet 2 of 2) Parameter Maximum Input Voltage - 3.0 Gb/s eSATA Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Absolute Crossing Point Differential Input Sensitivity Differential Common Mode Range Single-Ended Receiver Threshold HS Squelch Detection Threshold HS Disconnect Detection Threshold HS Data Signaling Common Mode Voltage Range Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Min — Max 750 0.35(3.3 V) 3.3 V + 0.5 0.150 0.850 0.8 3.3 V + 0.5 0.78 VccRTC + 0.5 (CL_VREF - 0.075) 1.2 0.3(VccCL3_3) VccCL3_3 + 0.5 0.550 — 2.5 2.0 150 625 500 0.4(Vcc_HDA) — 0.4 Vcc + 0.5 0.275(V_CPU_IO) V_CPU_IO + 0.5 Unit mVdiff p-p V V V V V V V V V V V V V V V V mV mV mV V V V V V V Note 1,3 Note 2,3 Note 3 Note 11 Note 11 Note 11 Note 7 Note 8 Note 8 Note 12 Notes 6 Note 12 Note 12 –0.5 0.65(3.3 V) -0.150 0.660 –0.5 2.0 –0.5 2.0 –0.3 (CL_VREF + 0.075) –0.5 0.5(VccCL3_3) 0.250 0.2 0.8 0.8 100 525 –50 — 0.6(Vcc_HDA) -0.5 1.1 -0.5 0.725(V_CPU_IO) NOTES: 1. VDI = | USBPx[P] – USBPx[N] 2. Includes VDI range 3. Applies to Low-Speed/Full-Speed USB 4. PCI Express mVdiff p-p = 2*|PETp[x] - PETn[x]| 5. GLAN mVdiff p-p = 2* |GLAN_RXp - GLAN_RXn| 6. SATA Vdiff, RX (VIMAX10/MIN10) is measured at the SATA connector on the receiver side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP SATA[x]RXN| Datasheet 261 Electrical Characteristics 7. 8. 9. 10. 11. 12. VccRTC is the voltage applied to the VccRTC well of the ICH10. When the system is in a G3 state, this is generally supplied by the coin cell battery, but for S5 and greater, this is generally VccSus3_3. CL_Vref = 0.27 (VccCL1_5). CL_VREF0 applies to all configurations. Applies to Ultra DMA Modes greater than Ultra DMA Mode 4 This is an AC Characteristic that represents transient values for these signals Applies to Hogh-Speed USB 2.0. 3.3 V refers to VccSus3_3 for signals in the suspend well and to Vcc3_3 for signals in the core well. See Table 3-2 or Table 3-3 for signal and power well association. Table 8-6. DC Characteristic Output Signal Association (Sheet 1 of 2) Symbol Associated Signals Processor Signals: A20M#, IGNNE#, INIT#, INTR, NMI, SMI#, STPCLK#, CPUPWRGD, DPSLP# Power Management Signals: DPRSTP# PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, PAR, PERR#, PLOCK#, SERR#(1), STOP#, TRDY# VOH2/VOL2 Intel® High Definition Audio Signals: HDA_RST#, HDA_SDOUT, HDA_SYNC, HDA_BIT_CLK NOTE: See VOH_HDA/VOL_HDA for High Definition Audio Low Voltage Mode GPIO Signals: GPIO33 SMBus Signals: SMBCLK VOH3/VOL3 (1), VOH1/VOL1 SMBDATA (1) System Management Signals: SMLINK[1:0](1), LINKALERT# GPIO Signals: GPIO[60, 11] Power Management Signals: SLP_S3#, SLP_S4#, SLP_S5#, SLP_M#, SUSCLK, SUS_STAT#/LPCPD#, CK_PWRGD, S4_STATE#, DPRSLPVR SATA Signals: SATACLKREQ#, SATALED#, SLOAD, SDATAOUT[1:0] VOH4/VOL4 GPIO Signals: GPIO[49:48, 39:35, 32:31, 26, 21:18, 16, 7:6, 0], GPIO32 Other Signals: SPKR Interrupt Signals: SERIRQ VOH5/VOL5 VOMIN6/VOMAX6 VOMIN7/VOMAX7 USB Signals: USBP[11:0][P,N] in Low-speed and Full-speed Modes PCI Express* Data TX Signals: PET[p,n][6:1] SATA Signals: SATA[5:4, 1:0]TX[P,N], SATA[3:2]TX[P,N] LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4], INIT3_3V# Power Management Signal: PLTRST# PCI Signals: PCIRST#, GNT[3:0]#, PME#(1) VOH8/VOL8 Interrupt Signals: PIRQ[D:A], PIRQ[H:E]#(1) GPIO Signals: GPIO[58, 55:50, 34, 23:22, 17, 5:2, 1] SATA Signals: SCLOCK SPI Signals: SPI_CS0#, SPI_CS1#, SPI_MOSI, SPI_CLK LAN Signals: LAN_RSTSYNC, LAN_TXD[2:0] 262 Datasheet Electrical Characteristics Table 8-6. DC Characteristic Output Signal Association (Sheet 2 of 2) Symbol Associated Signals Power Management Signals: STP_CPU#, STP_PCI# GPIO Signals: GPIO[60, 59, 57:56, 47:40, 31:27, 24, 15:12, 10:8], VOH9/VOL9 GPIO[25, 15] System Management Signals: LINKALERT#, VOMIN10/VOMAX10 VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK Intel® High Definition Audio Signals: HDA_RST#, HDA_SDOUT, HDA_SYNC NOTE: Only applies when running in Low Voltage Mode (1.5 V) VOH_PWM/ VOL_PWM VOH_CL1/VOL_CL1 VOH_CL2/VOL_CL2 VOH_SST/VOL_SST VOH_PECI/ VOL_PECI Intel® Quiet System Technology PWM: PWM[2:0](1) Link Controller Signals: CL_CLK0, CL_DATA0 Link Controller Signals: CL_RST0# SST signal: SST PECI signal: PECI USB Signals: USBP[11:0][P:N] in High-speed Mode Gigabit Lan Connect Signals: GLAN_TX[p,n] VOH_HDA/VOL_HDA NOTE: 1. These signals are open-drain. Datasheet 263 Electrical Characteristics Table 8-7. Symbol VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 VOL4 VOH4 VOL5 VOH5 VOMIN6 VOMAX6 VOMIN7-Gen1i,m VOMAX7-Gen1i,m VOMIN7-Gen2i,m VOMAX7-Gen2i,m VOL8 VOH8 VOL9 VOH9 VOMIN10 VOMAX10 VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK DC Output Characteristics (Sheet 1 of 2) Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Minimum Output Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Minimum Output Voltage Maximum Output Voltage HS Idle Level HS Data Signaling High HS Data Signaling Low Chirp J Level Chirp K Level Min — V_CPU_IO - 0.3 — 0.9(3.3 V) — 3.3 V - 0.5 — 3.3 V - 0.5 — 3.3 V – 0.5 800 — 400 — 400 — — 0.9(3.3 V) — 3.3 V - 0.5 750 — –10.0 360 –10.0 700 –900 Max 0.255 — 0.1(3.3 V) — 0.4 — 0.4 — 0.4 — — 1200 — 600 — 700 0.1(3.3 V) — 0.4 — — 1350 10.0 440 10.0 1100 –500 Unit V V V V V V V V V V mVdif fp-p mVdif fp-p mVdif fp-p mVdif fp-p mVdif fp-p mVdif fp-p V V V V mVdif fp-p mVdif fp-p mV mV mV mV mV 1.5 mA -0.5 mA 6 mA -0.5 mA Note 7 Note 6 Note 6 IOL / IOH 3 mA -3 mA 1.5 mA -0.5 mA 4 mA -2 mA 6 mA -2 mA 5 mA -2 mA Note 7 Note 2 Note 2 Note 3 Note 3 Note 3 Note 3 Note 7 Note 1, 7 Note 7 Note 1 Note 7 Note 7 Notes Note 4 264 Datasheet Electrical Characteristics Table 8-7. Symbol VOL_PWM VOH_PWM VOL_CL1 VOH_CL1 VOL_CL2 VOH_CL2 VOL_CL3 VOH_CL3 VOL_SST VOH_SST VOL_PECI VOH_PECI VOL_HDA VOH_HDA DC Output Characteristics (Sheet 2 of 2) Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Min — — — 0.485(VccCL1_5) — 0.9(VccCL1_5) — VccCL3_3 -0.5 — 1.1 — 0.75(V_CPU_IO) — 0.9(VccHDA) Max 0.4 — 0.15 — 0.1(VccCL1_5) — 0.4 — 0.3 — 0.25(V_CPU_IO) — 0.1(VccHDA) — V V V V V V V V V V V 1.5 mA -1.5 mA 6 mA -0.5 mA 0.5 mA -6 mA 0.5 mA -6 mA 1.5 mA -0.5 mA 1 mA Unit V IOL / IOH 5 mA Note 1 Notes NOTES: 1. The SERR#, PIRQ[H:A], SMBDATA, SMBCLK, LINKALERT#, SMLINK[1:0], and PWM[2:0] signal has an open-drain driver and SATALED# has an open-collector driver, and the VOH specification does not apply. This signal must have external pull up resistor. 2. PCI Express mVdiff p-p = 2*|PETp[x] – PETn[x]| 3. SATA Vdiff, tx (VOMIN7/VOMAX7) is measured at the SATA connector on the transmit side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]TXP – SATA[x]TXN| 4. Maximum Iol for CPUPWRGD is 12 mA for short durations ( 0 (more than one message allocated) 30:3 2 "MC.MME!= MC.MMC (messages allocated not equal to number requested) When this bit is set to 1, single MSI mode operation is in use and software is responsible for clearing bits in the IS register to clear interrupts. This bit shall be cleared to 0 by hardware when any of the four conditions stated is false. This bit is also cleared to 0 when MC.MSIE = 1 and MC.MME = 0h. In this case, the hardware has been programmed to use single MSI mode, and is not "reverting" to that mode. For ICH10, the Controller shall always revert to single MSI mode when the number of vectors allocated by the host is less than the number requested. This bit is ignored when GHC.HR = 1. Interrupt Enable (IE) — R/W. This global bit enables interrupts from the ICH10. 1 0 = All interrupt sources from all ports are disabled. 1 = Interrupts are allowed from the AHCI controller. Controller Reset (HR) — R/W. Resets ICH10 AHCI controller. 0 = No effect 1 = When set by SW, this bit causes an internal reset of the ICH10 AHCI controller. All state machines that relate to data transfers and queuing return to an idle condition, and all ports are re-initialized via COMRESET. NOTE: For further details, consult section 12.3.3 of the Serial ATA Advanced Host Controller Interface specification. 0 Datasheet 539 SATA Controller Registers (D31:F2) 14.4.1.3 IS—Interrupt Status Register (D31:F2) Address Offset: ABAR + 08h–0Bh Default Value: 00000000h Attribute: Size: R/WC 32 bits This register indicates which of the ports within the controller have an interrupt pending and require service. Bit 31:7 6 Reserved. Returns 0. Coalescing Interrupt Pending Status (CIPS) — R/WC. 0 = No interrupt pending. 1 = A command completion coalescing interrupt has been generated. Interrupt Pending Status Port[5] (IPS[5]) — R/WC. 5 0 = No interrupt pending. 1 = Port 5 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[4] (IPS[4]) — R/WC. 4 0 = No interrupt pending. 1 = Port 4 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[3] (IPS[3]) — R/WC. 3 0 = No interrupt pending. 1 = Port 3 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[2] (IPS[2]) — R/WC 2 0 = No interrupt pending. 1 = Port 2 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[1] (IPS[1]) — R/WC. 1 0 = No interrupt pending. 1 = Port 1has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[0] (IPS[0]) — R/WC. 0 0 = No interrupt pending. 1 = Port 0 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Description 540 Datasheet SATA Controller Registers (D31:F2) 14.4.1.4 PI—Ports Implemented Register (D31:F2) Address Offset: Default Value: Function Level Reset: ABAR + 0Ch–0Fh 00000000h No Attribute: Size: R/WO, RO 32 bits This register indicates which ports are exposed to the ICH10. It is loaded by platform BIOS. It indicates which ports that the device supports are available for software to use. For ports that are not available, software must not read or write to registers within that port. Bit 31:6 Reserved. Returns 0. Ports Implemented Port 5 (PI5) — R/WO. 5 0 = The port is not implemented. 1 = The port is implemented. This bit is read-only ‘0’ if MAP.SC = ‘0’ or SCC = ‘01h’. Ports Implemented Port 4 (PI4) — R/WO. 4 0 = The port is not implemented. 1 = The port is implemented. This bit is read-only ‘0’ if MAP.SC = ‘0’ or SCC = ‘01h’. Ports Implemented Port 3 (PI3) — R/WO. 3 0 = The port is not implemented. 1 = The port is implemented. Ports Implemented Port 2 (PI2)— R/WO. 2 0 = The port is not implemented. 1 = The port is implemented. Ports Implemented Port 1 (PI1) — R/WO. 1 0 = The port is not implemented. 1 = The port is implemented. Ports Implemented Port 0 (PI0) — R/WO. 0 0 = The port is not implemented. 1 = The port is implemented. Description Datasheet 541 SATA Controller Registers (D31:F2) 14.4.1.5 VS—AHCI Version (D31:F2) Address Offset: ABAR + 10h–13h Default Value: 00010200h Attribute: Size: RO 32 bits This register indicates the major and minor version of the AHCI specification. It is BCD encoded. The upper two bytes represent the major version number, and the lower two bytes represent the minor version number. Example: Version 3.12 would be represented as 00030102h. The current version of the specification is 1.20 (00010200h). Bit 31:16 15:0 Description Major Version Number (MJR) — RO. Indicates the major version is 1 Minor Version Number (MNR) — RO. Indicates the minor version is 20. 14.4.1.6 CCC_CTL—Command Completion Coalescing Control Register (D31:F2) Address Offset: ABAR + 14h–17h Default Value: 00010131h Attribute: Size: R/W, RO 32 bits This register is used to configure the command coalescing feature. This register is reserved if command coalescing is not supported (CAP_CCCS = ‘0’). Bit Description Timeout Value (TV) — R/W. The timeout value is specified in 10 microsecond intervals. hbaCCC_Timer is loaded with this timeout value. hbaCCC_Timer is only decremented when commands are outstanding on the selected ports. The Controller will signal a CCC interrupt when hbaCCC_Timer has decremented to ‘0’. The hbaCCC_Timer is reset to the timeout value on the assertion of each CCC interrupt. A timeout value of 0 is invalid. Command Completions (CC) — R/W. Specifies the number of command completions that are necessary to cause a CCC interrupt. The Controller has an internal command completion counter, hbaCCC_CommandsComplete. 15:8 hbaCCC_CommandsComplete is incremented by one each time a selected port has a command completion. When hbaCCC_CommandsComplete is equal to the command completions value, a CCC interrupt is signaled. The internal command completion counter is reset to ‘0’ on the assertion of each CCC interrupt. Interrupt (INT) — RO. Specifies the interrupt used by the CCC feature. This interrupt must be marked as unused in the AHCI Ports Implemented memory register by the corresponding bit being set to ‘0’. Thus, the CCC_interrupt corresponds to the interrupt for an unimplemented port on the controller. When a CCC interrupt occurs, the IS[INT] bit shall be asserted to ‘1’ regardless of whether PIRQ interrupt or MSI is used. Note that in MSI, CC interrupt may share an interrupt vector with other ports. For example, if the number of message allocated is 4, then CCC interrupt share interrupt vector 3 along with port 3, 4, and 5 but IS[6] shall get set. 2:1 Reserved Enable (EN) — R/W. 0 = The command completion coalescing feature is disabled and no CCC interrupts are generated 1 = The command completion coalescing feature is enabled and CCC interrupts may be generated based on timeout or command completion conditions. Software shall only change the contents of the TV and CC fields when EN is cleared to '0'. On transition of this bit from '0' to '1', any updated values for the TV and CC fields shall take effect. 31:16 7:3 0 542 Datasheet SATA Controller Registers (D31:F2) 14.4.1.7 CCC_Ports—Command Completion Coalescing Ports Register (D31:F2) Address Offset: ABAR + 18h–1Bh Default Value: 00000000h Attribute: Size: R/W 32 bits This register is used to specify the ports that are coalesced as part of the CCC feature when CCC_CTL.EN = ‘1’. This register is reserved if command coalescing is not supported (CAP_CCCS = ‘0’). Bit Ports (PRT) — R/W. 0 = The port is not part of the command completion coalescing feature. 1 = The corresponding port is part of the command completion coalescing feature. Bits set to ‘1’ in this register must also have the corresponding bit set to ‘1’ in the Ports Implemented register. Bits set to '1' in this register must also have the corresponding bit set to '1' in the Ports Implemented register. An updated value for this field shall take effect within one timer increment (1 millisecond). Description 31:0 14.4.1.8 EM_LOC—Enclosure Management Location Register (D31:F2) Address Offset: ABAR + 1Ch–1Fh Default Value: 01000002h Attribute: Size: RO 32 bits This register identifies the location and size of the enclosure management message buffer. This register is reserved if enclosure management is not supported (i.e., CAP.EMS = 0). Bit 31:16 Description Offset (OFST) — RO. The offset of the message buffer in Dwords from the beginning of the ABAR. Buffer Size (SZ) — RO. Specifies the size of the transmit message buffer area in Dwords. The ICH10 SATA controller only supports transmit buffer. A value of ‘0’ is invalid. 15:0 Datasheet 543 SATA Controller Registers (D31:F2) 14.4.1.9 EM_CTRL—Enclosure Management Control Register (D31:F2) Address Offset: ABAR + 20h–23h Default Value: 07010000h Attribute: Size: R/W, R/WO, RO 32 bits This register is used to control and obtain status for the enclosure management interface. This register includes information on the attributes of the implementation, enclosure management messages supported, the status of the interface, whether any message are pending, and is used to initiate sending messages. This register is reserved if enclosure management is not supported (CAP_EMS = ‘0’). Bit 31:27 Reserved Activity LED Hardware Driven (ATTR.ALHD) — R/WO. 1 = The SATA controller drives the activity LED for the LED message type in hardware and does not utilize software for this LED. The host controller does not begin transmitting the hardware based activity signal until after software has written CTL.TM=1 after a reset condition. Transmit Only (ATTR.XMT) — RO. 25 0 = The SATA controller supports transmitting and receiving messages. 1 = The SATA controller only supports transmitting messages and does not support receiving messages. Single Message Buffer (ATTR.SMB) — RO. 24 0 = There are separate receive and transmit buffers such that unsolicited messages could be supported. 1 = The SATA controller has one message buffer that is shared for messages to transmit and messages received. Unsolicited receive messages are not supported and it is software’s responsibility to manage access to this buffer. Reserved SGPIO Enclosure Management Messages (SUPP.SGPIO): — RO. 1 = The SATA controller supports the SGPIO register interface message type. SES-2 Enclosure Management Messages (SUPP.SES2): — RO. 1 = The SATA controller supports the SES-2 message type. SAF-TE Enclosure Management Messages (SUPP.SAFTE): — RO. 1 = The SATA controller supports the SAF-TE message type. LED Message Types (SUPP.LED): — RO. 1 = The SATA controller supports the LED message type. Reserved Reset (RST): — R/W. 9 0 = A write of ‘0’ to this bit by software will have no effect. 1 = When set by software, The SATA controller shall reset all enclosure management message logic and take all appropriate reset actions to ensure messages can be transmitted / received after the reset. After the SATA controller completes the reset operation, the SATA controller shall set the value to ‘0’. Transmit Message (CTL.TM): — R/W. 0 = A write of ‘0’ to this bit by software will have no effect. 1 = When set by software, The SATA controller shall transmit the message contained in the message buffer. When the message is completely sent, the SATA controller shall set the value to ‘0’. Software shall not change the contents of the message buffer while CTL.TM is set to '1'. 7:1 0 Reserved Message Received (STS.MR): — RO. Message Received is not supported in ICH10. Description 26 23:20 19 18 17 16 15:10 8 544 Datasheet SATA Controller Registers (D31:F2) 14.4.2 14.4.2.1 Vendor Specific Registers (D31:F2) VSP—Vendor Specific (D31:F2) Address Offset: ABAR + A0h–A3h Default Value: 00000000h Bit 31:1 Reserved Supports Low Power Device Detection (SLPD)— RWO 0 Indicates whether SATA power management and device hot (un)pulg is supported. 0 = Not supported. 1 = Supported. Attribute: Size: Description RO, RWO 32 bits 14.4.3 Port Registers (D31:F2) Ports not available will result in the corresponding Port DMA register space being reserved. The controller shall ignore writes to the reserved space on write cycles and shall return ‘0’ on read cycle accesses to the reserved location. Table 14-5. Port [5:0] DMA Register Address Map (Sheet 1 of 3) ABAR + Offset 100h–103h 104h–107h 108h–10Bh 10Ch–10Fh 110h–113h 114h–117h 118h–11Bh 11Ch–11Fh 120h–123h 124h–127h 128h–12Bh 12Ch–12Fh 130h–133h 134h–137h 138h–13Bh 13Ch–17Fh 180h–183h 184h–187h 188h–18Bh 18Ch–18Fh 190h–193h 194h–197h 198h–19Bh 19Ch–19Fh 1A0h–1A3h 1A4h–1A7h Mnemonic P0CLB P0CLBU P0FB P0FBU P0IS P0IE P0CMD — P0TFD P0SIG P0SSTS P0SCTL P0SERR P0SACT P0CI — P1CLB P1CLBU P1FB P1FBU P1IS P1IE P1CMD — P1TFD P1SIG Register Port 0 Command List Base Address Port 0 Command List Base Address Upper 32-Bits Port 0 FIS Base Address Port 0 FIS Base Address Upper 32-Bits Port 0 Interrupt Status Port 0 Interrupt Enable Port 0 Command Reserved Port 0 Task File Data Port 0 Signature Port 0 Serial ATA Status Port 0 Serial ATA Control Port 0 Serial ATA Error Port 0 Serial ATA Active Port 0 Command Issue Reserved Port 1 Command List Base Address Port 1 Command List Base Address Upper 32-Bits Port 1 FIS Base Address Port 1 FIS Base Address Upper 32-Bits Port 1 Interrupt Status Port 1 Interrupt Enable Port 1 Command Reserved Port 1 Task File Data Port 1 Signature Datasheet 545 SATA Controller Registers (D31:F2) Table 14-5. Port [5:0] DMA Register Address Map (Sheet 2 of 3) ABAR + Offset 1A8h–1ABh 1ACh–1AFh 1B0h–1B3h 1B4h–1B7h 1B8h–1BBh 1BCh–1FFh 200h–203h 204h–207h 208h–20Bh 20Ch–20Fh 210h–213h 214h–217h 218h–21Bh 21Ch–21Fh 220h–223h 224h–227h 228h–22Bh 22Ch–22Fh 230h–233h 234h–237h 238h–23Bh 23Ch–27Fh 280h–283h 284h–287h 288h–28Bh 28Ch–28Fh 290h–293h 294h–297h 298h–29Bh 29Ch–29Fh 2A0h–2A3h 2A4h–2A7h 2A8h–2ABh 2ACh–2AFh 2B0h–2B3h 2B4h–2B7h 2B8h–2BBh 2BCh–2FFh 300h–303h 304h–307h 308h–30Bh 30Ch–30Fh 310h–313h 314h–317h 318h–31Bh 31Ch–31Fh 320h–323h Mnemonic P1SSTS P1SCTL P1SERR P1SACT P1CI — P2CLB P2CLBU P2FB P2FBU P2IS P2IE P2CMD — P2TFD P2SIG P2SSTS P2SCTL P2SERR P2SACT P2CI — P3CLB P3CLBU P3FB P3FBU P3IS P3IE P3CMD — P3TFD P3SIG P3SSTS P3SCTL P3SERR P3SACT P3CI — P4CLB P4CLBU P4FB P4FBU P4IS P4IE P4CMD — P4TFD Port 1 Serial ATA Status Port 1 Serial ATA Control Port 1 Serial ATA Error Port 1 Serial ATA Active Port 1 Command Issue Reserved Port 2 Command List Base Address Port 2 Command List Base Address Upper 32-Bits Port 2 FIS Base Address Port 2 FIS Base Address Upper 32-Bits Port 2 Interrupt Status Port 2 Interrupt Enable Port 2 Command Reserved Port 2 Task File Data Port 2 Signature Port 2 Serial ATA Status Port 2 Serial ATA Control Port 2 Serial ATA Error Port 2 Serial ATA Active Port 2 Command Issue Reserved Port 3 Command List Base Address Port 3 Command List Base Address Upper 32-Bits Port 3 FIS Base Address Port 3 FIS Base Address Upper 32-Bits Port 3 Interrupt Status Port 3 Interrupt Enable Port 3 Command Reserved Port 3 Task File Data Port 3 Signature Port 3 Serial ATA Status Port 3 Serial ATA Control Port 3 Serial ATA Error Port 3 Serial ATA Active Port 3 Command Issue Reserved Port 4 Command List Base Address Port 4 Command List Base Address Upper 32-Bits Port 4 FIS Base Address Port 4 FIS Base Address Upper 32-Bits Port 4 Interrupt Status Port 4 Interrupt Enable Port 4 Command Reserved Port 4 Task File Data Register 546 Datasheet SATA Controller Registers (D31:F2) Table 14-5. Port [5:0] DMA Register Address Map (Sheet 3 of 3) ABAR + Offset 324h–327h 328h–32Bh 32Ch–32Fh 330h–333h 334h–337h 338h–33Bh 33Ch–37Fh 380h–383h 384h–387h 388h–38Bh 38Ch–38Fh 390h–393h 394h–397h 398h–39Bh 39Ch–39Fh 3A0h–3A3h 3A4h–3A7h 3A8h–3ABh 3ACh–3AFh 3B0h–3B3h 3B4h–3B7h 3B8h–3BBh 3BCh–3FFh Mnemonic P4SIG P4SSTS P4SCTL P4SERR P4SACT P4CI — P5CLB P5CLBU P5FB P5FBU P5IS P5IE P5CMD — P5TFD P5SIG P5SSTS P5SCTL P5SERR P5SACT P5CI — Port 4 Signature Port 4 Serial ATA Status Port 4 Serial ATA Control Port 4 Serial ATA Error Port 4 Serial ATA Active Port 4 Command Issue Reserved Port 5 Command List Base Address Port 5 Command List Base Address Upper 32-Bits Port 5 FIS Base Address Port 5 FIS Base Address Upper 32-Bits Port 5 Interrupt Status Port 5 Interrupt Enable Port 5 Command Reserved Port 5 Task File Data Port 5 Signature Port 5 Serial ATA Status Port 5 Serial ATA Control Port 5 Serial ATA Error Port 5 Serial ATA Active Port 5 Command Issue Reserved Register 14.4.3.1 PxCLB—Port [5:0] Command List Base Address Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: Undefined Bit + + + + + + 100h 180h 200h 280h 300h 380h Attribute: R/W Size: Description 32 bits 31:10 Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the command list for this port. This base is used when fetching commands to execute. The structure pointed to by this address range is 1 KB in length. This address must be 1-KB aligned as indicated by bits 31:10 being read/write. Note that these bits are not reset on a Controller reset. Reserved 9:0 Datasheet 547 SATA Controller Registers (D31:F2) 14.4.3.2 PxCLBU—Port [5:0] Command List Base Address Upper 32-Bits Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: Undefined Bit + + + + + + 104h 184h 204h 284h 304h 384h Attribute: R/W Size: Description 32 bits 31:0 Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for the command list base address for this port. This base is used when fetching commands to execute. Note that these bits are not reset on a Controller reset. 14.4.3.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: Undefined Bit + + + + + + 108h 188h 208h 288h 308h 388h Attribute: R/W Size: Description 32 bits 31:8 FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The structure pointed to by this address range is 256 bytes in length. This address must be 256-byte aligned, as indicated by bits 31:3 being read/write. Note that these bits are not reset on a Controller reset. Reserved 7:0 14.4.3.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: Undefined Bit 31:0 + + + + + + 10Ch 18Ch 20Ch 28Ch 30Ch 38Ch Attribute: R/W Size: Description 32 bits Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for the received FIS base for this port. Note that these bits are not reset on a Controller reset. 548 Datasheet SATA Controller Registers (D31:F2) 14.4.3.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: 00000000h Bit 31 30 + + + + + + 110h 190h 210h 290h 310h 390h Attribute: R/WC, RO Size: Description 32 bits Cold Port Detect Status (CPDS) — RO. Cold presence detect is not supported. Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is updated by the device and the error bit (PxTFD.bit 0) is set. Host Bus Fatal Error Status (HBFS) — R/WC. Indicates that the Intel® ICH10 encountered an error that it cannot recover from due to a bad software pointer. In PCI, such an indication would be a target or master abort. Host Bus Data Error Status (HBDS) — R/WC. Indicates that the ICH10 encountered a data error (uncorrectable ECC / parity) when reading from or writing to system memory. Interface Fatal Error Status (IFS) — R/WC. Indicates that the ICH10 encountered an error on the SATA interface which caused the transfer to stop. Interface Non-fatal Error Status (INFS) — R/WC. Indicates that the ICH10 encountered an error on the SATA interface but was able to continue operation. Reserved Overflow Status (OFS) — R/WC. Indicates that the ICH10 received more bytes from a device than was specified in the PRD table for the command. Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the ICH10 received a FIS from a device whose Port Multiplier field did not match what was expected. NOTE: Port Multiplier not supported by ICH10. PhyRdy Change Status (PRCS) — RO. When set to one indicates the internal PhyRdy signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is cleared. Note that the internal PhyRdy signal also transitions when the port interface enters partial or slumber power management states. Partial and slumber must be disabled when Surprise Removal Notification is desired, otherwise the power management state transitions will appear as false insertion and removal events. Reserved Device Interlock Status (DIS) — R/WC. When set, indicates that a platform interlock switch has been opened or closed, which may lead to a change in the connection state of the device. This bit is only valid in systems that support an interlock switch (CAP.SIS [ABAR+00:bit 28] set). For systems that do not support an interlock switch, this bit will always be 0. Port Connect Change Status (PCS) — RO. This bit reflects the state of PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this register, this bit is only cleared when PxSERR.DIAG.X is cleared. 0 = No change in Current Connect Status. 1 = Change in Current Connect Status. 29 28 27 26 25 24 23 22 21:8 7 6 5 Descriptor Processed (DPS) — R/WC. A PRD with the I bit set has transferred all its data. Datasheet 549 SATA Controller Registers (D31:F2) Bit Description Unknown FIS Interrupt (UFS) — RO. When set to ‘1’ indicates that an unknown FIS was received and has been copied into system memory. This bit is cleared to ‘0’ by software clearing the PxSERR.DIAG.F bit to ‘0’. Note that this bit does not directly reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown FIS is detected, whereas this bit is set when the FIS is posted to memory. Software should wait to act on an unknown FIS until this bit is set to ‘1’ or the two bits may become out of sync. Set Device Bits Interrupt (SDBS) — R/WC. A Set Device Bits FIS has been received with the I bit set and has been copied into system memory. DMA Setup FIS Interrupt (DSS) — R/WC. A DMA Setup FIS has been received with the I bit set and has been copied into system memory. PIO Setup FIS Interrupt (PSS) — R/WC. A PIO Setup FIS has been received with the I bit set, it has been copied into system memory, and the data related to that FIS has been transferred. Device to Host Register FIS Interrupt (DHRS) — R/WC. A D2H Register FIS has been received with the I bit set, and has been copied into system memory. 4 3 2 1 0 14.4.3.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: 00000000h + + + + + + 114h 194h 214h 294h 314h 394h Attribute: R/W, RO Size: 32 bits This register enables and disables the reporting of the corresponding interrupt to system software. When a bit is set (‘1’) and the corresponding interrupt condition is active, then an interrupt is generated. Interrupt sources that are disabled (‘0’) are still reflected in the status registers. Bit 31 30 Description Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect is not supported. Task File Error Enable (TFEE) — R/W. When set, and GHC.IE and PxTFD.STS.ERR (due to a reception of the error register from a received FIS) are set, the Intel® ICH10 will generate an interrupt. Host Bus Fatal Error Enable (HBFE) — R/W. When set, and GHC.IE and PxS.HBFS are set, the ICH10 will generate an interrupt. Host Bus Data Error Enable (HBDE) — R/W. When set, and GHC.IE and PxS.HBDS are set, the ICH10 will generate an interrupt. Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and PxIS.HBDS is set, the ICH10 will generate an interrupt. Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and PxIS.INFS is set, the ICH10 will generate an interrupt. Reserved Overflow Error Enable (OFE) — R/W. When set, and GHC.IE and PxS.OFS are set, the ICH10 will generate an interrupt. 29 28 27 26 25 24 550 Datasheet SATA Controller Registers (D31:F2) Bit 23 Description Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and PxIS.IPMS are set, the ICH10 will generate an interrupt. NOTE: Should be written as 0. Port Multiplier not supported by ICH10. PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and PxIS.PRCS is set, the ICH10 shall generate an interrupt. Reserved Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH10 will generate an interrupt. For systems that do not support an interlock switch, this bit shall be a read-only 0. Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS are set, the ICH10 will generate an interrupt. Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and PxS.DPS are set, the ICH10 will generate an interrupt Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an unknown FIS is received, the ICH10 will generate this interrupt. Set Device Bits FIS Interrupt Enable (SDBE) — R/W. When set, and GHC.IE and PxS.SDBS are set, the ICH10 will generate an interrupt. DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS are set, the ICH10 will generate an interrupt. PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS are set, the ICH10 will generate an interrupt. Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and GHC.IE and PxS.DHRS are set, the ICH10 will generate an interrupt. 22 21:8 7 6 5 4 3 2 1 0 Datasheet 551 SATA Controller Registers (D31:F2) 14.4.3.7 PxCMD—Port [5:0] Command Register (D31:F2) Address Offset: Port 0: ABAR + 118h Attribute: R/W, RO, R/WO Port 1: ABAR + 198h Port 2: ABAR + 218h Port 3: ABAR + 298h Port 4: ABAR + 318h Port 5: ABAR + 398h Default Value: 0000w00wh Size: 32 bits where w = 00?0b (for?, see bit description) Function Level Reset:No (Bit 21, 19 and 18 only) Bit Description Interface Communication Control (ICC) — R/W. This is a four bit field which can be used to control reset and power states of the interface. Writes to this field will cause actions on the interface, either as primitives or an OOB sequence, and the resulting status of the interface will be reported in the PxSSTS register (Address offset Port 0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3: ABAR+2A4h, Port 4: ABAR+224h, Port 5: ABAR+2A4h). Value Fh–7h 6h 5h–3h 31:28 2h Definition Reserved Slumber: This will cause the Intel® ICH10 to request a transition of the interface to the slumber state. The SATA device may reject the request and the interface will remain in its current state Reserved Partial: This will cause the ICH10 to request a transition of the interface to the partial state. The SATA device may reject the request and the interface will remain in its current state. Active: This will cause the ICH10 to request a transition of the interface into the active No-Op / Idle: When software reads this value, it indicates the ICH10 is not in the process of changing the interface state or sending a device reset, and a new link command may be issued. 1h 0h When system software writes a non-reserved value other than No-Op (0h), the ICH10 will perform the action and update this field back to Idle (0h). If software writes to this field to change the state to a state the link is already in (e.g. interface is in the active state and a request is made to go to the active state), the ICH10 will take no action and return this field to Idle. NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to 02h or 06h. Aggressive Slumber / Partial (ASP) — R/W. When set, and the ALPE bit (bit 26) is set, the ICH10 shall aggressively enter the slumber state when it clears the PxCI register and the PxSACT register is cleared. When cleared, and the ALPE bit is set, the ICH10 will aggressively enter the partial state when it clears the PxCI register and the PxSACT register is cleared. If CAP.SALP is cleared to '0', software shall treat this bit as reserved. Aggressive Link Power Management Enable (ALPE) — R/W. When set, the ICH10 will aggressively enter a lower link power state (partial or slumber) based upon the setting of the ASP bit (bit 27). 27 26 552 Datasheet SATA Controller Registers (D31:F2) Bit Description Drive LED on ATAPI Enable (DLAE) — R/W. When set, the ICH10 will drive the LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA commands. When cleared, the ICH10 will only drive the LED pin active for ATA commands. See Section 5.16.9 for details on the activity LED. Device is ATAPI (ATAPI) — R/W. When set, the connected device is an ATAPI device. This bit is used by the ICH10 to control whether or not to generate the desktop LED when commands are active. See Section 5.16.9 for details on the activity LED. Reserved External SATA Port (ESP) — R/WO. 0 = This port supports internal SATA devices only. 1 = This port will be used with an external SATA device and hot plug is supported. When set, CAP.SXS must also be set. This bit is not reset by Function Level Reset. Reserved Interlock Switch Attached to Port (ISP) — R/WO. When interlock switches are supported in the platform (CAP.SIS [ABAR+00h:bit 28] set), this indicates whether this particular port has an interlock switch attached. This bit can be used by system software to enable such features as aggressive power management, as disconnects can always be detected regardless of PHY state with an interlock switch. When this bit is set, it is expected that HPCP (bit 18) in this register is also set. The ICH10 takes no action on the state of this bit – it is for system software only. For example, if this bit is cleared, and an interlock switch toggles, the ICH10 still treats it as a proper interlock switch event. Note that these bits are not reset on a Controller reset. This bit is not reset by Function Level Reset. Hot Plug Capable Port (HPCP) — R/WO. 0 = Port is not capable of Hot-Plug. 1 = Port is Hot-Plug capable. This indicates whether the platform exposes this port to a device which can be HotPlugged. SATA by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it may be screwed into the chassis, for example). This bit can be used by system software to indicate a feature such as “eject device” to the end-user. The ICH10 takes no action on the state of this bit it is for system software only. For example, if this bit is cleared, and a Hot-Plug event occurs, the ICH10 still treats it as a proper Hot-Plug event. Note that these bits are not reset on a Controller reset. This bit is not reset by Function Level Reset. Port Multiplier Attached (PMA) — RO / R/W. When this bit is set, a port multiplier is attached to the ICH10 for this port. When cleared, a port multiplier is not attached to this port. This bit is RO 0 when CAP.PMS (offset ABAR+00h:bit 17) = 0 and R/W when CAP.PMS = 1. This bit may only be set when Px.CMD.ST is cleared. Port Multiplier FIS Based Switching Enable (PMFSE) — RO. The ICH10 does not support FIS-based switching. NOTE: FIS Port Multiplier not supported by ICH10. Controller Running (CR) — RO. When this bit is set, the DMA engines for a port are running. See section 5.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the ICH10. 25 24 23:22 21 20 19 18 17 16 15 Datasheet 553 SATA Controller Registers (D31:F2) Bit 14 Description FIS Receive Running (FR) — RO. When set, the FIS Receive DMA engine for the port is running. See section 12.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the ICH10. Interlock Switch State (ISS) — RO. For systems that support interlock switches (via CAP.SIS [ABAR+00h:bit 28]), if an interlock switch exists on this port (via ISP in this register), this bit indicates the current state of the interlock switch. A 0 indicates the switch is closed, and a 1 indicates the switch is opened. For systems that do not support interlock switches, or if an interlock switch is not attached to this port, this bit reports 0. Current Command Slot (CCS) — RO. Indicates the current command slot the ICH10 is processing. This field is valid when the ST bit is set in this register, and is constantly updated by the ICH10. This field can be updated as soon as the ICH10 recognizes an active command slot, or at some point soon after when it begins processing the command. This field is used by software to determine the current command issue location of the ICH10. In queued mode, software shall not use this field, as its value does not represent the current command being executed. Software shall only use PxCI and PxSACT when running queued commands. 13 12:8 7:5 Reserved FIS Receive Enable (FRE) — R/W. When set, the ICH10 may post received FISes into the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and PxFBU (ABAR+10Ch/18Ch/20Ch/28Ch). When cleared, received FISes are not accepted by the ICH10, except for the first D2H (device-to-host) register FIS after the initialization sequence. System software must not set this bit until PxFB (PxFBU) have been programmed with a valid pointer to the FIS receive area, and if software wishes to move the base, this bit must first be cleared, and software must wait for the FR bit (bit 14) in this register to be cleared. Command List Override (CLO) — R/W. Setting this bit to '1' causes PxTFD.STS.BSY and PxTFD.STS.DRQ to be cleared to '0'. This allows a software reset to be transmitted to the device regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS register. The Controller sets this bit to '0' when PxTFD.STS.BSY and PxTFD.STS.DRQ have been cleared to '0'. A write to this register with a value of '0' shall have no effect. This bit shall only be set to '1' immediately prior to setting the PxCMD.ST bit to '1' from a previous value of '0'. Setting this bit to '1' at any other time is not supported and will result in indeterminate behavior. Software must wait for CLO to be cleared to '0' before setting PxCMD.ST to '1'. 4 3 554 Datasheet SATA Controller Registers (D31:F2) Bit 2 Description Power On Device (POD) — RO. Cold presence detect not supported. Defaults to 1. Spin-Up Device (SUD) — R/W / RO This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W when CAP.SSS (ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not support staggered spin-up (when CAP.SSS is 0). 1 0 = No action. 1 = On an edge detect from 0 to 1, the ICH10 starts a COMRESET initialization sequence to the device. Clearing this bit to '0' does not cause any OOB signal to be sent on the interface. When this bit is cleared to '0' and PxSCTL.DET=0h, the Controller will enter listen mode. Start (ST) — R/W. When set, the ICH10 may process the command list. When cleared, the ICH10 may not process the command list. Whenever this bit is changed from a 0 to a 1, the ICH10 starts processing the command list at entry 0. Whenever this bit is changed from a 1 to a 0, the PxCI register is cleared by the ICH10 upon the ICH10 putting the controller into an idle state. Refer to section 12.2.1 of the Serial ATA AHCI Specification for important restrictions on when ST can be set to 1. 0 14.4.3.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: 0000007Fh + + + + + + 120h 1A0h 220h 2A0h 320h 3A0h Attribute: RO Size: 32 bits This is a 32-bit register that copies specific fields of the task file when FISes are received. The FISes that contain this information are: D2H Register FIS PIO Setup FIS Set Device Bits FIS Bit 31:16 15:8 Reserved Error (ERR) — RO. Contains the latest copy of the task file error register. Status (STS) — RO. Contains the latest copy of the task file status register. Fields of note in this register that affect AHCI. Bit 7 7:0 6:4 3 2:1 0 Field BSY N/A DRQ N/A ERR Definition Indicates the interface is busy Not applicable Indicates a data transfer is requested Not applicable Indicates an error during the transfer Description Datasheet 555 SATA Controller Registers (D31:F2) 14.4.3.9 PxSIG—Port [5:0] Signature Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: FFFFFFFFh + + + + + + 124h 1A4h 224h 2A4h 324h 3A4h Attribute: RO Size: 32 bits This is a 32-bit register which contains the initial signature of an attached device when the first D2H Register FIS is received from that device. It is updated once after a reset sequence. Bit Description Signature (SIG) — RO. Contains the signature received from a device on the first D2H register FIS. The bit order is as follows: Bit 31:0 31:24 23:16 15:8 7:0 Field LBA High Register LBA Mid Register LBA Low Register Sector Count Register 556 Datasheet SATA Controller Registers (D31:F2) 14.4.3.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: 00000000h + + + + + + 128h 1A8h 228h 2A8h 328h 3A8h Attribute: RO Size: 32 bits This is a 32-bit register that conveys the current state of the interface and host. The ICH10 updates it continuously and asynchronously. When the ICH10 transmits a COMRESET to the device, this register is updated to its reset values. Bit 31:12 Reserved Interface Power Management (IPM) — RO. Indicates the current interface state: Value 0h 11:8 1h 2h 6h Description Device not present or communication not established Interface in active state Interface in PARTIAL power management state Interface in SLUMBER power management state Description All other values reserved. Current Interface Speed (SPD) — RO. Indicates the negotiated interface communication speed. Value 0h 7:4 1h 2h Description Device not present or communication not established Generation 1 communication rate negotiated Generation 2 communication rate negotiated All other values reserved. ICH10 Supports Generation 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/ s). Device Detection (DET) — RO. Indicates the interface device detection and Phy state: Value 0h 3:0 1h 3h 4h Description No device detected and Phy communication not established Device presence detected but Phy communication not established Device presence detected and Phy communication established Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved. Datasheet 557 SATA Controller Registers (D31:F2) 14.4.3.11 PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: 00000004h + + + + + + 12Ch 1ACh 22Ch 2ACh 32Ch 3ACh Attribute: R/W, RO Size: 32 bits This is a 32-bit read-write register by which software controls SATA capabilities. Writes to the SControl register result in an action being taken by the ICH10 or the interface. Reads from the register return the last value written to it. Bit 31:20 19:16 15:12 Reserved Port Multiplier Port (PMP) — R/W. This field is not used by AHCI Select Power Management (SPM) — R/W. This field is not used by AHCI Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which power states the ICH10 is allowed to transition to: Value 0h 11:8 1h 2h 3h Description No interface restrictions Transitions to the PARTIAL state disabled Transitions to the SLUMBER state disabled Transitions to both PARTIAL and SLUMBER states disabled Description All other values reserved Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface. This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field. Value 0h 7:4 1h 2h Description No speed negotiation restrictions Limit speed negotiation to Generation 1 communication rate Limit speed negotiation to Generation 2 communication rate ICH10 Supports Generation 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/s). 558 Datasheet SATA Controller Registers (D31:F2) Bit Description Device Detection Initialization (DET) — R/W. Controls the ICH10’s device detection and interface initialization. Value 0h Description No device detection or initialization action requested Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications re-initialized Disable the Serial ATA interface and put Phy in offline mode 1h 3:0 4h All other values reserved. When this field is written to a 1h, the ICH10 initiates COMRESET and starts the initialization process. When the initialization is complete, this field shall remain 1h until set to another value by software. This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field while the ICH10 is running results in undefined behavior. Note: It is permissible to implement any of the Serial ATA defined behaviors for transmission of COMRESET when DET=1h. 14.4.3.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: 00000000h + + + + + + 130h 1B0h 230h 2B0h 330h 3B0h Attribute: R/WC Size: 32 bits Bits 26:16 of this register contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bits 11:0 contain error information used by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 31:27 Reserved Exchanged (X) — R/WC. When set to one this bit indicates that a change in device presence has been detected since the last time this bit was cleared. This bit shall always be set to 1 anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit. Unrecognized FIS Type (F) — R/WC. Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized. Transport state transition error (T) — R/WC. Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared. Transport state transition error (T) — R/WC. Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared. Description 26 25 24 23 Datasheet 559 SATA Controller Registers (D31:F2) Bit Description Handshake (H) — R/WC. Indicates that one or more R_ERR handshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. CRC Error (C) — R/WC. Indicates that one or more CRC errors occurred with the Link Layer. Disparity Error (D) — R/WC. This field is not used by AHCI. 10b to 8b Decode Error (B) — R/WC. Indicates that one or more 10b to 8b decoding errors occurred. Comm Wake (W) — R/WC. Indicates that a Comm Wake signal was detected by the Phy. Phy Internal Error (I) — R/WC. Indicates that the Phy detected some internal error. PhyRdy Change (N) — R/WC. When set to 1 this bit indicates that the internal PhyRdy signal changed state since the last time this bit was cleared. In the ICH10, this bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled. Software clears this bit by writing a 1 to it. Reserved Internal Error (E) — R/WC. The SATA controller failed due to a master or target abort when attempting to access system memory. Protocol Error (P) — R/WC. A violation of the Serial ATA protocol was detected. Note: The ICH10 does not set this bit for all protocol violations that may occur on the SATA link. Persistent Communication or Data Integrity Error (C) — R/WC. A communication error that was not recovered occurred that is expected to be persistent. Persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. Transient Data Integrity Error (T) — R/WC. A data integrity error occurred that was not recovered by the interface. Reserved. Recovered Communications Error (M) — R/WC. Communications between the device and host was temporarily lost but was re-established. This can arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PhyNRdy signal between the Phy and Link layers. Recovered Data Integrity Error (I) — R/WC. A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. 22 21 20 19 18 17 16 15:12 11 10 9 8 7:2 1 0 560 Datasheet SATA Controller Registers (D31:F2) 14.4.3.13 PxSACT—Port [5:0] Serial ATA Active (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: 00000000h Bit + + + + + + 134h 1B4h 234h 2B4h 334h 3B4h Attribute: R/W Size: Description 32 bits 31:0 Device Status (DS) — R/W. System software sets this bit for SATA queuing operations prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared via the Set Device Bits FIS. This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by software, and as a result of a COMRESET or SRST. 14.4.3.14 PxCI—Port [5:0] Command Issue Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Default Value: 00000000h Bit + + + + + + 138h 1B8h 238h 2B8h 338h 3B8h Attribute: R/W Size: Description 32 bits 31:0 Commands Issued (CI) — R/W. This field is set by software to indicate to the ICH10 that a command has been built-in system memory for a command slot and may be sent to the device. When the ICH10 receives a FIS which clears the BSY and DRQ bits for the command, it clears the corresponding bit in this register for that command slot. Bits in this field shall only be set to '1' by software when PxCMD.ST is set to '1'. This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by software. §§ Datasheet 561 SATA Controller Registers (D31:F2) 562 Datasheet SATA Controller Registers (D31:F5) 15 15.1 Note: SATA Controller Registers (D31:F5) PCI Configuration Registers (SATA–D31:F5) Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 15-1. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 1 of 2) Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h Mnemonic VID DID PCICMD PCISTS RID Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Default 8086h See register description 0000h 02B0h See register description See register description See register description 01h 00h 00000001h 00000001h 00000001h 00000001h 00000001h 00000000h 0000h 0000h 80h 00h See register description Type RO RO R/W, RO R/WC, RO RO See register description See register description RO RO R/W, RO R/W, RO R/W, RO R/W, RO R/W, RO See register description R/WO R/WO RO R/W RO 09h PI Programming Interface 0Ah 0Bh 0Dh 10h–13h 14h–17h 18h–1Bh 1Ch–1Fh 20h–23h 24h–27h 2Ch–2Dh 2Eh–2Fh 34h 3Ch 3Dh SCC BCC PMLT PCMD_BAR PCNL_BAR SCMD_BAR SCNL_BAR BAR SIDPBA SVID SID CAP INT_LN INT_PN Sub Class Code Base Class Code Primary Master Latency Timer Primary Command Block Base Address Primary Control Block Base Address Secondary Command Block Base Address Secondary Control Block Base Address Legacy Bus Master Base Address Serial ATA Index / Data Pair Base Address Subsystem Vendor Identification Subsystem Identification Capabilities Pointer Interrupt Line Interrupt Pin Datasheet 563 SATA Controller Registers (D31:F5) Table 15-1. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 2 of 2) Offset 40h-41h 42h-43h 70h–71h 72h–73h 74h–75h 80h–81h (Consumer Only) 82h–83h (Consumer Only) 84h–87h (Consumer Only) 88h–89h (Consumer Only) 90h 92h–93h A8h–ABh ACh–AFh B0h–B1h B2h–B3h B4h–B5h C0h C4h Mnemonic IDE_TIM IDE_TIM PID PC PMCS Register Name Primary IDE Timing Register Secondary IDE Timing Registers PCI Power Management Capability ID PCI Power Management Capabilities PCI Power Management Control and Status Message Signaled Interrupt Capability ID Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Message Data Address Map Port Control and Status SATA Capability Register 0 SATA Capability Register 1 FLR Capability ID FLR Capability Length and Value FLR Control APM Trapping Control ATM Trapping Status Default 0000h 0000h See register description 4003h 0008h Type R/W R/W RO RO R/W, RO, R/WC RO MSICI 7005h MSIMC 0000h RO, R/W MSIMA 00000000h RO, R/W MSIMD MAP PCS SCAP0 SCAP1 FLRCID FLRCLV FLRCTRL ATC ATS 0000h 00h 0000h 0010B012h 00000048h 0009h 2006h 0000h 00h 00h R/W R/W R/W, RO, R/WC RO RO RO RO R/W, RO R/W R/WC NOTE: The ICH10 SATA controller is not arbitrated as a PCI device, therefore it does not need a master latency timer. 15.1.1 VID—Vendor Identification Register (SATA—D31:F5) Offset Address: 00h–01h Default Value: 8086h Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16 bit Core Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 564 Datasheet SATA Controller Registers (D31:F5) 15.1.2 DID—Device Identification Register (SATA—D31:F5) Offset Address: 02h–03h Default Value: See bit description Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16 bit Core Device ID — RO. This is a 16-bit value assigned to the Intel® ICH10 SATA controller. NOTE: The value of this field will change dependent upon the value of the MAP Register. See Section 15.1.29 15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) Address Offset: 04h–05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 10 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 1 = Internal INTx# messages will not be generated. Fast Back to Back Enable (FBE) — RO. Reserved as 0. SERR# Enable (SERR_EN) — RO. Reserved as 0. Wait Cycle Control (WCC) — RO. Reserved as 0. Parity Error Response (PER) — R/W. 6 0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected. 1 = Enabled. SATA controller will generate PERR# when a data parity error is detected. 5 4 3 2 VGA Palette Snoop (VPS) — RO. Reserved as 0. Postable Memory Write Enable (PMWE) — RO. Reserved as 0. Special Cycle Enable (SCE) — RO. Reserved as 0. Bus Master Enable (BME) — R/W. This bit controls the ICH10’s ability to act as a PCI master for IDE Bus Master transfers. This bit does not impact the generation of completions for split transaction commands. Memory Space Enable (MSE) — RO. This controller does not support AHCI, therefore no memory space is required. I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers. 0 0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the Bus Master I/O registers. 1 = Enable. Note that the Base Address register for the Bus Master registers should be programmed before this bit is set. Attribute: Size: Description RO, R/W 16 bits 9 8 7 1 Datasheet 565 SATA Controller Registers (D31:F5) 15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) Address Offset: 06h–07h Default Value: 02B0h Attribute: Size: R/WC, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit 15 14 13 12 11 10:9 Description Detected Parity Error (DPE) — R/WC. 0 = No parity error detected by SATA controller. 1 = SATA controller detects a parity error on its interface. Signaled System Error (SSE) — RO. Reserved as 0. Received Master Abort (RMA) — R/WC. 0 = Master abort Not generated. 1 = SATA controller, as a master, generated a master abort. Reserved Signaled Target Abort (STA) — RO. Reserved as 0. DEVSEL# Timing Status (DEV_STS) — RO. 01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface. Data Parity Error Detected (DPED) — R/WC. For ICH10, this bit can only be set on read completions received from SiBUS where there is a parity error. 1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. Fast Back to Back Capable (FB2BC) — RO. Reserved as 1. User Definable Features (UDF) — RO. Reserved as 0. 66MHz Capable (66MHZ_CAP) — RO. Reserved as 1. Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities list. The minimum requirement for the capabilities list must be PCI power management for the SATA controller. Interrupt Status (INTS) — RO. Reflects the state of INTx# messages, IRQ14 or IRQ15. 3 0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register [offset 04h]). 1 = Interrupt is to be asserted Reserved 8 7 6 5 4 2:0 15.1.5 RID—Revision Identification Register (SATA—D31:F5) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID — RO. Refer to the Intel® I/O Controller Hub (ICH10) Family Specification Update for the value of the Revision ID Register 566 Datasheet SATA Controller Registers (D31:F5) 15.1.6 PI—Programming Interface Register (SATA–D31:F5) Address Offset: 09h Default Value: 85h When SCC = 01h Bit 7 6:4 Description This read-only bit is a 1 to indicate that the ICH10 supports bus master operation Reserved. Secondary Mode Native Capable (SNC) — RO. Indicates whether or not the secondary channel has a fixed mode of operation. 0 = Indicates the mode is fixed and is determined by the (read-only) value of bit 2. This bit will always return ‘0’. Secondary Mode Native Enable (SNE) — RO. 2 Determines the mode that the secondary channel is operating in. 1 = Secondary controller operating in native PCI mode. This bit will always return ‘1’. Primary Mode Native Capable (PNC) — RO. Indicates whether or not the primary channel has a fixed mode of operation. 0 = Indicates the mode is fixed and is determined by the (read-only) value of bit 0. This bit will always return ‘0’. Primary Mode Native Enable (PNE) — RO. 0 Determines the mode that the primary channel is operating in. 1 = Primary controller operating in native PCI mode. This bit will always return ‘1’. Attribute: Size: RO 8 bits 3 1 15.1.7 SCC—Sub Class Code Register (SATA–D31:F5) Address Offset: 0Ah Default Value: 01h Bit 7:0 Sub Class Code (SCC) — RO. The value of this field determines whether the controller supports legacy IDE mode. Attribute: Size: Description RO 8 bits 15.1.8 BCC—Base Class Code Register (SATA–D31:F5) Address Offset: 0Bh Default Value: 01h Bit 7:0 Base Class Code (BCC) — RO. 01h = Mass storage device Attribute: Size: Description RO 8 bits Datasheet 567 SATA Controller Registers (D31:F5) 15.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F5) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Master Latency Timer Count (MLTC) — RO. 00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. 15.1.10 PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F5) Address Offset: 10h–13h Default Value: 00000001h Attribute: Size: Description Reserved Base Address — R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. R/W, RO 32 bits . Bit 31:16 15:3 2:1 0 NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block. 15.1.11 PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F5) Address Offset: 14h–17h Default Value: 00000001h Attribute: Size: Description Reserved Base Address — R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. R/W, RO 32 bits . Bit 31:16 15:2 1 0 NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block. 568 Datasheet SATA Controller Registers (D31:F5) 15.1.12 SCMD_BAR—Secondary Command Block Base Address Register (IDE D31:F1) Address Offset: 18h–1Bh Default Value: 00000001h Bit 31:16 15:3 2:1 0 Reserved Base Address — R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. Attribute: Size: Description R/W, RO 32 bits NOTE: This 8-byte I/O space is used in native mode for the Secondary Controller’s Command Block. 15.1.13 SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) Address Offset: 1Ch–1Fh Default Value: 00000001h Bit 31:16 15:2 1 0 Reserved Base Address — R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. Attribute: Size: Description R/W, RO 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block. Datasheet 569 SATA Controller Registers (D31:F5) 15.1.14 BAR — Legacy Bus Master Base Address Register (SATA–D31:F5) Address Offset: 20h–23h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16byte IO space to provide a software interface to the Bus Master functions. Only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address. Bit 31:16 15:5 4 3:1 0 Reserved Base Address — R/W. This field provides the base address of the I/O space (16 consecutive I/O locations). Base Address 4 (BA4)— R/W. When SCC is 01h, this bit will be R/W resulting in requesting 16B of I/O space. Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. Description 15.1.15 SIDPBA — SATA Index/Data Pair Base Address Register (SATA–D31:F5) Address Offset: 24h–27h Default Value: 00000000h When SCC is 01h When the programming interface is IDE, the register represents an I/O BAR allocating 16B of I/O space for the I/O mapped registers defined in Section 15.3. Note that although 16B of locations are allocated, some maybe reserved. Bit 31:16 15:4 3:1 0 Reserved Base Address (BA) — R/W. Base address of register I/O space Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. Description Attribute: Size: R/W, RO 32 bits 570 Datasheet SATA Controller Registers (D31:F5) 15.1.16 SVID—Subsystem Vendor Identification Register (SATA–D31:F5) Address Offset: 2Ch–2Dh Default Value: 0000h Lockable: No Function Level Reset: No Bit 15:0 Attribute: Size: Power Well: R/WO 16 bits Core Description Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware action taken on this value. 15.1.17 SID—Subsystem Identification Register (SATA–D31:F5) Address Offset: 2Eh–2Fh Default Value: 0000h Lockable: No Bit 15:0 Attribute: Size: Power Well: Description R/WO 16 bits Core Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on this value. 15.1.18 CAP—Capabilities Pointer Register (SATA–D31:F5) Address Offset: 34h Default Value: 70h Bit 7:0 Attribute: Size: Description RO 8 bits Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is 70h if the Sub Class Code (SCC) (Dev 31:F2:0Ah) is configure as IDE mode (value of 01). 15.1.19 INT_LN—Interrupt Line Register (SATA–D31:F5) Address Offset: 3Ch Default Value: 00h Function Level Reset: No Bit 7:0 Attribute: Size: R/W 8 bits Description Interrupt Line — R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. These bits are not reset by FLR. 15.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F5) Address Offset: 3Dh Default Value: See Register Description Bit 7:0 Attribute: Size: RO 8 bits Description Interrupt Pin — RO. This reflects the value of D31IP.SIP1 (Chipset Config Registers:Offset 3100h:bits 11:8). Datasheet 571 SATA Controller Registers (D31:F5) 15.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F5) Address Offset: Primary: 40h–41h Secondary: 42h–43h Default Value: 0000h Bit Attribute: Size: Description R/W 16 bits IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode. 0 = Disable. 1 = Enables the Intel® ICH10 to decode the associated Command Blocks (1F0–1F7h for primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h for secondary). This bit effects the IDE decode ranges for both legacy and native-Mode decoding. NOTE: This bit affects SATA operation in both combined and non-combined ATA modes. See Section 5.16 for more on ATA modes of operation. 14:0 Reserved 15 15.1.22 PID—PCI Power Management Capability Identification Register (SATA–D31:F5) Address Offset: 70h–71h Default Value: B001h Bits 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) — RO. When SCC is 01h, this field will be B0h indicating the next item is FLR Capability Pointer in the list. Capability ID (CID) — RO. Indicates that this pointer is a PCI power management. 15.1.23 PC—PCI Power Management Capabilities Register (SATA–D31:F5) Address Offset: 72h–73h Default Value: 4003h Attribute: Size: Description PME Support (PME_SUP) — RO. By default with SCC = 01h, the default value of 00000 indicates no PME support in IDE mode. D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported Auxiliary Current (AUX_CUR) — RO. PME# from D3COLD state is not supported, therefore this field is 000b. Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no devicespecific initialization is required. Reserved PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to generate PME#. Version (VER) — RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI Power Management Specification. RO 16 bits f Bits 15:11 10 9 8:6 5 4 3 2:0 572 Datasheet SATA Controller Registers (D31:F5) 15.1.24 PMCS—PCI Power Management Control and Status Register (SATA–D31:F5) Address Offset: Default Value: Function Level Reset: Bits 74h–75h Attribute: 0008h Size: No (Bits 8 and 15 only) Description RO, R/W, R/WC 16 bits PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if this bit and PMEE is set, a PME# will be generated from the SATA controller. 15 Note: When SCC=01h this bit will be RO ‘0’. Software is advised to clear PMEE together with PMES prior to changing SCC through MAP.SMS. This bit is not reset by Function Level Reset. 14:9 Reserved PME Enable (PMEE) — R/W. When SCC is not 01h, this bit R/W. When set, the SATA controller generates PME# form D3HOT on a wake event. 8 Note: When SCC=01h this bit will be RO ‘0’. Software is advised to clear PMEE together with PMES prior to changing SCC through MAP.SMS. This bit is not reset by Function Level Reset. 7:4 Reserved No Soft Reset (NSFRST) — RO. These bits are used to indicate whether devices transitioning from D3HOT state to D0 state will perform an internal reset. 0 = Device transitioning from D3HOT state to D0 state perform an internal reset. 1 = Device transitioning from D3HOT state to D0 state do not perform an internal reset. 3 Configuration content is preserved. Upon transition from the D3HOT state to D0 state initialized state, no additional operating system intervention is required to preserve configuration context beyond writing to the PowerState bits. Regardless of this bit, the controller transition from D3HOT state to D0 state by a system or bus segment reset will return to the state D0 uninitialized with only PME context preserved if PME is supported and enabled. 2 Reserved Power State (PS) — R/W. These bits are used both to determine the current power state of the SATA controller and to set a new power state. 1:0 00 = D0 state 11 = D3HOT state When in the D3HOT state, the controller’s configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. 15.1.25 MID—Message Signal Interrupt Identifier (SATA–D31:F5) (Consumer Only) Address Offset: 80h-81h Default Value: 7005h Bits 15:8 7:0 Attribute: Size: Description RO 16 bits Next Pointer (NEXT)— RO. Indicates the next item in the list is the PCI Power Management Pointer. Capability ID (CID)— RO. Capability ID indicates Message Signal Interrupt. Datasheet 573 SATA Controller Registers (D31:F5) 15.1.26 MC—Message Signal Interrupt Message Control (SATA– D31:F5) (Consumer Only) Address Offset: 82h-83h Default Value: 0000h Bits 15:8 7 6:4 Reserved. 64 Bit Address Capable (C64)— RO. Capable of generating a 32-bit message only. Multiple Message Enable (MME)— RO. This controller supports a single interrupt message. This bit is RO ‘0’. Multiple Message Capable (MMC)— RO. System software reads this field to determine the number of requested vectors. This controller supports a single interrupt message, this field is RO ‘0’. MSI Enable (MSIE) — R/W. If set, MSI is enabled and traditional interrupt pins are not used to generate interrupts. 0 Note: CMD.ID bit does not effect MSI. Software must clear this bit to 0 to disable MSI before changing the number of messages allocated in the MMC field. Software must also make sure this bit is cleared to ‘0’ when operating in legacy IDE mode. This bit is R/W when SCC is not 01h and is RO ‘0’ when SCC is 01h. Attribute: Size: Description R/W, RO 16 bits 3:1 15.1.27 MA—Message Signal Interrupt Message Address (SATA– D31:F5) (Consumer Only) Address Offset: 84h Default Value: 00000000h Bits 31:2 1:0 Attribute: Size: Description R/W, RO 32 bits Address (ADDR)— R/W. Lower 32 bits of the system specified message address, always DWORD aligned. Reserved. 15.1.28 MD—Message Signal Interrupt Message Data (SATA– D31:F5) (Consumer Only) Address Offset: 88h Default Value: 0000h Bits Attribute: Size: Description R/W 16 bits 15:0 Data (DATA)— R/W. This 16-bit field is programmed by system software if MSI is enabled. Its content is driven onto the lower word of the data bus of the MSI memory write transaction. Note: When MC.MME field is set to a value other than ‘000’, some bits of the MSI memory write transaction will be driven based on the source of the interrupt rather than from MD[2:0]. 574 Datasheet SATA Controller Registers (D31:F5) 15.1.29 MAP—Address Map Register (SATA–D31:F5)16 Address Offset: Default Value: Function Level Reset: Bits 15:10 9:8 Reserved. Reserved SATA Mode Select (SMS) — R/W. Software programs these bits to control the mode in which the SATA Controller should operate. 00b = IDE Mode All other combinations are reserved. 5:2 1:0 Reserved. Map Value (MV)— Reserved. 90h Attribute: 00h Size: No (Bits 9:8 only) Description R/W, R/WO, RO bits 7:6 Datasheet 575 SATA Controller Registers (D31:F5) 15.1.30 PCS—Port Control and Status Register (SATA–D31:F5) Address Offset: 92h–93h Default Value: 0000h Function Level Reset: No Attribute: Size: R/W, RO 16 bits By default, the SATA ports are set to the disabled state (bits [5:0] = ‘0’). When enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. When disabled, the port is in the “off” state and cannot detect any devices. If an AHCI-aware or RAID enabled operating system is being booted then system BIOS shall insure that all supported SATA ports are enabled prior to passing control to the OS. Once the AHCI aware OS is booted it becomes the enabling/disabling policy owner for the individual SATA ports. This is accomplished by manipulating a port’s PxSCTL and PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of the PxE bits and because the PxE bits act as master on/off switches for the ports, preboot software must insure that these bits are set to 1 prior to booting the OS, regardless as to whether or not a device is currently on the port. Bits 15:10 Reserved Port 5 Present (P5P) — RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P1E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 1 has been detected. Port 4 Present (P4P) — RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P0E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 0 has been detected. 7:2 Reserved Port 5 Enabled (P5E) — R/W. 1 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. This bit is read-only ‘0’ when MAP.SPD[1]= 1. Port 4 Enabled (P4E) — R/W. 0 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. This bit is read-only ‘0’ when MAP.SPD[0]= 1. Description 9 8 576 Datasheet SATA Controller Registers (D31:F5) 15.1.31 SATACR0— SATA Capability Register 0 (SATA–D31:F5) Address Offset: A8h-ABh Default Value: 0010B012h Function Level Reset: No (Bits 15:8 only) Attribute: Size: RO, RWO 32 bits Note: . When SCC is 01h this register is read-only 0. Bit 31:24 23:20 19:16 15:8 7:0 Reserved. Major Revision (MAJREV) — RO. Major revision number of the SATA Capability Pointer implemented. Minor Revision (MINREV) — RO. Minor revision number of the SATA Capability Pointer implemented. Next Capability Pointer (NEXT) — RWO. Points to the next capability structure. Capability ID (CAP) — RO. The value of 12h has been assigned by the PCI SIG to designate the SATA capability pointer. Description 15.1.32 SATACR1— SATA Capability Register 1 (SATA–D31:F5) Address Offset: ACh-AFh Default Value: 00000048h When SCC is 01h this register is read-only 0. Attribute: Size: RO 32 bits . Bit 31:16 Reserved. Description 15:4 BAR Offset (BAROFST) — RO. Indicates the offset into the BAR where the index/Data pair are located (in DWord granularity). The index and Data I/O registers are located at offset 10h within the I/O space defined by LBAR (BAR4). A value of 004h indicates offset 10h. BAR Location (BARLOC) — RO. Indicates the absolute PCI Configuration Register address of the BAR containing the Index/Data pair (in DWord granularity). The Index and Data I/O registers reside within the space defined by LBAR (BAR4) in the SATA controller. a value of 8h indicates and offset of 20h, which is LBAR (BAR4). 3:0 15.1.33 FLRCID— FLR Capability ID (SATA–D31:F5) Address Offset: B0h-B1h Default Value: 0009h Attribute: Size: Description Next Capability Pointer — RO. A value of 00h indicates the final item in the Capability List. Capability ID — RO. The value of this field depends on the FLRCSSECL bit. 7:0 If FLRCSSEL = 0, this field is 13h If FLRCSSEL = 1, this field is 09h, indicating vendor specific capability. RO 16 bits . Bit 15:8 Datasheet 577 SATA Controller Registers (D31:F5) 15.1.34 FLRCLV— FLR Capability Length and Value (SATA–D31:F5) Address Offset: Default Value: Function Level Reset: B2h-B3h 2006h No (Bits 9:8 only) Attribute: Size: RO, RWO 16 bits When FLRCSSEL = ‘0’, this register is defined as follows. Bit 15:10 9 8 Reserved. FLR Capability — RWO. This field indicates support for Function Level Reset. TXP Capability — RWO. This field indicates support for the Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. Capability Length — RO. This field indicates the number of bytes of the Vendor Specific capability as required by the PCI spec. It has the value of 06h for FLR Capability. Description 7:0 When FLRCSSEL = ‘1’ , this register is defined as follows. Bit 15:12 11:8 7:0 Description Vendor Specific Capability ID — RO. A value of 02h identifies this capability as a Function Level Reset. Capability Version — RO. This field indicates the version of the FLR capability. Capability Length — RO. This field indicates the number of bytes of the Vendor Specific capability as required by the PCI spec. It has the value of 06h for FLR Capability. 15.1.35 FLRCTRL— FLR Control (SATA–D31:F5) Address Offset: B4h-B5h Default Value: 0000h Bit 15:9 8 7:1 0 Reserved. Transactions Pending (TXP) — RO. 0 = Completions for all Non-Posted requests have been received by the controller. 1 = Controller has issued Non-Posted request which has not been completed. Reserved. Initiate FLR — R/W. Used to initiate FLR transition. A write of ‘1’ indicates FLR transition. Attribute: Size: Description R/W, RO 16 bits 578 Datasheet SATA Controller Registers (D31:F5) 15.1.36 ATC—APM Trapping Control Register (SATA–D31:F5) Address Offset: C0h Default Value: 00h Attribute: Size: R/W 8 bits Note: . This SATA controller does not support legacy I/O access. Therefore, this register is reserved. Software shall not change the default values of the register; otherwise the result will be undefined. Bit 7:0 Reserved Description 15.1.37 ATC—APM Trapping Control (SATA–D31:F5) Address Offset: C4h Default Value: 00h Attribute: Size: R/WC 8 bits Note: . This SATA controller does not support legacy I/O access. Therefore, this register is reserved. Software shall not change the default values of the register; otherwise the result will be undefined. Bit 7:0 Reserved Description Datasheet 579 SATA Controller Registers (D31:F5) 15.2 Bus Master IDE I/O Registers (D31:F5) The bus master IDE function uses 16 bytes of I/O space, allocated via the BAR register, located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or dword quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). These registers are only used for legacy operation. Software must not use these registers when running AHCI. The description of the I/O registers is shown in Table 15-2. Table 15-2. Bus Master IDE I/O Register Address Map BAR+ Offset 00 01 02 03 04–07 08 09 0Ah 0Bh 0Ch–0Fh Mnemonic BMICP — BMISP — BMIDP BMICS — BMISS — BMIDS Register Command Register Primary Reserved Bus Master IDE Status Register Primary Reserved Bus Master IDE Descriptor Table Pointer Primary Command Register Secondary Reserved Bus Master IDE Status Register Secondary Reserved Bus Master IDE Descriptor Table Pointer Secondary Default 00h — 00h — xxxxxxxxh 00h — 00h — xxxxxxxxh Type R/W RO R/W, R/WC, RO RO R/W R/W RO R/W, R/WC, RO RO R/W 580 Datasheet SATA Controller Registers (D31:F5) 15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) Address Offset: Primary: BAR + 00h Secondary: BAR + 08h Default Value: 00h Bit 7:4 Reserved. Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master transfer: This bit must NOT be changed when the bus master function is active. 0 = Memory reads 1 = Memory writes Reserved. Start/Stop Bus Master (START) — R/W. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master IDE Active bit (D31:F5:BAR + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controller. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a 0 to this bit. NOTE: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. If this bit is cleared to 0 prior to the DMA data transfer being initiated by the drive in a device to memory data transfer, then the ICH10 will not send DMAT to terminate the data transfer. SW intervention (e.g. sending SRST) is required to reset the interface in this condition. Attribute: Size: Description R/W 8 bits 3 2:1 0 Datasheet 581 SATA Controller Registers (D31:F5) 15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) Address Offset: Primary: BAR + 02h Secondary: BAR + 0Ah Default Value: 00h Bit Attribute: Size: Description R/W, R/WC, RO 8 bits PRD Interrupt Status (PRDIS) — R/WC. 7 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit set. Reserved. Drive 0 DMA Capable — R/W. 5 0 = Not Capable 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The ICH10 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Reserved. Interrupt — R/WC. 2 0 = Software clears this bit by writing a 1 to it. 1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not disabled interrupts via the IEN bit of the Device Control Register (see chapter 5 of the Serial ATA Specification, Revision 1.0a). Error — R/WC. 1 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. Bus Master IDE Active (ACT) — RO. 0 = This bit is cleared by the ICH10 when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared by the ICH10 when the Start Bus Master bit (D31:F5:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = Set by the ICH10 when the Start bit is written to the Command register. 6 4:3 0 15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F5) Address Offset: Primary: BAR + 04h–07h Attribute: Secondary: BAR + 0Ch–0Fh Default Value: All bits undefined Size: Bit Description Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits [31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor Table must be dword-aligned. The Descriptor Table must not cross a 64-K boundary in memory. Reserved R/W 32 bits 31:2 1:0 582 Datasheet SATA Controller Registers (D31:F5) 15.3 Serial ATA Index/Data Pair Superset Registers All of these I/O registers are in the core well. They are exposed only when SCC is 01h (i.e. IDE programming interface) and the controller is not in combined mode. These are Index/Data Pair registers that are used to access the SerialATA superset registers (SerialATA Status, SerialATA Control and SerialATA Error). The I/O space for these registers is allocated through SIDPBA. Locations with offset from 08h to 0Fh are reserved for future expansion. Software-write operations to the reserved locations shall have no effect while software-read operations to the reserved locations shall return 0. 15.3.1 SINDX—SATA Index Register (D31:F5) Address Offset: SIDPBA + 00h Default Value: 00000000h Attribute: Size: R/W 32 bits Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and SERR. The I/O space for these registers is allocated through SIDPBA. Bit 31:16 Reserved Port Index (PIDX)— R/W: This Index field is used to specify the port of the SATA controller at which the port-specific SSTS, SCTL, and SERR registers are located. 15:8 00h = Primary Master (Port 4) 02h = Secondary Master (Port 5) All other values are Reserved. Register Index (RIDX)— R/W: This Index field is used to specify one out of three registers currently being indexed into. 7:0 00h = SSTS 01h = SCTL 02h = SERR All other values are Reserved Description 15.3.2 SDATA—SATA Index Data Register (D31:F5) Address Offset: SIDPBA + 04h Default Value: All bits undefined Attribute: Size: R/W 32 bits Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and SERR. The I/O space for these registers is allocated through SIDPBA. Bit Description Data (DATA)— R/W: This Data register is a “window” through which data is read or written to the memory mapped registers. A read or write to this Data register triggers a corresponding read or write to the memory mapped register pointed to by the Index register. The Index register must be setup prior to the read or write to this Data register. Note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. Since this is not a physical register, the “default” value is the same as the default value of the register pointed to by Index. 31:0 Datasheet 583 SATA Controller Registers (D31:F5) 15.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5) Address Offset: Default Value: 00000000h Attribute: Size: RO 32 bits SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state of the interface and host. The ICH10 updates it continuously and asynchronously. When the ICH10 transmits a COMRESET to the device, this register is updated to its reset values. Bit 31:12 Reserved Interface Power Management (IPM) — RO. Indicates the current interface state: Value 0h 11:8 1h 2h 6h Description Device not present or communication not established Interface in active state Interface in PARTIAL power management state Interface in SLUMBER power management state Description All other values reserved. Current Interface Speed (SPD) — RO. Indicates the negotiated interface communication speed. Value 0h 7:4 1h 2h Description Device not present or communication not established Generation 1 communication rate negotiated Generation 2 communication rate negotiated All other values reserved. ICH10 Supports Generation 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/s). Device Detection (DET) — RO. Indicates the interface device detection and Phy state: Value 0h 3:0 1h 3h 4h Description No device detected and Phy communication not established Device presence detected but Phy communication not established Device presence detected and Phy communication established Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved. 584 Datasheet SATA Controller Registers (D31:F5) 15.3.2.2 PxSCTL — Serial ATA Control Register (D31:F5) Address Offset: Default Value: 00000004h Attribute: Size: R/W, RO 32 bits SDATA when SINDX.RIDX is 01h. This is a 32-bit read-write register by which software controls SATA capabilities. Writes to the SControl register result in an action being taken by the ICH10 or the interface. Reads from the register return the last value written to it. Bit 31:20 19:16 15:12 Reserved Port Multiplier Port (PMP) — RO. This field is not used by AHCI. Select Power Management (SPM) — RO. This field is not used by AHCI. Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which power states the ICH10 is allowed to transition to: Value 0h 11:8 1h 2h 3h Description No interface restrictions Transitions to the PARTIAL state disabled Transitions to the SLUMBER state disabled Transitions to both PARTIAL and SLUMBER states disabled Description All other values reserved Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface. This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field. Value Description 0h 7:4 1h 2h No speed negotiation restrictions Limit speed negotiation to Generation 1 communication rate Limit speed negotiation to Generation 2 communication rate All other values reserved. ICH10 Supports Generation 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/s). Device Detection Initialization (DET) — R/W. Controls the ICH10’s device detection and interface initialization. Value 0h Description No device detection or initialization action requested Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications re-initialized Disable the Serial ATA interface and put Phy in offline mode 1h 3:0 4h All other values reserved. When this field is written to a 1h, the ICH10 initiates COMRESET and starts the initialization process. When the initialization is complete, this field shall remain 1h until set to another value by software. This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field while the ICH10 is running results in undefined behavior. Datasheet 585 SATA Controller Registers (D31:F5) 15.3.2.3 PxSERR—Serial ATA Error Register (D31:F5) Address Offset: Default Value: 00000000h SDATA when SINDx.RIDX is 02h. Bits 26:16 of this register contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bits 11:0 contain error information used by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 31:27 Reserved Exchanged (X) — R/WC. When set to one this bit indicates that a change in device presence has been detected since the last time this bit was cleared. This bit shall always be set to 1 anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit. Unrecognized FIS Type (F) — R/WC. Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized. Transport state transition error (T) — R/WC. Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared. Transport state transition error (T) — R/WC. Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared. Handshake (H) — R/WC. Indicates that one or more R_ERR handshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. CRC Error (C) — R/WC. Indicates that one or more CRC errors occurred with the Link Layer. Disparity Error (D) — R/WC. This field is not used by AHCI. 10b to 8b Decode Error (B) — R/WC. Indicates that one or more 10b to 8b decoding errors occurred. Comm Wake (W) — R/WC. Indicates that a Comm Wake signal was detected by the Phy. Phy Internal Error (I) — R/WC. Indicates that the Phy detected some internal error. PhyRdy Change (N) — R/WC. When set to 1 this bit indicates that the internal PhyRdy signal changed state since the last time this bit was cleared. In the ICH10, this bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled. Software clears this bit by writing a 1 to it. Reserved Internal Error (E) — R/WC. The SATA controller failed due to a master or target abort when attempting to access system memory. Protocol Error (P) — R/WC. A violation of the Serial ATA protocol was detected. Note: The ICH10 does not set this bit for all protocol violations that may occur on the SATA link. Description Attribute: Size: R/WC 32 bits 26 25 24 23 22 21 20 19 18 17 16 15:12 11 10 586 Datasheet SATA Controller Registers (D31:F5) Bit Description Persistent Communication or Data Integrity Error (C) — R/WC. A communication error that was not recovered occurred that is expected to be persistent. Persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. Transient Data Integrity Error (T) — R/WC. A data integrity error occurred that was not recovered by the interface. Reserved. Recovered Communications Error (M) — R/WC. Communications between the device and host was temporarily lost but was re-established. This can arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PhyNRdy signal between the Phy and Link layers. Recovered Data Integrity Error (I) — R/WC. A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. 9 8 7:2 1 0 §§ Datasheet 587 SATA Controller Registers (D31:F5) 588 Datasheet UHCI Controllers Registers 16 16.1 Note: UHCI Controllers Registers PCI Configuration Registers (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) The USB functions may be hidden based on the value of the corresponding bits in the Function Disable Register (see Chipset Configuration Registers). UHCIs must be disabled from highest number to lowest within their specific PCI device. Table 16-1. UHCI Controller PCI Configuration Map UHCI UHCI #1 UHCI #2 UHCI #3 UHCI #4 UHCI #5 UHCI #6 PCI Device:Function D29:F0 D29:F1 D29:F2 D26:F0 D26:F1 D26:F2 or D29:F3 D26:F2 can be configured as D29:F3 during BIOS post. Notes Note: Register address locations that are not shown in Table 16-2 should be treated as Reserved (see Section 9.2 for details). Table 16-2. UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2/F3, D26:F0/ F1/F2) Offset 00–01h 02–03h 04–05h 06–07h 08h 09h 0Ah 0Bh 0Dh 0Eh 20–23h 2C–2Dh 2E–2Fh 34h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC MLT HEADTYP BASE SVID SID CAP_PTR Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Master Latency Timer Header Type Base Address Subsystem Vendor Identification Subsystem Identification Capabilities Pointer UHCI #1-6 Default 8086h See register description 0000h 0290h See register description 00h 03h 0Ch 00h See register description 00000001h 0000h 0000h 50h Type RO RO R/W, RO R/WC, RO RO RO RO RO RO RO R/W, RO R/WO R/WO R/WO Datasheet 589 UHCI Controllers Registers Table 16-2. UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2/F3, D26:F0/ F1/F2) Offset 3Ch 3Dh 50h 51h 52–53h 54h 55h 60h C0–C1h C4h C8h CAh Mnemonic INT_LN INT_PN FLRCID FLRNCP FLRCLV FLRCTRL FLRSTAT USB_RELNUM USB_LEGKEY USB_RES CWP UCR1 Register Name Interrupt Line Interrupt Pin FLR Capability ID FLR Next Capability Pointer FLR Capability Length and Version FLR Control FLR Status Serial Bus Release Number USB Legacy Keyboard/Mouse Control USB Resume Enable Core Well Policy UHCI Configuration Register 1 UHCI #1-6 Default 00h See register description 09h 00h 2006h 00h 00h 10h 2000h 00h 00h 01h Type R/W RO RO RO RO R/W RO RO R/W, RO R/WC R/W R/W R/W NOTE: Refer to the Intel® I/O Controller Hub 10 (ICH10) Family Specification Update for the value of the Revision ID Register. 16.1.1 VID—Vendor Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 00h–01h Default Value: 8086h Bit 15:0 Attribute: Size: Description RO 16 bits Vendor ID — RO. This is a 16-bit value assigned to Intel 16.1.2 DID—Device Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 02h–03h Default Value: See bit description Bit 15:0 Attribute: Size: Description RO 16 bits Device ID — RO. This is a 16-bit value assigned to the Intel® ICH10 USB universal host controllers. Refer to the Intel® I/O Controller Hub (ICH10) Family for the value of the Device ID Register. 590 Datasheet UHCI Controllers Registers 16.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2/ F3, D26:F0/F1/F2) Address Offset: 04h–05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable — R/W. 10 0 = Enable. The function is able to generate its interrupt to the interrupt controller. 1 = Disable. The function is not capable of generating interrupts. The corresponding Interrupt Status bit is not affected by the interrupt enable. Fast Back to Back Enable (FBE) — RO. Hardwired to 0. SERR# Enable — RO. Reserved as 0. Wait Cycle Control (WCC) — RO. Hardwired to 0. Parity Error Response (PER) — RO. Hardwired to 0. VGA Palette Snoop (VPS) — RO. Hardwired to 0. Postable Memory Write Enable (PMWE) — RO. Hardwired to 0. Special Cycle Enable (SCE) — RO. Hardwired to 0. Bus Master Enable (BME) — R/W. 2 1 0 = Disable 1 = Enable. ICH10 can act as a master on the PCI bus for USB transfers. Memory Space Enable (MSE) — RO. Hardwired to 0. I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers. 0 0 = Disable 1 = Enable accesses to the USB I/O registers. The Base Address register for USB should be programmed before this bit is set. Attribute: Size: Description R/W, RO 16 bits 9 8 7 6 5 4 3 Datasheet 591 UHCI Controllers Registers 16.1.4 PCISTS—PCI Status Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 06h–07h Default Value: 0290h Attribute: Size: R/WC, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) — R/WC. 15 0 = No parity error detected. 1 = Set when a data parity error data parity error is detected on writes to the UHCI register space or on read completions returned to the host controller. Reserved. Received Master Abort (RMA) — R/WC. 13 12 0 = No master abort generated by USB. 1 = USB, as a master, generated a master abort. Reserved. Signaled Target Abort (STA) — R/WC. 11 0 = ICH10 did Not terminate transaction for USB function with a target abort. 1 = USB function is targeted with a transaction that the ICH10 terminates with a target abort. DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for DEVSEL# assertion. These read only bits indicate the ICH10's DEVSEL# timing when performing a positive decode. ICH10 generates DEVSEL# with medium timing for USB. Data Parity Error Detected (DPED) — RO. Hardwired to 0. Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. User Definable Features (UDF) — RO. Hardwired to 0. 66 MHz Capable — RO. Hardwired to 0. Capabilities List — RO. Hardwired to 1. Indicates that offset 34h contains a valid capabilities pointer. Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the input of the enable/disable logic. 3 0 = Interrupt is deasserted. 1 = Interrupt is asserted. The value reported in this bit is independent of the value in the Interrupt Enable bit. 2:0 Reserved 14 10:9 8 7 6 5 4 16.1.5 RID—Revision Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID — RO. Refer to the I/O Controller Hub (ICH10) Family Specification Update for the value of the Revision ID Register Intel® 592 Datasheet UHCI Controllers Registers 16.1.6 PI—Programming Interface Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: Default Value: Bit 7:0 Programming Interface — RO. 00h = No specific register level programming interface defined. 09h 00h Attribute: Size: Description RO 8 bits 16.1.7 SCC—Sub Class Code Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: Default Value: Bit 7:0 Sub Class Code (SCC) — RO. 03h = USB host controller. 0Ah 03h Attribute: Size: Description RO 8 bits 16.1.8 BCC—Base Class Code Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: Default Value: Bit 7:0 Base Class Code (BCC) — RO. 0Ch = Serial Bus controller. 0Bh 0Ch Attribute: Size: Description RO 8 bits 16.1.9 MLT—Master Latency Timer Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Master Latency Timer (MLT) — RO. The USB controller is implemented internal to the ICH10 and not arbitrated as a PCI device. Therefore the device does not require a Master Latency Timer. Datasheet 593 UHCI Controllers Registers 16.1.10 HEADTYP—Header Type Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 0Eh Default Value: See Bit Description Attribute: Size: RO 8 bits For UHCI #2, 3, 5 and 6 this register is hardwired to 00h. For UHCI #1 and UHCI #4, bit 7 is determined by the values in the USB Function Disable bits (11:8 of the Function Disable register Chipset Config Registers:Offset 3418h). Bit Description Multi-Function Device — RO. Since the upper functions in this device can be individually hidden, this bit is based on the function-disable bits in Chipset Config Space: Offset 3418h as follows: 0 = Single-function device. (Default for UHCI #2, 3, 5 and 6) 1 = Multi-function device. (Default for UHCI #1 and 4) 6:0 Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration layout. 7 16.1.11 BASE—Base Address Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 20h–23h Default Value: 00000001h Bit 31:16 15:5 4:1 0 Reserved Base Address — R/W. Bits [15:5] correspond to I/O address signals AD [15:5], respectively. This gives 32 bytes of relocatable I/O space. Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate that the base address field in this register maps to I/O space. Attribute: Size: Description R/W, RO 32 bits 16.1.12 SVID — Subsystem Vendor Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 2Ch–2Dh Default Value: 0000h Lockable: No Function Level Reset: No Bit Attribute: Size: Power Well: R/WO 16 bits Core Description Subsystem Vendor ID (SVID) — R/WO. BIOS sets the value in this register to identify the Subsystem Vendor ID. The USB_SVID register, in combination with the USB Subsystem ID register, enables the operating system to distinguish each subsystem from the others. NOTE: The software can write to this register only once per core well reset. Writes should be done as a single, 16-bit cycle. 15:0 594 Datasheet UHCI Controllers Registers 16.1.13 SID — Subsystem Identification Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 2Eh–2Fh Default Value: 0000h Lockable: No Function Level Reset: No Bit Attribute: Size: Power Well: R/WO 16 bits Core Description Subsystem ID (SID) — R/WO. BIOS sets the value in this register to identify the Subsystem ID. The SID register, in combination with the SVID register (D29:F0/F1/F2/ F3, D26:F0/F1/F2:2C), enables the operating system to distinguish each subsystem from other(s). The value read in this register is the same as what was written to the IDE_SID register. NOTE: The software can write to this register only once per core well reset. Writes should be done as a single, 16-bit cycle. 15:0 16.1.14 CAP_PTR—Capabilities Pointer (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: Default Value: Function Level Reset: 34h 50h No Attribute: Size: R/WO 8 bits Bit 7:0 Description Capability Pointer (CAP_PTR) — R/WO. This register points to the next capability in the Function Level Reset capability structure. 16.1.15 INT_LN—Interrupt Line Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: Default Value: Function Level Reset: Bit 7:0 3Ch 00h No Attribute: Size: R/W 8 bits Description Interrupt Line (INT_LN) — RO. This data is not used by the ICH10. It is to communicate to software the interrupt line that the interrupt pin is connected to. Datasheet 595 UHCI Controllers Registers 16.1.16 INT_PN—Interrupt Pin Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 3Dh Default Value: See Description Bit Attribute: Size: Description RO 8 bits Interrupt Line (INT_LN) — RO. This value tells the software which interrupt pin each USB host controller uses. The upper 4 bits are hardwired to 0000b; the lower 4 bits are determine by the Interrupt Pin default values that are programmed in the memorymapped configuration space as follows: UHCI #1 - D29IP.U0P (Chipset Config Registers:Offset 3108:bits 3:0) UHCI #2 - D29IP.U1P (Chipset Config Registers:Offset 3108:bits 7:4) 7:0 UHCI #3 - D29IP.U2P (Chipset Config Registers:Offset 3108:bits 11:8) UHCI #4 - D26IP.U0P (Chipset Config Registers:Offset 3114:bits 3:0) UHCI #5 - D26IP.U1P (Chipset Config Registers:Offset 3114:bits 7:4) UHCI #6 - D26IP.U2P (Chipset Config Registers:Offset 3114:bits 11:8) or UHCI #6 - D29IP.U3P (Chipset Config Registers:Offset 3108:bits 15:12) NOTE: This does not determine the mapping to the PIRQ pins. 16.1.17 FLRCID—Function Level Reset Capability ID (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 50h Default Value: 09h Bit Capability ID — RO. 7:0 13h = If FLRCSSEL = 0 09h (Vendor Specific Capability) = If FLRCSSEL = 1 Attribute: Size: Description RO 8 bits 16.1.18 FLRNCP—Function Level Reset Next Capability Pointer (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 51h Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits A value of 00h indicates that this is the last capability field. 596 Datasheet UHCI Controllers Registers 16.1.19 FLRCLV—Function Level Reset Capability Length and Version (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 52h-53h Default Value: 2006h Attribute: Size: RO, R/WO 16 bits When FLRCSSEL = 0, this register is defined as follows: Bit 15:10 9 Reserved. FLR Capability — R/WO. 1 = Support for Function Level Reset (FLR). TXP Capability — R/WO. 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. Capability Length — RO. This field indicates the # of bytes of this Vendor Specific capability as required by the PCI specification. It ha‘s the value of 06h for the FLR Capability. Description 8 7:0 When FLRCSSEL = 1, this register is defined as follows: Bit 15:12 11:8 7:0 Description Vendor Specific Capability ID — RO. A value of 02h in this field identifies this capability a‘s Function Level Reset. Capability Version — RO. This field indicates the version of the FLR capability. Capability Length — RO. This field indicates the # of bytes of this Vendor Specific capability as required by the PCI specification. It ha‘s the value of 06h for the FLR Capability. 16.1.20 USB_FLRCTRL—FLR Control Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 54h Default Value: 00h Bit 7:1 0 Reserved. Initiate FLR— R/W. Used to initiate FLR transition. a write of ‘1’ initiates FLR transition. Since hardware must not respond to any cycles until FLR completion, the value read by software from this bit i always ‘0’. Attribute: Size: Description R/W 8 bits Datasheet 597 UHCI Controllers Registers 16.1.21 USB_FLRSTAT—FLR Status Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 55h Default Value: 00h Bit 7:1 Reserved. Transaction Pending (TXP)— RO. 0 0 = Indicates completions for all Non-Posted requests have been received. 1 = Indicates the controller has issued Non-Posted request which have not been completed. Attribute: Size: Description RO 8 bits 16.1.22 USB_RELNUM—Serial Bus Release Number Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: 60h Default Value: 10h Bit 7:0 Serial Bus Release Number — RO. 10h = USB controller supports the USB Specification, Release 1.0. Attribute: Size: Description RO 8 bits 16.1.23 USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: C0h–C1h Default Value: 2000h Function Level Reset:No Attribute: Size: R/W, R/WC, RO 16 bits This register is implemented separately in each of the USB UHCI functions. However, the enable and status bits for the trapping logic are OR’d and shared, respectively, since their functionality is not specific to any one host controller. Bit Description SMI Caused by End of Pass-Through (SMIBYENDPS) — R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 7, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred 14 Reserved PCI Interrupt Enable (USBPIRQEN) — R/W. This bit is used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note that, when disabled, it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 0 = Disable 1 = Enable 15 13 598 Datasheet UHCI Controllers Registers Bit Description SMI Caused by USB Interrupt (SMIBYUSB) — RO. This bit indicates if an interrupt event occurred from this controller. The interrupt from the controller is taken before the enable in bit 13 has any effect to create this read-only bit. Note that even if the corresponding enable bit is not set in Bit 4, this bit may still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software should clear the interrupts via the USB controllers. Writing a 1 to this bit will have no effect. 1 = Event Occurred. SMI Caused by Port 64 Write (TRAPBY64W) — R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 3, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI Caused by Port 64 Read (TRAPBY64R) — R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI Caused by Port 60 Write (TRAPBY60W) — R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 1, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI Caused by Port 60 Read (TRAPBY60R) — R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI at End of Pass-Through Enable (SMIATENDPS) — R/W. This bit enables SMI at the end of a pass-through. This can occur if an SMI is generated in the middle of a pass-through, and needs to be serviced later. 0 = Disable 1 = Enable Pass Through State (PSTATE) — RO. 0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0. 1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence. A20Gate Pass-Through Enable (A20PASSEN) — R/W. 0 = Disable. 1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the SMI status bits. SMI on USB IRQ Enable (USBSMIEN) — R/W. 0 = Disable 1 = Enable. USB interrupt will cause an SMI event. 12 11 10 9 8 7 6 5 4 Datasheet 599 UHCI Controllers Registers Bit 3 Description SMI on Port 64 Writes Enable (64WEN) — R/W. 0 = Disable 1 = Enable. A 1 in bit 11 will cause an SMI event. SMI on Port 64 Reads Enable (64REN) — R/W. 0 = Disable 1 = Enable. A 1 in bit 10 will cause an SMI event. SMI on Port 60 Writes Enable (60WEN) — R/W. 0 = Disable 1 = Enable. A 1 in bit 9 will cause an SMI event. SMI on Port 60 Reads Enable (60REN) — R/W. 0 = Disable 1 = Enable. A 1 in bit 8 will cause an SMI event. 2 1 0 16.1.24 USB_RES—USB Resume Enable Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: C4h Default Value: 00h Function Level Reset:No Bit 7:2 Reserved PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events. 1 0 = The USB controller will not look at this port for a wakeup event. 1 = The USB controller will monitor this port for remote wakeup and connect/ disconnect events. PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events. 0 0 = The USB controller will not look at this port for a wakeup event. 1 = The USB controller will monitor this port for remote wakeup and connect/ disconnect events. Attribute: Size: R/W 8 bits Description 600 Datasheet UHCI Controllers Registers 16.1.25 CWP—Core Well Policy Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: C8h Default Value: 00h Function Level Reset: No Bit 7:3 2 Reserved Host Controller Alignment Enable (HCAE) — R/W. Setting this bit aligns the host controller’s start of the first frame to a central 1ms heartbeat. Setting this bit for each controller maintains alignment. HCHALTED Bit Read Mode (HBM) — R/W. This bit controls what SW sees on reads of the HCHALTED bit in the interval between when SW has set the RUN bit and the first heartbeat. 1 0 = Software reads the delayed value of HCHALTED (sees a 1 while the controller is waiting for the heartbeat). 1 = Software reads the value it would expect to see without the delay (sees a 0 even while the controller is waiting for the heartbeat). Static Bus Master Status Policy Enable (SBMSPE) — R/W. 0 = The UHCI host controller dynamically sets the Bus Master status bit (Power Management 1 Status Register,[PMBASE+00h], bit 4) based on the memory accesses that are scheduled. The default setting provides a more accurate indication of snoopable memory accesses in order to help with software-invoked entry to C3 and C4 power states 1 = The UHCI host controller statically forces the Bus Master Status bit in power management space to 1 whenever the HCHalted bit (USB Status Register, Base+02h, bit 5) is cleared. NOTE: The PCI Power Management registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte aligned). Attribute: Size: R/W 8 bits Description 0 16.1.26 UCR1—UCHI Configuration Register 1 (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2) Address Offset: Default Value: Bit 7:1 Reserved Initiator/Target Arbitration Disable (ITAD) — R/W. 0 When this bit is set to 1, the UHCI controller will force DMA read requests to return prior to completing transactions as a target. When this bit is set to 0, the UHCI controller will allow completions from target transactions to complete independent of the state of forward progress of the master. CAh 01h Attribute: Size: Description R/W 8 bits Datasheet 601 UHCI Controllers Registers 16.2 USB I/O Registers Some of the read/write register bits that deal with changing the state of the USB hub ports function such that on read back they reflect the current state of the port, and not necessarily the state of the last write to the register. This allows the software to poll the state of the port and wait until it is in the proper state before proceeding. A host controller reset, global reset, or port reset will immediately terminate a transfer on the affected ports and disable the port. This affects the USBCMD register, bit 4 and the PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail. Table 16-3. USB I/O Registers BASE + Offset 00–01h 02–03h 04–05h 06–07h 08–0Bh 0Ch 0D–0Fh 10–11h 12–13h Mnemonic USBCMD USBSTS USBINTR FRNUM FRBASEADD SOFMOD — PORTSC0 PORTSC1 Register Name USB Command USB Status USB Interrupt Enable Frame Number Frame List Base Address Start of Frame Modify Reserved Port 0 Status/Control Port 1 Status/Control Default 0000h 0020h 0000h 0000h Undefined 40h — 0080h 0080h Type R/W R/WC R/W R/W (see Note 1) R/W R/W — R/WC, RO, R/W (see Note 1) R/WC, RO, R/W (see Note 1) NOTE: 1. These registers are WORD writable only. Byte writes to these registers have unpredictable effects. 602 Datasheet UHCI Controllers Registers 16.2.1 USBCMD—USB Command Register I/O Offset: Default Value: Base + (00h–01h) 0000h Attribute: Size: R/W 16 bits The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. The table following the bit description provides additional information on the operation of the Run/Stop and Debug bits. Bit 15:7 Reserved Loop Back Test Mode — R/W. 8 0 = Disable loop back test mode. 1 = ICH10 is in loop back test mode. When both ports are connected together, a write to one port will be seen on the other port and the data will be stored in I/O offset 18h. Max Packet (MAXP) — R/W. This bit selects the maximum packet size that can be used for full speed bandwidth reclamation at the end of a frame. This value is used by the host controller to determine whether it should initiate another transaction based on the time remaining in the SOF counter. Use of reclamation packets larger than the programmed size will cause a Babble error if executed during the critical window at frame end. The Babble error results in the offending endpoint being stalled. Software is responsible for ensuring that any packet which could be executed under bandwidth reclamation be within this size limit. 0 = 32 bytes 1 = 64 bytes Configure Flag (CF) — R/W. This bit has no effect on the hardware. It is provided only as a semaphore service for software. 6 0 = Indicates that software has not completed host controller configuration. 1 = HCD software sets this bit as the last action in its process of configuring the host controller. Software Debug (SWDBG) — R/W. The SWDBG bit must only be manipulated when the controller is in the stopped state. This can be determined by checking the HCHalted bit in the USBSTS register. 5 0 = Normal Mode. 1 = Debug mode. In SW Debug mode, the host controller clears the Run/Stop bit after the completion of each USB transaction. The next transaction is executed when software sets the Run/Stop bit back to 1. Force Global Resume (FGR) — R/W. 0 = Software resets this bit to 0 after 20 ms has elapsed to stop sending the Global Resume signal. At that time all USB devices should be ready for bus activity. The 1 to 0 transition causes the port to send a low speed EOP signal. This bit will remain a 1 until the EOP has completed. 1 = Host controller sends the Global Resume signal on the USB, and sets this bit to 1 when a resume event (connect, disconnect, or K-state) is detected while in global suspend mode. Description 7 4 Datasheet 603 UHCI Controllers Registers Bit Description Enter Global Suspend Mode (EGSM) — R/W. 0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or after writing bit 4 to 0. 1 = Host controller enters the Global Suspend mode. No USB transactions occur during this time. The Host controller is able to receive resume signals from USB and interrupt the system. Software must ensure that the Run/Stop bit (bit 0) is cleared prior to setting this bit. Global Reset (GRESET) — R/W. 0 = This bit is reset by the software after a minimum of 10 ms has elapsed as specified in Chapter 7 of the USB Specification. 1 = Global Reset. The host controller sends the global reset signal on the USB and then resets all its logic, including the internal hub registers. The hub registers are reset to their power on state. Chip Hardware Reset has the same effect as Global Reset (bit 2), except that the host controller does not send the Global Reset on USB. Host Controller Reset (HCRESET) — R/W. The effects of HCRESET on Hub registers are slightly different from Chip Hardware Reset and Global USB Reset. The HCRESET affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of each port. HCRESET resets the state machines of the host controller including the Connect/ Disconnect state machine (one for each port). When the Connect/Disconnect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. This virtual disconnect causes the port to be disabled. This disconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the PORTSC to get set. The disconnect also causes bit 8 of PORTSC to reset. About 64 bit times after HCRESET goes to 0, the connect and low-speed detect will take place, and bits 0 and 8 of the PORTSC will change accordingly. 0 = Reset by the host controller when the reset process is complete. 1 = Reset. When this bit is set, the host controller module resets its internal timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. Run/Stop (RS) — R/W. When set to 1, the ICH10 proceeds with execution of the schedule. The ICH10 continues execution as long as this bit is set. When this bit is cleared, the ICH10 completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. The host controller clears this bit when the following fatal errors occur: consistency check failure, or memory access errors. 0 = Stop 1 = Run NOTE: This bit should only be cleared if there are no active Transaction Descriptors in the executable schedule or software will reset the host controller prior to setting this bit again. 3 2 1 0 604 Datasheet UHCI Controllers Registers Table 16-4. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation SWDBG (Bit 5) Run/Stop (Bit 0) Description If executing a command, the host controller completes the command and then stops. The 1.0 ms frame counter is reset and command list execution resumes from start of frame using the frame list pointer selected by the current value in the FRNUM register. (While Run/ Stop=0, the FRNUM register (BASE + 06h) can be reprogrammed). Execution of the command list resumes from Start Of Frame using the frame list pointer selected by the current value in the FRNUM register. The host controller remains running until the Run/Stop bit is cleared (by software or hardware). If executing a command, the host controller completes the command and then stops and the 1.0 ms frame counter is frozen at its current value. All status are preserved. The host controller begins execution of the command list from where it left off when the Run/Stop bit is set. Execution of the command list resumes from where the previous execution stopped. The Run/Stop bit is set to 0 by the host controller when a TD is being fetched. This causes the host controller to stop again after the execution of the TD (single step). When the host controller has completed execution, the HC Halted bit in the Status Register is set. 0 0 0 1 1 0 1 1 When the USB host controller is in Software Debug Mode (USBCMD Register bit 5=1), the single stepping software debug operation is as follows: To Enter Software Debug Mode: 1. HCD puts host controller in Stop state by setting the Run/Stop bit to 0. 2. HCD puts host controller in Debug Mode by setting the SWDBG bit to 1. 3. HCD sets up the correct command list and Start Of Frame value for starting point in the Frame List Single Step Loop. 4. HCD sets Run/Stop bit to 1. 5. Host controller executes next active TD, sets Run/Stop bit to 0, and stops. 6. HCD reads the USBCMD register to check if the single step execution is completed (HCHalted=1). 7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to end Software Debug mode. 8. HCD ends Software Debug mode by setting SWDBG bit to 0. 9. HCD sets up normal command list and Frame List table. 10. HCD sets Run/Stop bit to 1 to resume normal schedule execution. In Software Debug mode, when the Run/Stop bit is set, the host controller starts. When a valid TD is found, the Run/Stop bit is reset. When the TD is finished, the HCHalted bit in the USBSTS register (bit 5) is set. The SW Debug mode skips over inactive TDs and only halts after an active TD has been executed. When the last active TD in a frame has been executed, the host controller waits until the next SOF is sent and then fetches the first TD of the next frame before halting. Datasheet 605 UHCI Controllers Registers This HCHalted bit can also be used outside of Software Debug mode to indicate when the host controller has detected the Run/Stop bit and has completed the current transaction. Outside of the Software Debug mode, setting the Run/Stop bit to 0 always resets the SOF counter so that when the Run/Stop bit is set the host controller starts over again from the frame list location pointed to by the Frame List Index (see FRNUM Register description) rather than continuing where it stopped. 16.2.2 USBSTS—USB Status Register I/O Offset: Default Value: Base + (02h–03h) 0020h Attribute: Size: R/WC 16 bits This register indicates pending interrupts and various states of the host controller. The status resulting from a transaction on the serial bus is not indicated in this register. Bit 15:6 Reserved HCHalted — R/WC. 5 0 = Software clears this bit by writing a 1 to it. 1 = The host controller has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the host controller hardware (debug mode or an internal error). Default. Host Controller Process Error — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = The host controller has detected a fatal error. This indicates that the host controller suffered a consistency check failure while processing a Transfer Descriptor. An example of a consistency check failure would be finding an invalid PID field while processing the packet header portion of the TD. When this error occurs, the host controller clears the Run/Stop bit in the Command register (D29:F0/F1/F2/F3, D26:F0/F1/F2:BASE + 00h, bit 0) to prevent further schedule execution. A hardware interrupt is generated to the system. Host System Error — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = A serious error occurred during a host system access involving the host controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the host controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. A hardware interrupt is generated to the system. Resume Detect (RSM_DET) — R/WC. 2 0 = Software clears this bit by writing a 1 to it. 1 = The host controller received a “RESUME” signal from a USB device. This is only valid if the Host controller is in a global suspend state (Command register, D29:F0/ F1/F2/F3, D26:F0/F1/F2:BASE + 00h, bit 3 = 1). USB Error Interrupt — R/WC. 1 0 = Software clears this bit by writing a 1 to it. 1 = Completion of a USB transaction resulted in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit (D29:F0/F1/F2/F3, D26:F0/F1/F2:BASE + 04h, bit 2) set, both this bit and Bit 0 are set. USB Interrupt (USBINT) — R/WC. 0 0 = Software clears this bit by writing a 1 to it. 1 = The host controller sets this bit when the cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set. Also set when a short packet is detected (actual length field in TD is less than maximum length field in TD), and short packet detection is enabled in that TD. Description 4 3 606 Datasheet UHCI Controllers Registers 16.2.3 USBINTR—USB Interrupt Enable Register I/O Offset: Default Value: Base + (04h–05h) 0000h Attribute: Size: R/W 16 bits This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Fatal errors (host controller processor error, (D29:F0/F1/F2, D26:F0/F1:BASE + 02h, bit 4, USBSTS Register) cannot be disabled by the host controller. Interrupt sources that are disabled in this register still appear in the Status Register to allow the software to poll for events. Bit 15:5 4 3 Reserved Scratchpad (SP) — R/W. Short Packet Interrupt Enable — R/W. 0 = Disabled. 1 = Enabled. Interrupt on Complete Enable (IOC) — R/W. 2 0 = Disabled. 1 = Enabled. Resume Interrupt Enable — R/W. 1 0 = Disabled. 1 = Enabled. Timeout/CRC Interrupt Enable — R/W. 0 0 = Disabled. 1 = Enabled. Description 16.2.4 FRNUM—Frame Number Register I/O Offset: Word Writes) Default Value: Base + (06–07h) 0000h Attribute: Size: R/W (Writes must be 16 bits Bits [10:0] of this register contain the current frame number that is included in the frame SOF packet. This register reflects the count value of the internal frame number counter. Bits [9:0] are used to select a particular entry in the Frame List during scheduled execution. This register is updated at the end of each frame time. This register must be written as a word. Byte writes are not supported. This register cannot be written unless the host controller is in the STOPPED state as indicated by the HCHalted bit (D29:F0/F1/F2/F3, D26:F0/F1/F2:BASE + 02h, bit 5). A write to this register while the Run/Stop bit is set (D29:F0/F1/F2/F3, D26:F0/F1/F2:BASE + 00h, bit 0) is ignored. Bit 15:11 Reserved Frame List Current Index/Frame Number — R/W. This field provides the frame number in the SOF Frame. The value in this register increments at the end of each time frame (approximately every 1 ms). In addition, bits [9:0] are used for the Frame List current index and correspond to memory address signals [11:2]. Description 10:0 Datasheet 607 UHCI Controllers Registers 16.2.5 FRBASEADD—Frame List Base Address Register I/O Offset: Default Value: Base + (08h–0Bh) Undefined Attribute: Size: R/W 32 bits This 32-bit register contains the beginning address of the Frame List in the system memory. HCD loads this register prior to starting the schedule execution by the host controller. When written, only the upper 20 bits are used. The lower 12 bits are written as 0s (4 KB alignment). The contents of this register are combined with the frame number counter to enable the host controller to step through the Frame List in sequence. The two least significant bits are always 00. This requires dword-alignment for all list entries. This configuration supports 1024 Frame List entries. Bit 31:12 11:0 Description Base Address — R/W. These bits correspond to memory address signals [31:12], respectively. Reserved 16.2.6 SOFMOD—Start of Frame Modify Register I/O Offset: Default Value: Base + (0Ch) 40h Attribute: Size: R/W 8 bits This 1-byte register is used to modify the value used in the generation of SOF timing on the USB. Only the 7 least significant bits are used. When a new value is written into these 7 bits, the SOF timing of the next frame will be adjusted. This feature can be used to adjust out any offset from the clock source that generates the clock that drives the SOF counter. This register can also be used to maintain real time synchronization with the rest of the system so that all devices have the same sense of real time. Using this register, the frame length can be adjusted across the full range required by the USB specification. Its initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. It may be reprogrammed by USB system software at any time. Its value will take effect from the beginning of the next frame. This register is reset upon a host controller reset or global reset. Software must maintain a copy of its value for reprogramming if necessary. Bit 7 Reserved SOF Timing Value — R/W. Guidelines for the modification of frame time are contained in Chapter 7 of the USB Specification. The SOF cycle time (number of SOF counter clock periods to generate a SOF frame length) is equal to 11936 + value in this field. The default value is decimal 64 which gives a SOF cycle time of 12000. For a 12 MHz SOF counter clock input, this produces a 1 ms Frame period. The following table indicates what SOF Timing Value to program into this field for a certain frame period. Frame Length (# 12 MHz Clocks) (decimal) 6:0 11936 11937 — 11999 12000 12001 — 12062 12063 SOF Timing Value (this register) (decimal) 0 1 — 63 64 65 — 126 127 Description 608 Datasheet UHCI Controllers Registers 16.2.7 PORTSC[0,1]—Port Status and Control Register I/O Offset: Default Value: Port 0/2/4/6/8/10: Base + (10h–11h) Port 1/3/5/7/9/11: Base + (12h–13h) 0080h Attribute: R/WC, RO, R/W (Word writes only) Size: 16 bits Note: For UHCI #1 (D29:F0), this applies to ICH10 USB ports 0 and 1; for UHCI #2 (D29:F1), this applies to ICH10 USB ports 2 and 3; for UHCI #3 (D29:F2), this applies to ICH10 USB ports 4 and 5, for UHCI #4 (D26:F0), this applies to ICH10 USB ports 6 and 7, for UHCI #5 (D26:F1), this applies to ICH10 USB ports 8 and 9 and for UHCI #6 (D26:F2 or D29:F3), this applies to ICH10 USB ports 10 and 11. After a power-up reset, global reset, or host controller reset, the initial conditions of a port are: no device connected, Port disabled, and the bus line status is 00 (singleended 0). Port Reset and Enable Sequence When software wishes to reset a USB device it will assert the Port Reset bit in the Port Status and Control register. The minimum reset signaling time is 10 mS and is enforced by software. To complete the reset sequence, software clears the port reset bit. The Intel UHCI controller must re-detect the port connect after reset signaling is complete before the controller will allow the port enable bit to de set by software. This time is approximately 5.3 μs. Software has several possible options to meet the timing requirement and a partial list is enumerated below: • Iterate a short wait, setting the port enable bit and reading it back to see if the enable bit is set. • Poll the connect status bit and wait for the hardware to recognize the connect prior to enabling the port. • Wait longer than the hardware detect time after clearing the port reset and prior to enabling the port. Bit 15:13 Reserved. Suspend — R/W. This bit should not be written to a 1 if global suspend is active (bit 3=1 in the USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows: Bits [12,2] X,0 0, 1 1, 1 Hub State Disable Enable Suspend Description 12 When in suspend state, downstream propagation of data is blocked on this port, except for single-ended 0 resets (global reset and port reset). The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. 1 = Port in suspend state. 0 = Port not in suspend state. NOTE: Normally, if a transaction is in progress when this bit is set, the port will be suspended when the current transaction completes. However, in the case of a specific error condition (out transaction with babble), the ICH10 may issue a start-of-frame, and then suspend the port. Overcurrent Indicator — R/WC. Set by hardware. 11 0 = Software clears this bit by writing a 1 to it. 1 = Overcurrent pin has gone from inactive to active on this port. Datasheet 609 UHCI Controllers Registers Bit 10 Description Overcurrent Active — RO. This bit is set and cleared by hardware. 0 = Indicates that the overcurrent pin is inactive (high). 1 = Indicates that the overcurrent pin is active (low). Port Reset — R/W. 0 = Port is not in Reset. 1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling. Low Speed Device Attached (LS) — RO. 0 = Full speed device is attached. 1 = Low speed device is attached to this port. Reserved — RO. Always read as 1. Resume Detect (RSM_DET) — R/W. Software sets this bit to a 1 to drive resume signaling. The host controller sets this bit to a 1 if a J-to-K transition is detected for at least 32 microseconds while the port is in the Suspend state. The ICH10 will then reflect the K-state back onto the bus as long as the bit remains a 1, and the port is still in the suspend state (bit 12,2 are ‘11’). Writing a 0 (from 1) causes the port to send a low speed EOP. This bit will remain a 1 until the EOP has completed. 0 = No resume (K-state) detected/driven on port. 1 = Resume detected/driven on port. 9 8 7 6 5:4 Line Status — RO. These bits reflect the D+ (bit 4) and D– (bit 5) signals lines’ logical levels. These bits are used for fault detect and recovery as well as for USB diagnostics. This field is updated at EOF2 time (See Chapter 11 of the USB Specification). Port Enable/Disable Change — R/WC. For the root hub, this bit gets set only when a port is disabled due to disconnect on that port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). 0 = No change. Software clears this bit by writing a 1 to the bit location. 1 = Port enabled/disabled status has changed. Port Enabled/Disabled (PORT_EN) — R/W. Ports can be enabled by host software only. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction currently in progress on the USB. 0 = Disable 1 = Enable Connect Status Change — R/WC. This bit indicates that a change has occurred in the port’s Current Connect Status (see bit 0). The hub device sets this bit for any changes to the port device connect status, even if system software has not cleared a connect status change. If, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting” an alreadyset bit (i.e., the bit will remain set). However, the hub transfers the change bit only once when the host controller requests a data transfer to the Status Change endpoint. System software is responsible for determining state change history in such a case. 0 = No change. Software clears this bit by writing a 1 to it. 1 = Change in Current Connect Status. Current Connect Status — RO. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 0 = No device is present. 1 = Device is present on port. 3 2 1 0 §§ 610 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17 17.1 Note: EHCI Controller Registers (D29:F7, D26:F7) USB EHCI Configuration Registers (USB EHCI—D29:F7, D26:F7) Register address locations that are not shown in Table 17-1 should be treated as Reserved (see Section 9.2 for details). Table 17-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F7, D26:F7) (Sheet 1 of 2) Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 0Dh 10h–13h 2Ch–2Dh 2Eh–2Fh 34h 3Ch 3Dh 50h 51h 52h–53h 54h–55h 58h 59h 5Ah–5Bh 60h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC PMLT MEM_BASE SVID SID CAP_PTR INT_LN INT_PN PWR_CAPID NXT_PTR1 PWR_CAP PWR_CNTL_STS DEBUG_CAPID NXT_PTR2 DEBUG_BASE USB_RELNUM Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Primary Master Latency Timer Memory Base Address USB EHCI Subsystem Vendor Identification USB EHCI Subsystem Identification Capabilities Pointer Interrupt Line Interrupt Pin PCI Power Management Capability ID Next Item Pointer Power Management Capabilities Power Management Control/ Status Debug Port Capability ID Next Item Pointer #2 Debug Port Base Offset USB Release Number Default Value 8086h See register description 0000h 0290h See register description 20h 03h 0Ch 00h 00000000h XXXXh XXXXh 50h 00h See register description 01h 58h C9C2h 0000h 0Ah 98h 20A0h 20h Type RO RO R/W, RO R/WC, RO RO RO RO RO RO R/W, RO R/W R/W RO R/W RO RO R/W R/W R/W, R/WC, RO RO RO RO RO Datasheet 611 EHCI Controller Registers (D29:F7, D26:F7) Table 17-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F7, D26:F7) (Sheet 2 of 2) Offset 61h 62h–63h 64h–67h 68h–6Bh 6Ch–6Fh 70h–73h 74h–7Fh 80h 84h 98h 99h 9Ah-9Bh 9Ch 9Dh FCh Mnemonic FL_ADJ PWAKE_CAP — LEG_EXT_CAP LEG_EXT_CS SPECIAL_SMI — ACCESS_CNTL EHCIIR1 FLR_CID FLR_NEXT FLR_CLV FLR_CTRL FLR_STAT EHCIIR2 Register Name Frame Length Adjustment Port Wake Capabilities Reserved USB EHCI Legacy Support Extended Capability USB EHCI Legacy Extended Support Control/Status Intel Specific USB 2.0 SMI Reserved Access Control EHCI Initialization Register 1 FLR Capability ID FLR Next Capability Pointer FLR Capability Length and Version FLR Control FLR Status EHCI Initialization Register 2 Default Value 20h 01FFh — 00000001h 00000000h 00000000h — 00h 01h 09h 00h 2006h 00h 00h 20001706h Type R/W R/W — R/W, RO R/W, R/WC, RO R/W, R/WC — R/W R/W, RWL RO RO RO, R/WO R/W RO R/W Note: All configuration registers in this section are in the core well and reset by a core well reset and the D3-to-D0 warm reset, except as noted. 17.1.1 VID—Vendor Identification Register (USB EHCI—D29:F7, D26:F7) Offset Address: 00h–01h Default Value: 8086h Bit 15:0 Attribute: Size: Description RO 16 bits Vendor ID — RO. This is a 16-bit value assigned to Intel. 17.1.2 DID—Device Identification Register (USB EHCI—D29:F7, D26:F7) Offset Address: 02h–03h Default Value: See bit description Bit 15:0 Attribute: Size: Description RO 16 bits Device ID — RO. This is a 16-bit value assigned to the Intel® ICH10 USB EHCI controller. Refer to the Intel® I/O Controller Hub (ICH10) Family Specification Update for the value of the Device ID Register. 612 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.1.3 PCICMD—PCI Command Register (USB EHCI—D29:F7, D26:F7) Address Offset: 04h–05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable — R/W. 10 0 = The function is capable of generating interrupts. 1 = The function can not generate its interrupt to the interrupt controller. Note that the corresponding Interrupt Status bit (D29:F7, D26:F7:06h, bit 3) is not affected by the interrupt enable. 9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0. SERR# Enable (SERR_EN) — R/W 0 = Disables EHC’s capability to generate an SERR#. 1 = The Enhanced Host Controller (EHC) is capable of generating (internally) SERR# in the following cases: 8 • • • When it receives a completion status other than “successful” for one of its DMA -initiated memory reads on DMI (and subsequently on its internal interface). When it detects an address or command parity error and the Parity Error Response bit is set. When it detects a data parity error (when the data is going into the EHC) and the Parity Error Response bit is set. Attribute: Size: Description R/W, RO 16 bits 7 Wait Cycle Control (WCC) — RO. Hardwired to 0. Parity Error Response (PER) — R/W. 0 = The EHC is not checking for correct parity (on its internal interface). 1 = The EHC is checking for correct parity (on its internal interface) and halt operation when bad parity is detected during the data phase. 6 NOTE: If the EHC detects bad parity on the address or command phases when the bit is set to 1, the host controller does not take the cycle. It halts the host controller (if currently not halted) and sets the Host System Error bit in the USBSTS register. This applies to both requests and completions from the system interface. This bit must be set in order for the parity errors to generate SERR#. VGA Palette Snoop (VPS) — RO. Hardwired to 0. Postable Memory Write Enable (PMWE) — RO. Hardwired to 0. Special Cycle Enable (SCE) — RO. Hardwired to 0. Bus Master Enable (BME) — R/W. 0 = Disables this functionality. 1 = Enables the ICH10 to act as a master on the PCI bus for USB transfers. Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory Space registers. 5 4 3 2 1 0 = Disables this functionality. 1 = Enables accesses to the USB 2.0 registers. The Base Address register (D29:F7, D26:F7:10h) for USB 2.0 should be programmed before this bit is set. I/O Space Enable (IOSE) — RO. Hardwired to 0. 0 Datasheet 613 EHCI Controller Registers (D29:F7, D26:F7) 17.1.4 PCISTS—PCI Status Register (USB EHCI—D29:F7, D26:F7) Address Offset: 06h–07h Default Value: 0290h Attribute: Size: R/WC, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) — R/WC. 15 0 = No parity error detected. 1 = This bit is set by the ICH10 when a parity error is seen by the EHCI controller, regardless of the setting of bit 6 or bit 8 in the Command register or any other conditions. Signaled System Error (SSE) — R/WC. 14 0 = No SERR# signaled by ICH10. 1 = This bit is set by the ICH10 when it signals SERR# (internally). The SER_EN bit (bit 8 of the Command Register) must be 1 for this bit to be set. Received Master Abort (RMA) — R/WC. 13 0 = No master abort received by EHC on a memory access. 1 = This bit is set when EHC, as a master, receives a master abort status on a memory access. This is treated as a Host Error and halts the DMA engines. This event can optionally generate an SERR# by setting the SERR# Enable bit. Received Target Abort (RTA) — R/WC. 12 0 = No target abort received by EHC on memory access. 1 = This bit is set when EHC, as a master, receives a target abort status on a memory access. This is treated as a Host Error and halts the DMA engines. This event can optionally generate an SERR# by setting the SERR# Enable bit (D29:F7, D26:F7:04h, bit 8). Signaled Target Abort (STA) — RO. This bit is used to indicate when the EHCI function responds to a cycle with a target abort. There is no reason for this to happen, so this bit is hardwired to 0. DEVSEL# Timing Status (DEVT_STS) — RO. This 2-bit field defines the timing for DEVSEL# assertion. Master Data Parity Error Detected (DPED) — R/WC. 8 0 = No data parity error detected on USB2.0 read completion packet. 1 = This bit is set by the ICH10 when a data parity error is detected on a USB 2.0 read completion packet on the internal interface to the EHCI host controller and bit 6 of the Command register is set to 1. Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. User Definable Features (UDF) — RO. Hardwired to 0. 66 MHz Capable (66 MHz _CAP) — RO. Hardwired to 0. Capabilities List (CAP_LIST) — RO. Hardwired to 1 indicating that offset 34h contains a valid capabilities pointer. Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the input of the enable/disable logic. 3 0 = This bit will be 0 when the interrupt is deasserted. 1 = This bit is a 1 when the interrupt is asserted. The value reported in this bit is independent of the value in the Interrupt Enable bit. 2:0 Reserved 11 10:9 7 6 5 4 614 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.1.5 RID—Revision Identification Register (USB EHCI—D29:F7, D26:F7) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID — RO. Refer to the Intel® I/O Controller Hub (ICH10) Family Specification Update for the value of the Revision ID Register 17.1.6 PI—Programming Interface Register (USB EHCI—D29:F7, D26:F7) Address Offset: 09h Default Value: 20h Bit 7:0 Attribute: Size: Description RO 8 bits Programming Interface — RO. A value of 20h indicates that this USB 2.0 host controller conforms to the EHCI Specification. 17.1.7 SCC—Sub Class Code Register (USB EHCI—D29:F7, D26:F7) Address Offset: 0Ah Default Value: 03h Bit 7:0 Sub Class Code (SCC) — RO. 03h = Universal serial bus host controller. Attribute: Size: Description RO 8 bits 17.1.8 BCC—Base Class Code Register (USB EHCI—D29:F7, D26:F7) Address Offset: 0Bh Default Value: 0Ch Bit 7:0 Base Class Code (BCC) — RO. 0Ch = Serial bus controller. Attribute: Size: Description RO 8 bits Datasheet 615 EHCI Controller Registers (D29:F7, D26:F7) 17.1.9 PMLT—Primary Master Latency Timer Register (USB EHCI—D29:F7, D26:F7) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI controller is internally implemented with arbitration on an interface (and not PCI), it does not need a master latency timer. 17.1.10 MEM_BASE—Memory Base Address Register (USB EHCI—D29:F7, D26:F7) Address Offset: 10h–13h Default Value: 00000000h Bit 31:10 9:4 3 2:1 0 Attribute: Size: Description R/W, RO 32 bits Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10], respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries. Reserved Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched. Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere within 32-bit address space. Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address field in this register maps to memory space. 17.1.11 SVID—USB EHCI Subsystem Vendor ID Register (USB EHCI—D29:F7, D26:F7) Address Offset: 2Ch–2Dh Default Value: XXXXh Reset: None Bit Attribute: Size: R/W 16 bits Description Subsystem Vendor ID (SVID) — R/W. This register, in combination with the USB 2.0 Subsystem ID register, enables the operating system to distinguish each subsystem from the others. NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7, D26:F7:80h, bit 0) is set to 1. 15:0 616 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.1.12 SID—USB EHCI Subsystem ID Register (USB EHCI—D29:F7, D26:F7) Address Offset: 2Eh–2Fh Default Value: XXXXh Reset: None Bit Attribute: Size: R/W 16 bits Description Subsystem ID (SID) — R/W. BIOS sets the value in this register to identify the Subsystem ID. This register, in combination with the Subsystem Vendor ID register, enables the operating system to distinguish each subsystem from other(s). NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7, D26:F7:80h, bit 0) is set to 1. 15:0 17.1.13 CAP_PTR—Capabilities Pointer Register (USB EHCI—D29:F7, D26:F7) Address Offset: 34h Default Value: 50h Bit 7:0 Attribute: Size: Description RO 8 bits Capabilities Pointer (CAP_PTR) — RO. This register points to the starting offset of the USB 2.0 capabilities ranges. 17.1.14 INT_LN—Interrupt Line Register (USB EHCI—D29:F7, D26:F7) Address Offset: 3Ch Default Value: 00h Function Level Reset: No Bit 7:0 Attribute: Size: R/W 8 bits Description Interrupt Line (INT_LN) — R/W. This data is not used by the Intel® ICH10. It is used as a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to. 17.1.15 INT_PN—Interrupt Pin Register (USB EHCI—D29:F7, D26:F7) Address Offset: 3Dh Default Value: See Description Bit Attribute: Size: Description RO 8 bits 7:0 Interrupt Pin — RO. This reflects the value of D29IP.EIP (Chipset Config Registers:Offset 3108:bits 31:28) or D26IP.EIP (Chipset Config Registers:Offset 3114:bits 31:28). NOTE: Bits 7:4 are always 0h Datasheet 617 EHCI Controller Registers (D29:F7, D26:F7) 17.1.16 PWR_CAPID—PCI Power Management Capability ID Register (USB EHCI—D29:F7, D26:F7) Address Offset: 50h Default Value: 01h Bit 7:0 Attribute: Size: Description RO 8 bits Power Management Capability ID — RO. A value of 01h indicates that this is a PCI Power Management capabilities field. 17.1.17 NXT_PTR1—Next Item Pointer #1 Register (USB EHCI—D29:F7, D26:F7) Address Offset: 51h Default Value: 58h Bit Attribute: Size: Description R/W 8 bits 7:0 Next Item Pointer 1 Value — R/W (special). This register defaults to 58h, which indicates that the next capability registers begin at configuration offset 58h. This register is writable when the WRT_RDONLY bit (D29:F7, D26:F7:80h, bit 0) is set. This allows BIOS to effectively hide the Debug Port capability registers, if necessary. This register should only be written during system initialization before the plug-and-play software has enabled any master-initiated traffic. Only values of 58h (Debug Port visible) and 00h (Debug Port invisible) are expected to be programmed in this register. NOTE: Register not reset by D3-to-D0 warm reset. 618 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.1.18 PWR_CAP—Power Management Capabilities Register (USB EHCI—D29:F7, D26:F7) Address Offset: 52h–53h Default Value: C9C2h Bit Attribute: Size: Description R/W, RO 16 bits 15:11 PME Support (PME_SUP) — R/W. This 5-bit field indicates the power states in which the function may assert PME#. The Intel® ICH10 EHC does not support the D1 or D2 states. For all other states, the ICH10 EHC is capable of generating PME#. Software should never need to modify this field. D2 Support (D2_SUP) — RO. 0 = D2 State is not supported D1 Support (D1_SUP) — RO. 0 = D1 State is not supported Auxiliary Current (AUX_CUR) — R/W. The ICH10 EHC reports 375 mA maximum suspend well current required when in the D3COLD state. Device Specific Initialization (DSI)— RO. The ICH10 reports 0, indicating that no device-specific initialization is required. Reserved PME Clock (PME_CLK) — RO. The ICH10 reports 0, indicating that no PCI clock is required to generate PME#. Version (VER) — RO. The ICH10 reports 010b, indicating that it complies with Revision 1.1 of the PCI Power Management Specification. 10 9 8:6 5 4 3 2:0 NOTES: 1. Normally, this register is read-only to report capabilities to the power management software. To report different power management capabilities, depending on the system in which the ICH10 is used, bits 15:11 and 8:6 in this register are writable when the WRT_RDONLY bit (D29:F7, D26:F7:80h, bit 0) is set. The value written to this register does not affect the hardware other than changing the value returned during a read. 2. Reset: core well, but not D3-to-D0 warm reset. Datasheet 619 EHCI Controller Registers (D29:F7, D26:F7) 17.1.19 PWR_CNTL_STS—Power Management Control/ Status Register (USB EHCI—D29:F7, D26:F7) Address Offset: Default Value: Function Level Reset: Bit PME Status — R/WC. 0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if enabled). 1 = This bit is set when the ICH10 EHC would normally assert the PME# signal independent of the state of the PME_En bit. NOTE: This bit must be explicitly cleared by the operating system each time the operating system is loaded. This bit is not reset by Function Level Reset. 14:13 12:9 Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data register. Data Select — RO. Hardwired to 0000b indicating it does not support the associated Data register. PME Enable — R/W. 0 = Disable. 1 = Enables Intel® ICH10 EHC to generate an internal PME signal when PME_Status is 1. NOTE: This bit must be explicitly cleared by the operating system each time it is initially loaded. This bit is not reset by Function Level Reset. 7:2 Reserved Power State — R/W. This 2-bit field is used both to determine the current power state of EHC function and to set a new power state. The definition of the field values are: 00 = D0 state 11 = D3HOT state 1:0 If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. When in the D3HOT state, the ICH10 must not accept accesses to the EHC memory range; but the configuration space must still be accessible. When not in the D0 state, the generation of the interrupt output is blocked. Specifically, the PIRQH is not asserted by the ICH10 when not in the D0 state. When software changes this value from the D3HOT state to the D0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset. 54h–55h Attribute: 0000h Size: No (Bits 8 and 15 only) Description R/W, R/WC, RO 16 bits 15 8 620 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.1.20 DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F7, D26:F7) Address Offset: 58h Default Value: 0Ah Bit 7:0 Attribute: Size: Description RO 8 bits Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a Debug Port Capability structure. 17.1.21 NXT_PTR2—Next Item Pointer #2 Register (USB EHCI—D29:F7, D26:F7) Address Offset: 59h Default Value: 98h Function Level Reset: No Bit 7:0 Attribute: Size: RO 8 bits Description Next Item Pointer 2 Capability — RO. This register points to the next capability in the Function Level Reset capability structure. 17.1.22 DEBUG_BASE—Debug Port Base Offset Register (USB EHCI—D29:F7, D26:F7) Address Offset: 5Ah–5Bh Default Value: 20A0h Bit 15:13 12:0 Attribute: Size: Description RO 16 bits BAR Number — RO. Hardwired to 001b to indicate the memory BAR begins at offset 10h in the EHCI configuration space. Debug Port Offset — RO. Hardwired to 0A0h to indicate that the Debug Port registers begin at offset A0h in the EHCI memory range. 17.1.23 USB_RELNUM—USB Release Number Register (USB EHCI—D29:F7, D26:F7) Address Offset: 60h Default Value: 20h Bit 7:0 Attribute: Size: Description RO 8 bits USB Release Number — RO. A value of 20h indicates that this controller follows Universal Serial Bus (USB) Specification, Revision 2.0. Datasheet 621 EHCI Controller Registers (D29:F7, D26:F7) 17.1.24 FL_ADJ—Frame Length Adjustment Register (USB EHCI—D29:F7, D26:F7) Address Offset: 61h Default Value: 20h Function Level Reset: No Attribute: Size: R/W 8 bits This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written into these six bits, the length of the frame is adjusted. Its initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. This register should only be modified when the HChalted bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 1. Changing value of this register while the host controller is operating yields undefined results. It should not be reprogrammed by USB system software unless the default or BIOS programmed values are incorrect, or the system is restoring the register while returning from a suspended state. These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset. Bit 7:6 Description Reserved — RO. These bits are reserved for future use and should read as 00b. Frame Length Timing Value — R/W. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. Frame Length (# 480 MHz Clocks) (decimal) 59488 5:0 59504 59520 — 59984 60000 — 60480 Frame Length Timing Value (this register) (decimal) 0 1 2 — 31 32 — 62 622 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.1.25 PWAKE_CAP—Port Wake Capability Register (USB EHCI—D29:F7, D26:F7) Address Offset: Default Value: Function Level Reset: 62–63h 01FFh No Attribute: Size: R/W 16 bits This register is in the suspend power well. The intended use of this register is to establish a policy about which ports are to be used for wake events. Bit positions 1– 8(D29) or 1–6(D26) in the mask correspond to a physical port implemented on the current EHCI controller. A 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/ connect or overcurrent events as wake-up events. This is an information-only mask register. The bits in this register do not affect the actual operation of the EHCI host controller. The system-specific policy can be established by BIOS initializing this register to a system-specific value. System software uses the information in this register when enabling devices and ports for remote wake-up. These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 15:9 (D29) 15:7 (D26) 8:1 (D29) 6:1 (D26) 0 Description Reserved. Port Wake Up Capability Mask — R/W. Bit positions 1 through 8 (Device 29) or 1 through 6(Device 26) correspond to a physical port implemented on this host controller. For example, bit position 1 corresponds to port 1, bit position 2 corresponds to port 2, etc. Port Wake Implemented — R/W. A 1 in this bit indicates that this register is implemented to software. Datasheet 623 EHCI Controller Registers (D29:F7, D26:F7) 17.1.26 LEG_EXT_CAP—USB EHCI Legacy Support Extended Capability Register (USB EHCI—D29:F7, D26:F7) Address Offset: 68–6Bh Default Value: 00000001h Power Well: Suspend Function Level Reset: No Attribute: Size: R/W, RO 32 bits Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 31:25 24 23:17 16 Reserved — RO. Hardwired to 00h HC OS Owned Semaphore — R/W. System software sets this bit to request ownership of the EHCI controller. Ownership is obtained when this bit reads as 1 and the HC BIOS Owned Semaphore bit reads as clear. Reserved — RO. Hardwired to 00h HC BIOS Owned Semaphore — R/W. The BIOS sets this bit to establish ownership of the EHCI controller. System BIOS will clear this bit in response to a request for ownership of the EHCI controller by system software. Next EHCI Capability Pointer — RO. Hardwired to 00h to indicate that there are no EHCI Extended Capability structures in this device. Capability ID — RO. Hardwired to 01h to indicate that this EHCI Extended Capability is the Legacy Support Capability. Description 15:8 7:0 17.1.27 LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F7, D26:F7) Address Offset: 6C–6Fh Default Value: 00000000h Power Well: Suspend Function Level Reset: No Attribute: Size: R/W, R/WC, RO 32 bits Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 31 Description SMI on BAR — R/WC. Software clears this bit by writing a 1 to it. 0 = Base Address Register (BAR) not written. 1 = This bit is set to 1 when the Base Address Register (BAR) is written. SMI on PCI Command — R/WC. Software clears this bit by writing a 1 to it. 30 0 = PCI Command (PCICMD) Register Not written. 1 = This bit is set to 1 when the PCI Command (PCICMD) Register is written. SMI on OS Ownership Change — R/WC. Software clears this bit by writing a 1 to it. 29 0 = No HC OS Owned Semaphore bit change. 1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP register (D29:F7, D26:F7:68h, bit 24) transitions from 1 to 0 or 0 to 1. Reserved. 28:22 624 Datasheet EHCI Controller Registers (D29:F7, D26:F7) Bit Description SMI on Async Advance — RO. This bit is a shadow bit of the Interrupt on Async Advance bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register. 21 NOTE: To clear this bit system software must write a 1 to the Interrupt on Async Advance bit in the USB2.0_STS register. SMI on Host System Error — RO. This bit is a shadow bit of Host System Error bit in the USB2.0_STS register (D29:F7, D26:F7:CAPLENGTH + 24h, bit 4). 20 NOTE: To clear this bit system software must write a 1 to the Host System Error bit in the USB2.0_STS register. SMI on Frame List Rollover — RO. This bit is a shadow bit of Frame List Rollover bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register. 19 NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in the USB2.0_STS register. SMI on Port Change Detect — RO. This bit is a shadow bit of Port Change Detect bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register. 18 NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in the USB2.0_STS register. SMI on USB Error — RO. This bit is a shadow bit of USB Error Interrupt (USBERRINT) bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register. 17 NOTE: To clear this bit system software must write a 1 to the USB Error Interrupt bit in the USB2.0_STS register. SMI on USB Complete — RO. This bit is a shadow bit of USB Interrupt (USBINT) bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register. 16 NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the USB2.0_STS register. SMI on BAR Enable — R/W. 15 0 = Disable. 1 = Enable. When this bit is 1 and SMI on BAR (D29:F7, D26:F7:6Ch, bit 31) is 1, then the host controller will issue an SMI. SMI on PCI Command Enable — R/W. 14 0 = Disable. 1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F7, D26:F7:6Ch, bit 30) is 1, then the host controller will issue an SMI. SMI on OS Ownership Enable — R/W. 13 0 = Disable. 1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F7, D26:F7:6Ch, bit 29) is 1, the host controller will issue an SMI. Reserved. SMI on Async Advance Enable — R/W. 5 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F7, D26:F7:6Ch, bit 21) is a 1, the host controller will issue an SMI immediately. SMI on Host System Error Enable — R/W. 4 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F7, D26:F7:6Ch, bit 20) is a 1, the host controller will issue an SMI. 12:6 Datasheet 625 EHCI Controller Registers (D29:F7, D26:F7) Bit Description SMI on Frame List Rollover Enable — R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F7, D26:F7:6Ch, bit 19) is a 1, the host controller will issue an SMI. SMI on Port Change Enable — R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F7, D26:F7:6Ch, bit 18) is a 1, the host controller will issue an SMI. SMI on USB Error Enable — R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F7, D26:F7:6Ch, bit 17) is a 1, the host controller will issue an SMI immediately. SMI on USB Complete Enable — R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F7, D26:F7:6Ch, bit 16) is a 1, the host controller will issue an SMI immediately. 3 2 1 0 17.1.28 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7, D26:F7) Address Offset: 70h–73h Default Value: 00000000h Power Well: Suspend Function Level Reset: No Attribute: Size: R/W, R/WC 32 bits Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 31:30 (D29) 31:28 (D26) 29:22 (D29) 27:22 (D26) SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it. 0 = No Port Owner bit change. 1 = Bits 29:22, 27:22 correspond to the Port Owner bits for ports 1 (22) through 6 (27) or 8 (29). These bits are set to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to 0. SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it. 21 0 = Power State bits Not modified. 1 = Software modified the Power State bits in the Power Management Control/Status (PMCSR) register (D29:F7, D26:F7:54h). SMI on Async — R/WC. Software clears these bits by writing a 1 to it. 20 0 = No Async Schedule Enable bit change 1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1. SMI on Periodic — R/WC. Software clears this bit by writing a 1 it. 19 0 = No Periodic Schedule Enable bit change. 1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1. Reserved. Description 626 Datasheet EHCI Controller Registers (D29:F7, D26:F7) Bit 18 Description SMI on CF — R/WC. Software clears this bit by writing a 1 it. 0 = No Configure Flag (CF) change. 1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1. SMI on HCHalted — R/WC. Software clears this bit by writing a 1 it. 0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being cleared). 1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared). SMI on HCReset — R/WC. Software clears this bit by writing a 1 it. 0 = HCRESET did Not transitioned to 1. 1 = HCRESET transitioned to 1. Reserved. SMI on PortOwner Enable — R/W. 0 = Disable. 1 = Enable. When any of these bits are 1 and the corresponding SMI on PortOwner bits are 1, then the host controller will issue an SMI. Unused ports should have their corresponding bits cleared. SMI on PMSCR Enable — R/W. 0 = Disable. 1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller will issue an SMI. SMI on Async Enable — R/W. 0 = Disable. 1 = Enable. When this bit is 1 and SMI on Async is 1, then the host controller will issue an SMI SMI on Periodic Enable — R/W. 0 = Disable. 1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller will issue an SMI. SMI on CF Enable — R/W. 0 = Disable. 1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will issue an SMI. SMI on HCHalted Enable — R/W. 0 = Disable. 1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host controller will issue an SMI. SMI on HCReset Enable — R/W. 0 = Disable. 1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller will issue an SMI. 17 16 15:14 13:6 5 4 3 2 1 0 Datasheet 627 EHCI Controller Registers (D29:F7, D26:F7) 17.1.29 ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7, D26:F7) Address Offset: 80h Default Value: 00h Function Level Reset: No Bit 7:1 Reserved WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally readonly registers in the EHC function to be written by software. Registers that may only be written when this mode is entered are noted in the summary tables and detailed description as “Read/Write-Special”. The registers fall into two categories: 1. System-configured parameters, and 2. Status bits Attribute: Size: R/W 8 bits Description 0 17.1.30 EHCIIR1—EHCI Initialization Register 1 (USB EHCI—D29:F7, D26:F7) Address Offset: Default Value: Bit 7:5 4 3:0 Reserved Pre-fetch Based Pause Disable — R/W. 0 = Pre-fetch Based Pause is enabled. 1 = Pre-fetch Based Pause is disabled. Reserved 84h 01h Attribute: Size: Description R/W 8 bits 17.1.31 FLR_CID—Function Level Reset Capability ID (USB EHCI—D29:F7, D26:F7) Address Offset: 98h Default Value: 09h Function Level Reset: No Bit Capability ID — R0. 7:0 13h = If FLRCSSEL = 0 09h (Vendor Specific Capability) = If FLRCSSEL = 1 Attribute: Size: RO 8 bits Description 628 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.1.32 FLR_NEXT—Function Level Reset Next Capability Pointer (USB EHCI—D29:F7, D26:F7) Address Offset: 99h Default Value: 00h Function Level Reset: No Bit 7:0 Attribute: Size: RO 8 bits Description A value of 00h in this register indicates this is the last capability field. 17.1.33 FLR_CLV—Function Level Reset Capability Length and Version (USB EHCI—D29:F7, D26:F7) Address Offset: Default Value: Function Level Reset: 9Ah-9Bh 2006h No Attribute: Size: R/WO, RO 16 bits When FLRCSSEL = 0, this register is defined as follows: Bit 15:10 9 Reserved. FLR Capability — R/WO. 1 = Support for Function Level Reset (FLR). TXP Capability — R/WO. 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. Capability Length — RO. This field indicates the # of bytes of this vendor specific capability as required by the PCI specification. It has the value of 06h for the FLR capability. Description 8 7:0 When FLRCSSEL = 1, this register is defined as follows: Bit 15:12 11:8 7:0 Description Vendor Specific Capability ID — RO. A value of 2h in this field identifies this capability as Function Level Reset. Capability Version — RO. This field indicates the version of the FLR capability. Capability Length — RO. This field indicates the # of bytes of this vendor specific capability as required by the PCI specification. It has the value of 06h for the FLR capability. Datasheet 629 EHCI Controller Registers (D29:F7, D26:F7) 17.1.34 FLR_CTRL—Function Level Reset Control Register (USB EHCI—D29:F7, D26:F7) Address Offset: 9Ch Default Value: 00h Function Level Reset: No Bit 7:1 0 Reserved Initiate FLR — R/W. This bit is used to initiate FLR transition. A write of ‘1’ initiates FLR transition. Since hardware must not respond to any cycles until FLR completion, the value read by software from this bit is always ‘0’. Attribute: Size: R/W 8 bits Description 17.1.35 FLR_STS—Function Level Reset Status Register (USB EHCI—D29:F7, D26:F7) Address Offset: 9Dh Default Value: 00h Function Level Reset: No Bit 7:1 0 Reserved Transactions Pending (TXP) — RO. 0 = Completions for all non-posted requests have been received. 1 = Controller has issued non-posted requests which have no bee completed. Attribute: Size: RO 8 bits Description 17.1.36 EHCIIR2—EHCI Initialization Register 2 (USB EHCI—D29:F7, D26:F7) Address Offset: Default Value: Bit 31:30 29 28:18 17 16:4 3:2 1:0 Reserved EHCIIR2 Field 2 — R/W. BIOS must set this bit Reserved EHCIIR2 Field 1 — R/W. BIOS must set this bit Reserved EHCIIR2 Field 3 — R/W. BIOS must set this field to 10b Reserved FCh 20001706h Attribute: Size: Description R/W 32 bits 630 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.2 Memory-Mapped I/O Registers The EHCI memory-mapped I/O space is composed of two sets of registers: Capability Registers and Operational Registers. Note: The ICH10 EHCI controller will not accept memory transactions (neither reads nor writes) as a target that are locked transactions. The locked transactions should not be forwarded to PCI as the address space is known to be allocated to USB. When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory range are ignored and result a master abort. Similarly, if the Memory Space Enable (MSE) bit (D29:F7, D26:F7:04h, bit 1) is not set in the Command register in configuration space, the memory range will not be decoded by the ICH10 enhanced host controller (EHC). If the MSE bit is not set, then the ICH10 must default to allowing any memory accesses for the range specified in the BAR to go to PCI. This is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. Note: 17.2.1 Host Controller Capability Registers These registers specify the limits, restrictions and capabilities of the host controller implementation. Within the host controller capability registers, only the structural parameters register is writable. These registers are implemented in the suspend well and is only reset by the standard suspend-well hardware reset, not by HCRESET or the D3-to-D0 reset. Note: Note that the EHCI controller does not support as a target memory transactions that are locked transactions. Attempting to access the EHCI controller Memory-Mapped I/O space using locked memory transactions will result in undefined behavior. Note that when the USB2 function is in the D3 PCI power state, accesses to the USB2 memory range are ignored and will result in a master abort Similarly, if the Memory Space Enable (MSE) bit is not set in the Command register in configuration space, the memory range will not be decoded by the Enhanced Host Controller (EHC). If the MSE bit is not set, then the EHC will not claim any memory accesses for the range specified in the BAR. Note: Table 17-2. Enhanced Host Controller Capability Registers MEM_BASE + Offset 00h 02h–03h Mnemonic CAPLENGTH HCIVERSION Register Capabilities Registers Length Host Controller Interface Version Number Host Controller Structural Parameters Host Controller Capability Parameters Default 20h 0100h 00103206h (D29:F7) 00102205 (D26:F7) 00006871h Type RO RO 04h–07h HCSPARAMS R/W (special), RO 08h–0Bh HCCPARAMS RO NOTE: “Read/Write Special” means that the register is normally read-only, but may be written when the WRT_RDONLY bit is set. Because these registers are expected to be programmed by BIOS during initialization, their contents must not get modified by HCRESET or D3-toD0 internal reset. Datasheet 631 EHCI Controller Registers (D29:F7, D26:F7) 17.2.1.1 CAPLENGTH—Capability Registers Length Register Offset: Default Value: Bit MEM_BASE + 00h 20h Attribute: Size: Description RO 8 bits 7:0 Capability Register Length Value — RO. This register is used as an offset to add to the Memory Base Register (D29:F7, D26:F7:10h) to find the beginning of the Operational Register Space. This field is hardwired to 20h indicating that the Operation Registers begin at offset 20h. 17.2.1.2 HCIVERSION—Host Controller Interface Version Number Register Offset: Default Value: Bit 15:0 MEM_BASE + 02h–03h 0100h Attribute: Size: Description RO 16 bits Host Controller Interface Version Number — RO. This is a two-byte register containing a BCD encoding of the version number of interface that this host controller interface conforms. 632 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.2.1.3 HCSPARAMS—Host Controller Structural Parameters Offset: Default Value: MEM_BASE + 04h–07h 00103206h (D29:F7) 00103206h (D26:F7) Function Level Reset: No Attribute: Size: R/W, RO 32 bits Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET. Bit 31:24 23:20 19:16 Reserved. Debug Port Number (DP_N) — RO. Hardwired to 1h indicating that the Debug Port is on the lowest numbered port on the EHCI. Reserved Number of Companion Controllers (N_CC) — R/W. This field indicates the number of companion controllers associated with this USB EHCI host controller. A 0 in this field indicates there are no companion host controllers. Port-ownership handoff is not supported. Only high-speed devices are supported on the host controller root ports. 15:12 A value of 1 or more in this field indicates there are companion USB UHCI host controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed devices are supported on the host controller root ports. The ICH10 allows the default value of 3h (D29) or 3h (D26) to be over-written by BIOS. When removing classic controllers, they must be disabled in the following order: Function 3, Function 2, Function 1, and Function 0, which correspond to ports 11:10, 5:4, 3:2, and 1:0, respectively for Device 29. For Device 26 the following order is Function 2, Function 1 then Function 0, which correspond to ports 11:10, 9:8 and 7:6, respectively. 11:8 7:4 Number of Ports per Companion Controller (N_PCC) — RO. Hardwired to 2h. This field indicates the number of ports supported per companion host controller. It is used to indicate the port routing configuration to system software. Reserved. These bits are reserved and default to 0. N_PORTS — R/W. This field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register Space. Valid values are in the range of 1h to Fh. The ICH10 reports 6h for D29 and 6h for D26 by default. However, software may write a value less than the default for some platform configurations. A 0 in this field is undefined. NOTE: This register is writable when the WRT_RDONLY bit is set. Description 3:0 Datasheet 633 EHCI Controller Registers (D29:F7, D26:F7) 17.2.1.4 HCCPARAMS—Host Controller Capability Parameters Register Offset: Default Value: Bit 31:18 17 Reserved Asynchronous Schedule Update Capability (ASUC) — R/W. There is no functionality associated with this bit. Periodic Schedule Update Capability (PSUC) — RO. This field is hardwired to 0b to indicate that the EHC hardware supports the Periodic Schedule Update Event Flag in the USB2.0_CMD register. EHCI Extended Capabilities Pointer (EECP) — RO. This field is hardwired to 68h, indicating that the EHCI capabilities list exists and begins at offset 68h in the PCI configuration space. Isochronous Scheduling Threshold — RO. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller hold a set of isochronous data structures (one or more) before flushing the state. When bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. Refer to the EHCI specification for details on how software uses this information for scheduling isochronous transfers. This field is hardwired to 7h. 3 2 Reserved. Asynchronous Schedule Park Capability — RO. This bit is hardwired to 0 indicating that the host controller does not support this optional feature Programmable Frame List Flag — RO. 0 = System software must use a frame list length of 1024 elements with this host controller. The USB2.0_CMD register (D29:F7, D26:F7:CAPLENGTH + 20h, bits 3:2) Frame List Size field is a read-only register and must be set to 0. 1 = System software can specify and use a smaller frame list and configure the host controller via the USB2.0_CMD register Frame List Size field. The frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous. 64-bit Addressing Capability — RO. This field documents the addressing range capability of this implementation. The value of this field determines whether software should use the 32-bit or 64-bit data structures. Values for this field have the following interpretation: 0 0 = Data structures using 32-bit address memory pointers 1 = Data structures using 64-bit address memory pointers This bit is hardwired to 1. NOTE: ICH10 supports 64 bit addressing only. MEM_BASE + 08h–0Bh 00006871h Attribute: Size: Description RO 32 bits 16 15:8 7:4 1 634 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.2.2 Host Controller Operational Registers This section defines the enhanced host controller operational registers. These registers are located after the capabilities registers. The operational register base must be dword-aligned and is calculated by adding the value in the first capabilities register (CAPLENGTH) to the base address of the enhanced host controller register address space (MEM_BASE). Since CAPLENGTH is always 20h, Table 17-3 already accounts for this offset. All registers are 32 bits in length. Table 17-3. Enhanced Host Controller Operational Register Address Map MEM_BAS E + Offset 20h–23h 24h–27h 28h–2Bh 2Ch–2Fh 30h–33h 34h–37h 38h–3Bh 3Ch–5Fh 60h–63h 64h–67h 68h–6Bh 6Ch–6Fh 70h–73h 74h–77h 78h–7Bh 74h–77h (D29 Only) 78h–7Bh (D29 Only) 7Ch–9Fh A0h–B3h B4h–3FFh Mnemonic USB2.0_CMD USB2.0_STS USB2.0_INTR FRINDEX CTRLDSSEGMENT PERODICLISTBASE ASYNCLISTADDR — CONFIGFLAG PORT0SC PORT1SC PORT2SC PORT3SC PORT4SC PORT5SC PORT6SC PORT7SC — — — Register Name USB 2.0 Command USB 2.0 Status USB 2.0 Interrupt Enable USB 2.0 Frame Index Control Data Structure Segment Period Frame List Base Address Current Asynchronous List Address Reserved Configure Flag Port 0 Status and Control Port 1 Status and Control Port 2 Status and Control Port 3 Status and Control Port 4 Status and Control Port 5 Status and Control Port 6 Status and Control Port 7 Status and Control Reserved Debug Port Registers Reserved Default 00080000h 00001000h 00000000h 00000000h 00000000h 00000000h 00000000h 0h 00000000h 00003000h 00003000h 00003000h 00003000h 00003000h 00003000h 00003000h 00003000h Undefined Undefined Undefined Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend Special Notes Type R/W, RO R/WC, RO R/W R/W, R/W, RO R/W R/W RO R/W R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO RO See register description RO Note: Software must read and write these registers using only dword accesses.These registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are implemented in the core power well. Unless otherwise noted, the core well registers are reset by the assertion of any of the following: • Core well hardware reset • HCRESET • D3-to-D0 reset Datasheet 635 EHCI Controller Registers (D29:F7, D26:F7) The second set at offsets MEM_BASE + 60h to the end of the implemented register space are implemented in the Suspend power well. Unless otherwise noted, the suspend well registers are reset by the assertion of either of the following: • Suspend well hardware reset • HCRESET 17.2.2.1 USB2.0_CMD—USB 2.0 Command Register Offset: Default Value: Bit 31:24 Reserved. Interrupt Threshold Control — R/W. System software uses this field to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this register, the results are undefined. Value 00h 23:16 01h 02h 04h 08h 10h 20h 40h 15:14 13 Reserved. Asynch Schedule Update (ASC) — R/W. There is no functionality associated with this bit. Periodic Schedule Prefetch Enable — R/W. This bit is used by software to enable the host controller to prefetch the periodic schedule even in C0. 0 = Prefetch based pause enabled only when not in C0. 1 = Prefetch based pause enable in C0. 12 Once software has written a 1b to this bit to enable periodic schedule prefetching, it must disable prefecthing by writing a 0b to this bit whenever periodic schedule updates are about to begin. Software should continue to dynamically disable and re-enable the prefetcher surrounding any updates to the periodic scheduler (i.e. until the host controller has been reset via a HCRESET). Unimplemented Asynchronous Park Mode Bits — RO. Hardwired to 000b indicating the host controller does not support this optional feature. Light Host Controller Reset — RO. Hardwired to 0. The ICH10 does not implement this optional reset. Maximum Interrupt Interval Reserved 1 micro-frame 2 micro-frames 4 micro-frames 8 micro-frames (default, equates to 1 ms) 16 micro-frames (2 ms) 32 micro-frames (4 ms) 64 micro-frames (8 ms) MEM_BASE + 20–23h 00080000h Attribute: Size: Description R/W, RO 32 bits 11:8 7 636 Datasheet EHCI Controller Registers (D29:F7, D26:F7) Bit Description Interrupt on Async Advance Doorbell — R/W. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async Advance status bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register to a 1. 1 = Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance Enable bit in the USB2.0_INTR register (D29:F7, D26:F7:CAPLENGTH + 28h, bit 5) is a 1 then the host controller will assert an interrupt at the next interrupt threshold. See the EHCI specification for operational details. NOTE: Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. Asynchronous Schedule Enable — R/W. This bit controls whether the host controller skips processing the Asynchronous Schedule. 0 = Do not process the Asynchronous Schedule 1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. Periodic Schedule Enable — R/W. This bit controls whether the host controller skips processing the Periodic Schedule. 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. Frame List Size — RO. The ICH10 hardwires this field to 00b because it only supports the 1024-element frame list size. Host Controller Reset (HCRESET) — R/W. This control bit used by software to reset the host controller. The effects of this on root hub registers are similar to a Chip Hardware Reset (i.e., RSMRST# assertion and PWROK deassertion on the ICH10). When software writes a 1 to this bit, the host controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. NOTE: PCI configuration registers and Host controller capability registers are not effected by this reset. All operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s), with the side effects described in the EHCI spec. Software must re-initialize the host controller in order to return the host controller to an operational state. This bit is set to 0 by the host controller when the reset process is complete. Software cannot terminate the reset process early by writing a 0 to this register. Software should not set this bit to a 1 when the HCHalted bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 0. Attempting to reset an actively running host controller will result in undefined behavior. This reset me be used to leave EHCI port test modes. 6 5 4 3:2 1 Datasheet 637 EHCI Controller Registers (D29:F7, D26:F7) Bit Run/Stop (RS) — R/W. Description 0 = Stop (default) 1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule. The Host controller continues execution as long as this bit is set. When this bit is set to 0, the Host controller completes the current transaction on the USB and then halts. The HCHalted bit in the USB2.0_STS register indicates when the Host controller has finished the transaction and has entered the stopped state. Software should not write a 1 to this field unless the host controller is in the Halted state (i.e., HCHalted in the USBSTS register is a 1). The Halted bit is cleared immediately when the Run bit is set. 0 The following table explains how the different combinations of Run and Halted should be interpreted: Run/Stop 0b 0b 1b 1b Halted 0b 1b 0b 1b Interpretation In the process of halting Halted Running Invalid - the HCHalted bit clears immediately Memory read cycles initiated by the EHC that receive any status other than Successful will result in this bit being cleared. NOTE: The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. 638 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.2.2.2 USB2.0_STS—USB 2.0 Status Register Offset: Default Value: MEM_BASE + 24h–27h 00001000h Attribute: Size: R/WC, RO 32 bits This register indicates pending interrupts and various states of the Host controller. The status resulting from a transaction on the serial bus is not indicated in this register. See the Interrupts description in section 4 of the EHCI specification for additional information concerning USB 2.0 interrupt conditions. Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has no effect. Bit 31:16 Reserved. Asynchronous Schedule Status ⎯ RO. This bit reports the current real status of the Asynchronous Schedule. 0 = Status of the Asynchronous Schedule is disabled. (Default) 1 = Status of the Asynchronous Schedule is enabled. 15 NOTE: The Host controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit (D29:F7, D26:F7:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Periodic Schedule Status ⎯ RO. This bit reports the current real status of the Periodic Schedule. 0 = Status of the Periodic Schedule is disabled. (Default) 1 = Status of the Periodic Schedule is enabled. 14 NOTE: The Host controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit (D29:F7, D26:F7:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Reclamation ⎯ RO. This read-only status bit is used to detect an empty asynchronous schedule. The operational model and valid transitions for this bit are described in Section 4 of the EHCI Specification. HCHalted ⎯ RO. 12 0 = This bit is a 0 when the Run/Stop bit is a 1. 1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host controller hardware (e.g., internal error). (Default) Reserved Interrupt on Async Advance — R/WC. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit (D29:F7, D26:F7:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit indicates the assertion of that interrupt source. Description 13 11:6 5 Datasheet 639 EHCI Controller Registers (D29:F7, D26:F7) Bit Host System Error — R/WC. Description 0 = No serious error occurred during a host system access involving the Host controller module 1 = The Host controller sets this bit to 1 when a serious error occurs during a host system access involving the Host controller module. A hardware interrupt is generated to the system. Memory read cycles initiated by the EHC that receive any status other than Successful will result in this bit being set. When this error occurs, the Host controller clears the Run/Stop bit in the USB2.0_CMDregister (D29:F7, D26:F7:CAPLENGTH + 20h, bit 0) to prevent further execution of the scheduled TDs. A hardware interrupt is generated to the system (if enabled in the Interrupt Enable Register). Frame List Rollover — R/WC. 0 = No Frame List Index rollover from its maximum value to 0. 1 = The Host controller sets this bit to a 1 when the Frame List Index (see Section) rolls over from its maximum value to 0. Since the ICH10 only supports the 1024-entry Frame List Size, the Frame List Index rolls over every time FRNUM13 toggles. Port Change Detect — R/WC. This bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, overcurrent change, enable/disable change and connect status change). Regardless of the implementation, when this bit is readable (i.e., in the D0 state), it must provide a valid view of the Port Status registers. 0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0 to 1 as a result of a J-K transition detected on a suspended port. 1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is set to 0 has a change bit transition from a 0 to 1 or a Force Port Resume bit transition from 0 to 1 as a result of a J-K transition detected on a suspended port. USB Error Interrupt (USBERRINT) — R/WC. 0 = No error condition. 1 = The Host controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification for a list of the USB errors that will result in this interrupt being asserted. USB Interrupt (USBINT) — R/WC. 0 = No completion of a USB transaction whose Transfer Descriptor had its IOC bit set. No short packet is detected. 1 = The Host controller sets this bit to 1 when the cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set. The Host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). 4 3 2 1 0 640 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register Offset: Default Value: MEM_BASE + 28h–2Bh 00000000h Attribute: Size: R/W 32 bits This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USB2.0_STS Register to allow the software to poll for events. Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism (see Section 4 of the EHCI specification), or not. Bit 31:6 Reserved. Interrupt on Async Advance Enable — R/W. 5 0 = Disable. 1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. Host System Error Enable — R/W. 4 0 = Disable. 1 = Enable. When this bit is a 1, and the Host System Error Status bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 4) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. Frame List Rollover Enable — R/W. 3 0 = Disable. 1 = Enable. When this bit is a 1, and the Frame List Rollover bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. Port Change Interrupt Enable — R/W. 2 0 = Disable. 1 = Enable. When this bit is a 1, and the Port Change Detect bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit. USB Error Interrupt Enable — R/W. 1 0 = Disable. 1 = Enable. When this bit is a 1, and the USBERRINT bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software by clearing the USBERRINT bit in the USB2.0_STS register. USB Interrupt Enable — R/W. 0 0 = Disable. 1 = Enable. When this bit is a 1, and the USBINT bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software by clearing the USBINT bit in the USB2.0_STS register. Description Datasheet 641 EHCI Controller Registers (D29:F7, D26:F7) 17.2.2.4 FRINDEX—Frame Index Register Offset: Default Value: MEM_BASE + 2Ch–2Fh 00000000h Attribute: Size: R/W 32 bits The SOF frame number value for the bus SOF token is derived or alternatively managed from this register. Refer to Section 4 of the EHCI specification for a detailed explanation of the SOF value management requirements on the host controller. The value of FRINDEX must be within 125 µs (1 micro-frame) ahead of the SOF token value. The SOF value may be implemented as an 11-bit shadow register. For this discussion, this shadow register is 11 bits and is named SOFV. SOFV updates every 8 micro-frames (1 millisecond). An example implementation to achieve this behavior is to increment SOFV each time the FRINDEX[2:0] increments from 0 to 1. Software must use the value of FRINDEX to derive the current micro-frame number, both for high-speed isochronous scheduling purposes and to provide the get microframe number function required to client drivers. Therefore, the value of FRINDEX and the value of SOFV must be kept consistent if chip is reset or software writes to FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple as possible, software should never write a FRINDEX value where the three least significant bits are 111b or 000b. Note: This register is used by the host controller to index into the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Bits [12:3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index is fixed at 10 for the ICH10 since it only supports 1024-entry frame lists. This register must be written as a dword. Word and byte writes produce undefined results. This register cannot be written unless the Host controller is in the Halted state as indicated by the HCHalted bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 12). A write to this register while the Run/Stop bit (D29:F7, D26:F7:CAPLENGTH + 20h, bit 0) is set to a 1 (USB2.0_CMD register) produces undefined results. Writes to this register also effect the SOF value. See Section 4 of the EHCI specification for details. Bit 31:14 Reserved Frame List Current Index/Frame Number — R/W. The value in this register increments at the end of each time frame (e.g., micro-frame). 13:0 Bits [12:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. Description 642 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment Register Offset: Default Value: MEM_BASE + 30h–33h 00000000h Attribute: Size: R/W, RO 32 bits This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. Since the ICH10 hardwires the 64-bit Addressing Capability field in HCCPARAMS to 1, then this register is used with the link pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address. This register allows the host software to locate all control data structures within the same 4 GB memory segment. Bit 31:12 11:0 Description Upper Address[63:44] — RO. Hardwired to 0s. The ICH10 EHC is only capable of generating addresses up to 16 terabytes (44 bits of address). Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32 when forming a control data structure address. 17.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address Register Offset: Default Value: MEM_BASE + 34h–37h 00000000h Attribute: Size: R/W 32 bits This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. Since the ICH10 host controller operates in 64-bit mode (as indicated by the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the schedule execution by the host controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host controller to step through the Periodic Frame List in sequence. Bit 31:12 11:0 Description Base Address (Low) — R/W. These bits correspond to memory address signals [31:12], respectively. Reserved. Datasheet 643 EHCI Controller Registers (D29:F7, D26:F7) 17.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address Register Offset: Default Value: MEM_BASE + 38h–3Bh 00000000h Attribute: Size: R/W 32 bits This 32-bit register contains the address of the next asynchronous queue head to be executed. Since the ICH10 host controller operates in 64-bit mode (as indicated by a 1 in 64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register (offset 08h). Bits [4:0] of this register cannot be modified by system software and will always return 0s when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. Bit 31:5 4:0 Description Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH). Reserved. 17.2.2.8 CONFIGFLAG—Configure Flag Register Offset: Default Value: MEM_BASE + 60h–63h 00000000h Attribute: Size: R/W 32 bits This register is in the suspend power well. It is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. Bit 31:1 Reserved. Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process of configuring the Host controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below. See Chapter 4 of the EHCI specification for operation details. 0 = Port routing control logic default-routes each port to the UHCIs (default). 1 = Port routing control logic default-routes all ports to this host controller. Description 0 644 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.2.2.9 PORTSC—Port N Status and Control Register Offset: Port 0, Port 6: MEM_BASE + 64h–67h Port 1, Port 7: MEM_BASE + 68–6Bh Port 2, Port 8: MEM_BASE + 6C–6Fh Port 3, Port 9: MEM_BASE + 70–73h Port 4: Port 10: MEM_BASE + 74–77h Port 5: Port 11: MEM_BASE + 78–7Bh Port 6: MEM_BASE + 7Ch-7Bh Port 7: MEM_BASE + 80h-83h R/W, R/WC, RO 00003000h Size: Attribute: Default Value: 32 bits A host controller must implement one or more port registers. Software uses the N_Port information from the Structural Parameters Register to determine how many ports need to be serviced. All ports have the structure defined below. Software must not write to unreported Port Status and Control Registers. This register is in the suspend power well. It is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. The initial conditions of a port are: • No device connected • Port disabled. When a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. Refer to Section 4 of the EHCI specification for operational requirements for how change events interact with port suspend mode. Bit 31:23 Reserved. Wake on Overcurrent Enable (WKOC_E) — R/W. 22 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the overcurrent Active bit (bit 4 of this register) is set. Wake on Disconnect Enable (WKDSCNNT_E) — R/W. 21 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the Current Connect Status changes from connected to disconnected (i.e., bit 0 of this register changes from 1 to 0). Wake on Connect Enable (WKCNNT_E) — R/W. 20 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the Current Connect Status changes from disconnected to connected (i.e., bit 0 of this register changes from 0 to 1). Description Datasheet 645 EHCI Controller Registers (D29:F7, D26:F7) Bit Description Port Test Control — R/W. When this field is 0s, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. The encoding of the test mode bits are (0110b – 1111b are reserved): Value 0000b Maximum Interrupt Interval Test mode not enabled (default) Test J_STATE Test K_STATE Test SE0_NAK Test Packet FORCE_ENABLE 19:16 0001b 0010b 0011b 0100b 0101b Refer to USB Specification Revision 2.0, Chapter 7 for details on each test mode. 15:14 Reserved. Port Owner — R/W. This bit unconditionally goes to a 0 when the Configured Flag bit in the USB2.0_CMD register makes a 0 to 1 transition. 13 System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit means that a companion host controller owns and controls the port. See Chapter 4 of the EHCI Specification for operational details. Port Power (PP) — RO. Read-only with a value of 1. This indicates that the port does have power. Line Status— RO.These bits reflect the current logical levels of the D+ (bit 11) and D– (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is 0 and the current connect status bit is set to a 1. 00 10 01 11 = = = = SE0 J-state K-state Undefined 12 11:10 9 Reserved. 646 Datasheet EHCI Controller Registers (D29:F7, D26:F7) Bit Description Port Reset — R/W. When software writes a 1 to this bit (from a 0), the bus reset sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1 long enough to ensure the reset sequence completes as specified in the USB Specification, Revision 2.0. 1 = Port is in Reset. 0 = Port is not in Reset. NOTE: When software writes a 0 to this bit, there may be a delay before the bit status changes to a 0. The bit status will not read as a 0 until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g., set the Port Enable bit to a 1). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from 0 to 1. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2 ms of software writing this bit to a 0. The HCHalted bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register should be a 0 before software attempts to use this bit. The host controller may hold Port Reset asserted to a 1 when the HCHalted bit is a 1. This bit is 0 if Port Power is 0 NOTE: System software should not attempt to reset a port if the HCHalted bit in the USB2.0_STS register is a 1. Doing so will result in undefined behavior. Suspend — R/W. 0 = Port not in suspend state.(Default) 1 = Port in suspend state. Port Enabled Bit and Suspend bit of this register define the port states as follows: Port Enabled 0 Suspend X 0 1 Port State Disabled Enabled Suspend 8 7 1 1 When in suspend state, downstream propagation of data is blocked on this port, except for port reset. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port depending on the activity on the port. The host controller will unconditionally set this bit to a 0 when software sets the Force Port Resume bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host controller. If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is a 0) the results are undefined. Datasheet 647 EHCI Controller Registers (D29:F7, D26:F7) Bit Force Port Resume — R/W. Description 0 = No resume (K-state) detected/driven on port. (Default) 1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume signaling. The Host controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a 1 because a Jto-K transition is detected, the Port Change Detect bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is also set to a 1. If software sets this bit to a 1, the host controller must not set the Port Change Detect bit. NOTE: When the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification, Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a 1. Software must appropriately time the Resume and set this bit to a 0 when the appropriate amount of time has elapsed. Writing a 0 (from 1) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a 1 until the port has switched to the high-speed idle. 6 5 Overcurrent Change — R/WC. The functionality of this bit is not dependent upon the port owner. Software clears this bit by writing a 1 to it. 0 = No change. (Default) 1 = There is a change to Overcurrent Active. Overcurrent Active — RO. 0 = This port does not have an overcurrent condition. (Default) 1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0 when the over current condition is removed. The ICH10 automatically disables the port when the overcurrent active bit is 1. Port Enable/Disable Change — R/WC. For the root hub, this bit gets set to a 1 only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a port error). This bit is not set due to the Disabled-to-Enabled transition, nor due to a disconnect. Software clears this bit by writing a 1 to it. 0 = No change in status. (Default). 1 = Port enabled/disabled status has changed. Port Enabled/Disabled — R/W. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a 1 to this bit. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. 0 = Disable 1 = Enable (Default) Connect Status Change — R/WC. This bit indicates a change has occurred in the port’s Current Connect Status. Software sets this bit to 0 by writing a 1 to it. 4 3 2 1 0 = No change (Default). 1 = Change in Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be “setting” an already-set bit (i.e., the bit will remain set). Current Connect Status — RO. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 0 = No device is present. (Default) 1 = Device is present on port. 0 648 Datasheet EHCI Controller Registers (D29:F7, D26:F7) 17.2.3 USB 2.0-Based Debug Port Register The Debug port’s registers are located in the same memory area, defined by the Base Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register at Configuration offset 5Ah (D29:F7, D26:F7:offset 5Ah). The specific EHCI port that supports this debug capability (Port 0 for D29:F7 and Port 6 for D26:F7) is indicated by a 4-bit field (bits 20–23) in the HCSPARAMS register of the EHCI controller. The address map of the Debug Port registers is shown in Table 17-4. Table 17-4. Debug Port Register Address Map MEM_BASE + Offset A0–A3h A4–A7h A8–AFh B0–B3h Mnemonic CNTL_STS USBPID DATABUF[7:0] CONFIG Register Name Control/Status USB PIDs Data Buffer (Bytes 7:0) Configuration Default 00000000h 00000000h 00000000 00000000h 00007F01h Type R/W, R/WC, RO R/W, RO R/W R/W NOTES: 1. All of these registers are implemented in the core well and reset by PLTRST#, EHC HCRESET, and a EHC D3-to-D0 transition. 2. The hardware associated with this register provides no checks to ensure that software programs the interface correctly. How the hardware behaves when programmed improperly is undefined. Datasheet 649 EHCI Controller Registers (D29:F7, D26:F7) 17.2.3.1 CNTL_STS—Control/Status Register Offset: Default Value: MEM_BASE + A0h 00000000h Attribute: Size: R/W, R/WC, RO 32 bits Bit 31 Reserved OWNER_CNT — R/W. 30 Description 0 = Ownership of the debug port is NOT forced to the EHCI controller (Default) 1 = Ownership of the debug port is forced to the EHCI controller (i.e. immediately taken away from the companion Classic USB Host controller) If the port was already owned by the EHCI controller, then setting this bit has no effect. This bit overrides all of the ownership-related bits in the standard EHCI registers. Reserved ENABLED_CNT — R/W. 0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the same conditions where the Port Enable/Disable Change bit (in the PORTSC register) is set. (Default) 1 = Debug port is enabled for operation. Software can directly set this bit if the port is already enabled in the associated PORTSC register (this is enforced by the hardware). Reserved DONE_STS — R/WC. Software can clear this by writing a 1 to it. 29 28 27:17 16 0 = Request Not complete 1 = Set by hardware to indicate that the request is complete. LINK_ID_STS — RO. This field identifies the link interface. 0h = Hardwired. Indicates that it is a USB Debug Port. Reserved. IN_USE_CNT — R/W. Set by software to indicate that the port is in use. Cleared by software to indicate that the port is free and may be used by other software. This bit is cleared after reset. (This bit has no affect on hardware.) EXCEPTION_STS — RO. This field indicates the exception when the ERROR_GOOD#_STS bit is set. This field should be ignored if the ERROR_GOOD#_STS bit is 0. 000 = No Error. (Default) Note: This should not be seen since this field should only be checked if there is an error. Transaction error: Indicates the USB 2.0 transaction had an error (CRC, bad PID, timeout, etc.) Hardware error. Request was attempted (or in progress) when port was suspended or reset. 15:12 11 10 9:7 001 = 010 = All Other combinations are reserved ERROR_GOOD#_STS — RO. 6 0 = Hardware clears this bit to 0 after the proper completion of a read or write. (Default) 1 = Error has occurred. Details on the nature of the error are provided in the Exception field. 650 Datasheet EHCI Controller Registers (D29:F7, D26:F7) Bit GO_CNT — R/W. 5 Description 0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default) 1 = Causes hardware to perform a read or write request. NOTE: Writing a 1 to this bit when it is already set may result in undefined behavior. WRITE_READ#_CNT — R/W. Software clears this bit to indicate that the current request is a read. Software sets this bit to indicate that the current request is a write. 0 = Read (Default) 1 = Write DATA_LEN_CNT — R/W. This field is used to indicate the size of the data to be transferred. default = 0h. For write operations, this field is set by software to indicate to the hardware how many bytes of data in Data Buffer are to be transferred to the console. A value of 0h indicates that a zero-length packet should be sent. A value of 1–8 indicates 1–8 bytes are to be transferred. Values 9–Fh are invalid and how hardware behaves if used is undefined. For read operations, this field is set by hardware to indicate to software how many bytes in Data Buffer are valid in response to a read operation. A value of 0h indicates that a zero length packet was returned and the state of Data Buffer is not defined. A value of 1–8 indicates 1–8 bytes were received. Hardware is not allowed to return values 9–Fh. The transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. 4 3:0 NOTES: 1. Software should do Read-Modify-Write operations to this register to preserve the contents of bits not being modified. This include Reserved bits. 2. To preserve the usage of RESERVED bits in the future, software should always write the same value read from the bit until it is defined. Reserved bits will always return 0 when read. Datasheet 651 EHCI Controller Registers (D29:F7, D26:F7) 17.2.3.2 USBPID—USB PIDs Register Offset: Default Value: MEM_BASE + A4h–A7h 00000000h Attribute: Size: R/W, RO 32 bits This Dword register is used to communicate PID information between the USB debug driver and the USB debug port. The debug port uses some of these fields to generate USB packets, and uses other fields to return PID information to the USB debug driver. Bit 31:24 Reserved. RECEIVED_PID_STS[23:16] — RO. Hardware updates this field with the received PID for transactions in either direction. When the controller is writing data, this field is updated with the handshake PID that is received from the device. When the host controller is reading data, this field is updated with the data packet PID (if the device sent data), or the handshake PID (if the device NAKs the request). This field is valid when the hardware clears the GO_DONE#_CNT bit. SEND_PID_CNT[15:8] — R/W. Hardware sends this PID to begin the data packet when sending data to USB (i.e., WRITE_READ#_CNT is asserted). Software typically sets this field to either DATA0 or DATA1 PID values. TOKEN_PID_CNT[7:0] — R/W. Hardware sends this PID as the Token PID for each USB transaction. Software typically sets this field to either IN, OUT, or SETUP PID values. Description 23:16 15:8 7:0 17.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register Offset: Default Value: MEM_BASE + A8h–AFh 0000000000000000h Attribute: Size: R/W 64 bits This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register. Bit Description DATABUFFER[63:0] — R/W. This field is the 8 bytes of the data buffer. Bits 7:0 correspond to least significant byte (byte 0). Bits 63:56 correspond to the most significant byte (byte 7). 63:0 The bytes in the Data Buffer must be written with data before software initiates a write request. For a read request, the Data Buffer contains valid data when DONE_STS bit (offset A0, bit 16) is cleared by the hardware, ERROR_GOOD#_STS (offset A0, bit 6) is cleared by the hardware, and the DATA_LENGTH_CNT field (offset A0, bits 3:0) indicates the number of bytes that are valid. 17.2.3.4 CONFIG—Configuration Register Offset: Default Value: Bit 31:15 14:8 7:4 3:0 Reserved USB_ADDRESS_CNF — R/W. This 7-bit field identifies the USB device address used by the controller for all Token PID generation. (Default = 7Fh) Reserved USB_ENDPOINT_CNF — R/W. This 4-bit field identifies the endpoint used by the controller for all Token PID generation. (Default = 1h) MEM_BASE + B0–B3h 00007F01h Attribute: Size: Description R/W 32 bits §§ 652 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18 Intel® High Definition Audio Controller Registers (D27:F0) The Intel High Definition Audio controller resides in PCI Device 27, Function 0 on bus 0. This function contains a set of DMA engines that are used to move samples of digitally encoded data between system memory and external codecs. Note: All registers in this function (including memory-mapped registers) must be addressable in byte, word, and D-word quantities. The software must always make register accesses on natural boundaries (i.e. D-word accesses must be on D-word boundaries; word accesses on word boundaries, etc.) In addition, the memory-mapped register space must not be accessed with the LOCK semantic exclusive-access mechanism. If software attempts exclusive-access mechanisms to the Intel High Definition Audio memory-mapped space, the results are undefined. Users interested in providing feedback on the Intel High Definition Audio specification or planning to implement the Intel High Definition Audio specification into a future product will need to execute the Intel® High Definition Audio Specification Developer’s Agreement. For more information, contact nextgenaudio@intel.com. Note: 18.1 Note: Intel® High Definition Audio PCI Configuration Space (Intel® High Definition Audio— D27:F0) Address locations that are not shown should be treated as Reserved. Table 18-1. Intel® High Definition Audio PCI Register Address Map (Intel® High Definition Audio D27:F0) (Sheet 1 of 2) Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 10h–13h 14h–17h 2Ch–2Dh Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC CLS LT HEADTYP HDBARL HDBARU SVID Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Cache Line Size Latency Timer Header Type Intel® High Definition Audio Lower Base Address (Memory) Intel High Definition Audio Upper Base Address (Memory) Subsystem Vendor Identification Default 8086h See register description 0000h 0010h See register description 00h 03h 04h 00h 00h 00h 00000004h 00000000h 0000h Access RO RO R/W, RO R/WC, RO RO RO RO RO R/W RO RO R/W, RO R/W R/WO Datasheet 653 Intel® High Definition Audio Controller Registers (D27:F0) Table 18-1. Intel® High Definition Audio PCI Register Address Map (Intel® High Definition Audio D27:F0) (Sheet 2 of 2) 2Eh–2Fh 34h 3Ch 3Dh 40h 44h 50h–51h 52h–53h 54h–57h 60h–61h 62h–63h 64h–67h 68h–6Bh 6Ch–6Dh 70h–71h 72h–73h 74h–77h 78h–79h 7Ah–7Bh 100h–103h 104h–107h 108h–10Bh 10Ch–10D 10Eh–10Fh 110h–113h 114h–117h 11Ah–11Bh 11Ch–11Fh 120h–123h 126h–127h 130h–133h 134h–137h 140h–143h 148h–14Bh 14Ch–14Fh SID CAPPTR INTLN INTPN HDCTL TCSEL PID PC PCS MID MMC MMLA MMUA MMD PXID PXC DEVCAP DEVC DEVS VCCAP PVCCAP1 PVCCAP2 PVCCTL PVCSTS VC0CAP VC0CTL VC0STS VCiCAP VCiCTL VCiSTS RCCAP ESD L1DESC L1ADDL L1ADDU Subsystem Identification Capability List Pointer Interrupt Line Interrupt Pin Intel High Definition Audio Control Traffic Class Select PCI Power Management Capability ID Power Management Capabilities Power Management Control and Status MSI Capability ID MSI Message Control MSI Message Lower Address SMI Message Upper Address MSI Message Data PCI Express* Capability Identifiers PCI Express Capabilities Device Capabilities Device Control Device Status Virtual Channel Enhanced Capability Header Port VC Capability Register 1 Port VC Capability Register 2 Port VC Control Port VC Status VC0 Resource Capability VC0 Resource Control VC0 Resource Status VCi Resource Capability VCi Resource Control VCi Resource Status Root Complex Link Declaration Enhanced Capability Header Element Self Description Link 1 Description Link 1 Lower Address Link 1 Upper Address 0000h 50h 00h See Register Description 01h 00h 6001h C842h 00000000h 7005h 0080h 00000000h 00000000h 0000h 0010h 0091h 10000000h 0800h 0010h 13010002h 00000001h 00000000h 0000h 0000h 00000000h 800000FFh 0000h 00000000h 00000000h 0000h 00010005h 0F000100h 00000001h See Register Description 00000000h R/WO RO R/W RO R/W, RO R/W R/WO, RO RO R/W, RO, R/WC RO R/W, RO R/W, RO R/W R/W RO RO RO, R/WO R/W, RO RO R/WO RO RO RO RO RO R/W, RO RO RO R/W, RO RO RO RO RO RO RO 654 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.1 VID—Vendor Identification Register (Intel® High Definition Audio Controller—D27:F0) Offset: Default Value: Bit 15:0 00h-01h 8086h Attribute: Size: Description RO 16 bits Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 18.1.2 DID—Device Identification Register (Intel® High Definition Audio Controller—D27:F0) Offset Address: 02h–03h Default Value: See bit description Bit 15:0 Attribute: Size: Description RO 16 bits Device ID — RO. This is a 16-bit value assigned to the Intel® ICH10 Intel High Definition Audio controller. Refer to the Intel® I/O Controller Hub (ICH10) Family Specification Update for the value of the Device ID Register. 18.1.3 PCICMD—PCI Command Register (Intel® High Definition Audio Controller—D27:F0) Offset Address: 04h–05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable (ID) — R/W. 10 0= The INTx# signals may be asserted. 1= The Intel® High Definition Audio controller’s INTx# signal will be de-asserted. Note: that this bit does not affect the generation of MSI’s. 9 8 7 6 5 4 3 Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0. SERR# Enable (SERR_EN) — R/W. SERR# is not generated by the ICH10 Intel High Definition Audio Controller. Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0. Parity Error Response (PER) — R/W. Not implemented. VGA Palette Snoop (VPS). Not implemented. Hardwired to 0. Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0. Special Cycle Enable (SCE). Not implemented. Hardwired to 0. Attribute: Size: Description R/W, RO 16 bits Datasheet 655 Intel® High Definition Audio Controller Registers (D27:F0) Bit Description Bus Master Enable (BME) — R/W. Controls standard PCI Express* bus mastering capabilities for Memory and I/O, reads and writes. Note that this bit also controls MSI generation since MSI’s are essentially Memory writes. 0 = Disable 1 = Enable Memory Space Enable (MSE) — R/W. Enables memory space addresses to the Intel High Definition Audio controller. 0 = Disable 1 = Enable I/O Space Enable (IOSE)—RO. Hardwired to 0 since the Intel High Definition Audio controller does not implement I/O space. 2 1 0 18.1.4 PCISTS—PCI Status Register (Intel® High Definition Audio Controller—D27:F0) Offset Address: 06h–07h Default Value: 0010h Bit 15 14 Attribute: Size: Description RO, R/WC 16 bits Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0. SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0. Received Master Abort (RMA) — R/WC. Software clears this bit by writing a 1 to it. 13 0 = No master abort received. 1 = The Intel® High Definition Audio controller sets this bit when, as a bus master, it receives a master abort. When set, the Intel High Definition Audio controller clears the run bit for the channel that received the abort. Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0. Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0. DEVSEL# Timing Status (DEV_STS) — RO. Does not apply. Hardwired to 0. Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0. Fast Back to Back Capable (FB2BC) — RO. Does not apply. Hardwired to 0. Reserved. 66 MHz Capable (66MHZ_CAP) — RO. Does not apply. Hardwired to 0. Capabilities List (CAP_LIST) — RO. Hardwired to 1. Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. Interrupt Status (IS) — RO. 0 = This bit is 0 after the interrupt is cleared. 1 = This bit is 1 when the INTx# is asserted. Note that this bit is not set by an MSI. Reserved. 12 11 10:9 8 7 6 5 4 3 2:0 656 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.5 RID—Revision Identification Register (Intel® High Definition Audio Controller—D27:F0) Offset: Default Value: Bit 7:0 08h See bit description Attribute: Size: Description RO 8 Bits Revision ID — RO. Refer to the Intel® I/O Controller Hub (ICH10) Family Specification Update for the value of the Revision ID Register 18.1.6 PI—Programming Interface Register (Intel® High Definition Audio Controller—D27:F0) Offset: Default Value: Bit 7:0 Programming Interface — RO. 09h 00h Attribute: Size: Description RO 8 bits 18.1.7 SCC—Sub Class Code Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 0Ah Default Value: 03h Bit 7:0 Sub Class Code (SCC) — RO. 03h = Audio Device Attribute: Size: Description RO 8 bits 18.1.8 BCC—Base Class Code Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 0Bh Default Value: 04h Bit 7:0 Base Class Code (BCC) — RO. 04h = Multimedia device Attribute: Size: Description RO 8 bits 18.1.9 CLS—Cache Line Size Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 0Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Cache Line Size — R/W. Implemented as R/W register, but has no functional impact to the ICH10 Datasheet 657 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.10 LT—Latency Timer Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Latency Timer — RO. Hardwired to 00 18.1.11 HEADTYP—Header Type Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 0Eh Default Value: 00h Bit 7:0 Header Type — RO. Hardwired to 00. Attribute: Size: Description RO 8 bits 18.1.12 HDBARL—Intel® High Definition Audio Lower Base Address Register (Intel® High Definition Audio—D27:F0) Address Offset: 10h-13h Default Value: 00000004h Bit 31:14 13:4 3 2:1 0 Attribute: Size: Description R/W, RO 32 bits Lower Base Address (LBA) — R/W. Base address for the Intel® High Definition Audio controller’s memory mapped configuration registers. 16 Kbytes are requested by hardwiring bits 13:4 to 0s. Reserved. Prefetchable (PREF) — RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable Address Range (ADDRNG) — RO. Hardwired to 10b, indicating that this BAR can be located anywhere in 64-bit address space. Space Type (SPTYP) — RO. Hardwired to 0. Indicates this BAR is located in memory space. 18.1.13 HDBARU—Intel® High Definition Audio Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 14h-17h Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Upper Base Address (UBA) — R/W. Upper 32 bits of the Base address for the Intel® High Definition Audio controller’s memory mapped configuration registers. 658 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.14 SVID—Subsystem Vendor Identification Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: Default Value: Function Level Reset: 2Ch–2Dh 0000h No Attribute: Size: R/WO 16 bits The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh), enable the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. This register is not affected by the D3HOT to D0 transition. Bit 15:0 Subsystem Vendor ID — R/WO. Description 18.1.15 SID—Subsystem Identification Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 2Eh–2Fh Default Value: 0000h Function Level Reset: No Attribute: Size: R/WO 16 bits The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. T This register is not affected by the D3HOT to D0 transition. Bit 15:0 Subsystem ID — R/WO. Description 18.1.16 CAPPTR—Capabilities Pointer Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 34h Default Value: 50h Attribute: Size: RO 8 bits This register indicates the offset for the capability pointer. Bit 7:0 Description Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer offset is offset 50h (Power Management Capability) Datasheet 659 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.17 INTLN—Interrupt Line Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 3Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Interrupt Line (INT_LN) — R/W. This data is not used by the Intel® ICH10. It is used to communicate to software the interrupt line that the interrupt pin is connected to. 18.1.18 INTPN—Interrupt Pin Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 3Dh Default Value: See Description Bit 7:4 3:0 Reserved. Interrupt Pin — RO. This reflects the value of D27IP.ZIP (Chipset Config Registers:Offset 3110h:bits 3:0). Attribute: Size: Description RO 8 bits 18.1.19 HDCTL—Intel® High Definition Audio Control Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 40h Default Value: 01h Bit 7:1 0 Reserved. Intel® High Definition Signal Mode — RO. This bit is hardwired to 1 (High Definition Audio mode) Attribute: Size: Description RO 8 bits 660 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.20 TCSEL—Traffic Class Select Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: Default Value: Function Level Reset: 44h 00h No Attribute: Size: R/W 8 bits This register assigned the value to be placed in the TC field. CORB and RIRB data will always be assigned TC0. Bit 7:3 Reserved. Intel® HIgh Definition Audio Traffic Class Assignment (TCSEL)— R/W. This register assigns the value to be placed in the Traffic Class field for input data, output data, and buffer descriptor transactions. 000 = TC0 001 = TC1 010 = TC2 2:0 011 = TC3 100 = TC4 101 = TC5 110 = TC6 111 = TC7 NOTE: These bits are not reset on D3HOT to D0 transition; however, they are reset by PLTRST#. Description 18.1.21 PID—PCI Power Management Capability ID Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: Default Value: Function Level Reset: Bit 15:8 7:0 50h-51h 6001h No (Bits 7:0 only) Attribute: Size: R/WO, RO 16 bits Description Next Capability (Next) — R/WO. Points to the next capability structure (MSI). Cap ID (CAP) — RO. Hardwired to 01h. Indicates that this pointer is a PCI power management capability. These bits are not reset by Function Level Reset. Datasheet 661 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.22 PC—Power Management Capabilities Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 52h-53h Default Value: C842h Bit 15:11 10 9 8:6 5 4 3 2:0 Attribute: Size: Description RO 16 bits PME Support — RO. Hardwired to 11001b. Indicates PME# can be generated from D3 and D0 states. D2 Support — RO. Hardwired to 0. Indicates that D2 state is not supported. D1 Support —RO. Hardwired to 0. Indicates that D1 state is not supported. Aux Current — RO. Hardwired to 001b. Reports 55 mA maximum suspend well current required when in the D3COLD state. Device Specific Initialization (DSI) — RO. Hardwired to 0. Indicates that no device specific initialization is required. Reserved PME Clock (PMEC) — RO. Does not apply. Hardwired to 0. Version — RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power Management Specification. 662 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.23 PCS—Power Management Control and Status Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: Default Value: Function Level Reset: Bit 31:24 23 22 21:16 54h-57h 00000000h No Attribute: Size: RO, R/W, R/WC 32 bits Description Data — RO. Does not apply. Hardwired to 0. Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0. B2/B3 Support — RO. Does not apply. Hardwired to 0. Reserved. PME Status (PMES) — R/WC. 0 = Software clears the bit by writing a 1 to it. 1 = This bit is set when the Intel® High Definition Audio controller would normally assert the PME# signal independent of the state of the PME_EN bit (bit 8 in this register). This bit is in the resume well and is cleared by a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately. 15 14:9 Reserved PME Enable (PMEE) — R/W. 0 = Disable 1 = When set and if corresponding PMES also set, the Intel High Definition Audio controller sets the PME_B0_STS bit in the GPE0_STS register (PMBASE +28h). This bit in the resume well and is cleared on a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately. 8 7:2 Reserved Power State (PS) — R/W. This field is used both to determine the current power state of the Intel High Definition Audio controller and to set a new power state. 00 = D0 state 11 = D3HOT state Others = reserved 1:0 NOTES: 1. If software attempts to write a value of 01b or 10b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 2. When in the D3HOT states, the Intel High Definition Audio controller’s configuration space is available, but the IO and memory space are not. Additionally, interrupts are blocked. 3. When software changes this value from D3HOT state to the D0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. Datasheet 663 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.24 MID—MSI Capability ID Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 60h-61h Default Value: 7005h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (Next) — RO. Hardwired to 70h. Points to the PCI Express* capability structure. Cap ID (CAP) — RO. Hardwired to 05h. Indicates that this pointer is a MSI capability 18.1.25 MMC—MSI Message Control Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 62h-63h Default Value: 0080h Bit 15:8 7 6:4 3:1 Reserved 64b Address Capability (64ADD) — RO. Hardwired to 1. Indicates the ability to generate a 64-bit message address Multiple Message Enable (MME) — RO. Normally this is a R/W register. However since only 1 message is supported, these bits are hardwired to 000 = 1 message. Multiple Message Capable (MMC) — RO. Hardwired to 0 indicating request for 1 message. MSI Enable (ME) — R/W. 0 0 = an MSI may not be generated 1 = an MSI will be generated instead of an INTx signal. Attribute: Size: Description RO, R/W 16 bits 18.1.26 MMLA—MSI Message Lower Address Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 64h-67h Default Value: 00000000h Bit 31:2 1:0 Attribute: Size: Description RO, R/W 32 bits Message Lower Address (MLA) — R/W. Lower address used for MSI message. Reserved. 18.1.27 MMUA—MSI Message Upper Address Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 68h-6Bh Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Message Upper Address (MUA) — R/W. Upper 32-bits of address used for MSI message. 664 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.28 MMD—MSI Message Data Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 6Ch-6Dh Default Value: 0000h Bit 15:0 Attribute: Size: Description R/W 16 bits Message Data (MD) — R/W. Data used for MSI message. 18.1.29 PXID—PCI Express* Capability ID Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 70h-71h Default Value: 0010h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (Next) — RO. Hardwired to 0. Indicates that this is the last capability structure in the list. Cap ID (CAP) — RO. Hardwired to 10h. Indicates that this pointer is a PCI Express* capability structure 18.1.30 PXC—PCI Express* Capabilities Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 72h-73h Default Value: 0091h Bit 15:14 13:9 8 7:4 3:0 Reserved Interrupt Message Number (IMN) — RO. Hardwired to 0. Slot Implemented (SI) — RO. Hardwired to 0. Device/Port Type (DPT) — RO. Hardwired to 1001b. Indicates that this is a Root Complex Integrated endpoint device. Capability Version (CV) — RO. Hardwired to 0001b. Indicates version #1 PCI Express capability Attribute: Size: Description RO 16 bits Datasheet 665 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.31 DEVCAP—Device Capabilities Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 74h-77h Default Value: 10000000h Function Level Reset: No Bit 31:29 28 27:26 25:18 17:15 14 13 12 11:9 8:6 5 4:3 2:0 Reserved Function Level Reset (FLR) — R/WO. A 1 indicates that the ICH10 HD Audio Controller supports the Function Level Reset Capability. Captured Slot Power Limit Scale (SPLS) — RO. Hardwired to 0. Captured Slot Power Limit Value (SPLV) — RO. Hardwired to 0. Reserved Power Indicator Present — RO. Hardwired to 0. Attention Indicator Present — RO. Hardwired to 0. Attention Button Present — RO. Hardwired to 0. Endpoint L1 Acceptable Latency — R/WO. Endpoint L0s Acceptable Latency — R/WO. Extended Tag Field Support — RO. Hardwired to 0. Indicates 5-bit tag field support Phantom Functions Supported — RO. Hardwired to 0. Indicates that phantom functions not supported Max Payload Size Supported — RO. Hardwired to 0. Indicates 128-B maximum payload size capability Attribute: Size: R/WO, RO 32 bits Description 666 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.32 DEVC—Device Control Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: Default Value: Function Level Reset: Bit 15 78h-79h 0800h No (Bit 11 Only) Attribute: Size: R/W, RO 16 bits Description Initiate FLR (IF) — R/W. This bit is used to initiate FLR transition. 1 = A write of 1 initiates FLR transition. Since hardware does not respond to any cycles until FLR completion, the read value by software from this bit is 0. Max Read Request Size — RO. Hardwired to 0 enabling 128B maximum read request size. No Snoop Enable (NSNPEN) — R/W. 0 = The Intel® High Definition Audio controller will not set the No Snoop bit. In this case, isochronous transfers will not use VC1 (VCi) even if it is enabled since VC1 is never snooped. Isochronous transfers will use VC0. 1 = The Intel High Definition Audio controller is permitted to set the No Snoop bit in the Requester Attributes of a bus master transaction. In this case, VC0 or VC1 may be used for isochronous transfers. NOTE: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#. This bit is not reset by Function Level Reset. Auxiliary Power Enable — RO. Hardwired to 0, indicating that Intel High Definition Audio device does not draw AUX power Phantom Function Enable — RO. Hardwired to 0 disabling phantom functions. Extended Tag Field Enable — RO. Hardwired to 0 enabling 5-bit tag. Max Payload Size — RO. Hardwired to 0 indicating 128B. Enable Relaxed Ordering — RO. Hardwired to 0 disabling relaxed ordering. Unsupported Request Reporting Enable — R/W. Not implemented. Fatal Error Reporting Enable — R/W. Not implemented. Non-Fatal Error Reporting Enable — R/W. Not implemented. Correctable Error Reporting Enable — R/W. Not implemented. 14:12 11 10 9 8 7:5 4 3 2 1 0 Datasheet 667 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.33 DEVS—Device Status Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 7Ah-7Bh Default Value: 0010h Bit 15:6 Reserved Transactions Pending — RO. 5 0 = Indicates that completions for all non-posted requests have been received 1 = Indicates that Intel® High Definition Audio controller has issued non-posted requests which have not been completed. AUX Power Detected — RO. Hardwired to 1 indicating the device is connected to resume power Unsupported Request Detected — RO. Not implemented. Hardwired to 0. Fatal Error Detected — RO. Not implemented. Hardwired to 0. Non-Fatal Error Detected — RO. Not implemented. Hardwired to 0. Correctable Error Detected — RO. Not implemented. Hardwired to 0. Attribute: Size: Description RO 16 bits 4 3 2 1 0 18.1.34 VCCAP—Virtual Channel Enhanced Capability Header (Intel® High Definition Audio Controller—D27:F0) Address Offset: 100h-103h Default Value: 13010002h Bit 31:20 Attribute: Size: Description R/WO 32 bits Next Capability Offset — R/WO. Points to the next capability header. 130h = Root Complex Link Declaration Enhanced Capability Header 000h = Root Complex Link Declaration Enhanced Capability Header is not supported. Capability Version — R/WO. 19:16 0h = PCI Express Virtual channel capability and the Root Complex Topology Capability structure are not supported. 1h = PCI Express Virtual channel capability and the Root Complex Topology Capability structure are supported. PCI Express* Extended Capability — R/WO. 15:0 0000h =PCI Express Virtual channel capability and the Root Complex Topology Capability structure are not supported. 0002h =PCI Express Virtual channel capability and the Root Complex Topology Capability structure are supported. 668 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.35 PVCCAP1—Port VC Capability Register 1 (Intel® High Definition Audio Controller—D27:F0) Address Offset: 104h-107h Default Value: 00000001h Bit 31:12 11:10 9:8 7 6:4 3 2:0 Reserved. Port Arbitration Table Entry Size — RO. Hardwired to 0 since this is an endpoint device. Reference Clock — RO. Hardwired to 0 since this is an endpoint device. Reserved. Low Priority Extended VC Count — RO. Hardwired to 0. Indicates that only VC0 belongs to the low priority VC group Reserved. Extended VC Count — RO. Hardwired to 001b. Indicates that 1 extended VC (in addition to VC0) is supported by the Intel® High Definition Audio controller. Attribute: Size: Description RO 32 bits 18.1.36 PVCCAP2 — Port VC Capability Register 2 (Intel® High Definition Audio Controller—D27:F0) Address Offset: 108h-10Bh Default Value: 00000000h Bit 31:24 23:8 7:0 Attribute: Size: Description RO 32 bits VC Arbitration Table Offset — RO. Hardwired to 0 indicating that a VC arbitration table is not present. Reserved. VC Arbitration Capability — RO. Hardwired to 0. These bits are not applicable since the Intel® High Definition Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1 register. 18.1.37 PVCCTL — Port VC Control Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 10Ch-10Dh Default Value: 0000h Bit 15:4 3:1 Reserved. VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However, these bits are not applicable since the Intel® High Definition Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1 register Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not present. Attribute: Size: Description RO 16 bits 0 Datasheet 669 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.38 PVCSTS—Port VC Status Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 10Eh-10Fh Default Value: 0000h Bit 15:1 0 Reserved. VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not present. Attribute: Size: Description RO 16 bits 18.1.39 VC0CAP—VC0 Resource Capability Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 110h-113h Default Value: 00000000h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: Description RO 32 bits Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for endpoint devices Reserved. Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint devices Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for endpoint devices. Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for endpoint devices Reserved. Port Arbitration Capability — RO. Hardwired to 0 since this field is not valid for endpoint devices 670 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.40 VC0CTL—VC0 Resource Control Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 114h-117h Default Value: 800000FFh Function Level Reset: No Bit 31 30:27 26:24 23:20 19:17 16 15:8 7:0 Attribute: Size: R/W, RO 32 bits Description VC0 Enable — RO. Hardwired to 1 for VC0. Reserved. VC0 ID — RO. Hardwired to 0 since the first VC is always assigned as VC0. Reserved. Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint devices. Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. TC/VC0 Map — R/W, RO. Bit 0 is hardwired to 1 since TC0 is always mapped VC0. Bits [7:1] are implemented as R/W bits. 18.1.41 VC0STS—VC0 Resource Status Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 11Ah-11Bh Default Value: 0000h Bit 15:2 1 0 Reserved. VC0 Negotiation Pending — RO. Hardwired to 0 since this bit does not apply to the integrated Intel® High Definition Audio device. Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for endpoint devices. Attribute: Size: Description RO 16 bits Datasheet 671 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.42 VCiCAP—VCi Resource Capability Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 11Ch-11Fh Default Value: 00000000h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: Description RO 32 bits Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint devices. Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for endpoint devices. Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved Port Arbitration Capability — RO. Hardwired to 0 since this field is not valid for endpoint devices. 18.1.43 VCiCTL—VCi Resource Control Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: Default Value: Function Level Reset: Bit VCi Enable — R/W. 0 = VCi is disabled 31 1 = VCi is enabled NOTE: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#. 30:27 26:24 23:20 19:17 16 15:8 Reserved. VCi ID — R/W. This field assigns a VC ID to the VCi resource. This field is not used by the ICH10 hardware, but it is R/W to avoid confusing software. Reserved. Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint devices. Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. TC/VCi Map — R/W, RO. This field indicates the TCs that are mapped to the VCi resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1] are implemented as R/W bits. This field is not used by the ICH10 hardware, but it is R/W to avoid confusing software. 120h-123h 00000000h No Attribute: Size: R/W, RO 32 bits Description 7:0 672 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.1.44 VCiSTS—VCi Resource Status Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 126h-127h Default Value: 0000h Bit 15:2 1 0 Reserved. VCi Negotiation Pending — RO. Does not apply. Hardwired to 0. Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for endpoint devices. Attribute: Size: Description RO 16 bits 18.1.45 RCCAP—Root Complex Link Declaration Enhanced Capability Header Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 130h Default Value: 00010005h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32 bits Next Capability Offset — RO. Hardwired to 0 indicating this is the last capability. Capability Version — RO. Hardwired to 1h. PCI Express* Extended Capability ID — RO. Hardwired to 0005h. 18.1.46 ESD—Element Self Description Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 134h-137h Default Value: 0F000100h Bit 31:24 23:16 15:8 7:4 3:0 Attribute: Size: Description RO 32 bits Port Number — RO. Hardwired to 0Fh indicating that the Intel® High Definition Audio controller is assigned as Port #15d. Component ID — RO. This field returns the value of the ESD.CID field of the chip configuration section. ESD.CID is programmed by BIOS. Number of Link Entries — RO. The Intel High Definition Audio only connects to one device, the ICH10 egress port. Therefore this field reports a value of 1h. Reserved. Element Type (ELTYP) — RO. The Intel High Definition Audio controller is an integrated Root Complex Device. Therefore, the field reports a value of 0h. Datasheet 673 Intel® High Definition Audio Controller Registers (D27:F0) 18.1.47 L1DESC—Link 1 Description Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 140h-143h Default Value: 00000001h Bit 31:24 23:16 15:2 1 0 Attribute: Size: Description RO 32 bits Target Port Number — RO. The Intel High Definition Audio controller targets the Intel® ICH10’s Port 0. Target Component ID — RO. This field returns the value of the ESD.CID field of the chip configuration section. ESD.CID is programmed by BIOS. Reserved. Link Type — RO. Hardwired to 0 indicating Type 0. Link Valid — RO. Hardwired to 1. 18.1.48 L1ADDL—Link 1 Lower Address Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 148h-14Bh Default Value: See Register Description Bit 31:14 13:0 Attribute: Size: RO 32 bits Description Link 1 Lower Address — RO. Hardwired to match the RCBA register value in the PCILPC bridge (D31:F0:F0h). Reserved. 18.1.49 L1ADDU—Link 1 Upper Address Register (Intel® High Definition Audio Controller—D27:F0) Address Offset: 14Ch-14Fh Default Value: 00000000h Bit 31:0 Attribute: Size: Description RO 32 bits Link 1 Upper Address — RO. Hardwired to 00000000h. 674 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2 Intel® High Definition Audio Memory Mapped Configuration Registers (Intel® High Definition Audio— D27:F0) The base memory location for these memory mapped configuration registers is specified in the HDBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The individual registers are then accessible at HDBAR + Offset as indicated in Table 18.2. These memory mapped registers must be accessed in byte, word, or dword quantities. Table 18-2. Intel® High Definition Audio PCI Register Address Map (Intel® High Definition Audio D27:F0) (Sheet 1 of 4) HDBAR + Offset 00h–01h 02h 03h 04h–05h 06h–07h 08h–0Bh 0Ch–0Dh 0Eh–0Fh 10h–11h 12h–13h 18h–19h 1Ah–1Bh 1Ch–1Fh 20h–23h 24h–27h 30h–33h 34h–37h 40h–43h 44h–47h 48h–49h 4Ah–4Bh 4Ch 4Dh 4Eh 50h–53h 54h–57h 58h–59h 5Ah–5Bh 5Ch Mnemonic GCAP VMIN VMAJ OUTPAY INPAY GCTL WAKEEN STATESTS GSTS Rsv OUTSTRMPAY INSTRMPAY Rsv INTCTL INTSTS WALCLK SSYNC CORBLBASE CORBUBASE CORBWP CORBRP CORBCTL CORBST CORBSIZE RIRBLBASE RIRBUBASE RIRBWP RINTCNT RIRBCTL Register Name Global Capabilities Minor Version Major Version Output Payload Capability Input Payload Capability Global Control Wake Enable State Change Status Global Status Reserved Output Stream Payload Capability Input Stream Payload Capability Reserved Interrupt Control Interrupt Status Wall Clock Counter Stream Synchronization CORB Lower Base Address CORB Upper Base Address CORB Write Pointer CORB Read Pointer CORB Control CORB Status CORB Size RIRB Lower Base Address RIRB Upper Base Address RIRB Write Pointer Response Interrupt Count RIRB Control Default 4401h 00h 01h 003Ch 001Dh 00000000h 0000h 0000h 0000h 0000h 0030h 0018h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 0000h 0000h 00h 00h 42h 00000000h 00000000h 0000h 0000h 00h Access RO RO RO RO RO R/W R/W R/WC R/WC RO RO RO RO R/W RO RO R/W R/W, RO R/W R/W R/W, RO R/W R/WC RO R/W, RO R/W R/W, RO R/W R/W Datasheet 675 Intel® High Definition Audio Controller Registers (D27:F0) Table 18-2. Intel® High Definition Audio PCI Register Address Map (Intel® High Definition Audio D27:F0) (Sheet 2 of 4) HDBAR + Offset 5Dh 5Eh 60h–63h 64h–67h 68h–69h 70h–73h 74h–77h 80–82h 83h 84h–87h 88h–8Bh 8Ch–8Dh 8Eh–8F 90h–91h 92h–93h 98h–9Bh 9Ch–9Fh A0h–A2h A3h A4h–A7h A8h–ABh ACh–ADh AEh–AFh B0h–B1h B2h–B3h B8h–BBh BCh–BFh C0h–C2h C3h C4h–C7h C8h–CBh Mnemonic RIRBSTS RIRBSIZE IC IR IRS DPLBASE DPUBASE ISD0CTL ISD0STS ISD0LPIB ISD0CBL ISD0LVI ISD0FIFOW ISD0FIFOS ISD0FMT ISD0BDPL ISD0BDPU ISD1CTL ISD1STS ISD1LPIB ISD1CBL ISD1LVI ISD1FIFOW ISD1FIFOS ISD1FMT ISD1BDPL ISD1BDPU ISD2CTL ISD2STS ISD2LPIB ISD2CBL Register Name RIRB Status RIRB Size Immediate Command Immediate Response Immediate Command Status DMA Position Lower Base Address DMA Position Upper Base Address Input Stream Descriptor 0 (ISD0) Control ISD0 Status ISD0 Link Position in Buffer ISD0 Cyclic Buffer Length ISD0 Last Valid Index ISD0 FIFO Watermark ISD0 FIFO Size ISD0 Format ISD0 Buffer Descriptor List PointerLower Base Address ISD0 Buffer Description List PointerUpper Base Address Input Stream Descriptor 1(ISD01) Control ISD1 Status ISD1 Link Position in Buffer ISD1 Cyclic Buffer Length ISD1 Last Valid Index ISD1 FIFO Watermark ISD1 FIFO Size ISD1 Format ISD1 Buffer Descriptor List PointerLower Base Address ISD1 Buffer Description List PointerUpper Base Address Input Stream Descriptor 2 (ISD2) Control ISD2 Status ISD2 Link Position in Buffer ISD2 Cyclic Buffer Length Default 00h 42h 00000000h 00000000h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 0077h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 0077h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h Access R/WC RO R/W RO R/W, R/ WC R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W RO R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W RO R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W 676 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) Table 18-2. Intel® High Definition Audio PCI Register Address Map (Intel® High Definition Audio D27:F0) (Sheet 3 of 4) HDBAR + Offset CCh–CDh CEh–CFh D0h–D1h D2h–D3h D8h–DBh DCh–DFh E0h–E2h E3h E4h–E7h E8h–EBh ECh–EDh EEh–EFh F0h–F1h F2h–F3h F8h–FBh FCh–FFh 100h–102h 103h 104h–107h 108h–10Bh 10Ch–10Dh 10Eh–10Fh 110h–111h 112–113h 118h–11Bh 11Ch–11Fh 120h–122h 123h 124h–127h 128h–12Bh Mnemonic ISD2LVI ISD1FIFOW ISD2FIFOS ISD2FMT ISD2BDPL ISD2BDPU ISD3CTL ISD3STS ISD3LPIB ISD3CBL ISD3LVI ISD3FIFOW ISD3FIFOS ISD3FMT ISD3BDPL ISD3BDPU OSD0CTL OSD0STS OSD0LPIB OSD0CBL OSD0LVI OSD0FIFOW OSD0FIFOS OSD0FMT OSD0BDPL OSD0BDPU OSD1CTL OSD1STS OSD1LPIB OSD1CBL Register Name ISD2 Last Valid Index ISD1 FIFO Watermark ISD2 FIFO Size ISD2 Format ISD2 Buffer Descriptor List PointerLower Base Address ISD2 Buffer Description List PointerUpper Base Address Input Stream Descriptor 3 (ISD3) Control ISD3 Status ISD3 Link Position in Buffer ISD3 Cyclic Buffer Length ISD3 Last Valid Index ISD3 FIFO Watermark ISD3 FIFO Size ISD3 Format ISD3 Buffer Descriptor List PointerLower Base Address ISD3 Buffer Description List PointerUpper Base Address Output Stream Descriptor 0 (OSD0) Control OSD0 Status OSD0 Link Position in Buffer OSD0 Cyclic Buffer Length OSD0 Last Valid Index OSD0 FIFO Watermark OSD0 FIFO Size OSD0 Format OSD0 Buffer Descriptor List PointerLower Base Address OSD0 Buffer Description List PointerUpper Base Address Output Stream Descriptor 1 (OSD1) Control OSD1 Status OSD1 Link Position in Buffer OSD1 Cyclic Buffer Length Default 0000h 0004h 0077h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 0077h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 00BFh 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h Access R/W R/W RO R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W RO R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W R/W R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W Datasheet 677 Intel® High Definition Audio Controller Registers (D27:F0) Table 18-2. Intel® High Definition Audio PCI Register Address Map (Intel® High Definition Audio D27:F0) (Sheet 4 of 4) HDBAR + Offset 12Ch–12Dh 12Eh–12Fh 130h–131h 132h–133h 138h–13Bh 13Ch–13Fh 140h–142h 143h 144h–147h 148h–14Bh 14Ch–14Dh 14Eh–14Fh 150h–151h 152h–153h 158h–15Bh 15Ch–15Fh 160h–162h 163h 164h–167h 168h–16Bh 16Ch–16Dh 16Eh–16Fh 170h–171h 172h–173h 178h–17Bh 17Ch–17Fh Mnemonic OSD1LVI OSD1FIFOW OSD1FIFOS OSD1FMT OSD1BDPL OSD1BDPU OSD2CTL OSD2STS OSD2LPIB OSD2CBL OSD2LVI OSD2FIFOW OSD2FIFOS OSD2FMT OSD2BDPL OSD2BDPU OSD3CTL OSD3STS OSD3LPIB OSD3CBL OSD3LVI OSD3FIFOW OSD3FIFOS OSD3FMT OSD3BDPL OSD3BDPU Register Name OSD1 Last Valid Index OSD1 FIFO Watermark OSD1 FIFO Size OSD1 Format OSD1 Buffer Descriptor List PointerLower Base Address OSD1 Buffer Description List PointerUpper Base Address Output Stream Descriptor 2 (OSD2) Control OSD2 Status OSD2 Link Position in Buffer OSD2 Cyclic Buffer Length OSD2 Last Valid Index OSD2 FIFO Watermark OSD2 FIFO Size OSD2 Format OSD2 Buffer Descriptor List PointerLower Base Address OSD2 Buffer Description List PointerUpper Base Address Output Stream Descriptor 3 (OSD3) Control OSD3 Status OSD3 Link Position in Buffer OSD3 Cyclic Buffer Length OSD3 Last Valid Index OSD3 FIFO Watermark OSD3 FIFO Size OSD3 Format OSD3 Buffer Descriptor List PointerLower Base Address OSD3 Buffer Description List PointerUpper Base Address Default 0000h 0004h 00BFh 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 00BFh 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 00BFh 0000h 00000000h 00000000h Access R/W R/W R/W R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W R/W R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W R/W R/W R/W, RO R/W 678 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.1 GCAP—Global Capabilities Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 00h Default Value: 4401h Bit 15:12 11:8 7:3 2 1 Attribute: Size: Description RO 16 bits Number of Output Stream Supported — RO. Hardwired to 0100b indicating that the ICH10 Intel® High Definition Audio controller supports 4 output streams. Number of Input Stream Supported — RO. Hardwired to 0100b indicating that the ICH10 Intel High Definition Audio controller supports 4 input streams. Number of Bidirectional Stream Supported — RO. Hardwired to 0 indicating that the ICH10 Intel High Definition Audio controller supports 0 bidirectional stream. Reserved. Number of Serial Data Out Signals — RO. Hardwired to 0 indicating that the ICH10 Intel High Definition Audio controller supports 1 serial data output signal. 64-bit Address Supported — RO. Hardwired to 1b indicating that the ICH10 Intel High Definition Audio controller supports 64-bit addressing for BDL addresses, data buffer addressees, and command buffer addresses. 0 18.2.2 VMIN—Minor Version Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 02h Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Minor Version — RO. Hardwired to 0 indicating that the Intel® ICH10 supports minor revision number 00h of the Intel® High Definition Audio specification. 18.2.3 VMAJ—Major Version Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 03h Default Value: 01h Bit 7:0 Attribute: Size: Description RO 8 bits Major Version — RO. Hardwired to 01h indicating that the Intel® ICH10 supports major revision number 1 of the Intel® High Definition Audio specification. Datasheet 679 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.4 OUTPAY—Output Payload Capability Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 04h Default Value: 003Ch Bit 15:7 Reserved. Output Payload Capability — RO. Hardwired to 3Ch indicating 60 word payload. This field indicates the total output payload available on the link. This does not include bandwidth used for command and control. This measurement is in 16-bit word quantities per 48 MHz frame. The default link clock of 24.000 MHz (the data is double pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for command and control, leaving 60 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... FFh = 256 word payload. Attribute: Size: Description RO 16 bits 6:0 18.2.5 INPAY—Input Payload Capability Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 06h Default Value: 001Dh Bit 15:7 Reserved. Input Payload Capability — RO. Hardwired to 1Dh indicating 29 word payload. This field indicates the total output payload available on the link. This does not include bandwidth used for response. This measurement is in 16-bit word quantities per 48 MHz frame. The default link clock of 24.000 MHz provides 500 bits per frame, or 31.25 words in total. 36 bits are used for response, leaving 29 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... FFh = 256 word payload. Attribute: Size: Description RO 16 bits 6:0 680 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.6 GCTL—Global Control Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 08h Default Value: 00000000h Bit 31:9 Reserved. Accept Unsolicited Response Enable — R/W. 8 0 = Unsolicited responses from the codecs are not accepted. 1 = Unsolicited response from the codecs are accepted by the controller and placed into the Response Input Ring Buffer. Reserved. Flush Control — R/W. Writing a 1 to this bit initiates a flush. When the flush completion is received by the controller, hardware sets the Flush Status bit and clears this Flush Control bit. Before a flush cycle is initiated, the DMA Position Buffer must be programmed with a valid memory address by software, but the DMA Position Buffer bit 0 needs not be set to enable the position reporting mechanism. Also, all streams must be stopped (the associated RUN bit must be 0). When the flush is initiated, the controller will flush the pipelines to memory to ensure that the hardware is ready to transition to a D3 state. Setting this bit is not a critical step in the power state transition if the content of the FIFOs is not critical. Controller Reset # — R/W. 0 = Writing a 0 causes the Intel High Definition Audio controller to be reset. All state machines, FIFOs and non-resume well memory mapped configuration registers (not PCI configuration registers) in the controller will be reset. The Intel High Definition Audio link RESET# signal will be asserted, and all other link signals will be driven to their default values. After the hardware has completed sequencing into the reset state, it will report a 0 in this bit. Software must read a 0 from this bit to verify the controller is in reset. 1 = Writing a 1 causes the controller to exit its reset state and deassert the Intel High Definition Audio link RESET# signal. Software is responsible for setting/clearing this bit such that the minimum Intel High Definition Audio link RESET# signal assertion pulse width specification is met. When the controller hardware is ready to begin operation, it will report a 1 in this bit. Software must read a 1 from this bit before accessing any controller registers. This bit defaults to a 0 after Hardware reset, therefore, software needs to write a 1 to this bit to begin operation. NOTES: 1. The CORB/RIRB RUN bits and all stream RUN bits must be verified cleared to 0 before writing a 0 to this bit in order to assure a clean re-start. 2. When setting or clearing this bit, software must ensure that minimum link timing requirements (minimum RESET# assertion time, etc.) are met. 3. When this bit is 0 indicating that the controller is in reset, writes to all Intel High Definition Audio memory mapped registers are ignored as if the device is not present. The only exception is this register itself. The Global Control register is write-able as a DWord, Word, or Byte even when CRST# (this bit) is 0 if the byte enable for the byte containing the CRST# bit (Byte Enable 0) is active. If Byte Enable 0 is not active, writes to the Global Control register will be ignored when CRST# is 0. When CRST# is 0, reads to Intel High Definition Audio memory mapped registers will return their default value except for registers that are not reset with PLTRST# or on a D3HOT to D0 transition. Attribute: Size: Description R/W 32 bits 7:2 1 0 Datasheet 681 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.7 WAKEEN—Wake Enable Register (Intel® High Definition Audio Controller—D27:F0) Memory Address: Default Value: Function Level Reset: Bit 15:4 Reserved. SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may generate a wake event. A 1b in the bit mask indicates that the associated SDIN signal is enabled to generate a wake. Bit 0 is used for SDI[0] Bit 1 is used for SDI[1] 3:0 Bit 2 is used for SDI[2] Bit 3 is used for SDI[3] NOTE: These bits are in the resume well and only cleared on a power on reset. Software must not make assumptions about the reset state of these bits and must set them appropriately. HDBAR + 0Ch 0000h No Attribute: Size: R/W 16 bits Description 18.2.8 STATESTS—State Change Status Register (Intel® High Definition Audio Controller—D27:F0) Memory Address: Default Value: Function Level Reset: Bit 15:4 Reserved. SDIN State Change Status Flags — R/WC. Flag bits that indicate which SDI signal(s) received a state change event. The bits are cleared by writing 1s to them. Bit 0 = SDI[0] Bit 1 = SDI[1] 3:0 Bit 2 = SDI[2] Bit 3 = SDI[3] NOTE: These bits are in the resume well and only cleared on a power on reset. Software must not make assumptions about the reset state of these bits and must set them appropriately. HDBAR + 0Eh 0000h No Attribute: Size: R/WC 16 bits Description 682 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.9 GSTS—Global Status Register (Intel® High Definition Audio Controller—D27:F0) Memory Address: Default Value: Bit 15:4 3 2 Reserved. Reserved Reserved Flush Status — R/WC. This bit is set to 1 by hardware to indicate that the flush cycle initiated when the Flush Control bit (HDBAR + 08h, bit 1) was set has completed. Software must write a 1 to clear this bit before the next time the Flush Control bit is set to clear the bit. Reserved. HDBAR + 10h 0000h Attribute: Size: Description R/WC 16 bits 1 0 18.2.10 OUTSTRMPAY—Output Stream Payload Capability (Intel® High Definition Audio Controller—D27:F0) Memory Address: Default Value: Bit HDBAR + 18h 0030h Attribute: Size: Description RO 16 bits Output FIFO Padding Type (OPADTYPE)— RO: Indicates how the controller pads the samples in the controller's buffer (FIFO). Controllers may not pad at all or may pad to byte or memory container sizes. 15:14 0h 1h 2h 3h =Controller pads all samples to bytes = Reserved = Controller pads to memory container size = Controller does not pad and uses samples directly 13:0 Output Stream Payload Capability (OUTSTRMPAY)— RO: Indicates maximum number of words per frame for any single output stream. This measurement is in 16 bit word quantities per 48 kHz frame. 48 Words (96B) is the maximum supported, therefore a value of 30h is reported in this register. The value does not specify the number of words actually transmitted in the frame, but is the size of the data in the controller buffer (FIFO) after the samples are padded as specified by OPADTYPE. Thus to compute the supported streams, each sample is padded according to OPADTYPE and then multiplied by the number of channels and samples per frame. If this computed value is larger than OUTSTRMPAY then that stream is not supported. The value specified is not affected by striping. Software must ensure that a format which would cause more Words per frame than indicated is not programmed into the Output Stream Descriptor Register. The value may be larger than the OUTPAY register value in some cases. Datasheet 683 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.11 INSTRMPAY—Input Stream Payload Capability (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 1Ah Default Value: 0018h Bit Attribute: Size: Description RO 16 bits Input FIFO Padding Type (IPADTYPE)— RO. Indicates how the controller pads the samples in the controller's buffer (FIFO). Controllers may not pad at all or may pad to byte or memory container sizes. 15:14 0h 1h 2h 3h = = = = Controller pads all samples to bytes Reserved Controller pads to memory container size Controller does not pad and uses samples directly Input Stream Payload Capability (INSTRMPAY)— RO. Indicates the maximum number of Words per frame for any single input stream. This measurement is in 16-bit Word quantities per 48-kHz frame. 24 Words (48B) is the maximum supported, therefore a value of 18h is reported in this register. The value does not specify the number of words actually transmitted in the frame, but is the size of the data as it will be placed into the controller's buffer (FIFO). Thus samples will be padded according to IPADTYPE before being stored into controller buffer. To compute the supported streams, each sample is padded according to IPADTYPE and then multiplied by the number of channels and samples per frame. If this computed value is larger than INSTRMPAY then that stream is not supported. As the inbound stream tag is not stored with the samples it is not included in the word count. The value may be larger than INPAY register value in some cases, although values less than INPAY may also be invalid due to overhead. Software must ensure that a format which would cause more Words per frame than indicated is not programmed into the Input Stream Descriptor Register. 13:0 684 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.12 INTCTL—Interrupt Control Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 20h Default Value: 00000000h Bit Attribute: Size: Description R/W 32 bits 31 Global Interrupt Enable (GIE) — R/W. Global bit to enable device interrupt generation. 1 = When set to 1, the Intel® High Definition Audio function is enabled to generate an interrupt. This control is in addition to any bits in the bus specific address space, such as the Interrupt Enable bit in the PCI configuration space. NOTE: This bit is not affected by the D3HOT to D0 transition. Controller Interrupt Enable (CIE) — R/W. Enables the general interrupt for controller functions. 1 = When set to 1, the controller generates an interrupt when the corresponding status bit gets set due to a Response Interrupt, a Response Buffer Overrun, and State Change events. NOTE: This bit is not affected by the D3HOT to D0 transition. 30 29:8 Reserved Stream Interrupt Enable (SIE) — R/W. When set to 1, the individual streams are enabled to generate an interrupt when the corresponding status bits get set. A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry being completed, or as a result of a FIFO error (underrun or overrun) occurring. Control over the generation of each of these sources is in the associated Stream Descriptor. The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. 7:0 Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4 Datasheet 685 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.13 INTSTS—Interrupt Status Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 24h Default Value: 00000000h Bit 31 Attribute: Size: Description RO 32 bits Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits in this register. NOTE: This bit is not affected by the D3HOT to D0 transition. Controller Interrupt Status (CIS) — RO. Status of general controller interrupt. 1 = Interrupt condition occurred due to a Response Interrupt, a Response Buffer Overrun Interrupt, or a SDIN State Change event. The exact cause can be determined by interrogating other registers. This bit is an OR of all of the stated interrupt status bits for this register. NOTES: 1. This bit is set regardless of the state of the corresponding interrupt enable bit, but a hardware interrupt will not be generated unless the corresponding enable bit is set. 2. This bit is not affected by the D3HOT to D0 transition. Reserved Stream Interrupt Status (SIS) — RO. 1 = Interrupt condition occurred on the corresponding stream. This bit is an OR of all of the stream’s interrupt status bits. NOTE: These bits are set regardless of the state of the corresponding interrupt enable bits. The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. 30 29:8 7:0 Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4 18.2.14 WALCLK—Wall Clock Counter Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 30h Default Value: 00000000h Bit Attribute: Size: Description RO 32 bits 31:0 Wall Clock Counter — RO. 32 bit counter that is incremented on each link Bit Clock period and rolls over from FFFF FFFFh to 0000 0000h. This counter will roll over to 0 with a period of approximately 179 seconds. This counter is enabled while the Bit Clock bit is set to 1. Software uses this counter to synchronize between multiple controllers. Will be reset on controller reset. 686 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.15 SSYNC—Stream Synchronization Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 34h Default Value: 00000000h Bit 31:8 Reserved Stream Synchronization (SSYNC) — R/W. When set to 1, these bits block data from being sent on or received from the link. Each bit controls the associated stream descriptor (i.e. bit 0 corresponds to the first stream descriptor, etc.) To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits for the associated stream descriptors are then set to 1 to start the DMA engines. When all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at the same time, and transmission or reception of bits to or from the link will begin together at the start of the next full link frame. 7:0 To synchronously stop the streams, fist these bits are set, and then the individual RUN bits in the stream descriptor are cleared by software. If synchronization is not desired, these bits may be left as 0, and the stream will simply begin running normally when the stream’s RUN bit is set. The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Attribute: Size: Description R/W 32 bits 18.2.16 CORBLBASE—CORB Lower Base Address Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 40h Default Value: 00000000h Bit Attribute: Size: Description R/W, RO 32 bits 31:7 CORB Lower Base Address — R/W. Lower address of the Command Output Ring Buffer, allowing the CORB base address to be assigned on any 128-B boundary. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the CORB to be allocated with 128B granularity to allow for cache line fetch optimizations. 6:0 Datasheet 687 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.17 CORBUBASE—CORB Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 44h Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits CORB Upper Base Address — R/W. Upper 32 bits of the address of the Command Output Ring buffer. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. 18.2.18 CORBWP—CORB Write Pointer Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 48h Default Value: 0000h Bit 15:8 Reserved. CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this field in dword granularity. The DMA engine fetches commands from the CORB until the Read pointer matches the Write pointer. Supports 256 CORB entries (256x4B = 1 KB). This register field may be written when the DMA engine is running. Attribute: Size: Description R/W 16 bits 7:0 18.2.19 CORBRP—CORB Read Pointer Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 4Ah Default Value: 0000h Bit Attribute: Size: Description R/W, RO 16 bits 15 CORB Read Pointer Reset — R/W. Software writes a 1 to this bit to reset the CORB Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware buffer within the Intel® High Definition Audio controller. The hardware will physically update this bit to 1 when the CORB Pointer reset is complete. Software must read a 1 to verify that the reset completed correctly. Software must clear this bit back to 0 and read back the 0 to verify that the clear completed correctly. The CORB DMA engine must be stopped prior to resetting the Read Pointer or else DMA transfer may be corrupted. Reserved. CORB Read Pointer (CORBRP)— RO. Software reads this field to determine how many commands it can write to the CORB without over-running. The value read indicates the CORB Read Pointer offset in Dword granularity. The offset entry read from this field has been successfully fetched by the DMA controller and may be over-written by software. Supports 256 CORB entries (256 x 4B=1KB). This field may be read while the DMA engine is running. 14:8 7:0 688 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.20 CORBCTL—CORB Control Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 4Ch Default Value: 00h Bit 7:2 Reserved. Enable CORB DMA Engine — R/W. 0 = DMA stop 1 1 = DMA run After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from this bit to verify that the DMA engine is truly stopped. CORB Memory Error Interrupt Enable — R/W. 0 If this bit is set the controller will generate an interrupt if the CMEI status bit (HDBAR + 4Dh: bit 0) is set. Attribute: Size: Description R/W 8 bits 18.2.21 CORBST—CORB Status Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 4Dh Default Value: 00h Bit 7:1 Reserved. CORB Memory Error Indication (CMEI) — R/WC. 1 = Controller detected an error in the path way between the controller and memory. This may be an ECC bit error or any other type of detectable data error which renders the command data fetched invalid. Software can clear this bit by writing a 1 to it. However, this type of error leaves the audio subsystem in an un-viable state and typically required a controller reset by writing a 0 to the Controller Reset # bit (HDBAR + 08h: bit 0). Attribute: Size: Description R/WC 8 bits 0 18.2.22 CORBSIZE—CORB Size Register Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 4Eh Default Value: 42h Bit 7:4 3:2 1:0 Attribute: Size: Description RO 8 bits CORB Size Capability — RO. Hardwired to 0100b indicating that the ICH10 only supports a CORB size of 256 CORB entries (1024B) Reserved. CORB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B) Datasheet 689 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.23 RIRBLBASE—RIRB Lower Base Address Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 50h Default Value: 00000000h Bit Attribute: Size: Description R/W, RO 32 bits 31:7 CORB Lower Base Address — R/W. Lower address of the Response Input Ring Buffer, allowing the RIRB base address to be assigned on any 128-B boundary. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. RIRB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the RIRB to be allocated with 128-B granularity to allow for cache line fetch optimizations. 6:0 18.2.24 RIRBUBASE—RIRB Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 54h Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits RIRB Upper Base Address — R/W. Upper 32 bits of the address of the Response Input Ring Buffer. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. 18.2.25 RIRBWP—RIRB Write Pointer Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 58h Default Value: 0000h Bit Attribute: Size: Description R/W, RO 16 bits 15 RIRB Write Pointer Reset — R/W. Software writes a 1 to this bit to reset the RIRB Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write Pointer or else DMA transfer may be corrupted. This bit is always read as 0. Reserved. RIRB Write Pointer (RIRBWP) — RO. Indicates the last valid RIRB entry written by the DMA controller. Software reads this field to determine how many responses it can read from the RIRB. The value read indicates the RIRB Write Pointer offset in 2 dword RIRB entry units (since each RIRB entry is 2 dwords long). Supports up to 256 RIRB entries (256 x 8 B = 2 KB). This register field may be written when the DMA engine is running. 14:8 7:0 690 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.26 RINTCNT—Response Interrupt Count Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 5Ah Default Value: 0000h Bit 15:8 Reserved. N Response Interrupt Count — R/W. 0000 0001b = 1 response sent to RIRB ........... 1111 1111b = 255 responses sent to RIRB 0000 0000b = 256 responses sent to RIRB 7:0 The DMA engine should be stopped when changing this field or else an interrupt may be lost. Note that each response occupies 2 dwords in the RIRB. This is compared to the total number of responses that have been returned, as opposed to the number of frames in which there were responses. If more than one codecs responds in one frame, then the count is increased by the number of responses received in the frame. Attribute: Size: Description R/W 16 bits 18.2.27 RIRBCTL—RIRB Control Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 5Ch Default Value: 00h Bit 7:3 2 Reserved. Response Overrun Interrupt Control — R/W. If this bit is set, the hardware will generate an interrupt when the Response Overrun Interrupt Status bit (HDBAR + 5Dh: bit 2) is set. Enable RIRB DMA Engine — R/W. 1 0 = DMA stop 1 = DMA run After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from this bit to verify that the DMA engine is truly stopped. Response Interrupt Control — R/W. 0 0 = Disable Interrupt 1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR when an empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). The N counter is reset when the interrupt is generated. Attribute: Size: Description R/W 8 bits Datasheet 691 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.28 RIRBSTS—RIRB Status Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 5Dh Default Value: 00h Bit 7:3 Reserved. Response Overrun Interrupt Status — R/WC. 1 = Software sets this bit to 1 when the RIRB DMA engine is not able to write the incoming responses to memory before additional incoming responses overrun the internal FIFO. When the overrun occurs, the hardware will drop the responses which overrun the buffer. An interrupt may be generated if the Response Overrun Interrupt Control bit is set. Note that this status bit is set even if an interrupt is not enabled for this event. Software clears this bit by writing a 1 to it. 1 Reserved. Response Interrupt — R/WC. 1 = Hardware sets this bit to 1 when an interrupt has been generated after N number of Responses are sent to the RIRB buffer OR when an empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). Note that this status bit is set even if an interrupt is not enabled for this event. Software clears this bit by writing a 1 to it. Attribute: Size: Description R/WC 8 bits 2 0 18.2.29 RIRBSIZE—RIRB Size Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 5Eh Default Value: 42h Bit 7:4 3:2 1:0 Attribute: Size: Description RO 8 bits RIRB Size Capability — RO. Hardwired to 0100b indicating that the ICH10 only supports a RIRB size of 256 RIRB entries (2048B) Reserved. RIRB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (2048B) 18.2.30 IC—Immediate Command Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 60h Default Value: 00000000h Bit Attribute: Size: Description R/W 32 bits 31:0 Immediate Command Write — R/W. The command to be sent to the codec via the Immediate Command mechanism is written to this register. The command stored in this register is sent out over the link during the next available frame after a 1 is written to the ICB bit (HDBAR + 68h: bit 0) 692 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.31 IR—Immediate Response Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 64h Default Value: 00000000h Bit Attribute: Size: Description RO 32 bits 31:0 Immediate Response Read (IRR) — RO. This register contains the response received from a codec resulting from a command sent via the Immediate Command mechanism. If multiple codecs responded in the same time, there is no assurance as to which response will be latched. Therefore, broadcast-type commands must not be issued via the Immediate Command mechanism. 18.2.32 IRS—Immediate Command Status Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 68h Default Value: 0000h Bit 15:2 Reserved. Immediate Result Valid (IRV) — R/WC. 1 = Set to 1 by hardware when a new response is latched into the Immediate Response register (HDBAR + 64). This is a status flag indicating that software may read the response from the Immediate Response register. Software must clear this bit by writing a 1 to it before issuing a new command so that the software may determine when a new response has arrived. Immediate Command Busy (ICB) — R/W. When this bit is read as 0, it indicates that a new command may be issued using the Immediate Command mechanism. When this bit transitions from a 0 to a 1 (via software writing a 1), the controller issues the command currently stored in the Immediate Command register to the codec over the link. When the corresponding response is latched into the Immediate Response register, the controller hardware sets the IRV flag and clears the ICB bit back to 0. NOTE: An Immediate Command must not be issued while the CORB/RIRB mechanism is operating, otherwise the responses conflict. This must be enforced by software. Attribute: Size: Description R/W, R/WC 16 bits 1 0 Datasheet 693 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.33 DPLBASE—DMA Position Lower Base Address Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 70h Default Value: 00000000h Bit Attribute: Size: Description R/W, RO 32 bits 31:7 DMA Position Lower Base Address — R/W. Lower 32 bits of the DMA Position Buffer Base Address. This register field must not be written when any DMA engine is running or the DMA transfer may be corrupted. This same address is used by the Flush Control and must be programmed with a valid value before the Flush Control bit (HDBAR+08h:bit 1) is set. DMA Position Lower Base Unimplemented bits — RO. Hardwired to 0 to force the 128byte buffer alignment for cache line write optimizations. DMA Position Buffer Enable — R/W. 1 = Controller will write the DMA positions of each of the DMA engines to the buffer in the main memory periodically (typically once per frame). Software can use this value to know what data in memory is valid data. 6:1 0 18.2.34 DPUBASE—DMA Position Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 74h Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits DMA Position Upper Base Address — R/W. Upper 32 bits of the DMA Position Buffer Base Address. This register field must not be written when any DMA engine is running or the DMA transfer may be corrupted. 694 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.35 SDCTL—Stream Descriptor Control Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 80h Input Stream[1]: HDBAR + A0h Input Stream[2]: HDBAR + C0h Input Stream[3]: HDBAR + E0h Output Stream[0]: HDBAR + 100h Output Stream[1]: HDBAR + 120h Output Stream[2]: HDBAR + 140h Output Stream[3]: HDBAR + 160h Default Value: 040000h Bit Description Stream Number — R/W. This value reflect the Tag associated with the data being transferred on the link. When data controlled by this descriptor is sent out over the link, it will have its stream number encoded on the SYNC signal. When an input stream is detected on any of the SDI signals that match this value, the data samples are loaded into FIFO associated with this descriptor. 23:20 Note that while a single SDI input may contain data from more than one stream number, two different SDI inputs may not be configured with the same stream number. 0000 = Reserved 0001 = Stream 1 ........ 1110 = Stream 14 1111 = Stream 15 19 18 17:16 15:5 4 Bidirectional Direction Control — RO. This bit is only meaningful for bidirectional streams; therefore, this bit is hardwired to 0. Traffic Priority — RO. Hardwired to 1 indicating that all streams will use VC1 if it is enabled through the PCI Express* registers. Stripe Control — RO. This bit is only meaningful for input streams; therefore, this bit is hardwired to 0. Reserved Descriptor Error Interrupt Enable — R/W. 0 = Disable 1 = An interrupt is generated when the Descriptor Error Status bit is set. FIFO Error Interrupt Enable — R/W. This bit controls whether the occurrence of a FIFO error (overrun for input or underrun for output) will cause an interrupt or not. If this bit is not set, bit 3in the Status register will be set, but the interrupt will not occur. Either way, the samples will be dropped. Interrupt on Completion Enable — R/W. This bit controls whether or not an interrupt occurs when a buffer completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the Status register will be set, but the interrupt will not occur. Attribute: R/W, RO Size: 24 bits 3 2 Datasheet 695 Intel® High Definition Audio Controller Registers (D27:F0) Bit Stream Run (RUN) — R/W. Description 0 = DMA engine associated with this input stream will be disabled. The hardware will report a 0 in this bit when the DMA engine is actually stopped. Software must read a 0 from this bit before modifying related control registers or restarting the DMA engine. 1 = DMA engine associated with this input stream will be enabled to transfer data from the FIFO to the main memory. The SSYNC bit must also be cleared in order for the DMA engine to run. For output streams, the cadence generator is reset whenever the RUN bit is set. Stream Reset (SRST) — R/W. 0 = Writing a 0 causes the corresponding stream to exit reset. When the stream hardware is ready to begin operation, it will report a 0 in this bit. Software must read a 0 from this bit before accessing any of the stream registers. 1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers (except the SRST bit itself) and FIFO’s for the corresponding stream are reset. After the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. Software must read a 1 from this bit to verify that the stream is in reset. The RUN bit must be cleared before SRST is asserted. 1 0 696 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.36 SDSTS—Stream Descriptor Status Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 83h Input Stream[1]: HDBAR + A3h Input Stream[2]: HDBAR + C3h Input Stream[3]: HDBAR + E3h Output Stream[0]: HDBAR + 103h Output Stream[1]: HDBAR + 123h Output Stream[2]: HDBAR + 143h Output Stream[3]: HDBAR + 163h Default Value: 00h Bit 7:6 Reserved. FIFO Ready (FIFORDY) — RO. For output streams, the controller hardware will set this bit to 1 while the output DMA FIFO contains enough data to maintain the stream on the link. This bit defaults to 0 on reset because the FIFO is cleared on a reset. For input streams, the controller hardware will set this bit to 1 when a valid descriptor is loaded and the engine is ready for the RUN bit to be set. Descriptor Error — R/WC. 1 = A serious error occurred during the fetch of a descriptor. This could be a result of a Master Abort, a parity or ECC error on the bus, or any other error which renders the current Buffer Descriptor or Buffer Descriptor list useless. This error is treated as a fatal stream error, as the stream cannot continue running. The RUN bit will be cleared and the stream will stopped. Software may attempt to restart the stream engine after addressing the cause of the error and writing a 1 to this bit to clear it. FIFO Error — R/WC. 1 = FIFO error occurred. This bit is set even if an interrupt is not enabled. The bit is cleared by writing a 1 to it. 3 For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set. When this happens, the FIFO pointers do not increment and the incoming data is not written into the FIFO, thereby being lost. For an output stream, this indicates a FIFO underrun when there are still buffers to send. The hardware should not transmit anything on the link for the associated stream if there is not valid data to send. Buffer Completion Interrupt Status — R/WC. This bit is set to 1 by the hardware after the last sample of a buffer has been processed, AND if the Interrupt on Completion bit is set in the command byte of the buffer descriptor. It remains active until software clears it by writing a 1 to it. Reserved. Description Attribute:R/WC, RO Size: 8 bits 5 4 2 1:0 Datasheet 697 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.37 SDLPIB—Stream Descriptor Link Position in Buffer Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 84h Input Stream[1]: HDBAR + A4h Input Stream[2]: HDBAR + C4h Input Stream[3]: HDBAR + E4h Output Stream[0]: HDBAR + 104h Output Stream[1]: HDBAR + 124h Output Stream[2]: HDBAR + 144h Output Stream[3]: HDBAR + 164h Default Value: Bit 31:0 Attribute:RO 00000000h Description Size: 32 bits Link Position in Buffer — RO. Indicates the number of bytes that have been received off the link. This register will count from 0 to the value in the Cyclic Buffer Length register and then wrap to 0. 18.2.38 SDCBL—Stream Descriptor Cyclic Buffer Length Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 88h Input Stream[1]: HDBAR + A8h Input Stream[2]: HDBAR + C8h Input Stream[3]: HDBAR + E8h Output Stream[0]: HDBAR + 108h Output Stream[1]: HDBAR + 128h Output Stream[2]: HDBAR + 148h Output Stream[3]: HDBAR + 168h Default Value: Bit Attribute:R/W 00000000h Description Size: 32 bits Cyclic Buffer Length — R/W. Indicates the number of bytes in the complete cyclic buffer. This register represents an integer number of samples. Link Position in Buffer will be reset when it reaches this value. 31:0 Software may only write to this register after Global Reset, Controller Reset, or Stream Reset has occurred. This value should be only modified when the RUN bit is 0. Once the RUN bit has been set to enable the engine, software must not write to this register until after the next reset is asserted, or transfer may be corrupted. 698 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.39 SDLVI—Stream Descriptor Last Valid Index Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 8Ch Input Stream[1]: HDBAR + ACh Input Stream[2]: HDBAR + CCh Input Stream[3]: HDBAR + ECh Output Stream[0]: HDBAR + 10Ch Output Stream[1]: HDBAR + 12Ch Output Stream[2]: HDBAR + 14Ch Output Stream[3]: HDBAR + 16Ch Default Value: Bit 15:8 Reserved. Last Valid Index — R/W. The value written to this register indicates the index for the last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it will wrap back to the first descriptor in the list and continue processing. This field must be at least 1, i.e. there must be at least 2 valid entries in the buffer descriptor list before DMA operations can begin. This value should only modified when the RUN bit is 0. Attribute: R/W 0000h Description Size: 16 bits 7:0 18.2.40 SDFIFOW—Stream Descriptor FIFO Watermark Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 8Eh Input Stream[1]: HDBAR + AEh Input Stream[2]: HDBAR + CEh Input Stream[3]: HDBAR + EEh Output Stream[0]: HDBAR + 10Eh Output Stream[1]: HDBAR + 12Eh Output Stream[2]: HDBAR + 14Eh Output Stream[3]: HDBAR + 16Eh Default Value: Bit 15:3 Reserved. FIFO Watermark (FIFOW) — R/W. Indicates the minimum number of bytes accumulated/free in the FIFO before the controller will start a fetch/eviction of data. 010 = 8B 011 = 16B 100 = 32B (Default) 2:0 101 = 64B Others = Unsupported NOTE: When the bit field is programmed to an unsupported size, the hardware sets itself to the default value. Software must read the bit field to test if the value is supported after setting the bit field. Attribute: R/W 0004h Description Size: 16 bits Datasheet 699 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.41 SDFIFOS—Stream Descriptor FIFO Size Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 90hAttribute: Input Stream[1]: HDBAR + B0hOutput: Input Stream[2]: HDBAR + D0h Input Stream[3]: HDBAR + F0h Output Stream[0]: HDBAR + 110h Output Stream[1]: HDBAR + 130h Output Stream[2]: HDBAR + 150h Output Stream[3]: HDBAR + 170h Default Value: Input Stream: 0077h Output Stream: See Description. Description Reserved. FIFO Size — RO (Input stream), R/W (Output stream). Indicates the maximum number of bytes that could be fetched by the controller at one time. This is the maximum number of bytes that may have been DMA’d into memory but not yet transmitted on the link, and is also the maximum possible value that the PICB count will increase by at one time. The value in this field is different for input and output streams. It is also dependent on the Bits per Samples setting for the corresponding stream. Following are the values read/written from/to this register for input and output streams, and for non-padded and padded bit formats: Output Stream R/W value: Value 0Fh = 16B 1Fh = 32B 3Fh = 64B 7Fh = 128B BFh = 192B 9:0 FFh = 256B 17Fh = 384B 1FFh = 512B Input: RO R/W Size: 16 bits Bit 15:10 Output Streams 8, 16, 20, 24, or 32 bit Output Streams 8, 16, 20, 24, or 32 bit Output Streams 8, 16, 20, 24, or 32 bit Output Streams 8, 16, 20, 24, or 32 bit Output Streams 8, 16, or 32 bit Output Streams (Default) 20 or 24 bit Output Streams (Default) 8, 16, or 32 bit Output Streams 20 or 24 bit Output Streams NOTES: 1. All other values not listed are not supported. 2. When the output stream is programmed to an unsupported size, the hardware sets itself to the default value (BFh). 3. Software must read the bit field to test if the value is supported after setting the bit field. Input Stream RO value: Value 77h = 120B 9Fh = 160B Input Streams 8, 16, 32 bit Input Streams 20, 24 bit Input Streams NOTE: The default value is different for input and output streams, and reflects the default state of the BITS fields (in Stream Descriptor Format registers) for the corresponding stream. 700 Datasheet Intel® High Definition Audio Controller Registers (D27:F0) 18.2.42 SDFMT—Stream Descriptor Format Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 92h Input Stream[1]: HDBAR + B2h Input Stream[2]: HDBAR + D2h Input Stream[3]: HDBAR + F2h Output Stream[0]: HDBAR + 112h Output Stream[1]: HDBAR + 132h Output Stream[2]: HDBAR + 152h Output Stream[3]: HDBAR + 172h Default Value: Bit 15 14 Reserved. Sample Base Rate — R/W 0 = 48 kHz 1 = 44.1 kHz Sample Base Rate Multiple — R/W 13:11 000 = 48 kHz, 44.1 kHz or less 001 = x2 (96 kHz, 88.2 kHz, 32 kHz) 010 = x3 (144 kHz) 011 = x4 (192 kHz, 176.4 kHz) Others = Reserved. Sample Base Rate Devisor — R/W. 000 001 010 011 100 101 110 111 = = = = = = = = Divide Divide Divide Divide Divide Divide Divide Divide by by by by by by by by 1(48 kHz, 44.1 kHz) 2 (24 kHz, 22.05 kHz) 3 (16 kHz, 32 kHz) 4 (11.025 kHz) 5 (9.6 kHz) 6 (8 kHz) 7 8 (6 kHz) Attribute:R/W 0000h Description Size: 16 bits 10:8 7 Reserved. Bits per Sample (BITS) — R/W. 000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit boundaries 001 = 16 bits. The data will be packed in memory in 16-bit containers on 16-bit boundaries 6:4 010 = 20 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries 011 = 24 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries 100 = 32 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries Others = Reserved. Number of Channels (CHAN) — R/W. Indicates number of channels in each frame of the stream. 3:0 0000 =1 0001 =2 ........ 1111 =16 Datasheet 701 Intel® High Definition Audio Controller Registers (D27:F0) 18.2.43 SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 98h Input Stream[1]: HDBAR + B8h Input Stream[2]: HDBAR + D8h Input Stream[3]: HDBAR + F8h Output Stream[0]: HDBAR + 118h Output Stream[1]: HDBAR + 138h Output Stream[2]: HDBAR + 158h Output Stream[3]: HDBAR + 178h Default Value: Bit 31:7 6:0 Attribute: R/W,RO 00000000h Description Size: 32 bits Buffer Descriptor List Pointer Lower Base Address — R/W. Lower address of the Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA transfer may be corrupted. Hardwired to 0 forcing alignment on 128-B boundaries. 18.2.44 SDBDPU—Stream Descriptor Buffer Descriptor List Pointer Upper Base Address Register (Intel® High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 9Ch Input Stream[1]: HDBAR + BCh Input Stream[2]: HDBAR + DCh Input Stream[3]: HDBAR + FCh Output Stream[0]: HDBAR + 11Ch Output Stream[1]: HDBAR + 13Ch Output Stream[2]: HDBAR + 15Ch Output Stream[3]: HDBAR + 17Ch Default Value: Bit 31:0 Attribute: R/W 00000000h Description Size: 32 bits Buffer Descriptor List Pointer Upper Base Address — R/W. Upper 32-bit address of the Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA transfer may be corrupted. §§ 702 Datasheet SMBus Controller Registers (D31:F3) 19 19.1 SMBus Controller Registers (D31:F3) PCI Configuration Registers (SMBus—D31:F3) Table 19-1. SMBus Controller PCI Register Address Map (SMBus—D31:F3) Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 10h 14h 20h–23h 2Ch–2Dh 2Eh–2Fh 3Ch 3Dh 40h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC SMBMBAR0 SMBMBAR1 SMB_BASE SVID SID INT_LN INT_PN HOSTC Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Memory Base Address Register 0 (Bit 31:0) Memory Based Address Register 1 (Bit 63:32) SMBus Base Address Subsystem Vendor Identification Subsystem Identification Interrupt Line Interrupt Pin Host Configuration Default 8086 See register description 0000h 0280h See register description 00h 05h 0Ch 00000004h 00000000h 00000001h 0000h 0000h 00h See register description 00h Type RO RO R/W, RO RO RO RO RO RO R/W R/W R/W, RO RO R/WO R/W RO R/W NOTE: Registers that are not shown should be treated as Reserved (See Section 9.2 for details). 19.1.1 VID—Vendor Identification Register (SMBus—D31:F3) Address: Default Value: Bit 15:0 00h–01h 8086h Attribute: Size: Description RO 16 bits Vendor ID — RO. This is a 16-bit value assigned to Intel Datasheet 703 SMBus Controller Registers (D31:F3) 19.1.2 DID—Device Identification Register (SMBus—D31:F3) Address: Default Value: Bit 15:0 02h–03h See bit description Attribute: Size: Description RO 16 bits Device ID — RO. This is a 16-bit value assigned to the Intel® ICH10 SMBus controller. Refer to the Intel® I/O Controller Hub (ICH10) Family Specification Update for the value of the Device ID Register. 19.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) Address: Default Value: Bit 15:11 10 9 8 7 6 5 4 3 2 1 Reserved Interrupt Disable — R/W. 0 = Enable 1 = Disables SMBus to assert its PIRQB# signal. Fast Back to Back Enable (FBE) — RO. Hardwired to 0. SERR# Enable (SERR_EN) — R/W. 0 = Enables SERR# generation. 1 = Disables SERR# generation. Wait Cycle Control (WCC) — RO. Hardwired to 0. Parity Error Response (PER) — R/W. 0 = Disable 1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected. VGA Palette Snoop (VPS) — RO. Hardwired to 0. Postable Memory Write Enable (PMWE) — RO. Hardwired to 0. Special Cycle Enable (SCE) — RO. Hardwired to 0. Bus Master Enable (BME) — RO. Hardwired to 0. Memory Space Enable (MSE) — R/W. 0 = Disables memory mapped config space. 1 = Enables memory mapped config space. I/O Space Enable (IOSE) — R/W. 0 0 = Disable 1 = Enables access to the SMBus I/O space registers as defined by the Base Address Register. 04h–05h 0000h Attributes: Size: Description RO, R/W 16 bits 704 Datasheet SMBus Controller Registers (D31:F3) 19.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) Address: Default Value: 06h–07h 0280h Attributes: Size: RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit 15 0 = No parity error detected. 1 = Parity error detected. Signaled System Error (SSE) — R/WC. 14 13 12 11 10:9 8 7 6 5 4 3 2:0 0 = No system error detected. 1 = System error detected. Received Master Abort (RMA) — RO. Hardwired to 0. Received Target Abort (RTA) — RO. Hardwired to 0. Signaled Target Abort (STA) — RO. Hardwired to 0. DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for DEVSEL# assertion for positive decode. 01 = Medium timing. Data Parity Error Detected (DPED) — RO. Hardwired to 0. Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. User Definable Features (UDF) — RO. Hardwired to 0. 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list structures in this function Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is independent from the state of the Interrupt Enable bit in the PCI Command register. Reserved Description Detected Parity Error (DPE) — R/WC. 19.1.5 RID—Revision Identification Register (SMBus—D31:F3) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID — RO. Refer to the Intel® I/O Controller Hub (ICH10) Family Specification Update for the value of the Revision ID Register. Datasheet 705 SMBus Controller Registers (D31:F3) 19.1.6 PI—Programming Interface Register (SMBus—D31:F3) Offset Address: 09h Default Value: 00h Bit 7:0 Reserved Attribute: Size: Description RO 8 bits 19.1.7 SCC—Sub Class Code Register (SMBus—D31:F3) Address Offset: 0Ah Default Value: 05h Bit 7:0 Sub Class Code (SCC) — RO. 05h = SMBus serial controller Attributes: Size: Description RO 8 bits 19.1.8 BCC—Base Class Code Register (SMBus—D31:F3) Address Offset: 0Bh Default Value: 0Ch Bit 7:0 Base Class Code (BCC) — RO. 0Ch = Serial controller. Attributes: Size: Description RO 8 bits 19.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0 (SMBus—D31:F3) Address Offset: 10-13h Default Value: 00000004h Bit 31:8 7:4 3 2:1 0 Attributes: Size: Description R/W, RO 32 bits Base Address — R/W. Provides the 32 byte system memory base address for the Intel ICH10 SMB logic. Reserved Prefetchable (PREF) — RO. Hardwired to 0. Indicates that SMBMBAR is not prefetchable. Address Range (ADDRNG) — RO. Indicates that this SMBMBAR can be located anywhere in 64 bit address space. Hardwired to 10b. Memory Space Indicator — RO. This read-only bit always is 0, indicating that the SMB logic is Memory mapped. 706 Datasheet SMBus Controller Registers (D31:F3) 19.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1 (SMBus—D31:F3) Address Offset: 14h-17h Default Value: 00000000h Bit 31:0 Attributes: Size: Description R/W 32 bits Base Address — R/W. Provides bits 63-32 system memory base address for the Intel ICH10 SMB logic. 19.1.11 SMB_BASE—SMBus Base Address Register (SMBus—D31:F3) Address Offset: 20–23h Default Value: 00000001h Bit 31:16 15:5 4:1 0 Reserved — RO Base Address — R/W. This field provides the 32-byte system I/O base address for the ICH10 SMB logic. Reserved — RO IO Space Indicator — RO. Hardwired to 1 indicating that the SMB logic is I/O mapped. Attribute: Size: Description R/W, RO 32-bits 19.1.12 SVID—Subsystem Vendor Identification Register (SMBus—D31:F2/F4) Address Offset: 2Ch–2Dh Default Value: 0000h Lockable: No Bit Attribute: Size: Power Well: Description RO 16 bits Core 15:0 Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE SVID register. NOTE: Software can write to this register only once per core well reset. Writes should be done as a single 16-bit cycle. Datasheet 707 SMBus Controller Registers (D31:F3) 19.1.13 SID—Subsystem Identification Register (SMBus—D31:F2/F4) Address Offset: 2Eh–2Fh Default Value: 0000h Lockable: No Bit Attribute: Size: Power Well: Description R/WO 16 bits Core 15:0 Subsystem ID (SID) — R/WO. The SID register, in combination with the SVID register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE SID register. NOTE: Software can write to this register only once per core well reset. Writes should be done as a single 16-bit cycle. 19.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3) Address Offset: 3Ch Default Value: 00h Bit 7:0 Attributes: Size: Description R/W 8 bits Interrupt Line (INT_LN) — R/W. This data is not used by the ICH10. It is to communicate to software the interrupt line that the interrupt pin is connected to PIRQB#. 19.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3) Address Offset: 3Dh Default Value: See description Bit 7:0 Attributes: Size: Description RO 8 bits Interrupt PIN (INT_PN) — RO. This reflects the value of D31IP.SMIP in chipset configuration space. 708 Datasheet SMBus Controller Registers (D31:F3) 19.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3) Address Offset: 40h Default Value: 00h Bit 7:4 3 Reserved SSRESET - Soft SMBus Reset— R/W. 0 = The HW will reset this bit to 0 when SMBus reset operation is completed. 1 = The SMBus state machine and logic in ICH10 is reset. I2C_EN — R/W. 2 0 = SMBus behavior. 1 = The ICH10 is enabled to communicate with I2C devices. This will change the formatting of some commands. SMB_SMI_EN — R/W. 1 0 = SMBus interrupts will not generate an SMI#. 1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to Section 5.20.4 (Interrupts / SMI#). This bit needs to be set for SMBALERT# to be enabled. SMBus Host Enable (HST_EN) — R/W. 0 0 = Disable the SMBus Host controller. 1 = Enable. The SMB Host controller interface is enabled to execute commands. The INTREN bit (offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host controller to interrupt or SMI#. Note that the SMB Host controller will not respond to any new requests until all interrupt requests have been cleared. Attribute: Size: Description R/W 8 bits Datasheet 709 SMBus Controller Registers (D31:F3) 19.2 SMBus I/O and Memory Mapped I/O Registers The following SMBus registers can be accessed through I/O BAR or Memory BAR registers in PCI configuration space. The offsets are the same for both I/O and Memory Mapped I/O registers. Table 19-2. SMBus I/O and Memory Mapped I/O Register Address Map SMB_BASE + Offset 00h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah–0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 14h 16h 17h Mnemonic HST_STS HST_CNT HST_CMD XMIT_SLVA HST_D0 HST_D1 HOST_BLOCK_DB PEC RCV_SLVA SLV_DATA AUX_STS AUX_CTL SMLINK_PIN_CTL SMBus_PIN_CTL SLV_STS SLV_CMD NOTIFY_DADDR NOTIFY_DLOW NOTIFY_DHIGH Register Name Host Status Host Control Host Command Transmit Slave Address Host Data 0 Host Data 1 Host Block Data Byte Packet Error Check Receive Slave Address Receive Slave Data Auxiliary Status Auxiliary Control SMLink Pin Control (TCO Compatible Mode) SMBus Pin Control Slave Status Slave Command Notify Device Address Notify Data Low Byte Notify Data High Byte Default 00h 00h 00h 00h 00h 00h 00h 00h 44h 0000h 00h 00h See register description See register description 00h 00h 00h 00h 00h Type R/WC, RO R/W, WO R/W R/W R/W R/W R/W R/W R/W RO R/WC, RO R/W R/W, RO R/W, RO R/WC R/W RO RO RO 710 Datasheet SMBus Controller Registers (D31:F3) 19.2.1 HST_STS—Host Status Register (SMBus—D31:F3) Register Offset: SMBASE + 00h Default Value: 00h Attribute: Size: R/WC, RO 8-bits All status bits are set by hardware and cleared by the software writing a one to the particular bit position. Writing a 0 to any bit position has no effect. Bit Byte Done Status (DS) — R/WC. 0 = Software can clear this by writing a 1 to it. 1 = Host controller received a byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write commands) when the 32-byte buffer is not being used. Note that this bit will be set, even on the last byte of the transfer. This bit is not set when transmission is due to the LAN interface heartbeat. This bit has no meaning for block transfers when the 32-byte buffer is enabled. 7 NOTE: When the last byte of a block message is received, the host controller will set this bit. However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt handler clears the DS bit, the message is considered complete, and the host controller will then set the INTR bit (and generate another interrupt). Thus, for a block message of n bytes, the ICH10 will generate n+1 interrupts. The interrupt handler needs to be implemented to handle these cases. When not using the 32 Byte Buffer, hardware will drive the SMBCLK signal low when the DS bit is set until SW clears the bit. This includes the last byte of a transfer. Software must clear the DS bit before it can clear the BUSY bit. INUSE_STS — R/W. This bit is used as semaphore among various independent software threads that may need to use the ICH10’s SMBus logic, and has no other effect on hardware. 6 0 = After a full PCI reset, a read to this bit returns a 0. 1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0, and will then own the usage of the host controller. SMBALERT_STS — R/WC. 5 0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by writing a 1 to it. 1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by software writing a 1 to the bit position or by RSMRST# going low. If the signal is programmed as a GPIO, then this bit will never be set. FAILED — R/WC. 4 0 = Software clears this bit by writing a 1 to it. 1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to the KILL bit being set to terminate the host transaction. BUS_ERR — R/WC. 3 0 = Software clears this bit by writing a 1 to it. 1 = The source of the interrupt of SMI# was a transaction collision. DEV_ERR — R/WC. 0 = Software clears this bit by writing a 1 to it. The ICH10 will then deassert the interrupt or SMI#. 1 = The source of the interrupt or SMI# was due to one of the following: • • • Invalid Command Field, Unclaimed Cycle (host initiated), Host Device Time-out Error. Description 2 Datasheet 711 SMBus Controller Registers (D31:F3) Bit Description INTR — R/WC. This bit can only be set by termination of a command. INTR is not dependent on the INTREN bit (offset SMBASE + 02h, bit 0) of the Host controller register (offset 02h). It is only dependent on the termination of the command. If the INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be generated. Software can poll the INTR bit in this non-interrupt case. 0 = Software clears this bit by writing a 1 to it. The ICH10 then deasserts the interrupt or SMI#. 1 = The source of the interrupt or SMI# was the successful completion of its last command. HOST_BUSY — R/WC. 0 = Cleared by the ICH10 when the current transaction is completed. 1 = Indicates that the ICH10 is running a command from the host interface. No SMB registers should be accessed while this bit is set, except the BLOCK DATA BYTE Register. The BLOCK DATA BYTE Register can be accessed when this bit is set only when the SMB_CMD bits in the Host Control Register are programmed for Block command or I2C Read command. This is necessary in order to check the DONE_STS bit. 1 0 19.2.2 HST_CNT—Host Control Register (SMBus—D31:F3) Register Offset: SMBASE + 02h Default Value: 00h Attribute: Size: R/W, WO 8-bits Note: A read to this register will clear the byte pointer of the 32-byte buffer. Bit Description PEC_EN. — R/W. 0 = SMBus host controller does not perform the transaction with the PEC phase appended. 1 = Causes the host controller to perform the SMBus transaction with the Packet Error Checking phase appended. For writes, the value of the PEC byte is transferred from the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. This bit must be written prior to the write in which the START bit is set. START — WO. 6 0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset 00h) can be used to identify when the Intel® ICH10 has finished the command. 1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers should be setup prior to writing a 1 to this bit position. LAST_BYTE — WO. This bit is used for Block Read commands. 1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the block. This causes the ICH10 to send a NACK (instead of an ACK) after receiving the last byte. 5 NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h, bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is set, the LAST_BYTE bit cannot be cleared. This prevents the ICH10 from running some of the SMBus commands (Block Read/Write, I2C Read, Block I2C Write). 7 712 Datasheet SMBus Controller Registers (D31:F3) Bit Description SMB_CMD — R/W. The bit encoding below indicates which command the ICH10 is to perform. If enabled, the ICH10 will generate an interrupt or SMI# when the command has completed If the value is for a non-supported or reserved command, the ICH10 will set the device error (DEV_ERR) status bit (offset SMBASE + 00h, bit 2) and generate an interrupt when the START bit is set. The ICH10 will perform no command, and will not operate until DEV_ERR is cleared. 000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = Byte: This command uses the transmit slave address and command registers. Bit 0 of the slave address register determines if this is a read or write command. 010 = Byte Data: This command uses the transmit slave address, command, and DATA0 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, the DATA0 register will contain the read data. 011 = Word Data: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, after the command completes, the DATA0 and DATA1 registers will contain the read data. 100 = Process Call: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. After the command completes, the DATA0 and DATA1 registers will contain the read data. 101 = Block: This command uses the transmit slave address, command, DATA0 registers, and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block reads, the count is received and stored in the DATA0 register. Bit 0 of the slave address register selects if this is a read or write command. For writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. 110 = I2C Read: This command uses the transmit slave address, command, DATA0, DATA1 registers, and the Block Data Byte register. The read data is stored in the Block Data Byte register. The ICH10 continues reading data until the NAK is received. 111 = Block Process: This command uses the transmit slave address, command, DATA0 and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block read, the count is received and stored in the DATA0 register. Bit 0 of the slave address register always indicate a write command. For writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. NOTE: E32B bit in the Auxiliary Control register must be set for this command to work. KILL — R/W. 0 = Normal SMBus host controller functionality. 1 = Kills the current host transaction taking place, sets the FAILED status bit, and asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to allow the SMBus host controller to function normally. INTREN — R/W. 0 = Disable. 1 = Enable the generation of an interrupt or SMI# upon the completion of the command. 4:2 1 0 Datasheet 713 SMBus Controller Registers (D31:F3) 19.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) Register Offset: SMBASE + 03h Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol during the execution of any command. 19.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBus—D31:F3) Register Offset: SMBASE + 04h Default Value: 00h Attribute: Size: R/W 8 bits This register is transmitted by the host controller in the slave address field of the SMBus protocol. Bit 7:1 0 Description Address — R/W. This field provides a 7-bit address of the targeted slave. RW — R/W. Direction of the host transfer. 0 = Write 1 = Read 19.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) Register Offset: SMBASE + 05h Default Value: 00h Bit Attribute: Size: Description R/W 8 bits 7:0 Data0/Count — R/W. This field contains the 8-bit data sent in the DATA0 field of the SMBus protocol. For block write commands, this register reflects the number of bytes to transfer. This register should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host controller does not check or log invalid block counts. 19.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) Register Offset: SMBASE + 06h Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus protocol during the execution of any command. 714 Datasheet SMBus Controller Registers (D31:F3) 19.2.7 Host_BLOCK_DB—Host Block Data Byte Register (SMBus—D31:F3) Register Offset: SMBASE + 07h Default Value: 00h Bit Attribute: Size: Description R/W 8 bits Block Data (BDTA) — R/W. This is either a register, or a pointer into a 32-byte block array, depending upon whether the E32B bit is set in the Auxiliary Control register. When the E32B bit (offset SMBASE + 0Dh, bit 1) is cleared, this is a register containing a byte of data to be sent on a block write or read from on a block read, just as it behaved on the ICH3. When the E32B bit is set, reads and writes to this register are used to access the 32byte block data storage array. An internal index pointer is used to address the array, which is reset to 0 by reading the HCTL register (offset 02h). The index pointer then increments automatically upon each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0. When the E2B bit is set, for writes, software will write up to 32-bytes to this register as part of the setup for the command. After the Host controller has sent the Address, Command, and Byte Count fields, it will send the bytes in the SRAM pointed to by this register. When the E2B bit is cleared for writes, software will place a single byte in this register. After the host controller has sent the address, command, and byte count fields, it will send the byte in this register. If there is more data to send, software will write the next series of bytes to the SRAM pointed to by this register and clear the DONE_STS bit. The controller will then send the next byte. During the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. When the E2B bit is set for reads, after receiving the byte count into the Data0 register, the first series of data bytes go into the SRAM pointed to by this register. If the byte count has been exhausted or the 32-byte SRAM has been filled, the controller will generate an SMI# or interrupt (depending on configuration) and set the DONE_STS bit. Software will then read the data. During the time between when the last byte is read from the SRAM to when the DONE_STS bit is cleared, the controller will insert waitstates on the interface. 7:0 19.2.8 PEC—Packet Error Check (PEC) Register (SMBus—D31:F3) Register Offset: SMBASE + 08h Default Value: 00h Bit Attribute: Size: Description R/W 8 bits 7:0 PEC_DATA — R/W. This 8-bit register is written with the 8-bit CRC value that is used as the SMBus PEC data prior to a write transaction. For read transactions, the PEC data is loaded from the SMBus into this register and is then read by software. Software must ensure that the INUSE_STS bit is properly maintained to avoid having this field overwritten by a write transaction following a read transaction. Datasheet 715 SMBus Controller Registers (D31:F3) 19.2.9 RCV_SLVA—Receive Slave Address Register (SMBus—D31:F3) Register Offset: SMBASE + 09h Default Value: 44h Lockable: No Bit 7 Reserved SLAVE_ADDR — R/W. This field is the slave address that the Intel® ICH10 decodes for read and write cycles. the default is not 0, so the SMBus Slave Interface can respond even before the processor comes up (or if the processor is dead). This register is cleared by RSMRST#, but not by PLTRST#. Attribute: Size: Power Well: Description R/W 8 bits Resume 6:0 19.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) Register Offset: SMBASE + 0Ah–0Bh Default Value: 0000h Lockable: No Attribute: Size: Power Well: RO 16 bits Resume This register contains the 16-bit data value written by the external SMBus master. The processor can then read the value from this register. This register is reset by RSMRST#, but not PLTRST# . Bit 15:8 7:0 Description Data Message Byte 1 (DATA_MSG1) — RO. See Section 5.20.7 for a discussion of this field. Data Message Byte 0 (DATA_MSG0) — RO. See Section 5.20.7 for a discussion of this field. 19.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3) Register Offset: SMBASE + 0Ch Default Value: 00h Lockable: No Attribute: Size: Power Well: Description Reserved SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible mode vs. Advanced TCO mode. 1 0 = Intel® ICH10 is in the compatible TCO mode. 1 = ICH10 is in the advanced TCO mode. CRC Error (CRCE) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set if a received message contained a CRC error. When this bit is set, the DERR bit of the host status register will also be set. This bit will be set by the controller if a software abort occurs in the middle of the CRC portion of the cycle or an abort happens after the ICH10 has received the final data bit transmitted by an external slave. R/WC, RO 8 bits Resume . Bit 7:2 0 716 Datasheet SMBus Controller Registers (D31:F3) 19.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) Register Offset: SMBASE + 0Dh Default Value: 00h Lockable: No Attribute: Size: Power Well: Description Reserved Enable 32-Byte Buffer (E32B) — R/W. 1 0 = Disable. 1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as opposed to a single register. This enables the block commands to transfer or receive up to 32-bytes before the ICH10 generates an interrupt. Automatically Append CRC (AAC) — R/W. 0 0 = ICH10 will Not automatically append the CRC. 1 = The ICH10 will automatically append the CRC. This bit must not be changed during SMBus transactions or undetermined behavior will result. It should be programmed only once during the lifetime of the function. R/W 8 bits Resume . Bit 7:2 19.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register (SMBus—D31:F3) Register Offset: SMBASE + 0Eh Default Value: See below Attribute: Size: R/W, RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. This register is only applicable in the TCO compatible mode. Bit 7:3 Reserved SMLINK_CLK_CTL — R/W. 2 0 = ICH10 will drive the SMLINK0 pin low, independent of what the other SMLINK logic would otherwise indicate for the SMLINK0 pin. 1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state of the pin. (Default) SMLINK1_CUR_STS — RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMLINK1 pin. This allows software to read the current state of the pin. 0 = Low 1 = High SMLINK0_CUR_STS — RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMLINK0 pin. This allows software to read the current state of the pin. 0 = Low 1 = High Description 1 0 Datasheet 717 SMBus Controller Registers (D31:F3) 19.2.14 SMBus_PIN_CTL—SMBus Pin Control Register (SMBus—D31:F3) Register Offset: SMBASE + 0Fh Default Value: See below Attribute: Size: R/W, RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit 7:3 Reserved SMBCLK_CTL — R/W. 1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of the pin. 0 = ICH10 drives the SMBCLK pin low, independent of what the other SMB logic would otherwise indicate for the SMBCLK pin. (Default) SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMBDATA pin. This allows software to read the current state of the pin. 0 = Low 1 = High SMBCLK_CUR_STS — RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMBCLK pin. This allows software to read the current state of the pin. 0 = Low 1 = High Description 2 1 0 19.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3) Register Offset: SMBASE + 10h Default Value: 00h Attribute: Size: R/WC 8 bits Note: This register is in the resume well and is reset by RSMRST#. All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. Bit 7:1 Reserved HOST_NOTIFY_STS — R/WC. The ICH10 sets this bit to a 1 when it has completely received a successful Host Notify Command on the SMlink (Consumer Only) or SMBus pins (Corporate Only). Software reads this bit to determine that the source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this bit after reading any information needed from the Notify address and data registers by writing a 1 to this bit. Note that the ICH10 will allow the Notify Address and Data registers to be over-written once this bit has been cleared. When this bit is 1, the ICH10 will NACK the first byte (host address) of any new “Host Notify” commands on the SMlink (Consumer Only) or SMBus pins (Corporate Only). Writing a 0 to this bit has no effect. Description 0 718 Datasheet SMBus Controller Registers (D31:F3) 19.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3) Register Offset: SMBASE + 11h Default Value: 00h Attribute: Size: R/W 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit 7:2 Reserved SMBALERT_DIS — R/W. 0 = Allows the generation of the interrupt or SMI#. 1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT# source. This bit is logically inverted and ANDed with the SMBALERT_STS bit (offset SMBASE + 00h, bit 5). The resulting signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the wake logic. HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a Host Notify command as a wake event. When enabled this event is “OR’d" in with the other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register. 0 = Disable 1 = Enable HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation of interrupt or SMI# when HOST_NOTIFY_STS (offset SMBASE + 10h, bit 0) is 1. This enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQB# or SMI# is generated, depending on the value of the SMB_SMI_EN bit (D31:F3:40h, bit 1). If the HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or SMI#) is logically generated by AND’ing the STS and INTREN bits. 0 = Disable 1 = Enable Description 2 1 0 19.2.17 NOTIFY_DADDR—Notify Device Address Register (SMBus—D31:F3) Register Offset: SMBASE + 14h Default Value: 00h Attribute: Size: RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit Description DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during the Host Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1. Reserved 7:1 0 Datasheet 719 SMBus Controller Registers (D31:F3) 19.2.18 NOTIFY_DLOW—Notify Data Low Byte Register (SMBus—D31:F3) Register Offset: SMBASE + 16h Default Value: 00h Attribute: Size: RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit Description DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1. 7:0 19.2.19 NOTIFY_DHIGH—Notify Data High Byte Register (SMBus—D31:F3) Register Offset: SMBASE + 17h Default Value: 00h Attribute: Size: RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit Description DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received during the Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1. 7:0 §§ 720 Datasheet PCI Express* Configuration Registers 20 20.1 Note: / PCI Express* Configuration Registers PCI Express* Configuration Registers (PCI Express—D28:F0/F1/F2/F3/F4/F5) Register address locations that are not shown in Table 20-1 and should be treated as Reserved. Table 20-1. PCI Express* Configuration Registers Address Map (PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 1 of 3) Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 18h–1Ah 1Bh 1Ch–1Dh 1Eh–1Fh 20h–23h 24h–27h 28h–2Bh 2Ch–2Fh 34h 3Ch–3Dh 3Eh–3Fh 40h–41h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC CLS PLT HEADTYP BNUM SLT IOBL SSTS MBL PMBL PMBU32 PMLU32 CAPP INTR BCTRL CLIST Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Cache Line Size Primary Latency Timer Header Type Bus Number Secondary Latency Timer I/O Base and Limit Secondary Status Register Memory Base and Limit Prefetchable Memory Base and Limit Prefetchable Memory Base Upper 32 Bits Prefetchable Memory Limit Upper 32 Bits Capabilities List Pointer Interrupt Information Bridge Control Register Capabilities List Function 0–5 Default 8086h See register description 0000h 0010h See register description 00h 04h 06h 00h 00h 81h 000000h 00h 0000h 0000h 00000000h 00010001h 00000000h 00000000h 40h See bit description 0000h 8010 Type RO RO R/W, RO R/WC, RO RO RO RO RO R/W RO RO R/W RO R/W, RO R/WC R/W R/W, RO R/W R/W RO R/W, RO R/W RO Datasheet 721 PCI Express* Configuration Registers Table 20-1. PCI Express* Configuration Registers Address Map (PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 2 of 3) Offset 42h–43h 44h–47h 48h–49h 4Ah–4Bh 4Ch–4Fh 50h–51h 52h–53h 54h–57h 58h–59h 5Ah–5Bh 5Ch–5Dh 60h–63h 64h-67h (Corporate Only) 68h–69h (Corporate Only) 70h–71h (Corporate Only) 80h–81h 82h–83h 84h–87h 88h–89h 90h–91h 94h–97h A0h–A1h A2h–A3h A4–A7h D4-D7h D8–DBh Mnemonic XCAP DCAP DCTL DSTS LCAP LCTL LSTS SLCAP SLCTL SLSTS RCTL RSTS DCAP2 Register Name PCI Express* Capabilities Device Capabilities Device Control Device Status Link Capabilities Link Control Link Status Slot Capabilities Register Slot Control Slot Status Root Control Root Status Device Capabilities 2 Register Function 0–5 Default 0041 00000FE0h 0000h 0010h See bit description 0000h See bit description 00000060h 0000h 0000h 0000h 00000000h 00000016h Type R/WO, RO RO R/W, RO R/WC, RO R/W, RO, R/WO R/W, WO, RO RO R/WO, RO R/W, RO R/WC, RO R/W R/WC, RO RO DCTL2 Device Control 2 Register 0000h R/W, RO LCTL2 Link Control 2 Register Message Signaled Interrupt Identifiers Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Message Data Subsystem Vendor Capability Subsystem Vendor Identification Power Management Capability PCI Power Management Capability PCI Power Management Control and Status Miscellaneous Port Configuration 2 Miscellaneous Port Configuration 0001h RO MID MC MA MD SVCAP SVID PMCAP PMC PMCS MPC2 MPC 9005h 0000h 00000000h 0000h A00Dh 00000000h 0001h C802h 00000000h 00000000h 08110000h RO R/W, RO R/W R/W RO R/WO RO RO R/W, RO R/W, RO R/W 722 Datasheet PCI Express* Configuration Registers Table 20-1. PCI Express* Configuration Registers Address Map (PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 3 of 3) Offset DC–DFh E1h E8-EBh 100–103h 104h–107h 108h–10Bh 10Ch–10Dh 10Eh–10Fh 110h–113h 114–117h 11A–11Bh 11Ch–143h 144h–147h 148h–14Bh 14Ch–14Fh 150h–153h 154h–157h 158h–15Bh 170h–173h 180h–183h 184h–187h 190h–193h 198h–19Fh 300-303h 318h 324h–327h Mnemonic SMSCS RPDCGEN PECR1 VCH — VCAP2 PVC PVS V0CAP V0CTL V0STS — UES UEM UEV CES CEM AECC RES RCTCL ESD ULD ULBA PECR2 PEETM PEC1 Register Name SMI/SCI Status Register Rort Port Dynamic Clock Gating Enable PCI Express Configuration Register 1 Virtual Channel Capability Header Reserved Virtual Channel Capability 2 Port Virtual Channel Control Port Virtual Channel Status Virtual Channel 0 Resource Capability Virtual Channel 0 Resource Control Virtual Channel 0 Resource Status Reserved Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Error Severity Correctable Error Status Correctable Error Mask Advanced Error Capabilities and Control Root Error Status Root Complex Topology Capability List Element Self Description Upstream Link Description Upstream Link Base Address PCI Express Configuration Register 2 PCI Express Extended Test Mode Register PCI Express Configuration Register 1 Function 0–5 Default 00000000h 00h 00000020h 18010002h — 00000001h 0000h 0000h 00000001h 800000FFh 0000h — See bit description 00000000h 00060011h 00000000h 00000000h 00000000h 00000000h 00010005h See bit description 00000001h See bit description 60005007h See bit description 00000000h Type R/WC R/W R/W R/WO — RO R/W RO RO R/W, RO RO — R/WC, RO R/WO, RO RO R/WC R/WO RO R/WC, RO RO RO RO RO R/W RO RO, R/W Datasheet 723 PCI Express* Configuration Registers 20.1.1 VID—Vendor Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 00h–01h Default Value: 8086h Bit 15:0 Attribute: Size: Description RO 16 bits Vendor ID — RO. This is a 16-bit value assigned to Intel 20.1.2 DID—Device Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 02h–03h Default Value: Port 1= Bit Port 2= Bit Port 3= Bit Port 4= Bit Port 5= Bit Port 6= Bit Bit 15:0 Description Description Description Description Description Description Attribute: Size: RO 16 bits Description Device ID — RO. This is a 16-bit value assigned to the Intel® ICH10 PCI Express controller. Refer to the Intel® I/O Controller Hub (ICH10) Family for the value of the Device ID Register 724 Datasheet PCI Express* Configuration Registers 20.1.3 PCICMD—PCI Command Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 04h–05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled HotPlug and power management events. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power management and MSI is not enabled. 10 1 = Internal INTx# messages will not be generated. This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set. 9 8 7 Fast Back to Back Enable (FBE) — Reserved per the PCI Express* Base Specification. SERR# Enable (SEE) — R/W. 0 = Disable. 1 = Enables the root port to generate an SERR# message when PSTS.SSE is set. Wait Cycle Control (WCC) — Reserved per the PCI Express Base Specification. Parity Error Response (PER) — R/W. 6 0 = Disable. 1 = Indicates that the device is capable of reporting parity errors as a master on the backbone. VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specification. Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base Specification. Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specification. Bus Master Enable (BME) — R/W. 2 0 = Disable. All cycles from the device are master aborted 1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI Express* device. Memory Space Enable (MSE) — R/W. 1 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted on the backbone. 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the PCI Express device. I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers. 0 0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master aborted on the backbone. 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded to the PCI Express device. Attribute: Size: Description R/W, RO 16 bits 5 4 3 Datasheet 725 PCI Express* Configuration Registers 20.1.4 PCISTS—PCI Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 06h–07h Default Value: 0010h Bit 0 = No parity error detected. 1 = Set when the root port receives a command or data from the backbone with a parity error. This is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set. Signaled System Error (SSE) — R/WC. 14 0 = No system error signaled. 1 = Set when the root port signals a system error to the internal SERR# logic. Received Master Abort (RMA) — R/WC. 13 0 = Root port has not received a completion with unsupported request status from the backbone. 1 = Set when the root port receives a completion with unsupported request status from the backbone. Received Target Abort (RTA) — R/WC. 12 0 = Root port has not received a completion with completer abort from the backbone. 1 = Set when the root port receives a completion with completer abort from the backbone. Signaled Target Abort (STA) — R/WC. 11 0 = No target abort received. 1 = Set whenever the root port forwards a target abort received from the downstream device onto the backbone. DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base Specification. Master Data Parity Error Detected (DPED) — R/WC. 8 0 = No data parity error received. 1 = Set when the root port receives a completion with a data parity error on the backbone and PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set. Fast Back to Back Capable (FB2BC) — Reserved per the PCI Express* Base Specification. Reserved 66 MHz Capable — Reserved per the PCI Express* Base Specification. Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list. Interrupt Status — RO. Indicates status of Hot-Plug and power management interrupts on the root port that result in INTx# message generation. 3 0 = Interrupt is deasserted. 1 = Interrupt is asserted. This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3/F4/F5:04h:bit 10). 2:0 Reserved Attribute: Size: Description R/WC, RO 16 bits Detected Parity Error (DPE) — R/WC. 15 10:9 7 6 5 4 726 Datasheet PCI Express* Configuration Registers 20.1.5 RID—Revision Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID — RO. Refer to the Intel® I/O Controller Hub (ICH10) Family Specification Update for the value of the Revision ID Register 20.1.6 PI—Programming Interface Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 09h Default Value: 00h Bit 7:0 Programming Interface — RO. 00h = No specific register level programming interface defined. Attribute: Size: Description RO 8 bits 20.1.7 SCC—Sub Class Code Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Ah Default Value: 04h Bit Attribute: Size: Description RO 8 bits 7:0 Sub Class Code (SCC) — RO. This field is determined by bit 2 of the MPC register (D28:F0-5:Offset D8h, bit 2). 04h = PCI-to-PCI bridge. 00h = Host Bridge. 20.1.8 BCC—Base Class Code Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Bh Default Value: 06h Bit 7:0 Base Class Code (BCC) — RO. 06h = Indicates the device is a bridge device. Attribute: Size: Description RO 8 bits Datasheet 727 PCI Express* Configuration Registers 20.1.9 CLS—Cache Line Size Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Cache Line Size (CLS) — R/W. This is read/write but contains no functionality, per the PCI Express* Base Specification. 20.1.10 PLT—Primary Latency Timer Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Dh Default Value: 00h Bit 7:3 2:0 Attribute: Size: Description RO 8 bits Latency Count. Reserved per the PCI Express* Base Specification. Reserved 20.1.11 HEADTYP—Header Type Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Eh Default Value: 81h Bit Multi-Function Device — RO. 7 0 = Single-function device. 1 = Multi-function device. Configuration Layout— RO. This field is determined by bit 2 of the MPC register (D28:F0-5:Offset D8h, bit 2). 00h = Indicates a Host Bridge. 01h = Indicates a PCI-to-PCI bridge. Attribute: Size: Description RO 8 bits 6:0 20.1.12 BNUM—Bus Number Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 18–1Ah Default Value: 000000h Bit 23:16 15:8 7:0 Attribute: Size: Description R/W 24 bits Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below the bridge. Secondary Bus Number (SCBN) — R/W. Indicates the bus number the port. Primary Bus Number (PBN) — R/W. Indicates the bus number of the backbone. 728 Datasheet PCI Express* Configuration Registers 20.1.13 SLT—Secondary Latency Timer (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 1Bh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Secondary Latency Timer — Reserved for a Root Port per the PCI Express* Base Specification. 20.1.14 IOBL—I/O Base and Limit Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 1Ch–1Dh Default Value: 0000h Bit 15:12 11:8 7:4 3:0 Attribute: Size: Description R/W, RO 16 bits I/O Limit Address (IOLA) — R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh. I/O Limit Address Capability (IOLC) — R/O. Indicates that the bridge does not support 32-bit I/O addressing. I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h. I/O Base Address Capability (IOBC) — R/O. Indicates that the bridge does not support 32-bit I/O addressing. Datasheet 729 PCI Express* Configuration Registers 20.1.15 SSTS—Secondary Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 1Eh–1Fh Default Value: 0000h Bit 15 0 = No error. 1 = The port received a poisoned TLP. Received System Error (RSE) — R/WC. 14 0 = No error. 1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device. Received Master Abort (RMA) — R/WC. 13 0 = Unsupported Request not received. 1 = The port received a completion with “Unsupported Request” status from the device. Received Target Abort (RTA) — R/WC. 12 0 = Completion Abort not received. 1 = The port received a completion with “Completion Abort” status from the device. Signaled Target Abort (STA) — R/WC. 11 0 = Completion Abort not sent. 1 = The port generated a completion with “Completion Abort” status to the device. 10:9 Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base Specification. Data Parity Error Detected (DPD) — R/WC. 0 = Conditions below did not occur. 8 1 = Set when the BCTRL.PERE (D28:FO/F1/F2/F3/F4/F5:3E: bit 0) is set, and either of the following two conditions occurs: • • Port receives completion marked poisoned. Port poisons a write request to the secondary side. Attribute: Size: Description R/WC 16 bits Detected Parity Error (DPE) — R/WC. 7 6 5 4:0 Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base Specification. Reserved Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification. Reserved 730 Datasheet PCI Express* Configuration Registers 20.1.16 MBL—Memory Base and Limit Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 20h–23h Default Value: 00000000h Attribute: Size: R/W 32 bits Accesses that are within the ranges specified in this register will be sent to the attached device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5:04:bit 1) is set. Accesses from the attached device that are outside the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/F2/F3/F4/F5:04:bit 2) is set. The comparison performed is MB ≥ AD[31:20] ≤ ML. Bit 31:20 19:16 15:4 3:0 Description Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value of the range. Reserved Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value of the range. Reserved 20.1.17 PMBL—Prefetchable Memory Base and Limit Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 24h–27h Default Value: 00010001h Attribute: Size: R/W, RO 32 bits Accesses that are within the ranges specified in this register will be sent to the device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5;04, bit 1) is set. Accesses from the device that are outside the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/ F2/F3/F4/F5;04, bit 2) is set. The comparison performed is PMBU32:PMB ≥ AD[63:32]:AD[31:20] ≤ PMLU32:PML. Bit 31:20 19:16 15:4 3:0 Description Prefetchable Memory Limit (PML) — R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value of the range. 64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing Prefetchable Memory Base (PMB) — R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value of the range. 64-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing 20.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 28h–2Bh Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the prefetchable address base. Datasheet 731 PCI Express* Configuration Registers 20.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 2Ch–2Fh Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the prefetchable address limit. 20.1.20 CAPP—Capabilities List Pointer Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 34h Default Value: 40h Bit 7:0 Attribute: Size: Description R0 8 bits Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the capabilities list is at 40h in configuration space. 20.1.21 INTR—Interrupt Information Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: Default Value: Function Level Reset: Bit 3Ch–3Dh See bit description No (Bits 7:0 only) Attribute: Size: R/W, RO 16 bits Description Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the root port. At reset, this register takes on the following values, which reflect the reset state of the D28IP register in chipset config space: Port Reset Value D28IP.P1IP D28IP.P2IP D28IP.P3IP D28IP.P4IP D28IP.P5IP 15:8 1 2 3 4 5 NOTE: The value that is programmed into D28IP is always reflected in this register. 7:0 Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. These bits are not reset by FLR. 732 Datasheet PCI Express* Configuration Registers 20.1.22 BCTRL—Bridge Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 3Eh–3Fh Default Value: 0000h Bit 15:12 11 10 9 8 7 6 5 Reserved Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification, Revision 1.0a Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision 1.0a. Secondary Discard Timer (SDT): Reserved per PCI Express* Base Specification, Revision 1.0a. Primary Discard Timer (PDT): Reserved per PCI Express* Base Specification, Revision 1.0a. Fast Back to Back Enable (FBE): Reserved per PCI Express* Base Specification, Revision 1.0a. Secondary Bus Reset (SBR) — R/W. Triggers a hot reset on the PCI Express* port. Master Abort Mode (MAM): Reserved per Express specification. VGA 16-Bit Decode (V16) — R/W. 4 0 = VGA range is enabled. 1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled, and only the base I/O ranges can be decoded VGA Enable (VE)— R/W. 0 = The ranges below will not be claimed off the backbone by the root port. 3 1 = The following ranges will be claimed off the backbone by the root port: • • Memory ranges A0000h-BFFFFh I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits 15:10 in any combination of 1s Attribute: Size: Description R/W 16 bits ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. 2 0 = The root port will not block any forwarding from the backbone as described below. 1 = The root port will block any forwarding from the backbone to the device of I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh). SERR# Enable (SE) — R/W. 1 0 = The messages described below are not forwarded to the backbone. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are forwarded to the backbone. Parity Error Response Enable (PERE) — R/W. 0 0 = Poisoned write TLPs and completions indicating poisoned TLPs will not set the SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8). 1 = Poisoned write TLPs and completions indicating poisoned TLPs will set the SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8). Datasheet 733 PCI Express* Configuration Registers 20.1.23 CLIST—Capabilities List Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 40–41h Default Value: 8010h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) — RO. Value of 80h indicates the location of the next pointer. Capability ID (CID) — RO. Indicates this is a PCI Express* capability. 20.1.24 XCAP—PCI Express* Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 42h–43h Default Value: 0041h Bit 15:14 13:9 Reserved Interrupt Message Number (IMN) — RO. The Intel® ICH10 does not have multiple MSI interrupt numbers. Slot Implemented (SI) — R/WO. Indicates whether the root port is connected to a slot. Slot support is platform specific. BIOS programs this field, and it is maintained until a platform reset. Device / Port Type (DT) — RO. Indicates this is a PCI Express* root port. Capability Version (CV) — RO. Indicates PCI Express 1.0. Attribute: Size: Description R/WO, RO 16 bits 8 7:4 3:0 734 Datasheet PCI Express* Configuration Registers 20.1.25 DCAP—Device Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 44h–47h Default Value: 00008FC0h Bit 31:28 27:26 25:18 17:16 15 14:12 11:9 8:6 5 4:3 2:0 Reserved Captured Slot Power Limit Scale (CSPS) — RO. Not supported. Captured Slot Power Limit Value (CSPV) — RO. Not supported. Reserved Role Based Error Reporting (RBER) — RO. Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 spec. Reserved Endpoint L1 Acceptable Latency (E1AL) — RO. This field is reserved with a setting of 000b for devices other than Endpoints, per the PCI Express 1.1 Spec. Endpoint L0s Acceptable Latency (E0AL) — RO. This field is reserved with a setting of 000b for devices other than Endpoints, per the PCI Express 1.1 Spec. Extended Tag Field Supported (ETFS) — RO. Indicates that 8-bit tag fields are supported. Phantom Functions Supported (PFS) — RO. No phantom functions supported. Max Payload Size Supported (MPS) — RO. Indicates the maximum payload size supported is 128B. Attribute: Size: Description RO 32 bits Datasheet 735 PCI Express* Configuration Registers 20.1.26 DCTL—Device Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 48h–49h Default Value: 0000h Bit 15 14:12 11 10 9 8 7:5 4 Reserved Max Read Request Size (MRRS) — RO. Hardwired to 0. Enable No Snoop (ENS) — RO. Not supported. The root port will never issue non-snoop requests. Aux Power PM Enable (APME) — R/W. The OS will set this bit to 1 if the device connected has detected aux power. It has no effect on the root port otherwise. Phantom Functions Enable (PFE) — RO. Not supported. Extended Tag Field Enable (ETFE) — RO. Not supported. Max Payload Size (MPS) — R/W. The root port only supports 128-B payloads, regardless of the programming of this field. Enable Relaxed Ordering (ERO) — RO. Not supported. Unsupported Request Reporting Enable (URE) — R/W. 0 = The root port will ignore unsupported request errors. 3 1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when detecting an unmasked Unsupported Request (UR). An ERR_COR is signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable nonAdvisory UR is received with the severity set by the Uncorrectable Error Severity register. Fatal Error Reporting Enable (FEE) — R/W. 0 = The root port will ignore fatal errors. 2 1 = Enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. Non-Fatal Error Reporting Enable (NFE) — R/W. 0 = The root port will ignore non-fatal errors. 1 1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. Correctable Error Reporting Enable (CEE) — R/W. 0 = The root port will ignore correctable errors. 0 1 = Enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. Attribute: Size: Description R/W, RO 16 bits 736 Datasheet PCI Express* Configuration Registers 20.1.27 DSTS—Device Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 4Ah–4Bh Default Value: 0010h Bit 15:6 5 4 3 Reserved Transactions Pending (TDP) — RO. This bit has no meaning for the root port since only one transaction may be pending to the Intel® ICH10, so a read of this bit cannot occur until it has already returned to 0. AUX Power Detected (APD) — RO. The root port contains AUX power for wakeup. Unsupported Request Detected (URD) — R/WC. Indicates an unsupported request was detected. Fatal Error Detected (FED) — R/WC. Indicates a fatal error was detected. 2 0 = Fatal has not occurred. 1 = A fatal error occurred from a data link protocol error, link training error, buffer overflow, or malformed TLP. Non-Fatal Error Detected (NFED) — R/WC. Indicates a non-fatal error was detected. 1 0 = Non-fatal has not occurred. 1 = A non-fatal error occurred from a poisoned TLP, unexpected completions, unsupported requests, completer abort, or completer timeout. Correctable Error Detected (CED) — R/WC. Indicates a correctable error was detected. 0 0 = Correctable has not occurred. 1 = The port received an internal correctable error from receiver errors / framing errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout. Attribute: Size: Description R/WC, RO 16 bits Datasheet 737 PCI Express* Configuration Registers 20.1.28 LCAP—Link Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 4Ch–4Fh Default Value: See bit description Bit Attribute: Size: Description R/WO, RO 32 bits Port Number (PN) — RO. Indicates the port number for the root port. This value is different for each implemented port: Function D28:F0 31:24 D28:F1 D28:F2 D28:F3 D28:F4 D28:F5 23:22 21 (Corporate Only) 21 (Consumer Only) 20 19:18 17:15 Reserved Link Bandwidth Notification Capability (LBNC) – RO. 0 = Indicates root port can only support x1 link widths. 1 = Indicates root port can support link widths greater than x1. NOTE: Ports 1, 3, and 5 are required to set this bit. Ports 2, 4 and 6 can optionally set this bit. Reserved Link Active Reporting Capable (LARC) — RO. Hardwired to 1 to indicate that this port supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. Reserved L1 Exit Latency (EL1) — RO. Set to 010b to indicate an exit latency of 2 µs to 4 µs. L0s Exit Latency (EL0) — RO. Indicates as exit latency based upon commonclock configuration. LCLT.CCC 0 1 Value of EL0 (these bits) MPC.UCEL (D28:F0/F1/F2/F3:D8h:bits20:18) MPC.CCEL (D28:F0/F1/F2/F3:D8h:bits17:15) Port # 1 2 3 4 5 6 Value of PN Field 01h 02h 03h 04h 05h 06h 14:12 NOTE: LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5:50h:bit 6 738 Datasheet PCI Express* Configuration Registers Bit Description Active State Link PM Support (APMS) — R/WO. Indicates what level of active state link power management is supported on the root port. Bits Definition Neither L0s nor L1 are supported L0s Entry Supported L1 Entry Supported Both L0s and L1 Entry Supported 11:10 00b 01b 10b 11b Maximum Link Width (MLW) — RO. For the root ports, several values can be taken, based upon the value of the chipset config register field RPC.PC1 (Chipset Config Registers:Offset 0224h:bits1:0) for Ports 1-4 and RPC.PC2 (Chipset Config Registers:Offset 0224h:bits1:0) for Ports 5 and 6 Value of MLW Field Port # 9:4 1 2 3 4 Port # 5 3:0 RPC.PC1=00b 01h 01h 01h 01h RPC.PC2=00b 01h RPC.PC1=11b 04h 01h 01h 01h RPC.PC2=11b N/A Maximum Link Speed (MLS) — RO. Set to 1h to indicate the link speed is 2.5 Gb/s. Datasheet 739 PCI Express* Configuration Registers 20.1.29 LCTL—Link Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 50h-51h Default Value: 0000h Bit 15:8 Reserved Extended Synch (ES) — R/W. 7 0 = Extended synch disabled. 1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. Common Clock Configuration (CCC) — R/W. 6 0 = The ICH10 and device are not using a common reference clock. 1 = The ICH10 and device are operating with a distributed common reference clock. Retrain Link (RL) — R/W. 0 = This bit always returns 0 when read. 1 = The root port will train its downstream link. NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5:52, bit 11) to check the status of training. NOTE: It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that is already in progress. Link Disable (LD) — R/W. 4 0 = Link enabled. 1 = The root port will disable the link. 3 2 Read Completion Boundary Control (RCBC) — RO. Indicates the read completion boundary is 64 bytes. Reserved Active State Link PM Control (APMC) — R/W. Indicates whether the root port should enter L0s or L1 or both. 00 = Disabled 1:0 01 = L0s Entry Enabled 10 = L1 Entry Enabled 11 = L0s and L1 Entry Enabled Attribute: Size: Description R/W, RO 16 bits 5 740 Datasheet PCI Express* Configuration Registers 20.1.30 LSTS—Link Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 52h–53h Default Value: See bit description Bit 15:14 13 Reserved Data Link Layer Active (DLLA) — RO. Default value is 0b. 0 = Data Link Control and Management State Machine is not in the DL_Active state 1 = Data Link Control and Management State Machine is in the DL_Active state 12 Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Intel® ICH10 uses the same reference clock as on the platform and does not generate its own clock. Link Training (LT) — RO. Default value is 0b. 11 10 0 = Link training completed. 1 = Link training is occurring. Link Training Error (LTE) — RO. Not supported. Set value is 0b. Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the given PCI Express* link. The contents of this NLW field is undefined if the link has not successfully trained. Port # 1 9:4 2 3 4 5 6 Possible Values 000001b, 000010b, 000100b 000001b 000001b 000001b 000001b, 000010b 000001b Attribute: Size: Description RO 16 bits NOTE: 000001b = x1 link width, 000010b =x2 linkwidth, 000100b = x4 linkwidth 3:0 Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI Express* link. 01h = Link is 2.5 Gb/s. Datasheet 741 PCI Express* Configuration Registers 20.1.31 SLCAP—Slot Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 54h–57h Default Value: 00000060h (Consumer Only) 00040060h (Corporate Only) Bit 31:19 18:17 16:15 Attribute: Size: R/WO, RO 32 bits Description Physical Slot Number (PSN) — R/WO. This is a value that is unique to the slot number. BIOS sets this field and it remains set until a platform reset. Reserved. Corporate Only 10h. Consumer Only 00h Slot Power Limit Scale (SLS) — R/WO. Specifies the scale used for the slot power limit value. BIOS sets this field and it remains set until a platform reset. Slot Power Limit Value (SLV) — R/WO. Specifies the upper limit (in conjunction with SLS value), on the upper limit on power supplied by the slot. The two values together indicate the amount of power in watts allowed for the slot. BIOS sets this field and it remains set until a platform reset. Hot Plug Capable (HPC) — R/WO. 1b = Indicates that Hot-Plug is supported. Hot Plug Surprise (HPS) — R/WO. 1b = Indicates the device may be removed from the slot without prior notification. Power Indicator Present (PIP) — RO. 0b = Indicates that a power indicator LED is not present for this slot. Attention Indicator Present (AIP) — RO. 0b = Indicates that an attention indicator LED is not present for this slot. MRL Sensor Present (MSP) — RO. 0b = Indicates that an MRL sensor is not present. Power Controller Present (PCP) — RO. 0b = Indicates that a power controller is not implemented for this slot. Attention Button Present (ABP) — RO. 0b = Indicates that an attention button is not implemented for this slot. 14:7 6 5 4 3 2 1 0 742 Datasheet PCI Express* Configuration Registers 20.1.32 SLCTL—Slot Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 58h–59h Default Value: 0000h Bit 15:13 12 11 10 9:6 (Corporate Only) Reserved Link Active Changed Enable (LACE) — R/W. When set, this field enables generation of a hot plug interrupt when the Data Link Layer Link Active field (D28:F0/F1/F2/F3/F4/F5:52h:bit 13) is changed. Reserved Power Controller Control (PCC) — RO.This bit has no meaning for module based Hot-Plug. Reserved Power Indicator Control (PIC) — R/W. When read, the current state of the power indicator is returned. When written, the appropriate POWER_INDICATOR_* messages are sent. Defined encodings are: 9:8 (Consumer Only) Bits 00b 01b 10b 11b Definition Reserved On Blink Off Attribute: Size: Description R/W, RO 16 bits Attention Indicator Control (AIC) — R/W. When read, the current state of the attention indicator is returned. When written, the appropriate ATTENTION_INDICATOR_* messages are sent. Defined encodings are: 7:6 (Consumer Only) Bits 00b 01b 10b 11b Definition Reserved On Blink Off Hot Plug Interrupt Enable (HPE) — R/W. 5 0 = Hot plug interrupts based on Hot-Plug events is disabled. 1 = Enables generation of a Hot-Plug interrupt on enabled Hot-Plug events. 4 (Consumer Only) 4 (Corporate Only) Command Completed Interrupt Enable (CCE) — R/W. 0 = Hot plug interrupts based on command completions is disabled. 1 = Enables the generation of a Hot-Plug interrupt when a command is completed by the Hot-Plug controller. Reserved Presence Detect Changed Enable (PDE) — R/W. 3 0 = Hot plug interrupts based on presence detect logic changes is disabled. 1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence detect logic changes state. Datasheet 743 PCI Express* Configuration Registers Bit 2:1 Reserved. Description Attention Button Pressed Enable (ABE) — R/W. When set, enables the generation of a Hot-Plug interrupt when the attention button is pressed. 0 0 = Hot plug interrupts based on the attention button being pressed is disabled. 1 = Enables the generation of a Hot-Plug interrupt when the attention button is pressed. 20.1.33 SLSTS—Slot Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 5Ah–5Bh Default Value: 0000h Bit 15:9 Reserved Link Active State Changed (LASC) — R/WC. 1 = This bit is set when the value reported in Data Link Layer Link Active field of the Link Status register (D28:F0/F1/F2/F3/F4/F5:52h:bit 13) is changed. In response to a Data Link Layer State Changed event, software must read Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device. Reserved Presence Detect State (PDS) — RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5:42h:bit 8) is set (indicating that this root port spawns a slot), then this bit: 6 0 = Indicates the slot is empty. 1 = Indicates the slot has a device connected. Otherwise, if XCAP.SI is cleared, this bit is always set (1). 5 4 (Corporate Only) 4 (Consumer Only) MRL Sensor State (MS) — Reserved as the MRL sensor is not implemented. Reserved Command Completed (CC) — R/WC. 0 = Issued command not completed. 1 = The Hot-Plug controller completed an issued command. This is set when the last message of a command is sent and indicates that software can write a new command to the slot controller. Presence Detect Changed (PDC) — R/WC. 3 2 1 0 (Corporate Only) 0 (Consumer Only) 0 = No change in the PDS bit. 1 = The PDS bit changed states. MRL Sensor Changed (MSC) — Reserved as the MRL sensor is not implemented. Power Fault Detected (PFD) — Reserved as a power controller is not implemented. Reserved Attention Button Pressed (ABP) — R/WC. 0 = The attention button has not been pressed. 1 = The attention button is pressed. Attribute: Size: Description R/WC, RO 16 bits 8 7 744 Datasheet PCI Express* Configuration Registers 20.1.34 RCTL—Root Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 5Ch–5Dh Default Value: 0000h Bit 15:4 Reserved PME Interrupt Enable (PIE) — R/W. 0 = Interrupt generation disabled. 3 1 = Interrupt generation enabled when PCISTS.Inerrupt Status (D28:F0/F1/F2/F3/F4/ F5:60h, bit 16) is in a set state (either due to a 0 to 1 transition, or due to this bit being set with RSTS.IS already set). System Error on Fatal Error Enable (SFE) — R/W. 0 = An SERR# will not be generated. 2 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit 8) is set, if a fatal error is reported by any of the devices in the hierarchy of this root port, including fatal errors in this root port. System Error on Non-Fatal Error Enable (SNE) — R/W. 0 = An SERR# will not be generated. 1 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the hierarchy of this root port, including non-fatal errors in this root port. System Error on Correctable Error Enable (SCE) — R/W. 0 = An SERR# will not be generated. 0 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit 8) if a correctable error is reported by any of the devices in the hierarchy of this root port, including correctable errors in this root port. Attribute: Size: Description R/W 16 bits 20.1.35 RSTS—Root Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 60h–63h Default Value: 00000000h Bit 31:18 Reserved PME Pending (PP) — RO. 17 0 = When the original PME is cleared by software, it will be set again, the requestor ID will be updated, and this bit will be cleared. 1 = Indicates another PME is pending when the PME status bit is set. PME Status (PS) — R/WC. 16 0 = PME was not asserted. 1 = Indicates that PME was asserted by the requestor ID in RID. Subsequent PMEs are kept pending until this bit is cleared. PME Requestor ID (RID) — RO. Indicates the PCI requestor ID of the last PME requestor. Valid only when PS is set. Attribute: Size: Description R/WC, RO 32 bits 15:0 Datasheet 745 PCI Express* Configuration Registers 20.1.36 DCAP2—Device Capabilities 2 Register (Corporate Only) (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 64h–67h Default Value: 00000016h Bit 31:5 4 Reserved Completion Timeout Disable Supported (CTDS) — RO. A value of 1b indicates support for the Completion Timeout Disable mechanism. Completion Timeout Ranges Supported (CTRS) – RO. This field indicates device support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This field is hardwired to support 10 ms to 250 ms and 250 ms to 4 s. Attribute: Size: Description RO 32 bits 3:0 20.1.37 DCTL2—Device Control 2 Register (Corporate Only) (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 68h–69h Default Value: 0000h Bit 15:5 Reserved Completion Timeout Disable (CTD) — RW. When set to 1b, this bit disables the Completion Timeout mechanism. 4 If there are outstanding requests when the bit is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding requests. If this is done, it is permitted to base the start time for each request on either the time this bit was cleared or the time each request was issued. Completion Timeout Value (CTV) — RW. This field allows system software to modify the Completion Timeout value. 0000b = 40–50 ms (Default) (specification range 50 us to 50 ms) 0101b = 40–50 ms (specification range is 16 ms to 55 ms) 0110b = 160–170 ms (specification range is 65 ms to 210 ms) 1001b = 400–500 ms (specification range is 260 ms to 900 ms) 3:0 1010b = 1.6–1.7 s (specification range is 1 s to 3.5 s) All other values are Reserved. NOTE: Software is permitted to change the value in this field at any time. For requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding requests, and is permitted to base the start time for each request either on when this value was changed or on when each request w as issued. Attribute: Size: Description RO, R/W 16 bits 746 Datasheet PCI Express* Configuration Registers 20.1.38 LCTL2—Link Control 2 Register (Corporate Only) (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 70h–71h Default Value: 0001h Bit 15:4 Reserved Target Link Speed (TLS)— RO. This field sets an upper limit on Link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b = 2.5 GT/s Target Link Speed All other values reserved Attribute: Size: Description RO 16 bits 3:0 20.1.39 MID—Message Signaled Interrupt Identifiers Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 80h–81h Default Value: 9005h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Pointer (NEXT) — RO. Indicates the location of the next pointer in the list. Capability ID (CID) — RO. Capabilities ID indicates MSI. 20.1.40 MC—Message Signaled Interrupt Message Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 82–83h Default Value: 0000h Bit 15:8 7 6:4 3:1 Reserved 64 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only. Multiple Message Enable (MME) — R/W. These bits are R/W for software compatibility, but only one message is ever sent by the root port. Multiple Message Capable (MMC) — RO. Only one message is required. MSI Enable (MSIE) — R/W. 0 = MSI is disabled. 0 1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts. NOTE: CMD.BME (D28:F0/F1/F2/F3/F4/F5:04h:bit 2) must be set for an MSI to be generated. If CMD.BME is cleared, and this bit is set, no interrupts (not even pin based) are generated. Attribute: Size: Description R/W, RO 16 bits Datasheet 747 PCI Express* Configuration Registers 20.1.41 MA—Message Signaled Interrupt Message Address Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 84h–87h Default Value: 00000000h Bit 31:2 1:0 Attribute: Size: Description R/W 32 bits Address (ADDR) — R/W. Lower 32 bits of the system specified message address, always DW aligned. Reserved 20.1.42 MD—Message Signaled Interrupt Message Data Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 88h–89h Default Value: 0000h Bit 15:0 Attribute: Size: Description R/W 16 bits Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is enabled. Its content is driven onto the lower word (PCI AD[15:0]) during the data phase of the MSI memory write transaction. 20.1.43 SVCAP—Subsystem Vendor Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 90h–91h Default Value: A00Dh Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) — RO. Indicates the location of the next pointer in the list. Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor capability. 20.1.44 SVID—Subsystem Vendor Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 94h–97h Default Value: 00000000h Bit 31:16 Attribute: Size: Description R/WO 32 bits Subsystem Identifier (SID) — R/WO. Indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). Subsystem Vendor Identifier (SVID) — R/WO. Indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). 15:0 748 Datasheet PCI Express* Configuration Registers 20.1.45 PMCAP—Power Management Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: A0h–A1h Default Value: 0001h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) — RO. Indicates this is the last item in the list. Capability Identifier (CID) — RO. Value of 01h indicates this is a PCI power management capability. 20.1.46 PMC—PCI Power Management Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: A2h–A3h Default Value: C802h Bit Attribute: Size: Description RO 16 bits 15:11 PME_Support (PMES) — RO. Indicates PME# is supported for states D0, D3HOT and D3COLD. The root port does not generate PME#, but reporting that it does is necessary for some legacy operating systems to enable PME# in devices connected behind this root port. D2_Support (D2S) — RO. The D2 state is not supported. D1_Support (D1S) — RO The D1 state is not supported. Aux_Current (AC) — RO. Reports 375 mA maximum suspend well current required when in the D3COLD state. Device Specific Initialization (DSI) — RO. 1 = Indicates that no device-specific initialization is required. Reserved PME Clock (PMEC) — RO. 1 = Indicates that PCI clock is not required to generate PME#. Version (VS) — RO. Indicates support for Revision 1.1 of the PCI Power Management Specification. 10 9 8:6 5 4 3 2:0 Datasheet 749 PCI Express* Configuration Registers 20.1.47 PMCS—PCI Power Management Control and Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: A4h–A7h Default Value: 00000000h Bit 31:24 23 22 21:16 15 14:9 Reserved Bus Power / Clock Control Enable (BPCE) — Reserved per PCI Express* Base Specification, Revision 1.0a. B2/B3 Support (B23S) — Reserved per PCI Express* Base Specification, Revision 1.0a. Reserved PME Status (PMES) — RO. 1 = Indicates a PME was received on the downstream link. Reserved PME Enable (PMEE) — R/W. 8 1 = Indicates PME is enabled. The root port takes no action on this bit, but it must be R/W for some legacy operating systems to enable PME# on devices connected to this root port. This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which is not asserted during a warm reset. 7:2 Reserved Power State (PS) — R/W. This field is used both to determine the current power state of the root port and to set a new power state. The values are: 00 = D0 state 11 = D3HOT state 1:0 NOTE: When in the D3HOT state, the controller’s configuration space is available, but the I/O and memory spaces are not. Type 1 configuration cycles are also not accepted. Interrupts are not required to be blocked as software will disable interrupts prior to placing the port into D3HOT. If software attempts to write a ‘10’ or ‘01’ to these bits, the write will be ignored. Attribute: Size: Description R/W, RO 32 bits 750 Datasheet PCI Express* Configuration Registers 20.1.48 MPC2—Miscellaneous Port Configuration Register 2 (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: D4h–D7h Default Value: 00000000h Bit 31:5 Reserved. ASPM Control Override Enable (ASPMCOEN) — RW. 4 (Corporate Only) 1 = DMI will use the values in the ASPM Control Override registers 0 = DMI will use the ASPM Registers in the Link Control register. NOTES:This register allows BIOS to control the DMI ASPM settings instead of the OS. Reserved ASPM Control Override (ASPMO) — RW. Provides BIOS control of whether DMI should enter L0s or L1 or both. 00 = Disabled 01 = L0s Entry Enabled 10 = L1 Entry Enabled 11 = L0s and L1 Entry Enabled. 3:2 (Consumer Only) Reserved EOI Forwarding Disable (EOIFD) — R/W. When set, EOI messages are not claimed on the backbone by this port an will not be forwarded across the PCIe link. 0 = EOI forwarding is disabled. 1 = EOI forwarding is enabled. L1 Completion Timeout Mode (LICTM) — R/W. 0 0 = PCI Express Specification Compliant. Completion timeout is disabled during software initiated L1, and enabled during ASPM initiate L1. 1 = Completion timeout is enabled during L1, regardless of how L1 entry was initiated. Attribute: Size: Description R/W, RO 32 bits 4 (Consumer Only) 3:2 (Corporate Only) 1 Datasheet 751 PCI Express* Configuration Registers 20.1.49 MPC—Miscellaneous Port Configuration Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: D8h–DBh Default Value: 08110000h Bit Attribute: Size: Description R/W, RO 32 bits Power Management SCI Enable (PMCE) — R/W. 31 0 = SCI generation based on a power management event is disabled. 1 = Enables the root port to generate SCI whenever a power management event is detected. Hot Plug SCI Enable (HPCE) — R/W. 30 0 = SCI generation based on a Hot-Plug event is disabled. 1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected. Link Hold Off (LHO) — R/W. 29 1 = Port will not take any TLP. This is used during loopback mode to fill up the downstream queue. Address Translator Enable (ATE) — R/W. This bit is used to enable address translation via the AT bits in this register during loopback mode. 0 = Disable 1 = Enable Lane Reversal (LR) — R/O. Consumer Only: This register reads the setting of the SATALED# strap. Corporate Only: This register reads the setting of the PCIELR1 Soft Strap. 0 = PCI Express Lanes 0-3 are reversed. 27 1 = No Lane reversal (default). NOTE: The port configuration straps must be set such that Port 1 is configured as a x4 port using lanes 0-3 when Lane Reversal is enabled. x2 lane reversal is not supported. NOTE: This register is only valid on port 1. Invalid Receive Bus Number Check Enable (IRBNCE) — R/W. When set, the receive transaction layer will signal an error if the bus number of a Memory request does not fall within the range between SCBN and SBBN. If this check is enabled and the request is a memory write, it is treated as an Unsupported Request. If this check is enabled and the request is a non-posted memory read request, the request is considered a Malformed TLP and a fatal error. Messages, I/O, Config, and Completions are never checked for valid bus number. Invalid Receive Range Check Enable (IRRCE) — R/W. When set, the receive transaction layer will treat the TLP as an Unsupported Request error if the address range of a Memory request does not outside the range between prefetchable and nonprefetchable base and limit. Messages, I/O, Configuration, and Completions are never checked for valid address ranges. BME Receive Check Enable (BMERCE) — R/W. When set, the receive transaction layer will treat the TLP as an Unsupported Request error if a memory read or write request is received and the Bus Master Enable bit is not set. Messages, IO, Config, and Completions are never checked for BME. 23 Reserved 28 26 25 24 752 Datasheet PCI Express* Configuration Registers Bit Description Detect Override (FORCEDET) — R/W. 0 = Normal operation. Detected output from AFE is sampled for presence detection. 1 = Override mode. Ignores AFE detect output and link training proceeds as if a device were detected. Flow Control During L1 Entry (FCDL1E) — R/W. 0 = No flow control update DLLPs sent during L1 Ack transmission. 1 = Flow control update DLLPs sent during L1 Ack transmission as required to meet the 30 μs periodic flow control update. Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit Latency for unique-clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/ F5:Offset 50h:bit 6). It defaults to 512 ns to less than 1 µs, but may be overridden by BIOS. Common Clock Exit Latency (CCEL) — R/W. This value represents the L0s Exit Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/ F5:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden by BIOS. Reserved Port I/OxApic Enable (PAE) — R/W. 0 = Hole is disabled. 1 = A range is opened through the bridge for the following memory addresses: Port # 1 Address FEC1_0000h – FEC1_7FFFh FEC1_8000h – FEC1_FFFFh FEC2_0000h – FEC2_7FFFh FEC2_8000h – FEC2_FFFFh FEC3_0000h – FEC3_7FFFh FEC3_8000h – FEC3_FFFFh 22 21 20:18 17:15 14:8 7 2 3 4 5 6 6:3 Reserved Bridge Type (BT) — RO. This register can be used to modify the Base Class and Header Type fields from the default P2P bridge to a Host Bridge. Having the root port appear as a Host Bridge is useful in some server configurations. 2 0 = The root port bridge type is a P2P Bridge, Header Sub-Class = 04h, and Header Type = Type 1. 1 = The root port bridge type is a P2P Bridge, Header Sub-Class = 00h, and Header Type = Type 0. Hot Plug SMI Enable (HPME) — R/W. 1 0 = SMI generation based on a Hot-Plug event is disabled. 1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected. Power Management SMI Enable (PMME) — R/W. 0 = SMI generation based on a power management event is disabled. 1 = Enables the root port to generate SMI whenever a power management event is detected. 0 Datasheet 753 PCI Express* Configuration Registers 20.1.50 SMSCS—SMI/SCI Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: DCh–DFh Default Value: 00000000h Bit 31 Attribute: Size: Description R/WC 32 bits Power Management SCI Status (PMCS) — R/WC. 1 = PME control logic needs to generate an interrupt, and this interrupt has been routed to generate an SCI. Hot Plug SCI Status (HPCS) — R/WC. 30 29:5 1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been routed to generate an SCI. Reserved Hot Plug Link Active State Changed SMI Status (HPLAS) — R/WC. 4 1 = SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5:5A, bit 8) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot Plug Command Completed SMI Status (HPCCM) — R/WC. 3 1 = SLSTS.CC (D28:F0/F1/F2/F3/F4/F5:5A, bit 4) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot Plug Attention Button SMI Status (HPABM) — R/WC. 2 1 = SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5:5A, bit 0) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot Plug Presence Detect SMI Status (HPPDM) — R/WC. 1 1 = SLSTS.PDC (D28:F0/F1/F2/F3/F4/F5:5A, bit 3) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Power Management SMI Status (PMMS) — R/WC. 0 1 = RSTS.PS (D28:F0/F1/F2/F3/F4/F5:60, bit 16) transitioned from 0-to-1, and MPC.PMME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. 754 Datasheet PCI Express* Configuration Registers 20.1.51 RPDCGEN—Root Port Dynamic Clock Gating Enable (PCI Express-D28:F0/F1/F2/F3/F4/F5) Address Offset: E1h Default Value: 00h Bits 7:4 Reserved. RO Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — RW. 0 = Disables dynamic clock gating of the shared resource link clock domain. 3 1 = Enables dynamic clock gating on the root port shared resource link clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) — RW. 0 = Disables dynamic clock gating of the shared resource backbone clock domain. 2 1 = Enables dynamic clock gating on the root port shared resource backbone clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) — RW. 1 0 = Disables dynamic clock gating of the root port link clock domain. 1 = Enables dynamic clock gating on the root port link clock domain. Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) — RW. 0 0 = Disables dynamic clock gating of the root port backbone clock domain. 1 = Enables dynamic clock gating on the root port backbone clock domain. Attribute: Size: Description R/W 8-bits 20.1.52 PECR1—PCI Express* Configuration Register 1 (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: E8h–EBh Default Value: 00000020h Bit 31:2 1 0 Reserved PECR1 Field 2 — R/W. BIOS may set this bit to 1. Reserved. Attribute: Size: Description R/W 32 bits Datasheet 755 PCI Express* Configuration Registers 20.1.53 VCH—Virtual Channel Capability Header Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 100h–103h Default Value: 18010002h Bit 31:20 Attribute: Size: Description RWO 32 bits Next Capability Offset (NCO) — R/WO. Indicates the next item in the list. 000h = Does not support Root Complex Topology Capability Structure. 180h = Supports Root Complex Topology Capability Structure. Capability Version (CV) — R/WO. Indicates the version of the capability structure by the PCI SIG. 19:16 0h = Does not support PCI Express virtual Channel capability and the Root complex topology Capability Structure. 1h = Supports PCI Express virtual Channel capability and the Root complex topology Capability Structure. Capability ID (CID) — R/WO. Indicates this is the Virtual Channel capability item. 15:0 0000h = Does not support PCI Express virtual Channel capability and the Root complex topology Capability Structure. 0002h = Supports PCI Express virtual Channel capability and the Root complex topology Capability Structure. 20.1.54 VCAP2—Virtual Channel Capability 2 Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 108h–10Bh Default Value: 00000001h Bit 31:24 23:0 Attribute: Size: Description RO 32 bits VC Arbitration Table Offset (ATO) — RO. Indicates that no table is present for VC arbitration since it is fixed. Reserved. 20.1.55 PVC—Port Virtual Channel Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 10Ch–10Dh Default Value: 0000h Bit 15:4 3:1 Reserved. VC Arbitration Select (AS) — R/W. Indicates which VC should be programmed in the VC arbitration table. The root port takes no action on the setting of this field since there is no arbitration table. Load VC Arbitration Table (LAT) — R/W. Indicates that the table programmed should be loaded into the VC arbitration table. This bit always returns 0 when read. Attribute: Size: Description R/W 16 bits 0 756 Datasheet PCI Express* Configuration Registers 20.1.56 PVS—Port Virtual Channel Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 10Eh–10Fh Default Value: 0000h Bit 15:1 0 Reserved. VC Arbitration Table Status (VAS) — RO. Indicates the coherency status of the VC Arbitration table when it is being updated. This field is always 0 in the root port since there is no VC arbitration table. Attribute: Size: Description RO 16 bits 20.1.57 V0CAP—Virtual Channel 0 Resource Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 110h–113h Default Value: 00000001h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: Description RO 32 bits Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table since the arbitration is fixed. Reserved. Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration; therefore, this field is not used. Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable transactions. Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not just advanced packet switching transactions. Reserved. Port Arbitration Capability (PAC) — RO. Indicates that this VC uses fixed port arbitration. Datasheet 757 PCI Express* Configuration Registers 20.1.58 V0CTL—Virtual Channel 0 Resource Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 114h–117h Default Value: 800000FFh Bit 31 30:27 26:24 23:20 19:17 Attribute: Size: Description R/W, RO 32 bits Virtual Channel Enable (EN) — RO. Always set to 1. Virtual Channel 0 cannot be disabled. Reserved. Virtual Channel Identifier (VCID) — RO. Indicates the ID to use for this virtual channel. Reserved. Port Arbitration Select (PAS) — R/W. Indicates which port table is being programmed. The root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. Load Port Arbitration Table (LAT) — RO. The root port does not implement an arbitration table for this virtual channel. Reserved. Transaction Class / Virtual Channel Map (TVM) — R/W. Indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. Bit 7 6 Transaction Class Transaction Class 7 Transaction Class 6 Transaction Class 5 Transaction Class 4 Transaction Class 3 Transaction Class 2 Transaction Class 1 16 15:8 7:1 5 4 3 2 1 0 Reserved. Transaction class 0 must always mapped to VC0. 20.1.59 V0STS—Virtual Channel 0 Resource Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 11Ah–11Bh Default Value: 0000h Bit 15:2 1 Reserved. VC Negotiation Pending (NP) — RO. 0 = Negotiation is not pending. 1 = Indicates the Virtual Channel is still being negotiated with ingress ports. 0 Port Arbitration Tables Status (ATS). There is no port arbitration table for this VC, so this bit is reserved as 0. Attribute: Size: Description RO 16 bits 758 Datasheet PCI Express* Configuration Registers 20.1.60 UES—Uncorrectable Error Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 144h–147h Default Value: 00000000000x0xxx0x0x0000000x0000b Attribute: Size: R/WC, RO 32 bits This register maintains its state through a platform reset. It loses its state upon suspend. Bit 31:21 20 19 18 17 16 15 14 Reserved Unsupported Request Error Status (URE) — R/WC. Indicates an unsupported request was received. ECRC Error Status (EE) — RO. ECRC is not supported. Malformed TLP Status (MT) — R/WC. Indicates a malformed TLP was received. Receiver Overflow Status (RO) — R/WC. Indicates a receiver overflow occurred. Unexpected Completion Status (UC) — R/WC. Indicates an unexpected completion was received. Completion Abort Status (CA) — R/WC. Indicates a completer abort was received. Completion Timeout Status (CT) — R/WC. Indicates a completion timed out. This bit is set if Completion Timeout is enabled and a completion is not returned within the time specified by the Completion TImeout Value Flow Control Protocol Error Status (FCPE) — RO. Flow Control Protocol Errors not supported. Poisoned TLP Status (PT) — R/WC. Indicates a poisoned TLP was received. Reserved Data Link Protocol Error Status (DLPE) — R/WC. Indicates a data link protocol error occurred. Reserved Training Error Status (TE) — RO. Training Errors not supported. Description 13 12 11:5 4 3:1 0 Datasheet 759 PCI Express* Configuration Registers 20.1.61 UEM—Uncorrectable Error Mask (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 148h–14Bh Default Value: 00000000h Attribute: Size: R/WO, RO 32 bits When set, the corresponding error in the UES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:21 Reserved Unsupported Request Error Mask (URE) — R/WO. 20 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. 19 ECRC Error Mask (EE) — RO. ECRC is not supported. Malformed TLP Mask (MT) — R/WO. 18 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Receiver Overflow Mask (RO) — R/WO. 17 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Unexpected Completion Mask (UC) — R/WO. 16 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Completion Abort Mask (CA) — R/WO. 15 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Completion Timeout Mask (CT) — R/WO. 14 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. 13 Flow Control Protocol Error Mask (FCPE) — RO. Flow Control Protocol Errors not supported. Poisoned TLP Mask (PT) — R/WO. 12 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. 11:5 Reserved Description 760 Datasheet PCI Express* Configuration Registers Bit Description Data Link Protocol Error Mask (DLPE) — R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. 4 3:1 0 Reserved Training Error Mask (TE) — RO. Training Errors not supported 20.1.62 UEV — Uncorrectable Error Severity (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 14Ch–14Fh Default Value: 00060011h Bit 31:21 20 19 18 Reserved Unsupported Request Error Severity (URE) — RO. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. ECRC Error Severity (EE) — RO. ECRC is not supported. Malformed TLP Severity (MT) — RO. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) Receiver Overflow Severity (RO) — RO. 17 0 = Error considered non-fatal. 1 = Error is fatal. (Default) Unexpected Completion Severity (UC) — RO. 16 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Completion Abort Severity (CA) — RO. 15 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Completion Timeout Severity (CT) — RO. 14 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Flow Control Protocol Error Severity (FCPE) — RO. Flow Control Protocol Errors not supported. Poisoned TLP Severity (PT) — RO. 12 11:5 4 3:1 0 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Reserved Data Link Protocol Error Severity (DLPE) — RO. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) Reserved Training Error Severity (TE) — RO. TE is not supported. Attribute: Size: Description RO 32 bits 13 Datasheet 761 PCI Express* Configuration Registers 20.1.63 CES — Correctable Error Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 150h–153h Default Value: 00000000h Bit 31:14 13 12 11:9 8 7 6 5:1 0 Reserved Advisory Non-Fatal Error Status (ANFES) — R/WC. 0 = Advisory Non-Fatal Error did not occur. 1 = Advisory Non-Fatal Error did occur. Replay Timer Timeout Status (RTT) — R/WC. Indicates the replay timer timed out. Reserved Replay Number Rollover Status (RNR) — R/WC. Indicates the replay number rolled over. Bad DLLP Status (BD) — R/WC. Indicates a bad DLLP was received. Bad TLP Status (BT) — R/WC. Indicates a bad TLP was received. Reserved Receiver Error Status (RE) — R/WC. Indicates a receiver error occurred. Attribute: Size: Description R/WC 32 bits 20.1.64 CEM — Correctable Error Mask Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 154h–157h Default Value: 00000000h Attribute: Size: R/WO 32 bits When set, the corresponding error in the CES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:14 Reserved Advisory Non-Fatal Error Mask (ANFEM) — R/WO. 0 = Does not mask Advisory Non-Fatal errors. 13 1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control register and (b) updating the Uncorrectable Error Status register. This register is set by default to enable compatibility with software that does not comprehend Role-Based Error Reporting. NOTE: The correctable error detected bit in device status register is set whenever the Advisory Non-Fatal error is detected, independent of this mask bit. Replay Timer Timeout Mask (RTT) — R/WO. Mask for replay timer timeout. Reserved Replay Number Rollover Mask (RNR) — R/WO. Mask for replay number rollover. Bad DLLP Mask (BD) — R/WO. Mask for bad DLLP reception. Bad TLP Mask (BT) — R/WO. Mask for bad TLP reception. Reserved Receiver Error Mask (RE) — R/WO. Mask for receiver errors. Description 12 11:9 8 7 6 5:1 0 762 Datasheet PCI Express* Configuration Registers 20.1.65 AECC — Advanced Error Capabilities and Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 158h–15Bh Default Value: 00000000h Bit 31:9 8 7 6 5 4:0 Reserved ECRC Check Enable (ECE) — RO. ECRC is not supported. ECRC Check Capable (ECC) — RO. ECRC is not supported. ECRC Generation Enable (EGE) — RO. ECRC is not supported. ECRC Generation Capable (EGC) — RO. ECRC is not supported. First Error Pointer (FEP) — RO. Attribute: Size: Description RO 32 bits 20.1.66 RES — Root Error Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 170h–173h Default Value: 00000000h Bit 31:27 26:4 3 Attribute: Size: Description R/WC, RO 32 bits Advanced Error Interrupt Message Number (AEMN) — RO. There is only one error interrupt allocated. Reserved Multiple ERR_FATAL/NONFATAL Received (MENR) — RO. For Intel® ICH10, only one error will be captured. ERR_FATAL/NONFATAL Received (ENR) — R/WC. 0 = No error message received. 1 = Either a fatal or a non-fatal error message is received. Multiple ERR_COR Received (MCR) — RO. For ICH10, only one error will be captured. ERR_COR Received (CR) — R/WC. 0 = No error message received. 1 = A correctable error message is received. 2 1 0 20.1.67 RCTCL — Root Complex Topology Capability List Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 180–183h Default Value: 00010005h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32 bits Next Capability (NEXT) — RO. Indicates the next item in the list, in this case, end of list. Capability Version (CV) — RO. Indicates the version of the capability structure. Capability ID (CID) — RO. Indicates this is a root complex topology capability. Datasheet 763 PCI Express* Configuration Registers 20.1.68 ESD—Element Self Description Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 184h–187h Default Value: See Description Bit Attribute: Size: Description RO 32 bits Port Number (PN) — RO. Indicate the ingress port number for the root port. There is a different value per port: Port # 1 31:24 2 3 4 5 6 Value 01h 02h 03h 04h 05h 06h 23:16 Component ID (CID) — RO. This field returns the value of the ESD.CID field (Chipset Config Space: Offset 0104h:bits 23:16) of the chip configuration section, that is programmed by platform BIOS, since the root port is in the same component as the RCRB. Number of Link Entries (NLE) — RO. The default value of 01h indicates one link entry (corresponding to the RCRB). Reserved. Element Type (ET) — RO. The default value of 0h indicates that the element type is a root port. 15:8 7:4 3:0 20.1.69 ULD — Upstream Link Description Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 190h–193h Default Value: 00000001h Bit 31:24 Attribute: Size: Description RO 32 bits Target Port Number (PN) — RO. Indicates the port number of the RCRB. Target Component ID (TCID) — RO. This field returns the value of the ESD.CID field (Chipset Config Space: Offset 0104h:bits 23:16) of the chip configuration section, that is programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved. Link Type (LT) — RO. Indicates that the link points to the Intel® ICH10 RCRB. Link Valid (LV) — RO. Indicates that this link entry is valid. 23:16 15:2 1 0 764 Datasheet PCI Express* Configuration Registers 20.1.70 ULBA — Upstream Link Base Address Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 198h–19Fh Default Value: See Description Bit 63:32 31:0 Attribute: Size: Description RO 64 bits Base Address Upper (BAU) — RO. The RCRB of the Intel® ICH10 lives in 32-bit space. Base Address Lower (BAL) — RO. This field matches the RCBA register (D31:F0:Offset F0h) value in the LPC bridge. 20.1.71 PECR2 — PCI Express* Configuration Register 2 (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 300-303h Default Value: 60005007h Bit 31:20 21 20:0 Reserved PECR2 Field 1 — R/W. BIOS must set this bit to 1b. Reserved Attribute: Size: Description R/W 32 bits 20.1.72 PEETM — PCI Express* Extended Test Mode Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 318h Default Value: See Description Bit 7:3 Reserved Scrambler Bypass Mode (BAU) — R/W. 0 = Normal operation. Scrambler and descrambler are used. 2 1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in the receive direction. NOTE: This functionality intended for debug/testing only. NOTE: If bypassing scrambler with ICH10 root port 1 in x4 configuration, each ICH10 root port must have this bit set. Reserved Attribute: Size: Description RO 8 bits 1:0 Datasheet 765 PCI Express* Configuration Registers 20.1.73 PEC1 — PCI Express* Configuration Register 1 (PCI Express—D28:F0/F1/F2/F3/F4/F5) Address Offset: 324h Default Value: 14000016h Bit 31:8 7:0 Reserved PEC1 Field 1 — R/W. BIOS must program this field to 40h. Attribute: Size: Description RO, R/W 32 bits §§ 766 Datasheet High Precision Event Timer Registers 21 High Precision Event Timer Registers The timer registers are memory-mapped in a non-indexed scheme. This allows the processor to directly access each register without having to use an index register. The timer register space is 1024 bytes. The registers are generally aligned on 64-bit boundaries to simplify implementation with IA64 processors. There are four possible memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3) FED0_2000h, 4) FED0_3000h. The choice of address range will be selected by configuration bits in the High Precision Timer Configuration Register (Chipset Config Registers:Offset 3404h). Behavioral Rules: 1. Software must not attempt to read or write across register boundaries. For example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh. Any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. However, these accesses should not result in system hangs. 64bit accesses can only be to x0h and must not cross 64-bit boundaries. 2. Software should not write to read-only registers. 3. Software should not expect any particular or consistent value when reading reserved registers or bits. 21.1 Memory Mapped Registers Table 21-1. Memory-Mapped Registers (Sheet 1 of 2) Offset 000–007h 008–00Fh 010–017h 018–01Fh 020–027h 028–0EFh 0F0–0F7h 0F8–0FFh 100–107h 108–10Fh 110–11Fh 120–127h Mnemonic GCAP_ID — GEN_CONF — GINTR_STA — MAIN_CNT — TIM0_CONF TIM0_COMP — TIM1_CONF Register General Capabilities and Identification Reserved General Configuration Reserved General Interrupt Status Reserved Main Counter Value Reserved Timer 0 Configuration and Capabilities Timer 0 Comparator Value Reserved Timer 1 Configuration and Capabilities Default 0429B17F8 086A201h — 00000000 00000000h — 00000000 00000000h — N/A — N/A N/A — N/A Type RO — R/W — R/WC, R/ W — R/W — R/W, RO R/W — R/W, RO Datasheet 767 High Precision Event Timer Registers Table 21-1. Memory-Mapped Registers (Sheet 2 of 2) Offset 128–12Fh 130–13Fh 140–147h 148–14Fh 150–15Fh 160–167h 168–16Fh 170–3FFh (Consumer Only) 180–187h (Corporate Only) 188–18Fh (Corporate Only) 190–19Fh (Corporate Only) 1A0–1A7h (Corporate Only) 1A8–1AFh (Corporate Only) 1B0–1BFh (Corporate Only) 1C0–1C7h (Corporate Only) 1C8–1CFh (Corporate Only) 1D0–1DFh (Corporate Only) 1E0–1E7h (Corporate Only) 1E8–1EFh (Corporate Only) 1F0–19Fh (Corporate Only) 200–3FFh (Corporate Only) Mnemonic TIM1_COMP — TIM2_CONF TIM2_COMP — TIM3_CONG TIM3_COMP — TIM4_CONG TIM4_COMP — TIM5_CONG TIM5_COMP — TIM6_CONG TIM6_COMP — TIM7_CONG TIM7_COMP — — Register Timer 1 Comparator Value Reserved Timer 2 Configuration and Capabilities Timer 2 Comparator Value Reserved Timer 3 Configuration and Capabilities Timer 3 Comparator Value Reserved Timer 4 Configuration and Capabilities Timer 4 Comparator Value Reserved Timer 5 Configuration and Capabilities Timer 5 Comparator Value Reserved Timer 6 Configuration and Capabilities Timer 6 Comparator Value Reserved Timer 7 Configuration and Capabilities Timer 7 Comparator Value Reserved Reserved Default N/A — N/A N/A — N/A N/A — N/A N/A — N/A N/A — N/A N/A — N/A N/A — — Type R/W — R/W, RO R/W — R/W, RO R/W — R/W, RO R/W — R/W, RO R/W — R/W, RO R/W — R/W, RO R/W — — NOTES: 1. Reads to reserved registers or bits will return a value of 0. 2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision Event Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur. 768 Datasheet High Precision Event Timer Registers 21.1.1 GCAP_ID—General Capabilities and Identification Register Address Offset: 00h Default Value: 0429B17F8086A201h Bit Attribute: Size: Description RO 64 bits 63:32 Main Counter Tick Period (COUNTER_CLK_PER_CAP) — RO. This field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). This will return 0429B17F when read. This indicates a period of 69841279 fs (69.841279 ns). Vendor ID Capability (VENDOR_ID_CAP) — RO. This is a 16-bit value assigned to Intel. Legacy Replacement Rout Capable (LEG_RT_CAP) — RO. Hardwired to 1. Legacy Replacement Interrupt Rout option is supported. Reserved. This bit returns 0 when read. Counter Size Capability (COUNT_SIZE_CAP) — RO. Hardwired to 1. Counter is 64-bit wide. Number of Timer Capability (NUM_TIM_CAP) — RO. This field indicates the number of timers in this block. 03h = Four timers. (Consumer Only) 07h = Eight timers. (Corporate Only) Revision Identification (REV_ID) — RO. This indicates which revision of the function is implemented. Default value will be 01h. 31:16 15 14 13 12:8 7:0 Datasheet 769 High Precision Event Timer Registers 21.1.2 GEN_CONF—General Configuration Register Address Offset: 010h Default Value: 00000000 00000000h Bit 63:2 Attribute: Size: Description R/W 64 bits Reserved. These bits return 0 when read. Legacy Replacement Rout (LEG_RT_CNF) — R/W. If the ENABLE_CNF bit and the LEG_RT_CNF bit are both set, then the interrupts will be routed as follows: • Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC • Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC • Timer 2-n is routed as per the routing in the timer n config registers. 1 • If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC) will have no impact. • If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers are used. • This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to disable the legacy replacement routing. Overall Enable (ENABLE_CNF) — R/W. This bit must be set to enable any of the timers to generate interrupts. If this bit is 0, then the main counter will halt (will not increment) and no interrupts will be caused by any of these timers. For level-triggered interrupts, if an interrupt is pending when the ENABLE_CNF bit is changed from 1 to 0, the interrupt status indications (in the various Txx_INT_STS bits) will not be cleared. Software must write to the Txx_INT_STS bits to clear the interrupts. NOTE: This bit will default to 0. BIOS can set it to 1 or 0. 0 21.1.3 GINTR_STA—General Interrupt Status Register Address Offset: 020h Default Value: 00000000 00000000h Attribute: Size: Description Reserved. These bits will return 0 when read. Timer 7Interrupt Active (T07_INT_STS) — R/W. Same functionality as Timer 0. Timer 6Interrupt Active (T06_INT_STS) — R/W. Same functionality as Timer 0. Timer 5Interrupt Active (T05_INT_STS) — R/W. Same functionality as Timer 0. Timer 4Interrupt Active (T04_INT_STS) — R/W. Same functionality as Timer 0. R/W, R/WC 64 bits . Bit 63:8 7 (Corporate Only) 6 (Corporate Only) 5 (Corporate Only) 4 (Corporate Only) 7:4 (Consumer Only) 3 Reserved. These bits will return 0 when read. Timer 3Interrupt Active (T03_INT_STS) — R/W. Same functionality as Timer 0. 770 Datasheet High Precision Event Timer Registers Bit 2 1 Description Timer 2 Interrupt Active (T02_INT_STS) — R/W. Same functionality as Timer 0. Timer 1 Interrupt Active (T01_INT_STS) — R/W. Same functionality as Timer 0. Timer 0 Interrupt Active (T00_INT_STS) — R/WC. The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer. (default = 0) If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. If set to edge-triggered mode: This bit should be ignored by software. Software should always write 0 to this bit. NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes will have no effect. 0 21.1.4 MAIN_CNT—Main Counter Value Register Address Offset: 0F0h Default Value: N/A Attribute: Size: Description Counter Value (COUNTER_VAL[63:0]) — R/W. Reads return the current value of the counter. Writes load the new value to the counter. NOTES: 1. Writes to this register should only be done while the counter is halted. 2. Reads to this register return the current value of the main counter. 3. 32-bit counters will always return 0 for the upper 32-bits of this register. 4. If 32-bit software attempts to read a 64-bit counter, it should first halt the counter. Since this delays the interrupts for all of the timers, this should be done only if the consequences are understood. It is strongly recommended that 32-bit software only operate the timer in 32-bit mode. 5. Reads to this register are monotonic. No two consecutive reads return the same value. The second of two reads always returns a larger value (unless the timer has rolled over to 0). R/W 64 bits . Bit 63:0 Datasheet 771 High Precision Event Timer Registers 21.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register Address Offset: Timer Timer Timer Timer Timer Timer Timer Timer Default Value: N/A 0: 1: 2: 3: 4: 5: 6: 7: 100–107h Attribute: 120–127h 140–147h 160–167h 180–187h (Corporate Only) 1A0–1A7h (Corporate Only) 1C0–1C7h (Corporate Only) 1E0–1E7h (Corporate Only) Size: RO, R/W 64 bit Note: The letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 (4, 5, 6, 7 Corporate Only) referring to Timer 0, 1, 2, 3, 4, 5, 6, or 7(4,5,6,7 Corporate Only). Bit 63:56 Description Reserved. These bits will return 0 when read. Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) — RO. Timer 0, 1: Bits 52, 53, 54, and 55 in this field (corresponding to IRQ 20, 21, 22, and 23) have a value of 1. Writes will have no effect. Timer 2: Timer 3: Bits 43, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22, and 23) have a value of 1. Writes will have no effect. Bits 44, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22, and 23) have a value of 1. Writes will have no effect. 55:52, 43 Timer 4, 5, 6, 7 (Corporate Only). This field is always 0 as interrupts from these timers can only be delivered via direct FSB interrupt messages. NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to ensure the proper operation of HPET #2. NOTE: If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other devices to ensure the proper operation of HPET #3. 51:45, 42:16 15 (Corporate Only) 15 (Consumer Only) Reserved. These bits return 0 when read. TIMERn_FSB_INT_DEL_CAP: FSB Interrupt Delivery: (where n is the timer number: 00 to 07). If this read-only bit is 1, then the hardware supports a direct front-side bus delivery of this timer’s interrupt. Intel Specific: This bit is always read as 1, since the Intel ICH10 HPET implementation supports the direct FSB interrupt delivery. Reserved. This bit returns 0 when read. TIMERn_FSB_EN_CNF: (where n is the timer number: 00 to 07). If the TIMERn_FSB_INT_DEL_CAP bit is set for this timer, then the software can set the TIMERn_FSB_EN_CNF bit to force the interrupts to be delivered directly as FSB messages, rather than using the 8259 or I/O (x) APIC. In this case, the TIMERn_INT_ROUT_CNF field in this register will be ignored. The TIMERn_FSB_ROUT register will be used instead. Intel and Timer 0, 1, 2, 3 Specific: This bit is a read/write bit. Intel and Timer 4, 5, 6, 7 Specific: This bit is always Read Only 1 as interrupt from these timers can only be delivered via direct FSB interrupt messages. 14 (Consumer Only) Reserved. This bit returns 0 when read. 14 (Corporate Only) 772 Datasheet High Precision Event Timer Registers Bit Description Interrupt Rout (TIMERn_INT_ROUT_CNF) — R/W. This 5-bit field indicates the routing for the interrupt to the 8259 or I/O (x) APIC. Software writes to this field to select which interrupt in the 8259 or I/O (x) will be used for this timer’s interrupt. If the value is not supported by this particular timer, then the value read back will not match what is written. The software must only write valid values. Timer 4, 5, 6, 7 (corporate Only): This field is Read-only and reads will return 0. NOTES: 1. If the interrupt is handled via the 8259, only interrupts 0-15 are applicable and valid. Software must not program any value other than 0-15 in this field. 2. If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. 3. Timer 0,1: Software is responsible to make sure it programs a valid value (20, 21, 22, or 23) for this field. The ICH10 logic does not check the validity of the value written. 4. Timer 2: Software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23) for this field. The ICH10 logic does not check the validity of the value written. 5. Timer 3: Software is responsible to make sure it programs a valid value (12, 20, 21, 22, or 23) for this field. The ICH10 logic does not check the validity of the value written. Timer n 32-bit Mode (TIMERn_32MODE_CNF) — R/W or RO. Software can set this bit to force a 64-bit timer to behave as a 32-bit timer. Timer 0: Bit is read/write (default to 0). 0 = 64 bit; 1 = 32 bit Timers 1, 2, 3, 4, 5, 6, 7 (4, 5, 6, 7 Corporate Only): Hardwired to 0. Writes have no effect (since these two timers are 32-bits). NOTE: When this bit is set to 1, the hardware counter will do a 32-bit operation on comparator match and rollovers, thus the upper 32-bit of the Timer 0 Comparator Value register is ignored. The upper 32-bit of the main counter is not involved in any rollover from lower 32-bit of the main counter and becomes all zeros. 13:9 8 7 Reserved. This bit returns 0 when read. Timer n Value Set (TIMERn_VAL_SET_CNF) — R/W. Software uses this bit only for Timer 0 if it has been set to periodic mode. By writing this bit to a 1, the software is then allowed to directly set the timer’s accumulator. Software does not have to write this bit back to 1 (it automatically clears). 6 Software should not write a 1 to this bit position if the timer is set to non-periodic mode. NOTE: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it is set to periodic mode. Writes will have no effect for Timers 1, 2, 3, 4, 5, 6, 7 (4, 5, 6, 7 Corporate Only). Timer n Size (TIMERn_SIZE_CAP) — RO. This read only field indicates the size of the timer. Timer 0: Value is 1 (64-bits). Timers 1, 2, 3, 4, 5, 6, 7 (4, 5, 6, 7 Corporate Only): Value is 0 (32-bits). Periodic Interrupt Capable (TIMERn_PER_INT_CAP) — RO. If this bit is 1, the hardware supports a periodic mode for this timer’s interrupt. 5 4 Timer 0: Hardwired to 1 (supports the periodic interrupt). Timers 1, 2, 3, 4, 5, 6, 7 (4, 5, 6, 7 Corporate Only): Hardwired to 0 (does not support periodic interrupt). Datasheet 773 High Precision Event Timer Registers Bit Description Timer n Type (TIMERn_TYPE_CNF) — R/W or RO. Timer 0: Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 = Enable timer to generate a periodic interrupt. Timers 1, 2, 3, 4, 5, 6, 7 (4, 5, 6, 7 Corporate Only): Hardwired to 0. Writes have no affect. Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) — R/W. This bit must be set to enable timer n to cause an interrupt when it times out. 3 2 0 = Disable (Default). The timer can still count and generate appropriate status bits, but will not cause an interrupt. 1 = Enable. Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W. 0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is generated. If another interrupt occurs, another edge will be generated. 1 = The timer interrupt is level triggered. This means that a level-triggered interrupt is generated. The interrupt will be held active until it is cleared by writing to the bit in the General Interrupt Status Register. If another interrupt occurs before the interrupt is cleared, the interrupt will remain active. Timer 4, 5, 6, 7 (4, 5, 6, 7 Corporate Only): This bit is Read-Only, and will return 0 when read 1 0 Reserved. These bits will return 0 when read. NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any unimplemented registers will return an undetermined value. 774 Datasheet High Precision Event Timer Registers 21.1.6 TIMn_COMP—Timer n Comparator Value Register Address Offset: Timer Timer Timer Timer Timer Timer Timer Timer Attribute: Default Value: Bit 0: 1: 2: 3: 4: 5: 6: 7: 108h–10Fh 128h–12Fh 148h–14Fh 168h–16Fh 188h – 18Fh (Corporate Only) 1A8h – 1AFh (Corporate Only) 1C8h – 1CFh (Corporate Only) 1E8h – 1EFh (Corporate Only) Size: Description R/W N/A 64 bit Timer Compare Value — R/W. Reads to this register return the current value of the comparator Timers 0, 1, 2, 3, 4, 5, 6, 7 (4, 5, 6, 7 Corporate Only) are configured to non-periodic mode: Writes to this register load the value against which the main counter should be compared for this timer. • When the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). • The value in this register does not change based on the interrupt being generated. Timer 0 is configured to periodic mode: • When the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). • After the main counter equals the value in this register, the value in this register is increased by the value last written to the register. 63:0 For example, if the value written to the register is 00000123h, then 1. 2. 3. 4. An interrupt will be generated when the main counter reaches 00000123h. The value in this register will then be adjusted by the hardware to 00000246h. Another interrupt will be generated when the main counter reaches 00000246h The value in this register will then be adjusted by the hardware to 00000369h • As each periodic interrupt occurs, the value in this register will increment. When the incremented value is greater than the maximum value possible for this register (FFFFFFFFh for a 32-bit timer or FFFFFFFFFFFFFFFFh for a 64-bit timer), the value will wrap around through 0. For example, if the current value in a 32-bit timer is FFFF0000h and the last value written to this register is 20000, then after the next interrupt the value will change to 00010000h Default value for each timer is all 1s for the bits that are implemented. For example, a 32-bit timer has a default value of 00000000FFFFFFFFh. A 64-bit timer has a default value of FFFFFFFFFFFFFFFFh. §§ Datasheet 775 High Precision Event Timer Registers 776 Datasheet Serial Peripheral Interface (SPI) 22 Serial Peripheral Interface (SPI) The Serial Peripheral Interface resides in memory mapped space. This function contains registers that allow for the setup and programming of devices that reside on the SPI interface. Note: All registers in this function (including memory-mapped registers) must be addressable in byte, word, and dword quantities. The software must always make register accesses on natural boundaries (i.e., DWord accesses must be on dword boundaries; word accesses on word boundaries, etc.) In addition, the memory-mapped register space must not be accessed with the LOCK semantic exclusive-access mechanism. If software attempts exclusive-access mechanisms to the SPI memory-mapped space, the results are undefined. 22.1 Serial Peripheral Interface Memory Mapped Configuration Registers The SPI Host Interface registers are memory-mapped in the RCRB (Root Complex Register Block) Chipset Register Space with a base address (SPIBAR) of 3800h and are located within the range of 3800h to 39FFh. The address for RCRB can be found in RCBA Register see Section 13.1.36. The individual registers are then accessible at SPIBAR + Offset as indicated Table 22-1. These memory mapped registers must be accessed in byte, word, or dword quantities. Table 22-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) (Sheet 1 of 2) SPIBAR + Offset 00h–03h 04h–05h 06h–07h 08h–0Bh 0Ch–0Fh 10h–13h 14h–4Fh 50h–53h 54h–57h 58h–5Bh 5Ch–5F 60h–63h 64h–67h 67h–73h Mnemonic BFPR HSFSTS HSFCTL FADDR Reserved FDATA0 FDATAN FRACC FREG0 FREG1 FREG2 FREG3 FREG3 Reserved Register Name BIOS Flash Primary Region Hardware Sequencing Flash Status Hardware Sequencing Flash Control Flash Address Reserved Flash Data 0 Flash Data N Flash Region Access Permissions Flash Region 0 Flash Region 1 Flash Region 2 Flash Region 3 Flash Region 4 Reserved for Future Flash Regions Default 00000000h 0000h 0000h 00000000h 00000000h 00000000h 00000000h 00000202h 00000000h 00000000h 00000000h 00000000h 00000000h R/W R/W RO, R/W RO RO RO RO RO Type RO RO, R/WC, R/W R/W, R/WS R/W Datasheet 777 Serial Peripheral Interface (SPI) Table 22-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) (Sheet 2 of 2) SPIBAR + Offset 74h–77h 78h–7Bh 7Ch–7Fh 80–83h 84h–87h 88h–8Fh 90h 91h–93h 94h–95h 96h–97h 98h–9Fh A0h B0h–B3h B4h–B7h B8h–C3h C0h–C3h C4–C7h C8–C11h D0–D3h Mnemonic FPR0 FPR1 FPR2 FPR3 FPR4 — SSFSTS SSFCTL PREOP OPTYPE OPMENU BBAR FDOC FDOD — AFC LVSCC UVSCC FPB Register Name Flash Protected Range 0 Flash Protected Range 1 Flash Protected Range 2 Flash Protected Range 3 Flash Protected Range 4 Reserved Software Sequencing Flash Status Software Sequencing Flash Control Prefix Opcode Configuration Opcode Type Configuration Opcode Menu Configuration BIOS Base Address Configuration Flash Descriptor Observability Control Flash Descriptor Observability Data Reserved Additional Flash Control Host Lower Vendor Specific Component Capabilities Host Upper Vendor Specific Component Capabilities Flash Partition Boundary Default 00000000h 00000000h 00000000h 00000000h 00000000h — 00h 0000h 0000h 0000h 00000000 00000000h 00000000h 00000000h 00000000h — 00000000h 00000000h 00000000h 00000000h RO, R/W RO, R/WL RO, R/WL RO RO, R/WC R/W R/W R/W R/W R/W, RO R/W RO Type R/W R/W R/W R/W R/W 778 Datasheet Serial Peripheral Interface (SPI) 22.1.1 BFPR –BIOS Flash Primary Region Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 00h 00000000h Attribute: Size: RO 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit 31:29 Reserved BIOS Flash Primary Region Limit (PRL) — RO. This specifies address bits 24:12 for the Primary Region Limit. The value in this register loaded from the contents in the Flash Descriptor.FLREG1.Region Limit. Reserved BIOS Flash Primary Region Base (PRB) — RO. This specifies address bits 24:12 for the Primary Region Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base. Description 28:16 15:13 12:0 22.1.2 HSFS—Hardware Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Bit SPIBAR + 04h 0000h Attribute: Size: Description RO, R/WC, R/W 16 bits 15 Flash Configuration Lock-Down (FLOCKDN) — R/W/L. When set to 1, those Flash Program Registers that are locked down by this FLOCKDN bit cannot be written. Once set to 1, this bit can only be cleared by a hardware reset due to a global reset or host partition reset in an Intel ME enabled system. Flash Descriptor Valid (FDV) — RO. This bit is set to a 1 if the Flash Controller read the correct Flash Descriptor Signature. 14 If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing registers, but must use the software sequencing registers. Any attempt to use the Hardware Sequencing registers will result in the FCERR bit being set. Flash Descriptor Override Pin-Strap Status (FDOPSS) — RO: This register reflects the value the Flash Descriptor Override Pin-Strap. 0 = The Flash Descriptor Override strap is set 1 = No override Reserved SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0. NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. 13 12:6 5 Datasheet 779 Serial Peripheral Interface (SPI) Bit Description Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sector size for all Flash components. Valid Bit Settings: 00 = 256 Byte 01 = 4 K Byte 10 = 8 K Byte 11 = 64 K Byte If the FLA is less than FPBA then this field reflects the value in the LVSCC.LBES register. If the FLA is greater or equal to FPBA then this field reflects the value in the UVSCC.UBES register. NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. Access Error Log (AEL) — R/W/C. Hardware sets this bit to a 1 when an attempt was made to access the BIOS region using the direct access method or an access to the BIOS Program Registers that violated the security restrictions. This bit is simply a log of an access security violation. This bit is cleared by software writing a 1. NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program register access is blocked to the FLASH due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or until hardware reset occurs due to a global reset or host partition reset in an Intel ME enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in this register. NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. Flash Cycle Done (FDONE) — R/W/C. The ICH sets this bit to 1 when the SPI Cycle completes after software previously set the FGO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. 4:3 2 1 0 780 Datasheet Serial Peripheral Interface (SPI) 22.1.3 HSFC—Hardware Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 06h 0000h Attribute: Size: R/W, R/WS 16 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit 15 14 Description Flash SPI SMI# Enable (FSMIE) — R/W. When set to 1, the SPI asserts an SMI# request whenever the Flash Cycle Done bit is 1. Reserved Flash Data Byte Count (FDBC) — R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The contents of this register are 0s based with 0b representing 1 byte and 111111b representing 64 bytes. The number of bytes transferred is the value of this field plus 1. This field is ignored for the Block Erase command. 7:3 Reserved FLASH Cycle (FCYCLE) — R/W. This field defines the Flash SPI cycle type generated to the FLASH when the FGO bit is set as defined below: 2:1 00 = Read (1 up to 64 bytes by setting FDBC) 01 = Reserved 10 = Write (1 up to 64 bytes by setting FDBC) 11 = Block Erase Flash Cycle Go (FGO) — R/W/S. A write to this register with a 1 in this bit initiates a request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the cycle is complete, the FDONE bit is set. 0 Software is forbidden to write to any register in the HSFLCTL register between the FGO bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be ignored by hardware. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. This bit always returns 0 on reads. 13:8 22.1.4 FADDR—Flash Address Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:25 Reserved Flash Linear Address (FLA) — R/W. The FLA is the starting byte linear address of a SPI Read or Write cycle or an address within a Block for the Block Erase command. The Flash Linear Address must fall within a region for which BIOS has access permissions. Hardware must convert the FLA into a Flash Physical Address (FPA) before running this cycle on the SPI bus. SPIBAR + 08h 00000000h Attribute: Size: Description R/W 32 bits 24:0 Datasheet 781 Serial Peripheral Interface (SPI) 22.1.5 FDATA0—Flash Data 0 Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Bit SPIBAR + 10h 00000000h Attribute: Size: Description R/W 32 bits Flash Data 0 (FD0) — R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In Data pin during the data portion of the SPI cycle. This register also shifts in the data from the Master-In Slave-Out pin into this register during the data portion of the SPI cycle. 31:0 The data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24 Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always represents the value specified by the cycle address. Note that the data in this register may be modified by the hardware during any programmed SPI transaction. Direct Memory Reads do not modify the contents of this register. 22.1.6 FDATAN—Flash Data [N] Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 14h SPIBAR + 18h SPIBAR + 1Ch SPIBAR + 20h SPIBAR + 24h SPIBAR + 28h SPIBAR + 2Ch SPIBAR + 30h SPIBAR + 34h SPIBAR + 38h SPIBAR + 3Ch SPIBAR + 40h SPIBAR + 44h SPIBAR + 48h SPIBAR + 4Ch 00000000h Attribute: R/W Default Value: Bit 31:0 Size: Description 32 bits Flash Data N (FD[N]) — R/W. Similar definition as Flash Data 0. However, this register does not begin shifting until FD[N-1] has completely shifted in/out.— R/W. 782 Datasheet Serial Peripheral Interface (SPI) 22.1.7 FRAP—Flash Regions Access Permissions Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 50h 00000202h Attribute: Size: RO, R/W 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit Description BIOS Master Write Access Grant (BMWAG) — R/W. Each bit [31:29] corresponds to Master[7:0]. BIOS can grant one or more masters write access to the BIOS region 1 overriding the permissions in the Flash Descriptor. Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is Host processor/GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit. BIOS Master Read Access Grant (BMRAG) — R/W. Each bit [28:16] corresponds to Master[7:0]. BIOS can grant one or more masters read access to the BIOS region 1 overriding the read permissions in the Flash Descriptor. Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is Host processor/GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit BIOS Region Write Access (BRWA) — RO. Each bit [15:8] corresponds to Regions [7:0]. If the bit is set, this master can erase and write that particular region through register accesses. 15:8 The contents of this register are that of the Flash Descriptor. Flash Master 1 Master Region Write Access OR a particular master has granted BIOS write permissions in their Master Write Access Grant register or the Flash Descriptor Security Override strap is set. BIOS Region Read Access (BRRA) — RO. Each bit [7:0] corresponds to Regions [7:0]. If the bit is set, this master can read that particular region through register accesses. 7:0 The contents of this register are that of the Flash Descriptor.Flash Master 1.Master Region Write Access OR a particular master has granted BIOS read permissions in their Master Read Access Grant register or the Flash Descriptor Security Override strap is set. 31:24 23:16 Datasheet 783 Serial Peripheral Interface (SPI) 22.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 54h 00000000h Attribute: Size: RO 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit 31:29 28:16 15:13 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Limit Reserved Region Base (RB) / Flash Descriptor Base Address Region (FDBAR) — RO. This specifies address bits 24:12 for the Region 0 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Base Description 12:0 22.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 58h 00000000h Attribute: Size: RO 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit 31:29 28:16 15:13 12:0 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 1 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Limit Reserved Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base Description 784 Datasheet Serial Peripheral Interface (SPI) 22.1.10 FREG2—Flash Region 2 (ME) Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 5Ch 00000000h Attribute: Size: RO 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit 31:29 28:16 15:13 12:0 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 2 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Limit Reserved Region Base (RB) — RO. This specifies address bits 24:12 for the Region 2 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Base Description 22.1.11 FREG3—Flash Region 3 (GbE) Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 60h 00000000h Attribute: Size: RO 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit 31:29 28:16 15:13 12:0 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 3 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Limit Reserved Region Base (RB) — RO. This specifies address bits 24:12 for the Region 3 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Base Description Datasheet 785 Serial Peripheral Interface (SPI) 22.1.12 FREG4—Flash Region 4 (Platform Data) Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 64h 00000000h Attribute: Size: RO 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit 31:29 28:16 15:13 12:0 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 4 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG4.Region Limit Reserved Region Base (RB) — RO. This specifies address bits 24:12 for the Region 4 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG4.Region Base Description 22.1.13 PR0—Protected Range 0 Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 74h 00000000h Attribute: Size: R/W 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Bit Description Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. 31 30:29 28:16 15 14:13 12:0 786 Datasheet Serial Peripheral Interface (SPI) 22.1.14 PR1—Protected Range 1 Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 78h 00000000h Attribute: Size: R/W 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Bit Description Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. 31 30:29 28:16 15 14:13 12:0 Datasheet 787 Serial Peripheral Interface (SPI) 22.1.15 PR2—Protected Range 2 Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 7Ch 00000000h Attribute: Size: R/W 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Bit Description Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. 31 30:29 28:16 15 14:13 12:0 22.1.16 PR3—Protected Range 3 Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 80h 00000000h Attribute: Size: R/W 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Bit Description Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. 31 30:29 28:16 15 14:13 12:0 788 Datasheet Serial Peripheral Interface (SPI) 22.1.17 PR4—Protected Range 4 Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 84h 00000000h Attribute: Size: R/W 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Bit Description Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. 31 30:29 28:16 15 14:13 12:0 Datasheet 789 Serial Peripheral Interface (SPI) 22.1.18 SSFS—Software Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 90h 00h Attribute: Size: RO, R/WC 8 bits Note: The Software Sequencing control and status registers are reserved if the hardware sequencing control and status registers are used. Bit 7:5 4 Reserved Access Error Log (AEL) — RO. This bit reflects the value of the Hardware Sequencing Status AEL register. Flash Cycle Error (FCERR) — R/WC. Hardware sets this bit to 1 when a programmed access is blocked from running on the SPI interface due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME enabled system. Cycle Done Status — R/WC. The ICH sets this bit to 1 when the SPI Cycle completes (i.e., SCIP bit is 0) after software sets the GO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. Reserved SPI Cycle In Progress (SCIP) — RO. Hardware sets this bit when software sets the SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0. Description 3 2 1 0 790 Datasheet Serial Peripheral Interface (SPI) 22.1.19 SSFC—Software Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 23:19 Reserved SPI Cycle Frequency (SCF) — R/W. This register sets frequency to use for all SPI software sequencing cycles (write, erase, fast read, read status, etc.) except for the read cycle which always run at 20 MHz. 18:16 000 = 20 MHz 001 = 33 MHz All other values reserved. This register is locked when the SPI Configuration Lock-Down bit is set. 15 SPI SMI# Enable (SME) — R/W. When set to 1, the SPI asserts an SMI# request whenever the Cycle Done Status bit is 1. Data Cycle (DS) — R/W. When set to 1, there is data that corresponds to this transaction. When 0, no data is delivered for this cycle, and the DBC and data fields themselves are don’t cares Data Byte Count (DBC) — R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The valid settings (in decimal) are any value from 0 to 63. The number of bytes transferred is the value of this field plus 1. Note that when this field is 00_0000b, then there is 1 byte to transfer and that 11_1111b means there are 64 bytes to transfer. 7 6:4 Reserved Cycle Opcode Pointer (COP) — R/W. This field selects one of the programmed opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic Cycle Sequence, this determines the second command. Sequence Prefix Opcode Pointer (SPOP) — R/W. This field selects one of the two programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes register. By making this programmable, the ICH supports flash devices that have different opcodes for enabling writes to the data space vs. status register. Atomic Cycle Sequence (ACS) — R/W. When set to 1 along with the SCGO assertion, the ICH10 will execute a sequence of commands on the SPI interface without allowing the LAN component to arbitrate and interleave cycles. The sequence is composed of: 2 • • • Atomic Sequence Prefix Command (8-bit opcode only) Primary Command specified below by software (can include address and data) Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b. SPIBAR + 91h 000000h Attribute: Size: Description R/W 24 bits 14 13:8 3 The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset until the Busy bit in the Flash Status Register returns 0. SPI Cycle Go (SCGO) — R/WS. This bit always returns 0 on reads. However, a write to this register with a 1 in this bit starts the SPI cycle defined by the other bits of this register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action. Hardware must ignore writes to this bit while the Cycle In Progress bit is set. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. 0 Reserved 1 Datasheet 791 Serial Peripheral Interface (SPI) 22.1.20 PREOP—Prefix Opcode Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 15:8 7:0 SPIBAR + 94h 0000h Attribute: Size: Description R/W 16 bits Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. NOTE: This register is not writable when the Flash Configuration Lock-Down bit (SPIBAR + 04h:15) is set. 22.1.21 OPTYPE—Opcode Type Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 96h 0000h Attribute: Size: R/W 16 bits Entries in this register correspond to the entries in the Opcode Menu Configuration register. Note: The definition below only provides write protection for opcodes that have addresses associated with them. Therefore, any erase or write opcodes that do not use an address should be avoided (for example, “Chip Erase” and “Auto-Address Increment Byte Program”) Bit 15:14 13:12 11:10 9:8 7:6 5:4 3:2 Description Opcode Type 7 — R/W. See the description for bits 1:0 Opcode Type 6 — R/W. See the description for bits 1:0 Opcode Type 5 — R/W. See the description for bits 1:0 Opcode Type 4 — R/W. See the description for bits 1:0 Opcode Type 3 — R/W. See the description for bits 1:0 Opcode Type 2 — R/W. See the description for bits 1:0 Opcode Type 1 — R/W. See the description for bits 1:0 Opcode Type 0 — R/W. This field specifies information about the corresponding Opcode 0. This information allows the hardware to 1) know whether to use the address field and 2) provide BIOS and Shared Flash protection capabilities. The encoding of the two bits is: 00 = No address associated with this Opcode; Read cycle type 01 = No address associated with this Opcode; Write cycle type 10 = Address required; Read cycle type 11 = Address required; Write cycle type NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. 1:0 792 Datasheet Serial Peripheral Interface (SPI) 22.1.22 OPMENU—Opcode Menu Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 98h 0000000000000000h Attribute: Size: R/W 64 bits Eight entries are available in this register to give BIOS a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. This keeps the hardware flexible enough to operate with a wide variety of SPI devices. Note: It is recommended that BIOS avoid programming Write Enable opcodes in this menu. Malicious software could then perform writes and erases to the SPI flash without using the atomic cycle mechanism. This could cause functional failures in a shared flash environment. Write Enable opcodes should only be programmed in the Prefix Opcodes. Bit 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Description Allowable Opcode 7 — R/W. See the description for bits 7:0 Allowable Opcode 6 — R/W. See the description for bits 7:0 Allowable Opcode 5 — R/W. See the description for bits 7:0 Allowable Opcode 4 — R/W. See the description for bits 7:0 Allowable Opcode 3 — R/W. See the description for bits 7:0 Allowable Opcode 2 — R/W. See the description for bits 7:0 Allowable Opcode 1 — R/W. See the description for bits 7:0 Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use when initiating SPI commands through the Control Register. This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. Datasheet 793 Serial Peripheral Interface (SPI) 22.1.23 BBAR—BIOS Base Address Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + A0h 00000000h Attribute: Size: R/W, RO 32 bits Eight entries are available in this register to give BIOS a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. This keeps the hardware flexible enough to operate with a wide variety of SPI devices. Bit 31:24 Reserved Bottom of System Flash— R/W. This field determines the bottom of the System BIOS. The ICH10 will not run programmed commands nor memory reads whose address field is less than this value. this field corresponds to bits 23:8 of the 3-byte address; bits 7:0 are assumed to be 00h for this vector when comparing to a potential SPI address. 23:8 NOTE: The SPI host controller prevents any programmed cycle using the address register with an address less than the value in this register. Some flash devices specify that the Read ID command must have an address of 0000h or 0001h. If this command must be supported with these device, it must be performed with the BIOS Bar Reserved Description 7:0 22.1.24 FDOC—Flash Descriptor Observability Control Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + B0h 00000000h Attribute: Size: R/W 32 bits Note: This register that can be used to observe the contents of the Flash Descriptor that is stored in the ICH10 Flash Controller. This register is only applicable when SPI device is in descriptor mode. Bit 31:15 Reserved Flash Descriptor Section Select (FDSS) — R/W. Selects which section within the loaded Flash Descriptor to observe. 000 = Flash Signature and Descriptor Map 14:12 001 = Component 010 = Region 011 = Master 111 = Reserved 11:2 1:0 Flash Descriptor Section Index (FDSI) — R/W. Selects the DW offset within the Flash Descriptor Section to observe. Reserved Description 794 Datasheet Serial Peripheral Interface (SPI) 22.1.25 FDOD—Flash Descriptor Observability Data Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + B4h 00000000h Attribute: Size: RO 32 bits Note: This register that can be used to observe the contents of the Flash Descriptor that is stored in the ICH10 Flash Controller. Bit 31:0 Description Flash Descriptor Section Data (FDSD) — RO. Returns the DW of data to observe as selected in the Flash Descriptor Observability Control. 22.1.26 AFC—Additional Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:3 Reserved. Flash Controller Interface Dynamic Clock Gating Enable — R/W. 2:1 0 = Flash Controller Interface Dynamic Clock Gating is Disabled 1 = Flash Controller Interface Dynamic Clock Gating is Enabled Other configurations are Reserved. Flash Controller Core Dynamic Clock Gating Enable — R/W. 0 0 = Flash Controller Core Dynamic Clock Gating is Disabled 1 = Flash Controller Core Dynamic Clock Gating is Enabled SPIBAR + C0h 00000000h Attribute: Size: Description RO, R/W 32 bits. Datasheet 795 Serial Peripheral Interface (SPI) 22.1.27 LVSCC— Host Lower Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + C4h 00000000h Attribute: Size: RO, RWL 32 bits All attributes described in LVSCC must apply to all flash space below the FPBA, even if it spans between two separate flash parts. This register is only applicable when SPI device is in descriptor mode. Bit 31:24 23 22:16 15:8 7:5 Reserved. Vendor Component Lock (LVCL) — RW. This register locks itself when set. 0 = The lock bit is not set 1 = The Vendor Component Lock bit is set. Reserved Lower Erase Opcode (LEO)— RW. This register is programmed with the Flash erase instruction opcode required by the vendor’s Flash component. This register is locked by the Vendor Component Lock (LVCL) bit. Reserved Write Enable on Write Status (LWEWS) — RW. This register is locked by the Vendor Component Lock (LVCL) bit. 0 = No requirement to write to the Status Register prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 06h is the opcode used to unlock the Status register. 4 NOTES: 1. This is not an atomic sequence. If the SPI component’s status register is nonvolatile, then BIOS should issue an atomic software sequence cycle to unlock the flash part. 2. This bit should not be set to 1 if the SPI flash status register is non-volatile. This may lead to premature flash wear out. 3. Bit 3 and bit 4 should NOT be both set to 1. Lower Write Status Required (LWSR) — RW. This register is locked by the Vendor Component Lock (LVCL) bit. 0 = No requirement to write to the Status Register prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 50h is the opcode used to unlock the Status register. 3 NOTES: 1. This is not an atomic sequence. If the SPI component’s status register is nonvolatile, then an atomic software sequencing should be used to unlock the flash part. NOTE: This bit should not be set to 1 if the SPI flash status register is non-volatile. This may lead to premature flash wear out. NOTE: Bit 3 and bit 4 should NOT be both set to 1. Description Note: 796 Datasheet Serial Peripheral Interface (SPI) Bit Description Lower Write Granularity (LWG) — RW. This register is locked by the Vendor Component Lock (LVCL) bit. 0 = 1 Byte 1 = 64 Byte 2 NOTES: 1. If more than one Flash component exists, this field must be set to the lowest common write granularity of the different Flash components. 2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B boundaries. This will lead to corruption as the write will wrap around the page boundary on the SPI flash part. This is a a feature page writeable SPI flash. Lower Block/Sector Erase Size (LBES)— RW. This field identifies the erasable sector size for all Flash components. 00 01 10 11 = = = = 256 Byte 4 KB 8 KB 64 KB 1:0 This register is locked by the Vendor Component Lock (LVCL) bit. Hardware takes no action based on the value of this register. The contents of this register are to be used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the GbE program registers if FLA is less than FPBA. 22.1.28 UVSCC— Host Upper Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + C8h 00000000h Attribute: Size: RO, RWL 32 bits Note: All attributes described in UVSCC must apply to all flash space equal to or above the FPBA, even if it spans between two separate flash parts. This register is only applicable when SPI device is in descriptor mode. Bit 31:24 Reserved. Vendor Component Lock (UVCL) — RW. 23 0 = The lock bit is not set 1 = The Vendor Component Lock bit is set. This register locks itself when set. 22:16 15:8 7:5 Reserved Upper Erase Opcode (UEO)— RW. This register is programmed with the Flash erase instruction opcode required by the vendor’s Flash component. This register is locked by the Vendor Component Lock (UVCL) bit. Reserved Description Datasheet 797 Serial Peripheral Interface (SPI) Bit Description Write Enable on Write Status (UWEWS) — RW.This register is locked by the Vendor Component Lock (UVCL) bit. 0 = No requirement to write to the Status Register prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 06h is the opcode used to unlock the Status register. 4 NOTES: 1. This is not an atomic sequence. If the SPI component’s status register is nonvolatile, then BIOS should issue an atomic software sequence cycle to unlock the flash part. 2. This bit should not be set to 1 if the SPI flash status register is non-volatile. This may lead to premature flash wear out. 3. Bit 3 and bit 4 should NOT be both set to 1. Upper Write Status Required (UWSR) — RW. This register is locked by the Vendor Component Lock (UVCL) bit. 0 = No requirement to write to the Status Register prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 50h is the opcode used to unlock the Status register. 3 NOTES: 1. This is not an atomic sequence. If the SPI component’s status register is nonvolatile, then an atomic software sequencing should be used to unlock the flash part. 2. This bit should not be set to 1 if the SPI flash status register is non-volatile. This may lead to premature flash wear out. 3. Bit 3 and bit 4 should NOT be both set to 1. Upper Write Granularity (UWG) — RW. This register is locked by the Vendor Component Lock (UVCL) bit. 0 = 1 Byte 1 = 64 Byte 2 NOTES: 1. If more than one Flash component exists, this field must be set to the lowest common write granularity of the different Flash components. 2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B boundaries. This will lead to corruption as the write will wrap around the page boundary on the SPI flash part. This is a a feature page writeable SPI flash. Upper Block/Sector Erase Size (UBES)— RW. This field identifies the erasable sector size for all Flash components. Valid Bit Settings: 00 = 256 Byte 01 = 4 KB 1:0 10 = 8 KB 11 = 64 KB This register is locked by the Vendor Component Lock (UVCL) bit. Hardware takes no action based on the value of this register. The contents of this register are to be used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the GbE program registers if FLA is greater or equal to FPBA. 798 Datasheet Serial Peripheral Interface (SPI) 22.1.29 FPB — Flash Partition Boundary (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + D0h 00000000h Attribute: Size: RO 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Bit 31:13 12:0 Reserved. Flash Partition Boundary Address (FPBA) — RO. This register reflects the value of Flash Descriptor Component FPBA field. Description Datasheet 799 Serial Peripheral Interface (SPI) 22.2 Flash Descriptor Registers The following sections describe the data structure of the Flash Descriptor on the SPI device. These are not registers within ICH10. 22.2.1 22.2.1.1 Flash Descriptor Content FLVALSIG - Flash Valid Signature Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:0 FDBAR + 000h 32 bits Default Value: h Description Flash Valid Signature. This field identifies the Flash Descriptor sector as valid. If the contents at this location contain 0FF0A55Ah, then the Flash Descriptor is considered valid and it will operate in Descriptor Mode, else it will operate in Non-Descriptor Mode. 22.2.1.2 FLMAP0 - Flash Map 0 Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:27 26:24 Reserved Number Of Regions (NR). This field identifies the total number of Flash Regions. This number is 0's based, so a setting of all 0's indicates that the only Flash region is region 0, the Flash Descriptor region. Flash Region Base Address (FRBA). This identifies address bits [11:4] for the Region portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. A recommended FRBA is 04h. 15:10 Reserved Number Of Components (NC). This field identifies the total number of Flash Components. Each supported Flash Component requires a separate chip select. 9:8 00 = 1 Component. 01 = 2 Components. All other settings = Reserved 7:0 Flash Component Base Address (FCBA). This identifies address bits [11:4] for the Component portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. A recommended FCBA is 01h. FDBAR + 004h 32 bits Default Value: h Description 23:16 800 Datasheet Serial Peripheral Interface (SPI) 22.2.1.3 FLMAP1—Flash Map 1 Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:24 FDBAR + 008h 32 bits Default Value: h Description ICH Strap Length (ISL). Identifies the 1s based number of Dwords of ICH Straps to be read, up to 255 DWs (1KB) max. A setting of all 0's indicates there are no ICH DW straps. Flash ICH Strap Base Address (FISBA). This identifies address bits [11:4] for the ICH Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. For validation purposes, the recommended FISBA is 10h Reserved Number Of Masters (NM). This field identifies the total number of Flash Regions. This number is 0's based. Flash Master Base Address (FMBA). This identifies address bits [11:4] for the Master portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. A recommended FMBA is 06h. 23:16 15:11 10:08 7:0 22.2.1.4 FLMAP2—Flash Map 2 Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:16 15:08 Reserved MCH Strap Length (MSL). Identifies the 1's based number of Dwords of (G)MCH Straps to be read, up to 255 DWs (1KB) max. A setting of all 0's indicates there are no (G)MCH DW straps. Flash (G)MCH Strap Base Address (FMSBA). This identifies address bits [11:4] for the (G)MCH Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. A recommended FMSBA is 20h. FDBAR + 00Ch 32 bits Default Value: h Description 7:0 Datasheet 801 Serial Peripheral Interface (SPI) 22.2.2 Flash Descriptor Component Section The following section of the Flash Descriptor is used to identify the different Flash Components and their capabilities. 22.2.2.1 FLCOMP—Flash Components Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:30 Reserved Read ID and Read Status Clock Frequency. 000 = 20 MHz 29:27 001 = 33 MHz All other Settings = Reserved NOTE: If more than one Flash component exists, this field must be set to the lowest common frequency of the different Flash components. Write and Erase Clock Frequency. 000 = 20 MHz 26:24 001 = 33 MHz All other Settings = Reserved NOTE: If more than one Flash component exists, this field must be set to the lowest common frequency of the different Flash components. Fast Read Clock Frequency. This field identifies the frequency that can be used with the Fast Read instruction. This field is undefined if the Fast Read Support field is '0'. 000 = 20 MHz 23:21 001 = 33 MHz All other Settings = Reserved NOTE: If more than one Flash component exists, this field must be set to the lowest common frequency of the different Flash components. Fast Read Support. 0 = Fast Read is not Supported 1 = Fast Read is supported If the Fast Read Support bit is a '1' and a device issues a Direct Read or issues a read command from the Hardware Sequencer and the length is greater than 4 bytes, then the SPI Flash instruction should be "Fast Read". If the Fast Read Support is a '0' or the length is 1-4 bytes, then the SPI Flash instruction should be "Read". Reads to the Flash Descriptor always use the Read command independent of the setting of this bit. NOTE: If more than one Flash component exists, this field can only be set to '1' if both components support Fast Read. FCBA + 000h 32 bits Default Value: h Description 20 802 Datasheet Serial Peripheral Interface (SPI) Bits Read Clock Frequency. 000 = 20 MHz 19:17 All other Settings = Reserved Description NOTE: If more than one Flash component exists, this field must be set to the lowest common frequency of the different Flash components. 16:6 Reserved Component 2 Density. This field identifies the size of the 2nd Flash component. If there is not 2nd Flash component, the contents of this field are undefined. 000 = 512 KB 001 = 1 MB 5:3 010 = 2 MB 011 = 4 MB 100 = 8 MB 101 = 16 MB 111 = Reserved Component 1 Density. This field identifies the size of the 1st or only Flash component. 000 = 512 KB 001 = 1 MB 010 = 2 MB 2:0 011 = 4 MB 100 = 8 MB 101 = 16 MB 111 = Reserved This field is defaulted to "101b" (16 MB) after reset. In non-descriptor mode, only one flash component is supported and all accesses to flash will be to this component. Datasheet 803 Serial Peripheral Interface (SPI) 22.2.2.2 FLILL—Flash Invalid Instructions Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:24 23:16 15:8 FCBA + 004h 32 bits Default Value: h Description Invalid Instruction 3. See definition of Invalid Instruction 0 Invalid Instruction 2. See definition of Invalid Instruction 0 Invalid Instruction 1. See definition of Invalid Instruction 0 Invalid Instruction 0. Op-code for an invalid instruction in the that the Flash Controller should protect against such as Chip Erase. This byte should be set to 0 if there are no invalid instructions to protect against for this field. Op-codes programmed in the Software Sequencing Opcode Menu Configuration and Prefix-Opcode Configuration are not allowed o use any of the Invalid Instructions listed in this register. 7:0 22.2.2.3 FLPB—Flash Partition Boundary Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:13 Reserved Flash Partition Boundary Address (FPBA). This register specifies Flash Boundary Address bits[24:12] that logically divides the flash space into two partitions, a lower and an upper partition. The lower and upper partitions can support SPI flash parts with different attributes between partitions that are defined in the LVSCC and UVSCC. NOTE: All flash space in each partition must have the same in the VSCC attributes, even if it spans between different flash parts. NOTE: If this register is set to all 0s, then there is only one partition, the upper partition, and the entire address space has uniform erasable sector sizes, write granularity, and write state required settings. The FPBA must reside on an erasable sector boundary. FCBA + 008h 32 bits Default Value: h Description 12:0 804 Datasheet Serial Peripheral Interface (SPI) 22.2.3 Flash Descriptor Region Section The following section of the Flash Descriptor is used to identify the different Flash Regions Flash Regions: • If a particular region is not using SPI Flash, the particular region should be disabled by setting the Region Base to all 1's, and the Region Limit to all 0's (base is higher than the limit) • For each region except FLREG0, the Flash Controller must have a default Region Base of FFFh and the Region Limit to 000h within the Flash Controller in case the Number of Regions specifies that a region is not used. 22.2.3.1 FLREG0—Flash Region 0 (Flash Descriptor) Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:29 28:16 15:13 12:0 Reserved Region Limit. This specifies address bits 24:12 for the Region Limit. Reserved Region Base. This specifies address bits 24:12 for the Region Base. FRBA + 000h 32 bits Default Value: h Description 22.2.3.2 FLREG1—Flash Region 1 (BIOS) Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:29 28:16 15:13 Reserved Region Limit. This specifies address bits 24:12 for the Region Limit. Reserved Region Base. This specifies address bits 24:12 for the Region Base. 12:0 NOTE: If the BIOS region is not used, the Region Base must be programmed to 1FFFh and the Region Limit to 0000h to disable the region. FRBA + 004h 32 bits Default Value: h Description Datasheet 805 Serial Peripheral Interface (SPI) 22.2.3.3 FLREG2—Flash Region 2 (ME) Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:29 28:16 15:13 Reserved Region Limit. This specifies address bits 24:12 for the Region Limit. Reserved Region Base. This specifies address bits 24:12 for the Region Base. 12:0 NOTE: If the Intel Management Engine region is not used, the Region Base must be programmed to 1FFFh and the Region Limit to 0000h to disable the region. FRBA + 008h 32 bits Default Value: h Description 22.2.3.4 FLREG3—Flash Region 3 (GbE) Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:29 28:16 NOTE: The maximum Region Limit is 128KB above the region base. 15:13 Reserved Region Base. This specifies address bits 24:12 for the Region Base. 12:0 NOTE: If the GbE region is not used, the Region Base must be programmed to 1FFFh and the Region Limit to 0000h to disable the region. Reserved Region Limit. This specifies address bits 24:12 for the Region Limit. FRBA + 00Ch 32 bits Default Value: h Description 22.2.3.5 FLREG4—Flash Region 4 (Platform Data) Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:29 28:16 NOTE: The maximum Region Limit is 128KB above the region base. 15:13 Reserved Region Base. This specifies address bits 24:12 for the Region Base. 12:0 NOTE: If the Platform Data region is not used, the Region Base must be programmed to 1FFFh and the Region Limit to 0000h to disable the region. Reserved Region Limit. This specifies address bits 24:12 for the Region Limit. FRBA + 010h 32 bits Default Value: h Description 806 Datasheet Serial Peripheral Interface (SPI) 22.2.4 22.2.4.1 Flash Descriptor Master Section FLMSTR1—Flash Master 1 (Host CPU/ BIOS) (Flash Descriptor Registers) Memory Address: Size: Bits 31:29 28 27 26 Reserved, must be zero Platform Data Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. GbE Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. ME Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Host CPU/BIOS Master Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Bit 25 is a don’t care as the primary master always has read/write permissions to it’s primary region Flash Descriptor Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Reserved, must be zero Platform Data Region Read Access. If the bit is set, this master can read that particular region through register accesses. GbE Region Read Access. If the bit is set, this master can read that particular region through register accesses. ME Region Read Access. If the bit is set, this master can read that particular region through register accesses. Host CPU/BIOS Master Region Read Access. If the bit is set, this master can read that particular region through register accesses. Bit 17 is a don’t care as the primary master always has read/write permissions to it’s primary region Flash Descriptor Region Read Access. If the bit is set, this master can read that particular region through register accesses. Requester ID. This is the Requester ID of the Host processor. This must be set to 0000h. FMBA + 000h 32 bits Default Value: h Description 25 24 23:21 20 19 18 17 16 15:0 Datasheet 807 Serial Peripheral Interface (SPI) 22.2.4.2 FLMSTR2—Flash Master 2 (ME) (Flash Descriptor Registers) Memory Address: Size: Bits 31:29 28 27 Reserved, must be zero Platform Data Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. GbE Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. ME Master Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Bit 26 is a don’t care as the primary master always has read/write permissions to it’s primary region Host CPU/BIOS Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Flash Descriptor Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Reserved, must be zero Platform Data Region Read Access. If the bit is set, this master can read that particular region through register accesses. GbE Region Read Access. If the bit is set, this master can read that particular region through register accesses. ME Master Region Read Access. If the bit is set, this master can read that particular region through register accesses. Bit 18 is a don’t care as the primary master always has read/write permissions to it’s primary region Host CPU/BIOS Region Read Access. If the bit is set, this master can read that particular region through register accesses. Flash Descriptor Region Read Access. If the bit is set, this master can read that particular region through register accesses. Requester ID. This is the Requester ID of the Intel Management Engine. This must be set to 0000h. FMBA + 004h 32 bits Default Value: h Description 26 25 24 23:21 20 19 18 17 16 15:0 808 Datasheet Serial Peripheral Interface (SPI) 22.2.4.3 FLMSTR3—Flash Master 3 (GbE) (Flash Descriptor Registers) Memory Address: Size: Bits 31:29 28 Reserved, must be zero Platform Data Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. GbE Master Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Bit 27 is a don’t care as the primary master always has read/write permissions to it’s primary region ME Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Host CPU/BIOS Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Flash Descriptor Region Write Access. If the bit is set, this master can erase and write that particular region through register accesses. Reserved, must be zero Platform Data Region Read Access. If the bit is set, this master can read that particular region through register accesses. GbE Master Region Read Access. If the bit is set, this master can read that particular region through register accesses. Bit 19 is a don’t care as the primary master always has read/write permissions to it’s primary region ME Region Read Access. If the bit is set, this master can read that particular region through register accesses. Host CPU/BIOS Region Read Access. If the bit is set, this master can read that particular region through register accesses. Flash Descriptor Region Read Access. If the bit is set, this master can read that particular region through register accesses. Requester ID. This is the Requester ID of the GbE. This must be set to 0218h. FMBA + 008h 32 bits Default Value: h Description 27 26 25 24 23:21 20 19 18 17 16 15:0 Datasheet 809 Serial Peripheral Interface (SPI) 22.2.5 22.2.5.1 Descriptor Upper Map Section FLUMAP1—Flash Upper Map 1 (Flash Descriptor Registers) Memory Address: Size: Bits 31:16 15:8 Default 0 1 Reserved ME VSCC Table Length (VTL). Identifies the 1s based number of DWORDS contained in the VSCC Table. Each SPI component entry in the table is 2 DWORDS long. ME VSCC Table Base Address (VTBA). This identifies address bits [11:4] for the VSCC Table portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. NOTE: VTBA should be above the offset for MCHSTRP0 and below FLUMAP1. It is recommended that this address is set based on the anticipated maximum number of different flash parts entries. FDBAR + EFCh 32 bits Default Value: 0000FFFFh Description 7:0 1 22.2.6 Intel ME Vendor Specific Component Capabilities Table Entries in this table allow support for a SPI flash part for Intel® Quiet System Technology. BIOS will still need to set up the proper VSCC registers for BIOS and Integrated Gigabit Ethernet usage. Each VSCC table entry is composed of two 32 bit fields: JEDEC ID and the corresponding VSCC value. 22.2.6.1 JID0—JEDEC-ID 0 Register (Flash Descriptor Registers) Memory Address: Size: Bits 31:24 23:16 Reserved SPI Component Device ID 1. This field identifies the second byte of the Device ID of the SPI Flash Component. This is the third byte returned by the Read JEDEC-ID command (opcode 9Fh). SPI Component Device ID 0. This field identifies the first byte of the Device ID of the SPI Flash Component. This is the second byte returned by the Read JEDEC-ID command (opcode 9Fh). SPI Component Vendor ID. This field identifies the one byte Vendor ID of the SPI Flash Component. This is the first byte returned by the Read JEDEC-ID command (opcode 9Fh). VTBA + 000h 32 bits Default Value: Description 15:8 7:0 810 Datasheet Serial Peripheral Interface (SPI) 22.2.6.2 VSCC0—Vendor Specific Component Capabilities 0 (Flash Descriptor Registers) Memory Address: Size: VTBA + 004h 32 bits Default Value: Note: In this table “Lower” applies to characteristics of all flash space below the Flash Partition Boundary Address (FPBA). “Upper” applies to characteristics of all flash space above the FPBA. Bits 31:16 23:21 Description Lower Erase Opcode (LEO). This register must be programmed with the Flash erase instruction opcode that corresponds to the erase size that is in LBES. Reserved Lower Write Enable on Write Status (LWEWS). 0 = No write to the SPI flash’s status register required prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 06h is the opcode used to unlock the Status register. NOTES: 1. This bit should not be set to 1 if the SPI flash status register is non-volatile. This may lead to premature flash wear out. 2. Bit 20 and bit 19 should NOT be both set to 1. Lower Write Status Required (LWSR). 0 = No requirement to write to the Status Register prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 50h is the opcode used to unlock the Status register. NOTES: 1. Bit 20 and bit 19 should NOT be both set to 1. 2. Bit 19 should not be set if the flash part does not support the opcode 50h to unlock the status register. Lower Write Granularity (LWG). 18 0 = 1 Byte 1 = 64 Byte Lower Block/Sector Erase Size (LBES). This field identifies the erasable sector size for all Flash space below the flash partition boundary address. 17:16 00 = 256 Byte 01 = 4 KB 10 = 8 KB 11 = 64 KB 15:8 7:5 Upper Erase Opcode (UEO). This register must be programmed with the Flash erase instruction opcode that corresponds to the erase size that is in LBES. Reserved 20 19 Datasheet 811 Serial Peripheral Interface (SPI) Bits Description Upper Write Enable on Write Status (UWEWS). 0 = No write to the SPI flash’s status register required prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 06h is the opcode used to unlock the Status register. NOTES: 1. This bit should not be set to 1 if the SPI flash status register is non-volatile. This may lead to premature flash wear out. 2. Bit 4 and bit 3 should NOT be both set to 1. Upper Write Status Required (UWSR). 0 = No requirement to write to the Status Register prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 50h is the opcode used to unlock the Status register. NOTES: 1. Bit 4 and bit 3 should NOT be both set to 1. 2. Bit 3 should not be set if the flash part does not support the opcode 50h to unlock the status register. Upper Write Granularity (UWG). 0 = 1 Byte 1 = 64 Bytes Upper Block/Sector Erase Size (UBES). This field identifies the erasable sector size for all Flash components. 4 3 2 1:0 00 = 256 Bytes 01 = 4 KB 10 = 8 KB 11 = 64 KB 22.2.6.3 JIDn—JEDEC-ID Register n (Flash Descriptor Registers) Memory Address: Size: VTBA + (n*8)h 32 bits Default Value: Note: “n” is an integer denoting the index of the Intel ME VSCC table. Bits 31:24 23:16 Reserved SPI Component Device ID 1. This field identifies the second byte of the Device ID of the SPI Flash Component. This is the third byte returned by the Read JEDEC-ID command (opcode 9Fh). SPI Component Device ID 0. This field identifies the first byte of the Device ID of the SPI Flash Component. This is the second byte returned by the Read JEDEC-ID command (opcode 9Fh). SPI Component Vendor ID. This field identifies the one byte Vendor ID of the SPI Flash Component. This is the first byte returned by the Read JEDEC-ID command (opcode 9Fh). Description 15:8 7:0 812 Datasheet Serial Peripheral Interface (SPI) 22.2.6.4 VSCCn—Vendor Specific Component Capabilities n (Flash Descriptor Registers) Memory Address: Size: VTBA + 004h + (n*8)h 32 bits Default Value: Note: Note: “n” is an integer denoting the index of the Intel ME VSCC table. In this table “Lower” applies to characteristics of all flash space below the Flash Partition Boundary Address (FPBA). “Upper” applies to characteristics of all flash space above the FPBA. Bits 31:16 23:21 Description Lower Erase Opcode (LEO). This field must be programmed with the Flash erase instruction opcode that corresponds to the erase size that is in LBES. Reserved Lower Write Enable on Write Status (LWEWS). 0 = No write to the SPI flash’s status register required prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 06h is the opcode used to unlock the Status register. NOTES: 1. This bit should not be set to 1 if the SPI flash status register is non-volatile. This may lead to premature flash wear out. 2. Bit 20 and bit 19 should NOT be both set to 1. Lower Write Status Required (LWSR). 0 = No requirement to write to the Status Register prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 50h is the opcode used to unlock the Status register. NOTES: 1. Bit 20 and bit 19 should NOT be both set to1. 2. Bit 19 should not be set if the flash part does not support the opcode 50h to unlock the status register. Lower Write Granularity (LWG). 18 0 = 1 Byte 1 = 64 Byte Lower Block/Sector Erase Size (LBES). This field identifies the erasable sector size for all Flash space below the flash partition boundary address. Valid Bit Settings: 17:16 00 = 256 Byte 01 = 4 KB 10 = 8 KB 11 = 64 KB 15:8 7:5 Upper Erase Opcode (UEO). This field must be programmed with the Flash erase instruction opcode that corresponds to the erase size that is in LBES. Reserved 20 19 Datasheet 813 Serial Peripheral Interface (SPI) Bits Description Upper Write Enable on Write Status (UWEWS). 0 = No write to the SPI flash’s status register required prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 06h is the opcode used to unlock the Status register. NOTES: 1. This bit should not be set to 1 if the SPI flash status register is non-volatile. This may lead to premature flash wear out. 2. Bit 4 and bit 3 should NOT be both set to 1. Upper Write Status Required (UWSR). 0 = No requirement to write to the Status Register prior to a write 1 = A write of 00h to the SPI flash’s status register is required prior to write and erase to unlock the flash component. 50h is the opcode used to unlock the Status register. NOTES: 1. Bit 4 and bit 3 should NOT be both set to 1. 2. Bit 3 should not be set if the flash part does not support the opcode 50h to unlock the status register. Upper Write Granularity (UWG). 0 = 1 Byte 1 = 64 Bytes Upper Block/Sector Erase Size (UBES). This field identifies the erasable sector size for all Flash components. 4 3 2 1:0 00 = 256 Bytes 01 = 4 KB 10 = 8 KB 11 = 64 KB 814 Datasheet Serial Peripheral Interface (SPI) 22.3 OEM Section Memory Address: Size: F00h 256 Bytes Default Value: 256 Bytes are reserved at the top of the Flash Descriptor for use by the OEM. The information stored by the OEM can only be written during the manufacturing process as the Flash Descriptor read/write permissions must be set to Read Only when the computer leaves the manufacturing floor. The ICH Flash controller does not read this information. FFh is suggested to reduce programming time. 22.4 GbE SPI Flash Program Registers The GbE Flash registers are memory-mapped with a base address MBARB found in the GbE LAN register chapter Device 25: Function 0: Offset 14h. The individual registers are then accessible at MBARB + Offset as indicated in the following table. These memory mapped registers must be accessed in byte, word, or DWord quantities. Note: These register are only applicable when SPI flash is used in descriptor mode. Table 22-2. Gigabit LAN SPI Flash Program Register Address Map (GbE LAN Memory Mapped Configuration Registers) MBARB + Offset 00h–03h 04h–05h 06h–07h 08h–0Bh 0Ch–0Fh 10h–13h 14h–4Fh 50h–53h 54h–57h 58h–5Bh 5Ch–5F 60h–63h 64h–73h 74h–77h 78h–7Bh 7Ch–8Fh 90h 91h–93h 94h–95h 96h–97h 98h–9Fh A0h–DFh Mnemonic GLFPR HSFSTS HSFCTL FADDR Reserved FDATA0 Reserved FRAP FREG0 FREG1 FREG2 FREG3 Reserved FPR0 FPR1 Reserved SSFSTS SSFCTL PREOP OPTYPE OPMENU Reserved Register Name Gigabit LAN Flash Primary Region Hardware Sequencing Flash Status Hardware Sequencing Flash Control Flash Address Reserved Flash Data 0 Reserved Flash Region Access Permissions Flash Region 0 Flash Region 1 Flash Region 2 Flash Region 3 Reserved for Future Flash Regions Flash Protected Range 0 Flash Protected Range 1 Reserved Software Sequencing Flash Status Software Sequencing Flash Control Prefix Opcode Configuration Opcode Type Configuration Opcode Menu Configuration Reserved 00h 000000h 0000h 0000h 00000000 00000000h RO, R/W R/W R/W R/W R/W 00000000h 00000000h R/W R/W Default 00000000h 0000h 0000H 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h RO, R/W RO RO RO RO R/W Type RO RO, R/WC, R/W R/W, R/WS R/W Datasheet 815 Serial Peripheral Interface (SPI) 22.4.1 GLFPR –Gigabit LAN Flash Primary Region Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:29 Reserved GbE Flash Primary Region Limit (PRL)— RO. This specifies address bits 24:12 for the Primary Region Limit. The value in this register loaded from the contents in the Flash Descriptor.FLREG3.Region Limit Reserved GbE Flash Primary Region Base (PRB) — RO. This specifies address bits 24:12 for the Primary Region Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Base MBARB + 00h 00000000h Attribute: Size: Description RO 32 bits 28:16 15:13 12:0 816 Datasheet Serial Peripheral Interface (SPI) 22.4.2 HSFS—Hardware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit MBARB + 04h 0000h Attribute: Size: Description RO, R/WC, R/W 16 bits 15 Flash Configuration Lock-Down (FLOCKDN)— R/W. When set to 1, those Flash Program Registers that are locked down by this FLOCKDN bit cannot be written. Once set to 1, this bit can only be cleared by a hardware reset due to a global reset or host partition reset in an Intel ME enabled system. Flash Descriptor Valid (FDV)— RO. This bit is set to a 1 if the Flash Controller read the correct Flash Descriptor Signature. 14 If the Flash Descriptor Valid bit is not ‘1’, software cannot use the Hardware Sequencing registers, but must use the software sequencing registers. Any attempt to use the Hardware Sequencing registers will result in the FCERR bit being set. Flash Descriptor Override Pin Strap Status (FDOPSS)— RO. This bit reflects the value the Flash Descriptor Override Pin-Strap. 0 = No override 1 = The Flash Descriptor Override strap is set Reserved SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0. Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sector size for all Flash components. 00 = 256 Byte 01 = 4 K Byte 13 12:6 5 4:3 10 = 8 K Byte 11 = 64 K Byte If the FLA is less than FPBA then this field reflects the value in the LVSCC.LBES register. If the FLA is greater or equal to FPBA then this field reflects the value in the UVSCC.UBES register. 2 Access Error Log (AEL)— R/W/C. Hardware sets this bit to a 1 when an attempt was made to access the BIOS region using the direct access method or an access to the BIOS Program Registers that violated the security restrictions. This bit is simply a log of an access security violation. This bit is cleared by software writing a ‘1’ Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program register access is blocked to the FLASH due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or until hardware reset occurs due to a global reset or host partition reset in an Intel ME enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in this register. Flash Cycle Done (FDONE) — R/W/C. The ICH sets this bit to 1 when the SPI Cycle completes after software previously set the FGO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. 1 0 Datasheet 817 Serial Peripheral Interface (SPI) 22.4.3 HSFC—Hardware Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 15:10 Reserved Flash Data Byte Count (FDBC) — R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The content’s of this register are 0s based with 0b representing 1 byte and 11b representing 4 bytes. The number of bytes transferred is the value of this field plus 1. This field is ignored for the Block Erase command. 7:3 Reserved FLASH Cycle (FCYCLE) — R/W. This field defines the Flash SPI cycle type generated to the FLASH when the FGO bit is set as defined below: 2:1 00 = Read (1 up to 4 bytes by setting FDBC) 01 = Reserved 10 = Write (1 up to 4 bytes by setting FDBC) 11 = Block Erase Flash Cycle Go (FGO) — R/W/S. A write to this register with a ‘1’ in this bit initiates a request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the cycle is complete, the FDONE bit is set. 0 Software is forbidden to write to any register in the HSFLCTL register between the FGO bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be ignored by hardware. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. This bit always returns 0 on reads. MBARB + 06h 0000h Attribute: Size: Description R/W, R/WS 16 bits 9:8 22.4.4 FADDR—Flash Address Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:25 24:0 Reserved Flash Linear Address (FLA) — R/W. The FLA is the starting byte linear address of a SPI Read or Write cycle or an address within a Block for the Block Erase command. The Flash Linear Address must fall within a region for which BIOS has access permissions. MBARB + 08h 00000000h Attribute: Size: Description R/W 32 bits 818 Datasheet Serial Peripheral Interface (SPI) 22.4.5 FDATA0—Flash Data 0 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit MBARB + 10h 00000000h Attribute: Size: Description R/W 32 bits Flash Data 0 (FD0) — R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In Data pin during the data portion of the SPI cycle. This register also shifts in the data from the Master-In Slave-Out pin into this register during the data portion of the SPI cycle. 31:0 The data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24 Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always represents the value specified by the cycle address. Note that the data in this register may be modified by the hardware during any programmed SPI transaction. Direct Memory Reads do not modify the contents of this register. Datasheet 819 Serial Peripheral Interface (SPI) 22.4.6 FRAP—Flash Regions Access Permissions Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:28 Reserved GbE Master Write Access Grant (GMWAG) — R/W. Each bit 27:25 corresponds to Master[3:1]. GbE can grant one or more masters write access to the GbE region 3 overriding the permissions in the Flash Descriptor. Master[1] is Host CPU/BIOS, Master[2] is Intel Management Engine, Master[3] is Host processor/GbE. The contents of this register are locked by the FLOCKDN bit. 24:20 Reserved GbE Master Read Access Grant (GMRAG) — R/W. Each bit 19:17 corresponds to Master[3:1]. GbE can grant one or more masters read access to the GbE region 3 overriding the read permissions in the Flash Descriptor. Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is GbE. The contents of this register are locked by the FLOCKDN bit 16:12 Reserved GbE Region Write Access (GRWA) — RO. Each bit 11:8 corresponds to Regions 3:0. If the bit is set, this master can erase and write that particular region through register accesses. 11:8 The contents of this register are that of the Flash Descriptor. Flash Master 3.Master Region Write Access OR a particular master has granted GbE write permissions in their Master Write Access Grant register OR the Flash Descriptor Security Override strap is set. Reserved GbE Region Read Access (GRRA) — RO. Each bit 3:0 corresponds to Regions 3:0. If the bit is set, this master can read that particular region through register accesses. 3:0 The contents of this register are that of the Flash Descriptor. Flash Master 3.Master Region Write Access OR a particular master has granted GbE read permissions in their Master Read Access Grant register. MBARB + 50h 00000808h Attribute: Size: Description RO, R/W 32 bits 27:25 19:17 7:4 820 Datasheet Serial Peripheral Interface (SPI) 22.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:29 28:16 15:13 12:0 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Limit Reserved Region Base (RB) — RO. This specifies address bits 24:12 for the Region 0 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Base MBARB + 54h 00000000h Attribute: Size: Description RO 32 bits 22.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:29 28:16 15:13 12:0 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 1 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Limit. Reserved Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base. MBARB + 58h 00000000h Attribute: Size: Description RO 32 bits 22.4.9 FREG2—Flash Region 2 (ME) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:29 28:16 15:13 12:0 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 2 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Limit. Reserved Region Base (RB) — RO. This specifies address bits 24:12 for the Region 2 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Base. MBARB + 5Ch 00000000h Attribute: Size: Description RO 32 bits Datasheet 821 Serial Peripheral Interface (SPI) 22.4.10 FREG3—Flash Region 3 (GbE) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 31:29 28:16 15:13 12:0 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 3 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Limit. Reserved Region Base (RB) — RO. This specifies address bits 24:12 for the Region 3 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Base. MBARB + 60h 00000000h Attribute: Size: Description RO 32 bits 22.4.11 FPR0—Flash Protected Range 0 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 74h 00000000h Attribute: Size: R/W 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Bit Description Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. 31 30:29 28:16 15 14:13 12:0 822 Datasheet Serial Peripheral Interface (SPI) 22.4.12 FPR1—Flash Protected Range 1 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 78h 00000000h Attribute: Size: R/W 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Bit Description Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. 31 30:29 28:16 15 14:13 12:0 Datasheet 823 Serial Peripheral Interface (SPI) 22.4.13 SSFS—Software Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 90h 00h Attribute: Size: RO, R/WC 8 bits Note: The Software Sequencing control and status registers are reserved if the hardware sequencing control and status registers are used. Bit 7:5 4 Reserved Access Error Log (AEL) — RO. This bit reflects the value of the Hardware Sequencing Status AEL register. Flash Cycle Error (FCERR) — R/WC. Hardware sets this bit to 1 when a programmed access is blocked from running on the SPI interface due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME enabled system. Cycle Done Status — R/WC. The ICH sets this bit to 1 when the SPI Cycle completes (i.e., SCIP bit is 0) after software sets the GO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. Reserved SPI Cycle In Progress (SCIP) — RO. Hardware sets this bit when software sets the SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0. Description 3 2 1 0 824 Datasheet Serial Peripheral Interface (SPI) 22.4.14 SSFC—Software Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 23:19 Reserved SPI Cycle Frequency (SCF) — R/W. This register sets frequency to use for all SPI software sequencing cycles (write, erase, fast read, read status, etc.) except for the read cycle which always run at 20MHz. 18:16 000 = 20 MHz 001 = 33 MHz All other values = Reserved. This register is locked when the SPI Configuration Lock-Down bit is set. 15 14 Reserved Data Cycle (DS) — R/W. When set to 1, there is data that corresponds to this transaction. When 0, no data is delivered for this cycle, and the DBC and data fields themselves are don’t cares Data Byte Count (DBC) — R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The valid settings (in decimal) are any value from 0 to 3. The number of bytes transferred is the value of this field plus 1. Note that when this field is 00b, then there is 1 byte to transfer and that 11b means there are 4 bytes to transfer. 7 6:4 Reserved Cycle Opcode Pointer (COP) — R/W. This field selects one of the programmed opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic Cycle Sequence, this determines the second command. Sequence Prefix Opcode Pointer (SPOP) — R/W. This field selects one of the two programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes register. By making this programmable, the ICH supports flash devices that have different opcodes for enabling writes to the data space vs. status register. Atomic Cycle Sequence (ACS) — R/W. When set to 1 along with the SCGO assertion, the ICH will execute a sequence of commands on the SPI interface without allowing the LAN component to arbitrate and interleave cycles. The sequence is composed of: 2 • • • Atomic Sequence Prefix Command (8-bit opcode only) Primary Command specified below by software (can include address and data) Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b. MBARB + 91h 000000h Attribute: Size: Description R/W 24 bits 13:8 3 The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset until the Busy bit in the Flash Status Register returns 0. SPI Cycle Go (SCGO) — R/WS. This bit always returns 0 on reads. However, a write to this register with a ‘1’ in this bit starts the SPI cycle defined by the other bits of this register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action. Hardware must ignore writes to this bit while the Cycle In Progress bit is set. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. 0 Reserved 1 Datasheet 825 Serial Peripheral Interface (SPI) 22.4.15 PREOP—Prefix Opcode Configuration Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 15:8 7:0 MBARB + 94h 0000h Attribute: Size: Description R/W 16 bits Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. NOTE: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15) is set. 22.4.16 OPTYPE—Opcode Type Configuration Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 96h 0000h Attribute: Size: R/W 16 bits Entries in this register correspond to the entries in the Opcode Menu Configuration register. Note: The definition below only provides write protection for opcodes that have addresses associated with them. Therefore, any erase or write opcodes that do not use an address should be avoided (for example, “Chip Erase” and “Auto-Address Increment Byte Program”). Bit 15:14 13:12 11:10 9:8 7:6 5:4 3:2 Description Opcode Type 7 — R/W. See the description for bits 1:0 Opcode Type 6 — R/W. See the description for bits 1:0 Opcode Type 5 — R/W. See the description for bits 1:0 Opcode Type 4 — R/W. See the description for bits 1:0 Opcode Type 3 — R/W. See the description for bits 1:0 Opcode Type 2 — R/W. See the description for bits 1:0 Opcode Type 1 — R/W. See the description for bits 1:0 Opcode Type 0 — R/W. This field specifies information about the corresponding Opcode 0. This information allows the hardware to 1) know whether to use the address field and 2) provide BIOS and Shared Flash protection capabilities. The encoding of the two bits is: 00 = No address associated with this Opcode; Read cycle type 01 = No address associated with this Opcode; Write cycle type 10 = Address required; Read cycle type 11 = Address required; Write cycle type NOTE: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15) is set. 1:0 826 Datasheet Serial Peripheral Interface (SPI) 22.4.17 OPMENU—Opcode Menu Configuration Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 98h 0000000000000000h Attribute: Size: R/W 64 bits Eight entries are available in this register to give GbE a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. This keeps the hardware flexible enough to operate with a wide variety of SPI devices. Note: It is recommended that GbE avoid programming Write Enable opcodes in this menu. Malicious software could then perform writes and erases to the SPI flash without using the atomic cycle mechanism. This could cause functional failures in a shared flash environment. Write Enable opcodes should only be programmed in the Prefix Opcodes. Bit 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Description Allowable Opcode 7 — R/W. See the description for bits 7:0 Allowable Opcode 6 — R/W. See the description for bits 7:0 Allowable Opcode 5 — R/W. See the description for bits 7:0 Allowable Opcode 4 — R/W. See the description for bits 7:0 Allowable Opcode 3 — R/W. See the description for bits 7:0 Allowable Opcode 2 — R/W. See the description for bits 7:0 Allowable Opcode 1 — R/W. See the description for bits 7:0 Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use when initiating SPI commands through the Control Register. This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15) is set. §§ Datasheet 827 Serial Peripheral Interface (SPI) 828 Datasheet Thermal Sensor Registers (D31:F6) 23 23.1 Thermal Sensor Registers (D31:F6) PCI Bus Configuration Registers Table 23-1. Thermal Sensor Register Address Map Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h–13h 14h–17h 2Ch–2Dh 2Eh–2Fh 34h 3Ch 3Dh 40h–43h 44h–47h 50h–51h 52h–53h 54h–57h Mnemonic VID DID CMD STS RID PI SCC BCC CLS LT HTYPE BIST TBAR TBARH SVID SID CAP_PTR INTLN INTPN TBARB TBARBH PID PC PCS Register Name Vendor Identification Device Identification Command Register Device Status Revision ID Programming Interface Sub Class Code Base Class Code Cache Line Size Latency Timer Header Type Built-in Self Test Thermal Base Address (Memory) Thermal Base Address High DWord Subsystem Vendor Identifier Subsystem Identifier Capabilities Pointer Interrupt Line Interrupt Pin BIOS Assigned Thermal Base Address BIOS Assigned BA High DWord Power Management Identifiers Power Management Capabilities Power Management Control and Status Default 8086h TBD 0000h 0010h 00h 00h 80h 11h 00h 00h 00h 00h 00000004h 00000000h 0000h 0000h 50h 00h TBD 00000004h 00000000h 0001h 0022h 0000h Type RO RO R/W, RO R/WC, RO RO RO RO RO RO RO RO RO R/W, RO RO R/WO R/WO RO RW RO R/W, RO R/W RO RO R/W, RO Datasheet 829 Thermal Sensor Registers (D31:F6) 23.1.1 VID—Vendor Identification Offset Address: 00h–01h Default Value: 8086h Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16 bit Core Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 23.1.2 DID—Device Identification Offset Address: 02h–03h Default Value: TBD Bit 15:0 Attribute: Size: Description RO 16 bit Device ID (DID) — RO. Indicates the device number assigned by the SIG. 23.1.3 CMD—Command Address Offset: 04h–05h Default Value: 0000h Bit 15:11 10 9 8 7 6 5 4 3 2 1 Reserved Interrupt Disable (ID) — RW. Enables the device to assert an INTx#. 0 = When cleared, the INTx# signal may be asserted. 1 = When set, the Thermal logic’s INTx# signal will be de-asserted. FBE (Fast Back to Back Enable) — RO. Not implemented. Hardwired to 0. SEN (SERR Enable) — RO. Not implemented. Hardwired to 0. WCC (Wait Cycle Control) — RO. Not implemented. Hardwired to 0. PER (Parity Error Response) — RO. Not implemented. Hardwired to 0. VPS (VGA Palette Snoop) — RO. Not implemented. Hardwired to 0. MWI (Memory Write and Invalidate Enable) — RO. Not implemented. Hardwired to 0. SCE (Special Cycle Enable) — RO. Not implemented. Hardwired to 0. BME (Bus Master Enable) — RO. Not implemented. Hardwired to 0. Memory Space Enable (MSE) — RW. 0 = Disable 1 = Enable. Enables memory space accesses to the Thermal registers. IOS (I/O Space) — RO. The Thermal logic does not implement IO Space; therefore, this bit is hardwired to 0. Attribute: Size: Description RO, R/W 16 bits 0 830 Datasheet Thermal Sensor Registers (D31:F6) 23.1.4 STS—Status Address Offset: 06h–07h Default Value: 0010h Bit 15 14 13 12 11 10:9 8 7 6 5 4 Attribute: Size: Description R/WC, RO 16 bits Detected Parity Error (DPE) — R/WC. This bit is set whenever a parity error is seen on the internal interface for this function, regardless of the setting of bit 6 in the command register. Software clears this bit by writing a ‘1’ to this bit location. SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0. Received Master Abort (RMA) — RO. Not implemented. Hardwired to 0. Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0. Signaled Target-Abort (STA) — RO. Not implemented. Hardwired to 0. DEVSEL# Timing Status (DEVT) — RO. Does not apply. Hardwired to 0. Master Data Parity Error (MDPE) — RO. Not implemented. Hardwired to 0. Fast Back to Back Capable (FBC) — RO. Does not apply. Hardwired to 0. Reserved 66 MHz Capable (C66) — RO. Does not apply. Hardwired to 0. Capabilities List Exists (CLIST) — RO. Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. Interrupt Status (IS) — RO. Reflects the state of the INTx# signal at the input of the enable/disable circuit. This bit is a 1 when the INTx# is asserted. This bit is a 0 after the interrupt is cleared (independent of the state of the Interrupt Disable bit in the command register). Reserved 3 2:0 23.1.5 RID—Revision Identification Address Offset: 08h Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID (RID) — RO. Indicates the device specific revision identifier. 23.1.6 PI— Programming Interface Address Offset: 09h Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Programming Interface (PI) — RO. ICH Thermal logic has no standard programming interface. Datasheet 831 Thermal Sensor Registers (D31:F6) 23.1.7 SCC—Sub Class Code Address Offset: 0Ah Default Value: 80h Bit 7:0 Attribute: Size: Description RO 8 bits Sub Class Code (SCC) — RO. Value assigned to ICH Thermal logic. 23.1.8 BCC—Base Class Code Address Offset: 0Bh Default Value: 11h Bit 7:0 Attribute: Size: Description RO 8 bits Base Class Code (BCC) — RO. Value assigned to ICH Thermal logic. 23.1.9 CLS—Cache Line Size Address Offset: 0Ch Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Cache Line Size (CLS) — RO. Does not apply to PCI Bus Target-only devices. 23.1.10 LT—Latency Timer Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Latency Timer (LT) — RO. Does not apply to PCI Bus Target-only devices. 23.1.10.1 HTYPE—Header Type Address Offset: 0Eh Default Value: 00h Bit 7 6:0 Attribute: Size: Description RO 8 bits Multi-Function Device (MFD) — RO. This bit is 0 because a multi-function device only needs to be marked as such in Function 0, and the Thermal registers are not in Function 0. Header Type (HTYPE) — RO. Implements Type 0 Configuration header. 832 Datasheet Thermal Sensor Registers (D31:F6) 23.1.11 BIST—Built-in Self Test Address Offset: 0Fh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Built-in Self Test (BIST) — RO. Not implemented. Hardwired to 00h. 23.1.12 TBAR—Thermal Base Address Offset: 10h–13h Default Value: 00000004h Attribute: Size: RW, RO 32 bits This BAR creates 4K bytes of memory space to signify the base address of Thermal memory mapped configuration registers. This memory space is active when the Command (CMD) register Memory Space Enable (MSE) bit is set and either TBAR[31:12] or TBARH are programmed to a non-zero address. This BAR is owned by the Operating System, and allows the OS to locate the Thermal registers in system memory space. Bit 31:12 11:4 3 2:1 0 Description Thermal Base Address (TBA) — RW. This field provides the base address for the Thermal logic memory mapped configuration registers. 4 KB bytes are requested by hardwiring bits 11:4 to 0s. Reserved Prefetchable (PREF) — RO. Indicates that this BAR is NOT pre-fetchable. Address Range (ADDRNG) — RO. Indicates that this BAR can be located anywhere in 64 bit address space. Space Type (SPTYP) — RO. Indicates that this BAR is located in memory space. 23.1.13 TBARH—Thermal Base High DWord Address Offset: 14h–17h Default Value: 00000000h Attribute: Size: RW, RO 32 bits This BAR extension holds the high 32 bits of the 64 bit TBAR. In conjunction with TBAR, it creates 4 KB of memory space to signify the base address of Thermal memory mapped configuration registers. Bit 31:0 Description Thermal Base Address High (TBAH) — RW. TBAR bits 61:32. Datasheet 833 Thermal Sensor Registers (D31:F6) 23.1.14 SVID—Subsystem Vendor ID Address Offset: 2Ch–2Dh Default Value: 0000h Attribute: Size: R/WO 16 bits This register should be implemented for any function that could be instantiated more than once in a given system. The SVID register, in combination with the Subsystem ID register, enables the operating environment to distinguish one subsystem from the other(s). Software (BIOS) will write the value to this register. After that, the value can be read, but writes to the register will have no effect. The write to this register should be combined with the write to the SID to create one 32-bit write. This register is not affected by D3HOT to D0 reset. Bit 15:0 Description SVID (SVID) — R/WO. These RWO bits have no ICH10 functionality. 23.1.15 SID—Subsystem ID Address Offset: 2Eh–2Fh Default Value: 0000h Attribute: Size: R/WO 16 bits This register should be implemented for any function that could be instantiated more than once in a given system. The SID register, in combination with the Subsystem Vendor ID register make it possible for the operating environment to distinguish one subsystem from the other(s). Software (BIOS) will write the value to this register. After that, the value can be read, but writes to the register will have no effect. The write to this register should be combined with the write to the SVID to create one 32-bit write. This register is not affected by D3HOT to D0 reset. Bit 15:0 Description SID (SAID) — R/WO. These RWO bits have no ICH10 functionality. 23.1.16 CAP_PTR —Capabilities Pointer Address Offset: 34h Default Value: 50h Bit 7:0 Attribute: Size: Description RO 8 bits Capability Pointer (CP) — RO. Indicates that the first capability pointer offset is offset 50h (Power Management Capability). 23.1.17 Offset 3Ch – INTLN—Interrupt Line Address Offset: 3Ch Default Value: 00h Bit 7:0 Attribute: Size: Description RW 8 bits Interrupt Line — RW. ICH10 hardware does not use this field directly. It is used to communicate to software the interrupt line that the interrupt pin is connected to. 834 Datasheet Thermal Sensor Registers (D31:F6) 23.1.18 INTPN—Interrupt Pin Address Offset: 3Dh Default Value: TBD Bit 7:4 3:0 Reserved Interrupt Pin — RO. This reflects the value of the Device 31 interrupt pin bits 27:24 (TTIP) in chipset configuration space. Attribute: Size: Description RO 8 bits 23.1.19 TBARB—BIOS Assigned Thermal Base Address Address Offset: 40h–43h Default Value: 00000004h Attribute: Size: RW,RO 32 bits This BAR creates 4 KB of memory space to signify the base address of Thermal memory mapped configuration registers. This memory space is active when TBARB.SPTYPEN is asserted. This BAR is owned by the BIOS, and allows the BIOS to locate the Thermal registers in system memory space. If both TBAR and TBARB are programmed, then the OS and BIOS each have their own independent “view” of the Thermal registers, and must use the TSIU, TCIU, and TBIU registers to denote Thermal registers ownership/ availability. Bit 31:12 11:4 3 2:1 Description Thermal Base Address (TBA) — RW. This field provides the base address for the Thermal logic memory mapped configuration registers. 4K B bytes are requested by hardwiring bits 11:4 to 0s. Reserved Prefetchable (PREF) — RO. Indicates that this BAR is NOT pre-fetchable. Address Range (ADDRNG) — RO. Indicates that this BAR can be located anywhere in 64 bit address space. Space Type Enable (SPTYPEN) — RW. 0 0 = Disable. 1 = Enable. When set to 1b by software, enables the decode of this memory BAR. 23.1.20 TBARBH—BIOS Assigned Thermal Base High DWord Address Offset: 44h–47h Default Value: 00000000h Attribute: Size: RW 32 bits This BAR extension holds the high 32 bits of the 64 bit TBARB. Bit 31:0 Description Thermal Base Address High (TBAH) — RW. TBAR bits 61:32. Datasheet 835 Thermal Sensor Registers (D31:F6) 23.1.21 PID—PCI Power Management Capability ID Address Offset: 50h–51h Default Value: 0001h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) — RO. Indicates that this is the last capability structure in the list. Cap ID (CAP) — RO. Indicates that this pointer is a PCI power management capability 23.1.22 PC—Power Management Capabilities Address Offset: 52h–53h Default Value: 0022h Bit 15:11 10 9 8:6 5 4 3 2:0 Attribute: Size: Description RO 16 bits PME_Support — RO. Indicates PME# is not supported D2_Support — RO. The D2 state is not supported. D1_Support — RO. The D1 state is not supported. Aux_Current — RO. PME# from D3COLD state is not supported, therefore this field is 000b. Device Specific Initialization (DSI) — RO. Indicates that device-specific initialization is required. Reserved PME Clock (PMEC) — RO. Does not apply. Hardwired to 0. Version (VS) — RO. Indicates support for Revision 1.2 of the PCI Power Management Specification. 836 Datasheet Thermal Sensor Registers (D31:F6) 23.1.23 PCS—Power Management Control And Status Address Offset: 54h–57h Default Value: 0000h Bit 31:24 23 22 21:16 15 14:9 8 7:4 Attribute: Size: Description RW, RO 32 bits Data — RO. Does not apply. Hardwired to 0s. Bus Power/Clock Control Enable (BPCCE) — RO. Hardwired to 0. B2/B3 Support (B23) — RO. Does not apply. Hardwired to 0. Reserved PME Status (PMES) — RO. This bit is always 0, since this PCI Function does not generate PME# Reserved PME Enable (PMEE) — RO. This bit is always zero, since this PCI Function does not generate PME# Reserved No Soft Reset — RO. When set (1), this bit indicates that devices transitioning from D3HOT to D0 because of PowerState commands do not perform an internal reset. Configuration context is preserved. Upon transition from D3HOT to D0 initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. Reserved Power State (PS) — R/W. This field is used both to determine the current power state of the Thermal controller and to set a new power state. The values are: 00 = D0 state 11 = D3HOT state 3 2 1:0 If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. When in the D3HOT states, the Thermal controller’s configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. When software changes this value from the D3HOT state to the D0 state, no internal warm (soft) reset is generated. Datasheet 837 Thermal Sensor Registers (D31:F6) 23.2 Thermal Memory Mapped Configuration Registers (Thermal Sensor - D31:F26) The base memory for these thermal memory mapped configuration registers is specified in the TBARB (D31:F6:Offset 40h). The individual registers are then accessible at TBARB + Offset. There are two sensors in the ICH10. Each sensor has a separate configuration register set. Both sensors must be configured together. Table 23-2. Thermal Memory Mapped Configuration Register Address Map Offset 1h 2h 4h 8h 0Eh 41h 42h 44h 48h 4Eh 83h C3h Mnemonic TS0E TS0S TS0TTP TS0C0 TS0PC TS1E TS1S TS1TTP TS1C0 TS1PC TS0LOCK TS1LOCK Register Name Thermal Sensor 0 Enable Thermal Sensor 0 Enable Thermal Sensor 0 Catastrophic Trip Point Thermal Sensor 0 Catastrophic Lock Down Thermal Sensor 0 Policy Control Thermal Sensor 1 Enable Thermal Sensor 1 Enable Thermal Sensor 1 Catastrophic Trip Point Thermal Sensor 1 Catastrophic Lock Down Thermal Sensor 1 Policy Control Thermal Sensor 0 Register Lock Control Thermal Sensor 1 Register Lock Control Default 00h 00h 00000000h 00h 00h 00h 00h 00000000h 00h 00h 00h 00h Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 23.2.1 TSxE—Thermal Sensor [1:0] Enable Offset Address: Sensor 0: TBARB+01h Sensor 1: TBARB+41h Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bit Thermal Sensor Enable (TSE) — R/W. BIOS shall always program this register to the value BAh to enable the thermal sensor. All other values are reserved. 838 Datasheet Thermal Sensor Registers (D31:F6) 23.2.2 TSxS—Thermal Sensor[1:0] Status Offset Address: Sensor 0: TBARB+02h Sensor 1: TBARB+42h Default Value: 00h Bit 7 6:0 Attribute: Size: Description RO 8 bit Catastrophic Trip Indicator (CTI) — RO. 0 = The temperature is below the catastrophic setting. 1 = The temperature is above the catastrophic setting. Reserved 23.2.3 TSxTTP—Thermal Sensor [1:0] Catastrophic Trip Point Offset Address: Sensor 0: TBARB+04h Sensor 1: TBARB+44h Default Value: 00h Bit 31:8 Reserved Catastrophic Trip Point Setting (CTPS) — R/W. These bits set the catastrophic trip point. BIOS will program these bits. These bits are lockable via TSCO.bit 7. Attribute: Size: Description R/W 32 bit 7:0 23.2.4 TSxCO—Thermal Sensor [1:0] Catastrophic Lock-Down Offset Address: Sensor 0: TBARB+08h Sensor 1: TBARB+48h Default Value: 00h Bit Attribute: Size: Description R/W 8 bit Lock bit for Catastrophic (LBC) — R/W. 7 0 = Catastrophic programming interface is unlocked 1 = Locks the Catastrophic programming interface including TSTTP.bits[7:0]. This bit may only be set to a 0 by a hardware reset. Writing a 0 to this bit has no effect. 6:0 Reserved Datasheet 839 Thermal Sensor Registers (D31:F6) 23.2.5 TSxPC—Thermal Sensor [1:0] Policy Control Offset Address: Sensor 0: TBARB+0Eh Sensor 1: TBARB+4Eh Default Value: 00h Bit Policy Lock-Down Bit — R/W. 0 = This register can be programmed and modified. 1 = Prevents writes to this register. 7 NOTE: TSCO.bit 7 and TSLOCK.bit2 must also be 1 when this bit is set to 1. This bit may only be set to a 0 by a hardware reset. Writing a 0 to this bit has no effect. Catastrophic Power-Down Enable — R/W. 6 1 = When set to 1, the power management logic unconditionally transitions to the S5 state when a catastrophic temperature is detected by the sensor. Reserved Attribute: Size: Description R/W 8 bit 5:0 23.2.6 TSxLOCK—Thermal Sensor [1:0] Register Lock Control Offset Address: Sensor 0: TBARB+83h Sensor 1: TBARB+C3h Default Value: 00h Bit 7:3 2 1:0 Reserved Lock Control — R/W. This bit must be set to 1 when TSPC.bit7 is set to 1. Reserved Attribute: Size: Description R/W 8 bit §§ 840 Datasheet