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Intel® Celeron® M Processor on 90 nm Process Datasheet January 2007 Document Number: 303110-008 IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Celeron® M processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number for details. Intel, Celeron, MMX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright© 2004–2007, Intel Corporation. All rights reserved. 2 Datasheet Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 8 Low Power Features ................................................................................................ 11 2.1 Clock Control and Low Power States .................................................................... 11 2.1.1 Normal State ......................................................................................... 11 2.1.2 AutoHALT Power-Down State ................................................................... 11 2.1.3 Stop-Grant State.................................................................................... 11 2.1.4 HALT/Grant Snoop State ......................................................................... 12 2.1.5 Sleep State ........................................................................................... 12 2.1.6 Deep Sleep State ................................................................................... 13 2.2 FSB Low Power Enhancements ............................................................................ 13 2.3 Processor Power Status Indicator (PSI#) Signal..................................................... 14 Electrical Specifications ........................................................................................... 15 3.1 Power and Ground Pins ...................................................................................... 15 3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking ........................................... 15 3.2 Voltage Identification and Power Sequencing ........................................................ 15 3.3 Catastrophic Thermal Protection .......................................................................... 17 3.4 Signal Terminations and Unused Pins ................................................................... 17 3.5 FSB Frequency Select Signals (BSEL[1:0])............................................................ 17 3.6 FSB Signal Groups............................................................................................. 17 3.7 CMOS Signals ................................................................................................... 19 3.8 Maximum Ratings.............................................................................................. 19 3.9 Processor DC Specifications ................................................................................ 19 Package Mechanical Specifications and Pin Information .......................................... 29 4.1 Processor Pinout and Pin List .............................................................................. 37 4.2 Alphabetical Signals Reference ............................................................................ 55 Thermal Specifications and Design Considerations .................................................. 63 5.1 Thermal Specifications ....................................................................................... 65 5.1.1 Thermal Diode ....................................................................................... 65 5.1.2 Thermal Diode Offset .............................................................................. 66 5.1.3 Intel® Thermal Monitor........................................................................... 67 2 3 4 5 Datasheet 3 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 Clock Control States .................................................................................................11 Illustration of Deep Sleep State VCC Static and Ripple Tolerances for the Celeron M Processor (Deep Sleep State): VID=1.260 V .......................................22 Illustration of Active State VCC Static and Ripple Tolerances for the Celeron M Processor ULV: VID=0.940 V ............................................................24 Illustration of Deep Sleep State VCC Static and Ripple Tolerances for the Celeron M Processor ULV: VID=0.940 V ............................................................25 Active VCC and ICC Loadline for the Celeron M Processor: Standard Voltage and Ultra Low Voltage ......................................................................25 Deep Sleep VCC and ICC Loadline for Celeron M Processors: Standard Voltage and Ultra Low Voltage ......................................................................26 Micro-FCPGA Package Top and Bottom Isometric Views .................................................29 Micro-FCPGA Package - Top and Side Views .................................................................30 Micro-FCPGA Package - Bottom View...........................................................................31 Micro-FCBGA Package Top and Bottom Isometric Views .................................................33 Micro-FCBGA Package Top and Side Views ...................................................................34 Micro-FCBGA Package Bottom View.............................................................................36 The Coordinates of the Processor Pins As Viewed from the Top of the Package ..................38 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Voltage Identification Definition ..................................................................................16 FSB Pin Groups ........................................................................................................18 Processor DC Absolute Maximum Ratings.....................................................................19 Voltage and Current Specifications..............................................................................20 Voltage Tolerances for the Celeron M Processor (Deep Sleep State).................................22 Voltage Tolerances for the Celeron M Processor ULV (Active State)..................................23 Voltage Tolerances for the Celeron M Processor ULV (Deep Sleep State) ..........................24 FSB Differential BCLK Specifications ............................................................................26 AGTL+ Signal Group DC Specifications ........................................................................27 CMOS Signal Group DC Specifications..........................................................................27 Open Drain Signal Group DC Specifications ..................................................................28 Micro-FCPGA Package Dimensions ..............................................................................32 Micro-FCPGA Package Dimensions ..............................................................................35 Pin Listing by Pin Name .............................................................................................39 Pin Listing by Pin Number ..........................................................................................46 Signal Description.....................................................................................................55 Power Specifications for the Celeron M Processor ..........................................................64 Thermal Diode Interface ............................................................................................66 Thermal Diode Specification .......................................................................................66 4 Datasheet Revision History Revision -001 Initial release Updates include: • Document Title from “Intel® Celeron® M Processor Ultra Low Voltage on 90 nm Process” to “Intel® Celeron® M Processor on 90 nm Process” • Added Micro-FCPGA package information throughout Chapter 4 • Celeron® M Processor 360 and 350 DC and Thermal and Power Specifications (Updated Table 4 and Table 17) Updates include: • Added resources to the Reference Table 1 • BSEL[1:] literature updated • Celeron M processor 370 and 373 DC and Thermal and Power Specifications (Updated Table 4 and Table 17) • Execute Disable bit and Lead Free feature referenced • • • -006 • -007 -008 • • Celeron M processor 383 DC and Thermal and Power Specifications (Updated Table Table 4 and Table 17) Added Celeron M processor 380 specifications Updated Celeron M processor 370, 360J, 350J and Celeron M processor ULV 383, 373 specifications for optimized VID (T Table 4 and Table 17) Updated Celeron M processor ULV 383, 373 TDP specification (Table 17) Added Celeron M processor 390 specifications Updated Celeron M 390 Thermal Specifications Description Date July 2004 -002 August 2004 -003 January 2005 -004 -005 April 2005 July 2005 July 2005 January 2006 January 2007 § Datasheet 5 6 Datasheet Introduction 1 Introduction The Intel® Celeron® M processor based on 90 nm process technology is a highperformance, low-power mobile processor with several enhancements over previous mobile Celeron processors. Throughout this document, the term Celeron M processor signifies Intel Celeron M processor based on 90 nm technology. This document contains specification for the Celeron M processor 390, 380, 370, 360J, 360, 350J, 350Δ and the Celeron M processor Ultra Low Voltage 383, 373, 353Δ. Note: ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number for details. The following list provides some of the key features on this processor: • Manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect. • Supports Intel Architecture with Dynamic Execution • On-die, primary 32-KB instruction cache and 32-KB write-back data cache • On-die 1-MB (512-KB for Celeron M processor Ultra Low Voltage 373 and 353) second level cache with Advanced Transfer Cache Architecture, 8-way set associativity and ECC (Error Correcting Code) Support. • Data Prefetch Logic • Streaming SIMD extensions 2 (SSE2) • 400-MHz, source-synchronous front side bus (FSB) • Micro-FCPGA and Micro-FCBGA (ULV parts available only in Micro-FCBGA) packaging technologies (including lead free technology for the Micro-FCBGA package for Celeron M processors 390, 380, 370, 383, 373, and 353). • Execute Disable Bit support for enhanced security (available on processors with CPU Signature=06D8h and recommended for implementation on Intel® 915/910 Express Chipset-based platforms only) The Celeron M processor maintains support for MMX™ technology and Internet Streaming SIMD instructions and full compatibility with IA-32 software. The on-die, 32-KB Level 1 instruction and data caches and the 1-MB (512-KB for Celeron M processor Ultra Low Voltage 373 and 353) Level 2 cache with advanced transfer cache architecture enable significant performance improvement over existing mobile processors. The processor’s data prefetch logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. The streaming SIMD extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. The Celeron M processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The 400-MHz FSB uses source-synchronous transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data Datasheet 7 Introduction transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced Gunning Transceiver Logic (AGTL+) signalling technology, a variant of (GTL+) signaling technology with low power enhancements. The Celeron M processor utilizes socketable Micro Flip-Chip Pin Grid Array (MicroFCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is referred to as the mPGA479M socket. 1.1 Terminology Term Definition A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Refers to the interface between the processor and system core logic (also known as the chipset components). # Front Side Bus (FSB) 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document Intel® Celeron® M Processor Specification Update Document Location1 http://www.intel.com/ design/mobile/specupdt/ 300303.htm http://www.intel.com/ design/mobile/datashts/ 305264.htm http://www.intel.com/ design/mobile/specupdt/ 307167.htm http://www.intel.com/ design/chipsets/datashts/ 301473.htm http://www.intel.com/ design/chipsets/specupdt/ 301474.htm http://www.intel.com/ design/chipsets/datashts/ 252613.htm Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset Datasheet Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset Specification Update Intel® I/O Controller Hub 6 (ICH6) Family Datasheet Intel® I/O Controller Hub 6 (ICH6) Family Specification Update Intel® 855PM Chipset Memory Controller Hub (MCH) Datasheet 8 Datasheet Introduction Document Intel® 855PM Chipset MCH DDR 333/200/266 MHz Specification Update Intel® 855GM/GME Chipset Graphics and Memory Controller Hub (GMCH) Datasheet Intel® 855GM/GME Chipset Graphics and Memory Controller Hub (GMCH) Specification Update Document Location1 http://www.intel.com/ design/chipsets/specupdt/ 253488.htm http://www.intel.com/ design/chipsets/datashts/ 252615.htm http://www.intel.com/ design/chipsets/specupdt/ 253572.htm http://www.intel.com/ Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet design/mobile/datashts/ 252337.htm Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet Specification Update IA-32 Intel® Architecture Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A- M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide http://www.intel.com/ design/pentium4/manuals/ index_new.htm http://www.intel.com/ design/chipsets/specupdt/ 252663.htm § Datasheet 9 Introduction 10 Datasheet Low Power Features 2 2.1 Low Power Features Clock Control and Low Power States The Celeron M processor supports the AutoHALT Power-Down, Stop Grant, Sleep, Deep Sleep states for optimal power management. See Figure 1 for a visual representation of the processor low-power states. Figure 1. Clock Control States STPCLK# asserted Normal STPCLK# deasserted Stop Grant SLP# deasserted halt break HLT instruction STPCLK# asserted SLP# asserted Sleep snoop snoop STPCLK# serviced occurs deasserted DPSLP# de-asserted DPSLP# asserted Auto Halt snoop occurs snoop serviced HALT/ Grant Snoop Deep Sleep V0001-04 Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt 2.1.1 Normal State This is the normal operating state for the processor. 2.1.2 AutoHALT Power-Down State AutoHALT Power-Down is a low-power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#,INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately initialize itself. The system can generate a STPCLK# while the processor is in the AutoHALT PowerDown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Power-Down state, the processor will process bus snoops and interrupts. 2.1.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop-Grant Acknowledge special bus cycle. Datasheet 11 Low Power Features Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.4). A transition to the Sleep state (see Section 2.1.5) will occur with the assertion of the SLP# signal. While in the Stop-Grant state, SMI#, INIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the FSB, and it will latch interrupts delivered on the FSB. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state. 2.1.4 HALT/Grant Snoop State The processor will respond to snoop or interrupt transactions on the FSB while in StopGrant state or in AutoHALT Power-Down state. During a snoop or interrupt transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant state or AutoHALT Power-Down state, as appropriate. 2.1.5 Sleep State A low power state in which the processor maintains its context, maintains the phaselocked loop (PLL), and has stopped all internal clocks. The Sleep state can be entered only from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor 12 Datasheet Low Power Features is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state by asserting the DPSLP# pin. (See Section 2.1.6.) While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur. 2.1.6 Deep Sleep State Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on 855PM chipset family based platforms with compatible clock generator chips are as follows: • Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The clock chip will stop/tristate BCLK within two BCLKs +/- a few nanoseconds. • Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The clock chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6 BCLK periods later. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 30 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the StopGrant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. 2.2 FSB Low Power Enhancements The Celeron M processor incorporates the FSB low power enhancements: • Dynamic FSB Power Down • BPRI# control for address and control input buffers • Dynamic On Die Termination disabling • Low VCCP (I/O termination voltage) The Celeron M processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. The on-die termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times. Datasheet 13 Low Power Features 2.3 Processor Power Status Indicator (PSI#) Signal The Celeron M processor incorporates the PSI# signal that is asserted when the processor is in a low power (Deep Sleep) state. This signal is asserted upon Deep Sleep entry and deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. § 14 Datasheet Electrical Specifications 3 3.1 Electrical Specifications Power and Ground Pins For clean, on-chip power distribution, the Celeron M processor has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please refer to the platform design guides for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Celeron M processor core frequency is a multiple of the BCLK[1:0] frequency. The Celeron M processor uses a differential clocking implementation. 3.2 Voltage Identification and Power Sequencing The Celeron M processor uses six voltage identification pins, VID[5:0], to support automatic selection of power supply voltages. The VID pins for Celeron M processor are CMOS outputs driven by the processor VID circuitry. Table 1 specifies the voltage level corresponding to the state of VID[5:0]. Datasheet 15 Electrical Specifications Table 1. Voltage Identification Definition VID 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vcc V 1.708 1.692 1.676 1.660 1.644 1.628 1.612 1.596 1.580 1.564 1.548 1.532 1.516 1.500 1.484 1.468 1.452 1.436 1.420 1.404 1.388 1.372 1.356 1.340 1.324 1.308 1.292 1.276 1.260 1.244 1.228 1.212 VID 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vcc V 1.196 1.180 1.164 1.148 1.132 1.116 1.100 1.084 1.068 1.052 1.036 1.020 1.004 0.988 0.972 0.956 0.940 0.924 0.908 0.892 0.876 0.860 0.844 0.828 0.812 0.796 0.780 0.764 0.748 0.732 0.716 0.700 16 Datasheet Electrical Specifications 3.3 Catastrophic Thermal Protection The Celeron M processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. 3.4 Signal Terminations and Unused Pins All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Celeron M processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected. The TEST1 and TEST2 pins must have a stuffing option connection to VSS separately via 1-kΩ, pull-down resistors. 3.5 FSB Frequency Select Signals (BSEL[1:0]) The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and Intel 915PM/GM/ GMS and 910GML Express Chipset on the platform. These signals must be left unconnected on platforms designed with the Celeron M processor and the Intel 852/ 855 chipset families. 3.6 FSB Signal Groups In order to simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2 identifies which signals are common clock, source synchronous, and asynchronous. Datasheet 17 Electrical Specifications Table 2. FSB Pin Groups Signal Group Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY# AGTL+ Common Clock Input AGTL+ Common Clock I/O Signals REQ[4:0]#, A[16:3]# AGTL+ Source Synchronous I/O Synchronous to assoc. strobe A[31:17]# D[15:0]#, DINV0# D[31:16]#, DINV1# D[47:32]#, DINV2# D[63:48]#, DINV3# AGTL+ Strobes CMOS Input Open Drain Output CMOS Output CMOS Input Open Drain Output FSB Clock Power/Other Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK Clock Associated Strobe ADSTB[0]# ADSTB[1]# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, IERR#, PROCHOT#, THERMTRIP# PSI#, VID[5:0], BSEL[1:0] TCK, TDI, TMS, TRST# TDO BCLK[1:0], ITP_CLK[1:0]2 COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, VCC, VCCA[3:0], VCCP, VCCQ[1:0], VCC_SENSE, VSS, VSS_SENSE NOTES: 1. BPM[2:0}# and PRDY# are AGTL+ output only signals. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 18 Datasheet Electrical Specifications 3.7 CMOS Signals CMOS input signals are shown in Table 2. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize open drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them. See Section 3.9 for the CMOS signal group DC specifications. 3.8 Maximum Ratings Table 3 lists the processor’s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from electro static discharge (ESD), one should always take precautions to avoid high static voltages or electric fields. Table 3. Symbol TSTORAGE VCC VinAGTL+ VinAsynch_CMOS Processor DC Absolute Maximum Ratings Parameter Processor Storage Temperature Any Processor Supply Voltage with Respect to VSS AGTL+ Buffer DC Input Voltage with Respect to VSS CMOS Buffer DC Input Voltage with Respect to VSS Min -40 -0.3 -0.1 -0.1 Max 85 1.6 1.6 1.6 Unit °C V V V Notes 2 1 1, 2 1, 2 NOTES: 1. This rating applies to any processor pin. 2. Contact Intel for storage requirements in excess of one year. 3.9 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 2 for pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 9. DC specifications for the CMOS group are listed in Table 10. Table 4 through Table 10 list the DC specifications for the Celeron M processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Active mode load line specifications apply in all states except in the Deep Sleep state. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the Celeron M processor are at Tjunction = 100°C. Care should be taken to read all notes associated with each parameter. Datasheet 19 Electrical Specifications Table 4. Symbol VCC1 VCC2 VCC3 VCCULV VCC,BOOT VCCP VCCA ICCDES Voltage and Current Specifications (Sheet 1 of 2) Parameter Intel® Celeron® M Processor 360, 350 Core VCC Celeron M Processor 390, 380, 370, 360J, 350J Core VCC Celeron M Processor Ultra Low Voltage 383, 373 Core VCC Celeron M Processor Ultra Low Voltage 353 Core VCC Default VCC Voltage for Initial Power-up AGTL+ Termination Voltage PLL Supply Voltages ICC for Celeron M processor Recommended Design Target ICC for Celeron M processor 390, 380, 370, 360J, 350J & VCC2 ICC for Celeron M processor 360, 350 &1.260 V ICC for Celeron M processor Ultra Low Voltage 383, 373 & VCC3 ICC for Celeron M processor Ultra Low Voltage 353 & 0.940 V ICC Auto-Halt & Stop-Grant for Celeron M Processor 390, 380, 370, 360J, 350J & VCC2 ICC Auto-Halt & Stop-Grant for Celeron M Processor 360, 350 & 1.260 V ICC Auto-Halt & Stop-Grant for Celeron M processor Ultra Low Voltage 383, 373 & VCC3 ICC Auto-Halt & Stop-Grant for Celeron M processor Ultra Low Voltage 353 & 0.940 V ICC Sleep for Celeron M processor 390, 380, 370, 360J, 350J & VCC2 ICC Sleep for Celeron M processor 360, 350 & 1.260 V ICC Sleep for Celeron M processor Ultra Low Voltage 383, 373 & VCC3 ICC Sleep for Celeron M processor Ultra Low Voltage 353 & 0.940 V ICC Deep Sleep for Celeron M processor 390, 380, 370, 360J, 350J & VCC2 ICC Deep Sleep for Celeron M processor 360, 350 & 1.260 V 1.14 0.997 1.71 1.425 1.004 0.876 0.940 1.20 1.05 1.8 1.5 1.26 1.102 1.89 1.575 25 21.0 21.0 7.0 7.0 16.4 16.4 3.4 3.4 16.1 16.1 3.3 3.3 15.5 15.5 Min Typ 1.260 1.292 0.956 Max Unit V V V V V V V A A A A A A A A A A A A A A A Notes 1,2,9 2,9,11 2,9,11, 12 1,2,9 2 2 2,10 5 3,9,11 3,9 3,9,11, 12 3,9 4,9,11 4,9 4,9,11, 12 4,9 4,9,11 4,9 4,9,11, 12 4,9 4,9,11 4,9 ICC ICCULV IAH, ISGNT IAHULV, ISGNTULV ISLP ISLPULV IDSLP 20 Datasheet Electrical Specifications Table 4. Symbol Voltage and Current Specifications (Sheet 2 of 2) Parameter ICC Deep Sleep for Celeron M processor Ultra Low Voltage 383, 373 & VCC3 ICC Deep Sleep for Celeron M processor Ultra Low Voltage 353 & 0.940 V VCC power supply current slew rate ICC for VCCA Supply ICC for VCCP supply Min Typ Max 3.0 3.0 0.5 120 2.5 Unit A A A/ns mA A Notes 4,9,11, 12 4,9 6, 7 IDSLPULV dICC/DT ICCA ICCP NOTES: 1. The typical values shown are the VID encoded voltages. Static and ripple tolerances (for minimum and maximum voltages) are defined in the loadline tables i.e., Table 5 through Table 7. 2. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at VCC,STATIC (nominal) under maximum signal loading conditions. 4. Specified at the VID voltage. 5. The ICCDES(max) specification comprehends future processor HFM frequencies. Platforms should be designed to this specification. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Measured at the bulk capacitors on the motherboard. 8. Adherence to loadline specification for the Celeron M processor is required to ensure reliable processor operation. 9. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/ processor_number for details. 10. The Celeron M processor will support VCCA supply voltage of either 1.8 V ±5% or 1.5 V ±5%. Either one of these voltages can be used on the platform. 11. These are VID values. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings. Actual voltage supplied to the processor should be as specified in the load lines in Figure 5 and Figure 6. Adherence to load line specifications is required to ensure reliable processor operation. 12. For 350J and 360J, CPU signature = 06D8h. Datasheet 21 Electrical Specifications Table 5. Voltage Tolerances for the Celeron M Processor (Deep Sleep State) VID = 1.260 V, Offset = 1.2% Mode ICC, A 0.0 1.0 2.1 3.1 4.1 5.2 Deep Sleep 6.2 7.2 8.3 9.3 10.3 11.4 12.4 13.4 14.5 15.5 VCC, V 1.245 1.242 1.239 1.236 1.232 1.229 1.226 1.223 1.220 1.217 1.214 1.211 1.208 1.205 1.201 1.198 Static Min 1.226 1.223 1.220 1.217 1.214 1.210 1.207 1.204 1.201 1.198 1.195 1.192 1.189 1.186 1.183 1.179 Max 1.264 1.261 1.258 1.254 1.251 1.248 1.245 1.242 1.239 1.236 1.233 1.230 1.227 1.223 1.220 1.217 Min 1.216 1.213 1.210 1.207 1.204 1.200 1.197 1.194 1.191 1.188 1.185 1.182 1.179 1.176 1.173 1.169 Ripple Max 1.274 1.271 1.268 1.264 1.261 1.258 1.255 1.252 1.249 1.246 1.243 1.240 1.237 1.233 1.230 1.227 Figure 2. Illustration of Deep Sleep State VCC Static and Ripple Tolerances for the Celeron M Processor (Deep Sleep State): VID=1.260 V VID = 1.260: Deep Sleep 1.280 1.260 1.240 1.220 1.200 1.180 1.160 0.0 2.0 4.0 6.0 8.0 10.0 12.0 1.245 STATIC Static Min Static Max Ripple Min Ripple Max 22 Datasheet Electrical Specifications Table 6. Voltage Tolerances for the Celeron M Processor ULV (Active State) VID = 0.940 V, Offset=0% Mode ICC, A 0 0.3 0.5 0.8 1.0 1.3 1.6 1.8 2.1 2.3 2.6 2.9 3.1 Active 3.4 3.6 3.9 4.1 4.4 4.7 4.9 5.2 5.4 5.7 6.0 6.2 6.5 6.7 7.0 VCC, V 0.940 0.939 0.938 0.938 0.937 0.936 0.935 0.935 0.934 0.933 0.932 0.931 0.931 0.930 0.929 0.928 0.928 0.927 0.926 0.925 0.924 0.924 0.923 0.922 0.921 0.921 0.920 0.919 Static Min 0.926 0.925 0.924 0.924 0.923 0.922 0.921 0.920 0.920 0.919 0.918 0.917 0.917 0.916 0.915 0.914 0.913 0.913 0.912 0.911 0.910 0.910 0.909 0.908 0.907 0.906 0.906 0.905 Max 0.954 0.953 0.953 0.952 0.951 0.950 0.949 0.949 0.948 0.947 0.946 0.946 0.945 0.944 0.943 0.942 0.942 0.941 0.940 0.939 0.939 0.938 0.937 0.936 0.935 0.935 0.934 0.933 Min 0.916 0.915 0.914 0.914 0.913 0.912 0.911 0.910 0.910 0.909 0.908 0.907 0.907 0.906 0.905 0.904 0.903 0.903 0.902 0.901 0.900 0.900 0.899 0.898 0.897 0.896 0.896 0.895 Ripple Max 0.964 0.963 0.963 0.962 0.961 0.960 0.959 0.959 0.958 0.957 0.956 0.956 0.955 0.954 0.953 0.952 0.952 0.951 0.950 0.949 0.949 0.948 0.947 0.946 0.945 0.945 0.944 0.943 Datasheet 23 Electrical Specifications Figure 3. Illustration of Active State VCC Static and Ripple Tolerances for the Celeron M Processor ULV: VID=0.940 V VID = 0.940: Active 0.970 0.960 0.950 0.940 0.930 0.920 0.910 0.900 0.890 VCC, V 0.940 0 1 2 3 ICC, A 4 5 6 STATIC S tatic Min S tatic Max Ripple Min Ripple Max Table 7. Voltage Tolerances for the Celeron M Processor ULV (Deep Sleep State) VID = 0.940 V, Offset=0% Mode ICC, A 0 0.2 0.4 0.6 0.8 1.0 1.2 Active 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VCC, V 0.929 0.928 0.928 0.927 0.926 0.926 0.925 0.925 0.924 0.923 0.923 0.922 0.922 0.921 0.920 0.920 Static Min 0.915 0.914 0.913 0.913 0.912 0.912 0.911 0.910 0.910 0.909 0.909 0.908 0.907 0.907 0.906 0.906 Max 0.943 0.942 0.942 0.941 0.940 0.940 0.939 0.939 0.938 0.937 0.937 0.936 0.936 0.935 0.934 0.934 Min 0.905 0.904 0.903 0.903 0.902 0.902 0.901 0.900 0.900 0.899 0.899 0.898 0.897 0.897 0.896 0.896 Ripple Max 0.953 0.952 0.952 0.951 0.950 0.950 0.949 0.949 0.948 0.947 0.947 0.946 0.946 0.945 0.944 0.944 24 Datasheet Electrical Specifications Figure 4. Illustration of Deep Sleep State VCC Static and Ripple Tolerances for the Celeron M Processor ULV: VID=0.940 V VID = 0.940V: Deep Sleep 0.960 0.950 0.940 Vcc, V 0.930 0.920 0.910 0.900 0.890 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.929 STATIC Static Min StaticIcc, A Max Ripple Min Ripple Max Figure 5. Active VCC and ICC Loadline for the Celeron M Processor: Standard Voltage and Ultra Low Voltage V CC [V] Slope= -3.0 mV/A VCC Max VCC, DC Max VCC Nom 10mV= RIPPLE VCC, DC Min VCC Min +/-1.5% from Nominal =VR Error 0 I CC max I CC [A] Datasheet 25 Electrical Specifications Figure 6. Deep Sleep VCC and ICC Loadline for Celeron M Processors: Standard Voltage and Ultra Low Voltage VCC [V] Slope= -3.0 mV/A 10mV= RIPPLE Vcc nom - 1.2% +/-1.5% from Nominal =VR Error 0 I CC max Deep Sleep I CC [A] Table 8. Symbol VIH VIL VCROSS ΔVCROSS VTH ILI Cpad FSB Differential BCLK Specifications Parameter Input High Voltage Input Low Voltage Crossing Voltage Range of Crossing Points Threshold Region Input Leakage Current Pad Capacitance 1.8 2.3 0.25 N/A VCROSS - 0.100 Min 0.660 Typ 0.710 0 0.35 N/A 0.55 0.140 VCROSS + 0.100 ± 100 2.75 Max 0.850 Unit V V V V V µA pF 2 6 3 4 5 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis. 4. For Vin between 0 V and VIH. 5. Cpad includes die capacitance only. No package parasitics are included. 6. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2. 26 Datasheet Electrical Specifications Table 9. Symbol VCCP GTLREF VIH VIL VOH RTT RON ILI Cpad AGTL+ Signal Group DC Specifications Parameter I/O Voltage Reference Voltage Input High Voltage Input Low Voltage Output High Voltage Termination Resistance Buffer On Resistance Input Leakage Current Pad Capacitance 1.8 2.3 47 17.7 Min 0.997 2/3 VCCP - 2% GTLREF + 0.1 -0.1 VCCP 55 24.7 63 32.9 ±100 2.75 Ω Ω µA pF Typ 1.05 2/3 VCCP Max 1.102 2/3 VCCP + 2% VCCP + 0.1 GTLREF - 0.1 Unit V V V V 6 3,6 2,4 6 7 5 8 9 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications in Chapter 3. 5. This is the pull-down driver resistance. Refer to processor I/O buffer models for I/V characteristics. Measured at 0.31*VCCP. RON (min) = 0.38*RTT, RON (typ) = 0.45*RTT, RON (max) = 0.52*RTT. 6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics. 8. Specified with on die RTT and RON are turned off. 9. Cpad includes die capacitance only. No package parasitics are included. Table 10. Symbol VCCP VIH VIL VOH VOL IOH IOL ILI Cpad CMOS Signal Group DC Specifications Parameter I/O Voltage Input High Voltage Input Low Voltage CMOS Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current Pad Capacitance 1.0 2.3 Min 0.997 0.7*VCCP -0.1 0.9*VCCP -0.1 1.49 1.49 VCCP 0 Typ 1.05 Max 1.102 VCCP+0.1 0.3*VCCP VCCP+0.1 0.1*VCCP 4.08 4.08 ±100 3.0 Unit V V V V V mA mA µA pF 2 2, 3 2 2 5 4 6 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VCCP referred to in these specifications refers to instantaneous VCCP. 3. Measured at 0.1*VCCP. 4. Measured at 0.9*VCCP. 5. For Vin between 0 V and VCCP. Measured when the driver is tristated. 6. Cpad includes die capacitance only. No package parasitics are included. Datasheet 27 Electrical Specifications Table 11. Symbol VOH VOL IOL ILO Cpad Open Drain Signal Group DC Specifications Parameter Output High Voltage Output Low Voltage Output Low Current Output Leakage Current Pad Capacitance 1.7 2.3 0 16 Min Typ VCCP 0.20 50 ±200 3.0 Max Unit V V mA µA pF 2 4 5 Notes1 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2 V. 3. VOH is determined by value of the external pull-up resistor to VCCP. 4. For Vin between 0 V and VOH. 5. Cpad includes die capacitance only. No package parasitics are included. § 28 Datasheet Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information The Celeron M processor will be available in 478-pin, Micro-FCPGA and 479-ball, MicroFCBGA packages. Different views of the Micro-FCPGA package are shown in Figure 7 through Figure 9. Package dimensions are shown in Figure 7. Different views of the Micro-FCBGA package are shown in Figure 7 through Figure 9. Package dimensions are shown in Table 8. The Micro-FCBGA package may have capacitors placed in the area surrounding the die. Because the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. Doing so may short the capacitors, and possibly damage the device or render it inactive. The use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting. Figure 7. Micro-FCPGA Package Top and Bottom Isometric Views PACKAGE KEEPOUT CAPACITOR AREA DIE LABEL TOP VIEW BOTTOM VIEW NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 12 for details. Datasheet 29 Package Mechanical Specifications and Pin Information Figure 8. Micro-FCPGA Package - Top and Side Views SUBSTRATE KEEPO UT ZO NE DO NO T CONTACT PACKAG E I N S ID E T H IS L IN E 0 .2 8 6 7 (K 1) 8 p la ce s 5 ( K) 4 p la ce s A 1 .2 5 M A X (A 3) D1 3 5 (D ) Ø 0 .3 2 (B ) 4 7 8 p la ce s E1 3 5 (E) A2 P IN A 1 C O R N ER 2 .0 3 ± 0 .0 8 (A 1) NOTE: Die is centered on the Package. All dimensions in millimeters. Values shown for reference only. Refer to Table 12 for details. 30 Datasheet Package Mechanical Specifications and Pin Information Figure 9. Micro-FCPGA Package - Bottom View 1 4 (K3) AF AD AB Y V T P M K H F D B AE AC AA W U R N L J G E C A 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 14 (K3 ) 25X 1.27 ( e) 2 5X 1.27 (e) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 12 for details. Datasheet 31 Package Mechanical Specifications and Pin Information Table 12. Micro-FCPGA Package Dimensions Symbol A – A1 A2 A3 B D E D1 E1 e K K1 K3 N Pdie W Parameter Overall height, top of the die to package seating plane Overall height, top of die to PCB surface, including socket (Refer to Note 1) Pin length Die height Pin-side capacitor height Pin diameter Package substrate length Package substrate width Die length Die width Pin pitch Package edge keep-out Package corner keep-out Pin-side capacitor boundary Pin count Allowable pressure on the die for thermal solution Package weight Package surface flatness 4.5 0.286 – 0.28 34.9 34.9 Min 1.88 4.74 1.95 Max 2.02 5.16 2.11 Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm each 689 kPa g mm 0.820 1.25 0.36 35.1 35.1 12.54 6.99 1.27 5 7 14 478 NOTES: 1. Overall height with socket is based on design dimensions of the Micro-FCPGA package with no thermal solution attached. Values are based on design specifications and tolerances. This dimension is subject to change based on socket design, OEM motherboard design or OEM SMT process. 32 Datasheet Package Mechanical Specifications and Pin Information Figure 10. Micro-FCBGA Package Top and Bottom Isometric Views PACKAGE KEEPOUT CAPACITOR AREA LABEL TOP VIEW DIE BOTTOM VIEW Datasheet 33 Package Mechanical Specifications and Pin Information Figure 11. Micro-FCBGA Package Top and Side Views S UBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE INSIDE THIS LINE 7 (K1) 8 places 5 (K) 4 places 0.20 A A2 D1 35 (D) Ø 0.78 (b) 479 places E1 35 (E) K2 PIN A1 CORNER NOTE: Die is centered on the Package. All dimensions in millimeters. Values shown for reference only. Refer to Table 13 for details. 34 Datasheet Package Mechanical Specifications and Pin Information Table 13. Micro-FCPGA Package Dimensions Symbol A A2 b D E D1 E1 e K K1 K2 S N – Pdie W Parameter Overall height, as delivered (Refer to Note 1) Die height Ball diameter Package substrate length Package substrate width Die length Die width Ball pitch Package edge keep-out Package corner keep-out Die-side capacitor height Package edge to first ball center Ball count Solder ball coplanarity Allowable pressure on the die for thermal solution Package weight – 4.5 – 1.625 479 0.2 689 34.9 34.9 Min 2.60 0.82 0.78 35.1 35.1 Max 2.85 Unit mm mm mm mm mm mm mm mm mm mm 0.7 mm mm each mm kPa g 12.54 6.99 1.27 5 7 NOTES: 1. Overall height as delivered. Values are based on design specifications and tolerances. This dimension is subject to change based on OEM motherboard design or OEM SMT process Datasheet 35 Package Mechanical Specifications and Pin Information Figure 12. Micro-FCBGA Package Bottom View 1.625 (S) 4 places AF AD AB Y V T P M K H F D B AE AC AA W U R N L J G E C A 1 3 2 4 5 6 7 8 9 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 1.625 (S) 4 places 25X 1.27 (e) 25X 1.27 (e) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 13 for details. 36 Datasheet Package Mechanical Specifications and Pin Information 4.1 Processor Pinout and Pin List Figure 13 shows the top view pinout of the Celeron M processor. The pin list arranged in two different formats is shown in the following pages. Datasheet 37 Package Mechanical Specifications and Pin Information Figure 13. The Coordinates of the Processor Pins As Viewed from the Top of the Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A VSS IGNNE# IERR# VSS SLP# DBR# VSS BPM[2]# PRDY# BPM [1]# BPM [0]# VCC VSS TDO TCK VSS ITP_CLK ITP_CLK VSS [1] [0] VSS PROC HOT# THERM TRIP# VSS THER MDC THER MDA VSS D[0]# VSS D[6]# D[2]# VSS D[4]# D[1]# VSS A B VSS D[7]# D[3]# VSS D[13]# D[9]# VSS D[5]# B VCCA[1] RSVD VSS SMI# INIT# VSS STP CLK# VCC DPSLP# VSS BPM [3]# VSS PREQ# RESET# VSS TRST# BCLK1 BCLK0 C VSS A20M# RSVD VSS TEST1 VSS VSS TMS TDI VSS BSEL[1] VSS BSEL[0] DPWR# D[8]# VSS DSTBP DSTBN VSS [0]# [0]# VCC VSS D[10]# D[15]# D[12]# DINV [0]# VSS C D VSS D LINT0 VSS FERR# LINT1 PWR GOOD VSS VSS VSS VCCP VSS VCCP VSS VCCP VSS VCCP VCC VSS VCC VSS E PSI# VID[0] VSS VCC VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC VSS D[14]# D[11]# RSVD E F F VSS VID[1] VID[2] VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC TEST2 VSS D[21]# VCCA[0] G RSVD VSS VID[3] VID[4] VCC VSS VCC VSS VSS D[22]# D[17]# VSS G H RS[0]# DRDY# VSS VID[5] VSS VCC VSS VCC D[16]# D[20]# VSS D[29]# DINV [1]# VSS H J VSS LOCK# BPRI# VSS VCC VSS VCC VSS D[23]# VSS D[25]# J K K RS[1]# VSS HIT# HITM# VSS VCCP VSS VCC VSS DSTBN D[31]# [1]# DSTBP VSS [1]# VSS L BNR# RS[2]# VSS DEFER# VCCP VSS VCCP VSS D[18]# D[26]# L M VSS DBSY# TRDY# VSS VSS VCCP VSS VCCP D[24]# D[28]# D[19]# M N VCCA[2] ADS# VSS REQ [1]# A[6]# BR0# VCCP VSS N P R TOP VIEW VCCP VSS VSS D[27]# D[30]# COMP [0] VSS VSS COMP [1] D[38]# REQ [3]# VSS P R VSS REQ [0]# REQ [2]# VSS A[3]# VSS VCCP VSS VCCP VCCQ[0] VSS VSS VCCP VSS VCCP VSS D[39]# D[37]# T U REQ [4]# A[13]# T VSS ADSTB [0]# A[5]# A[9]# VSS VCCP VSS VCCP VSS DINV D[34]# [2]# VSS VSS U A[4]# VCC VSS VCCP VSS D[35]# D[43]# D[41]# V VSS A[7]# VSS VSS VCC VSS VCC D[36]# D[42]# VSS D[44]# V DSTBP DSTBN VSS [2]# [2]# VSS D[47]# D[32]# W A[8]# A[10]# VSS VCCQ[1] VCC VSS VCC VSS VSS W Y Y A[12]# VSS A[15]# A[11]# VSS VCC VSS VCC D[45]# AA VSS A[16]# A[14]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[40]# D[33]# VSS D[46]# AA AB VSS A[24]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[50]# D[48]# VSS AB AC COMP COMP [3] [2] VSS AC RSVD A[20]# A[18]# VSS A[25]# A[19]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D[51]# DINV [3]# VSS VSS D[52]# D[49]# VSS D[53]# VCCA[3] AD VSS A[23]# A[21]# VSS A[26]# A[28]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[60]# VSS D[54]# D[57]# VSS GTLREF AD AE AF AE A[30]# A[27]# VSS A[22]# ADSTB [1]# A[17]# VSS VSS VCC SENSE VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D[59]# D[55]# VSS DSTBN DSTBP VSS [3]# [3]# VSS D[61]# D[63]# AF A[31]# VSS A[29]# VSS RSVD SENSE VCC VSS VCC VSS VCC vss 13 VCC VSS VCC VSS VCC VSS D[58]# VSS D[62]# D[56]# A[31]# 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 VSS VCC Other Pin B2 is depopulated on the Micro-FCPGA package 38 Datasheet Package Mechanical Specifications and Pin Information Table 14. Table 14. Pin Name A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# Pin Listing by Pin Name Pin # AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 C2 N2 U3 AE5 B15 B14 L1 C8 B8 A9 C9 J3 N4 C14 C16 P25 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Source Synch Source Synch Bus Clock Bus Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock CMOS CMOS Power/Other Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input Input Input/ Output Output Output Output Input/ Output Input Input/ Output Output Output Input/ Output Pin Listing by Pin Name Pin # P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 AF4 AC4 AC7 AC3 AD3 AE4 AD2 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Pin Name A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A20M# ADS# ADSTB[0]# ADSTB[1]# BCLK[0] BCLK[1] BNR# BPM[0]# BPM[1]# BPM[2]# BPM[3]# BPRI# BR0# BSEL[1] BSEL[0] COMP[0] Datasheet 39 Package Mechanical Specifications and Pin Information Table 14. Pin Name COMP[1] COMP[2] COMP[3] D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# D[16]# D[17]# D[18]# Pin Listing by Pin Name Pin # P26 AB2 AB1 A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 H23 G25 L23 Signal Buffer Type Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 14. Pin Name D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# Pin Listing by Pin Name Pin # M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output 40 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Name D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# Pin Listing by Pin Name Pin # U26 V24 U25 V26 Y23 AA26 Y25 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 14. Pin Name D[63]# DBR# DBSY# DEFER# DINV[0]# DINV[1]# DINV[2]# DINV[3]# DPSLP# DPWR# DRDY# DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR# GTLREF HIT# HITM# IERR# Pin Listing by Pin Name Pin # AF26 A7 M2 L4 D25 J26 T24 AD20 B7 C19 H2 C23 K24 W25 AE24 C22 L24 W24 AE25 D3 AD26 K3 K4 A4 Signal Buffer Type Source Synch CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Open Drain Power/Other Common Clock Common Clock Open Drain Direction Input/ Output Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Output Input Input/ Output Input/ Output Output Datasheet 41 Package Mechanical Specifications and Pin Information Table 14. Pin Name IGNNE# INIT# ITP_CLK[0] ITP_CLK[1] LINT0 LINT1 LOCK# PRDY# PREQ# PROCHOT# PSI# PWRGOOD REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# RESET# RS[0]# RS[1]# RS[2]# RSVD RSVD RSVD RSVD RSVD RSVD SLP# SMI# Pin Listing by Pin Name Pin # A3 B5 A16 A15 D1 D4 J2 A10 B10 B17 E1 E4 R2 P3 T2 P1 T1 B11 H1 K1 L2 AF7 B2 C3 E26 G1 AC1 A6 B4 Signal Buffer Type CMOS CMOS CMOS CMOS CMOS CMOS Common Clock Common Clock Common Clock Open Drain CMOS CMOS Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Common Clock Common Clock Common Clock Reserved Reserved Reserved Reserved Reserved Reserved CMOS CMOS Input Input Direction Input Input input input Input Input Input/ Output Output Input Table 14. Pin Name STPCLK# TCK TDI TDO TEST1 TEST2 THERMDA THERMDC THERMTRIP# TMS TRDY# Pin Listing by Pin Name Pin # C6 A13 C12 A12 C5 F23 B18 A18 C17 C11 M3 B13 D6 D8 D18 D20 D22 E5 E7 E9 E17 E19 E21 F6 F8 F18 F20 F22 G5 G21 H6 H22 J5 J21 K22 U5 Signal Buffer Type CMOS CMOS CMOS Open Drain Test Test Power/Other Power/Other Open Drain CMOS Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Input Input Direction Input Input Input Output Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input Input TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 42 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Listing by Pin Name Pin # V6 V22 W5 W21 Y6 Y22 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC9 AC11 AC13 AC15 AC17 AC19 AD8 AD10 AD12 AD14 AD16 AD18 AE9 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 14. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA[0] VCCA[1] VCCA[2] VCCA[3] VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP Pin Listing by Pin Name Pin # AE11 AE13 AE15 AE17 AE19 AF8 AF10 AF12 AF14 AF16 AF18 F26 B1 N1 AC26 D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L5 L21 M6 M22 N5 N21 P6 P22 R5 R21 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 43 Package Mechanical Specifications and Pin Information Table 14. Pin Name VCCP VCCP VCCP VCCQ[0] VCCQ[1] VCCSENSE VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin # T6 T22 U21 P23 W4 AE7 E2 F2 F3 G3 G4 H4 A2 A5 A8 A11 A14 A17 A20 A23 A26 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS CMOS CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Output Output Direction Table 14. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin # C24 D2 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 44 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin # G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 14. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin # R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 45 Package Mechanical Specifications and Pin Information Table 14. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin # AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 14. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE Pin Listing by Pin Name Pin # AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24 AF6 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Direction Table 15. Pin # A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other CMOS Open Drain Power/Other CMOS CMOS Power/Other Common Clock Common Clock Power/Other Open Drain CMOS Output Input Output Output Input Output Input Output Direction VSS IGNNE# IERR# VSS SLP# DBR# VSS BPM[2]# PRDY# VSS TDO TCK 46 Datasheet Package Mechanical Specifications and Pin Information Table 15. Pin # A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other CMOS CMOS Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output input input Direction Table 15. Pin # AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction VSS ITP_CLK[1] ITP_CLK[0] VSS THERMDC D[0]# VSS D[6]# D[2]# VSS D[4]# D[1]# VSS VSS A[16]# A[14]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[40]# D[33]# VSS D[46]# COMP[3] COMP[2] VSS A[24]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[50]# D[48]# Datasheet 47 Package Mechanical Specifications and Pin Information Table 15. Pin # AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Reserved Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 15. Pin # AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction VSS RSVD VSS A[20]# A[18]# VSS A[25]# A[19]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D[51]# VSS D[52]# D[49]# VSS D[53]# VCCA[3] VSS A[23]# A[21]# VSS A[26]# A[28]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS DINV[3]# D[60]# VSS D[54]# D[57]# VSS GTLREF A[30]# A[27]# VSS A[22]# ADSTB[1]# VSS VCCSENSE 48 Datasheet Package Mechanical Specifications and Pin Information Table 15. Pin # AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 15. Pin # AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Reserved Power/Other CMOS CMOS Power/Other CMOS Common Clock Power/Other Common Clock Common Clock Power/Other CMOS Bus Clock Bus Clock Power/Other Open Drain Power/Other Power/Other Output Input Input Input Input Input Input Output Input Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[59]# D[55]# VSS DSTBN[3]# DSTBP[3]# VSS A[31]# VSS A[29]# A[17]# VSS VSSSENSE RSVD VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[58]# VSS D[62]# D[56]# VSS D[61]# D[63]# VCCA[1] RSVD VSS SMI# INIT# VSS DPSLP# BPM[1]# VSS PREQ# RESET# VSS TRST# BCLK[1] BCLK[0] VSS PROCHOT# THERMDA VSS Datasheet 49 Package Mechanical Specifications and Pin Information Table 15. Pin # B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 Pin Listing by Pin Number Pin Name Signal Buffer Type Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other CMOS Reserved Power/Other Test CMOS Power/Other Common Clock Common Clock Power/Other CMOS CMOS Power/Other CMOS Power/Other CMOS Open Drain Power/Other Common Clock Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Output Output Output Input Input Output Input/ Output Input Input Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output Table 15. Pin # C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Source Synch Source Synch CMOS Power/Other Open Drain CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other CMOS CMOS Power/Other CMOS Power/Other Input Output Output Input/ Output Input/ Output Output Input Input/ Output Input/ Output Input Direction D[7]# D[3]# VSS D[13]# D[9]# VSS D[5]# VSS A20M# RSVD VSS TEST1 STPCLK# VSS BPM[0]# BPM[3]# VSS TMS TDI VSS BSEL[1] VSS BSEL[0] THERMTRIP# VSS DPWR# D[8]# VSS DSTBP[0]# DSTBN[0]# VSS D[15]# D[12]# LINT0 VSS FERR# LINT1 VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC VSS D[10]# DINV[0]# VSS PSI# VID[0] VSS PWRGOOD VCC Input D26 Input/ Output E1 E2 E3 E4 E5 50 Datasheet Package Mechanical Specifications and Pin Information Table 15. Pin # E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Reserved Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Input/ Output Input/ Output Direction Table 15. Pin # F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Test Power/Other Source Synch Power/Other Reserved Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other CMOS Power/Other Power/Other Power/Other Power/Other Source Synch Input/ Output Output Input Input/ Output Input/ Output Input/ Output Output Output Input/ Output Direction VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC VSS D[14]# D[11]# VSS RSVD VSS VID[1] VID[2] VSS VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC TEST2 VSS D[21]# VCCA[0] RSVD VSS VID[3] VID[4] VCC VSS VCC VSS VSS D[22]# D[17]# VSS RS[0]# DRDY# VSS VID[5] VSS VCC VSS VCC D[16]# Datasheet 51 Package Mechanical Specifications and Pin Information Table 15. Pin # H24 H25 H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K21 K22 K23 K24 K25 K26 L1 Pin Listing by Pin Number Pin Name Signal Buffer Type Source Synch Power/Other Source Synch Power/Other Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Common Clock Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input Input/ Output Direction Input/ Output Table 15. Pin # L2 L3 L4 L5 L6 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 Pin Listing by Pin Number Pin Name Signal Buffer Type Common Clock Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Power/Other Common Clock Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input Direction Input D[20]# VSS D[29]# VSS LOCK# BPRI# VSS VCC VSS VCC VSS D[23]# VSS D[25]# DINV[1]# RS[1]# VSS HIT# HITM# VSS VCCP VSS VCC VSS DSTBN[1]# D[31]# VSS BNR# RS[2]# VSS DEFER# VCCP VSS VCCP VSS D[18]# DSTBP[1]# VSS D[26]# VSS DBSY# TRDY# VSS VSS VCCP VSS VCCP D[24]# VSS D[28]# D[19]# VCCA[2] ADS# VSS BR0# VCCP VSS 52 Datasheet Package Mechanical Specifications and Pin Information Table 15. Pin # N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R21 R22 R23 R24 R25 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 15. Pin # R26 T1 T2 T3 T4 T5 T6 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U21 U22 U23 U24 U25 U26 V1 V2 V3 Pin Listing by Pin Number Pin Name Signal Buffer Type Source Synch Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output Input/ Output VCCP VSS VSS D[27]# D[30]# VSS REQ[3]# VSS REQ[1]# A[3]# VSS VCCP VSS VCCP VCCQ[0] VSS COMP[0] COMP[1] VSS REQ[0]# A[6]# VSS VCCP VSS VCCP VSS D[39]# D[37]# VSS D[38]# REQ[4]# REQ[2]# VSS A[9]# VSS VCCP VSS VCCP VSS DINV[2]# D[34]# VSS A[13]# VSS ADSTB[0]# A[4]# VCC VSS VCCP VSS D[35]# VSS D[43]# D[41]# VSS A[7]# A[5]# Datasheet 53 Package Mechanical Specifications and Pin Information Table 15. Pin # V4 V5 V6 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 15. Pin # Y24 Y25 Y26 Pin Listing by Pin Number Pin Name Signal Buffer Type Power/Other Source Synch Source Synch Input/ Output Input/ Output Direction VSS VSS VCC VSS VCC D[36]# D[42]# VSS D[44]# A[8]# A[10]# VSS VCCQ[1] VCC VSS VCC VSS VSS DSTBP[2]# DSTBN[2]# VSS A[12]# VSS A[15]# A[11]# VSS VCC VSS VCC D[45]# VSS D[47]# D[32]# 54 Datasheet Package Mechanical Specifications and Pin Information 4.2 Table 16. Alphabetical Signals Reference Signal Description (Sheet 1 of 8) Name Type Description A[31:3]# (Address) define a 232-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel® Celeron® M processor FSB. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[31:17]# Associated Strobe ADSTB[0]# ADSTB[1]# A[31:3]# Input/ Output A20M# Input ADS# Input/ Output BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BNR# Input/ Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Celeron M FSB agents.This includes debug or performance monitoring tools. BPM[2:0]# BPM[3] Output Input/ Output Datasheet 55 Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 2 of 8) Name Type Description BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. The arbitration is done between Celeron M (Symmetric Agent) and Intel® 915/910 Express Chipset and Intel® 852/855 Chipset families (High Priority Agent). The BSEL[1:0] signals are used to select the frequency of the processor input clock(BCLK[1:0]. These signals should be connected to the clock chip and Intel 915GM/GMS/PM & 910GML Express Chipsets on the platform. These signals must be left unconnected on Intel 852/855 Chipset family-based platforms. COMP[3:0] Analog COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DINV# 0 1 2 3 BPRI# Input BR0# Input/ Output BSEL[1:0] Output Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBR# Output 56 Datasheet Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 3 of 8) Name Type Input/ Output Description DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both FSB agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment to Data Bus DINV[3:0]# Input/ Output Bus Signal DINV[3]# DINV[2]# DINV[1]# DINV[0]# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]# DBSY# DEFER# Input DPSLP# Input DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the ICH-M component and also connects to the MCH-M component. DPWR# is a control signal from the Intel chipset used to reduce power on the Celeron M data bus input buffers. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DPWR# Input DRDY# Input/ Output DSTBN[3:0] # Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Datasheet 57 Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 4 of 8) Name Type Description Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR#/PBE# Output FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volume 3 of the Intel® Architecture Software developer’s manual and the Intel® Processor Identification and CPUID Instruction application note. GTLREF Input Input/ Output Input/ Output GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. HIT# HITM# IERR# Output IGNNE# Input 58 Datasheet Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 5 of 8) Name Type Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Celeron processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. Probe Request signal used by debug tools to request debug operation of the processor. PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. See Chapter 5 for more details. Processor Power Status Indicator (PSI) signal. This signal is asserted when the processor is in a lower state (Deep Sleep). See Section 2.1.4 for more details. INIT# Input ITP_CLK[1:0] Input LINT[1:0] Input LOCK# Input/ Output PRDY# PREQ# Output Input PROCHOT# Output PSI# Output Datasheet 59 Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 6 of 8) Name Type Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. Input/ Output REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. PWRGOOD Input REQ[4:0]# RESET# Input RS[2:0]# Input Reserved /No Connect RSVD SLP# Input SMI# Input 60 Datasheet Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 7 of 8) Name Type Description STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor test bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TEST1 and TEST2 must have a stuffing option of separate pull down resistors to VSS. Thermal Diode Anode. Thermal Diode Cathode. The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Processor core power supply. VCCA provides isolated power for the internal processor core PLL’s. Processor I/O power supply. Quiet power supply for on die COMP circuitry. These pins should be connected to VCCP on the motherboard. However, these connections should enable addition of decoupling on the VCCQ lines if necessary. STPCLK# Input TCK TDI Input Input TDO TEST1, TEST2 THERMDA THERMDC Output Input Other Other THERMTRIP# Output TMS Input TRDY# Input TRST# VCC VCCA[3:0] VCCP VCCQ[1:0] Input Input Input Input Input Datasheet 61 Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 8 of 8) Name VCCSENSE Type Output Description VCCSENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure power near the silicon with little noise. VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike some previous generations of processors, these are CMOS signals that are driven by the Celeron M processor. The voltage supply for these pins must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 1 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. VID[5:0] Output VSSSENSE Output § 62 Datasheet Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The Celeron M processor requires a thermal solution to maintain temperatures within operating limits as set forth in Table 17. Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor via a heat pipe or direct die attachment. A secondary fan, or air from the processor fan, may also be used to cool other platform components or lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor must remain within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 17. Thermal solutions not design to provide this level of thermal capability may affect the long-term reliability of the processor and system. The maximum junction temperature is defined by an activation of the processor Intel® Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 17. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification. Datasheet 63 Thermal Specifications and Design Considerations Table 17. Symbol Power Specifications for the Celeron M Processor (Sheet 1 of 2) Processor Number 390 380 370 360J 360 350J 350 383 373 353 Processor Number Core Frequency & Voltage 1.7 GHz & VCC2 1.6 GHz & VCC2 1.5 GHz & VCC2 1.4 GHz & VCC2 1.4 GHz & 1.260 V 1.3 GHz & VCC2 1.3 GHz & 1.260 V 1.1 GHz & VCC3 1.0 GHz & VCC3 900 MHz & 0.940 V Parameter Auto Halt, Stop Grant Power at: 390 380 370 VCC2 VCC2 VCC2 VCC2 1.260 V VCC2 1.260 V VCC3 VCC3 0.940 V Sleep Power at: 390 380 370 360J VCC2 VCC2 VCC2 VCC2 1.260 V VCC2 1.260 V VCC3 VCC3 0.940 V 11.3 11.3 11.3 11.3 11.3 11.3 11.3 1.8 1.8 1.8 W At 50°C, Note 2,5,6 11.6 11.6 11.6 11.6 11.6 11.6 11.6 1.9 1.9 1.9 W At 50°C, Note 2,5,6 Min Thermal Design Power 27 21 21 21 21 21 21 5.5 5.5 5.0 Typ Max Unit Notes W At 100°C, Notes 1, 4,5,6 Unit Notes TDP Symbol PAH, PSGNT 360J 360 350J 350 383 373 353 PSLP 360 350J 350 383 373 353 64 Datasheet Thermal Specifications and Design Considerations Table 17. Power Specifications for the Celeron M Processor (Sheet 2 of 2) Deep Sleep Power at: 390 380 370 360J VCC2 VCC2 VCC2 VCC2 1.260 V VCC2 1.260 V VCC3 VCC3 0.940 V Junction Temperature 0 8.8 8.8 8.8 8.8 8.8 8.8 8.8 1.4 1.4 1.4 100 °C Notes 3, 4 W At 35°C, Note 2,5,6 PDSLP 360 350J 350 383 373 353 TJ NOTES: 1. The Thermal Design Power (TDP) specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can dissipate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/ processor_number for details. 6. See Table 4 for VCC2 and VCC3. 5.1 5.1.1 Thermal Specifications Thermal Diode The Celeron M processor incorporates two methods of monitoring die temperature, the Intel Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1) must be used to determine when the maximum specified processor junction temperature has been reached. The second method, the thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but cannot be used to indicate that the maximum TJ of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor Model Specific register (MSR) and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage recommendation when the PROCHOT# signal is not asserted. Table 18 and Table 19 provide the diode interface and specifications. Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change. Datasheet 65 Thermal Specifications and Design Considerations Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. 5.1.2 Thermal Diode Offset A temperature offset value (specified as Toffset in Table 19) will be programmed into a Celeron M processor Model Specific Register (MSR). This offset is determined by using a thermal diode ideality factor mean value of n = 1.0022 (shown in Table 19) as a reference. This offset must be applied to the junction temperature read by the thermal diode. Any temperature adjustments due to differences between the reference ideality value of 1.0022 and the default ideality values programmed into the on-board thermal sensors, will have to be made before the above offset is applied. Table 18. Thermal Diode Interface Signal Name THERMDA THERMDC Pin/Ball Number B18 A18 Signal Description Thermal diode anode Thermal diode cathode Table 19. Thermal Diode Specification Symbol IFW Toffset Parameter Forward Bias Current Thermal Diode Temperature Offset Reference Diode Ideality Factor Used to Calculate Temperature Offset Series Resistance Min 5 -4 Typ Max 300 11 Unit µA °C Notes Note 1 2, 6 Notes 2, 3, 4 Ω 2, 3, 5 n RT 1.0022 3.06 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. Characterized at 100°C. 3. Not 100% tested. Specified by design/characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVD/nkT) -1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). Value shown in the table is not the Celeron M processor thermal diode ideality factor. It is a reference value used to calculate the Celeron M thermal diode temperature offset. 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT*(N-1)*IFWmin]/[(no/q)*ln N] 6. Offset value is programmed in processor Model Specific Register. 66 Datasheet Thermal Specifications and Design Considerations 5.1.3 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature. The temperature at which Intel Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would not be detectable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and On-Demand mode. If both modes are activated, Automatic mode takes precedence. The Intel Thermal Monitor Automatic mode must be enabled via BIOS for the processor to be operating within specifications. The automatic mode called Intel Thermal Monitor 1 This mode is selected by writing values to the model specific registers (MSRs) of the processor. After Automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. When Intel Thermal Monitor 1 is enabled, and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a noncritical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active, however, with a properly designed and characterized thermal solution the TCC most likely will never be activated, or only will be activated briefly during the most power intensive applications. The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Intel Thermal Monitor Control Register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor Control Register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used at the same time Automatic mode is enabled, however, if the system tries to enable the TCC via On-Demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction Datasheet 67 Thermal Specifications and Design Considerations temperature within the 100°C (maximum) specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the Low Power state and the processor junction temperature drops below the thermal trip point. If automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the FSB signal THERMTRIP# will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within a time specified in Chapter 3. § 68 Datasheet