410

Intel® Celeron® M Processor on 65 nm Process Datasheet January 2007 Document Number: 312726-004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Celeron® M processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Intel, Celeron, Pentium, MMX, and the Intel logo are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. * Other brands and names are the property of their respective owners. Copyright © 2006 – 2007, Intel Corporation. All rights reserved. 2 Datasheet Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 Low Power Features ................................................................................................ 11 2.1 Clock Control and Low Power States .................................................................... 11 2.1.1 Core Low-Power States ........................................................................... 12 2.1.2 Package Low Power States ...................................................................... 13 2.2 FSB Low Power Enhancements ............................................................................ 15 2.3 Processor Power Status Indicator (PSI#) Signal..................................................... 16 Electrical Specifications ........................................................................................... 17 3.1 FSB (Front Side Bus) and GTLREF........................................................................ 17 3.2 Power and Ground Pins ...................................................................................... 17 3.3 Decoupling Guidelines ........................................................................................ 17 3.3.1 VCC Decoupling...................................................................................... 18 3.3.2 FSB AGTL+ Decoupling ........................................................................... 18 3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ........................................... 18 3.4 Voltage Identification and Power Sequencing ........................................................ 18 3.5 Catastrophic Thermal Protection .......................................................................... 22 3.6 Signal Terminations and Unused Pins ................................................................... 22 3.7 FSB Frequency Select Signals (BSEL[2:0])............................................................ 23 3.8 FSB Signal Groups............................................................................................. 23 3.9 CMOS Signals ................................................................................................... 25 3.10 Maximum Ratings.............................................................................................. 25 3.11 Processor DC Specifications ................................................................................ 25 Package Mechanical Specifications and Pin Information .......................................... 31 4.1 Processor Component Keep-Out Zones ................................................................. 31 4.2 Package Loading Specifications ........................................................................... 31 4.3 Processor Mass Specifications ............................................................................. 31 4.4 Processor Pinout and Pin List .............................................................................. 36 4.5 Alphabetical Signals Reference ............................................................................ 55 Thermal Specifications and Design Considerations .................................................. 63 5.1 Thermal Specifications ....................................................................................... 65 5.1.1 Thermal Diode ....................................................................................... 65 5.1.2 Thermal Diode Offset .............................................................................. 68 5.1.3 Intel® Thermal Monitor........................................................................... 68 5.1.4 Digital Thermal Sensor............................................................................ 70 5.1.5 Out of Specification Detection .................................................................. 70 5.1.6 PROCHOT# Signal Pin ............................................................................. 70 2 3 4 5 Datasheet 3 Figures 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Package-Level Low Power States ................................................................................11 Core Low Power States..............................................................................................12 Active VCC and ICC Loadline for the Celeron M Processor Standard Voltage .......................28 Active VCC and ICC Loadline for the Celeron M Processor Ultra Low Voltage .......................28 Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................................................32 Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................................................33 Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ................................................34 Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ................................................35 Coordination of Core-Level Low Power States at the Package Level for the Celeron M Processor ................................................................................................................11 Voltage Identification Definition ..................................................................................19 BSEL[2:0] Encoding for BCLK Frequency......................................................................23 FSB Pin Groups ........................................................................................................24 Processor DC Absolute Maximum Ratings.....................................................................25 Voltage and Current Specifications for the Celeron M Processor Standard Voltage..............26 Voltage and Current Specifications for the Celeron M Processor Ultra Low Voltage .............27 FSB Differential BCLK Specifications ............................................................................29 AGTL+ Signal Group DC Specifications ........................................................................29 CMOS Signal Group DC Specifications..........................................................................30 Open Drain Signal Group DC Specifications ..................................................................30 The Coordinates of the Processor Pins As Viewed from the Top of the Package .................36 Pin Listing by Pin Name .............................................................................................39 Pin Listing by Pin Number ..........................................................................................46 Signal Description.....................................................................................................55 Power Specifications for the Celeron M Processor Standard Voltage .................................64 Power Specifications for the Celeron M Processor Ultra Low Voltage.................................65 Thermal Diode Interface ............................................................................................66 Thermal Diode Parameters using Diode Model ..............................................................66 Thermal Diode Parameters using Transistor Mode .........................................................67 Thermal Diode ntrim and Diode Correction Toffset..........................................................68 Tables 4 Datasheet Revision History Revision -001 Initial release • -002 • Chapter 3, “Electrical Specifications” — Added 440 and 450 processor specifications to Table 6. Chapter 5, “Thermal Specifications and Design Considerations” — Added power specifications for the 440 and 450 processor to Table 16. Corrected page numbering in Chapter 5 Chapter 3, “Electrical Specifications” — Added 443 ULV processor specifications to Table 7. Chapter 5, “Thermal Specifications and Design Considerations” Added power specifications for the 443 ULV processor to Table 17. Description Date April 2006 September 2006 -003 • • September 2006 -004 • • January 2007 § Datasheet 5 6 Datasheet Introduction 1 Introduction The Intel® Celeron® M processor based on 65 nm process technology is a highperformance, low-power mobile processor with several enhancements over previous mobile Celeron processors. Throughout this document, the term “Celeron M processor” refers to the Intel® Celeron® M processor based on 65 nm process technology. This document contains specifications for both the Intel® Celeron® M processor 450, 440, 430, 420, 410 and Intel® Celeron® M processor Ultra Low Voltage 443 and 423Δ. Note: ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. The following list provides some of the key features on this processor: • On-die, 1-MB second level cache with Advanced Transfer Cache Architecture • Supports Intel Architecture with Dynamic Execution • On-die, primary 32-kB instruction cache and 32-kB write-back data cache • Data Prefetch Logic • Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3) • The Celeron M processor and the Celeron M processor Ultra Low Voltage are offered at 533-MHz FSB • Digital Thermal Sensor • The Celeron M is a single core processor offered in both Micro-FCPGA and MicroFCBGA packages • The Celeron M processor Ultra Low Voltage is a single core processor offered only in a Micro-FCBGA package • Execute Disable Bit support for enhanced security The Celeron M processor will be manufactured on Intel’s 65 nanometer process technology with copper interconnect. The processor maintains support for MMX™ technology, Streaming SIMD instructions, and full compatibility with IA-32 software. The Celeron M processor features on-die, 32-kB level 1 instruction and data caches and a 1-MB level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before the L1 cache requests occurs, resulting in reduced bus cycle penalties. The Celeron M processor includes the Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, the Writer Order Buffer depth is enhanced to help with the write-back latency performance. In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new instructions which further extend the capabilities of Intel processor technology. These new instructions are called Streaming SIMD Extensions 3 (SSE3). 3D graphics and other entertainment applications such as gaming will have the opportunity to take advantage of these new instructions as platforms with the Celeron M processor based on 65 nm process and SSE3 become available in the market place. The Celeron M processor’s front side bus (FSB) utilizes a split-transaction, deferred reply protocol. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock. The 4X data bus can deliver data four times per bus clock and is referred as “quad-pumped” or 4X data Datasheet 7 Introduction bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and the 2X address bus provide a data bus bandwidth of up to 4.26 GB/second. The FSB uses Advanced Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling technology with low power enhancements. The processor features the Auto Halt, Stop Grant and Deep Sleep low power C-states. The Celeron M processor utilizes socketable Micro Flip-Chip Pin Grid Array (MicroFCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket. Celeron M processor supports the Execute Disable Bit capability. This feature combined with a support operating system allows memory to be marked as executable or non executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the IA-32 Intel® Architecture Software Developer's Manual for more detailed information. 1.1 Terminology Term Definition A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Refers to the interface between the processor and system core logic (also known as the chipset components). Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors. # Front Side Bus (FSB) AGTL+ 8 Datasheet Introduction 1.2 References Document Intel® Celeron® M Processor Specification Update Mobile Intel® 945 Express Chipset Family Datasheet Mobile Intel® 945 Express Chipset Family Specification Update Intel® I/O Controller Hub 7 (ICH7) Family Datasheet Intel® I/O Controller Hub 7 (ICH7) Family Specification Update IA-32 Intel® Architecture Software Developer's Manual Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A- M Volume 2B: Instruction Set Reference. N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide AP-485, Intel® Processor Identification and CPUID Instruction Application Note 241618 http:// www.intel.com/ design/ pentium4/ manuals/ index_new.htm Document Number 300303 309219 309220 307013 307014 § Datasheet 9 Introduction 10 Datasheet Low Power Features 2 2.1 Low Power Features Clock Control and Low Power States The Celeron M processor supports the C1/AutoHALT, C1/MWAIT, Stop Grant, Sleep, and Deep Sleep for power management. See Figure 1 for a visual representation of package level low-power states for the Celeron M processor. Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep and Deep Sleep. Refer Figure 2 for a visual representation of the core low-power states for the Celeron M processor. The Celeron M processor implements two software interfaces for requesting low power states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The monitor address does not need to be setup before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model specific register (MSR). If the processor encounters a chipset break event while STPCLK# is asserted, it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that the processor should return to the Normal state. Table 1. Coordination of Core-Level Low Power States at the Package Level for the Celeron M Processor Core States C0 C1(1) C2 C3 Package States Normal Normal Stop Grant Deep Sleep NOTE: (1)AutoHALT or MWAIT/C1 Figure 1. Package-Level Low Power States STPCLK# asserted SLP# asserted DPSLP# asserted Normal STPCLK# de-asserted Stop Grant SLP# de-asserted Sleep DPSLP# de-asserted Deep Sleep Snoop serviced Snoop occurs Stop Grant Snoop Datasheet 11 Low Power Features Figure 2. Core Low Power States Stop Grant STPCLK# asserted STPCLK# de-asserted STPCLK# de-asserted STPCLK# asserted C1/ MWAIT STPCLK# de-asserted STPCLK# asserted Core state break MWAIT(C1) C1/Auto Halt HLT instruction Halt break C0 Core state break P_LVL3 or MWAIT(C3) P_LVL2 or MWAIT(C2) Core state break C3 † C2 † halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) † — STPCLK# assertion and de-assertion have no affect if a core is in C2, or C3. 2.1.1 2.1.1.1 Core Low-Power States C0 State This is the normal operating state for the core of the Celeron M processor. 2.1.1.2 C1/AutoHALT Powerdown State C1/AutoHALT is a low power state entered when the processor core executes the HALT instruction. The processor core will transition to the C0 state upon the occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the IA-32 Intel® Architecture Software Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Powerdown state the Celeron M processor will process only the bus snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the AutoHALT Powerdown state. 12 Datasheet Low Power Features 2.1.1.3 C1/MWAIT Powerdown State MWAIT is a low power state entered when the processor core executes the MWAIT instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the IA-32 Intel® Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information. 2.1.1.4 Core C2 State The core of the Celeron M processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in C2 state, the Celeron M processor will process only the bus snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the C2 state. 2.1.1.5 Core C3 State Core C3 state is a very low power state the processor core can enter while maintaining context. The core of the Celeron M processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB. The processor core will transition to the C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself. 2.1.2 Package Low Power States The package level low power states are applicable for the Celeron M processor. All package level low power states are described as follows: 2.1.2.1 Normal State This is the normal operating state for the processor. The Celeron M processor enters the Normal state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state. 2.1.2.2 Stop-Grant State When the STPCLK# pin is asserted the core of the Celeron M processor enters the StopGrant state within 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core returns to the previous core low-power state. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to RESET# Datasheet 13 Low Power Features deassertion (AC Specification T45). When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP# (AC Specification T75). While in the Stop-Grant State, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT#, LINT[1:0] interrupts and will serviced only upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the FSB and it will latch interrupts delivered on the FSB. The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the processor should return to the Normal state. A transition to the Stop Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) will occur with the assertion of the SLP# signal. 2.1.2.3 Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor will return to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched. 2.1.2.4 Sleep State The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 2.1.2.5.) While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur. 14 Datasheet Low Power Features 2.1.2.5 Deep Sleep State Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset based platforms with the CK410M clock chip are as follows: • Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep. • Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. 2.2 FSB Low Power Enhancements The Celeron M processor incorporates FSB low power enhancements: • Dynamic FSB Power Down • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On Die Termination disabling • Low VCCP (I/O termination voltage) The Celeron M processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times. Datasheet 15 Low Power Features 2.3 Processor Power Status Indicator (PSI#) Signal The Celeron M processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the Celeron M processor uses for determining when to assert PSI# is different from the algorithm used in previous Celeron M processors. For more information, contact your Intel Representative. § 16 Datasheet Electrical Specifications 3 3.1 Electrical Specifications FSB (Front Side Bus) and GTLREF Most Celeron M processor FSB signals use Advanced Gunning Transceiver Logic (AGTL+) signalling technology. This signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. The termination voltage level for the Celeron M processor AGTL+ signals is VCCP = 1.05 V (nominal). Due to speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. Contact your Intel representative for more information on design guidelines for the Celeron M processor FSB. The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its I/O voltage (VCCP). Intel® 945GMS and 940GML Express Chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ signals. Refer to your Intel representative for board level termination resistor requirements. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system. 3.2 Power and Ground Pins For clean, on-chip power distribution, the Celeron M processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please contact your Intel representative for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Caution: Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 6. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, contact your Intel representative. Datasheet 17 Electrical Specifications 3.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. It is strongly recommended that the layout and decoupling recommendations be followed - for more details, contact your Intel representative. 3.3.2 FSB AGTL+ Decoupling Celeron M processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. For more information, contact your Intel representative. 3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Celeron M processor core frequency is a multiple of the BCLK[1:0] frequency. The Celeron M processor bus ratio multiplier will be set at its default ratio at manufacturing. The Celeron M processor uses a differential clocking implementation. For more information on Celeron M processor clocking, contact your Intel representative. 3.4 Voltage Identification and Power Sequencing Information regarding the VID specification for the Celeron M processor is available from your Intel representative. The Celeron M processor uses seven voltage identification pins, VID[6:0], to support automatic selection of power supply voltages. The VID pins for Celeron M processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. For more details about VR design to support the Celeron M processor power supply requirements, please contact your Intel representative. Power source characteristics must be stable whenever the supply to the voltage regulator is stable. Refer to the Figure 3 for timing details of the power-up sequence. Figure 4 shows the power-down sequencing requirements. 18 Datasheet Electrical Specifications Table 2. Voltage Identification Definition (Sheet 1 of 4) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCC(V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 Datasheet 19 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 4) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCC(V) 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 20 Datasheet Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 4) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCC(V) 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 Datasheet 21 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 4 of 4) VID6 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 1 VID2 0 0 0 1 1 1 1 0 VID1 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 VCC(V) 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 NOTE: A “1” in this table refers to a high-voltage level and a “0” refers to low-voltage level. Contact your Intel representative for further information on BIOS VID programming. 3.5 Catastrophic Thermal Protection The Celeron M processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. 3.6 Signal Terminations and Unused Pins All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Celeron M processors. See Section 4.4 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected. Please contact your Intel representative for details on signal terminations and TAP signal termination requirements. The TEST1 and TEST2 pins must have a stuffing option connection to VSS separately via 1-kΩ, pull-down resistors. The TEST2 pin must have a 51-Ω ±5%, pull-down resistor to VSS. 22 Datasheet Electrical Specifications 3.7 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and Intel 945GMS and 940GML Express Chipsets on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3. Table 3. BSEL[2:0] Encoding for BCLK Frequency BSEL[2] L L L L BSEL[1] L L H H BSEL[0] L H L H BCLK Frequency RESERVED 133 MHz RESERVED RESERVED 3.8 FSB Signal Groups In order to simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous. Datasheet 23 Electrical Specifications Table 4. FSB Pin Groups Signal Group AGTL+ Common Clock Input AGTL+ Common Clock I/O Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3 Signals REQ[4:0]#, A[16:3]# AGTL+ Source Synchronous I/O Synchronous to assoc. strobe A[31:17]# D[15:0]#, DINV0# D[31:16]#, DINV1# D[47:32]#, DINV2# D[63:48]#, DINV3# Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK Clock Associated Strobe ADSTB[0]# ADSTB[1]# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# AGTL+ Strobes ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPRSTP# (not used), DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, IERR#, THERMTRIP# PROCHOT#4 PSI#, VID[6:0], BSEL[2:0] TCK, TDI, TMS, TRST# TDO BCLK[1:0] COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, VCC, VCCA, VCCP, VCCSENSE, VSS, VSSSENSE CMOS Input Open Drain Output Open Drain I/O CMOS Output CMOS Input Open Drain Output FSB Clock Power/Other NOTES: 1. Refer to Chapter 4 for signal descriptions and termination requirements. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. BPM[2:1]# and PRDY# are AGTL+ output only signals. 4. PROCHOT# signal type is open drain output and CMOS input. 24 Datasheet Electrical Specifications 3.9 CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them. See Section 3.11 for the DC specifications for the CMOS signal groups. 3.10 Maximum Ratings Table 5 specifies absolute maximum and minimum ratings. Only within specified operation limits, can functionality and long-term reliability be expected. At condition outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from electro static discharge, precautions should always be taken to avoid high static voltages or electric fields. Table 5. Symbol TSTORAGE VCC VinAGTL+ VinAsynch_CMOS Processor DC Absolute Maximum Ratings Parameter Processor Storage Temperature Any Processor Supply Voltage with Respect to VSS AGTL+ Buffer DC Input Voltage with Respect to VSS CMOS Buffer DC Input Voltage with Respect to VSS Min -40 -0.3 -0.3 -0.3 Max 85 1.6 1.6 1.6 Unit °C V V V Notes 2 1 1, 2 1, 2 NOTES: 1. This rating applies to any processor pin. 2. Contact Intel for storage requirements in excess of one year. 3.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 9. DC specifications for the CMOS group are listed in Table 10. Table 9 through Table 11 list the DC specifications for the Celeron M processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Active mode load line specifications apply in all states except in the Deep Sleep state. VCC,BOOT is the default voltage driven by the voltage regulator at Datasheet 25 Electrical Specifications power up in order to set the VID values. Unless specified otherwise, all specifications for the Celeron M processor are at Tjunction = 100°C. Care should be taken to read all notes associated with each parameter. Table 6. Symbol VCC VCC,BOOT VCCP VCCA ICCDES VCC of Core Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage ICC for Processors Recommended Design Target ICC Core Processors Processor Number: ICC 450 440 430 420 410 IAH, ISGNT ISLP IDSLP dICC/DT ICCA ICCP Core Frequency/Voltage 2.00 GHz and VCC 1.86 GHz and VCC 1.73 GHz and VCC 1.60 GHz and VCC 1.46 GHz and VCC 29 29 29 29 29 16.5 16.4 14.7 600 120 6.0 2.5 A A A A/µs mA A A 9 10 3,4 3,4 3,4 6, 7 A 3,4 0.997 1.425 Voltage and Current Specifications for the Celeron M Processor Standard Voltage Parameter Min 1.0 1.20 1.05 1.5 1.102 1.575 36 Typ Max 1.3 Unit V V V V A 5 Notes 1, 2 2, 8 2 ICC Auto-Halt & Stop-Grant ICC Sleep ICC Deep Sleep VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. 2. The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the VID voltage. 5. The ICCDES(max) specification of 36 A comprehends only Celeron M processor on 65 nm process. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Measured at the bulk capacitors on the motherboard. 8. VCC, BOOT tolerance is shown in Figure 3. 9. This is a steady-state ICCP current specification, which is applicable when both VCCP and VCC_CORE are high. 10. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 11. Specified at the nominal VCC. 26 Datasheet Electrical Specifications Table 7. Symbol VCC VCC,BOOT VCCP VCCA ICCDES Voltage and Current Specifications for the Celeron M Processor Ultra Low Voltage Parameter VCC Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage ICC for Recommended Design Target ICC Processor Number: 443 423 Core Frequency/Voltage: 1.20 GHz at VCC 1.06 GHz at VCC 8.2 8.2 4.6 4.5 3.6 600 120 6.0 2.5 A 3,4 0.997 1.425 Min 0.85 1.20 1.05 1.5 1.102 1.575 8 Typ Max 1.10 Unit V V V V A 5 Notes 1, 2 2, 8 2 ICC IAH, ISGNT ISLP IDSLP dICC/DT ICCA ICCP ICC Auto-Halt & Stop-Grant ICC Sleep ICC Deep Sleep VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before Vcc Stable ICC for VCCP Supply after Vcc Stable A A A A/µs mA A A 3,4 3,4 3,4 6, 7 9 10 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. 2. The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100 °C Tj. 4. Specified at the VID voltage. 5. The ICCDES(max) specification of 8 A comprehends only the Celeron M processor ULV and the value is based on pre-silicon estimates. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Measured at the bulk capacitors on the motherboard. 8. VCC, BOOT tolerance is shown in Figure 3. 9. This is a steady-state ICCP current specification, which is applicable when both VCCP and VCC_CORE are high. 10. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. Datasheet 27 Electrical Specifications Figure 3. Active VCC and ICC Loadline for the Celeron M Processor Standard Voltage VCC [V] VCC max VCC, DC max Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. 10mV= RIPPLE VCC nom VCC, DC min VCC min +/-VCC nom * 1.5% = VR St. Pt. Error 1/ 0 Note 1 / V C C S et Poi nt Error Tol erance i s per below : Tolerance --------------+/-1.5% +/ -11.5mV V C C A ctive Mode VID Code Range -------------------------------------------------------V C C > 0 .7500 V (VID 0111100). V C C < 0 .7500 V (VID 0111100) ICC [A] ICC max Figure 4. Active VCC and ICC Loadline for the Celeron M Processor Ultra Low Voltage V CC-CORE [V] Slope = -5.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. V CC m ax V CC- DC m ax 10mV= RIPPLE V CC n om V CC-DC m in V CC m in +/-V CC-CORE Tolerance = VR St. Pt. Error 1 / 0 N ote 1/ VCC Set Point Error Tolerance is per below : ICC-CORE m ax T oleranc e V CC V ID V o ltage R an ge --------------- -------------------------------------------------------+/-1.5% V CC > 0.7500V +/-11.5m V 0.75000 V < VCC < 0.5000V 28 Datasheet Electrical Specifications Table 8. Symbol VIL VIH VCROSS ΔVCROSS VTH ILI Cpad FSB Differential BCLK Specifications Parameter Input Low Voltage Input High Voltage Crossing Voltage Range of Crossing Points Threshold Region Input Leakage Current Pad Capacitance 0.95 1.2 VCROSS -0.100 0.660 0.25 Min Typ 0 0.710 0.35 0.85 0.55 0.14 VCROSS+0.100 ±100 1.45 Max Unit V V V V V µA pF 2 6 3 4 5 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis. 4. For Vin between 0 V and VIH. 5. Cpad includes die capacitance only. No package parasitics are included. 6. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2. Table 9. Symbol VCCP GTLREF VIH VIL VOH RTT RON ILI Cpad1 AGTL+ Signal Group DC Specifications Parameter I/O Voltage Reference Voltage Input High Voltage Input Low Voltage Output High Voltage Termination Resistance Buffer on Resistance Input Leakage Current Pad Capacitance 1.8 2.3 50 22.3 GTLREF+0.1 -0.1 0 VCCP 55 25.5 61 28.7 ±100 2.75 Ω Ω µA pF Min 0.997 Typ 1.05 2/3 VCCP VCCP+0.1 GTLREF-0.1 Max 1.102 Unit V V V V 6 3,6 2,4 6 7,10 5 8 9 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. Measured at 0.31*VCCP. RON (min) = 0.38*RTT, RON (typ) = 0.45*RTT, RON (max) = 0.52*RTT. 6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. Tolerance of resistor divider decides the tolerance of GTLREF. The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics. 8. Specified with on die RTT and RON are turned off. 9. Cpad includes die capacitance only. No package parasitics are included. 10. This spec applies to all AGTL+ signals except for PREQ#. RTT for PREQ# is between 1.5 kΩ to 6.0 kΩ. Datasheet 29 Electrical Specifications . Table 10. Symbol VCCP VIL VIH VOL VOH IOL IOH ILI Cpad1 Cpad2 CMOS Signal Group DC Specifications Parameter I/O Voltage Input Low Voltage - CMOS Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Input Leakage Current Pad Capacitance Pad Capacitance for CMOS Input 1.8 0.95 2.3 1.2 Min 1.0 -0.1 0.7 -0.1 0.9 1.3 1.3 Typ 1.05 0.0 1.05 0 VCCP Max 1.10 0.33 1.20 0.11 1.20 4.1 4.1 ±100 2.75 1.45 Unit V V V V V mA mA µA pF pF 2, 3 2 2 2 4 5 6 7 8 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VCCP referred to in these specifications refers to instantaneous VCCP. 3. Refer to the processor I/O Buffer Models for I/V characteristics. 4. Measured at 0.1*VCCP. 5. Measured at 0.9*VCCP. 6. For Vin between 0 V and VCCP. Measured when the driver is tristated. 7. Cpad1 includes die capacitance only for DPSLP#,PWRGOOD. No package parasitics are included. 8. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included. Table 11. Symbol VOH VOL IOL ILeak Cpad Open Drain Signal Group DC Specifications Parameter Output High Voltage Output Low Voltage Output Low Current Output Leakage Current Pad Capacitance 1.8 2.3 Min 1.0 0 11.40 Typ 1.05 Max 1.10 0.20 50 ±200 2.75 Unit V V mA µA pF 2 4 5 Notes1 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2*VCCP. 3. VOH is determined by value of the external pull-up resistor to VCCP. Please contact your Intel representative for details. 4. For Vin between 0 V and VOH. 5. Cpad includes die capacitance only. No package parasitics are included. § 30 Datasheet Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information The Celeron M processor is available in 478-pin Micro-FCPGA and 479-ball Micro-FCBGA packages. The package mechanical dimensions, keep-out zones, loading specifications, and mass specifications are shown in Figure 5 through Figure 8. Table 12 shows a topview of package pinout with their functionalities. Caution: The Micro-FCBGA package incorporates land-side capacitors. Avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors, and possibly damage the device or render it inactive. 4.1 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. The location and quantity of capacitors may change, but will remain within the component keep-in. 4.2 Package Loading Specifications Maximum package loading specifications are static compressive loading in the direction normal to the processor. This maximum load limit should not be exceeded during shipping conditions, standard use condition, or by thermal solution. In addition, there are additional load limitations against transient bend, shock, and tensile loading, all of which can be obtained by contacting your field support. Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. 4.3 Processor Mass Specifications The typical mass of the processor is given in Figure 5 and Figure 8. This mass includes all the components that are included in the package. Datasheet 31 Package Mechanical Specifications and Pin Information Figure 5. Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) 32 Datasheet Package Mechanical Specifications and Pin Information Figure 6. Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) Datasheet 33 Package Mechanical Specifications and Pin Information Figure 7. Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) 34 Datasheet Package Mechanical Specifications and Pin Information Figure 8. Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) Datasheet 35 Package Mechanical Specifications and Pin Information 4.4 Processor Pinout and Pin List Table 12 shows the top view pinout of the Celeron M processor. The pin list arranged in two different formats is shown in the following pages. Table 12. 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF RESET# RSVD VSS DBSY# BR0# VSS ADS# A[9]# VSS A[13]# A[7]# VSS A[15]# A[16]# VSS COMP[2] COMP[3] VSS A[31]# RSVD VSS PREQ# BPM[2]# VSS RSVD 1 The Coordinates of the Processor Pins As Viewed from the Top of the Package (Sheet 1 of 2) 2 3 SMI# RSVD VSS RSVD BNR# VSS TRDY# REQ[1] # VSS REQ[2] # ADSTB[ 0]# VSS A[8]# A[12]# VSS RSVD A[23]# VSS A[30]# A[17]# VSS RSVD PRDY# VSS VID[6] VID[5] 2 INIT# RSVD RSVD VSS RS[0]# RS[2]# VSS REQ[3] # REQ[0] # VSS A[5]# A[10]# VSS A[19]# A[26]# VSS RSVD A[27]# VSS RSVD TDO VSS BPM[1] # VID[4] VSS 3 4 VSS LINT1 IGNNE # VSS HITM# RS[1]# VSS LOCK# A[3]# VSS A[4]# RSVD VSS A[14]# A[24]# VSS A[21]# ADSTB [1]# VSS A[29]# RSVD VSS BPM[3] # BPM[0] # VSS VID[3] 4 5 FERR# DPSLP# VSS STPCLK # DPRSTP # VSS BPRI# DEFER# VSS A[6]# REQ[4] # VSS RSVD A[11]# VSS A[25]# A[18]# VSS A[28]# A[22]# VSS TMS TCK VSS VID[2] VID[1] 5 6 A20M# VSS LINT0 PWRGO OD VSS RSVD HIT# VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP A[20]# VSS TDI TRST# VSS VID[0] PSI# VSS 6 VCC VCC VCC VCC VSS SENSE VCC SENSE 7 VSS VSS VSS VSS VSS VSS 8 VCC VCC VCC VCC VCC VCC 9 VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS 11 VCC VCC VCC VCC VCC VCC 12 VCC VSS VCC VSS VCC VSS 13 7 VCC VCC THERM TRIP# SLP# VCC VCC 8 VSS VSS VSS VSS VSS VSS 9 VCC VCC VCC VCC VCC VCC 10 VCC VCC VCC VCC VCC VCC 11 VSS VSS VSS VSS VSS VSS 12 VCC VCC VCC VCC VCC VCC 13 VCC VSS VCC VSS VCC VSS A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 36 Datasheet Package Mechanical Specifications and Pin Information Table 12. The Coordinates of the Processor Pins As Viewed from the Top of the Package (Sheet 2 of 2) 14 A B C D E F G H J K L M N P R T U V W Y AA AB AC A D AE AF VSS VCC VSS VCC VSS VCC 14 VCC VCC VCC VCC VCC VCC 15 VSS VSS VSS VSS VSS VSS 16 VCC VCC VCC VCC VCC VCC 17 VCC VCC VCC VCC VCC VCC 18 VSS VSS VSS VSS VSS VSS 19 VCC VCC DINV[3 ]# D[54]# VCC VCC 20 VSS VCC VSS VCC VSS VCC 15 VCC VCC VCC VCC VCC VCC 16 VSS VSS VSS VSS VSS VSS 17 VCC VCC VCC VCC VCC VCC 18 VCC VCC VCC VCC VCC VCC 19 VSS VSS VSS VSS VSS VSS 20 VCC VCC DBR# IERR# VCC VCC 21 BCLK[1] VSS BSEL[2] PROC HOT# VSS DRDY# VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS D[51]# D[52]# VSS D[59]# D[58]# VSS 21 22 BCLK[0] BSEL[0] VSS RSVD D[0]# VSS DSTBP[0] # D[3]# VSS D[14]# D[21]# VSS D[16]# D[25]# VSS RSVD D[39]# VSS D[41]# D[45]# VSS D[50]# D[48]# VSS D[55]# D[62]# 22 23 VSS BSEL[1] RSVD VSS D[7]# D[4]# VSS DSTBN[0] # D[11]# VSS D[22]# D[23]# VSS D[26]# D[19]# VSS D[37]# DINV[2]# VSS D[42]# D[32]# VSS D[49]# DSTBN[3] # VSS D[56]# 23 24 THRMDA VSS RSVD DPWR# VSS D[1]# D[9]# VSS D[10]# D[8]# VSS DSTBN[1] # D[31]# VSS D[28]# D[27]# VSS D[34]# DSTBN[2] # VSS D[47]# D[33]# VSS D[57]# DSTBP[3] # VSS 24 25 THRMDC RSVD VSS TEST2 D[6]# VSS D[5]# D[15]# VSS D[17]# D[20]# VSS DSTBP[1] # D[24]# VSS D[30]# D[38]# VSS D[36]# DSTBP[2] # VSS D[40]# D[53]# VSS D[60]# D[61]# 25 26 VSS VCCA TEST1 VSS D[2]# D[13]# VSS D[12]# DINV[0 ]# VSS D[29]# DINV[1 ]# VSS D[18]# COMP [0] VSS COMP [1] D[35]# VSS D[44]# D[43]# VSS D[46]# GTLREF VSS D[63]# 26 A B C D E F G H J K L M N P R T U V W Y A A A B AC A D AE AF Datasheet 37 Package Mechanical Specifications and Pin Information This page intentionally left blank. 38 Datasheet Package Mechanical Specifications and Pin Information Table 13. Pin Name A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# Pin Listing by Pin Name Pin Number J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 R4 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 13. Pin Name A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A20M# ADS# ADSTB[0]# ADSTB[1]# BCLK[0] BCLK[1] BNR# BPM[0]# BPM[1]# BPM[2]# BPM[3]# BPRI# BR0# BSEL[0] BSEL[1] BSEL[2] COMP[0] Pin Listing by Pin Name Pin Number T5 T3 W3 W5 Y4 W2 Y1 A6 H1 L2 V4 A22 A21 E2 AD4 AD3 AD1 AC4 G5 F1 B22 B23 C21 R26 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Source Synch Source Synch Bus Clock Bus Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock CMOS CMOS CMOS Power/Other Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input Input Input/ Output Input/ Output Output Output Input/ Output Input Input/ Output Output Output Output Input/ Output Datasheet 39 Package Mechanical Specifications and Pin Information Table 13. Pin Name COMP[1] COMP[2] COMP[3] D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# D[16]# D[17]# D[18]# Pin Listing by Pin Name Pin Number U26 U1 V1 E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 N22 K25 P26 Signal Buffer Type Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 13. Pin Name D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# Pin Listing by Pin Name Pin Number R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output 40 Datasheet Package Mechanical Specifications and Pin Information Table 13. Pin Name D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# Pin Listing by Pin Name Pin Number W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 13. Pin Name D[63]# DBR# DBSY# DEFER# DINV[0]# DINV[1]# DINV[2]# DINV[3]# DPRSTP# DPSLP# DPWR# DRDY# DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR# GTLREF HIT# HITM# Pin Listing by Pin Name Pin Number AF26 C20 E1 H5 J26 M26 V23 AC20 E5 B5 D24 F21 H23 M24 W24 AD23 G22 N25 Y25 AE24 A5 AD26 G6 E4 Signal Buffer Type Source Synch CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch CMOS CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Open Drain Power/Other Common Clock Common Clock Direction Input/ Output Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Not used Input Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Output Input Input/ Output Input/ Output Datasheet 41 Package Mechanical Specifications and Pin Information Table 13. Pin Name IERR# IGNNE# INIT# LINT0 LINT1 LOCK# PRDY# PREQ# PROCHOT# PSI# PWRGOOD REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# RESET# RS[0]# RS[1]# RS[2]# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Pin Listing by Pin Name Pin Number D20 C4 B3 C6 B4 H4 AC2 AC1 D21 AE6 D6 K3 H2 K2 J3 L5 B1 F3 F4 G3 D2 F6 D3 C1 AF1 D22 C23 C24 Signal Buffer Type Open Drain CMOS CMOS CMOS CMOS Common Clock Common Clock Common Clock Open Drain CMOS CMOS Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Common Clock Common Clock Common Clock Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Direction Output Input Input Input Input Input/ Output Output Input Input/ Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input Table 13. Pin Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SLP# SMI# STPCLK# TCK TDI TDO TEST1 TEST2 THERMDA THERMDC THERMTRIP # TMS TRDY# TRST# Pin Listing by Pin Name Pin Number AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25 D7 A3 D5 AC5 AA6 AB3 C26 D25 A24 A25 C7 AB5 G2 AB6 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 Signal Buffer Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CMOS CMOS CMOS CMOS CMOS Open Drain Test Test Power/Other Power/Other Open Drain CMOS Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Input Input Input Input Input Input Input Output Direction Input VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 42 Datasheet Package Mechanical Specifications and Pin Information Table 13. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Listing by Pin Name Pin Number AC18 AC17 AF18 AF17 AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 13. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Listing by Pin Name Pin Number AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 43 Package Mechanical Specifications and Pin Information Table 13. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCSENSE VID[0] VID[1] VID[2] Pin Listing by Pin Name Pin Number B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7 E7 B26 K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21 AF7 AD6 AF5 AE5 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS CMOS Output Output Output Direction Table 13. Pin Name VID[3] VID[4] VID[5] VID[6] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number AF4 AE3 AF2 AE2 AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 Signal Buffer Type CMOS CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output Output Output 44 Datasheet Package Mechanical Specifications and Pin Information Table 13. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 13. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1 K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 45 Package Mechanical Specifications and Pin Information Table 13. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 13. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE Pin Listing by Pin Name Pin Number G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21 AE7 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Direction Table 14. Pin Number A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Pin Listing by Pin Number Pin Name SMI# VSS FERR# A20M# VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS Signal Buffer Type CMOS Power/Other Open Drain CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Direction Input 46 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Number A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 Pin Listing by Pin Number Pin Name VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THERMDA THERMDC VSS RSVD VSS RSVD RSVD VSS TDI VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC D[51]# VSS D[32]# D[47]# VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Bus Clock Bus Clock Power/Other Power/Other Power/Other Power/Other Reserved Power/Other Reserved Reserved Power/Other CMOS Power/Other Power/other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input Input Input Direction Table 14. Pin Number AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 Pin Listing by Pin Number Pin Name D[43]# VSS RSVD TDO VSS TMS TRST# VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC D[52]# D[50]# VSS D[33]# D[40]# VSS PREQ# PRDY# VSS BPM[3]# TCK Signal Buffer Type Source Synch Power/Other Reserved Open Drain Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other Common Clock CMOS Input/ Output Input Input Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input Output Direction Input/ Output Datasheet 47 Package Mechanical Specifications and Pin Information Table 14. Pin Number AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 Pin Listing by Pin Number Pin Name VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS DINV[3]# VSS D[48]# D[49]# VSS D[53]# D[46]# BPM[2]# VSS BPM[1]# BPM[0]# VSS VID[0] VCC VSS VCC VCC VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Input/ Output Input/ Output Input/ Output Output Input/ Output Input/ Output Input/ Output Direction Table 14. Pin Number AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 Pin Listing by Pin Number Pin Name VCC VSS VCC VCC VSS VCC VCC VSS D[54]# D[59]# VSS DSTBN[3]# D[57]# VSS GTLREF VSS VID[6] VID[4] VSS VID[2] PSI# VSSSENSE VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other CMOS CMOS Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Direction 48 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Number AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 Pin Listing by Pin Number Pin Name VCC D[58]# D[55]# VSS DSTBP[3]# D[60]# VSS RSVD VID[5] VSS VID[3] VID[1] VSS VCCSENSE VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS D[62]# D[56]# VSS D[61]# Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Reserved CMOS Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Input/ Output Input/ Output Input/ Output Output Output Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 14. Pin Number AF26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 Pin Listing by Pin Number Pin Name D[63]# RESET# RSVD INIT# LINT1 DPSLP# VSS VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS BSEL[0] BSEL[1] VSS RSVD VCCA RSVD VSS RSVD IGNNE# VSS LINT0 THERMTRIP # VSS Signal Buffer Type Source Synch Common Clock Reserved CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Power/Other Reserved Power/Other Reserved Power/Other Reserved CMOS Power/Other CMOS Open Drain Power/Other Input Output Input Output Output Input Input Input Direction Input/ Output Input Datasheet 49 Package Mechanical Specifications and Pin Information Table 14. Pin Number C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 Pin Listing by Pin Number Pin Name VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS DBR# BSEL[2] VSS RSVD RSVD VSS TEST1 VSS RSVD RSVD VSS STPCLK# PWRGOOD SLP# VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Power/Other Reserved Reserved Power/Other Test Power/Other Reserved Reserved Power/Other CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Output Output Direction Table 14. Pin Number D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 Pin Listing by Pin Number Pin Name IERR# PROCHOT# RSVD VSS DPWR# TEST2 VSS DBSY# BNR# VSS HITM# DPRSTP# VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS D[0]# D[7]# VSS D[6]# Signal Buffer Type Open Drain Open Drain Reserved Power/Other Common Clock Test Power/Other Common Clock Common Clock Power/Other Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Not used Input/ Output Input/ Output Input Direction Output Input/ Output 50 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Number E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 Pin Listing by Pin Number Pin Name D[2]# BR0# VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC DRDY# VSS D[4]# D[1]# VSS D[13]# VSS TRDY# RS[2]# Signal Buffer Type Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Common Clock Common Clock Input Input/ Output Input/ Output Input/ Output Input/ Output Input Input Direction Input/ Output Input/ Output Table 14. Pin Number G4 G5 G6 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 Pin Listing by Pin Number Pin Name VSS BPRI# HIT# VCCP DSTBP[0]# VSS D[9]# D[5]# VSS ADS# REQ[1]# VSS LOCK# DEFER# VSS VSS D[3]# DSTBN[0]# VSS D[15]# D[12]# A[9]# VSS REQ[3]# A[3]# VSS Signal Buffer Type Power/Other Common Clock Common Clock Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Common Clock Common Clock Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Direction Input J5 Datasheet 51 Package Mechanical Specifications and Pin Information Table 14. Pin Number J6 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L21 L22 Pin Listing by Pin Number Pin Name VCCP VCCP VSS D[11]# D[10]# VSS DINV[0]# VSS REQ[2]# REQ[0]# VSS A[6]# VCCP VCCP D[14]# VSS D[8]# D[17]# VSS A[13]# ADSTB[0]# VSS A[4]# REQ[4]# VSS VSS D[21]# Signal Buffer Type Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 14. Pin Number L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N21 N22 N23 N24 N25 N26 Pin Listing by Pin Number Pin Name D[22]# VSS D[20]# D[29]# A[7]# VSS A[5]# RSVD VSS VCCP VCCP VSS D[23]# DSTBN[1]# VSS DINV[1]# VSS A[8]# A[10]# VSS RSVD VCCP VCCP D[16]# VSS D[31]# DSTBP[1]# VSS Signal Buffer Type Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Reserved Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Reserved Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output 52 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Number P1 P2 P3 P4 P5 P6 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R21 R22 R23 R24 R25 R26 T1 T2 T3 Pin Listing by Pin Number Pin Name A[15]# A[12]# VSS A[14]# A[11]# VSS VSS D[25]# D[26]# VSS D[24]# D[18]# A[16]# VSS A[19]# A[24]# VSS VCCP VCCP VSS D[19]# D[28]# VSS COMP[0] VSS RSVD A[26]# Signal Buffer Type Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Reserved Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output Table 14. Pin Number T4 T5 T6 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V21 Pin Listing by Pin Number Pin Name VSS A[25]# VCCP VCCP RSVD VSS D[27]# D[30]# VSS COMP[2] A[23]# VSS A[21]# A[18]# VSS VSS D[39]# D[37]# VSS D[38]# COMP[1] COMP[3] VSS RSVD ADSTB[1]# VSS VCCP VCCP Signal Buffer Type Power/Other Source Synch Power/Other Power/Other Reserved Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Reserved Source Synch Power/Other Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Datasheet 53 Package Mechanical Specifications and Pin Information Table 14. Pin Number V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Pin Listing by Pin Number Pin Name VSS DINV[2]# D[34]# VSS D[35]# VSS A[30]# A[27]# VSS A[28]# A[20]# VCCP D[41]# VSS DSTBN[2]# D[36]# VSS A[31]# A[17]# VSS A[29]# A[22]# VSS VSS D[45]# D[42]# Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 14. Pin Number Y24 Y25 Y26 Pin Listing by Pin Number Pin Name VSS DSTBP[2]# D[44]# Signal Buffer Type Power/Other Source Synch Source Synch Input/ Output Input/ Output Direction 54 Datasheet Package Mechanical Specifications and Pin Information 4.5 Table 15. Alphabetical Signals Reference Signal Description (Sheet 1 of 8) Name Type Description A[31:3]# (Address) define a 232-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel® Celeron® M processor FSB. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[31:17]# Associated Strobe ADSTB[0]# ADSTB[1]# A[31:3]# Input/ Output A20M# Input ADS# Input/ Output BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BNR# Input/ Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Celeron M processor FSB agents.This includes debug or performance monitoring tools. Please contact your Intel representative for more detailed information. BPM[2:1]# BPM[3,0]# Output Input/ Output Datasheet 55 Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 2 of 8) Name Type Description BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. The arbitration is done between the Celeron M processor (Symmetric Agent) and Intel® 945GMS and Intel 940GML Express Chipset (High Priority Agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 on page 23 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Celeron M processor operates 533 MHz system bus frequency (133-MHz BCLK[1:0] frequency). COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Please contact your Intel representative for more implementation details. D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DINV# 0 1 2 3 BPRI# Input BR0# Input/ Output BSEL[2:0] Output COMP[3:0] Analog Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBR# Output 56 Datasheet Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 3 of 8) Name Type Input/ Output Description DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/ Output agent. This signal must connect the appropriate pins of both FSB agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment to Data Bus DINV[3:0]# Input/ Output Bus Signal DINV[3]# DINV[2]# DINV[1]# DINV[0]# DPRSTP# Not used Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]# DBSY# DEFER# Input DPRSTP# is not used by the Celeron M processor. DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the ICH7-M chipset. DPWR# is a control signal from the Intel 945GMS and Intel 940GML Express Chipsets used to reduce power on the Celeron M data bus input buffers. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DPSLP# Input DPWR# Input DRDY# Input/ Output DSTBN[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Datasheet 57 Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 4 of 8) Name Type Description Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR#/PBE# Output FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volume 3 of the IA 32 Intel® Architecture Software Developer’s Manual and the Intel® Processor Identification and CPUID Instruction application note. For termination requirements, please contact your Intel representative. GTLREF Input GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. For termination requirements, please contact your Intel representative. HIT#/ HITM# Input/ Output IERR# Output 58 Datasheet Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 5 of 8) Name Type Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). For termination requirements, please contact your Intel representative. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Intel® Pentium® processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. Please contact your Intel representative for more implementation details. Probe Request signal used by debug tools to request debug operation of the processor. Please contact your Intel representative for more implementation details. IGNNE# Input INIT# Input LINT[1:0] Input LOCK# Input/ Output PRDY# Output PREQ# Input Datasheet 59 Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 6 of 8) Name Type Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system deasserts PROCHOT#. By default PROCHOT# is configured as an output only. Bidirectional PROCHOT# must be enabled via the BIOS. For termination requirements, please contact your Intel representative. This signal may require voltage translation on the motherboard. Please contact your Intel representative for more detailed information. Processor Power Status Indicator signal. This signal is asserted when the processor is in a lower state (Deep Sleep). Please contact your Intel representative for more details on the PSI# signal. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. For termination requirements, please contact your Intel representative. Input/ Output REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. There is a 55-Ω (nominal) on die pull-up resistor on this signal. RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please contact your Intel representative for more detailed information. PROCHOT# Input/ Output PSI# Output PWRGOOD Input REQ[4:0]# RESET# Input RSVD Reserved /No Connect 60 Datasheet Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 7 of 8) Name Type Description SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). Please contact your Intel representative for termination requirements and implementation details. TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. Please contact your Intel representative for termination requirements and implementation details. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Please contact your Intel representative for termination requirements and implementation details. TEST1 must have a stuffing option of separate pull-down resistor to VSS. Please contact your Intel representative for more detailed information. TEST2 must have a 51-Ω ±5% pull-down resistor to VSS. Please contact your Intel representative for more detailed information. Thermal Diode Anode. Thermal Diode Cathode. SLP# Input SMI# Input STPCLK# Input TCK Input TDI Input TDO Output TEST1 Input TEST2 THERMDA THERMDC Input Other Other Datasheet 61 Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 8 of 8) Name Type Description The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. For termination requirements, please contact your Intel representative. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Please contact your Intel representative for termination requirements and implementation details. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. Please contact your Intel representative for termination requirements and implementation details. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Please contact your Intel representative for termination requirements and implementation details. Processor core power supply. VCCA provides isolated power for the internal processor core PLL’s. Please contact your Intel representative for complete implementation details. Processor I/O Power Supply. VCCSENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure power near the silicon with little noise. Please contact your Intel representative for termination requirements and routing recommendations. VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike some previous generations of processors, these are CMOS signals that are driven by the Celeron M processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. Please contact your Intel representative for termination requirements and routing recommendations. THERMTRIP# Output TMS Input TRDY# Input TRST# Input VCC VCCA VCCP VCCSENSE Input Input Input Output VID[6:0] Output VSSSENSE Output § 62 Datasheet Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The Celeron M processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor via a heat pipe or direct die attachment. A secondary fan or air from the processor fan may also be used to cool other platform components or to lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 16 and Table 17. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. Contact your Intel representative for more details on processor and system level cooling approaches. The maximum junction temperature is defined by an activation of the processor Intel® Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 16 and Table 17. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification. Datasheet 63 Thermal Specifications and Design Considerations Table 16. Power Specifications for the Celeron M Processor Standard Voltage Symbol 450 440 TDP 430 420 410 Symbol PAH, PSGNT PSLP Processor Number Core Frequency & Voltage 2.00 GHz & HFM VCC 1.86 GHz & HFM VCC 1.73 GHz & HFM VCC 1.60 GHz & HFM VCC 1.46 GHz & HFM VCC Parameter Auto Halt, Stop Grant Power Min Thermal Design Power 27 27 27 27 27 Typ Max 10.1 Unit W At 50°C 2 At 50°C 2 At 35°C 2 3, 4 W 1, 4 Unit Notes Sleep Power at VCC 10.0 W PDSLP TJ Deep Sleep Power at VCC Junction Temperature 0 6.5 100 W °C NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 64 Datasheet Thermal Specifications and Design Considerations Table 17. Power Specifications for the Celeron M Processor Ultra Low Voltage Symbol TDP Symbol PAH, PSGNT PSLP 443 423 Processor Number Core Frequency & Voltage 1.20 GHz & HFM VCC 1.06 GHz & HFM VCC Parameter Auto Halt, Stop Grant Power Min Thermal Design Power 5.5 Typ Max 3.0 Unit W Unit W At 50°C 2 At 50°C 2 At 35°C 2 3, 4 Notes 1, 4 Sleep Power at VCC 2.9 W PDSLP TJ Deep Sleep Power at VCC Junction Temperature 0 1.5 100 W °C NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5.1 Thermal Specifications The Celeron M processor incorporates three methods of monitoring die temperature, the Digital thermal sensor, Intel Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1.3) must be used to determine when the maximum specified processor junction temperature has been reached. 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to Ground. The thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor model specific register (MSR) and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage recommendation when the PROCHOT# signal is not asserted. Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, Datasheet 65 Thermal Specifications and Design Considerations on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change. Offset between the thermal diode-based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the Intel Core Duo and Intel Core Solo processors’ MSR. Table 18, Table 19, Table 20, and Table 21 provide the diode interface and specifications. Two different sets of diode parameters are listed in Table 19 and Table 20. The Diode Model parameters (Table 19) apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature. Transistor Model parameters (Table 20) have been added to support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. Please contact your external thermal sensor supplier for their recommendation. This thermal diode is separate from the Intel Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor. Table 18. Thermal Diode Interface Signal Name THERMDA THERMDC Pin/Ball Number A24 A25 Signal Description Thermal diode anode Thermal diode cathode Table 19. Thermal Diode Parameters using Diode Model Symbol IFW n RT Parameter Forward Bias Current Diode Ideality Factor Series Resistance Min 5 1.000 2.79 Typ 1.009 4.52 Max 200 1.050 6.24 Unit µA Ω Notes 1 2, 3, 4 2, 3, 5 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. Characterized across a temperature range of 50 – 100°C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW = IS * (e qVD/nkT –1) where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 66 Datasheet Thermal Specifications and Design Considerations 5. The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature. RT, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N] where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic charge. Table 20. Thermal Diode Parameters using Transistor Mode Symbol IFW IE nQ Beta RT Series Resistance Parameter Forward Bias Current Emitter Current Transistor Ideality Min 5 5 0.997 0.3 2.79 4.52 1.001 Typ Max 200 200 1.005 0.760 6.24 Ω Unit µA µA 3, 4, 5 3, 4 3, 6 Notes 1, 2 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 19 3. Characterized across a temperature range of 50 - 100 °C. 4. Not 100% tested. Specified by design characterization. 5. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current: IC = IS * (e qVBE/nQkT –1) Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin). 6. The series resistance, RT, provided in the Diode Model Table (Table 19) can be used for more accurate readings as needed. When calculating a temperature based on thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although some are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 19. In most temperature sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode the ideality value (also called ntrim) will be 1.000. Given that most diodes are not perfect, the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. If the processors diode ideality deviates from that of ntrim, each calculated temperature will be offset by a fixed amount. This temperature offset can be calculated with the equation: Terror(nf) = Tmeasured X (1 - nactual/ntrim) Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing device. Datasheet 67 Thermal Specifications and Design Considerations 5.1.2 Thermal Diode Offset In order to improve the accuracy of diode based temperature measurements, a temperature offset value (specified as Toffset) will be programmed into a Intel Core Duo and Intel Core Solo processors’ MSR, which will contain thermal diode characterization data. During manufacturing each processors thermal diode will be evaluated for its behavior relative to a theoretical diode. Using the equation above, the temperature error created by the difference between ntrim and the actual ideality of the particular processor will be calculated. If the ntrim value used to calculate Toffset differs from the ntrim value used in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the actual ntrim as defined in the temperature sensor manufacturers' datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 21. Table 21. Thermal Diode ntrim and Diode Correction Toffset Symbol ntrim Parameter Diode ideality used to calculate Toffset 1.01 Unit Contact your Intel representative for more details on the temperature offset MSR definition and recommended offset implementation. 5.1.3 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An underdesigned thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses this mode to activate the TCC: Automatic mode and on-demand mode. If both modes are activated, Automatic mode takes precedence. Note: The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. This automatic mode is called Intel Thermal Monitor 1 (TM1). This mode is selected by writing values to the Model Specific Registers (MSRs) of the processor. After Automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. 68 Datasheet Thermal Specifications and Design Considerations When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a noncritical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSRs, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep and Deep Sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. Contact your Intel representative for more details on the Intel Thermal Monitor register and programming details. If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3.5. Datasheet 69 Thermal Specifications and Design Considerations 5.1.4 Digital Thermal Sensor The Celeron M processor also contains an on die digital thermal sensor that can be read via a MSR (no I/O interface). The digital thermal sensor is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor. The digital thermal sensor is only valid while the processor is in the normal operating state (C0 state). Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature relative to the maximum supported operating temperature of the processor (TJ,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the digital thermal sensor will always be at or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the Intel Thermal Monitor (TM1) trigger point. When the DTS indicates maximum processor core temperature has been reached TM1 hardware thermal control mechanism will activate. The DTS and Intel Thermal Monitor (TM1) temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications. Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the IA-32 Intel® Architecture Software Developer's Manual and your Intel representative for specific register and programming details. 5.1.5 Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s TM1 is triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt. For more details on the interrupt mechanism, contact your Intel representative. 5.1.6 PROCHOT# Signal Pin An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 is enabled (note that the Intel Thermal Monitor 1 must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the IA-32 Intel® Architecture Software Developer's Manuals and your Intel representative for specific register and programming details. The Celeron M processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has 70 Datasheet Thermal Specifications and Design Considerations reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. When PROCHOT# is driven by an external agent, TM1 is enabled and the processor core will have their core clocks modulated. One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An underdesigned thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Contact your Intel representative for details on implementing the bi-directional PROCHOT# feature. § Datasheet 71