6400

Intel® 6400/6402 Advanced Memory Buffer Datasheet October 2006 Reference Number: 313072-002 IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. 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All Rights Reserved. 2 Intel® 6400/6402 Advanced Memory Buffer Datasheet Contents 1 Introduction ............................................................................................................ 11 1.1 Intel® 6400/6402 Advanced Memory Buffer Overview ............................................ 11 1.1.1 Transparent Mode for DRAM Test Support.................................................. 12 1.1.2 Debug and Logic Analyzer Interface .......................................................... 12 1.1.3 DDR SDRAM .......................................................................................... 12 1.2 AMB Block Diagram ........................................................................................... 12 1.3 Interfaces ........................................................................................................ 13 1.3.1 FBD High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces ............................................................................................ 14 1.3.2 DDR2 Channel ....................................................................................... 14 1.3.3 SMBus Slave Interface ............................................................................ 14 1.4 References ....................................................................................................... 15 FBD Channel Interface ............................................................................................. 17 2.1 Intel 6400/6402 Advanced Memory Buffer (AMB) Support for FBD Operating Modes .. 17 2.2 Channel Initialization ......................................................................................... 17 2.3 Channel Protocol ............................................................................................... 17 2.3.1 General................................................................................................. 17 2.3.2 Timeouts During TS0 .............................................................................. 17 2.3.3 Recalibrate State Considerations .............................................................. 18 2.3.4 Address Mapping of DDR Commands to DRAMs .......................................... 19 2.3.5 FBD L0s State........................................................................................ 19 2.4 Reliability, Availability, and Serviceability ............................................................. 19 2.4.1 Channel Error Detection and Logging ........................................................ 19 2.5 Channel Configuration........................................................................................ 19 2.5.1 Re-sync and Resample Modes .................................................................. 19 2.5.2 Other Channel Configuration Modes .......................................................... 20 2.5.3 Lane to Lane Skew on a Channel .............................................................. 20 2.6 Repeater Mode.................................................................................................. 21 2.7 Channel Latency ............................................................................................... 21 2.7.1 Command to Data Delay Calculation ......................................................... 21 DDR Interface.......................................................................................................... 25 3.1 Intel 6400/6402 Advanced Memory Buffer (AMB) DDR Interface Overview ............... 25 3.2 Data Mapping ................................................................................................... 25 3.3 Command / Address Outputs .............................................................................. 26 3.3.1 CKE Output Control ................................................................................ 27 3.4 DQS I/O and DM Outputs ................................................................................... 27 3.5 Refresh ............................................................................................................ 28 3.5.1 Self-Refresh During Channel Reset ........................................................... 29 3.5.2 Automatic Refresh .................................................................................. 29 3.6 Back to Back Turnaround Time............................................................................ 30 3.7 S3 State Background Description......................................................................... 31 3.7.1 S3 Recovery Configuration Registers......................................................... 32 3.8 DDR Calibration ................................................................................................ 32 3.8.1 DRAM Initialization and (E)MRS FSM ......................................................... 32 3.8.2 DQS Failure CSR .................................................................................... 33 3.8.3 Automatic DDR Bus Calibration ................................................................ 34 3.8.4 Receive Enable Calibration....................................................................... 34 3.8.5 DQS Delay Calibration............................................................................. 34 3.9 DIMM Organization ............................................................................................ 35 Electrical, Power, and Thermal ................................................................................ 37 4.1 Electrical DC Parameters .................................................................................... 37 2 3 4 Intel® 6400/6402 Advanced Memory Buffer Datasheet 3 4.2 4.3 4.4 4.5 4.6 4.7 4.1.1 Absolute Maximum Ratings ......................................................................37 4.1.2 Operating DC Parameters ........................................................................37 4.1.3 AMB Power Specifications ........................................................................38 FB-DIMM Electrical Timing Specifications...............................................................44 DDR2 DRAM Interface Electrical Specifications .......................................................45 DDR2 Electrical Output Timing Specifications .........................................................46 4.4.1 Description of DQ/DQS Alignment .............................................................46 4.4.2 Description of ADD/CMD/CNTL Outputs......................................................46 4.4.3 Test Load Specification ............................................................................46 4.4.4 tDVA and tDVB Parameter Description .......................................................46 4.4.5 tjit and tjitHP Parameter Description..........................................................46 4.4.6 tCVA, tCVB, tECVA and tECVB Parameter Description...................................47 4.4.7 tDQSCK Timing Parameter Description.......................................................47 4.4.8 DQ and CB (ECC) Setup/Hold Relationships to/from DQS (Read Operation) ....................................................................................48 4.4.9 Write Preamble Duration..........................................................................49 4.4.10 Write Postamble Duration ........................................................................49 4.4.11 Advance Memory Buffer Component Electrical Timing Summary ....................50 4.4.12 Reference DDR2 Interface Package Trace Lengths .......................................51 SMBUS Interface ...............................................................................................51 Miscellaneous I/O (1.5 Volt CMOS Driver) .............................................................51 Thermal Diode and Analog to Digital Converter (ADC).............................................51 4.7.1 Thermal Sensor Effects on the AMB’s Functional Behavior.................................................................................52 5 Debug and Logic Analyzer Mode ...............................................................................53 5.1 Logic Analyzer Interface (LAI) Mode .....................................................................53 5.1.1 LAI Mode Architecture .............................................................................54 5.1.2 LAI Mode Clocking ..................................................................................55 5.1.3 LAI Mode Pins ........................................................................................55 5.1.4 LAI Mode Signal Definitions ......................................................................56 5.1.5 LAI to DDR Pin Mapping...........................................................................57 5.1.6 FBD to LAI Signal Mapping .......................................................................58 5.1.7 LAI to DDR Pin Timing .............................................................................59 5.1.8 LAI Features ..........................................................................................60 5.1.9 LAI Block Diagram ..................................................................................67 5.2 Normal Mode Debug Features..............................................................................68 5.2.1 Normal Mode Debug Triggers ...................................................................68 5.2.2 Error Injection........................................................................................68 Errors ......................................................................................................................71 6.1 Types of Errors and Responses ............................................................................71 6.1.1 FBD Link Errors ......................................................................................71 6.1.2 DDR Errors ............................................................................................73 6.1.3 Host Protocol Errors ................................................................................73 6.1.4 Other Errors...........................................................................................74 6.2 Error Logging ....................................................................................................74 6.2.1 Error Logging Procedure ..........................................................................74 6.3 Fail Over Mode Support ......................................................................................75 6.4 Failback to Pass-Thru .........................................................................................75 SMBus Interface ......................................................................................................77 7.1 System Management Access ...............................................................................77 7.1.1 SMBus 2.0 Specification Compatibility........................................................77 7.1.2 Supported SMBus Commands ...................................................................77 7.1.3 FBD AMB Register Access Protocols ...........................................................78 7.1.4 SMBus Error Handling..............................................................................81 7.1.5 SMBus Resets ........................................................................................81 6 7 4 Intel® 6400/6402 Advanced Memory Buffer Datasheet 8 Clocking .................................................................................................................. 83 8.1 Intel 6400/6402 Advanced Memory Buffer (AMB) Clock Domains ............................. 83 8.2 PLL Clocks ........................................................................................................ 85 8.3 Reference Clock ................................................................................................ 85 8.4 FBD Lane Frame Clocks...................................................................................... 86 8.5 Clock Ratios ..................................................................................................... 86 8.6 DDR DRAM Clock Support................................................................................... 86 8.7 SMBus ............................................................................................................. 86 8.8 Clock Pins ........................................................................................................ 86 8.9 Additional Clock Modes....................................................................................... 87 8.9.1 Transparent Mode Clocking...................................................................... 87 8.10 PLL Requirements.............................................................................................. 87 8.10.1 Jitter .................................................................................................... 87 8.10.2 PLL Bandwidth Requirements ................................................................... 87 8.10.3 External Reference ................................................................................. 87 8.10.4 Spread Spectrum Support ....................................................................... 88 8.10.5 Frequency of Operation ........................................................................... 88 8.10.6 RESET# ................................................................................................ 88 8.10.7 Other PLL Characteristics......................................................................... 88 8.11 Analog Power Supply Pins................................................................................... 89 Reset ....................................................................................................................... 91 9.1 Platform Reset Functionality ............................................................................... 91 9.1.1 Platform RESET# Requirements ............................................................... 91 9.1.2 RESET# Requirements ............................................................................ 91 9.1.3 Power-Up and Suspend-to-RAM Considerations .......................................... 92 9.2 Reset Types...................................................................................................... 92 9.3 Pads Controlling Reset ....................................................................................... 92 9.3.1 RESET# Pad .......................................................................................... 92 9.3.2 Primary FBD Link ................................................................................... 93 9.4 Details ............................................................................................................. 93 9.4.1 Cold Power-Up Reset Sequence ................................................................ 93 9.4.2 S3 Restore Power-Up Reset Sequence ....................................................... 94 9.4.3 Reset Sequence for a Fast Reset .............................................................. 95 9.4.4 Fast Reset Handshake............................................................................. 95 9.4.5 Timing Diagrams .................................................................................... 96 9.5 I/O Initialization ................................................................................................ 97 9.5.1 FBD Channel Initialization........................................................................ 97 9.5.2 DDR ..................................................................................................... 97 Transparent Mode ................................................................................................... 99 10.1 Transparent Mode ............................................................................................. 99 10.1.1 Block Diagram ..................................................................................... 100 10.1.2 Transparent Mode Signal Definitions ....................................................... 100 10.1.3 Transparent Mode to FBD Pin Mapping .................................................... 101 10.2 Transparent Mode Timing ................................................................................. 102 10.2.1 Clock Frequency and Core Timing ........................................................... 102 10.2.2 Edge Placement Accuracy ...................................................................... 102 10.2.3 Transparent Mode Timing ...................................................................... 102 10.2.4 Error Reporting .................................................................................... 106 10.2.5 Transparent Mode IO Specifications ........................................................ 107 10.2.6 IO Implementation Guidelines ................................................................ 108 10.3 Transparent Mode Control and Status Registers................................................... 109 DDR 11.1 11.2 11.3 MemBIST ....................................................................................................... 111 MemBIST Overview ......................................................................................... 111 MemBIST Feature Summary ............................................................................. 112 MemBIST Operation......................................................................................... 113 5 9 10 11 Intel® 6400/6402 Advanced Memory Buffer Datasheet 11.4 11.5 11.3.1 Fundamental Operations ........................................................................ 113 11.3.2 Memory Addressing .............................................................................. 114 11.3.3 Memory Data Formatting ....................................................................... 123 11.3.4 Algorithmic Testing ............................................................................... 126 11.3.5 Error Reporting and Control ................................................................... 128 11.3.6 DRAM Throttling ................................................................................... 131 11.3.7 Refresh Control .................................................................................... 131 11.3.8 DRAM Initialization................................................................................ 132 MemBIST Memory Test Examples ...................................................................... 132 11.4.1 Write a Fixed Pattern to a Range of DRAM Addresses................................. 132 11.4.2 Write Random Data to a Range of DRAM Addresses and Check ................... 133 11.4.3 Write Leaping 0s to the Full DRAM Address Range and Check ..................... 134 11.4.4 Write 144-bit User-defined Pattern to a Range of Addresses and Check ........ 136 11.4.5 Test a Range of DRAM Addresses With March C- Algorithm ........................ 137 MemBIST Implementation................................................................................. 138 11.5.1 MemBIST Block Diagram ....................................................................... 138 11.5.2 MB Flow Control State Machine ............................................................... 139 11.5.3 CS Finite State Machine ......................................................................... 141 12 Ballout and Package Information ........................................................................... 143 12.1 Ballout .......................................................................................................... 143 12.2 655-Ball FBGA 0.8mm Pitch Pin Configuration...................................................... 143 12.3 Pin Assignments for the Advanced Memory Buffer (AMB)....................................... 144 12.4 Package Information ........................................................................................ 152 Signal Lists ............................................................................................................ 155 13.1 Conventions.................................................................................................... 155 13.2 Intel 6400/6402 Advanced Memory Buffer (AMB) Pin Description List...................... 156 Registers ............................................................................................................... 159 14.1 Access Mechanisms.......................................................................................... 159 14.1.1 Conflict Resolution and Usage Model Limitations ....................................... 159 14.1.2 FBD Data on Configuration Read Returns ................................................. 159 14.1.3 Non-Existent Register Bits...................................................................... 159 14.1.4 Register Attribute Definition ................................................................... 160 14.1.5 Binary Number Notation ........................................................................ 161 14.1.6 Function Mapping ................................................................................. 161 14.2 PCI Standard Header Identification Registers (Function 0) ..................................... 169 14.2.1 VID: Vendor Identification Register ......................................................... 169 14.2.2 DID: Device Identification Register.......................................................... 169 14.2.3 RID: Revision Identification Register ....................................................... 169 14.2.4 CCR: Class Code Register ...................................................................... 170 14.2.5 HDR: Header Type Register.................................................................... 170 14.3 FBD Link Registers (Function 1) ......................................................................... 170 14.3.1 FBD Link Control and Status................................................................... 170 14.3.2 SM Bus Register ................................................................................... 180 14.3.3 Error Registers ..................................................................................... 181 14.3.4 PERSONALITY BYTES Loaded From the SPD.............................................. 183 14.3.5 Hardware Configuration Registers ........................................................... 184 14.4 Implementation Specific FBD Registers (Function 2) ............................................. 185 14.5 DDR and Miscellaneous Registers (Function 3) ..................................................... 186 14.5.1 Memory Registers ................................................................................. 186 14.5.2 Memory BIST Registers ......................................................................... 191 14.5.3 Thermal Sensor Registers ...................................................................... 201 14.6 Implementation Specific DDR Initialization and Calibration Registers (Function 4) ...................................................................... 203 14.6.1 DDR Calibration .................................................................................... 203 14.6.2 Memory Interface Control ...................................................................... 219 13 14 6 Intel® 6400/6402 Advanced Memory Buffer Datasheet 14.7 14.8 14.6.3 Firmware Support Registers................................................................... 221 DFX Registers (Function 5) ............................................................................... 222 14.7.1 Transparent Mode Registers................................................................... 222 14.7.2 Logic Analyzer Interface (LAI) Registers .................................................. 223 14.7.3 Error Injection Registers........................................................................ 230 Bring-up and Debug Registers (Function 6)......................................................... 231 14.8.1 SPAD[1:0]: Scratch Pad ........................................................................ 231 14.8.2 Southbound FBD Intel® Interconnect BIST Registers................................. 231 14.8.3 Northbound FBD Intel IBIST Registers..................................................... 236 15 SPD Bits ................................................................................................................ 243 15.1 Access Mechanisms ......................................................................................... 243 15.1.1 Raw Cards A, B, and C .......................................................................... 243 15.1.2 Raw Cards D, E, H, and J....................................................................... 244 15.1.3 Category Byte 99 ................................................................................. 245 Glossary ................................................................................................................ 247 A.1 Terms and Definitions ...................................................................................... 247 1-1 1-2 2-1 2-2 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 7-1 7-2 7-3 7-4 7-5 7-6 8-1 8-2 9-1 9-2 10-1 Advanced Memory Buffer Block Diagram............................................................... 13 AMB Interfaces ................................................................................................. 14 Delays Through an AMB ..................................................................................... 22 Command to Data Delay Timing .......................................................................... 23 Nominal Turnaround Time Timing Diagram ........................................................... 31 Latency Timing Diagrams ................................................................................... 44 tDVA and tDVB Timing Diagram .......................................................................... 46 tjit and tjitHP Timing Diagram ............................................................................. 47 tCVA and tCVB Timing Diagram ........................................................................... 47 tECVA and tECVB Timing Diagram ....................................................................... 47 TDQSCK Timing Diagram.................................................................................... 48 DQ and CB (ECC) Setup/Hold Relationship to/from DQS Timing Diagram .................. 48 Write Preamble Duration Timing Diagram ............................................................. 49 Write Postamble Duration Timing Diagram ............................................................ 49 AMB LAI Mode Usage Diagram ............................................................................ 54 AMB LAI Mode Connectivity ................................................................................ 55 LAI Signal Group Timing..................................................................................... 60 LAI Match and Mask Logic .................................................................................. 61 Local Event Mux Block Diagram ........................................................................... 62 EVBus Overview ................................................................................................ 64 Event Bus Signal Timing..................................................................................... 65 LAI Qualification Signal Block Diagram ................................................................. 66 Block Diagram of AMB in LAI Mode ...................................................................... 67 SMBus Configuration Read (Block Write / Block Read, PEC Enabled) ......................... 79 SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled) ........................ 80 SMBus Configuration Double Word Write (Block Write, PEC Enabled) ........................ 80 SMBus Configuration Double Word Write (Write Bytes, PEC Enabled)........................ 81 SMBus Configuration Word Write (Block Write, PEC Disabled) .................................. 81 SMBus Configuration Byte Write (Write Bytes, PEC Disabled)................................... 81 AMB Clock Domains ........................................................................................... 84 FBD PLL Power Supply Filter ............................................................................... 89 Cold Power-Up Reset ......................................................................................... 96 AMB Fast Reset Sequence .................................................................................. 96 DRAM Architecture ............................................................................................ 99 A Figures Intel® 6400/6402 Advanced Memory Buffer Datasheet 7 10-2 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 12-1 12-2 12-3 12-4 Block Diagram for the AMB in transparent mode .................................................. 100 Transparent Mode Timing ................................................................................. 103 Transparent Mode Write Timing ......................................................................... 104 Transparent Mode Read Timing.......................................................................... 105 BL=8 Read Timing ........................................................................................... 105 Range and Full Address Spaces.......................................................................... 117 Fast Y Address Sequencing ............................................................................... 119 Fast X Address Sequencing ............................................................................... 120 Fast XY Address Sequencing Examples ............................................................... 121 MemBIST Circular Shift and LFSR Data Block Diagram .......................................... 124 MemBIST Block Diagram .................................................................................. 138 MBFSM Diagram .............................................................................................. 139 CS State Machine ............................................................................................ 141 Pinout Configuration......................................................................................... 143 Bottom View ................................................................................................... 152 Top View ........................................................................................................ 153 Package Stackup ............................................................................................. 154 Tables 3-1 4-1 DQS Association with DQ/CB Pins in x8 and x4 Mode ..............................................27 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (See Note 1) .....................................................................................................37 4-2 AMB Operating DC Electrical Parameters ...............................................................37 4-3 Power Values for x8 DIMMS ................................................................................38 4-4 Power Values for x4 DIMMs .................................................................................41 4-5 AMB FB-DIMM Timing/Electrical ...........................................................................44 4-6 AMB FB-DIMM Latency .......................................................................................44 4-7 Recommended Operating Conditions for DRAM Interface .........................................45 4-8 Advance Memory Buffer Component DDR2 Electrical Timing Specifications.................50 4-9 Advance Memory Buffer DDR2 Package Lengths.....................................................51 4-10 Recommended Operating Conditions for SMBUS Interface .......................................51 4-11 Recommended Operating Conditions for RESET and BFUNC Pins...............................51 5-1 DDR Pins Shared With LAI Functionality ................................................................56 5-2 List of Pins Required to Enable Debug With LAI Functionality ...................................56 5-3 LAI Mode Added Signals .....................................................................................56 5-4 List of Shared DDR/LAI Pins ................................................................................57 5-5 Typical FBD Southbound Command Frame ............................................................59 5-6 LAI Local Events ................................................................................................62 5-7 LAI Event Selection ............................................................................................63 6-1 Link Errors in Initialization ..................................................................................71 6-2 Link Errors in Normal Operation ...........................................................................72 6-3 DDR Errors .......................................................................................................73 6-4 Host Protocol Errors ...........................................................................................73 6-5 Other Errors......................................................................................................74 7-1 SMBus Command Encoding .................................................................................78 7-2 SMBus Protocol Addressing Fields ........................................................................78 7-3 Status Field Encoding for SMBus Reads.................................................................79 8-1 PLL Clocks ........................................................................................................85 8-2 AMB Clock Ratios ...............................................................................................86 8-3 Clock Pins .........................................................................................................86 10-1 Additional Signals in Transparent Mode............................................................... 101 8 Intel® 6400/6402 Advanced Memory Buffer Datasheet 10-2 10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 12-1 12-2 12-3 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 15-1 15-2 15-3 Mapping of FBD Pins in Transparent Mode........................................................... 101 Mapping of Burst Position Bits to Error Capture.................................................... 106 Selection of 8 bit Data Paths When ENDOUT is Set............................................... 107 Transparent Mode FB-DIMM Interface Signaling Specifications ............................... 107 MemBIST Feature Summary ............................................................................. 112 Memory Address Definition, BL=4...................................................................... 114 Memory Address Definition, BL=8...................................................................... 115 MemBIST Addressing Behavior .......................................................................... 116 Dynamic Address Inversion, XZY Address Sequencing and Range Addressing .......... 122 Example of Circular Data Shifting ...................................................................... 125 Example of LFSR Random Data ......................................................................... 126 Address Log to Bank, Row and Column Bit Correspondence................................... 129 Failure Data Bit Location Accumulator to MBDATA Bit Correspondence .................... 129 Failure to Logging Register Correspondence ........................................................ 130 Refresh Programming ...................................................................................... 132 655-Ball FBGA 0.8 mm Pitch - Left Side.............................................................. 144 655-Ball FBGA 0.8 mm Pitch - Right Side............................................................ 145 Advanced Memory Buffer Signals By Ball Number ................................................ 145 Signal Naming Conventions .............................................................................. 155 Buffer Signal Types ......................................................................................... 156 Pin Description................................................................................................ 156 Pin Count ....................................................................................................... 158 Access to “Non-existent” Register Bits................................................................ 159 Register Attributes Definitions ........................................................................... 160 Function Mapping Legend ................................................................................. 161 Function 0: PCI Standard Header Identification Registers...................................... 162 Function 1: FBD Link Registers.......................................................................... 163 Function 2: Implementation Specific FBD Registers .............................................. 164 Function 3: DDR and Miscellaneous Registers ..................................................... 165 Function 4: Implementation Specific DDR Initialization and Calibration Registers ..... 166 Function 5: DFX Registers ................................................................................ 167 Function 6: Bring-up and Debug Registers .......................................................... 168 MBDATA Failure Address Register Correspondence to DRAM Address ...................... 195 BL4 Column and Chunk Correspondence to DRAM Address .................................... 195 BL8 Column and Chunk Correspondence to DRAM Address .................................... 196 Functional Characteristics of DCALADDR ............................................................. 205 Functional Characteristics of DCALDATA for Calibration Algorithms ......................... 206 Functional Characteristics of DCALDATA for HVM Algorithms ................................. 208 Bit Locations for SB Match and Mask .................................................................. 224 Raw Cards A, B, and C ..................................................................................... 243 Raw Cards D, E, H, and J.................................................................................. 244 Category ByteJ ............................................................................................... 245 Intel® 6400/6402 Advanced Memory Buffer Datasheet 9 Revision History Revision 001 002 Updated Release Updated Chapter 15 SPD Bits tables Description Date May 2006 October 2006 § 10 Intel® 6400/6402 Advanced Memory Buffer Datasheet Introduction 1 Introduction This document is a core specification for a Fully Buffered DIMM (FB DIMM, also FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to an Intel® 6400/6402 Advanced Memory Buffer (AMB) design appears in the other specifications, with specific cross-references provided. 1.1 Intel® 6400/6402 Advanced Memory Buffer Overview The Intel 6400/6402 Advanced Memory Buffer (AMB) complies with the FB-DIMM Architecture and Protocol Specification. This device supports DDR2 SDRAM memory components. The AMB allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM devices resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for handling FBD channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the FBD channel. Fully Buffered DIMM (FBD) provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. Fully Buffered DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is 288 devices per channel and total memory capacity scales with DRAM bit density. The AMB will perform the following FBD channel functions: • Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB DIMM position. • Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames. • If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames. • Detects errors on the channel and reports them to the host memory controller. • Support the FBD configuration register set as defined in the register chapters. • Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM. • Provides a read buffer FIFO and a write buffer FIFO. • Supports an SMBus protocol interface for access to the AMB configuration registers. • Provides logic to support MemBIST and IBIST Design for Test (DFx) functions. • Provides a register interface for the thermal sensor and status indicator. • Functions as a repeater to extend the maximum length of FBD Links. Intel® 6400/6402 Advanced Memory Buffer Datasheet 11 Introduction 1.1.1 Transparent Mode for DRAM Test Support In this mode, the AMB will provide lower speed tester access to DRAM pins through the FBD I/O pins. This allows the tester to send an arbitrary test pattern to the DRAMs. Transparent mode only supports a maximum DRAM frequency equivalent to DDR2 400. Transparent mode functionality: • Reconfigures FBD inputs from differential high speed link receivers to two single ended lower speed receivers (~200 MHz) • These inputs directly control DDR2 Command/Address and input data that is replicated to all DRAMs • Uses low speed direct drive FBD outputs to bypass high speed Parallel/Serial circuitry and provide test results back to tester 1.1.2 Debug and Logic Analyzer Interface When optional LAI functionality is supported, the AMB can be used to support the connection of FBD links to a Logic Analyzer (LA) for debug. AMB debug functionality: • Reconfigures DDR2 interface to act as a Logic Analyzer Interface (LAI) to observe activity on FBD high speed links • Triggers on programmable events in normal operation 1.1.3 DDR SDRAM DDR2 SDRAM support: • Supports DDR2 at speeds of 533, 667 MT/s • Supports 256, 512, 1024, 2048 and 4096 Mb devices in x4 and x8 configurations • 288 devices/channel (8 DIMMs/channel, 1 and 2 ranks/DIMM) • 72-bit DDR2 SDRAM unregistered, unbuffered memory interface 1.2 AMB Block Diagram Figure 1-1 is a conceptual block diagram of the AMB’s data flow and clock domains. 12 Intel® 6400/6402 Advanced Memory Buffer Datasheet Introduction 1.3 Figure 1-1. Interfaces Advanced Memory Buffer Block Diagram Advance Memory Buffer Block DIagram 10x2 Southbound Data In 10x2 SOUTH 2/03/04 NORTH Southbound Data Out Data Merge Re-Time 1x2 PLL demux 10*12 Re-synch PISO 10*12 Ref Clock mux Reset# Reset Reset s Control Link Init SM and Control and CSRs Init patterns 4 DRAM Clock IBIST - RX Command Decoder & CRC Check failover LAI Logic IBIST - TX 4 DRAM Clock # Cmd Out 29 DRAM Address / Command Copy 1 mux DRAM Cmd Thermal Sensor DDR State Controller and CSRs Core Control and CSRs 36 deep Write Data FIFO 29 Data Out DDR IO’s 72 + 18x2 DRAM Address / Command Copy 2 mux DRAM Data / Strobe External MEMBIST DDR Calibration & DDR IOBIST/DFX Data In LAI Controller Data CRC Gen & Read FIFO Sync & Idle Pattern Generator IBIST - TX SMBus NB LAI Buffer IBIST - RX SMbus Controller mux Link Init SM and Control and CSRs failover 14*6*2 PISO demux Re-synch 14*12 Re-Time Data Merge Northbound Data Out Northbound Data In 14x2 14x2 Figure 1-2 illustrates the AMB and all of its interfaces. They consist of two FBD links, one DDR2 channel, and an SMBus interface. Each FBD link connects the AMB to a host memory controller or an adjacent FBD. The DDR2 channel supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM. Intel® 6400/6402 Advanced Memory Buffer Datasheet 13 Introduction Figure 1-2. AMB Interfaces MEMORY INTERFACE DDR2 CHANNEL Primary or Host Direction NB FBD Out Link NB FBD In Link AMB SB FBD Out Link SB FBD In Link SMB 1.3.1 FBD High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces The AMB supports one FBD Channel interface consisting of two bidirectional link interfaces using high-speed differential point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the first adjacent DIMM in the host direction. The southbound output link forwards this same data to the next adjacent FBD. The northbound input link is 13 to 14 lanes wide and carries read return data or status information from the next FB DIMM in the chain back towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. 1.3.2 DDR2 Channel The DDR2 channel on the AMB supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data signals, and eight check-bit signals. There are two copies of address and command signals to support DIMM routing and electrical requirements. Four-transfer bursts are driven on the data and check-bit lines at 800 MHz. Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The AMB provides four copies of the command clock phase references (CLK[3:0]) and write data/check-bit strobes (DQSs) for each DRAM nibble. 1.3.3 SMBus Slave Interface The AMB supports an SMBus interface to allow system access to configuration registers independent of the FBD link. The AMB will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100 kHz. 14 Intel® 6400/6402 Advanced Memory Buffer Datasheet Secondary or to optional next FBD Introduction SMBus access to the AMB may be a requirement to boot a system. This provides a mechanism to set link strength, frequency and other parameters needed to insure robust operation given platform specific configurations. It is also required for diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the AMB to get its unique ID. More information is available in the SMBus chapter of this document. Additionally, more detailed information about the SMBus, refer to the System Management Bus (SMBus) Specification [HTTP://smbus.org/]. 1.4 References This product and datasheet are consistent with the following documents: • FB DIMM Architecture and Protocol Specification, [1] • FBD Design for Test, Design for Validation (DFx) Specification, [2] • FB4300/5300/6400 DDR2 Fully Buffered DIMM Design Specification, [3] • JEDEC DDR2 SDRAM Specification, JC 42.3 [4] • High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM, [5] • SMBus Specification (http://smbus.org/specs/smbus20.pdf) [6] • Advanced Configuration and Power Interface Specification Version 2.0c (www.acpi.info) [7] • Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices, IPC/JEDEC J-STD-020C § Intel® 6400/6402 Advanced Memory Buffer Datasheet 15 Introduction 16 Intel® 6400/6402 Advanced Memory Buffer Datasheet FBD Channel Interface 2 2.1 FBD Channel Interface Intel 6400/6402 Advanced Memory Buffer (AMB) Support for FBD Operating Modes The AMB may not support all operating modes documented in the FB-DIMM Architecture and Protocol Specification [1]. The following list defines which features/ modes are supported: • 14 lane northbound (NB) with and without single lane Fail Over • 13 lane NB with and without single lane Fail Over • 10 lane southbound (SB) with and without single lane Fail Over • Repeater mode • LAI mode (optional feature supported in the Intel AMB) • Transparent mode • Recalibrate state The following are optional FBD features not supported in the AMB: • 12 lane NB non-ECC • L0s low power state • Data mask • Variable read latency 2.2 Channel Initialization Refer to Chapter 3, “Channel Initialization” in the FB DIMM Architecture and Protocol Specification [1] for FBD initialization protocol. The reset chapter covers some additional details about the initialization process. 2.3 2.3.1 Channel Protocol General Refer to Chapter 4, “Channel Protocol” in the FB DIMM Architecture and Protocol Specification [1] for FBD protocol. 2.3.2 Timeouts During TS0 The FBDLOCKTO register is used to help the AMB determine when to give up waiting for individual lanes to bit lock. The NBLINKCFG field is used to communicate when lanes are intentionally not in use. The BLTOCNT field is used to set a time out on waiting for a lane to bit lock. Lanes not bit locked by this time will be marked as failed. Intel® 6400/6402 Advanced Memory Buffer Datasheet 17 FBD Channel Interface 2.3.3 Recalibrate State Considerations In addition to what the FBD Architecture and Protocol specification describes around Recalibrate State, the AMB further requires that the host be sending NOP commands in at least the 2 frames preceding the exit from recalibrate state. Requirement: 2 Cycles before the recalibrate counter expires, NOPs must be sent from the host. Recal Frame Counter 0 RECALDUR RECALDUR - 1 .... RECALDUR - 7 RECALDUR - 8 .... 8 .... 4 3 2 1 0 Time N N+1 N+2 ... N+8 N+9 ... N + RECALDUR 7 ... N + RECALDUR 3 N + RECALDUR 2 N + RECALDUR 1 N + RECALDUR 0 Frame Description Sync with ERC bit set NOP frame NOP frame NOP frame NOP frame NOP frame - host may begin recalibration ..... NOP frame - host must be finished with recalibration ..... NOP frame NOP frame NOP frame - must be received at AMB without corruption NOP frame - must be received at AMB without corruption Valid Sync Frame Recal Frame Counter:54 3 Rx Data:X X X 2 NOP 1 NOP 0 Valid Cmd where X represents “don’t care” data 18 Intel® 6400/6402 Advanced Memory Buffer Datasheet FBD Channel Interface 2.3.4 DDR2 x4 Config 256Mb (64Mbx4) 1KB page 512Mb (128Mbx4) 1KB page 1Gb (256Mbx4) 1KB page 2Gb (512Mbx4) 1KB page DDR2 x8 Config 256Mb (32Mbx8) 1KB page 512Mb (64Mbx8) 1KB page 1Gb (128Mbx8) 1KB page 2Gb (256Mbx8) Address Mapping of DDR Commands to DRAMs Row Col Row Col Row Col Row Col 20 1 0 1 0 1 0 1 0 20 1 0 1 0 1 0 1 19 X 1 X 1 X 1 X 1 19 X 1 X 1 X 1 X 18 X r/w X r/w X r/w A 14 r/w 18 X r/w X r/w X r/w A 14 17 16 15 RS X X RS X X RS A 13 X RS X X RS A 13 B2 RS X B2 RS A 13 B2 RS X B2 14 B1 B1 B1 B1 B1 B1 B1 B1 14 B1 B1 B1 B1 B1 B1 B1 13 B0 B0 B0 B0 B0 B0 B0 B0 13 B0 B0 B0 B0 B0 B0 B0 12 A 12 X A 12 X A 12 X A 12 X 12 A 12 X A 12 X A 12 X A 12 11 A 11 A 11 A 11 A 11 A 11 A 11 A 11 10 A 10 AP A 10 AP A 10 AP A 10 9 A9 A9 A9 A9 A9 A9 A9 A9 9 A9 A9 A9 A9 A9 A9 A9 8 A8 A8 A8 A8 A8 A8 A8 A8 8 A8 A8 A8 A8 A8 A8 A8 7 A7 A7 A7 A7 A7 A7 A7 A7 7 A7 A7 A7 A7 A7 A7 A7 6 A6 A6 A6 A6 A6 A6 A6 A6 6 A6 A6 A6 A6 A6 A6 A6 5 A5 A5 A5 A5 A5 A5 A5 A5 5 A5 A5 A5 A5 A5 A5 A5 4 A4 A4 A4 A4 A4 A4 A4 A4 4 A4 A4 A4 A4 A4 A4 A4 3 A3 A3 A3 A3 A3 A3 A3 A3 3 A3 A3 A3 A3 A3 A3 A3 2 A2 A2 A2 A2 A2 A2 A2 A2 2 A2 A2 A2 A2 A2 A2 A2 1 A1 A1 A1 A1 A1 A1 A1 A1 1 A1 A1 A1 A1 A1 A1 A1 0 A0 A0 A0 A0 A0 A0 A0 A0 0 A0 A0 A0 A0 A0 A0 A0 A 11 A P 11 A 11 X A 11 X A 11 X A 11 10 A 10 AP A 10 AP A 10 AP A 10 Row Col Row Col Row Col Row 17 16 15 RS X X RS X X RS A 13 X RS X X RS A 13 B2 RS X B2 RS A 13 B2 2.3.5 FBD L0s State The L0s state is not supported in the AMB. 2.4 Reliability, Availability, and Serviceability Refer to Chapter 5, “Reliability, Availability and Serviceability” in the FB DIMM Architecture and Protocol Specification [1] for FBD RAS requirements. 2.4.1 Channel Error Detection and Logging See for details on the error handling. 2.5 2.5.1 Channel Configuration Re-sync and Resample Modes A separate control is available for both the NB and SB FBD links to select between lower latency re-sample and lower jitter re-sync modes for repeating received data. Selection between these two modes is a function of platform design and configuration and should be set by BIOS prior to link initialization The FBDSBCFGNXT.SBRESYNCEN and FBDNBCFGNXT.NBRESYNCEN bits make this selection. Descriptions of these two modes follows. 2.5.1.1 Accumulated Tracking Effects (Re-Sample Option) Each AMB acts as a repeater for the FBD channel. Since the data driven from each DIMM to the next DIMM may experience random or periodic phase shifts, the effect of these phase shifts must be accommodated in the design. Consider a system with three DIMMs daisy-chained together. A phase shift generated in the first DIMM will be seen by the second DIMM but will not be immediately propagated to the third DIMM. Unlike an analog buffer, the phase shift is not automatically driven to subsequent DIMMs since Intel® 6400/6402 Advanced Memory Buffer Datasheet 19 FBD Channel Interface the data driven to the subsequent DIMMs is re-sampled in the AMB to reduce jitter. The lowest latency implementation would use the derived clock to retransmit the outbound signal. The second DIMM will see the phase shift as a slight change in the position of the data eye at its receiver. The clock tracking loop filter in the second DIMM will measure several bit cells and may eventually determine that it should adjust the phase of its derived clock to capture the data closer to the center of the new data eye location. Only when the second DIMM makes its phase change will the effect propagate to the third DIMM. More detail of the data sampling technique may be found in the “High Speed Differential Point-to-Point Link at 1.5V for Fully Buffered DIMM Specification”. 2.5.1.2 Accumulated Tracking Effects (Re-Sync Option) An alternative implementation would place a voltage/thermal (VT) drift compensation buffer between the receiver and the transmitter section of the AMB I/O cell. The drift compensation buffer would re-synchronize the signal with a multiple of the reference clock. This buffer would have to be deep enough to handle the absolute magnitude of delay change of the daisy-chain channel over voltage and temperature. More detail of the data sampling technique may be found in the “High Speed Differential Point-toPoint Link at 1.5V for Fully Buffered DIMM Specification”. 2.5.2 Other Channel Configuration Modes Other channel electrical configuration parameters that should be set up prior to link initialization include • Link frequency (LINKPARNXT.CFREQ) • SB Transmitter drive current (FBDSBCFGNXT.SBTXDRVCUR) • SB Transmitter de-emphasis values (FBDSBCFGNXT.SBTXPREEMP) • NB Transmitter drive current (FBDNBCFGNXT.NBTXDRVCUR) • NB Transmitter de-emphasis values (FBDNBCFGNXT.NBTXPREEMP) The parameters contained in these registers are described more completely in the “High Speed Differential Point-to-Point Link at 1.5V for Fully Buffered DIMM Specification”. Additional channel configuration registers that should be set up prior to link initialization include • First 6 bytes of the SPD parameter registers — SPDPAR01NXT,SPDPAR23NXT,SPDPAR45NXT • FBD Bit Lock Time Out Register (FBDLOCKTO) 2.5.3 Lane to Lane Skew on a Channel The FBD Channel is expected to support a maximum skew of up to 46UI. The deskew buffers on an individual AMB need to be able to support this amount of accumulated skew. The actual skew observed will be a function of the skew introduced by platform layout, DIMM layout, the number of active AMBs in the channel and skew introduced by AMBs. 20 Intel® 6400/6402 Advanced Memory Buffer Datasheet FBD Channel Interface 2.6 Repeater Mode The AMB may also be used as an FBD link repeater to extend distances at which links can operate. This mode can be automatically set by the BFUNC and SA pins. In this mode, the AMB functions in the same way as a regular DIMM with the exception that DRAM commands are not supported. Link behavior is the same as for normal DIMMs • Participates in link initialization like a normal DIMM • Responds to Reads and Writes to AMB configuration registers • Status is returned in response to Sync commands • Link errors are detected and alerts generated SMBus access is the same except for the base Slave address is different than from normal DIMM. Slave address[6:3] = 4’b0011 for Repeaters, instead of Slave address[6:3] == 4’b1011 for normal DIMMs 2.7 Channel Latency The critical elements that AMB contributes to the latency calculation are the chip crossing delays. • Southbound latency contributions — Delay from an input FBD link transaction to commands on the DDR interface and — Pass-thru delay of forwarded Southbound FBD transactions. • Northbound latency contributions — Delay from DDR Read data input on the last DIMM to FBD link transactions and — Pass-thru delay of forwarded Northbound FBD transactions back towards the host. These timing delay values are documented in Chapter 4, “Electrical, Power, and Thermal.” 2.7.1 Command to Data Delay Calculation shows the various components that make up the over all delay through an AMB for a memory command. Intel® 6400/6402 Advanced Memory Buffer Datasheet 21 FBD Channel Interface Figure 2-1. Delays Through an AMB TAMB_Cmd_Delay D SET TDimm_Cmd_Delay D SET Q DDR Command Q SB Frame Clock CLR Q CLR Q DRAM Clock D DDR IO CMD Clock DRAMs D Q Q SET D DRAM Data Q SET D Data DQS Q CLR Q CLR Buffer/FIFO NB Frame Clock TDimm_Data_Delay TAMB_Data_Delay The definition for terms used in the are given below. UI NB: SB: This is the unit interval on the FBD link. This is same as the period of the FBD link bit-rate clock. Northbound Southbound TRead_Latency: DRAM Parameter. TCAS + TAdditive_Latency TAMB_Cmd_Delay This value is very specific to an AMB implementation. This is the time it takes for the command to be transferred from the FBD receiver to the DDR I/O Cluster. This includes any differences between the FBD frame clock and the DDR I/O clock that latches the command into the DDR I/O cluster. This can be different for different DRAM frequencies. This value is very specific to an AMB implementation. This is the minimum time it takes for the data that is returned from the DRAMs to be transferred from the DDR I/O cluster to the FBD I/ O for transmission on the link. This includes any buffering and clocking delays for the data within the chip. This can be different for different DRAM frequencies. This includes the delays for the command through the DDR I/O cluster, differences between DDR I/O CMD Clock and DRAM clock, any routing delays for the clock and command on the TAMB_Data_Delay TDimm_Cmd_Delay 22 Intel® 6400/6402 Advanced Memory Buffer Datasheet Q CLR SET TRead_Latency CLR SET Q Q FBD Channel Interface DIMM and any set-up and hold-times in the AMB and the DRAMs. TDimm_Data_Delay This includes the routing delays for the data and strobes from the DRAM to the AMB, skews between the DRAMs, delays through the DDR I/O cluster and any set-up and hold-times in the AMB and DRAMs. This is equal to (TRead_Latency + TAMB_Cmd_Delay + TDimm_Cmd_Delay + TDimm_Data_Delay + TAMB_Data_Delay). This can be specified with 1UI granularity. This will be different for each DRAM type. It does not include any delays inside the I/O to deskew and frame align the incoming data on the SB side nor does it include the delays inside the NB I/O on the transmit side. TCMD_To_Data The TCAS and TAdditive_Latency are specified in the DRC register (DRC.cl and DRC.al). The CMD2DATANXT register is initialized with a value equal to (TCMD_To_Data - TRead_Latency). This value of CMD2DATANXT is specified in the SPD EEPROM. All AMBs are expected to receive the data from the DRAMs with the calculated value of TCMD_To_Data. All AMBs power up with a default value of 5 for TCMD_To_Data. This can be done either by setting the default values of DRC.CL and DRC.AL or by setting the default value of the CMD2DATACUR.FRMS to be 5. The AMBs must be able to return status and configuration register reads with this default timing. This will enable the BIOS to initialize the proper values from SPD. The following simplified timing diagram illustrates how the last AMB uses the values specified in DRC.CL, DRC.AL, CMD2DATANXT.DLYFRMS and CMD2DATANXT.DLYFRAC. Figure 2-2. Command to Data Delay Timing In Figure 2-2, it is assumed that there are no routing delays on the DIMM itself. The command takes 10UI to get from SB FBD to the DDR I/O (TAMB_Cmd_Delay). This includes time it takes to validate CRC of the frame and to decode the command. It is assumed DDR_IO_Cmd_Clk shown in is delayed from the SB_Frame_Clk by 10 UI. The Intel® 6400/6402 Advanced Memory Buffer Datasheet 23 FBD Channel Interface DRAM SCLK is placed at the center of the command window which adds an additional 6UI of delay. The DRAMs are programmed with a TRead_Latency of 4. The DQS strobes are centered when they get to the AMB (3UI delay) and the data takes an additional 10 UI to propagate from the DDR I/O to the NB FBD I/O (including setup time at NB FBD and CRC generation) before it can be clocked into the NB FBD for transmission. The total delay without including the DRAM access time in this case is (10 + 6 + 3 + 10UI) 29UI. The CMD2DATANXT.DLYFRMS will be programmed with a value 2 and the CMD2DATANXT.DLYFRAC with 5UI. If the AMB supports only a 2UI granularity, then the values should be 2 frames and 6UI respectively. If an AMB does not support sub-frame delays, it is expected that the value in SPD will be round up the to the nearest frame. Any additional delays caused by rounding up should be supported by additional buffering in the DDR I/O. The above figure shows the last arriving data from the DDR. It is expected that any data arriving earlier than this, due to differences in routing, and so forth, is buffered up in some way inside the DDR I/O. The expectation is that all AMBs (last and intermediate) unload the data from the DDR I/O with the timing specified by the TCMD_To_DATA. The Last AMB is expected to be able send data on the NB links with no additional delay added, if C2DINCRCUR.INCRDLY is 0. Any additional delay needed due to the value programmed in C2DINCRCUR.INCRDLY register in the last AMB or to delay the data in intermediate AMB before the merge, is handled by FIFOs in the AMB core. In the above figure, it is assumed that the AMB can place the clocks in position shown above. If this is not the case, then additional delays due to non-optimal placement of the clocks should be taken into account to calculate the total delay to be programmed into the SPD. § 24 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR Interface 3 3.1 DDR Interface Intel 6400/6402 Advanced Memory Buffer (AMB) DDR Interface Overview The DDR interface on the AMB consists of: • A command decoder. • A FIFO write buffer to hold the write data before it is written to the DDR channel. The write FIFO buffer has 36 entries of 72 bits (36 x 72b). A maximum of 35 entries can be used to store DDR bursts. Write data targeted for other AMB parts on the channel will use three of the 35 entries until the target AMB is known. The write FIFO buffer fills at half of the DDR data rate, and empties at the DDR data rate. The write FIFO buffer must support an invalidate write FIFO command (FBD Soft Reset command). • A FIFO read buffer to hold the read data so that each DIMM returns data with the same latency as the southernmost DIMM in the chain. Latency is measured in increments of core clock periods. The core clock runs at the DDR command clock rate (half the data rate frequency). The latency through the FIFO read buffer on the southernmost DIMM is expected to be zero. • A DDR cluster which serves as a DIMM buffer by registering outbound commands and data at output flops. The cluster also captures and levelizes incoming read data. • A reset FSM which puts the DIMM in self-refresh when reset is asserted, and exits self-refresh when reset is deasserted and southbound frame training is complete. • A calibration FSM that automatically sets the timing for DQS receiver enable and DQS delay or equivalent DDR timing control mechanism. The DQS receiver enable calibration uses a series of DRAM read and write operations to find the center of the read DQS preamble. During normal operation the DQS receivers will be enabled at the preamble center to ensure that the DQS signal is received correctly into the AMB Component’s DDR I/O circuits. The DQS delay calibration uses a series of reads and writes to align the read DQS waveform rising and falling edges to the center of the DQ data eye. • A configuration register set to allow software to issue DRAM power up and DRAM MRS/EMRS commands, as well as a self-refresh entry command. These registers are accessible through FBD channel commands and the SMBUS interface. • “Burst Write Interrupt” is not supported. 3.2 Data Mapping See the protocol chapter of the FB DIMM Architecture and Protocol Specification for the mapping between data in DDR DRAM devices and data in FBD frame formats for 4-bit and 8-bit devices. Intel® 6400/6402 Advanced Memory Buffer Datasheet 25 DDR Interface 3.3 Command / Address Outputs Two sets of DRAM command and address output pins are provided for loading and timing considerations. Each set drives the same DRAM commands, but the two address busses are inverted from each other in order to reduce power consumption and heat produced on the DIMM. The command and address output pin behavior is detailed below: 1. Minimum address toggling. The address associated with the last command issued on the DRAM bus is retained during DRAM NOP/Deselect commands. The address and bank bits do not revert to all 1’s (or all 0’s) when the command bus is idle. 2. Balanced bank and address busses. With some exceptions, the bank and address busses on the two bus copies are inverted from each other. This minimizes the current load on the VTT supply regulator because the balanced address bus sinks as much current as it sources. There are exceptions to the inversion behavior to allow for commands that use one or more address bits to control DRAM functionality. Balancing can also be disabled by setting the DRC.BALDIS register field. Balancing Exceptions: a. b. c. Address bit A10 is not balanced during all read, write, and precharge commands. No address or bank bits are balanced during any MRS and EMRS commands. Column address A0 is not balanced when the DRC.SEQADD bit is set. As with A10, A0 is only not balanced during read, write, and precharge commands. This mode is intended to work with DRAMs in sequential address mode. No address or bank bits are balanced during any command when the DRC.BALDIS register field is set. d. 3. Balanced idle command bus. When the command bus is idle, a deselect command is issued with all chip selects high and all RAS/CAS/WE signals driven low on both command/address copies. 4. Command/Address output control with CKE. All command and address pin outputs, except for ODT, CKE, and CLK, will float one DRAM clock cycle after both CKE pins transition from high to low. The command/address pins will be driven to valid signal levels on the same cycle that either CKE pin is driven from low to high. 5. Output control during link reset. When the AMB core logic is in reset, CKE and ODT will be driven low, and CLK will run at normal levels and frequency. The remaining command/address pins will float during reset. 6. Command/Address output control in S3 mode. When the AMB core logic is in S3 power mode, all command/address outputs, including CKE, ODT, CLK, and all other command/address pins, will be driven low. 7. CSR output control of command/address. All command/address pin outputs will float when the appropriate DRC bits are set. Setting the DRC.CADIS field will float the RAS, CAS, WE, Bank, and Address pins. DRC.CSDIS controls the chip select pins. DRC.ODTDIS, DRC.CKEDIS, and DRC.CLKDIS float the ODT, CKE, and clock pins respectively. 26 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR Interface 3.3.1 CKE Output Control The are six different functions that affect the state of the CKE outputs during normal operation: 1. DRC.CKEFRCLOW CSR. When set, this bit forces both CKE outputs low. No other CKE control function overrides this CSR. This allows firmware to prevent hardware from issuing all DRAM commands. This could be used by firmware to keep the DRAM bus idle throughout a fast reset sequence that occurs before the DRAM initialization command sequence has been initiated. 2. Self-Refresh FSM. When entering a fast reset sequence, a hardware FSM takes control of the DDR command bus, including the CKE outputs, in order to issue a series of commands to put the DRAM’s into self-refresh. This FSM is overridden by the DRC.CKEFRCLOW CSR. 3. Automatic self-refresh exit with link training. When a T0 link training sequence is complete, both CKE outputs will be automatically asserted high in order to exit selfrefresh. This control is inhibited by setting the DSREFTC.DISSREXIT bit. The DRC.CKEFRCLOW also overrides this automatic self-refresh exit function. 4. Self-Refresh entry DCALCSR command. The DCALCSR register can be programmed to launch an FSM that issues a single self-refresh entry command. The DRC.CKEFRCLOW bit overrides this function. 5. Channel commands. The host can directly control the CKE output state through channel command protocol. The DRC.CKEFRCLOW bit overrides this function. 6. DRC CKE0 and CKE1 CSR bits. These CKE bits in the DRC are both control and status bits for the CKE outputs. Software can write these bits to directly control the CKE outputs. These bits reflect the state of the CKE outputs one cycle after the output state is changed by one of the other control functions. The DRC.CKEFRCLOW bit overrides this function. Channel commands that change the state of the same CKE output must be separated by at least two DRAM clock cycles. Configuration writes and channel commands that affect the same CKE output must not occur within two cycles of each other to avoid unstable CKE behavior. 3.4 DQS I/O and DM Outputs The AMB sends and receives source synchronous differential strobes (DQS) to transfer data (DQ/CB) during write and read DRAM transactions. DQS9 through DQS17 also support the data mask (DM) function in x8 mode. Setting the MTR.WIDTH configuration register enables x8 mode. When driving DM, the timing of the transition from floating, to driving, and back to floating is unchanged, but DQS[17:9] do not toggle and instead drive a constant level. DQSP[17:9] drive low and DQSN[17:9] drive high. In x8 mode DQS[17:9] are not used to capture read data. The table below lists which DQS signals are associated with which DQ/CB pins in x8 and x4 mode. Table 3-1. DQS Association with DQ/CB Pins in x8 and x4 Mode x4 Mode: MTR.WIDTH=0 DQS Pin Output Function Write DQS Write DQS Write DQS Input/Output Data Mapping CB[7:4] CB[3:0] DQ[63:60] DM Write DQS DM x8 Mode: MTR.WIDTH=1 Output Function Input/Output Data Mapping N/A CB[7:0] N/A DQS17 DQS8 DQS16 Intel® 6400/6402 Advanced Memory Buffer Datasheet 27 DDR Interface Table 3-1. DQS Association with DQ/CB Pins in x8 and x4 Mode x4 Mode: MTR.WIDTH=0 DQS Pin Output Function Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Write DQS Input/Output Data Mapping DQ[59:56] DQ[55:52] DQ[51:48] DQ[47:44] DQ[43:40] DQ[39:36] DQ[35:32] DQ[31:28] DQ[27:24] DQ[23:20] DQ[19:16] DQ[15:12] DQ[11:8] DQ[7:4] DQ[3:0] x8 Mode: MTR.WIDTH=1 Output Function Write DQS DM Write DQS DM Write DQS DM Write DQS DM Write DQS DM Write DQS DM Write DQS DM Write DQS Input/Output Data Mapping DQ[63:56] N/A DQ[55:48] N/A DQ[47:40] N/A DQ[39:32] N/A DQ[31:24] N/A DQ[23:16] N/A DQ[15:8] N/A DQ[7:0] DQS7 DQS15 DQS6 DQS14 DQS5 DQS13 DQS4 DQS12 DQS3 DQS11 DQS2 DQS10 DQS1 DQS9 DQS0 3.5 Refresh The AMB is required to manage DRAM refresh during channel resets and when the auto-refresh function is enabled. During channel resets, the Self-Refresh FSM takes control of the DDR command bus and places the DRAMs in self-refresh mode. The Auto-Refresh FSM generates auto-refresh commands when the DAREFTC.AREFEN bit is set. The Self-Refresh FSM will override and take control away from the Auto-Refresh FSM when a reset event occurs. A self-refresh entry command can also be generated by programming the DCALCSR register. The FSM that controls this function will be described in the DRAM initialization and (E)MRS command section. 28 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR Interface 3.5.1 Self-Refresh During Channel Reset The Self-Refresh FSM is launched by a sync train error on the link, or when an electrical idle condition is detected on the link. The Self-Refresh FSM will take the DRAM’s from an unknown state and put them into self-refresh mode. The AMB does not track the DRAM state during normal operation, and so has a single process for getting from any DRAM state starting point to the self-refresh state. When launched, the Self-Refresh FSM will execute the following steps. Each step below is one of the states of the FSM. Setting the DRC.CKEFRCLOW bit will prevent the command sequence described below from being issued on the DDR bus since it will force the CKE outputs low. 1. Clear the DAREFTC.AREFEN CSR to stop the AMB auto-refresh engine if enabled. 2. Block all DRAM commands, except those initiated by the self-refresh FSM. 3. Wait until any in-process read or write commands complete, with a minimum wait time of DSREFTC.TCKE, the DRAM “Minimum CKE pulse width time” specification. In-process reads/writes must complete to ensure that the DRAM ODT control outputs are driven low. The minimum time allows for the case where self-refresh entry or power-down entry was executed just before the channel reset. 4. Assert both CKE output pins by setting the DRC.CKE0/1 CSR fields. This will have no effect on the DRAM’s if the CKE pins were already asserted. 5. Wait DSREFTC.TXSNR, the DRAM’s “Exit self-refresh to a non-read command” specification, to allow any in-process DRAM command to complete. This allows time to complete any command that may have been issued just before the channel reset event, such as an auto-refresh, as well as allows for self-refresh exit that may have been initiated when the self-refresh FSM asserted the CKE pins high. 6. Issue a “precharge all” command to both ranks. This guarantees that the DRAM’s will be in an “idle” state. 7. Wait as required by DSREFTC.TRP, the DRAM “Precharge time.” 8. Issue an auto-refresh command to both ranks. This meets the DRAM requirement that at least one auto-refresh command is issued between any self-refresh exit to self-refresh entry transition. The AMB staggers the auto-refresh commands to the two ranks by the DSRETC.DRARTIM value in order to avoid stressing the system power supply with too many DRAM’s refreshing at the same time. 9. Wait as required by DAREFTC.TRFC, the DRAM “Refresh to active/refresh command time.” 10. Issue a self-refresh entry command to both ranks. The AMB staggers the selfrefresh entry commands to the two ranks by the DSRETC.DRSRENT value to avoid stressing the system power supply. When the channel comes out of “fast reset” (exiting the FBD link disable state), the AMB will automatically issue a self-refresh exit command to both ranks after the FBD Link Testing State is reached and the AMB core clock is stable. Note that this does not apply when the DISSREXIT bit is set as it should be when the AMB is powering up or when exiting S3 mode. The DRC.CKEFRCLOW CSR also overrides the automatic exit command by forcing the CKE outputs to stay low. 3.5.2 Automatic Refresh The AMB has an Auto-Refresh FSM for issuing auto-refresh commands to the DRAM’s on regular intervals. This can be enabled when the DRAM bus is otherwise idle, but not during any other mode that generates DRAM commands, including DRAM power up and Intel® 6400/6402 Advanced Memory Buffer Datasheet 29 DDR Interface initialization, DDR I/O calibration, and normal operation where the FBD channel issues DRAM commands. The DAREFTC CSR controls the refresh interval and period, and includes an enable bit to turn auto-refresh command generation on and off. The autorefresh FSM may be integrated or separate from the MemBIST functions in hardware, but the auto-refresh function runs independently of the MemBIST state. Multiple MemBIST tests can be started and completed with the auto-refresh FSM running during, in between, and after all MemBIST tests complete. The Auto-Refresh FSM generates auto-refresh command requests to an arbiter in hardware at regularly spaced intervals defined by the DAREFTC.TREFI CSR. For a single rank DIMM the command spacing is equal to TREFI cycles. For dual rank DIMMs the command spacing is TREFI/2, alternating between the two ranks so that each rank receives an auto-refresh command every TREFI cycles on average. Hardware abitrates between the Self-Refresh FSM command requests and commands generated by the MemBIST function. When MemBIST is not running, the auto-refresh command is immediately issued on the DDR bus. When MemBIST is running, an auto-refresh request is posted until the MemBIST FSM can interrupt its command sequence, precharge all open banks on all ranks, and all DRAM timing requirements are met so that an auto-refresh command can be accepted. The MemBIST FSM resumes its command sequence TRFC later. The MemBIST FSM must interrupt its operation within TREFI/2 in order to avoid causing an auto-refresh command to be dropped by the arbiter. 3.6 Back to Back Turnaround Time The host controller is required to observe a turnaround time on the DRAM data pins within a DIMM when switching between read and write cycles, and when switching from reads from one rank vs. the other rank on the DIMM. The nominal turnaround time is one clock for each parameter, which is the minimum time required to prevent a collision of the postamble of the first transaction and preamble of the second transaction. Additional clocks may be required by the DIMM, especially at higher speeds. The three timing parameters are: • Read to write turnaround time. The number of additional DRAM clocks in which the DRAM data bus must be idle between a read from either rank and a write cycle to either rank. • Write to read turnaround time. The number of additional DRAM clocks in which the DRAM data bus must be idle between a write to one rank and a read from either rank. The write to read turnaround time to the same rank will generally dominated by the tWTR specification, which must also be observed. • Read to read turnaround time. The number of additional DRAM clocks in which the DRAM data bus must be idle between a read from one rank and a read from the opposite rank. These parameters are dependent on the AMB design and the DIMM PC board layout. The parameters are stored in the SPD. Each parameter is a 2 bit field allowing 0 to 3 additional clocks of turnaround time. See the FB4300/5300/6400 DDR2 Fully Buffered DIMM Design Specification for additional details. Figure 3-1 shows the nominal turnaround times, with no additional clocks. Note that the DQS preamble and postamble may merge slightly when the first transaction is at worst case timings and the second transaction is at best case timings. 30 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR Interface Figure 3-1. Nominal Turnaround Time Timing Diagram Clock DQS DQ Preamble A Postamble A Preamble B Data A-0 Data A-1 Data A-2 Data A-3 Data B-0 Data B-1 Data B-2 Data B-3 Read to Read turnaround (nominal) Clock DQS DQ Preamble R (read) Data R-0 Data R-1 Data R-2 Postamble R Preamble W (write) Data W-0 Data W-1 Data W-2 Data W-3 Data R-3 Read to Write turnaround (nominal) Clock DQS DQ Preamble W (write) Data W-0 Data W-1 Data W-2 Postamble W Preamble R (read) Data R-0 Data R-1 Data R-2 Postamble R Data W-3 Data R-3 Write to Read turnaround (nominal) 3.7 S3 State Background Description S3 is a platform power down state where DRAM memory contents are preserved while the rest of the platform powers down. This state is described more formally in the Advanced Configuration and Power Interface Specification. It is much like the Standby mode on mobile computers. Functionally, the requirement for an AMB is that after a sequence in which: • AMBS3 Recovery state is stored by the host, • DRAMs are put into Self-Refresh, • RESET# is asserted, • Vcc (1.5 V), Vtt (0.9 V) and VddSPD(3.3 V) are powered down, The contents of memory on the DIMM are preserved until S3 Recovery. Recovery requires that the memory on the DIMM be restored without losing data integrity. The recovery sequence is much the same as an initial power on with the exceptions of: • Vdd is already powered on • DDR interface state is restored from stored register values (since no calibration which might compromise memory content is allowed) To minimize DIMM current, VCC should be powered up during VTT transitions. The AMB determines that it is in the S3 mode by checking that VDD (1.8 V) is powered up and that VCC (1.5 V) is powered off. When in S3 the AMB drives all command/address outputs (including CKE, ODT, and CLK) to a low. This keeps the DRAM in auto-refresh and helps prevent DRAM data corruption. When coming out of the S3 mode, if the system brings VTT (0.9 V) up before VCC the AMB will drive low into the VTT pull-up circuitry. This causes significant current (approximately two times average but still normal) to flow from VTT into the AMB until VCC is powered up and the AMB comes out of S3. Intel® 6400/6402 Advanced Memory Buffer Datasheet 31 DDR Interface 3.7.1 S3 Recovery Configuration Registers The following CSRs should be stored in non-volatile memory before entering S3 mode and restored before normal DRAM transactions begin. • DRC • MTR • DSREFTC • DAREFTC • DDR2ODTC • CMD2DATANXT • S3RESTORE[15:0] • PERSBYTE[13:0] - SPD Personality Bytes 3.8 DDR Calibration The following sections describe these DDR calibration and initialization features: • DRAM initialization and (E)MRS command CSR’s and FSM • DQS failure CSR • DQS receive enable calibration • DQS calibration 3.8.1 DRAM Initialization and (E)MRS FSM The AMB provides a set of CSR’s and an FSM that allow BIOS to manage DRAM power up initialization and set DRAM mode register bits. All commands needed for DRAM initialization can be generated, including precharge, refresh, mode register set (MRS), and extended mode register set EMRS commands. A self-refresh command can also be generated, although this is not required for initialization. The initialization/(E)MRS FSM only controls the issuing of single commands, and does not automatically initialize the DRAM. It is the responsibility of software to control the command sequence to correctly initialize the DRAM. The set of CSR’s include the DCALCSR and DCALADDR registers. The fields of these CSR’s are described in detail in the configuration register chapter. The DCALCSR is used to select the command to be issued, which ranks to select, start the FSM that issues the command, and provide completion status. The DCALADDR sets the bank and address issued to the DRAM, and therefore defines the type of (E)MRS to be issued, including limited OCD commands. The DCALADDR can also be used to configure a precharge command as a “precharge all” command. DCALADDR[31:16] defines the DDR address bus during these commands, and DCALADDR[2:0] defines the ddr bank address bus. The FSM that controls this function can have as few as three states: idle, issue command, and clear start bit. When the DCALCSR.START bit is set, and the DCALCSR.OPCODE bits select one of the command options, the FSM transitions from idle to the “issue command” state. After the command is issued, the FSM clears the DCALCSR.START bit and returns to the idle state. A more elaborate FSM may also be implemented. Firmware is required to control the minimum command spacing to meet all DRAM timing requirements. After setting the start bit, firmware should poll the 32 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR Interface DCALCSR until the start bit is cleared. After the start bit is cleared, firmware waits a period of time based on DRAM command timing specifications before issuing a new command through the DCALCSR. 3.8.1.1 OCD EMRS Commands FB DIMM DRAM timing is set up to work with OCD default calibration. Using the DCALCSR and DCALADDR registers, EMRS OCD default and OCD exit commands can be sent to the DRAMs. Sending OCD EMRS drive(0), drive(1), or adjust DRAM commands may have implementation dependent outcomes and should not be used in normal operation. 3.8.1.2 MRS Command Example The following example shows how to send out an MRS command: 1. Write a value of 0x02320000 to the DCALADDR csr. This will configure the address/ bank bus for an MRS command with burst length 4, CAS latency 3, and write recovery 2. 2. Write a value of 0x80000003 to the DCALCSR. This selects the (E)MRS command mode and initiates the FSM that will issue the command. 3. Poll the DCALCSR until bit 31 is cleared to zero by hardware. This indicates that the FSM has completed the selected operation. 3.8.2 DQS Failure CSR The DQSFAIL CSR allows the AMB to calibrate properly even when one or more DQS signals are missing, either through PCB or component failure. DQSFAIL is a 36 bit register, one bit for each DQS pair of each rank. Software can set this CSR to force any DQS signal to be excluded from the automatic DDR bus calibration. Hardware will also detect missing DQS signals and automatically exclude them from calibration. Intel® 6400/6402 Advanced Memory Buffer Datasheet 33 DDR Interface 3.8.3 Automatic DDR Bus Calibration The AMB has two automatic DDR bus calibration functions that must be executed before read data can be captured reliably. These functions issue a series of write and read transactions on the DRAM bus, analyze the read data captured, and program a set of calibration results configuration registers. During subsequent operations, these configuration registers control the DDR I/O circuits and ensure proper data capture. DIMM memory contents are not preserved during calibration. Calibration can take up to several ms to complete. The following steps run the calibration: 1. Program the DCALCSR to 0x8000000C. This selects and initiates the first of two calibrations. 2. Poll the DCALCSR until bit 31 is cleared to zero by hardware. 3. Program the DCALCSR to 0x80000005. This selects/initiates the second calibration. 4. Poll the DCALCSR until bit 31 is cleared to zero by hardware. 3.8.4 Receive Enable Calibration The DQS input receiver needs to be disabled when the DDR bus is floating (tri-stated), for example, between the read and write data transfers. Otherwise, the floating strobe would cause spurious data to be written into the read data FIFO. Also, the DQS input receiver needs to be disabled during a write so that the write data strobes do not cause unwanted data or check-bits to be written into the read data FIFO. During a read, the DRAM’s initially drive the DQS signals low for a full cycle. This is the preamble. After the preamble, the DQS signals are toggled twice per cycle, for every cycle there is a data transfer, which is determined by the configured burst length and the number of back-to-back read commands that were issued to the selected rank. After the last DQS falling edge, the DQS signal is driven low for a half cycle. This is the post-amble. After the post-amble the DQS signals are tri-stated. The AMB automatically finds the end of the preamble of each of the 18 DQS pairs on the DDR bus. That is, it finds the location of the first waveform transition that defines the end of the preamble of each DQS pair. Once this is complete, the AMB calculates the location of the center of the preambles, and stores this information for use during read transactions. Receiver calibration is initiated by setting the DCALCSR.START CSR. Hardware clears this bit when the calibration is complete. The calibration method modifies the data contents of the DIMM. 3.8.5 DQS Delay Calibration The DQS Delay calibration adjusts the AMB Component’s on-chip delay circuits that align DQS signals to the center of their associated DQ/CB data eyes at the capture flops in the DDR I/O cluster. This maximizes the DQ/CB setup and hold time at these flops, which capture source synchronous data from the DDR data bus. DQS delay calibration is initiated by setting the DCALCSR.START CSR. Hardware clears this bit when the calibration is complete. The calibration method modifies the data contents of the DIMM. The calibration is accomplished by issuing a series of write and read transactions, and comparing expected to captured data 34 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR Interface 3.9 DIMM Organization The AMB supports DIMMs with 1 or 2 independent ranks (chip-selects). Each rank consists of DDR SDRAM devices or DDR SDRAM devices. Dual rank DIMMs consist of DDR SDRAM devices or DDR SDRAM devices. The AMB DDR I/O circuits provide three main functions: an outbound command and data path, an inbound data path, and analog compensation. Analog compensation is provided, along with configuration registers, to control and match the output impedance and slew rate of the off-chip drivers and on on-die termination. The main configuration registers are the leg override (for impedance) and slew override fields of the spdpar67cur and spdpar1011cur CSR’s. The analog compensation circuits match driver characteristics to a ratio of an externally provided resistance. The CSR’s control the ratio. The outbound data path is relatively simple compared to the inbound. On the outbound command, the I/O circuits provide a minimum latency, registered path to transfer commands from the core to the DDR command bus as quickly as possible, but with tight timing control. For the DQ, DQS, and DRAM clock outputs, the I/O provides registered paths to transfer these signals to the DDR bus with the proper phase relationship to the command. The phase of the DRAM clocks (along with the DQS and DQ phase) relative to the command can be controlled by the ddr1xphsel and ca2xphsel fields of the spdpar45cur and spdpar67cur CSR’s. The inbound data path includes calibrated receiver enable circuits, calibrated DQS delay lines, and an eight entry deep levelization FIFO. Calibration is controlled by the core at power up and can take several ms to execute. Calibration involves a series of read and write operations to the DRAM. Receiver enable is calibrated on a per byte basis. DQS delay is calibrated at a coarse level on a word basis, with a fine calibration adjustment for each nibble. The fine adjustment can be dynamic so that a different calibration value can be sent from the core for each nibble depending on which rank is being accessed. The core provides a read pointer to access the contents of the FIFO. The IO I/O circuits manage the FIFO write pointer automatically, with timing based on both the receiver enable and DQS delay calibrations. § Intel® 6400/6402 Advanced Memory Buffer Datasheet 35 DDR Interface 36 Intel® 6400/6402 Advanced Memory Buffer Datasheet Electrical, Power, and Thermal 4 Electrical, Power, and Thermal This chapter contains a description of the Intel 6400/6402 Advanced Memory Buffer (AMB)’s electrical DC parameters, timing parameters, power considerations, and thermal considerations. 4.1 4.1.1 Electrical DC Parameters Absolute Maximum Ratings Table 4-1 contains absolute maximum ratings over operating free-air temperature range (see Note 1). Table 4-1. Absolute Maximum Ratings Over Operating Free-Air Temperature Range (See Note 1) Parameter Supply voltage DRAM Interface Voltage on any DDR2 interface pin relative to Vss (See Notes 2 and 3) Input clamp current Output clamp current Continuous output current Continuous current through each VDD or GND Supply voltage for Core and High Speed Interface Storage temperature range –0.3 –55 Min –0.5 –0.5 Max +2.3 +2.3 +30 +30 +30 +100 +1.75 +100 Unit V V mA mA mA mA V °C Symbol VDD VIN (DDR2), VOUT (DDR2) IINK (VIN < 0 or VIN > VDD) IOUTK (VOUT < 0 or VOUT > VDD) IOUT (VOUT = 0 to VDD) N/A VCC Tstg Notes: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.This value is limited to 2.3 V maximum. 4.1.2 Operating DC Parameters Table 4-2 contains the electrical DC parameters for the AMB part for normal operation. Table 4-2. AMB Operating DC Electrical Parameters Parameter VCC link / core VDD VDDSPD AMB Mode Units Volts Volts Volts Min 1.455 1.7 3.0 Typ 1.5 1.8 3.3 Max 1.575 1.9 3.6 Note: There will also be a VTT termination supply at VDDR/2 available on the DIMM but does not connect to the AMB. Intel® 6400/6402 Advanced Memory Buffer Datasheet 37 Electrical, Power, and Thermal 4.1.3 AMB Power Specifications Table 4-3 contains the AMB power specifications related to parameters stored in the SPD for the AMB . Table 4-3. Power Values for x8 DIMMS (Sheet 1 of 3) 533 MHz 667 MHz Thermal Design 2.4 0.6 Max Current 2.6 0.7 Units A A A Notes Symbol Idd_Idle_0 Conditions Idle Current, single or last DIMM L0 state, idle (0 BW) Primary channel enabled, Secondary Channel Disabled CKE high. Command and address lines stable. DRAM clock active. Power Supply @1.5 V @1.8 V @3.3 V Thermal Design 2.1 0.6 Max Current 2.2 0.7 Idd_Idle_0 Total Power Idd_Idle_1 Idle Current, first DIMM L0 state, idle (0 BW) Primary and Secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. @1.5 V @1.8 V @3.3 V 3.5 2.7 0.6 3.0 0.7 4.0 3.1 0.6 3.4 0.7 W A A A Idd_Idle_1 Total Power Idd_TDP_0 (for AMB spec, Not in SPD) Active Power, TDP BW, Single or Last DIMM L0 state TDP Channel BW = 2.0GB/s@533; 2.4GB/ s@667; DIMM BW = 2.0GB/ s@533; 2.4GB/s@667; 67% read, 33% write. Primary channel Enabled Secondary channel Disabled CKE high. Command and Address @1.5 V @1.8 V @3.3 V 4.6 2.4 1.1 2.6 1.3 5.1 2.8 1.2 3.0 1.3 W A A A Idd_TDP_0 Total Power Idd_TDP_1 (for AMB spec, Not in SPD) Active Power, TDP BW, First DIMM L0 state TDP Channel BW = 2.0GB/s@533; 2.4GB/ s@667; DIMM BW =2/3 Channel BW = 1.3GB/s@533; 1.6GB/s@667; 67% read, 33% write. Primary channel Enabled Secondary channel Enabled CKE high. Command and Ad @1.5 V @1.8 V @3.3 V 5.2 3.0 0.9 3.3 1.0 5.8 3.5 0.9 3.8 1.0 W A A A 38 Intel® 6400/6402 Advanced Memory Buffer Datasheet Electrical, Power, and Thermal Table 4-3. Power Values for x8 DIMMS (Sheet 2 of 3) 533 MHz 667 MHz Thermal Design 6.4 3.4 1.3 3.6 1.2 3.9 1.3 Max Current Units W A A A Notes Symbol Idd_TDP_1 Total Power Idd_Active_1 Conditions Power Supply Thermal Design 5.8 Max Current Active Power L0 state. 50% DRAM BW, 67% read, 33% write. Primary and Secondary channels enabled. DRAM clock active, CKE high. @1.5 V @1.8 V @3.3 V 3.1 1.2 Idd_Active_1 Total Power Idd_Active_2 Active Power, data pass through L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. @1.5 V @1.8 V @3.3 V 6.4 2.9 0.6 3.2 0.7 7.1 3.3 0.6 3.7 0.7 W A A A Idd_Active_2 Total Power Idd_Training (for AMB spec, Not in SPD) Training Primary and Secondary channels enabled. 100% toggle on all channel lanes DRAMs idle. 0 BW. CKE high, Command and address lines stable. DRAM clock active. @1.5 V @1.8 V @3.3 V 5.0 3.5 0.7 5.6 4.0 0.7 W A A A Idd_Training Total Power Idd_IBIST (for AMB spec, Not in SPD) IBIST Over all IBIST modes DRAM Idle (0 BW) Primary channel Enabled Secondary channel Enabled CKE high. Command and Address lines stable DRAM clock active @1.5 V @1.8 V @3.3 V 3.8 0.7 4.5 0.7 W A A A Idd_IBIST Total Power W Intel® 6400/6402 Advanced Memory Buffer Datasheet 39 Electrical, Power, and Thermal Table 4-3. Power Values for x8 DIMMS (Sheet 3 of 3) 533 MHz 667 MHz Thermal Design Max Current 3.8 2.1 Units A A A Notes Symbol Idd_MemBIST (for AMB spec, Not in SPD) Conditions MemBIST Over all MemBIST modes >50% DRAM BW (as dictated by the AMB) Primary channel Enabled Secondary channel Enabled CKE high. Command and Address lines stable DRAM clock active Power Supply @1.5 V @1.8 V @3.3 V Thermal Design Max Current 3.3 2.1 Idd_MemBIST Total Power Idd_EI (for AMB spec, Not in SPD) Electrical Idle DRAM Idle (0 BW) Primary channel Disabled Secondary channel Disabled CKE low. Command and Address lines Floated DRAM clock active, ODT and CKE driven low @1.5 V @1.8 V @3.3 V 2.0 0.2 2.5 0.2 W A A A Idd_EI Total Power IDD_S3 S3 Current VDD = 1.9V VCC = 0V VTT = 0V Across process variations Across the operating TCASE temp range DIMM types, R/C A, B, C, D, E, H & J VDD (1.8V) 75 75 W mA 40 Intel® 6400/6402 Advanced Memory Buffer Datasheet Electrical, Power, and Thermal Table 4-4 contains the AMB Power Specification Parameters for the Advanced Memory Buffer part in normal mode. Table 4-4. Power Values for x4 DIMMs (Sheet 1 of 3) 533 MHz Symbol Idd_Idle_0 Conditions Idle Current, single or last DIMM L0 state, idle (0 BW) Primary channel enabled, Secondary Channel Disabled CKE high. Command and address lines stable. DRAM clock active. Power Supply @1.5 V @1.8 V @3.3 V Thermal Design 2.1 0.9 Max Current 2.2 0.9 667 MHz Thermal Design 2.4 0.9 Max Current 2.6 0.9 Units A A A Idd_Idle_0 Total Power Idd_Idle_1 Idle Current, first DIMM L0 state, idle (0 BW) Primary and Secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. @1.5 V @1.8 V @3.3 V 3.9 2.7 0.9 3.0 0.9 4.4 3.1 0.9 3.4 0.9 W A A A Idd_Idle_1 Total Power Idd_TDP_0 (for AMB spec, Not in SPD) Active Power, TDP BW, Single or Last DIMM L0 state TDP Channel BW = 2.0GB/ s@533; 2.4GB/s@667; DIMM BW = 2.0GB/s@533; 2.4GB/s@667; 67% read, 33% write. Primary channel Enabled Secondary channel Disabled CKE high. Command and Address @1.5 V @1.8 V @3.3 V 4.9 2.4 1.5 2.6 1.6 5.5 2.8 1.5 3.0 1.6 W A A A Idd_TDP_0 Total Power Idd_TDP_1 (for AMB spec, Not in SPD) Active Power, TDP BW, First DIMM L0 state TDP Channel BW = 2.0GB/ s@533; 2.4GB/s@667; DIMM BW =2/3 Channel BW = 1.3GB/s@533; 1.6GB/s@667; 67% read, 33% write. Primary channel Enabled Secondary channel Enabled CKE high. Command and Ad @1.5 V @1.8 V @3.3 V 5.9 3.0 1.3 3.3 1.4 6.5 3.5 1.3 3.8 1.4 W A A A Idd_TDP_1 Total Power Idd_Active_ 1 Active Power L0 state. 50% DRAM BW, 67% read, 33% write. Primary and Secondary channels enabled. DRAM clock active, CKE high. @1.5 V @1.8 V @3.3 V 6.3 3.1 1.6 3.4 1.7 6.9 3.6 1.6 3.9 1.7 W A A A Idd_Active_1 Total Power 6.9 7.6 W Intel® 6400/6402 Advanced Memory Buffer Datasheet 41 Electrical, Power, and Thermal Table 4-4. Power Values for x4 DIMMs (Sheet 2 of 3) 533 MHz Symbol Idd_Active_ 2 Conditions Active Power, data pass through L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. Power Supply @1.5 V @1.8 V @3.3 V Thermal Design 2.9 0.9 Max Current 3.2 0.9 667 MHz Thermal Design 3.3 0.9 Max Current 3.7 0.9 Units A A A Idd_Active_2 Total Power Idd_Training (for AMB spec, Not in SPD) Training Primary and Secondary channels enabled. 100% toggle on all channel lanes DRAMs idle. 0 BW. CKE high, Command and address lines stable. DRAM clock active. @1.5 V @1.8 V @3.3 V 5.5 3.5 0.9 6.1 4.0 0.9 W A A A Idd_Training Total Power Idd_IBIST (for AMB spec, Not in SPD) IBIST Over all IBIST modes DRAM Idle (0 BW) Primary channel Enabled Secondary channel Enabled CKE high. Command and Address lines stable DRAM clock active @1.5 V @1.8 V @3.3 V 3.8 0.9 4.5 0.9 W A A A Idd_IBIST Total Power Idd_MemBI ST (for AMB spec, Not in SPD) MemBIST Over all MemBIST modes >50% DRAM BW (as dictated by the AMB) Primary channel Enabled Secondary channel Enabled CKE high. Command and Address lines stable DRAM clock active @1.5 V @1.8 V @3.3 V 3.3 2.4 3.8 2.4 W A A A Idd_MemBIST Total Power W 42 Intel® 6400/6402 Advanced Memory Buffer Datasheet Electrical, Power, and Thermal Table 4-4. Power Values for x4 DIMMs (Sheet 3 of 3) 533 MHz Symbol Idd_EI (for AMB spec, Not in SPD) Conditions Electrical Idle DRAM Idle (0 BW) Primary channel Disabled Secondary channel Disabled CKE low. Command and Address lines Floated DRAM clock active, ODT and CKE driven low Power Supply @1.5 V @1.8 V @3.3 V Thermal Design Max Current 2.0 0.2 667 MHz Thermal Design Max Current 2.5 0.2 Units A A A Idd_EI Total Power IDD_S3 S3 Current VDD = 1.9V VCC = 0V VTT = 0V Across process variations Across the operating TCASE temp range DIMM types, R/C A, B, C, D, E, H&J VDD (1.8V) 75 75 W mA Notes: 1. Vdd : Thermal Design = 1.845 V (+2.5%) ; Max Current = 1.900 V (+5.5%) 2. Vcc : Thermal Design = 1.530 V (+2%) ; Max Current = 1.575 V (+5%) 3. Includes all DIMM DRAM organizations (SRx4, DRx4, SRx8, DRx8) and Raw Cards (A, B, C, D, E, H, J) 4. For x8, measured with DRx8 raw card B with 39 ohm termination for command, address, and clocks, and 47 ohm termination for CS and CKE 5. For x4, measured with DRx4 raw card E with parallel 33 ohm termination for command, address, and 39 ohm termination for CS, CKE and clocks 6. Cards using smaller termination resistors will have higher powers. for example, x4 cards parallel 22 ohm termination for command and address could add as much as 0.4W to the power for all states. 7. Total DIMM current during S3 includes AMB IDD_S3 and self-refresh current of all DRAM devices. Intel® 6400/6402 Advanced Memory Buffer Datasheet 43 Electrical, Power, and Thermal 4.2 FB-DIMM Electrical Timing Specifications The FB-DIMM Channel link electrical interface is more completely described in the High Speed Differential Point-to-Point Link at 1.5V for Fully Buffered DIMM specification. Refer to this document for recommended operating conditions. Table 4-5 contains the FB-DIMM electrical timing specifications. Table 4-5. AMB FB-DIMM Timing/Electrical Symbol tEI Propagate tEID tEI tBitLock tFrameLock Parameter EI Assertion Pass-Thru Timing EI Deassertion Pass-Thru Timing EI Assertion Duration Bit Lock Interval Frame Lock Interval Units clks clks clks frames frames 100 119 154 Min Typ Max 4 tBitLock 1 1 1 Notes Notes: 1. Defined in FB-DIMM Architecture and Protocol Spec 2. Clocks defined as core clocks = 2x SCLK input Table 4-6. AMB FB-DIMM Latency Symbol tC2D_AMB Parameter CMD2DATA = 0x36 CMD2DATA = 0x40 CMD2DATA = 0x40 CMD2DATA = 0x46 R/C B R/C B Resample Delay Date Rate 533 667 533 667 533 667 533 667 tRESYNC Resync Delay 533 667 Min 18.7 16.2 20.5 17.7 0x36 0x40 0.9 0.9 2.3 2 Max 22.3 19 24.2 20.5 0x48 0x50 1.6 1.4 3.9 3.2 Units nS nS nS nS nS nS nS nS nS nS 1 1 2 2 Comments tC2D_AMB CMD2DATA tRESAMPLE . Note: 1. tRESAMPLE is the delay from the southbound input to the southbound output, or the northbound input to the northbound output when in resample mode, measured from the center of the data eye. 2. tRESYNC is the delay from the southbound input to the southbound output, or the northbound input to the northbound output when in resync mode, measured from the center of the data eye. Figure 4-1. Latency Timing Diagrams Receiver Input 11 0 1 2 3 4 5 6 7 8 9 10 11 Transmit Output 11 0 1 2 3 4 5 6 7 8 9 10 11 tRESAMPLE tRESYNC 44 Intel® 6400/6402 Advanced Memory Buffer Datasheet Electrical, Power, and Thermal 4.3 Table 4-7. Symbol VDD VREF VTT DDR2 DRAM Interface Electrical Specifications Table 4-7 contains the electrical DC parameters for the AMB DDR2 Recommended Operating Conditions for DRAM Interface Parameter Supply voltage Input reference voltage Termination voltage Min 1.7 0.49 * VDD VREF – 40 Single Ended Signals Nom 1.8 0.50 * VDD VREF Max 1.9 0.51 * VDD VREF + 40 Unit V mV mV VIN VIH(dc) VIL(dc) VIH(ac) VIL(ac) VOH VOL VOTR IOH(dc) IOL(dc) Input voltage DC HIGH-level input voltage DC LOW-level input voltage AC HIGH-level input voltage AC LOW-level input voltage Minimum Required Output Pull-up under AC Test Load Maximum Required Output Pull-down under AC Test Load Output Timing Measurement Reference Level Output minimum source dc current Output minimum sink dc current 0 VDD / 2 + 100 -300 VDD / 2 + 200 VDD / 2 + 575 -13.8 13.8 Differential Signals 0.5*VDD - VDD VDD + 300 VDD / 2 - 100 VDD / 2 – 200 VDD / 2 - 575 mV mV mV mV mV mV V mA mA VID(dc) VID(ac) VIX(ac) Vr VOX(ac) DC differential input voltage AC differential input voltage AC differential input crossing voltage Input timing measurement reference level AC differential output crossing voltage 0.2 0.4 0.5 * VDD 0.100 VIX(ac) 0.5 * VDD + 0.100 V V V 0.5 * VDD 0.100 - 0.5 * VDD + 0.100 V VOUT (slew) Iih Iil CIO ROUT TC Output slew-rate requirement Input leakage current (HIGH) Input leakage current (LOW) Input/Output Capacitance Output Impedance Package surface (case) temperature for AMB 2.2 2.0 13 - - 3.2 10 10 2.5 20 110 V/ns µA µA pF Ohms oC Notes: 1. Values highlighted in ‘Red’ are for reference (that is, placeholder value) 2. No VREF pin on AMB 3. VOUT (slew) covers all other outputs slew rate including clock 4. Input voltage for all pins is limited to a maximum of 2.3 V. 5. VDD/2 = 1.7/2 = 850 mV; VOUT = 575 mV. (VOUT - VDD/2)/IOH must be less than 20 Ohm for values of VOUT between VDD/2 and VDD/2 - 275 mV. 6. VDD/2 = 1.7/2 = 850 mV; VOUT = 275 mV. VOUT/IOH must be less than 20 Ohm for values of VOUT between 0V and 275 mV. 7. CIO is the Input/Output capacitance for DQ/DQS, and Output capacitance for CMD/ADDR/CK. Intel® 6400/6402 Advanced Memory Buffer Datasheet 45 Electrical, Power, and Thermal 4.4 4.4.1 DDR2 Electrical Output Timing Specifications Description of DQ/DQS Alignment The DQS output rising edge aligns with the CLK output rising edge and the DQS output falling edge aligns with the CLK output falling edge. The DQ outputs are 1/4 cycle offset from the DQS outputs. DQ/DQS inputs are edge aligned and will be skewed by internal receiver DLL. Inputs are terminated on-die by a resistive circuit during reads only. 4.4.2 Description of ADD/CMD/CNTL Outputs ADD/CMD/CNTL outputs can be adjusted relative to CLK (see Table 4-8.) to improve setup or hold times. The value of this delay is fixed at boot time. These outputs are either aligned with CLK falling or with a certain timing offset before CLK falling. The amount of offset is implementation specific (for example, can be a constant timing offset, or a known ratio of the DRAM clock period). 4.4.3 Test Load Specification DDR2 timings are specified for a 25 Ohm test load terminated to Vdd/2, measured at the Advance Memory Buffer component package pins. 4.4.4 tDVA and tDVB Parameter Description The timing parameters tDVA and tDVB indicate the time the DQ is valid after or before DQS. tDVA is used to indicate the time that Data is Valid After. tDVA is used for DQ/ DQS write hold calculations (tDH). tDVB is used to indicate the time that Data is Valid Before. tDVB is used for DQ/DQS write setup calculations (tDS). Figure 4-2. tDVA and tDVB Timing Diagram DQS/DQS From AMB tDVB DQ From AMB tDVA 4.4.5 tjit and tjitHP Parameter Description The parameter tjit is the full period jitter, and tjitHP is the half-period jitter. 46 Intel® 6400/6402 Advanced Memory Buffer Datasheet Electrical, Power, and Thermal Figure 4-3. tjit and tjitHP Timing Diagram tCK/2 tjitHP CLK/CLK From AMB tjit tCK 4.4.6 tCVA, tCVB, tECVA and tECVB Parameter Description The parameters tCVA and tCVB specify the time that command is valid after and before CLK. tCVA stands for the time that the Command is Valid After the CLK/CLK crossing point. tCVA is used for CA/CLK hold calculations (tIH). tCVB stands for the time that the Command is Valid Before the CLK/CLK crossing point. tCVB is used for CA/CLK setup calculations (tIS). Table 4-4 shows tCVA and tCVB. tECVA and tECVB apply in early mode. For DIMMs with 36 devices, the command, address and control signals can be shifted by 1/6 clock in early mode. Table 4-5 shows tECVA and tECVB. Figure 4-4. tCVA and tCVB Timing Diagram CLK/CLK FromAMB tCVB CA From AMB tCVA Figure 4-5. tECVA and tECVB Timing Diagram CLK/CLK From AMB tECVB CA From AMB tECVA 4.4.7 tDQSCK Timing Parameter Description tDQSCK indicated the CLK to DQS delay. This value is used for tDQSS, tDSS and tDSH timing calculations. In order to determine these numbers accurately, package parameters must be taken into account. This adjusts the minimum time by -110 ps and the maximum by -70 ps. Intel® 6400/6402 Advanced Memory Buffer Datasheet 47 Electrical, Power, and Thermal Figure 4-6. TDQSCK Timing Diagram CLK (AMB) CLK (AMB) TDQSCK TDQSCK DQS (AMB) 0.5xVCC 4.4.8 DQ and CB (ECC) Setup/Hold Relationships to/from DQS (Read Operation) Table 4-7 shows the timing diagram for tHDamb and tSUamb. The data is launched from the DRAM “edge aligned,” meaning that the DQ data signals switch coincident with the DQS strobe rising and falling edges. Internal to the Advance Memory Buffer, the DQS strobe is delayed by approximately a quarter clock, and this delayed clock is then used to capture the DQ data. Thus, the setup time tSUamb is negative, meaning that the data can arrive at the Advance Memory Buffer inputs after the strobe, and tHDamb is greater than a quarter clock, so that the data will not change until after it has been captured by the internally delayed strobe. The Advance Memory Buffer determines the correct internal delay of strobe DQS based on a search of the data eye during the initialization of the system. The tHDamb and tSUamb specifications are based on an idealized data eye, where the search delays the strobe by exactly one quarter clock. The sum of tHDamb and tSUamb is equivalent to the minimum data valid window at the Advance Memory Buffer inputs. Figure 4-7. DQ and CB (ECC) Setup/Hold Relationship to/from DQS Timing Diagram DQS (AMB) observed at pins DQS (AMB) observed at pins tSUamb DQ, CB (AMB) observed at pins tSUamb tHDamb tHDamb DQS (AMB) delayed internally DQS (AMB) delayed internally DQS Delay (90 deg. nom.) 48 Intel® 6400/6402 Advanced Memory Buffer Datasheet Electrical, Power, and Thermal 4.4.9 Write Preamble Duration The write preamble duration is the measurement from the point when DQS and DQS start to be driven, to the crossing point of DQS and DQS. Typically, to determine when DQS and DQS are starting to be driven, timing measurements are made at 0.5xVCC +/ - 50 mV, and 0.5xVCC +/- 100 mV, and then the measurements are linearly extrapolated back to 0.5xVCC. Figure 4-8. Write Preamble Duration Timing Diagram tWPREamb DQS (AMB) 0.5xVCC 4.4.10 Write Postamble Duration The write postamble duration is the measurement from the crossing point of DQS and DQS, to the point where DQS and DQS start to go into a high impedance state. Typically, to determine when DQS and DQS are starting to go into a high impedance state, for DQS, timing measurements are made at Vlow + 50 mV, and Vlow + 100 mV, and then the measurements are linearly extrapolated back to Vlow. For DQS, timing measurements are made at Vhigh - 50 mV, and Vhigh - 100 mV, and then the measurements are extrapolated back to Vhigh. Figure 4-9. Write Postamble Duration Timing Diagram tW P S T a m b 0 .5 x V C C DQS (A M B ) Intel® 6400/6402 Advanced Memory Buffer Datasheet 49 Electrical, Power, and Thermal 4.4.11 Advance Memory Buffer Component Electrical Timing Summary Table 4-8 and Table 4-9 contain the electrical timing specifications for the Advance Memory Buffer component DDR2 interface. Table 4-8. Advance Memory Buffer Component DDR2 Electrical Timing Specifications DDR2 667 Symbol Parameter Min System Memory Clock Timings tCK tCH tCL tjit tjitHP TDQSCK Ideal clock (CK) period CK high time CK low time CK cycle to cycle Jitter CK half-cycle jitter Clock rising edge to DQS rising edge, or clock falling edge to DQS falling edge -includes -110/-70 ps for package -200 1.35 1.35 150 150 20 -210 3.0 1.70 1.70 175 175 30 3.75 ns ns ns ps ps ps 4-7 4-7 4-10 Max Min Max DDR2 533 Unit s Fig # System Memory Address/Command/Control Signal Timings (Normal) tCVB CMD/ADD/CNTL output valid before CLK/CLK tCVA CMD/ADD/CNTL output valid after CLK/CLK -- includes -140 ps for package System Memory Address/Command/Control Signal Timings (Early) tECVB tECVA Early CMD/ADD/CNTL output valid before CLK/CLK Early CMD/ADD/CNTL output valid after CLK/CLK -includes -140 ps for package 1760 620 2240 850 4-9 4-9 1120 1475 ps 4-8 1260 1615 ps 4-8 System Memory Data and Strobe Signal Timings tDVB DQ[63:0], CB[7:0], valid before DQS[15:0]/ DQS[15:0] crossing DQ[63:0], CB[7:0], valid after DQS[15:0]/DQS[15:0] crossing DQ[63:0]. CB[7:0] Output Valid Pulse Width DQ and CB Input Setup Time to DQS Crossing DQ and CB Input Hold Time After DQS Crossing DQS Write Preamble Duration DQS Write Postamble Duration 575 750 ps 4-6 tDVA 575 750 ps 4-6 tDOPW tSUAMB tHDAMB tWPREAMB tWPSTAMB 1.35 -530 970 2.85 1.35 3.5 1.65 1.70 -700 1180 3.58 1.7 4.25 2.05 ns ps ps ns ns 4-11 4-11 4-12 4-13 50 Intel® 6400/6402 Advanced Memory Buffer Datasheet Electrical, Power, and Thermal 4.4.12 Reference DDR2 Interface Package Trace Lengths The following reference package trace lengths have been incorporated into the Advance Memory Buffer timings in Table 4-9. Table 4-9. Advance Memory Buffer DDR2 Package Lengths Signal Group CLK/CLK Command/Address CKE, CS# ODT DQS/DQS/DQ Min Length 24 4 9 10 9 Max Length 26 20 22 16 13 Units mm mm mm mm mm 4.5 SMBUS Interface Table 4-10. Recommended Operating Conditions for SMBUS Interface Symbol VDDSPD VIL VIH VOL ILEAK-BUS ILEAK-PIN IPULLUP CBUS CI VNOISE Parameter Supply voltage (SMBUS) SMBus signal input low voltage SMBus signal input high voltage SMBus signal output low voltage Input Leakage per bus segment Input Leakage per device pin Current sinking, VOL = 0.4V Capacitive load per bus segment Capacitance for SMBDAT or SMBCLK pin Signal noise immunity from 10MHz to 100MHz Min 3.0 2.1 4 300 Typ 3.3 Max 3.6 0.8 VDDSPD 0.4 +200 +10 400 10 Unit V V V V µA µA mA pF pF mV p-p This is AC item applies to the high-power DC specification only @IPULLUP Comments 3.3v +10% Note: Based on High-power SMBus DC Specification 4.6 Miscellaneous I/O (1.5 Volt CMOS Driver) Table 4-11. Recommended Operating Conditions for RESET and BFUNC Pins Symbol VIH(dc) VIL(dc) ILEAK Parameter DC HIGH-level input voltage DC LOW-level input voltage Input leakage Min 1.0 Typ Max 0.5 + 90 Unit V V µA Comments 4.7 Thermal Diode and Analog to Digital Converter (ADC) A thermal diode with an analog to digital converter (ADC) is required. The thermal sensor will be used to ensure prevention of catastrophic failure. Intel® 6400/6402 Advanced Memory Buffer Datasheet 51 Electrical, Power, and Thermal An 8-bit register will store the temperature. The sensor measures from 0 to 127 degrees C measured in 0.5 degree increments in a register with values from 0 to 255. Internal analog nodes (anode, cathode, and so forth) of this circuit will not be brought out to package pins to keep noise at a minimum. Refer to the Intel® 6400/6402 Advanced Memory Buffer Thermal Mechanical Design Guide for more information on the thermal sensor. 4.7.1 Thermal Sensor Effects on the AMB’s Functional Behavior When enabled, the results of the thermal trip points TEMPLO and TEMPMID are reported in FBD Status 0 responses following Sync commands. If the temperature exceeds TEMPHI, errors are logged. If the TEMPHIENABLE bit in the TEMPSTAT register is set, DDR shutdown occurs and FBD links go into electrical idle mode. This over TEMPHI behavior also applies when in LAI mode. See the error chapter for a more complete description of chip behavior when TEMPHI is exceeded. A temperature TEMPSTAT.INCREASING bit is also generated depending on whether the temp is greater or less than the last time the INCREASING bit was sampled. Sampling to create INCREASING bit is controlled by writes to register UPDATED. When temperature is above TEMPMID, this information also shows up in the FBDS0.Thermal_Trip register field and in the Status response of FBD Sync commands targeted to FBDS0. § 52 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode 5 5.1 Debug and Logic Analyzer Mode Logic Analyzer Interface (LAI) Mode This section describes the functionality of the optional Logic Analyzer Mode for the Intel 6400/6402 Advanced Memory Buffer (AMB). The features of the logic analyzer mode (LAI mode) in the Fully Buffered DIMM will enable select bus observability capabilities. The mode will be the basis of an LAI assembly to provide link traffic trace capability and will support design and manufacturing debug and validation needs for systems featuring FBD links. In this application, the device is programmed to perform the following functions: • Repeater pass-through operation for southbound and northbound links • Provides enough link protocol unwinding to allow extraction of framing boundaries, idle filtering opportunities, and pattern match triggering • Performs logic analysis functions such as cross-triggering, match/mask, and local event detection. These functions cannot be effectively performed using a remote logic analyzer. • Provides independent demuxed northbound and southbound traffic stream in LA compatible signal levels and timing format through reuse of the existing device DRAM I/O pins • Provides SMB (or possibly another communications interface) access to allow external, non-intrusive access to component LAI control functions/parameters • The AMB is commanded to power up in LAI mode when SMA[3:2] addresses are strapped to 2’b11 and LAI capability bit is enabled. Intel® 6400/6402 Advanced Memory Buffer Datasheet 53 Debug and Logic Analyzer Mode Figure 5-1 is a conceptual depiction of the AMB used in a LAI mode application. Figure 5-1. AMB LAI Mode Usage Diagram LAI Interposer Probe Assembly Concept Instantiation of LAI Interposer Using AMB Standard LA High Density Probes Interposed DIMM DRAM DIMM0 AMB DIMM1 DIMM2 DIMM3 AMB In LAI Mode MCH Showing only southbound FBD Links, but northbound follow same path in reverse. 5.1.1 LAI Mode Architecture The diagram below illustrates the AMB as a functional block when used as a LAI. The normal southbound and northbound links, the reference clock, and the SMB bus are used “as is”. The channel traffic is reflected onto the DRAM interface with frame alignment for access with a logic analyzer. To be effective in collecting useful FBD traces, the information provided to a logic analyzer must include not only a demuxed copy of the direct information transferred on the links, but also several types of derived information that a logic analyzer is not equipped to derive itself. These include specifically: • Cross-triggering information with finer timing granularity than LA can achieve • Simple filtering (qualified storage) opportunities recognition • Traffic framing 54 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode Figure 5-2. AMB LAI Mode Connectivity AMB in LAI Mode 6 Reference clock 1 x2 To MCH or next DIMM to the North Southbound In 10 x2 Northbound Out 14 x2 14 x2 TRIG[10:0] 4 FRAME 1 CLK[p,n] 1 x2 QUAL 1 MODE 1 Shared signals to other trace Bds S[59:00] EV[3:0] 4 60 N[83:00] 84 Southbound and northbound signals to logic analyzer Shared signals to logic analyzer 10 x2 Northbound In Southbound Out To next DIMM to the South SMB 5.1.2 LAI Mode Clocking To eliminate frequency drifts, the AMB on each DIMM and the chipset in an FBD channel will be provided with a reference clock that is from a clock source common to the FBD channel. A clock buffer will be placed on the LAI card to take the reference clock input and provide the required two reference clocks for the LAI AMB and the attached DIMM AMB. 5.1.3 LAI Mode Pins The DDR pins designed in the AMB can be enabled to carry signals for the logic analyzer debug and validation of the FBD channel. The LAI mode is selected by strapping the following input pins on a AMB which has the LAI capability bit enabled. SA[:0] = DIMM ID = 4b’11XX The list below highlights the pins in the AMB that are dedicated for DDR, all of which are not required to operate at speed equal to the DDR data rate. Address/Command pins are specially designed in the AMB to be able to drive double data rate to support the LAI functionality. Intel® 6400/6402 Advanced Memory Buffer Datasheet 55 Debug and Logic Analyzer Mode Table 5-1. DDR Pins Shared With LAI Functionality Signal Type DDR DDR DQ & DQS DDR Cmd/Addr 108 56 533/667 266/333 ~ LAI signal ~ LAI signal DQS must run single ended in LAI mode Most must run double speed in LAI mode Some may be dedicated to bidirectional Event Bus May run single ended in LAI mode Not suitable for LAI signals Count Speed (MHz) Use in LAI Mode Comment Clocks to DRAMs DDR Comp and analog Total DDR Pins 8 5 177 533/667 analog ~ LAI signal Table 5-2. List of Pins Required to Enable Debug With LAI Functionality Signal Type Southbound S[59:0] Northbound N[83:0] MODE TRIG[10:0] CLK QUAL FRAME EV[3:0] Comp Pins Total Pins 84 1 11 4 1 1 4 5 171 533/667 267/333 267/333 267/333 533/667 533/667 100 Analog Bidirectional Required for signal integrity Two Differential pairs Data 60 533/667 Data Count Speed (MHz) Comment 5.1.4 Table 5-3. LAI Mode Signal Definitions LAI Mode Added Signals (Sheet 1 of 2) Signal Type S[59:0] N[83:0] MODE Direction Out Out Out Definition Southbound demuxed (6x10) traffic Northbound demuxed (6x14) traffic Link mode: 0 = after training complete 1 = before training complete Triggers to LA. This provides eleven unique trigger signals to the LA from the AMB LAI as a result of frame pattern matching, state matching, and/or cross-triggering events from other LAIs. This allows cooperating AMB LAIs to overcome (a) limitations of LA in recognizing serial traffic patterns that exceed LA pattern matching capabilities and, (b) relatively long latencies in crosstriggering between LA modules. TRIG[10:0] Out 56 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode Table 5-3. LAI Mode Added Signals (Sheet 2 of 2) Signal Type CLK Direction Out Definition Logic analyzer reference clock (differential). This provides a LA compatible timing reference clock for capture of all signals to the LA, with fine capture phase adjust using the native LA clock edge offset capabilities. Store qualifier: 1 = store 0 = do not store Drives 1 when LAI pins are valid level. Should be connected to pull down on LAI board to detect when LAI pins are tri-stated and LA should ignore data. Inter-AMB event bus for cross-triggering (wired-OR, high active, slow).This four bit event bus allows multiple AMB (and similar) LAIs to be programmed to inter-communicate locally detected matching and/or filtering opportunities events (cross-triggering and cross-qualification). QUAL Out FRAME Out EV[3:0] I/O 5.1.5 LAI to DDR Pin Mapping Table 5-4 contains the LAI-to-DDR pin mapping. Table 5-4. List of Shared DDR/LAI Pins (Sheet 1 of 2) DDR Pin DQ[55:52], DQS[15], DQS[15] Count 6 Speed Mbit/sec 533/667 LAI Mode sbframe_data0[5:0], [11:6] Comment 5:0 captured on rising edge of CLK, 11:6 captured on falling edge of CLK DQ[59:56], DQS[7], DQS[7] DQ[51:48], DQS[6], DQS[6] DQ[39:36], DQS[13], DQS[13] DQ[47:44], DQS[14], DQS[14] DQ[35:32], DQS[4], DQS[4] DQ[43:40], DQS[5], DQS[5] RASB, A[10:9)B, DYBA[2:0]B A[6:2]B, A[0]B A[15:11],B A[8]B CKE[1:0]B, CS[1:0]B, ODTB, BA[2]A CASB, WEB, A[7]B, A[1]B CASA RASA CKE[1:0]A, CS[1:0]A, ODTA, WEA 6 6 6 6 6 6 6 6 6 5 1 4 1 1 6 533/667 533/667 533/667 533/667 533/667 533/667 533/667 533/667 533/667 267/333 533/667 100 MHz 267/333 267/333 267/333 sbframe_data1[5:0], [11:6] sbframe_data2[5:0], [11:6] sbframe_data3[5:0], [11:6] sbframe_data4[5:0], [11:6] sbframe_data5[5:0], [11:6] sbframe_data6[5:0], [11:6] sbframe_data7[5:0], [11:6] sbframe_data8[5:0], [11:6] sbframe_data9[5:0], [11:6] trigger[10:6] frame evbus[3:0] mode qual trigger[5:0] Will only change at 1/2 freq Will only change at 1/2 freq 1 if transferring first half of frame, 0 if second half Inner DY bumpout rows Intel® 6400/6402 Advanced Memory Buffer Datasheet 57 Debug and Logic Analyzer Mode Table 5-4. List of Shared DDR/LAI Pins (Sheet 2 of 2) DDR Pin A[5:0]A Count 6 Speed Mbit/sec 533/667 LAI Mode nbframe_data0[5:0], [11:6] Comment 5:0 captured on rising edge of CLK, 11:6 captured on falling edge of CLK A[11:6]A BA[1:0]A, A[15:12]A DQ[23:20], DQS[11], DQS[11] DQ[31:28], DQS[12], DQS[12] DQ[19:16], DQS[2], DQS[2]] DQ[27:24], DQS[3], DQS[3] DQ[15:12], DQS[10], DQS[10] DQ[7:4], DQS[9], DQS[9] DQ[11:8], DQS[1], DQS[1] DQ[3:0], DQS[0], DQS[0] CB[3:0], DQS[8], DQS[8] CB[7:4], DQS[17], DQS[17] DQ[63:60], DQS[16], DQS[16] CLK[3:2] CLK[3:2] CLK[1:0] CLK[1:0]# Total DDR Pins 6 6 6 6 6 6 6 6 6 6 6 6 6 2 2 2 2 162 533/667 533/667 533/667 533/667 533/667 533/667 533/667 533/667 533/667 533/667 533/667 533/667 533/667 267/333 MHz 267/333 MHz 267/333 MHz 267/333 MHz nbframe_data1[5:0], [11:6] nbframe_data2[5:0], [11:6] nbframe_data3[5:0], [11:6] nbframe_data4[5:0], [11:6] nbframe_data5[5:0], [11:6] nbframe_data6[5:0], [11:6] nbframe_data7[5:0], [11:6] nbframe_data8[5:0], [11:6] nbframe_data9[5:0], [11:6] nbframe_data10[5:0], [11:6] nbframe_data11[5:0], [11:6] nbframe_data12[5:0], [11:6] nbframe_data13[5:0], [11:6] nc nc LAI clock p [1:0] LAI clock n [1:0] No spare pins Not supported in LAI Mode Not supported in LAI Mode 5.1.6 FBD to LAI Signal Mapping The following example show how an FBD Southbound Command Frame is transferred from FBD frame format to LA Interface early/late data. The LAI interface delays the SB “A slot” by one clock to capture the FBD frame in the same “ABC” slot format that is sent from the host - rather than the “BCA” (B and C slots from host frame N-1 plus A slot from host frame N) used by the normal mode AMBs to minimize latency on the decode of slot A commands. 58 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode Table 5-5. Transfer N0 N1 N2 N3 N4 N5 N6 N7 N8 N9 N 10 N 11 \ Bit Typical FBD Southbound Command Frame 9 aE0 aE1 aE2 aE3 FE21 FE20 FE19 FE18 FE17 FE16 FE15 FE14 8 aE7 aE6 aE5 aE4 0 0 0 0 0 0 0 0 7 aE8 aE9 aE10 aE11 0 0 0 0 0 0 0 0 6 F0=0 F1=0 aE13 aE12 0 0 0 0 0 0 0 0 5 aC20 aC21 aC22 aC23 bC20 bC21 bC22 bC23 cC20 cC21 cC22 cC23 4 aC16 aC17 aC18 aC19 bC16 bC17 bC18 bC19 cC16 cC17 cC18 cC19 3 aC12 aC13 aC14 aC15 bC12 bC13 bC14 bC15 cC12 cC13 cC14 cC15 2 aC8 aC9 aC10 aC11 bC8 bC9 bC10 bC11 cC8 cC9 cC10 cC11 1 aC4 aC5 aC6 aC7 bC4 bC5 bC6 bC7 cC4 cC5 cC6 cC7 0 aC0 aC2 aC3 bC0 bC1 bC2 cC0 cC1 cC2 cC3 Output to logic analyzer is lane by lane early data [lane 9][lane 1][lane0] [FE20,FE21,….,aE0] ……… [bC5, bC4, aC7, aC6, aC5, aC4] [bC1, bC0, aC3, aC2, aC1, aC0] late data [lane 9][lane 1][lane0] [FE14,FE15,….,FE19] … … [cC7, cC6, cC5, cC4, bC7, bC6] [cC3,cC2, cC1, cC0, bC3, bC2] Note: CRC codes in A cmd (aE0 - aE13) are a function of FE21:FE14 of previous frame. 5.1.7 LAI to DDR Pin Timing The phases of data presented to the logic analyzer have some odd timing due to reuse of some many different types of DDR I/O outputs to achieve the desired pin count. The LA will compensate for these predictable phase offsets. Intel® 6400/6402 Advanced Memory Buffer Datasheet Late Data 59 bC3 Early Data aC1 Debug and Logic Analyzer Mode Figure 5-3. LAI Signal Group Timing CLK LAI data Cmd/Addr LAI data on DQ LAI data on DQS Triggers Cmd/Addr Qual early data early data early data late data late data late data trigger matched to early/late data qual on frame 5.1.8 5.1.8.1 LAI Features Control and Status Registers (CSRs) LAI mode CSRs will be accessed and programmed through SMBus when in LAI mode. See Chapter 14, “Registers,” for complete details. Note: LAI registers cannot be accessed in-band over the FBD link 5.1.8.2 Pattern Matching The LAI block can pattern match on three command values at any of three command slots and combine the results into independent and combined local events. There are 13 total pattern matching events: a command value matches a command slot (9 events), a command value matches any slot (3 events), and all command values appear in the frame (1 event). This pattern matching is also used in normal mode for error injection and NB in-band event generation.Figure 5-4 shows the LAI match and mask logic. 60 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode Figure 5-4. LAI Match and Mask Logic MM_12 Match & Mask Registers for Cmnd #0 Mask & match A Cmd slot Combining Results & Reg. AND (full frame) OR – match MM_11 0 in any pos MMEVENT[2] A matches 0 13:1 mux MM_2 13 B matches 0 Cmd Qual Logic MM_5 Early Southbound Pipeline stage Mask & match B Cmd slot Combining Results & Reg. Match & Mask Registers for Cmnd #1 Mask & match C Cmd slot Combining Results & Reg. C matches 0 OR -match 1 in any pos MM_8 Match Events MMEVENT[1 13:1 mux 13 MM_10 13 M&M CmdA A matches 1 B matches 1 C matches 1 Cmd Qual Logic OR – match 2 in any pos MM_1 MM_4 M&M CmdB MMEVENT[0 Match & Mask Registers for Cmnd #2 M&M CmdC MM_7 MM_9 MM_0 MM_3 MM_6 13:1 mux 13 M&M CmdA A matches 2 B matches 2 C matches 2 M&M CmdB Cmd Qual Logic M&M CmdC 5.1.8.2.1 Additional Qualification on Match/Mask Full frame and A-slot matching is enabled part way through TS0, once FBD inputs have been aligned with the core clocking phases. Though generally, will not be used until link has completed initialization. Slot B and Slot C pattern matching is further qualified so that true commands can be differentiated from data when not doing full frame matching. For each mask and match pair 0, 1 or 2 • If Mask[39] = 1, then match and mask against any received data in Slot B and Slot C. • If Mask[39] = 0 AND Match[39] = 0 then only match on commands. — Ignore a match with contents of Slot B if Frame type is not Command or Frame type is command and A-command is Sync or Soft Reset — Ignore a match with contents of Slot C if Frame type is not Command or Frame type is command and A-command is Sync or Soft Reset or B-command is Write Configuration Register Intel® 6400/6402 Advanced Memory Buffer Datasheet 61 Debug and Logic Analyzer Mode To match an FBD command that might occur in any slot including the A slot, mask out bits [38:24] and set both Mask[39] and Match[39] to 0. • If Mask[39] = 0 AND Match[39] = 1 then only match on memory write data. — Match and mask against received data in slot B and slot C if Frame type is Write Data Frame 5.1.8.3 Local Events The mask/match features in the AMB LAI, and certain internal state and error conditions, will be used to generate local events. Global events propagated through the in-band debug and external event (EV) bus will also generate local events. All of the local events can be selected by muxes as trigger sources for LAI event signals and event bus signals. While not used in LAI mode, these events are also used in error injection and for sourcing events in the NB status frames. For exact details see the Configuration Registers Chapter. An overview of the Local Events logic is shown below. The Match/Mask, Qualification and Event Bus blocks are described in more detail in other sections. Figure 5-5. Local Event Mux Block Diagram Local Event Mux Block Diagram Local pattern matching events 12 3 Qual_start event SQ Other Qual logic Qual R MMEVENTSEL Qual_stop / Inj_err event Delay Qual_flag LAI Match and Mask Logic LAI Qualification Logic Local Event Muxes 0 Spare Errors Qual flag SB IB debug events EVBus in[3:0] MMEVENT[2:0] FBD link states 0 Null event 77 31 66 30-25 55 24 44 23-16 33 15-12 22 11-9 11 8-1 0 00 Lai mode Error injection control 18 LAI trigger[10:0] NB IB event control EVENTSELx, EVBUS EVBus out[3:0] 4 Output filter 1 EVBus[3:0] EVBus in[3:0] 4 Input filter EVBus Input and Output Table 5-6 shows the 32 local events. Each of these local events is logged in a configuration register and is sent to 19 32:1 muxes. The select lines for these muxes are programmed in configuration registers. Table 5-7 shows the destination (intended use) of the 19 selected events. Table 5-6. LAI Local Events (Sheet 1 of 2) Name Mask and Match Events 3 Sel Addr 11:9 Description MMEVENT2:MMEVENT0 Slota, Slotb, Slotc, and Frame command matches - 3 events preselected from 13 possible matches Received on SB link in-band EV[7:0] Received on select DDR pins Event Bus EV[3:0] In-band debug EVBus events 8 4 23:16 15:12 62 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode Table 5-6. LAI Local Events (Sheet 2 of 2) Name Initialization States Errors Events 8 6 Sel Addr 1:8 30:25 Description Disable[1], calibrate[2], training[3], testing[4], pollling[5], config[6], l0[7], l0s or recalibrate[8] • SB/NB Fail Over mode [25], when unmasked: • SB CRC error[26], • Thermal overload[27], • Clock training violation (< 6 transitions in 512 UI) [28], • Unimplemented register access[29], • Other implementation specific errors[30] For the Intel 6400/6402 Advanced Memory Buffer: event[30] is the “OR“ of any bit in FERR[7:4] or NERR[7:4] Qual_Flag Spare NOP Total Events 1 1 1 32 24 31 0 Null Event For the Intel 6400/6402 Advanced Memory Buffer: There is enough space for 32 events Table 5-7. LAI Event Selection Name Output event/triggers EVBus events Inject Event NB Error Injection Trigger Qual Events Total Events Events 11 4 1 1 2 19 Sent to LA on DDR pins Sent on DDR pins Assert NB event bit - not necessarily LAI usage Inject errors - not necessarily LAI usage Start and stop events for qualification signal Description 5.1.8.4 Event Bus The AMB LAI mode enables four events signals (EV[3:0]) to be shared between the AMB or compatible LAI devices in a system. The signals are shared through a uniquely defined interconnect that connects all the devices to the 4-bit wide daisy chain bus. The 4 lanes are independent and carry separate events or triggers. Due to the noisy nature of the interconnect between LAI devices, filtering is required to eliminate spurious events from being introduced. A typical lane is shown in Figure 5-7 below. Intel® 6400/6402 Advanced Memory Buffer Datasheet 63 Debug and Logic Analyzer Mode Figure 5-6. EVBus Overview EV Bus System Topology Local Events bus to other LAI Output Filter ENB “1” EVBus Event Select pin EVBus Local Event Input Filter Each lane in the bus can be selected by the EVTYPE parameter to be a pulse (trigger) event or a level (qualifier) event. Timing for the input and output filters is set by the EVT parameter which defines the Tmin in core clock cycles. Both of these parameters reside in the EVBUS control register along with the local event select controls for each lane in the bus. Pulse mode timing: Input: Inputs are digitally filtered to reduce spurious events from bus ringing. Once a rising edge is detected a single one clock width pulse event is sent to the local events. No further pulse events are permitted until the next rising edge that occurs after the longer of either (2 * Tmin) or (T_source_event_actual + T min). Output: An output high pulse of length Tmin or T_local event_actual (whichever is longer) is sourced whenever triggered by the selected local event. This is followed by an output low pulse of length Tmin. Further toggling by the selected local event is ignored until this output sequence is complete. Level mode timing: Input: Once a rising edge is detected the local event is asserted and remains asserted for Tmin or T_source_event_actual which ever is longer. Output: An output high pulse of length Tmin or T_local event_actual (whichever is longer) is sourced whenever triggered by the selected local event. Figure 5-7 shows the event signal timing. 64 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode Figure 5-7. Event Bus Signal Timing P ulse E V B us tim ing S elected Local E vent Filtered E V B us P ulse O ut EVT EVT R eceived E V B us S ignal Filtered E V B us P ulse In Local E vent Additional pulses filtered out for period of at least 2 * EVT Q ualifier Level E V B us tim ing S elected Local E vent Filtered E V B us P ulse O ut M inim um Pulse = E V T R eceived E V B us S ignal Filtered E V B us P ulse In Local E vent M inim um P ulse = EV T The signals will be driven or captured by four DDR I/O buffers. Intel® 6400/6402 Advanced Memory Buffer Datasheet 65 Debug and Logic Analyzer Mode 5.1.8.5 Qualification The AMB in LAI mode sends a qualification signal, QUAL, on a DDR pin along with each frame. A qualified frame contains data likely to be of interest to the user of the logic analyzer. Conversely, an unqualified frame has been chosen to be filtered out because it only contains idle NOP frames or has otherwise been “flagged” as not occurring between pre-selected events. The logic analyzer can capture data when QUAL is asserted, and ignore data when QUAL is deasserted. Once a qualified frame is seen, the QUAL signal is asserted, and it remains asserted for an additional programmable number of cycles, using a timer ranging from 0 to 63. This timer is restarted if it is already running when a new qualified frame is seen. The error injection timer will be used to push out the triggering of the QUAL_STOP signal by N timer count of clock cycles (where N is user programmed for delay range of 0 to 63), thus increasing the length of the QUAL_FLAG interval. One QUAL_START event will enable the assertion of QUAL_FLAG and another QUAL_STOP event will disable assertion of QUAL_FLAG. A frame of all NOPs is not a qualified frame. A sync frame is not a qualified frame if the FILTER_SYNC configuration register bit is set; otherwise it is considered qualified. Note: The ability to determine which frames are qualified may be lost following an unmasked CRC or Few Edges error. This is the result of the architected behavior that future commands following the error will ignored. As a side effect, QUAL may stay high once these errors are detected. If the QUAL_MODE configuration register bit is set, frames must additionally occur between QUAL_START and QUAL_STOP events to be qualified. A frame that triggers QUAL_START may also cause the QUAL signal to assert, and a frame that triggers QUAL_STOP will not be considered qualified. The QUAL_START and QUAL_STOP events are programmable and are selected from the 32 local events. Figure 5-8 is a block diagram of the qualification signal control logic. Figure 5-8. LAI Qualification Signal Block Diagram F ILTER_SYNC F ormat = cmd+wdata QUAL_PERIOD[5:0] C ommand A C ommand SYNC C ommand NOP A ND 1 0 OR A ND >0 Q UAL_MODE QUAL input load dec C ommand B C ommand NOP C ommand C C ommand NOP Q UAL_START[4:0] s et QUAL_FLAG local events T imer 0…63 clr QUAL_STOP[4 :0] QUALSTOPDELAY[5:0] 66 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode 5.1.9 LAI Block Diagram Figure 5-9 is a block diagram of the LAI implementation. The LAI block defines a frame from the host (not the AMB) point-of-view, so the slota command is delayed by one core cycle relative to the slotb and slotc commands. The southbound delay pipeline consists of one set of core registers for slota, and one set of core registers for delayed slota, and slotb and slotc. The protocol unwrapping and pattern recognition block takes the registered southbound frame and detects and logs any local events. Events are selected in this same cycle, registered on the core clock, and then forwarded to the DDR cluster. The southbound frame is also registered once more and forwarded to the DDR cluster. The northbound registers the line this data to the same clock domain as the southbound data before it is forwarded to the DDR cluster. Figure 5-9. Block Diagram of AMB in LAI Mode AMB in LAI Mode Southbound In Retiming Remainder of path unmodified* Southbound Out S[59:00] Reference clock Demux Deskew Southbound Delay Registers Q SMB Protocol & Pattern Recognition Q CLK[p,n] QUAL FRAME Q Events Selection, & Responses EV[3:0] TRIG[10:0] Q MODE Control/Status Register Demux Deskew Northbound Delay Registers Q N[83:00] Q Northbound Out Retiming & Merge* Remainder of path unmodified* Northbound In Intel® 6400/6402 Advanced Memory Buffer Datasheet 67 Debug and Logic Analyzer Mode 5.2 5.2.1 Normal Mode Debug Features Normal Mode Debug Triggers Southbound command matching/masking functionality may be available in normal AMB operation. This can be used for triggering error injection or returning a signal in a northbound status frame for debug/monitoring purposes for example. 5.2.2 Error Injection Refer to the JEDEC publication: FB-DIMM Draft Specification: Design for Test, Design for Validation (DFx) Specification for more information regarding Error Injection. Selected errors of specific types may be injected internal to the AMB in response to selected in-band events or by mask/match events from commands arriving at the AMB . In the case of stuck lane errors, these are controlled directly via registers on the AMB The AMB will also forward errors injected by the host into the SB link. 5.2.2.1 Types of Injected Errors There are several types of errors that the AMB can inject in order to enable validation and debug hardware and software mechanisms intended to deal with each error type in operating systems. 5.2.2.1.1 Errors Injected in Northbound Command Register Read and Read Data Frames In response to a selected local event, the AMB will inject an error in frame data after or during calculating frame CRCs and transmitting the frame northbound. This is necessary to test/validate/debug HW and SW mechanisms designed to detect and deal with northbound channel soft (non-repeatable) channel transport errors. Errors can be injected using the LFSR Idle pattern generator as a default. 5.2.2.1.2 Status Bits Injected in Status Block Sent Back in Response to Sync Command In response to an FBD Sync command with R[1:0] = 2’b11, the AMB will return the user written FBDS3 for the next status block returned in response to a Sync command. 5.2.2.1.3 Invalid Parity Injected in Status Block Sent Back in Response to Sync Command If the FBDS3.OVREN bit is set and FBDS3.USRPAR contains invalid parity for the data in FBDS3.USRVAL, the in response to an FBD Sync command with R[1:0] = 2’b11 and, the AMB will cause invalid parity to be passed in the next status a block returned in response to a Sync command. 5.2.2.1.4 Force Alert In response to a selected local event, the AMB will force the beginning of alerts northbound. An error status bit indicating an injected alert error as the source will also be set. This error may be created by artificially corrupting CRC on the frame whose timing matches the error injection. This may have the same side effects as corrupting the CRC but will have a different error status. The beginning of alerts northbound will begin with the frame that would match read return slot for the corrupted frame. For the Intel 6400/6402 Advanced Memory Buffer, the alert takes place 2 to 3 clocks after the NB response for the SB frame that caused the trigger 68 Intel® 6400/6402 Advanced Memory Buffer Datasheet Debug and Logic Analyzer Mode 5.2.2.1.5 Selectively Force “Stuck On” Northbound Lanes This capability is required to test ability of components and system to accomplish lane fail-over. Note that this is the only error injection feature which is not event driven, but rather shall be controlled directly by the STUCKL register in the AMB. The selected lanes are “stuck” by being forced into “Electrical Idle”. 5.2.2.1.6 Sourcing Northbound In-Band Event The northbound event shall be asserted in the next transmitted FBDS0 status block following assertion of a selected local event. This approach allows any local event to be propagated past a tracing AMB LAI monitoring the FBD channel as well as for use as an event stimulus to the Host Interface logic. § Intel® 6400/6402 Advanced Memory Buffer Datasheet 69 Debug and Logic Analyzer Mode 70 Intel® 6400/6402 Advanced Memory Buffer Datasheet Errors 6 6.1 Errors Types of Errors and Responses The Intel 6400/6402 Advanced Memory Buffer (AMB) detects link errors that could lead to data corruption. This includes CRC on commands and write data. The AMB also prevents damage to the machine state. 6.1.1 6.1.1.1 FBD Link Errors Link Initialization Errors Table 6-1 shows link errors that can occur during initialization. Table 6-1. Link Errors in Initialization Error Multi-lane failures - unable to achieve bit lock on at least 9 of 10 SB lanes Multi-lane failures - unable to achieve bit lock on at least 12 NB lanes NB_Data_Merge_Disable - able to achieve bit lock (pass thru link data) but internal errors prevent receiving valid link cmds or merging data Single Lane failure - SB and/or NB Response Never come out of training state Never come out of training state Host sets NB_Merge_Disable bit in TS2 to cause DIMM to be in a passthru mode both SB and NB - act as a blind repeater 1. No attempt to decode commands, no response to link register RD/ WR, generate no alerts, neither generate or merge any NB traffic 2. SMBus access enabled Support normal initialization protocol and Fail Over mode if commanded by host Intel® 6400/6402 Advanced Memory Buffer Datasheet 71 Errors 6.1.1.2 Table 6-2. Errors during Channel Operation Link Errors in Normal Operation (Sheet 1 of 2) Error Response If CMDCRC error type enabled in EMASK Register 1. No command executed 2. 120-bit Raw SB Frame captured in RECFBD Error Log Registers 3. Type of error logged in FERR/NERR registers 4. Error/Alert Asserted bit set in FBD Status 0 register 5. Ignore future commands except Soft Channel Reset until Soft Channel Reset or Link Reset Received 6. Alert Frame sent continuously starting with NB frame in which returned data pattern would be sent if aborted command had been a config read. Alert patterns continue until Soft Channel Reset or Link Fast Reset received. Note: Will NOT close DRAM pages or place DRAM into Self Refresh until detection of Link Reset. Else ignore error If FEWEDGES error type enabled in EMASK Register 1. No command executed in expected Sync slot 2. 120 bit Raw SB Frame captured in RECFBD Error Log Registers 3. Type of error logged in FERR/NERR registers 4. Error/Alert Asserted bit set in FBD Status 0 register 5. DDR Self Refresh FSM triggered to put DRAMs into Self Refresh 6. Ignore future commands including Soft Channel Reset until Link Reset Received 7. Alert Frame sent continuously starting with NB frame in which returned data pattern would be sent if aborted command had been a config read. Alert patterns continue until Link Fast Reset received. Else ignore error Overwriting the write buffer is a host error. The AMB does not take any action based on an overrun. DRAM writes will proceed. What data item is written following an overrun condition is not defined. An overrun could be the result of channel errors, but these errors are detectable by other means. Detection of an overrun condition is not required, but may be done by implementation dependent means for debug. Underrunning the write buffer is a host error. The AMB does not take any action based on an underrun. DRAM writes will proceed. What data item is written following an underrun condition is not defined. An underrun could be the result of channel errors, but these errors are detectable by other means. Detection of an underrun condition is not required, but may be done by implementation dependent means for debug. CRC Error on SB frame “A” Command - detected by 14-bit CRC (or reduced 10-bit CRC in Fail Over mode) or CRC Error on SB data or “BC” Commands in Command Frame - detected by 22-bit CRC (or reduced 10bit CRC in Fail Over mode Lose transition density on channel as detected by no Sync in within 2 times the SYNCTRAININT value (typically last 84 frames). Note: Purpose of this error is not to detect violation of required transition density (6 out of 512) but to detect hang in the host and put DRAM into self refresh. Any corruption caused by lack of transitions will be detected by CRC violations. Write Buffer Overrun Write data received when FIFO is full Write Buffer Underrun: not enough valid entries in Write FIFO to support write data to memory 72 Intel® 6400/6402 Advanced Memory Buffer Datasheet Errors Table 6-2. Link Errors in Normal Operation (Sheet 2 of 2) Error Response If UNIMPLCFG error type enabled in EMASK Register 1. Drop Config Write cmds 2. Capture Addr in RECCFG register if not previously set 3. Return 0’s data if Config Read (or return -1 if Read addr to unimplemented function - though currently expect all functions to be used) 4. UNIMPLCFG error type logged in FERR or NERR registers 5. Error/Alert Asserted bit set in FBD Status 0 register Else ignore error NOTE: The timing of the Error/Alert Asserted bit in FBD Status 0 response for an unimplemented register is not guaranteed relative to the corresponding Sync/Status boundaries. For example, if an unimplemented register access occurs in the frame before a Sync frame, the Error Asserted bit in FBD Status 0 may not be asserted in northbound Status corresponding to that Sync. But it will be asserted in a later Status response. Access to unimplemented register Undefined command TID error on config writes Undefined commands with good CRC are ignored. This is not considered an error condition, and is not logged. Treat as reserved command or Channel NOP If the TID bit on a config write matches the value of the previous TID bit, the write is ignored. The TID bit stored in the AMB is left unchanged in this case. This error does not cause an alert frame, and is not logged. The purpose of the TID bit is to allow the host to retry a config write command following a fast reset if it does not know if it had been executed prior to an alert. If the config write had occurred the TID bit will be the same, the retried write will be ignored. If it had not occurred, the TID bit will be opposite, and the retried write to will be executed. 6.1.2 Table 6-3. DDR Errors DDR Errors Error Response This is detected through firmware during the calibration routine. Firmware should treat the DIMM as a repeater if it is an intermediate DIMM or map it out if it is the last DIMM in the chain if normal FBD interface comes up, should at least act like a repeater. Does not bring down FBD channel - like above. DDR cmds directed at DIMM will fail to return valid responses. Failure of software to achieve calibration DDR voltage does not power up 6.1.3 Host Protocol Errors AMBs are not expected to detect bad protocol from the host. Table 6-4. Host Protocol Errors Error Response AMB response to illegal command combinations is undefined Illegal combinations of commands • see Concurrent Command Delivery Rules section of the FBD Architecture and Protocol Specification Commands to multiple AMBs to return data in the same return frame. If multiple AMBs attempt to return data in the same frame, the host will see the data from the northern most AMB which is providing data, as it will replace any data sent from AMBs to its south. A host controller should not produce commands which would cause multiple AMBs to respond with data in the same frame. A special case can occur where Alert frames are being sent by one or more AMBs while another AMB is returning data from a command. These cases are discussed in the Architecture and Protocol spec in the Northbound Alert Frame section. Intel® 6400/6402 Advanced Memory Buffer Datasheet 73 Errors 6.1.4 Table 6-5. Other Errors Other Errors Error Response If OVERTEMP error type enabled in EMASK Register 1. The OVERTEMP bit will be set in the FERR or NERR register as appropriate 2. Error/Alert Asserted bit set in FBD Status 0 register If TEMPHIENABLE set in TEMPSTAT register also 3. Shut down DDR channel: • Drive CKE low to the DRAMs and float the command, address, and data signals. CKE, ODT, and clock continue to be driven. The clocks to the DRAMS may be stopped after the CKE has been registered low 4. The FBD interface goes to electrical idle, with the receivers shut off to reduce power. 5. The core will continue to be clocked, and the AMB will respond to SMBus commands. This allows the host controller to determine the error condition Note: No recovery expected, just trying to prevent Si meltdown The AMB will remain in this state until the temperature is below TEMPHI and the OVERTEMP bit is reset via SMBus or a hardware reset. Else ignore error Note: A hardware reset will place the TEMPHIENABLE bit in its default state of disabled. If INJCRC error type enabled in EMASK Register 1. No command executed 2. 120 bit Raw SB Frame captured in RECFBD Error Log Registers 3. Type of error logged in FERR/NERR registers 4. Error/Alert Asserted bit set in FBD Status 0 register 5. Ignore future commands except Soft Channel Reset until Soft Channel Reset or Link Reset Received 6. Alert Frame sent continuously starting with NB frame in which returned data pattern would be sent if aborted command had been a config read. Alert patterns continue until Soft Channel Reset or Link Fast Reset received. Else ignore error NOTE: this basically the same as a CRC error except that CRC is not actually corrupted Overtemp - Temp > TEMPHI and overtemp enabled Injected alert Injected error If INJERR error type enabled in EMASK Register 1. Type of error logged in FERR/NERR registers 2. Error/Alert Asserted bit set in FBD Status 0 register Else ignore error Reset should not be released if no REFCLK present.PLL will not achieve lock, the AMB will not come out of reset. No REFCLK 6.2 6.2.1 Error Logging Error Logging Procedure There are three basic types of errors in FBD: OverTemp, Alerts and Status Only Errors.The first occurrence of any type of unmasked error are flagged in the FERR register. Multiple bits can be set in this register if multiple errors occur in the same clock period. Subsequent errors are flagged in the NERR register. Unmasked “Alert” errors generate in-band link alert messages. All unmasked errors also set the error bit in FBDS0 that is returned in regularly scheduled in-band status response messages that occur following Sync commands. There are error data logs associated with some of the errors. Once the first “Alert” error has been flagged in the FERR or NERR (and matching SB frame data logged), the log registers for that error remain locked until either 1) all “Alert” error bits in the FERR and/or NERR are cleared, or 2) a power-up reset. Once the first Unimplemented 74 Intel® 6400/6402 Advanced Memory Buffer Datasheet Errors Configuration Register Access error has been flagged (and matching address logged), the log registers for that error remain locked until either 1) that bit in the FERR and/or NERR cleared or 2) a power-up reset. 6.3 Fail Over Mode Support The AMB supports single lane Fail Over mode as described in the FB DIMM Architecture and Protocol Specification,. This is done under host control or through the SMBus. 6.4 Failback to Pass-Thru In general, the AMB attempts to minimize the number of Single Points Of Failure (SPOF) that could bring down the entire channel. Errors in any one lane can be mapped out with Fail Over. Errors on the DDR interface can be handled by disabling the DRAM interface and leaving the AMB in a repeater like mode. The goal is to allow the system (following a reset or fast reset sequence) to work around the bad DIMM and keep the DIMMs downstream in operation until there is time for system maintenance. A AMB in an intermediate DIMM should continue to operate in pass-thru mode so that NB and SB data are relayed to the next links in the channel with minimal functionality. Only the following parts of the AMB need to be healthy to support this mode: • Clock inputs and PLL circuitry to generate FBD clocks • Minimal core logic around FBD I/O enabling and reset — Reset generation — Bit lock detection. • at least N-1 FBD lanes operational in NB and SB channels § Intel® 6400/6402 Advanced Memory Buffer Datasheet 75 Errors 76 Intel® 6400/6402 Advanced Memory Buffer Datasheet SMBus Interface 7 SMBus Interface The Intel 6400/6402 Advanced Memory Buffer (AMB) has configuration registers that provide flexibility and allow for testing and optimization of the chip. Upon system reset (RESET#), configuration registers are reset to predetermined default states, representing the minimum feature set required to successfully bring up a nominal channel. It is expected that the BIOS will properly determine and program the optimal configuration settings. For all of these registers, the AMB supports register access mechanisms through SMBus as well as through in-band channel commands. 7.1 System Management Access System Management software in the platform can initiate system management access to the configuration registers. This can be done through SMBus accesses. The mechanism for the Server Management (SM) software to access configuration registers is through a SMBus Specification, Rev. 2.0-compliant slave port. The AMB contain this slave port and allow access to the configuration registers. SMBus operations are made up of two major steps: (1) writing information to registers within each component and (2) reading configuration registers from each component. The following sections will describe the protocol for an SMBus master to access a AMB’s internal configuration registers. Refer to the SMBus Specification, Rev. 2.0 for the bus protocol, timings, and waveforms. 7.1.1 SMBus 2.0 Specification Compatibility The principal requirement from the SMBus 2.0 specification is support of the “high power” bus electrical specifications described in the layer 1 (Physical layer) chapter. For the simple register access requirements of FBD, no layer 2 (Link layer) or layer 3 (Network layer) extensions provided by the 2.0 specification are used. In particular, there is no support for Address Resolution Protocol (ARP) since FBD is using fixed addresses. Additionally, only a subset of the network packet protocols described in the specification are needed and these are described below. AMB’s are required to support read and write transactions without requiring clock stretching in order to simplify host controller requirements. For similar reasons, AMB’s should not master SMBus transactions in normal operation. 7.1.2 Supported SMBus Commands The AMB SMBus Rev. 2.0 slave ports support register reads and writes built out of the following SMBus primitive commands: The slave address for each primitive SMBus transaction are determined from the SA pins. • For normal FBD DIMMs: — Slave Address[6:3] = 4’b1011 — Slave Address[2:0] = SA[2:0] Intel® 6400/6402 Advanced Memory Buffer Datasheet 77 SMBus Interface • For repeaters or LAI AMBs: — Slave Address[6:3] = 4’b0011 — Slave Address[2:0] = SA[2:0] Each SMBus transaction has an 8-bit command driven by the master. The format for this command is illustrated in Table 7-1 below. Table 7-1. SMBus Command Encoding 7 6 5 4 3:2 Internal Command: 00 - Read DWord 01 - Write Byte 10 - Write Word 11 - Write DWord 1:0 SMBus Command: 00 - Byte 01 - Word 10 - Block 11 - Rsvd Begin End Rsvd PEC_en The Begin bit indicates the first transaction of a read or write sequence. The End bit indicates the last transaction of a read or write sequence. The PEC_en bit enables the 8-bit PEC generation and checking logic. The Internal Command field specifies the internal command to be issued by the SMBus slave logic. Note that the Internal Command must remain consistent (that is, not change) during a sequence that accesses a configuration register. Operation cannot be guaranteed if it is not consistent when the command setup sequence is done. The SMBus Command field specifies the SMBus command to be issued on the bus. This field is used as an indication of the length of transfer so the slave knows when to expect the PEC packet (if enabled). Reserved bits should be written to zero to preserve future compatibility. 7.1.3 FBD AMB Register Access Protocols Sequences of these basic commands will initiate internal accesses to the component’s configuration registers. Each configuration read or write first consists of an SMBus write sequence which initializes the register’s address. The term sequence is used since these variables may be written with a single block write or multiple word or byte writes. Once these parameters are initialized, the SMBus master can initiate a read sequence (which performs a configuration read) or a write sequence (which performs a configuration write). Table 7-2. SMBus Protocol Addressing Fields Address Field Name Reserved Dev Function Reg_Num[15:8] Reg_Num[7:0] Bits 7:0 4:0 2:0 7:0 7:0 Description Reserved - AMB may alias all these addresses to 00h Reserved - AMB may alias all these addresses to 00h Function Address Reserved - AMB may alias all these addresses to 00h Register Address within Function 78 Intel® 6400/6402 Advanced Memory Buffer Datasheet SMBus Interface 7.1.3.1 Configuration Register Read Protocol Configuration reads are accomplished through an SMBus write(s) and later followed by an SMBus read. The write sequence is used to initialize the Bus Number, Device, Function, and Register Number for the configuration access. The writing of this information can be accomplished through any combination of the supported SMBus write commands (Block, Word, or Byte). The Internal Command field for each write should specify Read DWord. After all the information is set up, the last write (End bit is set) initiates an internal configuration read. If an error occurs during the internal access, the last write command will receive a NACK. A status field indicates abnormal termination and contains status information such as target abort, master abort, and time-outs. The status field encoding is defined in the following table. Table 7-3. Status Field Encoding for SMBus Reads Bit 7 6 5 4 3:1 0 Reserved Reserved Reserved Internal Target Abort Reserved Successful Description Examples of configuration reads are illustrated below. All of these examples have PEC (Packet Error Code) enabled. If the master does not support PEC, then bit 4 of the command would be cleared and there would not be a PEC phase. For the definition of the diagram conventions below, refer to the SMBus Specification, Rev. 2.0. For SMBus read transactions, the last byte of data (or the PEC byte if enabled) is NACKed by the master to indicate the end of the transaction. For diagram compactness, “Register Number[]” is also sometimes referred to as “Reg Number” or “Reg Num”. Figure 7-1. S X011_XXX SMBus Configuration Read (Block Write / Block Read, PEC Enabled) WA Cmd = 11010010 A Byte Count = 4 A Reserved A Device/Function A Reg Number[15:8] A Reg Number [7:0] A PEC AP S Sr X011_XXX X011_XXX WA RA Cmd = 11010010 Byte Count = 5 A A Status A Data[31:24] A Data[23:16] A NP Data[15:8] A Data[7:0] A PEC The following example uses byte reads. Intel® 6400/6402 Advanced Memory Buffer Datasheet 79 SMBus Interface Figure 7-2. SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled) S S S S X011_XXX X011_XXX X011_XXX X011_XXX WA WA WA WA Cmd = 10010000 Cmd = 00010000 Cmd = 00010000 Cmd = 01010000 A A A A Reserved Device/Function Register[15:8] Register[7:0] A A A A PEC PEC PEC PEC AP AP AP AP S Sr X011_XXX X011_XXX X011_XXX X011_XXX X011_XXX X011_XXX X011_XXX X011_XXX X011_XXX X011_XXX WA RA WA RA WA RA WA RA WA RA Cmd = 10010000 Status Cmd = 00010000 Data[31:24] Cmd = 00010000 Data[23:16] Cmd = 00010000 Data[15:8] Cmd = 01010000 Data[7:0] A A A A A A A A A A PEC NP S Sr PEC NP S Sr PEC NP S Sr PEC NP S Sr PEC NP 7.1.3.2 Configuration Register Write Protocol Configuration writes are accomplished through a series of SMBus writes. As with configuration reads, a write sequence is first used to initialize the Bus Number, Device, Function, and Register Number for the configuration access. The writing of this information can be accomplished through any combination of the supported SMBus write commands (Block, Word or Byte). On SMBus, there is no concept of byte enables. Therefore, the Register Number written to the slave is assumed to be aligned to the length of the Internal Command. In other words, for a Write Byte internal command, the Register Number specifies the byte address. For a Write DWord internal command, the two least-significant bits of the Register Number are ignored. This is different from PCI where the byte enables are used to indicate the byte of interest. After all the information is set up, the SMBus master initiates one or more writes which sets up the data to be written. The final write (End bit is set) initiates an internal configuration write. If an error occurred, the SMBus interface NACKs the last write operation just before the stop bit. Examples of configuration writes are illustrated below. For the definition of the diagram conventions below, refer to the SMBus Specification, Rev. 2.0. Figure 7-3. SMBus Configuration Double Word Write (Block Write, PEC Enabled) S X011_XXX WA Cmd = 11011110 A Byte Count = 8 A Reserved A Device/Function A Reg Number[15:8] A Reg Number [7:0] A Data[31:24] A Data[23:16] A Data[16:8] A Data[7:0] A PEC AP 80 Intel® 6400/6402 Advanced Memory Buffer Datasheet SMBus Interface Figure 7-4. SMBus Configuration Double Word Write (Write Bytes, PEC Enabled) S S S S S S S S X 011_X X X X 011_X X X X 011_X X X X 011_X X X X 011_X X X X 011_X X X X 011_X X X X 011_X X X WA WA WA WA WA WA WA WA C m d = 10011100 C m d = 00011100 C m d = 00011100 C m d = 00011100 C m d = 00011100 C m d = 00011100 C m d = 00011100 C m d = 01011100 A A A A A A A A R eserved D evice/Function R egister[15:8] R egister[7:0] D ata[31:24] D ata[23:16] D ata[15:8] D ata[7:0] A A A A A A A A PEC PEC PEC PEC PEC PEC PEC PEC A A A A A A A A P P P P P P P P Figure 7-5. SMBus Configuration Word Write (Block Write, PEC Disabled) S X011_XXX WA Cmd = 11001010 A Byte Count = 6 A Reserved A Device/Function A Reg Number[15:8] A Reg Number [7:0] A Data[16:8] A Data[7:0] AP Figure 7-6. SMBus Configuration Byte Write (Write Bytes, PEC Disabled) S S S S S X 011_X XX X 011_X XX X 011_X XX X 011_X XX X 011_X XX WA WA WA WA WA C m d = 10000100 C m d = 00000100 C m d = 00000100 C m d = 00000100 C m d = 01000100 A A A A A R eserved D evice/Function R egister[15:8] R egister[7:0] D ata[7:0] A A A A A P P P P P 7.1.4 SMBus Error Handling The SMBus slave interface handles two types of errors: internal and PEC. These errors manifest as a Not-Acknowledge (NACK) for the read command (End bit is set). If an internal error occurs during a configuration write, the final write command receives a NACK just before the stop bit. If the master receives a NACK, the entire configuration transaction should be reattempted. If the master supports packet error checking (PEC) and the PEC_en bit in the command is set, then the PEC byte is checked in the slave interface. If the check indicates a failure, then the slave will NACK the PEC packet. 7.1.5 7.1.5.1 SMBus Resets SMBus Transactions During FBD Link Fast Reset When the FBD link transitions into Electrical Idle (disable state) from an active state, this causes a “fast” reset of all non-sticky registers in the AMB. SMB transactions underway during a “fast” reset will not complete normally. Intel® 6400/6402 Advanced Memory Buffer Datasheet 81 SMBus Interface This is not a problem since SMBus accesses are only required prior to initial link turn-on or for diagnostic access when a link can not be initialized. It is the host’s responsibility to monitor for SMBus transactions during a fast reset and retry these transactions when the link is stable. An interrupted transaction will result in the AMB as slave not properly acknowledging the Master. This protects write transactions. However, if a read transaction has proceeded to the point where the slave no longer acknowledges the master, read data can be lost when the SMBus state machine is reset. If PEC is enabled, this data loss will be detected as a PEC error. The host restricting usage of SMBus to when the link is idle or monitoring “fast resets” and retrying transactions that are interrupted is the safest SMBus access method. 7.1.5.2 SMBus Interface State Machine Reset The slave interface state machine can be reset by the master in two ways: • The master holds SCL low for 25 ms cumulative. Cumulative in this case means that all the “low time” for SCL is counted between the Start and Stop bit. If this totals 25 ms before reaching the Stop bit, the interface is reset. — Timing is set up to be: * 30 ms at DDR2-667 * 37.5 ms at DDR2-533 • The master holds SCL continuously high for 50 µs. — Timing is set up to be: * 60 µs at DDR2-667 * 75 µs at DDR2-533 7.1.5.3 SMBus Transactions During Hard Reset Since the configuration registers are affected by the reset pin, SMBus masters will NOT be able to access the internal registers while the system is reset. § 82 Intel® 6400/6402 Advanced Memory Buffer Datasheet Clocking 8 8.1 Clocking Intel 6400/6402 Advanced Memory Buffer (AMB) Clock Domains There are three main clock domains in the Intel 6400/6402 Advanced Memory Buffer (AMB). The FBD (Fully-Buffered DIMM) link domain is a 12x multiple of the core clock. The DDR data-rate domain is 2x the core clock. The core domain frequency equals the DDR command-rate, and is a 2x multiple of the external reference clock. The ratio between these domains remains fixed.The AMB logic in each domain is shown in Figure 8-1. Intel® 6400/6402 Advanced Memory Buffer Datasheet 83 Clocking Figure 8-1. AMB Clock Domains 10/17/03 Gold Block Diagram AMBBridge Block DIagram SOUTH NORTH 10x2 10x2 Southbound Data In Southbound Data Out Data Merge 2x CA DDR 1x DDR/Core 2x DDR + 2xbar Deskew Reference Clock 1x2 Re-Time Re-synch alignment PLL 1x Rd DDR 1x fixed/ HVM 4 phases of 6x FBD RefClk 10*12 demux Frame State and clks and control state PISO 10*12 Reset# Reset Control Link Init SM and Control mux Reset s SB Link CSR’s failover Init patterns IBIST/DFX TX LAI data CLR IBIST/DFX - RX SB LAI Buffer 2 deep x 120 LAI Match and Mask DRAM Cmd 4 D SET Q 4 DRAM Clock Q DRAM Clock # Command Decoder & CRC Check Cmd Out D 29 SET Q 29 DRAM Address / Command Copy 1 mux Thermal Sensor CLR Q DDR Link CSR’s Core Control: NB/SB Combined Init Reset control CSR chain control Internal debug control DDR State Controller DRAM Address / Command Copy 2 LAI data Data Out D SET Core CSR’s mux Q 36 deep Write Data FIFO CLR Q 72 + 18x2 DRAM Data / Strobe External MEMBIST DDR Calibration & DDR IOBIST/DFX Data In Q SET D Data CRC Gen & Read FIFO Sync & Idle Pattern Generator Init Patterns mux Link Init SM and Control NB Link CSR’s failover IBIST/DFX TX NB LAI Buffer 1 deep x 168 LAI data Q CLR IBIST/DFX RX 14*6*2 PISO LAI Controller alignment State and control Frame clks and state 14*12 demux Deskew 5 SMBus SMbus Controller Re-synch JTAG 5 JTAG Controller Re-Time Data Merge Northbound Data Out Northbound Data In 14x2 14x2 84 Intel® 6400/6402 Advanced Memory Buffer Datasheet Clocking 8.2 PLL Clocks The PLL receives a reference clock at 1/2X, where X is the DDR command frequency. The PLL generates the internal clocks shown below in Table 8-1. Table 8-1. PLL Clocks Clock DDRCA1X DDRCA2X DDR1X DDR2X DDR2X# DDRRD1X Notes This clock is unused in the AMB. It is still used for setting the alignment of the DDRCA2X clock within the PLL. Rising edge aligned to DDRCA1X. Also allows command/address bus to run at DDR data rate in LAI mode. Along with DDR2X and DDR2X#, used by DDRI/O cluster to generate DDR command clock, DDR DQS output, and DDR DQ output. This is also used as core clock. Rising edge aligned to DDR1X Inverted DDR2X Used by DDRI/O cluster to advance the DDR Read FIFO read-pointer. It is also by Northbound logic. This is driven by an independent divider and can be moved w.r.t to the core clock in 2UI increments to align it with the DDR data availability. This is a fixed clock at the same frequency as the core clock but is driven by a independent divider. Four phases of 6X clock. Provided to FBD Northbound, Southbound high-speed I/O clusters. These signals are connected by abutment. HVMCLK FBDCK (4) There are additional PLL modes used for testing and bring up. Details are in Section 8.9, “Additional Clock Modes” on page 87. 8.3 Reference Clock A low-jitter differential reference clock (REFCLK) is routed to the host and each DIMM from a common clock source on the system board. This reference clock uses HCSL (High-Speed Current Steering Logic) signaling and its detailed requirements are documented in the FB-DIMM Draft Specification: High Speed Differential P2P Link at 1.5V. The AMB uses the reference clock to generate internal buffer clocks and to generate the clocks to the DRAMs located on each DIMM. The frequency of the reference clocks (133 to 200 Mhz) is one half the frequency of the DRAM base clock (267 to 400 Mhz), that is, it is one half the command-rate of the DRAM devices located behind the AMB. For example, for DDR2 667 DRAM devices the reference clock frequency would be 167 MHz. The reference clock is the basis for the various Core, FBD and DDR internal clocks. It is a requirement for the FBD channel to operate in the presence of Spread Spectrum Clocking (SSC), which is commonly used to reduce EMI. The reference clocks for FBD have to meet a jitter specification. The reference clocks to the host and each DIMM are mesochronous, that is, they have an unknown but fixed phase relationship to each other or the memory channel. This simplifies PCB routing since no precise length matching is required. However an upper bound for the clock length mismatch is necessary since the maximum phase difference between the data sent out with the transmitter clock and the receiver clock needs to be limited in the presence of SSC. It is required that all the reference clocks for a given FBD channel originate from a single clock source, for example, a common clock synthesizer or clock oscillator, and travel through the same jitter spectrum modifying components (for example, PLL clock buffer) thereby ensuring that there is no frequency mismatch or frequency drift between FBD agents. Intel® 6400/6402 Advanced Memory Buffer Datasheet 85 Clocking The PLL will also operate with the REFCLK at 100 MHz during special transparent mode testing. Since there is no high speed link operation, there can be looser requirements for jitter and no SSC. 8.4 FBD Lane Frame Clocks Each FBD I/O lane also sources a frame clock at core frequency that is matched to the parallel data sourced by the lane. These are used during initialization to capture data in training sequences and to align data across the link. 8.5 Clock Ratios The core, DDR and FBD link clock domains are fixed in a 1:2:12 ratio. The SMBus asynchronous subsystem need not scale. The supported clock ratios are shown in Table 8-2. Table 8-2. AMB Clock Ratios FBD Link Data Rate 3.2 Gb/s 4.0 Gb/s DDR Data Rate 533 Mb/s 667 Mb/s Core Frequency 266 MHz 333 MHz Ref Clk 133 MHz 167 MHz FBD Link : Core 12 : 1 12 : 1 Core : DDR 1:2 1:2 8.6 DDR DRAM Clock Support The DDR command clocks (CLK[3:0], CLK[3:0])are generated by the AMB. They operate at 1X the core frequency for DDR2. The write strobes operate at the same frequency as the CLK/CLK signals. Write data and check bits are aligned to both the rising and falling edges of the write strobe. The source-synchronous read strobes operate at the same rates as the write strobes. Each read strobe will be individually aligned with its portion of the data and check-bits. 8.7 SMBus The SMBus clock is synchronized to the core clock. Data is driven into the AMB with respect to the serial clock signal. Data received on the data signal with respect to the clock signal will be synchronized to the core using a metastability hardened synchronizer guaranteeing an MTBF greater than 107 years. When inactive, the serial clock should be deasserted (High). The serial clock frequency is 100 kHz. 8.8 Table 8-3. Clock Pins Clock Pins (Sheet 1 of 2) Pin Name SCK SCK VCCAPLL VSSAPLL TCK AMB clock AMB clock (Complement) analog power supply for PLL analog ground for PLL TAP clock Pin Description 86 Intel® 6400/6402 Advanced Memory Buffer Datasheet Clocking Table 8-3. Clock Pins (Sheet 2 of 2) Pin Name SCL CKE[1:0]{A,B} CLK[3:0] CLK[3:0] DQS[17:0] DQS[17:0] SMBus clock DDR clock enables DDR clocks DDR clocks (Complements) DDR data/check-bit strobes DDR data/check-bit strobes (Complements) Pin Description 8.9 8.9.1 Additional Clock Modes Transparent Mode Clocking In transparent mode, all input signals are registered in the core clock domain and all outputs are driven from the output of registers clocked by core clock. In order to achieve determinism on a tester in this mode, the feedback clock for the PLL is taken from the end of the core clock tree. This makes all timing relative to the input reference clock. 8.10 8.10.1 PLL Requirements Jitter The FBD link clocks are produced by a PLL that multiplies the SCLK frequency. See the High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM Specification and the Circuit Architecture Specifications for the DDR, FBD and PLL custom I/Osfor more details. 8.10.2 PLL Bandwidth Requirements The PLL -3dB loop bandwidth shall be between fREFCLK/18 and fREFCLK/6 with a 3dB maximum peaking. See the High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM Specification and the Circuit Architecture Specifications for the DDR, FBD and PLL custom I/Osfor more details. 8.10.3 External Reference The PLL uses an external reference clock - described previously. See the High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM Specificationand the Circuit Architecture Specifications for the DDR, FBD and PLL custom I/Os for more details. Intel® 6400/6402 Advanced Memory Buffer Datasheet 87 Clocking 8.10.4 Spread Spectrum Support The AMB PLL will support Spread Spectrum Clocking (SSC). SSC is a frequency modulation technique for EMI reduction. Instead of maintaining a constant frequency, SSC modulates the clock frequency/period along a modulation profile.The AMB is designed to support a nominal modulation frequency of 30-33 kHz with a downspread of 0.5%. See the High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM Specification and the Circuit Architecture Specifications for the DDR, FBD and PLL custom I/Os for more details. 8.10.5 Frequency of Operation The PLL’s support a range of operation that exceeds the AMB’s functional range. This allows the AMB to be tested at a higher frequency than the maximum specification to provide test guardband. Lower frequencies are supported to allow system debug. The PLL will also operate with the REFCLK at 100 MHz during transparent mode testing. 8.10.6 RESET# The externally generated RESET# signal indicates when the core voltage is up and reference clocks are stable. The core will use an asserted RESET# to asynchronously put the AMB in reset, and to hold the AMB in reset. For details see the reset chapter. External clocks dependent on PLL’s are DDR clocks and strobes, and SMBus clock. 8.10.7 Other PLL Characteristics The PLL VCOs oscillate continually from power-up. At all other times, PLL output dividers track the VCO, providing pulses to the clock trees. Logic that does not receive an asynchronous reset can thus be reset “synchronously”. A “locked” PLL will only serve to prove that the feedback loop is continuous. It will not prove that the entire clock tree is continuous. The PLL is disabled for leakage test. 88 Intel® 6400/6402 Advanced Memory Buffer Datasheet Clocking 8.11 Analog Power Supply Pins The incorporates one PLL. This PLL requires an Analog VCC and Analog Vss pad. Therefore, there will be external LC filters for the AMB . Figure 8-2. FBD PLL Power Supply Filter VCC R1 1 2 4.7UH 0.4 0805 VCCA VCCA VCCA bump Connected to PLL Circuitry L1 pin Package Routing C1 10UF 6.3V 0805 C2 10UF 6.3V 0805 VSSA VSSA VSS bump Connection in Metal 6 Package Routing pin VSSA bump Board Package Die Separate filtered power pins are available for use by a PLL if needed. Warning: The filters are NOT to be connected to board Vss. The ground connection of the filters will be routed through the package and grounded to on-die Vss. § Intel® 6400/6402 Advanced Memory Buffer Datasheet 89 Clocking 90 Intel® 6400/6402 Advanced Memory Buffer Datasheet Reset 9 Reset This chapter describes aspects of hardware reset specific to the Intel 6400/6402 Advanced Memory Buffer (AMB). 9.1 Platform Reset Functionality The FBD channel provides a RESET# signal to initialize all AMBs on the channel. The generation of this signal is platform dependent, and may be asynchronous to the clock. The platform will assert RESET# at power up. This signal may be asserted at other times, such as a warm boot. It is possible that platform conditions cause RESET# to be asserted at any time, including in the middle of DRAM commands. This could occur during a warm boot. Under these conditions, the AMB will be reset and the contents of memory are not guaranteed. The state of the DRAMs must be guaranteed when reinitialized for proper response. 9.1.1 Platform RESET# Requirements • RESET# must be asserted at power up, and may also be asserted at other times such as a warm boot. Asserting RESET# at warm boot will clear all error logging registers.Asserting RESET# only at power up will allow error logging registers to be maintained through a warm boot cycle. • Asserting RESET# at warm boot will clear all error logging registers. There is no need to delay or lockout RESET# going to the FBD channel since the AMB will guarantee that the tDelay parameter is met. Reference Clocks must remain stable for at least 4 clock cycles after RESET# is asserted in order to allow the AMB to satisfy the tDelay requirement. • RESET# must be asserted during power up, and for a minimum of 1 mS after the FBD channel power and reference clocks SCK/SCK are stable. • RESET# must be asserted for a minimum of 100 uS. This will only apply if RESET# is re-asserted while power and clocks remain stable. • After initial power on, if the reference clock frequency is changed while Reset is asserted, reset must not be deasserted until power and reference clocks SCK/SCK have been stable for at least 1 ms. 9.1.2 RESET# Requirements RESET# is asynchronously applied to all storage elements. Assertion of RESET# does not effect AMB PLL operation. Internal clocks continue to run. Upon assertion of RESET#: • DRAM CKE is driven low asynchronously with minimal delay (within 1 clock, asynch path from reset to CKE). • DRAM CLK/CLK continue to run with no short pulses generated within the tDelay period specified in JEDEC ballot 1410.01. • DRAM CLK/CLK may be stopped after the tDelay has been satisfied. Intel® 6400/6402 Advanced Memory Buffer Datasheet 91 Reset • All internal register bits are set to their default values, including any error logging bits that are normally not reset by the channel reset. • The initialization FSM is put into the disable state. All internal state machines are put in their default state. • All southbound and northbound Tx outputs are put into electrical idle (EI) mode. All Tx outputs stay in EI mode until the appropriate initialization state after deassertion of RESET#. 9.1.3 Power-Up and Suspend-to-RAM Considerations In a suspend to RAM environment the DRAMs are put into self-refresh mode, and the FBD channel power may be removed. The DRAM power supply remains active. This supply is used by the AMB DRAM interface I/O circuits. The AMB must keep the CKE pins low, without glitches through this transition. RESET# should be asserted before channel power goes away when entering S3. DDR control and clock signals will be pulled low during initial power up. This may be done with a voltage detection circuit. CKE must be maintained low during this time without glitches to prevent the DRAMs from exiting self refresh mode. The RESET# signal will remain low during the power-up sequence, for at least 1mS after power and clocks are stable. The CKE signals must remain low until a command is received that takes the CKE signals high. This could be an exit self refresh command, or any of the DRAM CKE commands. 9.2 Reset Types Types of reset: • Hard resets occur when the RESET# signal is low. This usually occurs at power up. • Fast resets occur when there is a reset event on the primary southbound FBD Link. • SMBus resets affect only the SMBus interface. 9.3 Pads Controlling Reset The AMB resets are controlled by the RESET# pad and the primary southbound FBD link pads. The RESET# pad resets the chip at power up. When the primary southbound FBD link pads indicate EI, a fast reset is started. 9.3.1 RESET# Pad The low true RESET# pad is controlled by the platform which holds it low until after power and SCK/SCK are stable. RESET# asynchronously resets most of the chip to a safe initial state. The PLLs and TAP are not reset.When RESET# goes high, logic running on REFCLK waits an appropriate amount of time and then resets the core. Logic running on REFCLK is reset by RESET# directly. As the chip comes out of reset, the Primary South FBD Link is expected to be in a reset state. As the link sequences through the first initialization sequence after power up, the AMB will not generate any DRAM commands other than to maintain CKE low and enable DRAM clocks at the appropriate time. 92 Intel® 6400/6402 Advanced Memory Buffer Datasheet Reset 9.3.2 Primary FBD Link When an EI occurs on the primary southbound FBD link a fast reset is started. This starts a handshake procedure putting the DRAMs into self-refresh mode and resetting the AMB. Fast reset does not reset the PLL, sticky flops, and sticky configuration registers. 9.4 9.4.1 Details Reset details and sequences will be released in a future revision of this document. Cold Power-Up Reset Sequence 1. 1.5 V, 1.8 V and 3.3 V power supplies comes up • RESET# asserted low while power supplies are coming up • CKE’s are low upon 1.8 V power up 2. BIOS queries SPD on all the FBDs on the channel to determine operating conditions — channel frequency, compatible DIMMs, DRAM and AMB parameters 3. Clocks up and stable at required frequency • Reference Clocks (SCK/SCK) should be stable at least 1ms before RESET# deasserted for designs with PLL running independent of RESET# • DRAM clocks (CLK/CLK) may be toggling at this time 4. RESET# deasserted high • CKE’s to DRAMs remain low 5. No transactions for at least 200 us after RESET# deasserted for designs with PLL’s tied to RESET# • No SMBus or in-band activity during this period • DRAM clocks should be stable at this time 6. AMB parameters critical for robust link initialization are programmed via SMBus • Architected link registers — LINKPARNXT: link frequency - Note: some AMBs may use this write to trigger PLL init — FBDSBCFGNXT: SB transmitter drive strength, de-emphasis setting and passthru mode — FBDNBCFGNXT:NB transmitter drive strength, de-emphasis setting and passthru mode — FBDBLTO:if NB lanes are to be deconfigured • Personality Bytes from SPD needed for link initialization — PERSBYTE[5:0]NXT: In the AMB, these match: — SPDPAR01NXT: various FBD IO implementation specific controls — SPDPAR23NXT:various FBD IO implementation specific controls — SPDPAR45NXT — remaining Personality bytes are not required for link init and may be loaded over the high speed FBD configuration register accesses Intel® 6400/6402 Advanced Memory Buffer Datasheet 93 Reset • These “Next” register values must be transferred to the matching “Current” registers before the FBD link leaves the DISABLE state — Updates may be done right after the NXT register is updated when link is in electrical idle. Updates must be complete before the beginning of training. 7. FBD Link is initialized including CALIBRATION state. 8. Remaining AMB configuration is loaded over high speed FBD channel • CMD2DATA, remaining personality bytes, other SPD parameters, DRAM parameters, Errors enabled, and so forth. 9. FBD Link goes through fast reset (no CALIBRATION) to establish the desired configuration 10. DRAM interface can now be established a. b. c. d. MRS/EMRS setup using DCALCSR and DCALADDR DRAM interface calibrated using DCALCSR Optionally, MemBIST functionality can be used to test the DRAMs DRAM’s can be initialized using MemBIST 11. Refresh must now be transferred to the host • Option 1: Use fast reset on the link with DRAMs in self-refresh — clear DSREFTC:DISSREXIT to enable fast self refresh exit when link is reestablished — put the link in disable state which automatically puts the DRAMs in self refresh. — Start the refresh engine on the host — bring up the link again — Host starts sending refresh commands as soon as L0 state reached • Option 2: write control register to disable auto-refresh engine followed by — Clear DAREFTC:AREFEN to turn off auto-refresh — Host then immediately takes over sending refresh commands 12. Host now has complete control of the FBD Channel 9.4.2 S3 Restore Power-Up Reset Sequence Follow steps 1) through 9) from cold power up sequence above. Step 2, BIOS query of SPD may be skipped if these values are saved elsewhere. Either way the personality bytes from the SPD are restored to their prior values in the AMB. Once this is done the DRAM interface can be restored. 1. DRAM interface can now be restored a. b. DRC, MTR, DSREFTC, and DAREFTC register restored Stored S3RESTORE[15:0] are written back into each AMB — do NOT recalibrate the DRAM interface using DCALCSR — do NOT reinitialize the DRAMs using MemBIST 2. Refresh must now be transferred to the host as in cold power up 3. Host now has complete control of the FBD Channel and prior DRAM memory state has been preserved. 94 Intel® 6400/6402 Advanced Memory Buffer Datasheet Reset 9.4.2.1 Implementation Detail 1. The RESET# pad starts out low. This asynchronously asserts all internal resets. 2. After power comes up and REFCLK stabilizes, the PLLs start generating clocks. At this time, the phase relations between the clocks are not guarantied to be correct. 3. RESET# rises. A synchronized version releases the reset on the logic running on REFCLK. The chip monitors RESET# for 100 and 200 usec RESET# must remain stable during this time. If it falls the wait starts again until a stable high occurs. 4. After a stable RESET# high is detected, the PLL is reset to bring the generated clocks into correct alignment with themselves. 5. At this point the chip waits for the PLL to indicate reset complete. When it does, the internal resets are deasserted for all clock domains except TCK. 9.4.3 Reset Sequence for a Fast Reset Figure 9-1 below shows a fast reset sequence. Important steps are described below: • The chip is running with the RESET# high and a full link initialization sequence has been completed at least once. • A electrical idle is detected on the primary Southbound FBD Link. • If not the last DIMM, forward electrical idle Southbound to the next DIMM. • Drive logic “0’s” on Northbound transmitters. • The AMB completes the fast reset handshake (see below). • Reset is asserted for all non-sticky registers. • The values in the next fields are transferred to the Current fields. • The PLL remains in lock but the clock outputs are reset, causing them to realign. • IF not the last DIMM, the AMB waits for an electrical idle to appear on the secondary Northbound FBD link. • Forward electrical idle Northbound • The chip is released from reset. • Freezing sticky configuration registers through reset 9.4.4 Fast Reset Handshake When a reset event is detected on the primary Southbound FBD link, the AMB does the following: • Immediately stops accepting new DRAM commands from the link. • Halts all on-chip algorithms, including DRAM cal and MemBIST. • Waits 200 ns for any in-process DRAM commands to complete. • Asserts CKE high. • Waits 200 ns for DRAM self-refresh exit to complete. • Sends a DRAM precharge all to all ranks. • Waits 30 ns for precharge all to complete. • Sends DRAM self-refresh entry commands to all ranks . Intel® 6400/6402 Advanced Memory Buffer Datasheet 95 Reset 9.4.5 Figure 9-1. Timing Diagrams Cold Power-Up Reset A M B C old Pow er-U p R eset Sequence Inputs to AM B 1.8 V supply 1.5, 3.3 V supplies R ef clk A t least 2 m sec Stable RE SET# A t least 200 usec SM Bus FB D link Q uiet D isabled Pgm phys link regs Link init and cal AM B config EI Link init Bring up DRAM ifc O utputs from AM B CKE D R A M clk Stable N xt C ur updated by this tim e Inputs: value irrelevant . O utputs: value unknow n Figure 9-2. AMB Fast Reset Sequence AMB Fast Reset Sequence (DISSREXIT not Set) Inputs to AMB Power supplies and Ref clk stable RESET# high P rimary SB FBD Secondary NB FBD L0 L0 EI 0's EI Nxt C ur updated by this time TS1 TS2 TS3 TS0 TS0 L0 TS3 TS1 TS2 L0 Outputs from AMB S econdary SB FBD L0 EI TS0 TS1 TS2 TS3 L0 P rimary NB FBD L0 0's Precharge All & AutoRefresh EI TS0 TS1 TS2 TS3 L0 DRAM Commands CKE DRAM clks on-going SRF Exit SRF Entry SRF Exit Stable May change Stable Internal Signals Non-Sticky Reset 0001 96 Intel® 6400/6402 Advanced Memory Buffer Datasheet Reset 9.5 9.5.1 I/O Initialization FBD Channel Initialization Channel initialization states and uses of fast reset are described in the FB-DIMM Architecture and Protocol Specification. 9.5.2 DDR Analog compensation commences at power-up. It’s completed by “RESET#” deassertion. After the FBD link reaches L0 state, setting the DRC.CKEN configuration bit enables CKE.The DDR interface is now ready for calibration. § Intel® 6400/6402 Advanced Memory Buffer Datasheet 97 Reset 98 Intel® 6400/6402 Advanced Memory Buffer Datasheet Transparent Mode 10 Transparent Mode Figure 10-1 shows the typical architecture of a DRAM with a 4 bit wide data path. The memory array operates at 100 to 200 MHz. With a pre-fetch of 4, there are 4 bits of data on each array access, allowing us to clock data in or out at 400 MHz. This 4 to 1 multiplexing and de-multiplexing is performed in the input register or output multiplexer. Figure 10-1. DRAM Architecture 10.1 Transparent Mode Refer to the JEDEC publication: FB-DIMM Draft Specification: Design for Test, Design for Validation (DFx) Specification for information regarding transparent mode. Transparent mode is designed to allow access to the DRAM behind the AMB. In this mode high speed pins are converted into low speed pins and mapped to DRAM pins. The objective is to allow the use of existing test equipment and manufacturing processes. The tester must be capable of operation at 200 MHz. Transparent mode offers potential improvements in test capacity over traditional DIMMs. In this mode, FBD requires only 60 active pins to test the DIMM. Intel® 6400/6402 Advanced Memory Buffer Datasheet 99 Transparent Mode Data from the tester is 16 bits wide at 200 MHz (single data rate). The data rate is doubled and the width halved on the way to the DRAM (by clocking out 8 bits of data on the rising edge of the clock and the remaining 8 bits on the falling edge). The tester will drive data to be written to the DRAM on a write pass and data to be compared on a read. DRAM data and the expected data from the tester is compared in the AMB. If the actual and expected data differ the pass/fail outputs will indicate which DRAM failed. 10.1.1 Block Diagram The data paths for transparent mode will bypass all link logic and normal DRAM control logic. The DDR interfaces are used intact. Figure 10-2 is a block diagram of the Intel 6400/6402 Advanced Memory Buffer (AMB) in transparent mode. Figure 10-2. Block Diagram for the AMB in transparent mode TCMD/TADD D SET Q D SET Q DRAM CMD/ADD CLR Q CLR Q TDRV D SET Q Shift Register Controlled by AMB CL, AL or hard coded for WL=3 Multiplexer CLR Q D SET ENB Q CLR Q TDQ D SET Q 16 CLR S1 S2 D 144 Q DFTDATA C ENB D SET ENB Q CLR Q DRAMWR DRAM DQ DRAM DQS Multiplexer Status Q SET D D 16 S1 S2 ENB C Q DDR IO Read Data FIFO Q SET D CLR Q CLR ENDOUT, DRAMRD Read Pointer TCMP D SET Q Shift Register Controlled by AMB CL, AL, CMD2DATA or hard coded to RL=4 and CMD2DATA=4 ENB CLR Q 10.1.2 Transparent Mode Signal Definitions When the transparent mode is enabled. The FBD (Fully-Buffered DIMM) differential input pins designed in the AMB part become two single ended inputs. In transparent mode the FBD input pins require 0 to 500 mV swing (half of the normal differential input voltage). Input slew rates should be approximately 5 V/ns. This parameter is not critical, but it must be fast enough to be recognized by the AMB receiver. The DDR pins will operate with normal DDR2 timings and levels. The AMB clock input pins will be used for transparent mode as well as normal mode. This also allows use of most of the existing on-chip clock distribution network. 100 Intel® 6400/6402 Advanced Memory Buffer Datasheet Transparent Mode Table 10-1. Additional Signals in Transparent Mode Transparent Mode Signal Name TCKE[1:0] TCS#[1:0] TODT TRAS# TCAS# TWE# TBA[2:0] TA[14:0] TDRV TCMP TDQ[15:8] TDQ[7:0] TPF[8:0] or TDQO[15:0] Sum of receivers Sum of drivers Pin Count 2 2 1 1 1 1 3 15 1 1 8 8 9 or 16 44 16 Frequency 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz Direction In In In In In In In In In In In In Out Tester signal to drive data on writes Tester signal to compare on reads Early data to each byte Late data to each byte Used for pass/fail (8:0) or direct access (15:0) Controls WE{A,B} Controls both ODT[1:0]{A,B} Definition Controls CKE[1:0]{A,B} 10.1.3 Transparent Mode to FBD Pin Mapping The FBD pin mapping is shown in Table 10-2. Table 10-2. Mapping of FBD Pins in Transparent Mode FBD Pin Name SN[0], SN[0] SN[1], SN[1] SN[2], SN[2] SN[3], SN[3] SN[4], SN[4] SN[5] SN[13:6], SN[13:6] PS[8] PS[8] PS[7:0] PS[7:0] SS[8:0] PN[13:7], SS[8:0] Total Pins Count 2 2 1 1 1 1 3 16 1 1 8 8 9 16 Speed 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz Transparent Mode Signal Name TCKE[1:0] TCS#[1:0] TODT TRAS# TCAS# TWE# TBA[2:0] TA[15:0] TDRV TCMP TDQ[15:8] TDQ[7:0] TPF[8:0] TDQO[15:0] Early data Late data Pass/Fail mode (TRANSCFG.ENDOUT =0) Data output mode (TRANSCFG.ENDOUT =1) Comment Intel® 6400/6402 Advanced Memory Buffer Datasheet 101 Transparent Mode 10.2 10.2.1 Transparent Mode Timing Clock Frequency and Core Timing The DDR2 DRAM clock frequency is 200 to 400 MHz but core timings require several clocks (or nS) to complete. For example on DDR2 667: • tCL, tRP and tRCD are 4 clocks or 12 ns • tRC is 57 ns • tRRD is 7.5 ns DDR2 transactions are burst-oriented, reading or writing 4 or 8 words of data across 4 or 8 clock edges. Assuming a 4 bit burst, a x8 DRAM will transfer 32 bits on successive edges of 2 DRAM clock cycles. On the tester side of the interface the same 32 bits of data is transferred, 16 bits at a time, over two DRAM cycles. 10.2.2 Edge Placement Accuracy Command, address and data edges should be reasonably close to the appropriate clock edge but with some margin of error. DRAM setup and hold times are 400 to 600 pS, while the half cycle time is at least 1250 pS. As long as the data is within 625 pS of the clock edge it will not violate setup or hold. Since there will be other error terms (DIMM trace length matching, jitter, and so forth) it is recommended the tester be accurate to ±300 pS. During Transparent mode testing, the core clock is tied to the input reference clock by selecting a special mode in the PLL. Normally, the PLL uses an internal feedback loop for maintaining lock. In this special mode, the end of the core clock tree is fed back as the feedback clock to the PLL. This makes driving and receiving data at the pins of the chip deterministic with respect to the reference clock. This feedback mode for the PLL can be selected automatically in Transparent Mode. 10.2.3 Transparent Mode Timing Normally, transparent mode will use DDR2-400 timing even if the DRAM is rated for faster operation. Optionally an AMB may support operation at frequencies higher than 200 MHz. To set up transparent mode the appropriate AMB registers should be set to AL=0, CL=4 and CMD2DATA=4. Some AMBs may default to these values, in which case programming has no effect. These values establish an internal timing relationship as illustrated in the following figures. Optionally other register values may be supported for special test cases. Actual placement of DRAM read/write or other commands is dependent on the incoming signals, not the AMB register values. Figure shows an example of a write, read, write sequence using incoming signals that correspond to WL=4 and RL=5. The timing relationships in red (normal font) are fixed relationships (established by the AMB register settings above). These edges will move together. The relationships in green (italic font) are the DRAM timings, which are under control of the tester. 102 Intel® 6400/6402 Advanced Memory Buffer Datasheet Transparent Mode Timing may be changed on the fly (for example, in the middle of a test pattern) by changing the placement of edges from the tester. DRAM mode registers can be programmed on the fly as needed by including (E)MRS commands in the tester data stream. There is no need to change AMB settings during a test. The only exception is that DRAM BL may be changed on the fly but the data logging logic may get confused if DRAM BL does not match the BL expected by the data logger. All other DRAM settings such as AL and CL may be changed at any time. Figure 10-1. Transparent Mode Timing 10.2.3.1 Write Timing Figure 10-2 illustrates write timing with the tester set to WL=3, 4, and 5. There is a constant offset of three cycles from TDRV to TDQ and one cycle from TDQ to DRAM DQ. The DRAM mode registers must, of course, be set to the appropriate timing to recognize the read. For BL=8 the TDRV pulse will be 4 clocks wide rather than 2. 10.2.3.2 Extended Write Timing The TDRV pulse may be extended indefinitely in cases where it is necessary to apply constant data to the DRAM pins. As long as TDRV remains asserted the AMB will continuously propagate data from the tester TDQ inputs through to the DRAM DQ pins (delayed by 1 cycle) as indicated below. Intel® 6400/6402 Advanced Memory Buffer Datasheet 103 Transparent Mode Figure 10-2. Transparent Mode Write Timing 10.2.3.3 Read Timing Figure 10-3 shows read timing with the tester set to RL=3 and RL=5. Due to complexities in the handling of read data in an AMB there is a latency of several cycles from the TDRV pulse to TDQ and test status outputs. Specifically there is a constant latency of four cycles plus the programmed CMD2DATA value from TDRV to TDQ (8 cycles total using the AMB settings above) and one cycle from TDQ to DRAM DQ. An AMB may support shorter latencies but this is not required. TCMP is latched on the rising edge of core clock. This initiates the read inside the AMB. In most cases the AMB will latch DRAM read data slightly before TDQ data is needed. The reason is most AMBs will load DDR data into a queue in the DRAM domain and unload the data on a core clock edge. TDQ is typically not needed until the DRAM data is in the core. The comparison of actual and expected data and propagation back to the tester will occur on the next core clock edge. The timings below are for BL=4. When testing BL=8 the TCMP pulse should be 3 clocks wide rather than 1. Tester DQ data, DRAM data and the status outputs will be extended appropriately to cover the burst length. 104 Intel® 6400/6402 Advanced Memory Buffer Datasheet Transparent Mode Figure 10-3. Transparent Mode Read Timing Figure 10-4. BL=8 Read Timing Intel® 6400/6402 Advanced Memory Buffer Datasheet 105 Transparent Mode 10.2.4 Error Reporting By default the status pins will be the xor of actual data from the DRAM and expected data from the tester. The AMB also stores 144 bits of DQ data. If the LGFBITS control bit is cleared the 144 bits of data will be actual data read from the DRAM. Otherwise the result of the data compare is stored. In either case the tester must still provide expected data for the AMB to properly set the status pins. Normally the test will stop when an error occurs. It is the responsibility of the tester or test program to track errors, read error registers and stop or continue as appropriate. This may require multiple iterations of the same test to execute, collect data and restart the test. 10.2.4.1 Multiple Failures There are some implications if multiple failures occur in the same DRAM burst. Three control register bits determine how these failures should be captured. If the log first fail (lgffail) bit is zero (default) the AMB will record only the last failure in a burst. When the bit is set the AMB will record the first failure at the burst position matching the burst position (bstpos) setting. If the bit is set and an error is logged, no further logging will occur until the bit is cleared. a) If a failure is detected only in one half of the burst (first and second or third and fourth data words), the error pins will indicate which DRAM or DRAMs failed. The error register will indicate which data lines failed and in which data words. b) If a failure is detected in both halves of the burst (data word 1 or 2 and words 3 or 4), data from the second failure would overwrite data from the first failure. By default this is prevented by the log fail bit. The error pins will continue to operate correctly. If it is desired to collect data from a specific portion of the burst the burst position bits can be used to select an appropriate burst position to record. For a 4 bit burst it is possible to select data from the first or second half of the burst. For an 8 bit burst there are four positions to choose from. These mappings are illustrated in the following figure. Table 10-3. Mapping of Burst Position Bits to Error Capture Log First Fail Bit0 0 1 1 Burst Position Bit1 x 0 0 Bit0 x 0 1 1 144 bits* 144 bits 144 bits 2 BL=4 3 4 or 144 bits* Log First Fail Bit0 0 1 Burst Position Bit1 x 0 Bit0 x 0 1 144 bits* 144 bits 2 3 4 BL=8 5 6 7 8 or 144 bits* or 144 bits* or 144 bits* 1 1 1 0 1 1 1 0 1 144 bits 144 bits 144 bits * The last failure will be saved in whatever burst position it occurs. 106 Intel® 6400/6402 Advanced Memory Buffer Datasheet Transparent Mode 10.2.4.2 Direct Access - Testing of Individual DRAMs In certain cases it is desirable to test one or two DRAMs. Transparent mode allows direct access to a single x8 or two x4 DRAMs. In this mode 8 DDR DQ pins are demultiplexed onto 16 SDR status pins, providing16 bit input data path (on TDQ) and a 16 bit output data path on the status pins. The transparent mode configuration register has one bit (ENDOUT) to enable this mode. On reads, the DRAMRD bits will select the bytes of DRAM data to be presented on the status pins. On writes the DRAMWR bits select a DRAM to receive data from the TDQ bus. A separate register holds 8 bits of default data to be applied to non-selected DRAMs in the early/even cycles and another 8 bits for late/odd cycles. The mapping of these bits to DQ selection is illustrated in the following table. Table 10-4. Selection of 8 bit Data Paths When ENDOUT is Set Early Data DQ Byte Late Data DQ Byte DRAM RD/WR 0xF (DRAM WR only) 8 7 6 5 4 3 2 1 0 DQ All Bytes 71:64 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 DRAMWR is the byte of data bus selected to receive transparent write data, and byte of data bus to be compared against transparent read data. DRAMWR allows a setting of 0xF (all ones) which sends the TDQ input data to all DQ bytes. DRAMRD is the byte of data bus selected to be output on transparent data/status pins when ENDOUT bit is set. 10.2.5 Transparent Mode IO Specifications Listed below are the specifcations for transparent mode input and output pins. Table 10-5. Transparent Mode FB-DIMM Interface Signaling Specifications (Sheet 1 of 2) Minimum I/O voltage swing Input slew rate Input to refclk (rising or falling edges) setup time Input to refclk (rising or falling edges) hold time Status output valid to refclk time Vref Vil (DC) Vil (AC) Vih (DC) 0 2 3000 1000 -1000 200 -300 -300 300 +1000 300 200 150 900 Maximum 500 mV V/ns ps ps ps mV mV mV mV Units Intel® 6400/6402 Advanced Memory Buffer Datasheet 107 Transparent Mode Table 10-5. Transparent Mode FB-DIMM Interface Signaling Specifications (Sheet 2 of 2) Minimum Vih (AC) Voh Vol Ioh Iol 8 12 350 400 100 Maximum 900 mV mV mV mA mA Units Note: 1. Ioh: current into a 50-ohm external load to ground, with on-die transmitter termination enabled 2. Iol: current into a 50-ohm external load to 1.5 V supply rail, with on-die transmitter termination enabled 10.2.6 10.2.6.1 IO Implementation Guidelines Dedicated Receivers Simple one-stage receivers for the transparent mode have been added in parallel to the existing high-speed sampling receivers. The latter can be turned off during transparent mode, as well as the DRC and the phase interpolator, to save power and avoid noise. An internal VREF set to 0.25 V will be used, so the tester signals should oscillate between 0 and 0.5 V. The transparent mode RX should be turned off during normal mode, so as to save power/avoid noise. 10.2.6.2 Common Clock Scheme To avoid costly implementations using strobes and FIFOs, a common clock scheme is followed, implemented in the core, where the data capture flops reside. Since transparent mode data signals from the tester are all in phase with the 100 MHz system clock, the clock used for the capture flops has to be aligned with the external system clock (or slightly delayed, to account for the propagation delay difference between data receivers and clock receiver). Aligning core clock and external clock can be done using the HVM mode circuitry included in the PLL. The HVM clock tree will have to feed the capture flops, and one of its leaves has to be fed back to the PLL, in order to achieve adequate synchronization. 10.2.6.3 Tester Interface Clock and Data Routing The following uncertainties have to be factored in: • Tester board (TIU) trace mismatches • Package trace mismatches • FBD low speed RX propagation delay variations due to PVT • Set up and hold of capture flops (typically 1 ns. The tester should have 50 ohm terminations to ground for all TX pins in use (on-tester termination can be used where applicable). The tester should enable 50 ohm terminations to ground for all the signals sent to RX pins. This will guarantee reasonable signal integrity. 10.3 Transparent Mode Control and Status Registers In transparent mode, CSRs will be accessed and programmed through SMBus. See Section 14.3.5, ‚ “Hardware Configuration Registers,” for register descriptions. § Intel® 6400/6402 Advanced Memory Buffer Datasheet 109 Transparent Mode 110 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST 11 11.1 DDR MemBIST MemBIST Overview The Intel 6400/6402 Advanced Memory Buffer (AMB) supports memory built-in self test (MemBIST) for memory initialization during system boot up and for testing the installed memory. During DIMM manufacturing, MemBIST may be used to apply tests at speed to test the AMB-to-DRAM interface. Table 11-1 below lists the features provided by MemBIST. At the system level, MemBIST may be executed on multiple DIMMs simultaneously. This could be used to speed memory test during system boot. During DIMM manufacturing, MemBIST offers a fast method to detect FBD assemblyrelated defects, interface defects and the majority of memory-core-related defects. This testing may be done through commands initiated across the FBD channel (in-band test initiation) or through SMBus or JTAG commands (out-of-band test initiation), making MemBIST compatible with motherboards, low cost ATE, or standalone equipment such as continuity testers. To perform in-band testing on a motherboard, the motherboard must contain an FBD-based memory subsystem. MemBIST is primarily intended to test the AMB-to-DRAM interface and not the DRAM core. It is expected that transparent mode will be used to test the core logic in DRAMs already installed on DIMMs. For this reason, MemBIST includes primarily those features needed for interface testing. MemBIST does not include all features needed for DRAM core testing. Traditional system test methods are expected to be used for operating system or application-based testing of the memory subsystem. This may include existing memory stress tests, applications or other tests selected by the DIMM manufacturer. DDR interface testing requires stress of the AMB DDR I/O circuitry and the DDR I/O-tocore path in the DRAM. The test needs to be able to detect static faults (such as stuck signals) as well as dynamic faults (for example, slow timing paths) in the logic. Testing this logic requires: • Delivering patterns at full speed (667 MT/S). • Incrementing and decrementing addresses. The address decoders are best tested with marching or other non-linear patterns. • Alternating data patterns (single rotating bits, checkerboards) to detect slow nodes or capacitive coupling in the data path. • Using standard interface timing (nominal clock cycle time, setup, hold, pre and post-amble). • Verifying ODT operation at speed To accomplish the required testing, MemBIST has a number of modes of operation and data formats which can be chosen to meet the specific need. In addition, MemBIST supports a variety of DRAM timings and densities. A fundamental feature of the MemBIST architecture is that, unlike transparent mode, which simply replicates 8 bits of data across the DQ bus, MemBIST can control individual bits in the 72 bit DQ bus. In addition, MemBIST can apply test patterns at a rate as high as the DRAM address rate. To accomplish this, the MemBIST architecture Intel® 6400/6402 Advanced Memory Buffer Datasheet 111 DDR MemBIST provides two 72 bit words, or 144 bits of test data for each DRAM clock cycle. The data is supplied to the DRAMs on “early” and “late” phases of the DDR clock cycle. Early data is provided on the rising edge of CK. Late data is provided one half cycle later on the falling edge of CK. DRAM compare data is treated in a similar manner with appropriate clock alignment. 11.2 MemBIST Feature Summary Table 11-1 lists the features of MemBIST in summary form. Each feature is explained in subsequent sections. The registers used to control these features are detailed in the MemBIST register section. Table 11-1. MemBIST Feature Summary (Sheet 1 of 2) Feature Memory Address Control Address pattern in tests User defined start and end physical address Fast X, Fast Y, Fast XY, XZY address modes Choice of incrementing or decrementing addresses Dynamic address inversion (DAI) inverts alternate addresses X (row) address bits Y (column) address bits Z (bank) address bits Data Patterns Static data patterns fixed nibble data patterns (0, 3, 5, 6, 9, A, C, F) 144-bit user-defined data pattern 288-bit user-defined data pattern Dynamic data patterns 32-bit user-defined circular shifted data pattern Random data pattern derived from user-specified 32-bit seed using an LFSR (CRC32) Data pattern inversion Any data pattern can be inverted before being applied Up to 16 Up to 13 (limited by MTR:numcol to A[13:11,9:0]) Up to 3 Feature Description Programmable DRAM Timing Control DDR2 DRAM timing Burst Length Refresh control BIST Engine Control Fundamental commands Access method DRAM data width DRAM initialization and mode settings Execution speed Execution control Write, read, read with data compare, write + read with data compare all registers and settings accessible using FBD, JTAG, or SMBus x4 or x8 Set by AMB registers A programmable number of deselect commands may be inserted after DRAM accesses to slow down the speed of execution Halt on error or run to completion of test Test abort during the test Set in AMB registers 4 or 8 DDR2 refresh intervals programmable in AMB registers 112 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST Table 11-1. MemBIST Feature Summary (Sheet 2 of 2) Feature Failure data access Feature Description Failure data logged and accessible using FBD, JTAG or SMBus Logging may be delayed to capture later failures Algorithms Provided Algorithms operate over a specified address range with a fixed data pattern of 0xA only Notation for algorithm definitions: ^ = increasing address from start to end v = decreasing address from end to start W / R = Write / Read and check D / I = Data / Inverted Data number = sequence of events (x, y) = for each address, first x is applied, then y, before continuing to next address Scan Init Mats+ MarchC– ^ (WD1); ^(RD2); ^ (WI3); ^ (RI4) ^ (WD1) ^(WD1); ^(RD2, WI3); v(RI4, WD5); ^(WD1); ^(RD2, WI3); ^(RI4, WD5); v(RD6, WI7); v(RI8, WD9); v(RD10); ^(RD1); Read and check Error Logging Error logging Pass / fail indicator Log up to 5 failing addresses Record up to 4 sets of 144-bit failure data 144-bit failure data bit location accumulator marking bit failures through entire test 11.3 11.3.1 MemBIST Operation Fundamental Operations The MemBIST logic provides a number of operational modes which can be combined in various ways to provide a large number of useful combinations. For example, there is a mode in which it is possible to select address incrementing first by column and then by row, or the opposite of this. There is also a mode to dynamically invert every other address, which toggles all address lines to opposite states. These two independent modes can be combined to test a bank by toggling row address lines to opposite states or by toggling column address lines to opposite states. Limits on combinations are mentioned where they exist. MemBIST also provides a number of complete operations which it can perform. MemBIST operations can be characterized as a task which MemBIST carries out automatically after being programmed for the task. The operation begins when MBCSR:start is set by the user and ends when MemBIST clears this same bit. MemBIST operations include built-in algorithms and fundamental commands. MemBIST built-in algorithms consist of complete testing schemes which are implemented in MemBIST and which carry out complete tests for meeting specific testing objectives. They accomplish their testing completely under automatic control once the operation is started. Intel® 6400/6402 Advanced Memory Buffer Datasheet 113 DDR MemBIST In addition, MemBIST has 4 fundamental commands which can be utilized directly by the user. They are write, read, read with data compare, and write followed by read with data compare. They are also used by the MemBIST built-in algorithms. Some MemBIST algorithms also utilize additional fundamental commands that are not available to users. As a result, users cannot duplicate all algorithm functionality by sequentially running individual MemBIST commands. 11.3.2 Memory Addressing A memory test is characterized by a starting address, an ending address and a direction. The address generation logic has counters for row, column and bank addresses. MemBIST does not change the rank bit during execution. Each rank on a DIMM must be tested by a separate execution of MemBIST. Addresses in MemBIST are logical addresses, meaning they follow the order of the DRAM external address pins. The actual arrangement of bits in the array (the physical address) will differ from the logical address. Therefore, an addressing scheme or data pattern may not be applied to the array exactly as one might think. For example, accesses to logically adjacent cells will not necessarily access physically adjacent cells. For general purpose testing such as that intended for MemBIST this is not an issue. Indepth array testing is best done on a portion of the array where the logical to physical mapping is known, or in transparent mode where one has full control of address and data sequencing. 11.3.2.1 Address Definition All addresses in MemBIST have three components: a row address, a column address and a bank address. The user communicates these values to MemBIST through 32-bit registers. Column address 0 is not stored since the DRAMs are 72 bits wide and the MemBIST engine has an internal 144 bit architecture. Column address 10 is used for auto-precharge (always low in MemBIST) so it is also not specified in the address registers. User-defined start and end addresses are constrained to contain a column address modulo the burst length. For instance, at BL=4, assume a memory access starts at column 0. The next access would start at column 4, the next at column 8 and so on (assuming Fast Y address sequencing). The address register bits reflect these constraints. BL=4 allows specification of column bits 14..2, while BL=8 allows specification of column bits 15..3. Table 11-2. Memory Address Definition, BL=4 Address register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 14 13 12 11 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 2 1 1 Bank 0 0 Row Column Note: Address register bit 15 “R” = Reserved for future use 114 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST Table 11-3. Memory Address Definition, BL=8 Address register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 15 14 13 12 11 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 Bank 0 0 Row Column Note: Address register bit 15 “R” = Reserved for future use 11.3.2.2 Address Generation The address generation logic and controlling register bits allow a variety of methods to traverse the address space of the DRAM. These are described in the next sections. In these explanations, the symbol X refers to the row address. Row address lines are also called word lines. The symbol Y refers to the column address. Column address lines are also called bit lines. The symbol Z refers to the bank address. The MemBIST start address consists of a triple of row, bank, and column address (Xstart, Zstart, Ystart) or (Xs, Zs, Ys) for brevity. Likewise, the end address consists of the triple (Xend, Zend, Yend) or (Xe, Ze, Ye). The row, bank or column symbols may also be used individually to refer to a value without being included in the address triple to which it belongs. 11.3.2.2.1 Address Sequencing Options MemBIST provides several options to select the address space for MemBIST operation and for sequencing through the address space chosen. Table 11-4 below shows how the MemBIST addresses are generated based on various parameters that affect address generation. Detailed explanations of the entries are found in later sections. Intel® 6400/6402 Advanced Memory Buffer Datasheet 115 DDR MemBIST Table 11-4. MemBIST Addressing Behavior Address Type (MBSCR:atype) Address Sequencing (MBCSR:fast) Range (specified in MB_START_ADDR and MB_END_ADDRa) Counter orderb XZY X, Y increment3 start to end X, Y decrement3 end to start Z increments Zs to Ze if Zs < Ze Z decrements Ze to Zs if Zs < Ze Following is for Intel 6400/6402 Advanced Memory Buffer only and not required by the FBD DFx Spec Z fixed at Zs if Zs = Ze Z increments Zs to MTR limit, wraps to 0, then to Ze if Zs > Ze. Ze to Zs is skipped. • Z decrements Ze to 0, wraps to MTR limit, then to Zs if Zs > Ze. Ze to Zs is skipped. Counter order XY X, Y increment start to end X, Y decrement end to start Z fixed at Zs. Ze is ignored. Counter order YX X, Y increment start to end X, Y decrement end to start Z fixed at Zs. Ze is ignored X and Y count simultaneously X, Y increment start to end X, Y decrement end to start Z fixed at Zs. Ze is ignored Counter order XY X, Y increment 0 to MTR limit X, Y decrement MTR limit to 0 Z fixed at 0 Counter order YX X, Y increment 0 to MTR limit X, Y decrement MTR limit to 0 Z fixed at 0 X and Y count simultaneously X, Y increment 0 to MTR limit X, Y decrement MTR limit to 0 Z fixed at 0 Full (uses range of 0 to MTR limit) Counter order XZY X, Y, Z incrementc 0 to MTR limitd X, Y, Z decrement MTR limit to 0 Single (specified in MBADDR) Single burst to address specified in MBADDR MBCSR:fast ignored XZY Fast Y Fast X Fast XY Notes: a. b. c. d. It is required that Xs < Xe, Ys < Ye and Zs < Ze. Xs, Zs, Ys and Xe, Ze, Ye are the values in MB_START_ADDR and MB_END_ADDR respectively Counter order is counter MSB to LSB in the order given. Increment or decrement is selected using MBCSR:adir MTR limit is the value shown in MTR for this address and refers to the top of this address range. 11.3.2.3 Address Space The address space for MemBIST is selected using the MBCSR:atype field. The choices include a single physical address specified in the MBADDR register, a range of addresses as specified using the MB_START_ADDR and MB_END_ADDR registers, and the full address space of the DRAMs as specified in the MTR register. The range and full address spaces are depicted in the next figure, Figure 11-1. 116 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST Figure 11-1. Range and Full Address Spaces One Bank Limit of address space as set by number of X and Y address lines Address space as set by values in MTR register Address space as set by start and end values in MB_START_ADDR and MB_END_ADDR registers E S Increasing X 0 0 Increasing Y 0001 As the figure above illustrates, when the values of the MB_START_ADDR (marked S) and MB_END_ADDR (marked E) registers are used to set the address space for a MemBIST operation, the values in these registers must bear the correct relationship to each other. The start address sets the lower bound for the test address space in both the X and Y directions, and the end address sets the upper bound in both the X and Y directions. For a start and end address to define a usable address space, it is required that Xs < Xe, and Ys < Ye. In addition, when an address sequencing mode is chosen in which the bank field in MB_END_ADDR is significant, it is also required that Zs < Ze. (If a single physical address is to be tested, MBADDR, not MB_START_ADDR and MB_END_ADDR, is used.) In every case in which an address endpoint is specified using a register value, MemBIST includes the address endpoint in the operation. For example, if an address range is specified using the MB_START_ADDR and MB_END_ADDR registers, the locations specified in these registers are included as part of the address range. The MemBIST operation will be performed on both of the locations specified in these registers. 11.3.2.3.1 Order and Direction of Address Sequencing The order of sequencing through the test address space is chosen using the MBCSR:fast field. The options are Fast Y (with fixed bank), Fast X (with fixed bank), Fast XY (with fixed bank) and XZY. The terms Fast X, Fast Y, Fast XY and XZY refer to the order in which addresses are incremented or decremented during MemBIST execution. This order is given in Table 11-4 above as “counter order.” Counter order of XZY, for example, indicates that the Y counter is counted most rapidly. When counter Y over or underflows due to reaching the programmed limit of its count, the overflow or Intel® 6400/6402 Advanced Memory Buffer Datasheet 117 DDR MemBIST underflow is applied to the next, or Z, counter. When counter Z reaches its limit, its overflow or underflow is applied to counter X. A counter that overflows or underflows resets to its initial starting value and continues counting from that value. When using XZY addressing, MemBIST accesses the banks specified by MB_START_ADDR and MB_END_ADDR (with range addressing) or bank 0 through the MTR limit (with full addressing). When using XZY addressing, MemBIST accesses multiple banks. • With range addressing (MBCSR:atype = 0x2), the banks accessed are in the inclusive range specified by MB_START_ADDR:ba and MB_END_ADDR:ba. • With full addressing (MBCSR:atype = 0x3), the bank address is bank 0 through the MTR limit. When using Fast X, Fast Y or Fast XY addressing, MemBIST will traverse a single bank. • With range addressing (MBCSR:atype = 0x2), the bank is specified by MB_START_ADDR:ba. MB_END_ADDR:ba is ignored. • With full addressing (MBCSR:atype = 0x3), the bank address is always 0. The direction of sequencing through the test address space is chosen using the MBCSR:adir field. In this field, either incrementing addresses or decrementing addresses may be selected. The beginning and ending addresses for the counters depend upon the choice of addressing type programmed in MBCSR:atype. With range addressing, the counter limits are specified in MB_START_ADDR and in MB_END_ADDR. With full addressing, the counter limits are 0 and the MTR limit for each counter. Special cases which exist for the bank address are specified in Table 11-4. 11.3.2.4 11.3.2.4.1 Details and Examples Fast Y Figure 11-2 below depicts how Fast Y with incrementing addresses cycles through a range of addresses specified by MB_START_ADDR and MB_END_ADDR. In this execution mode, Z, or bank address, is held constant (except in the case of dynamic address inversion mode, DAI, mentioned later). The order in which the locations are accessed is shown in the boxes representing the memory locations. Note that the Y (or column) address counter counts from Ys to Ye before incrementing the X (or row) address counter and beginning again at Ys. This process continues until both the X and Y address counters reach their end values simultaneously. This ending condition results in the address range being covered once. The name “Fast Y” is descriptive of this testing order in which the Y address range changes faster than the X address range. 118 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST Figure 11-2. Fast Y Address Sequencing One Bank Address space as set by values in MTR register Address space as set by start and end values in MB_START_ADDR and MB_END_ADDR registers 13 14 15 16 17 E 18 12 7 8 9 10 11 S 1 2 3 4 5 6 Increasing X 0 0 Increasing Y Fast Y address sequencing, increasing address, specified address range 0001 11.3.2.4.2 Fast X Figure 11-3 below depicts how Fast X with decrementing addresses cycles through a range of addresses specified by MB_START_ADDR and MB_END_ADDR. In this execution mode, Z, or bank address, is held constant (except in the case of dynamic address inversion mode, DAI, mentioned later). Note that the X address counter counts down from Xe to Xs before decrementing the Y address counter and beginning again at Xe. This process continues until both the X and Y address counters reach their end Xs and Ys values simultaneously. This ending condition results in the address range being covered once. The name “Fast X” is descriptive of this testing order in which the X address range changes faster than the Y address range. Intel® 6400/6402 Advanced Memory Buffer Datasheet 119 DDR MemBIST Figure 11-3. Fast X Address Sequencing One Bank Address space as set by values in MTR register Address space as set by start and end values in MB_START_ADDR and MB_END_ADDR registers 16 13 10 7 4 E 1 2 17 14 11 8 5 S 18 15 12 9 6 3 Increasing X 0 0 Increasing Y Fast X address sequencing, decreasing address, specified address range 0001 11.3.2.4.3 Fast XY In Fast XY execution, both the X and Y address counters are changed by one count at the same time. Each of these counters begins at its starting address and increments to its ending address (or decrements from ending to starting address if so programmed) and then reloads on the next count to its initial value. As a result, test execution accesses the RAM locations in diagonal rows across the RAM. Execution stops when both the X and Y address counters reach their end values simultaneously. In the special case when there are the same number of rows and columns in the address space, only the locations on the diagonal (whose relative row and column positions are equal) will be tested. In the general case in which the specified address range results in different numbers of rows and columns, not all locations may be accessed. Which locations are accessed in this case depends upon the X to Y ratio of the address space specified for the test. See Figure 11-4 below for several examples. Because the starting and ending addresses are always located at opposite corners of the address space, the end address is always eventually reached, and the MemBIST operation always completes. 120 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST Figure 11-4. Fast XY Address Sequencing Examples Fast XY Examples BL = 4, incrementing addresses X (Rows) 0 1 2 3 0 Y (Columns) 4 8 C --2 --------3 --------- X (Rows) 0 1 2 3 0 4 Y (Columns) 8 C 13 18 3 8 9 14 19 4 10 5 10 15 S 1 ------- S 1 6 11 16 17 2 7 12 E 4 E 20 X (Rows) 0 1 0 Y (Columns) 4 8 C --2 3 ----- S 1 --- E 4 Numbers inside of cells indicate order of access. --- inside a cell indicates that cell is not accessed. 0001 11.3.2.4.4 XZY Addressing In XZY (range) address sequencing the MSB-to-LSB ordering of the address counters is Row, Bank, Column, although this is not the order of the fields in the registers used for address specification for MemBIST. As a result of this ordering of the counters, first the columns in one row in the starting bank will be accessed, followed by those on the same row in the second bank, and so on until that row in all banks has been accessed. Then the columns in the next row in the first bank will be selected and the process continued. Intel® 6400/6402 Advanced Memory Buffer Datasheet 121 DDR MemBIST 11.3.2.4.5 Dynamic Address Inversion (DAI): Dynamic address inversion (DAI) is provided to maximize the switching of address lines during testing. When dynamic address inversion is enabled, the address counters increment or decrement as usual, but every other address driven to the DRAMs is the logical inverse of the previous address used. The least significant address bit is not inverted since it already toggles at the address rate. All address lines (X, Y and Z) are inverted by DAI, creating a ping-pong access pattern. This occurs in all address sequencing modes. This behavior might lead to accesses in unexpected portions of the address space. For example, DAI inverts the bank address lines even in Fast X, Fast Y and Fast XY modes, which normally have fixed bank addresses. As a result, every other access is to a different bank than the fixed bank selected by the addressing mode (either MB_START_ADDR:ba field or bank 0 for range or full addressing respectively). Between each access, the old bank must be closed and the new bank must be activated. In another example, with XZY address sequencing and range addressing, it is normal to think of accesses as being restricted to the address range specified in MB_START_ADDR and MB_END_ADDR. But with DAI enabled, the non-inverted accesses will be within the specified range, but the inverted accesses could possibly fall outside of the specified address range. DAI can be used with any address sequencing mode. It can also be used with either incrementing or decrementing addresses. Table 11-5 gives an example of both address incrementing and address decrementing in DAI mode. This example is of XZY address sequencing with range addressing and shows only low-order bank and column address lines. Shaded rows are non-inverted, non-shaded rows show inverted addresses. Table 11-5. Dynamic Address Inversion, XZY Address Sequencing and Range Addressing Normal Bank 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 Etc. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 Column 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAI, incrementing address Bank 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 01 10 Etc. 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 Column 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAI, decrementing address Bank 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 11 00 Etc. 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 Column 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 122 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST 11.3.2.4.6 Address Inversion for Vtt Balancing FB-DIMMs use a separate termination (Vtt) power supply for command/address termination. Keep in mind the AMB has two copies of the CA bus. In normal operation the AMB attempts to balance the number of high and low address lines by inverting one of the address ports. Inverting one copy of the addresses reduces Vtt power consumption. This operation is invisible to the controller and DRAM, as this is simply a static inversion of address lines. By default this behavior is enabled for all memory accesses including during MemBIST operation. Most memory test patterns assume a particular address sequence. Vtt balancing might not be desirable in these cases. The AMB provides a control bit (DRC.BALDIS) to turn off Vtt balancing if desired. If the bit is set, no balancing will take place. If adjacent address inversion is disabled Vtt power may increase substantially, placing additional load on the system power supply. 11.3.3 Memory Data Formatting During MemBIST operation, 144-bit data is used to write to memory and to check data read from memory. The data register MBDATA allows definition of a 144-bit data pattern. The 144-bit data will be written in two consecutive 72-bit locations within a memory burst. When operating with a burst length of 4 (BL4), early data is written to the first and third locations in the burst and late data to the second and fourth locations. An 8-word burst (BL8) is treated in similar manner, with early data written to odd-numbered locations and late data to even locations. 11.3.3.1 Static Data Formats MemBIST provides a number of static data patterns which can be selected using bits in MBCSR. A static data pattern is one in which the data remains the same throughout the MemBIST operation. One such static data format is the fixed data pattern. The fixed data patterns are concatenated together multiple times to make up the number of bits required supply data to the DRAMs. In addition to these fixed patterns, the MBDATA registers can be used to supply 144 bits of user-defined data. The data from this static pattern is also concatenated together multiple times to make up the required number of bits for MemBIST use. Finally, there are certain cases, such as initializing ECC bits in system memory, that require unique data in each data word. This requirement is met by using all 288 bits of the data register MBDATA for user-defined data. This usage of the data register for user-defined data occupies bits which normally are used for failure information. Because the registers normally used for failure information are occupied with the data pattern, when 288-bit user-defined data is used, no checking is performed. 11.3.3.2 Dynamic Data Formats In addition to the static data formats, MemBIST has the ability to provide dynamically changing data patterns. Dynamic data changes each time that a new address is accessed. These supply shifted data and pseudo-random data. Note: The following description of circular shift and LFSR random data generation describes the Intel 6400/6402 Advanced Memory Buffer implementation. This does not match the FBD DFx description of these functions. Resolution of these differences will be decided based on potential changes to Intel 6400/6402 Advanced Memory Buffer. Intel® 6400/6402 Advanced Memory Buffer Datasheet 123 DDR MemBIST The simplified block diagram of Figure 11-5 below depicts the relationship between the LFSR seed register MBLFSRSED, the MBDATA[9, 7:4] registers, and the data sent on the CB and DQ chip pins when MemBIST executes a write command in the circular shift or in the LFSR data modes. The LFSR seed register is the source of the data written to the CD and DQ chip pins (and thus to the DRAMs) in both of these modes. When MemBIST executes a read command, the data generation is the same, but the data is not sent on the CB and DQ pins. Instead, it is used for comparison against the data received from the DRAMs on the corresponding pins. Figure 11-5. MemBIST Circular Shift and LFSR Data Block Diagram MemBIST Circular Shift and LFSR Data Block Diagram MBLFSRSED[31:0] 32 MBDATA9[31:0] [31] [30:0] [31:1] [0] [31:0] [15:8] [7:0] [31:0] late_DQ_wr_data[71:64] DDR Logic early_DQ_wr_data[71:64] late_DQ_wr_data[63:32] cb[7:0] 32 1 0 CRC-32 32 1 0 lfsr_mode load_lfsrseed MBDATA7[31:0] [31] [30:0] [31:1] [0] MBDATA6[31:0] [31] [30:0] [31:1] [0] [31:0] late_DQ_wr_data[31:0] 1 0 DDR Logic dq[63:0] load_circseed MBDATA5[31:0] [31] [30:0] [31:1] [0] [31:0] early_DQ_wr_data[63:32] MBDATA4[31:0] [31] [30:0] [31:1] [0] [31:0] early_DQ_wr_data[31:0] MBCSR: invert 32 0002 In circular shift data mode, the 0 input of the mux at the far right is selected, since this is not LFSR mode. At the beginning of MemBIST execution in this mode, the value of the LFSR seed register is loaded into MBDATA9 by asserting the load_circseed signal shown. Registers MBDATA[7:4] are all cleared to 0 at this time, so that their previous contents are lost. Each time that MemBIST execution requires data to be written to the DRAMs, 144 bits are taken from the 160 bits comprising MBDATA[9,7:4], as shown in the figure. The 144 bits are either inverted or not before being sent to the DDR logic to be written to the DRAMs, depending upon the state of the MBCSR:invert bit. After using the data, the MBDATA[9,7:4] registers are clocked once, shifting the data around within these registers to form new data to be used by MemBIST the next time that data is required. For example, when MemBIST starts and MBCSR:invert is 0, the value from the LFSR seed register will be loaded into MBDATA9, and MBDATA[7:4] will be cleared, so that the first data available for MemBIST to write to the CB and DQ pins will consist of MBDATA9[7:0] sent on the early cycle on the CB pins, MBDATA9[15:8] on the late cycle on the CB pins, and 0s sent on all of the DQ pins on both the early and late cycles. Once this data has been used, the MBDATA[9,7:4] registers are clocked. The data path between the MBDATA registers is wired so that the data undergoes a left circular shift when passing to the next register. Bits [30:0] become bits [31:1] in the receiving register, and bit [31] becomes bit [0] in the receiving register. For example, 0x8000_0001 in MBDATA9 becomes 0x0000_0003 upon being loaded into MBDATA7. 124 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST In LFSR data mode, a similar procedure is followed, with the exception that the lfsr_mode signal causes the mux on the far right of the figure to select the output of the CRC-32 block to provide the input to register MBDATA9. At the beginning of MemBIST execution, load_lfsrseed asserts once to use the value in the LFSR seed register as the initial input to the CRC-32 block. On subsequent register loads, the current value in MBDATA9 is used as the input to the CRC-32 block. Each time that MBDATA9 is loaded with a new data value from the CRC-32 block, each of MBDATA[7:4] also load new values from their inputs. Before the first 144 bits of data are used by MemBIST in LFSR mode, 5 register loads occur. This fills all bits in MBDATA[9,7:4] with random data values before the first data is written to the DRAMs. Table 11-6 below shows an excerpt from an example run of MemBIST executing with MBCSR:dtype = 2, circular shift data. The table illustrates the relationship between the LFSR seed register MBLFSRSED, the BMDATA[9, 7:4] registers, and the data sent on the CB and DQ chip pins when executing in the circular shift mode with MBCSR:invert = 0. The table also illustrates how the circular shift occurs in the MBDATA registers. This further illustrates the process explained and shown above. Table 11-6. Example of Circular Data Shifting # 1 2 3 4 5 6 Mbdata9 xxL[71:64 ]E[71:64] 0000_0001 0 0 0 0 0000_0020 Mbdata7 L[63:32] 0 0000_0002 0 0 0 0 Mbdata6 L[31:0] 0 0 0000_0004 0 0 0 Mbdata5 E[63:32] 0 0 0 0000_0008 0 0 Mbdata4 E[31:0] 0 0 0 0 0000_0010 0 Early CB 01 0 0 0 0 20 Late CB 0 0 0 0 0 0 Early DQ 0 0 0 0000_0008 _0000_0000 0000_0000 _0000_0010 0 Late DQ 0 0000_0002 _0000_0000 0000_0000 _0000_0004 0 0 0 In the example shown, MBLFSRSED contains 0x0000_0001 when MemBIST execution starts. MBCSR contains 0x8022_0a90. Line 1 shows the data from MBLFSRSED loaded into MBDATA9, and shows how 144 bits of the data from MBDATA[9,7:4] are sent on the CB and DQ pins when required by MemBIST. Line 2 shows the result of the circular shift of MBDATA9 into MBDATA7, as explained previously. Line 2 also shows how this second set of 144 bits of data will appear on the CB and DQ pins when it is used by MemBIST. The table shows how the original data from MBLFSRSED is transferred from register to register each time that data is required by MemBIST execution, with a onebit left circular shift occurring at each register transfer. Line 6 shows the data from MBDATA4 arriving at MBDATA9, again with a circular shift left. Table 11-7 below shows an excerpt from an example run of MemBIST executing with MBCSR:dtype = 3, LFSR data. The table illustrates the relationship between the LFSR seed register MBLFSRSED, the MBDATA[9, 7:4] registers, and the data sent on the CB and DQ chip pins when executing in the LFSR data mode. The table also illustrates how the circular shift occurs in the MBDATA registers during LFSR data mode with MBCSR:invert = 0. This further illustrates the process shown in the figure above. Intel® 6400/6402 Advanced Memory Buffer Datasheet 125 DDR MemBIST Table 11-7. Example of LFSR Random Data # 1 2 3 4 5 6 Mbdata9 xxL[71:64 ]E[71:64] 27fe_3b3d 4e2e_350c Mbdata7 L[63:32] 0 4ffc_767a Mbdata6 L[31:0] 0 0 9ff8_ecf4 Mbdata5 E[63:32] 0 0 0 3ff1_d9e9 Mbdata4 E[31:0] 0 0 0 0 dd d0 8e 1d 7171_a862 _7fe3_b3d2 4d44_dd76 _ e2e3_50c4 2f95_386d _26a2_6ebb cc5f_1dba _5f2a_70da Early CB Late CB Early DQ Late DQ C9a8_9bae 9c5c_6a18 97ca_9c36 9351_375d 38b8_d431 662f_8edd 4031_1dd0 2f95_386d 26a2_6ebb 7171_a862 7fe3_b3d2 cc5f_1dba 5f2a_70da 4d44_dd76 e2e3_50c4 In the example shown, MBLFSRSED contains 0x93d7_8768 when MemBIST execution starts. MBCSR contains 0x8011_0b90. Lines 1 through 5 show filling of MBDATA[9,7:4] with random data generated by the CRC-32 block. For each line, newly generated random data is loaded into MBDATA9, and MBDATA[7:4] are loaded with data which is the result of a circular left shift from the register above it. Line 5 shows how 144 bits of the data from MBDATA[9,7:4] is sent on the CB and DQ pins when required by MemBIST. Line 6 shows the result of the circular shift of the contents of each MBDATA register into the next MBDATA register. Line 6 also shows how this second set of 144 bits of data will appear on the CB and DQ pins when it is used by MemBIST. The table shows how the random data from MBDATA9 is transferred from register to register each time that data is required by MemBIST execution, with a onebit left circular shift occurring at each register transfer. 11.3.4 Algorithmic Testing MemBIST provides several of the more common algorithmic tests. Several of these are directed at basic operation such as initializing memory or verifying proper connectivity of the AMB and DRAM on a DIMM. In addition there are a few tests that are intended to perform testing of the AMB address generators and DRAM internal address decoders, multiplexers and related logic that is not otherwise testable at speed. The algorithm engine takes control of the MemBIST engine to carry out the algorithm steps. It does this by writing to some of the control bits in MBCSR. As a result, those control bits used by the algorithm engine are not available for setting by the user. However, the remaining control bits may be utilized by the user to control the algorithm. The MemBIST controls which may be selected by the user when using one of the built-in algorithms are: • Address sequencing (Fast X, Fast Y, Fast XY, and XZY) • Rank selection • Halt or continue on error When an algorithm is used, the data used for the test is always the fixed pattern 0xA. No other pattern may be chosen. The address space for the algorithm is always the address range specified by MB_START_ADDR and MB_END_ADDR. If testing of the full address range of the DRAM is required, then the MB_START_ADDR and MB_END_ADDR registers must be set to this address range. 126 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST When using the built-in algorithms, the initial command for the algorithm must be entered into MBCSR:cmd. For all algorithms except data retention read, the initial command to enter is write (0x1). For the data retention read algorithm, the initial command to enter is read and check (0x3). Because the algorithm engine takes control of the MemBIST engine to carry out the algorithm steps, a guess about the algorithm step during which the first failure occurred can be formulated by examining the various MemBIST control registers after MemBIST halts on error. After the operation halts, the control register values will generally still reflect their settings when the algorithm step detected the failure. The algorithms provided by MemBIST are specified in the following sections. The algorithms are specified using the following notation: ^ = increasing addressing. Addresses will be counted up, starting at 0 or the userdefined start address as appropriate. v = decreasing addressing. Addresses will be counted down, starting at the end of the array or from the user-defined end address, as appropriate. w or r = Write or Read with checking of the data against the expected data. D or I = Data or Inverted Data number = sequence of events ( ) = back to back operations. Example: (wD, rD) will read and then write the same cell before moving to the next cell. 11.3.4.1 Initialization Tests Init: ^ (wD)1 This is a simple memory initialization algorithm. Data is written to the array with incrementing addressing. Read and check: ^(rD)1This test is used to verify memory contents. One use of this is data retention testing. Init may be used to write known data in the array. The tester or system can then alter an environmental condition, or simply wait for some period of time, and then read the array to see if the data changed. Scan: ^(wD)1; ^(rD)2; ^ (wI)3; ^ (rI)4 The scan test writes data to the array then reads the data back. The second half of the test writes inverted data and reads it back. Scan is a 4N pattern, meaning test time will be 4 traversals, times the size of the array (rows * columns * banks, also known as ‘N’) times the average time for a read or write operation. 11.3.4.2 Memory Stress Tests Mats+: ^(wD)1; ^(rD2, wI3); v(rI4, wD5) The Mats+ algorithm initializes the array to a known data background and steps through with a read-write-inverted-data sequence. The algorithm is performed with both incrementing and decrementing addressing. Mats+ will detect stuck at faults and basic address decoder faults. The algorithm is order 5N. MarchC-: ^(wD)1; ^(rD2, wI3); ^(rI4, wD5); v(rD6, wI7); v(rI8, wD9); v(rD)10 The MarchC- algorithm initializes the array to a known data background and steps through the array in both count-up and count-down addressing with a read-write sequence. MarchCtests the array decoders and basic neighboring faults. As might Intel® 6400/6402 Advanced Memory Buffer Datasheet 127 DDR MemBIST be determined from the sequence numbering this is a 10N pattern. 11.3.5 Error Reporting and Control Information about failures detected by MemBIST is reported in a variety of ways. These are summarized here and detailed in the following sections. MBCSR:pf set during a MemBIST operation indicates that a failure was detected. MBDATA can log the addresses of up to 5 failures. When the MemBIST operation is utilizing a fixed data pattern selected using MBCSR:dtype = 0x0, MBDATA also contains a failure data bit location accumulator, which logs any data bit that has seen a failure during the operation. With other dtypes, the failure data bit location accumulator may replace the address logs. MB_ERR_DATA logs the first four 144-bit data words which MemBIST detects as containing an error after the Memory Test Failure Address Pointer Register (MBFADDRPTR) has counted down to zero. MBFADDRPTR makes it possible to extract the failure data information for all repeatable failures which occur during execution of a MemBIST operation. How the available logs in are filled depends partly upon the MemBIST configuration and partly upon how the errors detected by MemBIST occur. For example, when MemBIST is set to halt on error and a failure is detected, MemBIST does not advance to the next address. However, due to the architecture of the memory system, there may be more than one error to log from the single address that was being checked when the failure was detected. At burst length of 4, for each address there are four 72-bit bus-widths of data to be checked. Data is logged in 144-bit quantities. If a bit in the DRAM bus was stuck, this might result in an error being detected in each of the four 72-bit bus-widths of data. Even though MemBIST is set to halt on error, this would result in two 144-bit data error logs, each with a corresponding failure address log. Operating at BL=8 could result in up to four 144-bit data error logs being written with their corresponding address logs. When MemBIST is not set to halt on error, logs will fill as errors occur. The logs may contain information from several unrelated failing addresses. The first four failures to be detected will cause the first four 144-bit failure data chunks to be logged along with their corresponding addresses. The address of the fifth error to occur will also be logged, although there is no location available to log the failure data. The sixth and succeeding errors will not be logged. During execution of a MemBIST operation, MemBIST will not overwrite a log entry that has already been filled during that operation to record a more recent failure. 11.3.5.1 Control Register Pass/Fail Bit and Halt On Error The MemBIST pass/fail bit, MBCSR:pf, is always cleared when MemBIST execution starts. If a failure is ever detected, this bit is always set immediately. If MBCSR:halt (halt on detection of read-compare error) is set, and MBCSR:pf is then set due to detection of an error, MemBIST execution always completes the accesses to the current address and then halts without proceeding to the next address. No other MemBIST controls, including a non-zero value in MBFADDRPTR, modifies the setting of the failure bit or the halting on failure detection as described. 11.3.5.2 Failure Address Logging The addresses of the first 5 detected failures can be logged by MemBIST. The address logs (located in MBDATA) are always cleared, and the logging pointer is always reset to start logging with the first log, each time that MemBIST starts execution of a new operation. 128 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST Failure addresses are logged in a slightly different format than the format which is used when specifying start and end addresses. To compress the failure address into 32 bits, bits that are always zero are not stored in the log. These unstored bits include AutoPrecharge Column address [10] and the least significant bits assumed by burst length. In BL=4 operation, column bit 1 in the log is replaced by a bit which distinguishes whether the error was detected in the first 144-bit data chunk (the bit is 0) or in the second chunk (the bit is 1). In like manner, for BL=8 operation, column bits 2:1 are replaced by two bits to identify the data chunk containing the error. The bits used for BL=8 are shaded in Table 11-8 below. See Section 14.5.2.3.1, “MBDATA Failure Address Mapping” for more information. Table 11-8. Address Log to Bank, Row and Column Bit Correspondence Address Log Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 2 1 Bank 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 9 7 8 6 7 5 6 4 5 3 4 2 3 1 2 0 1 14 13 12 11 Row Column 11.3.5.3 Failure Data Bit Location Accumulator MemBIST provides a (sometimes optional) 144-bit failure data bit location accumulator, maintained in the MBDATA registers. Each bit tracks a data bit during MemBIST operation. This accumulator is automatically zeroed each time that MemBIST starts execution of a new operation. An accumulator bit set to 1 indicates that the corresponding data bit failed to have the expected value at least once during the operation. This accumulator is used primarily for recording detected failed data lines to facilitate DRAM replacement during DIMM manufacturing. Table 11-9 below shows the correspondence between the DRAM data bus bits and the 160 bits in the MBDATA registers used to store the failure data bit location accumulator. Table 11-9. Failure Data Bit Location Accumulator to MBDATA Bit Correspondence MBDATA[8] 31 24 23 16 15 71 8 64 7 71 0 64 MBDATA[3] 31 63 0 32 MBDATA[2] 31 31 Late data 0 0 MBDATA[1] 31 63 0 32 MBDATA[0] 31 31 Early data 0 0 Unused Late data Early data Late data Early data 11.3.5.4 Failure Data Logging Failure data is logged in the MB_ERR_DATA registers. These data logging registers are not cleared when MemBIST starts execution of a new operation, although the corresponding address logs in the MBDATA registers are cleared. The user desiring to discard failure data logs from a previous operation must write zeros to these registers before starting the next operation. During execution of a subsequent operation, when the first failure is detected, both an address and a data log are written, beginning with the first error log entry. Any existing data in the data logging registers used for this log entry is overwritten. The data in the other data logging registers is not affected. Table 11-10 shows the correspondence between the failure number, the address log for this error, and the data log for this error. Which register is used to log the address of the failure depends upon settings in MBCSR:dtype and MBCSR:algo. If MBCSR:algo is non-zero, then an algorithm is selected, and fixed data is used. Address logging will occur according to the “Fixed data pattern” entries in Table 11-10. Intel® 6400/6402 Advanced Memory Buffer Datasheet 129 DDR MemBIST If MBCSR:algo = 0x0 (no algorithm), then MBCSR:dtype determines the failure address error logging registers. For dtype = 0x0 (fixed), address logging will occur according the to “Fixed data pattern” entries in Table 11-10. For dtype other than 0x0 (that is, circular, random, or user data), if MBCSR:mbdata = 1, then the “Other data pattern” entries show the address logging registers. For these dtypes, if MBCSR:mbdata = 0 (accumulator), no failure address logging is available. Table 11-10. Failure to Logging Register Correspondence Failure number 1 2 3 4 5 6+ Address logged in Fixed data pattern: MBDATA4 Other data pattern: MBDATA0 Fixed data pattern: MBDATA5 Other data pattern: MBDATA1 Fixed data pattern: MBDATA6 Other data pattern: MBDATA2 Fixed data pattern: MBDATA7 Other data pattern: MBDATA3 Fixed data pattern: MBDATA9 Other data pattern: MBDATA8 Not logged Data logged in MB_ERR_DATA0[4:0] MB_ERR_DATA1[4:0] MB_ERR_DATA2[4:0] MB_ERR_DATA3[4:0] Not logged Not logged 11.3.5.5 Multiple Failures MemBIST may detect many more failures than there are available registers in which to log them. For some test purposes, the information captured by the failure data bit location accumulator may be sufficient. However, in other situations, capturing all of the failure data and failure addresses may be significant. As long as the failures are repeatable, MemBIST provides a mechanism to extract the failure information about all failures which MemBIST detects during execution of each MemBIST operation. Repeatable failures are ones which occur each time that a test is run. MemBIST uses the MBFADDRPTR register to discard logs for certain errors, allowing other errors to be logged instead. (However, this register has no effect on setting bits in the failure data bit location accumulator.) The error logging described in the previous section actually occurs on the first through fifth errors after the MBFADDRPTR register equals zero. Since this register defaults to zero, this is the normal logging behavior. However, if storing of logs for later errors is desired, the MBFADDRPTR register should simply be set to the number of earlier logs which are to be discarded. For example, suppose that MemBIST has been executed, and 5 logs were stored in the failure address logs. Full information was available for the first four (because both address and data logs exist). To collect both the failure address and data for the fifth failure, set MBFADDRPTR to 0x4 and rerun MemBIST. Each of the first 4 logs will be discarded, and will decrement MBFADDRPTR until it reaches 0. The fifth log will be stored, as it is the first to occur after MBFADDRPTR reached 0. This will work no matter what the position of the error is within the burst. Referencing the above example, if the fourth error is within a burst, and the fifth error is within the same burst but not in the same 144-bit chunk containing the fourth error, the fourth error will not be logged and the fifth error will be logged. 130 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST To use this feature, MemBIST must be set to continue on error by clearing MBCSR:halt. Otherwise MemBIST will halt on detecting the first failure and later failures will not be detected or logged. Neither setting of the failure bit, nor halting on failure detection is affected by a non-zero value in MBFADDRPTR. The general procedure for using this feature is to run MemBIST, read and record the address and data failure information from the logs, and then add the number of failure logs received to the value in MBFADDRPTR to cause the failure information already captured to be ignored on the next pass. This process is repeated until MemBIST completes with zeros in the address logs. This indicates that no further errors were detected beyond those already logged. (Watch the case of decrementing addressing ending at address 0. A failure at address 0 with failure data of zero is possible.) To generate a complete data log of all failures, use the following procedure: 1. Define starting and ending addresses, address modes and data patterns, set MBFADDRPTR to zero, set halt on error to 0 (don’t halt on error). 2. Start MemBIST and check the result. If pass, exit. If fail, continue. 3. Read out the failing addresses and data. If the address and data logs are zero (and the address space covered by this pass of MemBIST does not include address 0), exit, as all failures have been seen. Otherwise, continue. (If the address space covered by this pass of MemBIST does include address 0, and it is ambiguous whether or not address 0 has failed, the ambiguity can be resolved by retesting only address 0.) 4. Add the number of complete logs (for which both address and data were read) obtained during this pass to the value in MBFADDRPTR so that these failures will not be seen again on the next pass of MemBIST. 5. Go to step 2 11.3.6 DRAM Throttling MemBIST can generate high DRAM bandwidth and consequently, high power consumption and thermal stress. Although this is manageable in a dedicated test environment, a system’s power and cooling capacity may be exceeded. For this reason MemBIST allows insertion of deselect cycles on every address change. The deselects will be inserted after each read or write command. This allows slowing down BIST execution if necessary to stay within a given power or cooling envelope. 11.3.7 Refresh Control In normal operation, refresh commands are issued by the host rather than by the AMB. However, during MemBIST, when commands to the DRAM originate from the AMB, refresh must be provided by MemBIST. The refresh and MemBIST state machines are implemented as separate state machines, allowing refresh when MemBIST is not active. The refresh interval is programmable by setting a 15 bit refresh counter. For example, at the maximum address frequency of 400 Mhz (250 pS), 3120 clocks are needed to achieve the nominal refresh interval of 7.8 µS. The maximum interval in this case will be 81.9 µS. The default refresh value should be usable in most circumstances. The refresh interval may be programmed to other values to meet special needs. Intel® 6400/6402 Advanced Memory Buffer Datasheet 131 DDR MemBIST Table 11-11. Refresh Programming spec (uS) tREFI (15 bits) min spec max 0 7.8 81.9 clk period (uS) 0.0025 0.0025 0.0025 count 1 3120 32768 11.3.8 DRAM Initialization As in other operating modes, MemBIST requires the DRAM be initialized prior to the start of any operation. DRAM initialization is accomplished by starting the initialization engine (using the DCALCSR register). This may be done in band or out of band. 11.4 MemBIST Memory Test Examples In general, using MemBIST will involve the following five steps: 1. Define DRAM characteristics. Set up AMB registers for normal DRAM operation. This includes programming the MTR register to match the geometry of the DRAMs on the DIMM. In addition, program the DRT register to match the DDR2 timing of the DRAMs installed on the DIMM. MemBIST uses settings from MTR and DRT to match its operation to the characteristics of the DRAMs being tested. Change the default refresh interval if it does not meet the test objectives. Perform any other normal initialization. 2. Define the test address space. Define the starting and ending physical Row/ Column/Bank address range which MemBIST is to test in registers MBADDR, MB_START_ADDR, and MB_END_ADDR as required. Which of these registers is used depends upon which address range is selected in MBCSR:atype and whether or not an algorithm is selected. 3. Enter required user test data. Define any required user test data for this test, using registers MBDATA[9:0] and MBLFSRSED as appropriate. Which of these registers is used depends upon the setting of MBCSR:dtype, MBCSR:algo, and MBCSR:enable288. 4. Set test parameters and start MemBIST. Write MBCSR with MBCSR:start set and other bits set as required to select the desired MemBIST operation. 5. Evaluate the result. The test result is available through MBCSR:pf. Depending upon which settings were specified in MBCSR, error information is contained in the MBDATA[9:0]and MB_ERRDATA[4:0] registers. The next sections provide specific examples of MemBIST execution for selected test cases. 11.4.1 Write a Fixed Pattern to a Range of DRAM Addresses The following points describe the programming required to write a fixed data pattern to all of the addresses within a selected address range, and to optionally check this data, using MemBIST. 1. Set up registers for normal DRAM operation. 2. Program MB_START_ADDR and MB_END_ADDR registers to the desired address range to be tested. 132 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST 3. No user data is required, as fixed data (selected in MBCSR) will be used for this test. Therefore, the MBDATA[9:0] and MBLFSRSED registers are not written. 4. Program MBCSR. These fields are required for the specified test: — Program DTYPE (bits [9:8]) to 00 to select fixed data pattern. — Program ATYPE (bits [7:6]) to 10 to use the address range already defined in the MB_START_ADDR and MB_END_ADDR registers. — Select either Rank 0 or Rank 1 by programming CS (bits [21:20]). — MBDATA (bit 14) and ENABLE288 (bit 15) are not relevant when fixed data has been selected. INVERT (bit 19) is unnecessary for fixed data, since the data choices include inverses for all fixed data patterns. Rewrite these fields with their default values. The values for these fields can be selected to choose options for use during MemBIST operation: — Program ABAR (bit 13) to select DAI if desired. — Either program CMD (bits [5:4]) to be “01” (write only without data comparison) or “11” (write followed by read with data comparison). — Program FAST (bits [11:10]) to select Fast X, Fast Y, Fast XY, or XZY (column->bank->row) address sequencing. — Program ADIR (bit 12) to select whether addresses should increment or decrement. — Program FIXED (bits [18:16]) to specify which fixed data pattern to apply. Set these control values to start the MemBIST engine. — Set ALGO (bits 26:24) to 0 to prevent the algorithm engine from overwriting bits it controls in MBCSR. — Set ABORT (bit 28) to 0. — Clear PF (bit 30). Hardware will set this bit if a failure is detected. — If desired to halt whenever there is an error, set HALT (bit 29). — Set START (bit 31) to 1 to start MemBIST execution. 5. Check the MemBIST results, and if checking was enabled, observe failure data or address through MBDATA registers and MB_ERR_DATA registers: — Check MBCSR:start. 0 means MemBIST has completed. Check MBCSR:PF. 1 means a failure has occurred. — Failure data bit location accumulator will be stored in MBDATA[8, 3:0]. — Up to 5 failure addresses will be placed in MBDATA[9, 7:4] — Failure data will be stored in MB_ERR_DATA[3:0][4:0] registers. 11.4.2 Write Random Data to a Range of DRAM Addresses and Check This describes writing randomly generated data to a range of DRAM addresses and checking this data. 1. Set up registers for normal DRAM operation. 2. Program MB_START_ADDR and MB_END_ADDR registers to the desired address range to be tested. Intel® 6400/6402 Advanced Memory Buffer Datasheet 133 DDR MemBIST 3. Random data is created by the LFSR using the seed value in MBLFSRSED. Either a value can be written, or the default value can be used. MBDATA[9:0] is unused and is therefore not written. 4. Program MBCSR. These fields are required for the specified test: — Program DTYPE (bits [9:8]) to 11 to select LFSR-generated random data. — Program CMD (bits [5:4]) to be 11 (write followed by read with data comparison). — Program ATYPE (bits [7:6]) to 10 to use the address range already defined in the MB_START_ADDR and MB_END_ADDR registers. — Select either Rank 0 or Rank 1 by programming CS (bits [21:20]). — ENABLE288 (bit 15) is not relevant when random LFSR data has been selected. INVERT (bit 19) is unnecessary for random data. Rewrite these fields with their default values. The values for these fields can be selected to choose options for use during MemBIST operation: — Program ABAR (bit 13) to select DAI if desired. — Program FAST (bits [11:10]) to select Fast X, Fast Y, Fast XY, or XZY (column>bank->row) address sequencing. — Program ADIR (bit 12) to select whether addresses should increment or decrement. — MBDATA (bit 14) is set to select failure address logging or failure data bit location accumulator logging in MBDATA. Set these control values to start the MemBIST engine. — Set ALGO (bits 26:24) to 0 to prevent the algorithm engine from overwriting bits it controls in MBCSR. — Set ABORT (bit 28) to 0. — Clear PF (bit 30). Hardware will set this bit if a failure is detected. — If desired to halt whenever there is an error, set HALT (bit 29). — Set START (bit 31) to 1 to start MemBIST execution. 5. Check the MemBIST results, and if a failure occurred, observe failure data or address through MBDATA registers and MB_ERR_DATA registers: — Check MBCSR:start. 0 means MemBIST has completed. Check MBCSR:PF. 1 means a failure has occurred. — Depending upon the value chosen for MBCSR:mbdata, either up to 5 failure addresses or the failure data bit location accumulator will be stored in MBDATA[8, 3:0]. — Failure data will be stored in MB_ERR_DATA[3:0][4:0] registers. 11.4.3 Write Leaping 0s to the Full DRAM Address Range and Check This describes writing leaping 0s to all locations in the DRAM on the DIMM and checking this data. Leaping 0s are like walking 0s except that rather than moving from bit to adjacent bit, the single 0 in a field of 1s moves from one bit to another bit far removed from it. Of every 160 writes to the DRAMs, 144 will have a 0 on some bit, and 16 will have no 0s on any bit. Refer to the tables and block diagram above to see how this works. 1. Set up registers for normal DRAM operation. 134 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST 2. This example illustrates the use of MBCSR:atype = 11, so MB_START_ADDR and MB_END_ADDR are not programmed. However, these registers could alternatively be set to 0 and the maximum address in the DIMM respectively, and MBCRS:atype set to 10, to accomplish the same effect. 3. To get a field of 1s for the leaping 0 to traverse, data to the DRAMs must be inverted. This is because MBDATA[9, 7:4] are set to zeros at the start of MemBIST execution. That also means that the data programmed into MBLFSRSED must be inverted. So MBLFSRSED is set to 0x0000_0001. When inverted, this will give a single 0 in a field of 1s. Registers MBDATA[8, 3:0] are unused and are therefore not written. 4. Program MBCSR. These fields are required for the specified test: — Program DTYPE (bits [9:8]) to 10 to select circular shifted data. — Program CMD (bits [5:4]) to be 11 (write followed by read with data comparison). — Program ATYPE (bits [7:6]) to 11 to use the full address range of the DIMMs as already defined in the MTR register. — Select either Rank 0 or Rank 1 by programming CS (bits [21:20]). — INVERT (bit 19) must be set to 1 to create the field of 1s from the 0s in MBDATA[9, 7:4]. — ENABLE288 (bit 15) is not relevant when circular shifted data has been selected. Rewrite this field with its default value of 0. The values for these fields can be selected to choose options for use during MemBIST operation: — Program ABAR (bit 13) to select DAI if desired. — Program FAST (bits [11:10]) to select Fast X, Fast Y, Fast XY, or XZY (column>bank->row) address sequencing. — Program ADIR (bit 12) to select whether addresses should increment or decrement. — MBDATA (bit 14) is set to select failure address logging or failure data bit location accumulator logging in MBDATA. Set these control values to start the MemBIST engine. — Set ALGO (bits 26:24) to 0 to prevent the algorithm engine from overwriting bits it controls in MBCSR. — Set ABORT (bit 28) to 0. — Clear PF (bit 30). Hardware will set this bit if a failure is detected. — If desired to halt whenever there is an error, set HALT (bit 29). — Set START (bit 31) to 1 to start MemBIST execution. 5. Check the MemBIST results, and if a failure occurred, observe failure data or address through MBDATA registers and MB_ERR_DATA registers: — Check MBCSR:start. 0 means MemBIST has completed. Check MBCSR:PF. 1 means a failure has occurred. — Depending upon the value chosen for MBCSR:mbdata, either up to 5 failure addresses or the failure data bit location accumulator will be stored in MBDATA[8, 3:0]. — Failure data will be stored in the MB_ERR_DATA[3:0][4:0] registers. Intel® 6400/6402 Advanced Memory Buffer Datasheet 135 DDR MemBIST 11.4.4 Write 144-bit User-defined Pattern to a Range of Addresses and Check This describes writing user-defined data to a range of DRAM addresses and checking this data. 1. Set up registers for normal DRAM operation. 2. Program MB_START_ADDR and MB_END_ADDR registers to the desired address range to be tested. 3. 144 bits of user-defined data is written to MBDATA[9, 7:4]. MBLFSRSED are unused and are therefore not written. 4. Program MBCSR. These fields are required for the specified test: — Program DTYPE (bits [9:8]) to 01 to select user-defined data. — ENABLE288 (bit 15) is left 0 to select 144 bit user-defined data. — Program CMD (bits [5:4]) to be 11 (write followed by read with data comparison). — Program ATYPE (bits [7:6]) to 10 to use the address range already defined in the MB_START_ADDR and MB_END_ADDR registers. — Select either Rank 0 or Rank 1 by programming CS (bits [21:20]). — INVERT (bit 19) is unnecessary for user-defined data, as the user can set the bits to the values desired directly. Set this field to 0. The values for these fields can be selected to choose options for use during MemBIST operation: — Program ABAR (bit 13) to select DAI if desired. — Program FAST (bits [11:10]) to select Fast X, Fast Y, Fast XY, or XZY (column>bank->row) address sequencing. — Program ADIR (bit 12) to select whether addresses should increment or decrement. — MBDATA (bit 14) is set to select failure address logging or failure data bit location accumulator logging in MBDATA[8, 3:0]. Set these control values to start the MemBIST engine. — Set ALGO (bits 26:24) to 0 to prevent the algorithm engine from overwriting bits it controls in MBCSR. — Set ABORT (bit 28) to 0. — Clear PF (bit 30). Hardware will set this bit if a failure is detected. — If desired to halt whenever there is an error, set HALT (bit 29). — Set START (bit 31) to 1 to start MemBIST execution. 5. Check the MemBIST results, and if a failure occurred, observe failure data or address through MBDATA registers and MB_ERR_DATA registers: — Check MBCSR:start. 0 means MemBIST has completed. Check MBCSR:PF. 1 means a failure has occurred. — Depending upon the value chosen for MBCSR:mbdata, either up to 5 failure addresses or the failure data bit location accumulator will be stored in MBDATA[8, 3:0]. — Failure data will be stored in MB_ERR_DATA[3:0][4:0] registers. MBDATA[8, 3:0] and 136 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST 11.4.5 Test a Range of DRAM Addresses With March C- Algorithm The following points describe the programming required to test all of the addresses within a selected address range using the March C- algorithm provided by MemBIST. 1. Set up registers for normal DRAM operation. 2. Program MB_START_ADDR and MB_END_ADDR registers to the desired address range to be tested. If the full address of the DIMM is to be tested, it must be programmed here. 3. No user data is required, as all built-in testing algorithms use the fixed data pattern 0xA (regardless of the pattern selected by MBCSR:fixed). Therefore, the MBDATA[9:0] and MBLFSRSED registers are not written. 4. Program MBCSR. These fields are required for the specified test: — Set ALGO (bits 26:24) to 110 to select the built-in March C- testing algorithm. — Program CMD (bits [5:4]) to be 01 (write only without data comparison), as this is required for the March C- algorithm. The values for these fields can be selected to choose options for use during MemBIST operation: — Select either Rank 0 or Rank 1 by programming CS (bits [21:20]). — Program FAST (bits [11:10]) to select Fast X, Fast Y, Fast XY, or XZY (column->bank->row) address sequencing. These bits are taken over by the algorithm engine to execute the algorithm. Set them to their default values. — FIXED (bits [18:16]). — ADIR (bit 12). — ABAR (bit 13). — DTYPE (bits [9:8]). — ATYPE (bits [7:6]). — ENABLE288 (bit 15) — INVERT (bit 19). — MBDATA (bit 14). This bit is irrelevant because algorithms always use fixed data, so both failure data bit lane accumulator and failure addresses are logged in MBDATA. Set these control values to start the MemBIST engine. — Set ABORT (bit 28) to 0. — Clear PF (bit 30). Hardware will set this bit if a failure is detected. — If desired to halt whenever there is an error, set HALT (bit 29). — Set START (bit 31) to 1 to start MemBIST execution. 5. Check the MemBIST results, and if checking was enabled, observe failure data or address through MBDATA registers and MB_ERR_DATA registers: — Check MBCSR:start. 0 means MemBIST has completed. Check MBCSR:PF. 1 means a failure has occurred. — Failure data bit location accumulator will be stored in MBDATA[8, 3:0]. Up to 5 failure addresses will be placed in MBDATA[9, 7:4]. Use the “Fixed Data Pattern” mapping for these registers. — Failure data will be stored in MB_ERR_DATA[3:0][4:0] registers. Intel® 6400/6402 Advanced Memory Buffer Datasheet 137 DDR MemBIST 11.5 11.5.1 MemBIST Implementation MemBIST Block Diagram Figure 11-6. MemBIST Block Diagram GB MemBist Internal block diagram mb_raddr/mb_caddr/mb_baddr/mb_cs mbist_cmd_l[2:0] mtr drt/drc mcre2mcmb_cntl_req mcsr2mcmb_rst_req mbcsr[31:0] mbaddr[31:0] mbcsr[31:0] start_addr/end_addr Command Control CS FSM Cycle Tracker Dataput Generator raddr/caddr/baddr cs mbcavail mbstart readcmd writecmd read_idle write_idle dataput dcget raddr/caddr/baddr readcmd writecmd tstinit Address Generator MemBist Flow Control rdstart/wrstart * Refresh logic is implemented outside of MCMB block. Embedded Algorithm tstcompare tstdone wrpattern data_reset Data Tracker mbdata[319:0] mbcsr[31:0] early_read_data[71:0] late_read_data[71:0] late_write_data[71:0] early_write_data[71:0] Rev 3.0 05/22/04 138 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST 11.5.2 MB Flow Control State Machine Figure 11-7. MBFSM Diagram core_rst_l =0 M em Bist M BFSM IDLE m bstart & (wronly | wrrdcm p) Always RD_DONE W R_START lfsrdata rdidle & ~rd2wr or wridle & rd2wr W R_SEED ~ lfsrdata RD_W AIT cget & lastaddr & rd2wr RD_W RAVL (r d o ta rt & m b s rd c m p ) n ly | cget & lastaddr & ~rdw2wr lfsrseed_done W R_NXTAD Always wronly RD_AVAIL cget & ~lastaddr Always cget & rd2wr RD_NXTW R W R_AVAIL c get & ~lastaddr & ~rd2wr Always c get & ~lastaddr & rd2wr RD_NXTAD cget & lastaddr lfsrseed_done W R_W AIT ~ lfsrdata RD_SEED writeidle lfsrdata W R_DO NE ~wronly RD_START This FSM controls the MemBIST flow and generates read/write commands for MemBIST. • When MBCSR bit[31] is programmed to begin execution, the MemBIST FSM will transition out of the IDLE state to either WR_START or RD_START, depending upon the MemBIST command programmed in MBCSR:cmd. • In WR_START state, FSM will look at the decoding of DATA type selection. If LFSR data type generation is selected, FSM will go to WR_SEED state. If not, FSM will directly go to WR_NXTAD state. Intel® 6400/6402 Advanced Memory Buffer Datasheet 139 DDR MemBIST • In WR_SEED state, MemBIST will create 5 crc32 data sets and load into MBDATA4/ 5/6/7/9 from the initial seed register MBLFSRSED. When 5 sets of random data are loaded into MBDATA, the FSM will transition out of this state to WR_NXTAD state. • In the WR_NXTAD state, the next address for the operation is calculated and the address issued. The FSM then transitions to the WR_AVAIL state immediately. • The FSM will alternate between WR_NXTAD and WR_AVAIL until all writes are issued. In the WR_AVAIL state, a write command will be issued. Once the previous cycle’s DRAM timing requirements are met (indicated by cget true), the FSM leaves the WR_AVAIL state. If the write command issued was not to the last address, the FSM will transition to WR_NXTAD. If this was the last address, the FSM will go to WR_WAIT state. • In the WR_WAIT state, the FSM will wait for the timing for the last write to be met, and then will transition to the WR_DONE state. • If this is a write only operation, then the FSM will go back to the IDLE state. If this is a write with read comparison test, the FSM will go to the RD_START state. • In RD_START state, FSM will look at the decoding of DATA type selection. If LFSR data type generation is selected, FSM will go to RD_SEED state. If not, FSM will directly go to RD_NXTAD state. • In RD_SEED state, MemBIST will create 5 crc32 data sets and load into MBDATA4/ 5/6/7/9 from the initial seed register MBLFSRSED. When 5 sets of random data is set and loaded into MBDATA, FSM will transit out of this state to RD_NXTAD state. • In the RD_NXTAD state, the next address for the operation is calculated and the address issued. The FSM transitions to the RD_AVAIL state immediately. • The FSM will alternate between RD_NXTAD and RD_AVAIL until all reads are issued. In the RD_AVAIL state, a read command will be issued. Once the previous cycle’s DRAM timing requirements are met (indicated by cget true), the FSM leaves the RD_AVAIL state. If the read command issued was not to the last address, the FSM will transition to RD_NXTAD. If this was the last address, the FSM will go to RD_WAIT state. If this is a back to back read/write operation, the FSM will transit from the RD_AVAIL state to the RD_NXTWR state. • In the RD_NXTWR state, the address for the write command will be issued (which is the same as the read address previously used). The FSM then transitions to the RD_WRAVL state immediately. • From the RD_WRAVL state, if this is the last address, the FSM will go to the RD_WAIT state after meeting the DRAM timing requirements. If this is not the last address, the FSM will go back to the RD_NXTAD state again after meeting the DRAM timing requirements. • In the RD_WAIT state, the FSM will wait for the timing requirements for the last read or write to be met, and then transition to the RD_DONE state. • From the RD_DONE state the FSM will always go to the IDLE state. 140 Intel® 6400/6402 Advanced Memory Buffer Datasheet DDR MemBIST 11.5.3 CS Finite State Machine Figure 11-8. CS State Machine MemBist CSFSM ept _acc Sref Self-Refresh core_rst_l =0 IDLE Sref_request ACT Aref_request Ar ef _a cc ep t Activating AutoRefresh Go_idle RCD_met samepage & timing_met RDWT ~samepage & timing_met Precharge Intel® 6400/6402 Advanced Memory Buffer Datasheet 141 DDR MemBIST 11.5.3.1 MemBIST CSFSM This FSM creates DRAM commands for MemBIST. • When read or write command is available and tRP/tRC timing are met, MemBIST CSFSM will transit out of IDLE state to ACT state. • In ACT state, FSM will wait for tRCD timing parameter qualified and go to RDWT state. • If the next coming read or write command is in same page and DRAM timing is qualified, FSM will be looping in this state. If the next command is not in the same page or there is an auto-refresh/self-refresh request, FSM will go to PRECHARGE state. • In PRECHARGE state, FSM always go back to IDLE state. • In IDLE state, if there is a self refresh or an auto refresh request, FSM will wait for self refresh logic accept signal or auto refresh accept signal. § 142 Intel® 6400/6402 Advanced Memory Buffer Datasheet Ballout and Package Information 12 12.1 Ballout and Package Information Ballout The following section presents preliminary ballout information for the Intel 6400/6402 Advanced Memory Buffer (AMB). This ballout is subject to change and is to be used for informational purposes only. 12.2 655-Ball FBGA 0.8mm Pitch Pin Configuration Figure 12-1. Pinout Configuration 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Intel® 6400/6402 Advanced Memory Buffer Datasheet 143 Ballout and Package Information 12.3 Pin Assignments for the Advanced Memory Buffer (AMB) Table 12-1. 655-Ball FBGA 0.8 mm Pitch - Left Side 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC VSS DQ19 DQ21 VSS VDD DQS2 DQS2 VSS DQ20 2 3 VSS DQS3 DQ18 VSS DQ17 DQ23 NC NC NC NC NC NC NC NC NC NC NC VSS VSS VSS PN4 RESET VSS 4 DQ26 DQS3 VSS DQ16 DQ29 VSS NC NC NC NC NC NC NC NC NC NC NC SN0 SN1 SN2 VSS PN5 PN5 5 DQ12 VSS DQ4 DQ24 VSS DQ31 NC NC NC NC NC NC NC NC NC NC NC SN0 SN1 SN2 VSS PN13 PN13 6 VDD DQ14 DQS9 VSS DQ25 DQ27 VSS DQ28 BA1A VSS A0A CASA VSS A2A A11A VSS A15A VCCFBD SN3 SN3 VSS RFU a 7 DQS10 DQS10 VSS DQS9 DQ6 VSS DQS12 DQ30 VSS WEA CKE0A VSS BA0A A1A VSS A9A A14A VSS SN4 SN4 VSS PN12 PN12 8 DQ13 VSS DQ15 DQ7 VSS TESTLO 9 VDD DQ11 DQ9 VSS DQ5 TEST 10 DQS1 DQS1 VSS DQ3 DQ1 VSS NC NC NC NC NC NC NC NC NC NC NC RFUa SN12 SN12 VSS PN8 PN8 11 DQ10 VSS DQ8 DQS0 VSS DQS0 NC NC NC NC NC NC NC NC NC NC NC RFUa SN6 SN6 VSS PN9 PN9 12 VDD DDRC DDRC VSS DQ0 DQ2 BFUNC VSS VDD VSS VCC VSS VCC 13 TESTLO TESTLO 14 VDD VDD DDRC DQS8 VSS CB0 RFU VSS VDD VSS VCC VSS VCC VSS VCC VSS VSS VSS SN9 SN9 VSS PN10 PN10 15 VDD VSS DQS17 VDD CB2 CB3 RFU VDD VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS SN10 SN10 VSS PN11 PN11 VSS DQS8 CB1 VDD RFU VDD VSS VCC VSS VCC VSS VCC VSS VCC VCCFBD VSS SN8 SN8 VSS DQS11 DQS11 DQ22 VSS CLK2 CLK0 ODT0A CS1A A6A VSS A4A PN0 PN1 PN2 PN3 VSS VSS CLK2 CLK0 VSS RFU CS0A VSS A8A A13A PN0 PN1 PN2 PN3 PN4 VSS DQS12 VSS CKE1A RASA VSS BA2A A10A A3A A5A A7A A12A VCCFBD SN5 SN5 VSS PN6 PN6 NC NC NC NC NC NC NC NC NC NC NC VSS SN13 SN13 VSS PN7 PN7 VSS VCC VSS RFU VCCFBD SN7 SN7 VSS VSSAPLL VCCAPLL FBDRES PLLTST O RFUa These pin positions are reserved for forward clocks to be used in future AMB implementations. 144 Intel® 6400/6402 Advanced Memory Buffer Datasheet Ballout and Package Information Table 12-2. 655-Ball FBGA 0.8 mm Pitch - Right Side 16 A B C D E F VDD VDD DQS17 CB6 VSS CB4 TEST LO VSS VDD VSS VCC VSS VCC VSS VCC VSS VSS VCCFBD VSS VSS VSS VSS 17 TEST TEST VSS CB7 CB5 VDD 18 VDD DDRC DDRC VSS DQS16 DQ62 19 DQ52 VSS DQ54 DQS16 VSS DQ60 20 DQS15 DQS15 VSS DQ63 DQ61 VSS 21 VDD DQ53 DQ55 VSS DQ57 TEST 22 DQ49 VSS DQ51 DQ59 VSS TEST 23 DQS6 DQS6 VSS DQS7 DQ58 VSS 24 VDD DQ50 DQS7 VSS DQ39 DQ37 25 DQ48 VSS DQ56 DQ36 VSS DQ35 26 DQ38 DQS13 VSS DQ44 DQ33 VSS 27 VDD DQS13 DQ46 VSS DQ45 DQS5 VSS DQS14 DQS14 VSS DQ43 VDD DQ47 DQ41 VSS 28 29 G H J K L M N P R T U V W Y AA AB RFU VDD VSS VCC VSS VCC VSS VCC VSS VCC VCCFBD VSS SS0 SS0 VSS SN11 RFU VSS VDD VSS VCC VSS VCC VSS VCC VSS RFU VCCFBD SS1 SS1 VSS VSS NC NC NC NC NC NC NC NC NC NC NC VSS SS2 SS2 VSS SCK NC NC NC NC NC NC NC NC NC NC NC VCCFBD SS3 SS3 VSS TESTLO _AB20 TEST LO_AC2 0 NC NC NC NC NC NC NC NC NC NC NC RFUa SS4 SS4 VSS PS0 DQS4 VSS RASB ODT0B VSS CS0B A0B VSS A6B A11B A8B RFUa SS9 SS9 VSS PS1 DQS4 DQ34 VSS CS1B CASB VSS A2B A4B VSS A9B A15B VSS SS5 SS5 VSS PS2 VSS DQ32 RFU VSS WEB BA1B VSS A1B A10B VSS A14B A13B SS6 SS6 VSS PS3 NC NC NC NC NC NC NC NC NC NC SA0 A12 B SS7 SS7 VSS PS4 NC NC NC NC NC NC NC NC NC NC SCL SA2 SS8 SS8 VSS RFUa NC NC NC NC NC NC NC NC NC NC SDA SA1 VSS VSS PS9 VDDSPD DQS5 VSS CLK3 CLK1 VSS CKE0B BA0B VSS A3B A7B PS8 PS7 PS6 PS5 PS9 VSS DQ40 DQ42 VSS CLK3 CLK1 VSS BA2B CKE1B VSS A5B PS8 PS7 PS6 PS5 VSS AC RFU SN11 VSS SCK PS0 PS1 PS2 PS3 PS4 RFUa VSS These pin positions are reserved for forward clocks to be used in future AMB implementations. Table 12-3. Advanced Memory Buffer Signals By Ball Number (Sheet 1 of 7) Ball No. A3 A4 A5 A6 A7 A8 A9 VSS DQ26 DQ12 VDD DQS10 DQ13 VDD Signal Ball No. B15 B16 B17 B18 B19 B20 B21 VSS VDD TESTLO DDRC_B18 VSS DQS15 DQ53 Signal Ball No. C25 C26 C27 C28 C29 D1 D2 DQ56 VSS DQ46 DQS14 VDD DQ19 DQS2 Signal Intel® 6400/6402 Advanced Memory Buffer Datasheet 145 Ballout and Package Information Table 12-3. Advanced Memory Buffer Signals By Ball Number (Sheet 2 of 7) Ball No. A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 DDQS1 DQ10 VDD TESTLO VDD VDD VDD TEST VDD DQ52 DQS15 VDD DQ49 DQS6 VDD DQ48 DQ38 VDD VDD DQS3 DQS3 VSS DQ14 DQS10 VSS DQ11 DQS1 VSS DDRC_B12 TESTLO VDD VSS DQ25 DQ6 VSS DQ5 DQ1 VSS DQ0 CB1 VSS CB2 Signal Ball No. B22 B23 B24 B25 B26 B27 B28 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 VSS DQS6 DQ50 VSS DQS13 DQS13 VSS VSS DQS2 DQ18 VSS DQ4 DQS9 VSS DQ15 DQ9 VSS DQ8 DDRC_C12 VSS DDRC_C14 DQS17 DQS17 VSS DDRC_C18 DQ54 VSS DQ55 DQ51 VSS DQS7 CB0 CB3 CB4 VDD DQ62 DQ60 VSS TEST TEST VSS DQ37 Signal Ball No. D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 E1 E2 E3 E4 G23 G24 G25 G26 G27 G28 G29 H1 H2 H3 H4 VSS DQ16 DQ24 VSS DQS9 DQ7 VSS DQ3 DQS0 VSS DQS8 DQS8 VDD CB6 CB7 VSS DQS16 DQ63 VSS DQ59 DQS7 VSS DQ36 DQ44 VSS DQS14 DQ47 DQ21 VSS DQ17 DQ29 DQS4 VSS NC NC NC DQS5 DQ40 DQ22 VSS NC NC Signal 146 Intel® 6400/6402 Advanced Memory Buffer Datasheet Ballout and Package Information Table 12-3. Advanced Memory Buffer Signals By Ball Number (Sheet 3 of 7) Ball No. E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 VSS CB5 DQS16 VSS DQ61 DQ57 VSS DQ58 DQ39 VSS DQ33 DQ45 VSS DQ41 VSS DQ20 DQ23 VSS DQ31 DQ27 VSS TESTLO TEST VSS DQS0 -> DQS0 DQ2 VDD NC NC NC BA1A VSS CKE1A NC NC NC VDD VSS VDD VSS VDD VSS Signal Ball No. F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 DQ35 VSS DQS5 DQ43 VSS DQS11 DQS11 NC NC NC VSS DQS12 DQS12 NC NC NC BFUNC RFU RFU RFU TESTLO RFU RFU NC NC NC DQS4 VSS VCC VSS VCC VSS VCC VSS NC NC NC ODT0B CS1B VSS NC NC Signal Ball No. H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 J1 J2 L21 L22 L23 L24 L25 L26 L27 L28 L29 M1 M2 M3 M4 M5 M6 NC DQ28 DQ30 VSS NC NC NC VSS VDD VSS VDD VSS VDD VSS NC NC NC VSS DQ34 DQ32 NC NC NC VSS DQ42 VSS CLK2 NC VSS CASB WEB NC NC NC VSS CLK1 ODT0A RFU NC NC NC CASA Signal Intel® 6400/6402 Advanced Memory Buffer Datasheet 147 Ballout and Package Information Table 12-3. Advanced Memory Buffer Signals By Ball Number (Sheet 4 of 7) Ball No. J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 VDD NC NC NC RASB VSS RFU NC NC NC CLK3 VSS CLK2 CLK0 NC NC NC VSS WEA RASA NC NC NC CS1A CS0A NC NC NC VSS BA0A A10A NC NC NC VCC VSS VCC VSS VCC VSS VCC NC Signal Ball No. K27 K28 K29 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 NC CLK1 CLK3 CLK0 VSS NC NC NC A0A CKE0A VSS NC NC NC VCC VSS VCC VSS VCC VSS VCC NC NC NC NC VSS VCC VSS VCC VSS VCC VSS NC NC NC VSS A4B A1B NC NC NC VSS Signal Ball No. M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 T1 T2 T3 T4 T5 T6 T7 T8 VSS BA2A NC NC NC VSS VCC VSS VCC VSS VCC VSS NC NC NC CS0B VSS BA1B NC NC NC CKE0B VSS NC NC NC A6B VSS A10B NC NC NC A3B VSS A4A A13A NC NC NC VSS A9A A7A Signal 148 Intel® 6400/6402 Advanced Memory Buffer Datasheet Ballout and Package Information Table 12-3. Advanced Memory Buffer Signals By Ball Number (Sheet 5 of 7) Ball No. N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 P1 P2 P3 P4 P5 P6 P7 P8 P9 T28 T29 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 NC NC A0B A2B VSS NC NC NC BA0B BA2B A6A VSS NC NC NC A2A A1A A3A NC A7B A5B PN0 PN0 NC NC NC A15A A14A A12A NC NC NC RFU VCCFBD VSS VSS VSS VCCFBD RFU NC NC NC Signal Ball No. P29 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 W1 CKE1B VSS A8A NC NC NC A11A VSS A5A NC NC NC VCC VSS VCC VSS VCC VSS VCC VCCFBD VSS RFUa RFUa VCCFBD VSS VSS VSS VCCFBD VSS VCCFBD VSS VCCFBD RFUa RFUa VSS A13B A12B SA2 SA1 PS7 PS7 PN2 Signal Ball No. T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 NC NC NC VSS VCC VSS VCC VSS VCC VSS NC NC NC A11B A9B VSS NC NC NC SS0 SS1 -> SS1 SS2 SS3 SS4 SS9 SS5 SS6 SS7 SS8 VSS PS6 PS6 PN3 PN3 VSS SN2 SN2 SN3 SN4 SN5 SN13 SN12 Signal Intel® 6400/6402 Advanced Memory Buffer Datasheet 149 Ballout and Package Information Table 12-3. Advanced Memory Buffer Signals By Ball Number (Sheet 6 of 7) Ball No. U22 U23 U24 U25 U26 U27 U28 U29 V1 V2 V3 V4 V5 V6 V7 A8B A15B A14B SA0 SCL SDA PS8 PS8 PN1 PN1 VSS SN0 SN0 VCCFBD VSS Signal Ball No. W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 PN2 VSS SN1 SN1 SN3 SN4 SN5 SN13 SN12 SN6 SN7 SN8 SN9 SN10 VSS Signal Ball No. Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 SN6 SN7 SN8 SN9 SN10 VSS SS0 SS1 SS2 SS3 SS4 SS9 SS5 SS6 SS7 Signal These pin positions are reserved for forward clocks to be used in future AMB implementations. Y26 Y27 Y28 Y29 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 SS8 VSS PS5 PS5 VSS PN4 PN4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AC3 AC4 AC5 AC6 PN12 PN6 PN7 PN8 PN9 VSSAPLL VCCAPLL PN10 PN11 VSS SN11 VSS SCK TESTLO_AB20 PS0 PS1 PS2 PS3 PS4 RFUa VDDSPD VSS VSS PN5 PN13 RFUa AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 SCK TESTLO_AC20 PS0 PS1 PS2 PS3 PS4 RFUa VSS 150 Intel® 6400/6402 Advanced Memory Buffer Datasheet Ballout and Package Information Table 12-3. Advanced Memory Buffer Signals By Ball Number (Sheet 7 of 7) Ball No. AA23 AA24 AA25 AA26 AA27 AA28 AA29 AB2 AB3 AB4 AB5 AB6 VSS VSS VSS VSS PS9 PS9 VSS VSS RESET PN5 PN13 RFUa Signal Ball No. AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 PN12 PN6 PN7 PN8 PN9 FBDRES PLLTSTO PN10 PN11 RFU SN11 VSS Signal Ball No. Signal These pin positions are reserved for forward clocks to be used in future AMB implementations. Intel® 6400/6402 Advanced Memory Buffer Datasheet 151 Ballout and Package Information 12.4 Package Information Figure 12-2. Bottom View 152 Intel® 6400/6402 Advanced Memory Buffer Datasheet Ballout and Package Information Figure 12-3. Top View T Intel® 6400/6402 Advanced Memory Buffer Datasheet 153 Ballout and Package Information Figure 12-4. Package Stackup T § 154 Intel® 6400/6402 Advanced Memory Buffer Datasheet Signal Lists 13 13.1 Signal Lists Conventions The terms assertion and de-assertion are used extensively when describing signals, to avoid confusion when working with a mix of active-high and active-low signals. The term assert, or assertion, indicates that the signal is active, independent of whether the active level is represented by a high or low voltage. The term de-assert, or deassertion, indicates that the signal is inactive. Signal names may or may not have a “#” at appended to them. The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when at the high voltage level. Differential pairs use the “#” to indicate the “negative” signal in the pair. The “positive” signal in When discussing data values used inside the component, the logical value is used; that is, a data value described as “1101b” would appear as “1101b” on an activehigh bus, and as “0010b” on an active-low bus. When discussing the assertion of a value on the actual signal, the physical value is used; that is, asserting an active-low signal produces a “0” value on the signal. Typical frequencies of operation for the fastest operating modes are indicated. Test guardbands are not included. No frequency is mentioned for asynchronous or analog signals. Some signals or groups of signals have multiple versions. These signal groups may represent distinct but similar ports or interfaces, or may represent identical copies of the signal used to reduce loading effects. Table 13-1 shows the conventions used in this document. Curly-bracketed non-trailing numerical indices, for example, “{X/Y}”, represent replications of major buses. Square-bracketed numerical indices, , “[n:m]” represent functionally similar but logically distinct bus signals; each signal provides an independent control, and may or may not be asserted at the same time as the other signals in the grouping. In contrast, trailing curly-bracketed numerical indices, for example, “{x/y}” typically represent identical duplicates of a signal; such duplicates are provided for electrical reasons. Table 13-1. Signal Naming Conventions Convention RR{0/1/2}XX RR[2:0] RR{0/1/2} RR# or RR[2:0]# Expands to Expands to: RR0XX, RR1XX, and RR2XX. This denotes similar signals on replicated buses. Expands to: RR[2], RR[1], and RR[0]. This denotes a bus. Expands to: RR2, RR1, and RR0. This denotes electrical duplicates. Denotes an active low signal or bus. Table 13-2 lists the reference terminology used for signal types. Intel® 6400/6402 Advanced Memory Buffer Datasheet 155 Signal Lists Table 13-2. Buffer Signal Types Buffer Direction I O A I/O Input signal Output signal Analog Bidirectional (input/output) signal Description 13.2 Intel 6400/6402 Advanced Memory Buffer (AMB) Pin Description List Table 13-3 describes the Intel 6400/6402 Advanced Memory Buffer (AMB) packagepins. Table 13-3. Pin Description (Sheet 1 of 2) Signal Channel Interface PN[13:0] PN[13:0] SN[13:0] SN[13:0] PS[9:0] PS[9:0] SS[9:0] O O I I I I O Northbound Output Data: High speed serial signal. Read path from AMB toward host on primary side of the DIMM connector. Northbound Output Data Complement Northbound Input Data: High speed serial signal. Read path from the previous AMB toward this AMB on secondary side of the DIMM connector. Northbound Input Data Complement Southbound Input Data: High speed serial signal. Write path from host toward AMB on primary side of the DIMM connector. Southbound Input Data Complement Southbound Output Data: High speed serial signal. Write path from this AMB toward next AMB on secondary side of the DIMM connector. These output buffers are disabled for the last AMB on the channel. Southbound Output Data Complement External precision resistor connected to VCC. On-die termination calibrated against this resistor. Type Description SS[9:0] FBDRES DRAM Interface CB[7:0] DQ[63:0] DQS[17:0] DQS[17:0] A0A-A15A, A0B-A15B BA0A-BA2A, BA0B-BA2B RASA, RASB CASA, CASB WEA, WEB CS0A-CS1A, CS0B-CS1B CKE0A-CKE1A, CKE0B-CKE1B O A I/O I/O I/O I/O O O O O O O Check bits Data Data Strobe: DDR2 data and check-bit strobe. Data Strobe Complement: DDR2 data and check-bit strobe complements. Address: Used for providing multiplexed row and column address to SDRAM. Bank Active: Used to select the bank within a rank. Row Address Strobe: Used with CS, CAS, and WE to specify the SDRAM command. Column Address Strobe: Used with CS, RAS, and WE to specify the SDRAM command. Write Enable: Used with CS, CAS, and RAS to specify the SDRAM command. Chip Select: Used with CAS, RAS, and WE to specify the SDRAM command. These signals are used for selecting one of two SDRAM ranks. CS0 is used to select the first rank and CS1 is used to select the second rank. Clock Enable: DIMM command register enable. O 156 Intel® 6400/6402 Advanced Memory Buffer Datasheet Signal Lists Table 13-3. Pin Description (Sheet 2 of 2) Signal ODT0A, ODT0B CLK[3:0] CLK[3:0] DDR Compensation DDRC_C14 DDRC_B18 DDRC_C18 DDRC_B12 DDRC_C12 Clocking SCK I AMB Clock: This is one of the two differential reference clock inputs to the Phase Locked Loop in the AMB core. Phase Locked Loops in the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel. AMB Clock Complement: This is the other differential reference clock input to the Phase Locked Loop in the AMB core. Phase Locked Loops in the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel. VCC: PLL Analog Voltage for the core PLL (See Chapter 8, Clocking) VSS: PLL Analog Voltage for the core PLL (See Chapter 8, Clocking) A A A A A DDR Compensation Common: Common return (ground) pin for DDRC_B18 and DDRC_C18 DDR Compensation Ball Resistor connected to Compensation Common above DDR Compensation Ball Resistor connected to Compensation Common above DDR Compensation Ball Resistor connected to VSS DDR Compensation Ball Resistor connected to VDD Type O O O Description DIMM On-Die-Termination: Dynamic ODT enables for each DIMM on the channel. Clock: Clocks to DRAMs. CLK0 and CLK1 are always used. CLK2 and CLK3 are optional and may be disabled when not required. Clock Complement: Clocks to DRAMs. SCK I VCCAPLL VSSAPLL System Management SCL SDA SA[2:0] Reset RESET# Miscellaneous Test TEST (6 pins) TESTLO (3 pins) TESTLO_AB20 TESTLO_AC20 Power Supplies VCC (2pins) VCCFBD (8 pins) VDD (24 pins) VSS (156 pins) VDDSPD Other Pins BFUNC A A I/O I/O SMBus Clock SMBus Address/Data DIMM Select ID Power Good Reset NC A A A Pin for debug and test. Must be floated on DIMM. Pin for debug and test. Must be tied to Ground on DIMM Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS. Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS. A A A A A 1.5V nominal supply for core logic 1.5V nominal supply for FBD high speed I/O 1.8V nominal supply for DDR I/O Ground 3.3V nominal supply for SMB receivers and ESD diodes I Buffer Function Bit: When BFUNC = 0, AMB is used as a regular buffer on FB-DIMM. When BFUNC = 1, AMB is used as either a repeater or a buffer for LAI function. On FB-DIMM, BFUNC is tied to Ground Reserved for Future Use. Must be floated on DIMM. RFU pins denoted by “a” are reserved for forwarded clocks in future AMB implementations. RFU (18 pins) Other No Connect Pins NC (129 pins) NC NC No Connect pins Intel® 6400/6402 Advanced Memory Buffer Datasheet 157 Signal Lists Table 13-4 lists the signal types and pin counts. Table 13-4. Pin Count Signal Channel Interface DRAM Interface DDR Compensation Clocking System Management Reset Miscellaneous Test Power Supplies Other Pins Sub-total Other No Connect Pins Total Pin Count 97 170 5 5 5 1 11 213 19 526 129 655 § 158 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14 14.1 Registers Access Mechanisms The Intel 6400/6402 Advanced Memory Buffer (AMB) component supports PCI configuration space access as defined in the PCI Local Bus Specification, Rev.2.2. The internal registers of the AMB can be accessed in byte (8-bit), word (16-bit), or double word (32-bit) quantities. All multi-byte numeric fields use “little-endian” ordering (that is, lower addresses contain the least significant parts of the field). As a memory buffer (not a PCI device or bridge) the AMB is not fully compliant with this mechanism with respect to the standard registers (those with offsets 0-3Fh). The AMB will not be mapped into the host system's PCI Plug and Play hierarchy, but is accessed through a method that is host controller implementation specific. Problems will occur if the host system maps the registers into the PCI PnP hierarchy. Configuration accesses are transported on the FBD link as configuration read and write commands, which mimic the corresponding PCI commands. The AMB responds to any device encoded in an FBD command. The AMB responds only to SM Bus requests that match the NodeID. The “Device:” mentioned in the heading of each configuration register table does not designate the PCI device; it designates the SM Bus node. 14.1.1 Conflict Resolution and Usage Model Limitations AMB accepts configuration register reads and writes through the FBD link and through SMBus transactions. In Logic Analyzer Interface (LAI) mode, registers are not accessible through the in-band FBD link configuration read/write commands. Registers do not incur read side-effects. 14.1.2 FBD Data on Configuration Read Returns FBD read return data from the AMB is described in the FB-DIMM Architecture and Protocol Specification. Configuration reads are sent in northbound data frames. Only the bottom four bytes of this data are defined for a configuration access. The rest of the bytes in the read return are undefined. Legal CRCs are generated for these undefined inbound bytes. 14.1.3 Non-Existent Register Bits To comply with the PCI specification, accesses to non-existent registers and bits will be treated as follows: Table 14-1. Access to “Non-existent” Register Bits Access to Registers in unimplemented functions Registers not listed Reserved bits in registers Writes Have no effect Have no effect Software must read-modifywrite to preserve the value Reads AMB returns -1 AMB returns all zeroes AMB returns implementation specific values Intel® 6400/6402 Advanced Memory Buffer Datasheet 159 Registers 14.1.4 Register Attribute Definition Table 14-2. Register Attributes Definitions Attribute Read Only Write Only Read/Write Read/Write / Clear Read/Write / Set Read/Write Lock Read/Write Once Abbreviation RO WO RW RWC Description This bit is set by the hardware. Software can only read the bit. Writes to the register have no effect. The bit is not implemented as a bit. The write causes some hardware event to take place. Read returns all zeroes. The bit can be read or written by software. The bit can be either read or cleared by software. In order to clear a bit, the software must write a one to it. Writing a zero to an RWC bit will have no effect. Hardware will set this bit. The bit can be either read or set by software. In order to set this RWS bit, the software must write a one to it. Writing a zero to an RWS bit will have no effect. Hardware will clear this bit. The bit can be read and written by software. Hardware or a configuration bit can lock this bit and prevent it from being updated. The bit can be read by software. It can also be written by software but the hardware prevents writing/setting it more than once without a prior “effective” reset. This protection applies on a byte-by-byte basis. For example, if a two-bit RWO field straddles a byte boundary and only one byte is written, then the written bit cannot be rewritten (unless reset). However, the unwritten bit can still be written once. This is a special form of RWL The bit field can be read by software. Only a restricted set of values can be written through a configuration write in-band from the host. Illegal values will be aborted and dropped. The bit is “sticky” or unchanged by a link reset. These bits can only be defaulted by a power-up reset. RWS RWL RWO Read/Restricted RRW Write Sticky All of the above with “ST” appended to the end RV Reserved This bit is reserved for future expansion and must not be written. The PCI Local Bus Specification, Revision 2.2 requires that reserved bits must be preserved. Any software that modifies a register that contains a reserved bit is responsible for reading the register, modifying the desired bits, and writing back the result. 160 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.1.5 Binary Number Notation When references are made to binary numbers, the following notation is used: n’bXX n - number of digits b - indicates binary XX - binary value For example, 2’b01 is two binary digital of value “01”. 14.1.6 Function Mapping The following functions are described in this chapter: 0) PCI Standard Header Identification Registers 1) FBD Link Registers 2) Implementation Specific FBD Registers 3) DDR and Miscellaneous Registers 4) Implementation Specific DDR Initialization and Calibration Registers 5) DFX Registers 6) Bring-up and Debug Registers Table 14-3. Function Mapping Legend Fill RegName Reserved RegName Description Required Architected Register”RegName” in these bytes Reserved Register for future architecture in these bytes Optional Architected Register”RegName” in these bytes • No Implementation Specific Registers usage recommended Unused Register location available for Implementation Specific use Intel® 6400/6402 Advanced Memory Buffer Datasheet 161 Registers Table 14-4. Function 0: PCI Standard Header Identification Registers DID VID 00h 04h CCR HDR RID 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h RESERVED 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh 162 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Table 14-5. Function 1: FBD Link Registers 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch FBDS3 FBDS2 FBDS1 FBDS0 40h 44h 48h 4Ch LINKPARCUR LINKPARNXT FBDNBC FGCUR FBDNBC FGNXT FBDSBC FGCUR FBDSBC FGNXT 50h 54h 58h MODES FEATURES FBDLIS FBDLOCKTO FBDLS FBDHAC RECALDU R 5Ch 60h 64h 68h 6Ch 70h 74h SYNCTR AININT NBCALSTATUS SBCALSTATUS 78h 7Ch C2DINCRC UR C2DINCR NXT CMD2DAT ACUR CMD2DA TANXT SPDPAR23CUR SPDPAR67CUR SPDPAR1011CUR RECFBD1 RECFBD3 RECFBD5 RECFBD7 RECFBD9 SPDPAR23NXT SPDPAR67NXT SPDPAR1011NXT EMASK FERR NERR RECCFG RECFBD0 RECFBD2 RECFBD4 RECFBD6 RECFBD8 SPDPAR01NXT SPDPAR45NXT SPDPAR89NXT SPDPAR 13NXT SPDPAR 12NXT CBC 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh SPDPAR01CUR SPDPAR45CUR SPDPAR89CUR SPDPAR 13CUR SPDPAR 12CUR Intel® 6400/6402 Advanced Memory Buffer Datasheet 163 Registers Table 14-6. Function 2: Implementation Specific FBD Registers 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh 164 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Table 14-7. Function 3: DDR and Miscellaneous Registers 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch MBCSR MBADDR MBDATA0 MBDATA1 MBDATA2 MBDATA3 MBDATA4 MBDATA5 MBDATA6 MBDATA7 MBDATA8 MBDATA9 DAREFTC MTR DSREFTC DRT DRC 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch MB_ERR_DATA00 MB_ERR_DATA01 MB_ERR_DATA02 MB_ERR_DATA03 MB_ERR_DATA04 MB_START_ADDR MB_END_ADDR MB_LFSR MBFADDRPTR UPDATED TEMPHI TEMPMID TEMP TEMPLO TEMPSTAT 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh Intel® 6400/6402 Advanced Memory Buffer Datasheet 165 Registers Table 14-8. Function 4: Implementation Specific DDR Initialization and Calibration Registers 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch DCALCSR DCALADDR DCALDATA 3 DCALDATA 7 DCALDATA 11 DCALDATA 15 DCALDATA 19 DCALDATA 23 DCALDATA 27 DCALDATA 31 DCALDAT A35 DCALDAT A39 DCALDAT A43 DCALDAT A47 DCALDAT A51 DCALDAT A55 DCALDATA5 9 DCALDATA6 3 DCALDATA6 7 DCALDATA7 1 DCALDATA5 8 DCALDATA6 2 DCALDATA6 6 DCALDATA7 0 DCALDATA5 7 DCALDATA6 1 DCALDATA6 5 DCALDATA6 9 DCALDATA5 6 DCALDATA6 0 DCALDATA6 4 DCALDATA6 8 80h 84h 88h 8Ch 90h 94h 98h DDBISTLM RCVENAC DSRETC DQSFAIL1 9Ch A0h A4h A8h ACh DRRTC00 DRRTC01 DQSOFCS00 DQSOFCS01 DQSOFCS10 DQSOFCS11 DQSOFC S12 DQSOFC S02 DRAMDLLC WPTRTC0 WPTRT C1 DDQSCVDP0 DDQSCVDP1 DDQSCADP0 DDQSCADP1 DRRTC00 DRRTC0 2 B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h 40h 44h DCALDATA 0 DCALDATA 4 DCALDATA 8 DCALDATA 12 DCALDATA 16 DCALDATA 20 DCALDATA 24 DCALDATA 28 DCALDAT A32 DCALDAT A36 DCALDAT A40 DCALDAT A44 DCALDAT A48 DCALDAT A52 DCALDATA 2 DCALDATA 6 DCALDATA 10 DCALDATA 14 DCALDATA 18 DCALDATA 22 DCALDATA 26 DCALDATA 30 DCALDAT A34 DCALDAT A38 DCALDAT A42 DCALDAT A46 DCALDAT A50 DCALDAT A54 DCALDATA 1 DCALDATA 5 DCALDATA 9 DCALDATA 13 DCALDATA 17 DCALDATA 21 DCALDATA 25 DCALDATA 29 DCALDAT A33 DCALDAT A37 DCALDAT A41 DCALDAT A45 DCALDAT A49 DCALDAT A53 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch FIVESREG AAAAREG DIOMON ODTZTC DRAMISCTL DDR2O DTC E8h ECh F0h F4h F8h FCh 166 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Table 14-9. Function 5: DFX Registers RESERVED RESERVED RESERVED RESERVED 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h TRANSCFG TRANDERR1 TRANDERR3 TRANDERR5 TRANDERR7 TRANDERR0 TRANDERR2 TRANDERR4 TRANDERR6 TRANDERR8 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch STUCKL EICNTL EVENT EVBUS EVENTSEL0 EVENTSEL1 EVENTSEL2 LAI SBMATCHU SBMATCHL0 SBMATCHL1 SBMATCHL2 SBMASKU SBMASKL0 SBMASKL1 SBMASKL2 MMEVENTSEL 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh Intel® 6400/6402 Advanced Memory Buffer Datasheet 167 Registers Table 14-10. Function 6: Bring-up and Debug Registers Register Bit Location RESERVED 04h 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h NBFIBINIT NBIBISTMISC NBFIBPORTCTL NBFIBPGCTL NBFIBPATTBUF1 NBFIBTXMSK NBFIBRXMSK NBFIBTXSHFT NBFIBRXSHFT NBFIBRXLNERR NBFIBPATTBUF2 NBFIBPATTBUF2EN SBFIBINIT SBIBISTMISC SBFIBPGCTL SBFIBRXMSK SBFIBTXSHFT SBFIBRXSHFT SBFIBRXLNERR SBFIBPATTBUF2 SBFIBPATTBUF2EN 84h 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h F8h 168 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.2 14.2.1 PCI Standard Header Identification Registers (Function 0) VID: Vendor Identification Register This register identifies Intel as the manufacturer of the AMB. Device: NodeID Function: 0 Offset: 00h Bit 15:0 Attr RO Default 8086h Description Vendor Identification Number The value assigned to Intel. 14.2.2 DID: Device Identification Register These registers combined with the vendor identification register uniquely identifies the AMB Devices. Device: NodeID Function: 0 Offset: 02h Bit 15:0 Attr RO Default A620h Description Device Identification Number Identifies each function of the AMB 14.2.3 RID: Revision Identification Register This register contains the revision number of the AMB. Device: NodeID Function: 0 Offset: 08h Bit 7:0 Attr RO Default 10h Description Revision Identification Number: RID “00h” = A0 stepping “01h” = A1 stepping “02h” = A2 stepping “10h” = B0 stepping Intel® 6400/6402 Advanced Memory Buffer Datasheet 169 Registers 14.2.4 CCR: Class Code Register This register contains the Class Code for the AMB, specifying the device function. Device: NodeID Function: 0 Offset: 09h Bit 23:16 Attr RO Default 05h Description Base Class. This field indicates the general device category. For the AMB, this field is hardwired to 05h, indicating it is a “memory controller”. Sub-Class. This field qualifies the Base Class, providing a more detailed specification of the device function. For the AMB, this field is hardwired to 00h, indicating it is a “RAM”. Register-Level Programming Interface. This field identifies a specific programming interface (if any), that device independent software can use to interact with the device. There are no such interfaces defined for “memory controllers”. 15:8 RO 00h 7:0 RO 00h 14.2.5 HDR: Header Type Register This register identifies the header layout of the configuration space. Device: NodeID Function: 0 Offset: 0Eh Bit 7 Attr RO Default 1 Description Multi-function Device. Selects whether this is a multi-function device, that may have alternative configuration layouts. The AMB has more than the 256 bytes of configuration registers allotted to a single function. Therefore, the AMB is defined to be a multifunction device, and this bit is hardwired to 1. Configuration Layout. This field identifies the format of the 10h through 3Fh space. The AMB uses header type “00”: these bits are hardwired to 00h. 6:0 RO 00h 14.3 14.3.1 14.3.1.1 FBD Link Registers (Function 1) FBD Link Control and Status FBDS0: FBD Status 0 This register contains copies of status bits returned by the AMB in the most recent northbound status frame when SYNC command R[1:0] field is 2’b00. In the absence of SYNCs to this register, this register is not updated. Device: NodeID Function: 1 Offset: 40h Bit 7:5 4 Att r RV RO Default 0h 0h Reserved SP: Parity: This bit contains an odd parity bit that covers the S[3:0] field. Description 170 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 1 Offset: 40h Bit 3 2:1 Att r RO RO Default 0h 0h Description S3: Northbound Debug Event (1 = asserted, 0 = inactive): This bit is used to communicate debug events to the host. S[2:1]: Thermal Trip: This field indicates various thermal conditions of the AMB as follows: • 00 – Below TEMPLO • 01 – Above TEMPLO • 10 – Above TEMPMID and falling • 11 – Above TEMPMID and rising The TEMPLO threshold is generally used to inform the host to accelerate refresh events. The TEMPMID threshold is generally used to inform the host that a thermal limit has been exceeded and that thermal throttling is needed. Refer to the RAS chapter for more details on thermal management. S0: ERROR Asserted: This bit indicates an error has been detected by the AMB. Errors can be alert or other type. 0 RO 0h 14.3.1.2 FBDS1: FBD Status 1 This register contains copies of status bits returned by the AMB in the most recent northbound status frame when SYNC command R[1:0] field is 2’b01. Device: NodeID Function: 1 Offset: 41h Bit 7:5 4 3:1 0 Att r RV RO RV RO Default 0h 0h 0h 0h Reserved SP: Parity: This bit contains an odd parity bit that covers the S[3:0] field. Reserved S0: Data Merge Error: This bit indicates that the northbound data merge alignment logic of an intermediate AMB cannot met the timing required to merge its DRAM data into the northbound data stream when required. Refer to the initialization chapter for details. Description 14.3.1.3 FBDS2: FBD Status 2 This register contains copies of status bits returned by the AMB in the most recent northbound status frame when SYNC command R[1:0] field is 2’b10. Device: NodeID Function: 1 Offset: 42h Bit 7:5 4 3:0 Att r RV RO RV Default 0h 0h 0h Reserved SP: Parity: This bit contains an odd parity bit that covers the S[3:0] field. Reserved Description Intel® 6400/6402 Advanced Memory Buffer Datasheet 171 Registers 14.3.1.4 FBDS3: FBD Status 3 This register contains copies of bits that were returned by the AMB in the most recent northbound status frame when the SYNC command R[1:0] field is 2’b11. This can also be written with an override value that will be returned if selected during SYNC command. Device: NodeID Function: 1 Offset: 43h Bit 7:6 5 Att r RV RW Default 0h 0h Reserved OVREN: Use values written by user. Setting this bit causes the values specified in the lower 5 bits of this register returned as-is if requested by SYNC command. USRPAR: User Specified parity for USRVAL USRVAL: User Specified value Description 4 3:0 RW RW 1h 0h 14.3.1.5 MODES: Operating Mode This register contains overview configuration status of chip. Device: NodeID Function: 1 Offset: 5Ch Bit 7 6 5 4 3:0 Att r RO RO RO RO RV Default 1 0 0 0 0 Description NORMAL: • 1 = Normal AMB Buffer LAI: • 1 = LAI REPEATER: • 1 = Repeater TRANSPARENT: • 1 = Transparent Test Mode Reserved 14.3.1.6 FEATURES: Capabilities This register reports optional capabilities of this DIMM. Device: NodeID Function: 1 Offset: 60h Bit 31:15 14:11 Attr RV RO Default 0h 0011 Reserved DDRFREQ: DDR2 frequencies supported • 1XXX = reserved • X1XX = DDR2-800 • XX1X = DDR2-667 • XXX1 = DDR2-533 Description 172 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 1 Offset: 60h Bit 10 Attr RO Default 0 Description VARLAT: Variable Read Latency Mode • 1 = Support Variable Read Latency on data returns • 0 = Not supported LAI: Logic Analyzer Interface Mode • 1 = Support remapping DDR interface as Logic Analyzer Interface • 0 = Not supported DMASK: Data Mask for non-ECC Write Data • 1 = Support data mask with non-ECC Write • 0 = Not supported L0S: Low Power Link State • 1 = Support L0s state • 0 = Not supported NBWC: Northbound Width Capability • 1XXXX = 14 bits NB width supported • X1XXX = 14bits fail over to 13 bits mode supported. • XX1XX = 13 bits NB width supported • XXX1X = 13 bits fail over to 12 bits mode supported. SBWC: Southbound Width Capability • X1 = 10 SB bits: Device supports 10-bits and 10-bit fail-over to 9-bits. Both configurations deliver 72-bits of data payload frame. • 1X = Reserved 9 RO 1 8 RO 0 7 RO 0 6:2 RO 1Eh 1:0 RO 01 14.3.1.7 FBDLIS: FBD Link Initialization Status This register reports FBD initialization status and is only valid when the link is up since it is not sticky. Device: NodeID Function: 1 Offset: 64h Bit 31:20 19 18 Attr RV RO ROST Default 0 0 0 Reserved DATAMERGEERROR: NorthBound Data Merge Error • 1 = NB merge error NBMERGEDIS: NorthBound Merge Disable Set by TS2 packet addressed to it • 1 = Disable NB merge • Note: state in AMB should be sticky through fast link reset until new TS2 resets bit or hard pin reset NBWCFG: Northbound width configuration set by TS3 • See table in FBD Architecture & Protocol Specification for full decoding • [5:4] = Selects 14, 13 or 12 lane operation. = Protocol Selection[1:0] out TS3 Protocol Selection[3:0] • [3:0] - Selects none or one lane to map out = NB Channel Configuration [3:0] in TS3 SBWCFG: Southbound width capability set by TS3 • See Table in FBD Architecture & Protocol Specification for full decoding • [3:0] - Selects none or one lane to map out Reserved Description 17:12 RO 3Fh 11:8 RO Fh 7 RV 0 Intel® 6400/6402 Advanced Memory Buffer Datasheet 173 Registers Device: NodeID Function: 1 Offset: 64h Bit 6 Attr RO Default 0 Description TS2RESP: Responded to a TS2 packet addressed to it 1: TS2 was addressed to this AMB • In polling mode - DS matches TS2 AMB_ID value • Undefined in other states SB2NBLBMAP: Specifies if upper or lower SB lanes are reflected in TS1 Valid only during testing phase (TS1) 1 = upper SB bit lanes 0 = lower SB lanes LASTAMBFLAG: Indicates if this AMB is acting like the last AMB • In Disable, Calibrate - always 0. • In training - Set if DS matches TS0 AMB_ID value • Retains value after training till next reset. LINITST: Link initialization state Encoding is • 0000 - Disable • 0001 - Calibrate • 0010 - Training • 0011 - Testing • 0100 - Polling • 0101 - Config • 0110 - L0 • 0111 - L0s • 1000 - Recalibrate 5 RO 0 4 RO 0 3:0 RO 0h 174 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.3.1.8 FBDSBCFGNXT: FBD SB Link Electrical Configuration This register contains next settings of control bits to set link electrical parameters to match link length and frequency characteristics. Device: NodeID Function: 1 Offset: 54h Bit 7:5 4:3 Attr RV RWST Default 0h 00 Reserved SBTXDRVCUR: ‘11’ = Small ‘10’ = reserved ‘01’ = Regular ‘00’ = Large SBTXDEEMP: 00 = 0 dB 01 = 3.5dB 10 = 6dB 11 = 9.5dB SBRESYNCEN: ‘1’ = SB pass-thru data is in Re-sync mode ‘0’ = SB pass-thru is in Re-sample mode. Description 2:1 RWST 10b 0 RWST 1b 14.3.1.9 FBDNBCFGNXT: FBD NB Link Electrical Configuration This register contains next settings of control bits to set link electrical parameters to match link length and frequency characteristics. Device: NodeID Function: 1 Offset: 55h Bit 7:5 4:3 Attr RV RWST Default 0h 00 Reserved NBTXDRVCUR: ‘11’ = Small ‘10’ = reserved ‘01’ = Regular ‘00’ = Large NBTXDEEMP: 00 = 0 dB 01 = 3.5dB 10 = 6dB 11 = 9.5dB NBRESYNCEN: ‘1’ = SB pass-thru data is in Re-sync mode ‘0’ = SB pass-thru is in Re-sample mode. Description 2:1 RWST 10b 0 RWST 1b Intel® 6400/6402 Advanced Memory Buffer Datasheet 175 Registers 14.3.1.10 LINKPARNXT: FBD Link Frequency This register contains current settings of control bits to set link electrical parameters to match link length and frequency characteristics. Device: NodeID Function: 1 Offset: 56h Bit 15:2 1:0 Attr RV RWST Default 0h Reserved CFREQ: Current Link Frequency • 11 = DDR2-800 • 10 = DDR2-667 • 01 = DDR2-533 • 00 = Uninitialized Description 14.3.1.11 FBDSBCFGCUR: FBD SB Link Electrical Configuration This register contains current settings of control bits to set link electrical parameters to match link length and frequency characteristics. Device: NodeID Function: 1 Offset: 50h Bit 7:5 4:3 Attr RV ROST Default 0h 00b Reserved SBTXDRVCUR: ‘11’ = Small ‘10’ = reserved ‘01’ = Regular ‘00’ = Large SBTXDEEMP: 00 = 0 dB 01 = 3.5dB 10 = 6dB 11 = 9.5dB SBRESYNCEN: ‘1’ = SB pass-thru data is in Re-sync mode ‘0’ = SB pass-thru is in Re-sample mode. Description 2:1 ROST 10b 0 ROST 1 176 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.3.1.12 FBDNBCFGCUR: FBD NB Link Electrical Configuration This register contains current settings of control bits to set link electrical parameters to match link length and frequency characteristics. Device: NodeID Function: 1 Offset: 51h Bit 7:5 4:3 Attr RV ROST Default 0h 00 Reserved NBTXDRVCUR: ‘11’ = Small ‘10’ = reserved ‘01’ = Regular ‘00’ = Large NBTXDEEMP: 00 = 0 dB 01 = 3.5dB 10 = 6dB 11 = 9.5dB NBRESYNCEN: ‘1’ = SB pass-thru data is in Re-sync mode ‘0’ = SB pass-thru is in Re-sample mode. Description 2:1 ROST 10b 0 ROST 1 14.3.1.13 LINKPARCUR: FBD Link Frequency This register contains current settings of control bits to set link electrical parameters to match link length and frequency characteristics Device: NodeID Function: 1 Offset: 52h Bit 15:2 1:0 Attr RV ROST Default 0h 01 Reserved CFREQ: Current Link Frequency • 11 = DDR2-800 • 10 = DDR2-667 • 01 = DDR2-533 • 00 = Reserved Description Intel® 6400/6402 Advanced Memory Buffer Datasheet 177 Registers 14.3.1.14 FBDLOCKTO: FBD Bit Lock Time Out Register This register contains the bit lock time out value. This value is used by the to figure out when it should stop waiting for lanes to bit lock and make forward progress. The register also contains the width that the host is going to be starting with on the NB side. This will be used to mask off lanes for initial bit lock decision Device: NodeID Function: 1 Offset: 68h Bit 15:2 1:0 Attr RWST RWST Default 0594h 0h Description BLTOCNT: Bit Lock Time Out Counter default: 1428 frames NBLINKCFG: Northbound Link Config 00 = 14 lane 01 = 13 lane 10 = 12 lane 11 = reserved 14.3.1.15 FBDHAC: FBD Hot Add Control This register contains control to aid in hot add functionality. Device: NodeID Function: 1 Offset: 6Ch Bit 7:2 1 Attr RV RO Default 0 0 Reserved NB_DATA_ALL_ONES_FLAG: • 1 = Receiving ones on sufficient NB lanes to support init • 0 = Not receiving calibrate handshake on NB Rx DRIVE_ONES_SB: • 1 = Enable SB Tx Outputs and drive one’s • 0 = Normal operation Description 0 RW 0 14.3.1.16 FBDLS: FBD Link Status This register reports AMB FBD link status. Device: NodeID Function: 1 Offset: 6Eh Bit 7:3 2 Attr RV RO Default 0h 0 Reserved NLQS: Northbound Lane Electrical Status ‘1’ = Northbound lanes are quiesced ‘0’ = Northbound lanes are active SLQS: Southbound Lane Electrical Status ‘1’ = Southbound lanes are quiesced ‘0’ = Southbound lanes are active LNKRDY: Link Ready ‘1’ = FBD link is ready to accept requests and deliver responses ‘0’ = FBD link is not ready Description 1 RO 0 0 RO 0 178 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.3.1.17 RECALDUR: FBD Recalibrate Duration This register determines the duration of the Recalibration state between 32 and 42 frames. During recalibration state all commands and CRC are ignored. Device: NodeID Function: 1 Offset: 70h Bit 7 6:1 Attr RV RW Default 0 0h Reserved Recalibrate_Duration: This field sets the duration of the Recalibrate state once a sync command with the ERC bit. set is received. Legal values are between 32 and 42. Functionality if set outside this range is undefined. • > ‘42d (101010b) = undefined • = ‘42d (101010b) = ignore for 42 frames after Sync • .... • = 32d (100000b) = ignore for 32 frames after Sync • TEMPHI and temp enabled UNIMPLCFG: Unimplemented Configuration Address CMDCRCERR: SB CRC Error Description 14.3.3.2 FERR: First Error This register contains bits specifying which errors occurred first as related to the FBD channel. Device: NodeID Function: 1 Offset: 90h Bit 31:8 7 6 5 4 3 Attr RV RWCST RWCST RWCST RWCST RWCST Default 0 0 0 0 0 0 Reserved WBUFOVFL: Write Buffer overflow - Implementation Specific - only supported for debug WPLDERR: Wrong Number of Write Payloads (Buffer Underflow) - Implementation Specific - only supported for debug INJERR: Error Injection has sourced an injected error bit in the status return field (optional) INJALERT: Error Injection has sourced an injected alert error (optional) FEWEDGES: tClk Training Violation (no sync cmd for2x SYNCTRAININT typically 84 frames) Logs in RECFBD registers. Sends Alerts NB. Triggers auto self refresh SM. OVERTEMP: Temp > TEMPHI and temp enabled Fatal. AMB shuts down. UNIMPLCFG: Unimplemented Configuration Address Correctable. Logs in RECCFG* registers. AMB drops the command. Description 2 1 RWCST RWCST 0 0 Intel® 6400/6402 Advanced Memory Buffer Datasheet 181 Registers Device: NodeID Function: 1 Offset: 90h Bit 0 Attr RWCST Default 0 Description CMDCRCERR: SB CRC Error Correctable. Logs in RECFBD registers. AMB drops the current command and sources alerts. 14.3.3.3 NERR: Successive Error This register is used to report successive errors. More than two bits can be set in this register. This register contains bits specifying which errors occurred as related to the FBD channel. Device: NodeID Function: 1 Offset: 94h Bit 31:8 7 6 5 4 3 Attr RV RWCST RWCST RWCST RWCST RWCST Default 0 0 0 0 0 0 Reserved Reserved Reserved INJERR: Error Injection has sourced an injected error bit in the status return field (optional) INJALERT: Error Injection has sourced an injected alert error (optional) FEWEDGES: tClkTraining Violation (no sync cmd for 2x SYNCTRAININT typically 84 frames) Logs in RECFBD registers. Sends Alerts NB. Triggers auto self refresh SM. OVERTEMP: Temp > TEMPHI and temp enabled Fatal. AMB shuts down. UNIMPLCFG: Unimplemented Configuration Address Correctable. Logs in RECCFG* registers. Drops the command. CMDCRCERR: SB CRC Error Correctable. Logs in RECFBD registers. Drops the current command and sources alerts. Description 2 1 0 RWCST RWCST RWCST 0 0 0 14.3.3.4 RECCFG: Configuration Register Error Log This register contains the received address for an unimplemented configuration register access error. The contents of this register are only valid when the error that set this register is logged in the FERR or NERR register. Device: NodeID Function: 1 Offset: 98h Bit 15:13 12:10 Attr RV RWST Default 0 0h Reserved function: Description 182 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 1 Offset: 98h Bit 9:8 Attr RWST Default 0h Description size: 00 = one byte 01 = two bytes 10 = three bytes 11 = four bytes Note: This field only defined for errors on Config Register Writes. This field is undefined for other transactions. register address: 7:0 RWST 0h 14.3.3.5 RECFBD[9:0]: FBD Error Log .This register contains FBD frame data received that matches the logged frame error. Captures {BC} from frame N and A from frame N+1 where [11:8] = A[n+1] [7:4] = C[n] slot [3:0] = B[n] slot The contents of this register are only valid when one of the errors that set this register is logged in the FERR register. The contents of this register should not change until the error indication is cleared from the FERR register. Device: NodeID Function: 1 Offset: AEh, ACh, AAh, A8h, A6h, A4h, A2h, A0h, 9Eh, 9Ch Bit 15:12 11:0 Attr RV RWST Default 0 0 Reserved FRMDATA: Frame data for lane n Description 14.3.4 PERSONALITY BYTES Loaded From the SPD These bytes allow for AMB implementation specific settings to be loaded in an architected way by BIOS without BIOS being aware of specific AMB requirements. Each AMB vendor defines how these bytes should be loaded for the specific DIMM being built. The values to be loaded into these bytes are stored in the SPD EEPROM on the DIMM. The first six bytes are required to be loaded into the AMB via SMBus before link initialization to allow for configuration information needed for robust link operation. The remaining 8 bytes must be loaded before the FBD begins normal operation. Usage of these bytes can include • DDR electrical parameters to optimize performance on a given DIMM — For example, DLL delay settings, various I/O driver slew settings, • Enable/disable of various optimizations that may have been included in the design but can be turned off if they are not needed on this DIMM or they have unanticipated side effects - for example, power save modes, alternate clock recovery algorithms, and so forth. • Temperature Sensor offsets Intel® 6400/6402 Advanced Memory Buffer Datasheet 183 Registers • Internal clock domain phase offsets 14.3.4.1 PERSBYTE[13:0]NXT: Personality Bytes These bytes are loaded from SPD bytes 114:101 respectively. (PERSBYTE13NXT = SPD byte 114, ... , PERSBYTE0NXT = SPD byte 101) Function: 1 Offset: BDh:B0h Bit 7:0 Attr RWST Default 0 PData: Personality Data Byte Implementation specific registers Description 14.3.4.2 PERSBYTE[13:0]CUR: Personality Bytes Function: 1 Offset: BDh:B0h Bit 7:0 Attr ROST Default 0 PData: Personality Data Byte Implementation specific registers Description 14.3.5 14.3.5.1 Hardware Configuration Registers CMD2DATANXT: Next Value of Command to Data Delay This register has the next value of the command to data delay. This will be used after the next fast reset. For correct DIMM operation, CMD2DATA may be limited to a subset of the architecturally valid values. The allowed values are AMB specific and may vary with frequency. Values come from SPD. Device: NodeID Function: 1 Offset: E8h Bit 7:4 Attr RWST Default 0h Description DLYFRMS: Number of frames This specifies full frame delay part of the command to data delay. 0 - 9: Valid delays 10 - 15: Reserved DLYFRAC: Fractional delay of command to data This specifies fractional frame delay part of the command to data delay. 0 - 11: Specifies the delay in 1UI increments 12 - 15: Reserved 3:0 RWST 0h 184 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.3.5.2 CMD2DATACUR: Current Value of Command to Data Delay This register has the current value of the command to data delay. Device: NodeID Function: 1 Offset: E9h Bit 7:4 Attr ROST Default 0h Description DLYFRMS: Number of frames This specifies full frame delay part of the command to data delay. 0 - 9: Valid delays 10 - 15: Reserved DLYFRAC: Fractional delay of command to data This specifies fractional frame delay part of the command to data delay. 0 - 11: Specifies the delay in 1UI increments 12 - 15: Reserved 3:0 ROST 0h 14.3.5.3 C2DINCRNXT: Next Value of Command to Data Delay Increment This register has the next value of the command to data incremental delay. This will be used after the next fast reset. This will be used by the last AMB to delay driving the data beyond that specified in the command to data delay. Device: NodeID Function: 1 Offset: EAh Bit 7:2 1:0 Attr RV RWST Default 0h 0h Reserved INCRDLY: Incremental Delay for command to data 0 - 3: Specifies the incremental delay in frames Description 14.3.5.4 C2DINCRCUR: Current Value of Command to Data Delay Increment This register has the current value of the command to data incremental delay. This will be used by the last AMB to delay driving the data beyond that specified. Device: NodeID Function: 1 Offset: EBh Bit 7:2 1:0 Attr RV ROST Default 0h 0h Reserved INCRDLY: Incremental Delay for command to data 0 - 3: Specifies the incremental delay in frames Description 14.4 Implementation Specific FBD Registers (Function 2) No register information is available for the implementation specific registers. Intel® 6400/6402 Advanced Memory Buffer Datasheet 185 Registers 14.5 14.5.1 14.5.1.1 DDR and Miscellaneous Registers (Function 3) Memory Registers DAREFTC: DRAM Auto-Refresh Timing and Control Device: NodeID Function: 3 Offset: 70h Bit 31 30 29 28 27:24 23:16 15 14:0 Attr RV RWST RWST RWST RWST RWST RW RWST Default 0 0 0 0 0 4Eh 0 0C30h Reserved REFDERR: refresh buffer overflow error REFIERR: buffer count greater than the number of installed ranks ORIDEHS: override handshake; auto-refresh wins arbitration for command bus RBUF: number of pending refreshes for all ranks combined TRFC: DRAM refresh period AREFEN: auto-refresh enable TREFI: DRAM refresh interval Description 14.5.1.2 DSREFTC: DRAM Self-Refresh Timing and Control Device: NodeID Function: 3 Offset: 74h Bit 23:17 16 15:8 7:4 3 2:0 Attr RV RWST RWST RWST RV RWST Default 0 1 56h Fh 0 7h Reserved DISSREXIT: Disable DRAM Self-Refresh Exit when the link comes up TXSNR: DRAM Self-Refresh Exit to Non-Read Command Timing TRP: DRAM Precharge Timing Reserved TCKE: DRAM Minimum CKE Pulse Width Description 14.5.1.3 MTR: Memory Technology Register This register provides a local definition of the organization of DIMMs. This DRAM configuration information is used for MemBIST and DDR calibration. Device: NodeID Function: 3 Offset: 77h Bit 7 6 Attr RV RWST Default 0 0 Reserved WIDTH: Technology – DRAM data width Define the data width of SDRAMs within these DIMM’s 0 = x4 (4 bits wide) 1 = x8 (8 bits wide) Description 186 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 3 Offset: 77h Bit 5 Attr RWST Default 0 Description NUMRANK: Technology – Number of Ranks Define the number of ranks within these DIMM’s 0 = single ranked 1 = double ranked NUMBANK: Technology – Number of Banks Define the number of banks within these DIMM’s 0 = 4 banks 1 = 8 banks NUMROW: Technology – Number of Rows Define the number of rows within these DIMM’s 00 = 8,192 01 = 16,384 10 = 32,768 11 = 65,536 NUMCOL: Technology – Number of Columns Define the number of columns within these DIMM’s 00 = 1,024 01 = 2,048 10 = 4,096 11 = 8,192 4 RWST 0 3:2 RWST 00 1:0 RWST 00 14.5.1.4 DRT: DRAM Timing Control The DRAM Timing Control register is used to setup timing for MemBIST access to DRAMs. Device: NodeID Function: 3 Offset: 78h Bit 31 30:29 Attr RV RWST Default 0 00 Description Reserved TRAS: DRAM tRAS minimum required delay from active command to precharge command. Delay cycles based on JEDEC DDRII spec 45 ns for DDRII 400/533/667. Based on the latest JEDEC spec (JESD79-2, Sept 2003) for DDRII 800 MHz min tRAS is not defined yet. tRASMIN clocks delay: 00 => 18 for DDRII 800 MHz 01 => 15 for DDRII 667 MHz 10 => 12 for DDRII 533 MHz 11 => Reserved TRTP: DRAM cell internal read to precharge command delay. tRTP clocks delay: 00 => 2 01 => 3 10 => 4 11 => 5 28:27 RWST 00 Intel® 6400/6402 Advanced Memory Buffer Datasheet 187 Registers Device: NodeID Function: 3 Offset: 78h Bit 26:24 Attr RWST Default 000 Description BBRW: Back to Back Read-Write turn around. This field determines the minimum number of CMDCLK between Read-Write commands. The purpose of these 3 bits are to control the turnaround time on the DQ bus. Regular setting will be based on BL/2 + 2 tCK. BL4: tR2W = 4 tCK BL8: tR2W = 6 tCK Command clocks apart based on the following encoding: 000 => 10 001 => 9 010 => 8 011 => 7 100 => 6 101 => 5 110 => 4 111 => 3 (stress mode, not recommended) 23 22:20 RV RWST 0 000 Reserved BBWR: Back to Back Write-Read turn around. This field determines the minimum number of CMDCLK between Write-Read commands. The purpose of these 3 bits are to control the turnaround time on the DQ bus. Regular setting will be based on (CL-1)+BL/2+tWTR. Command clocks apart based on the following encoding: 000 => 12 001 => 11 010 => 10 011 => 9 100 => 8 101 => 7 110 => 6 111 => 5 (stress mode, not recommended 19 18:16 RV RWST 0 000 Reserved TWR: Twr DRAM Write Recovery delay Overall delay clocks will be (CL+AL-1) +BL/2 + tWR from write command to precharge command. 000 => 9 001 => 8 010 => 7 011 => 6 100 => 5 101 => 4 110 => 3 111 => 2 188 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 3 Offset: 78h Bit 15:12 Attr RWST Default 0000 Description TRC: Trc DRAM activate to another activate delay 0000 => 26 0001 => 25 0010 => 24 0011 => 23 0100 => 22 0101 => 21 0110 => 20 0111 => 19 1000 => 18 1001 => 17 1010 => 16 1011 => 15 1100 => 14 1101 => 13 1110 => 12 1111 => 11 TRCD: 00 => 01 => 10 => 11 => Trcd DRAM RAS# to CAS# delay 6 5 4 3 11:10 RWST 00 If AL >= Trcd, Read/Write command will be issued right after ACT cycle. 9:8 RWST 00 TRP: Trp DRAM RAS# to Precharge delay 00 => 6 01 => 5 10 => 4 11 => 3 NOPCNT: Programmable NOP insertion (Device Deselect actually). Number of Nops will be inserted between read/write commands to slow down Membist activities in the same page. Up to 255 clocks NOPs can be programmed to insert delay between read/write commands. If NOPs delay is programmable less than the required DRAM timing, Overall NOP delay from command to command will not be seen. 7:0 RWST 00h 14.5.1.5 DRC: DRAM Controller Mode Register This register controls the mode of the DRAM Controller. Device: NodeID Function: 3 Offset: 7Ch Bit 31:30 29 Attr RV RW Default 00 0 Reserved INITDONE: Initialization Complete. This scratch bit communicates software state from the AMB to BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. This bit has no effect on AMB operation. Reserved Description 28 RV 0 Intel® 6400/6402 Advanced Memory Buffer Datasheet 189 Registers Device: NodeID Function: 3 Offset: 7Ch Bit 27:24 23 22 Attr RWST RWST RWST Default 0 0 0 Description CLKDIS: clock[3:0] output disable SEQADDR: When set to 1 turns off address balancing on address bit A0 to support DRAMs programmed for Sequential Burst Type DQSHALFGAIN: - select for DQS differential amplifier gain. When set to 0 the amplifier gain is cut half to support differential strobes for DDR2 Note: the sense of this field is inverted from past DDR designs so that BIOS supporting generic AMBs do not have to write a “1” to what is a “reserved” field on other AMBs TESTMODE: When set to 1 the LEGSEL output of the DDR comp block selects one of eight driver legs to enable. This bit can be used in conjunction with the DRAMISCTL.DRVOVR bits to override the LEGSEL output generated by the comp block. 21 RW 0 20 19 RWST RWST 0 0 RWPRDIS: Read/Write pointer reset disable Disables the resetting of DDR cluster FIFO read and write pointers during normal operation that occurs when a READ command finishes executing and no additional READ commands are in process. ODTZ: On-Die Termination Strength. “0” Disabled “1” Enabled HLDDIS: command/address hold disable Disabling hold will allow the address and bank address pins to revert to all zeros (all ones on the balanced address copy) during idle cycles. When hlddis is clear, the addresses retain the value of the last non-idle command cycle in order to reduce switching on the bus. BALDIS: command/address balancing disable CADIS: command/address output disable CSDIS: chip select output disable ODTDIS: ODT output disable CKEFRCLOW: CKE Force Low Forces CKE low. Must be cleared to enable normal DDR functionality. This bit overrides the CKE1 and CKE0 fields described below, and also overrides all channel commands and other hardware functions that would otherwise affect the state of the CKE outputs. CKEDIS: CKE output disable CKE1: CKE output 1 control and status. Software can write to this bit to change the state of the CKE 1 output. Hardware will update this bit with the current status of the CKE1 output two core cycles after a channel command or other hardware function changes the state of the CKE1 output. ‘1’ = CKE1 pads asserted. ‘0’ = CKE1 pads de-asserted. CKE0: CKE output 0 control and status. Software can write to this bit to change the state of the CKE 0 output. Hardware will update this bit with the current status of the CKE 0 output two core cycles after a channel command or other hardware function changes the state of the CKE 0 output. ‘1’ = CKE0 pads asserted. ‘0’ = CKE0 pads de-asserted. BL: DRAM burst length. ‘1’ = bl8 ‘0’ = bl4 AL: DRAM Additive Latency [3:0] Note: This AL value is sampled during TS2 training sequences to set timing for FBD link data returns. Changes to AL after this time will not effect FBD link data return timing until the next TS2 sequence following link reset. 18 RWST 1 17 RWST 0 16 15 14 13 12 RWST RW RW RW RWST 0 0 0 0 1 11 10 RW RWST 0 0 9 RWST 0 8 RWST 0 7:4 RWST 2h 190 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 3 Offset: 7Ch Bit 3:0 Attr RWST Default 3h Description CL: DRAM CAS Latency [3:0] Note: This CL value is sampled during TS2 training sequences to set timing for FBD link data returns. Changes to CL after this time will not effect FBD link data return timing until the next TS2 sequence following link reset. 14.5.2 14.5.2.1 Memory BIST Registers MBCSR: MemBIST Control Architected MemBIST control interface. Device: NodeID Function: 3 Offset: 40h Bit 31 Attr RWS Default 0 Description START: Start operation: 1 => Set this bit to begin MemBIST execution. 0 => Hardware will clear this bit when MemBIST execution is completed. PF: Fail/Pass indicator: Write to 0 when start MemBIST. Hardware will set to 1 when a failure is detected. 0 => Pass 1 => Fail HALT: Halt on Error 0 => Operation will not halt due to a detected error. 1 => Operation will halt after read-compare data error is detected. MemBIST will complete the current transaction before halting. This may result in multiple errors being logged. 28 RW 0 ABORT: MemBIST test abort. When test abort bit is set, MBCSR bit 31 (Start operation, RWS) needs to be set to "0" at the same time to avoid restarting MemBIST. 0 => Normal operation. 1 => Need to abort the test during MemBIST operation. If there is any following membist test after the abort test, bit [28] needs to be cleared. The Write to set MBCSR.abort must occur at least tRFC after the Write to set MBCSR.start. Otherwise subsequent MemBIST operations may fail. tRFC value is set in DAREFTC.trfc (Function3, offset70h, bit field 23:16). 27 RW 0 SPARE: 30 RW 0 29 RW 0 Intel® 6400/6402 Advanced Memory Buffer Datasheet 191 Registers Device: NodeID Function: 3 Offset: 40h Bit 26:24 Attr RW Default 000 Description ALGO: Embedded Algorithm selection: Embedded Algorithm selection: 000 => No embedded algorithm is selected. Normal command will be executed from the selection of MBCSR bits field [5:4] 001 => Scan: ^ (WD1); ^(RD2); ^ (WI3); ^ (RI4) 010 => Undefined 011 => Data Retention Write or Init: ^ (WD1); 100 => Data Retention Read : ^ (RD2); 101 => Mats +: ^(WD1); ^(RD2, WI3); v(RI4, WD5); 110 => March C-: ^(WD1); ^(RD2, WI3); ^(RI4, WD5); v(RD6, WI7); v(RI8, WD9); v(RD10); 111 => Undefined 23:22 21:20 RV RW 00 00 Reserved CS: CS[1:0] selection in MemBIST mode 01: select Rank 0 10: select Rank 1 00: Reserved 11: Reserved INVERT: Invert data pattern when data is written out to DRAM. FIXED: Fixed data pattern selection for MemBIST operation 000 => 0 001 => F 010 => A 011 => 5 100 => C 101 => 3 110 => 9 111 => 6 ENABLE288: Enable 288 bits user defined pattern for memory fill write only. There is no data comparison, error logger functions for 288 bits user defined data. 0 => 144 bits user defined data pattern when MBCSR[9:8] selects user defined data. 1 => 288 bits user defined data pattern when MBCSR[9:8] selects user defined data. MBDATA: Selects use of MBDATA for error log field for LFSR, Circular Shift and user defined data modes. This field has no effect on fixed data patterns. 0 => use MBDATA0/1/2/3/8 for failure data bit location accumulator. 1 => use MBDATA0/1/2/3/8 to log 5 failure addresses. ABAR: MemBIST output address compliment for FastX, FastY, and FastXY. Whenever this bit is enabled, Bank, Row, Column address will be inverted on alternate addresses as described in the MemBIST chapter. 0 => Regular addressing 1 => Dynamic address inversion ADIR: Address decode direction for FastX, Fast Y, FastXY 0 => Address increments 1 => Address decrements 19 18:16 RW RW 0 000 15 RW 0 14 RW 0 13 RW 0 12 RW 0 192 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 3 Offset: 40h Bit 11:10 Attr RW Default 00 Description FAST: Address sequencing 00 => addressing with XZY toggling (column->bank->row) 01 => Fast Y with fixed bank 10 => Fast X with fixed bank 11 => Fast XY with fixed bank DTYPE: Data type selection: 00 => Fixed data pattern, selected by MBCSR bits 18:16 01 => 144 or 288 bits user defined data 10 => Circular shift data 11 => LFSR data, seeded from 32 bit LFSR seed register. Note: Algorithm mode only supports DTYPE = Fixed Note: Circular shift data and LFSR data type should not be used for single address operation (ATYPE = 01). 7:6 RW 00 ATYPE: Address type 00 => Reserved 01 => Single physical address operation, contained in MBADDR row/column/ bank. 10 => start/end physical address range defined in MB_START_ADDR & MB_END_ADDR registers. • In FastX, FastY and FastXY modes, only the bank specified in MB_START_ADDR will be exercised. 11 => full address range of the DIMM as defined in MTR register which specifies the number of banks, rows, and columns. • In FastX, FastY and FastXY modes, only the bank 0 will be exercised. CMD: Command execution: 00 => Read only without data comparison 01 => Write only 10 => Read with data comparison 11 => Write followed by Read with data comparison Reserved 9:8 RW 00 5:4 RW 00 3:0 RV 0 Algorithms: When Embedded algorithm is applied, please program the following bits at the same time. 1. Select MBCSR.cmd bit[5:4] for the initial command execution mode. For all algorithm choices except for Data Retention Read, select "01: write only". For Data Retention Read, select "10: read with data comparison". 2. Program MBCSR.fast bit[11:10] to select FastX, FastY, FastXY, or XZY. 3. Program proper start/end address registers and corresponding MTR value for DIMM type. Do not leave start and end address register as default "00" or the same value. Algorithm does not support single or full address modes. 14.5.2.2 MBADDR: Memory Test Address The register is used by MemBIST only when testing to a single memory location. (MBCSR.atype = 2b‘01) Intel® 6400/6402 Advanced Memory Buffer Datasheet 193 Registers Device: NodeID Function: 3 Offset: 44h Bit 31:16 15 14:3 Attr RWST RWST RWST Default 0000h 0 0000h ROW: Row Address 15:0 SPARE: COL: Column Address BL8[14:3] DRAM Column Address 15:11,9:3 BL4[14:3] DRAM Column Address 14:11,9:2 BA: Bank Address 2:0 Description 2:0 RWST 000 14.5.2.3 MBDATA[9:0]: Memory Test Data Device: NodeID Function: 3 Offset: 6Ch, 68h, 64h, 60h,5Ch, 58h, 54h, 50h,4Ch, 48h Bit 31:0 Attr RWST Default 0000h Description DATA: see functional description below for definition by mode and register Description by mode (note: MBCSR.dtype, MBCSR.mbdata and MBCSR.enable288 select mode) Reg Bit Offset Fixed Data Pattern 5th Fail address 144 bit User Defined Pattern Circular Shift LFSR 288 bit User defined pattern MBDATA9 31:0 6Ch User defined Late Word4 Circular data [71:64] & shift data Early data [71:64] LFSR random Late User defined Late data [71:64] & data [71:64] (2nd Early data [71:64] burst data) & Early data [71:64] (2nd burst data) 5th Fail address Or Late data [71:64] & Early data [71:64] Failure bit location accumulator LFSR random Late data [63:32] LFSR random Late data [31:0] User defined Late data [71:64] (1st burst data) & Early data [71:64] (1st burst data) MBDATA8 31:0 68h Late data [71:64] & Early data [71:64] Failure bit location accumulator 5th Fail address Or Late data [71:64] & Early data [71:64] Failure bit location accumulator User defined Late data [63:32] User defined Late data [31:0] User defined Early data [63:32] User defined Early data [31:0] Fail address 4 Or Late data [63:32] Failure bit location accumulator 5th Fail address Or Late data [71:64] & Early data [71:64] Failure bit location accumulator DW3 Circular shift data DW2 Circular shift data DW1 Circular shift data DW0 Circular shift data Fail address 4 Or Late data [63:32] Failure bit location accumulator MBDATA7 31:0 64h Fail address 4 User defined Late data [63:32] (2nd burst data) User defined Late data [31:0] (2nd burst data) MBDATA6 31:0 60h Fail address 3 MBDATA5 31:0 5Ch Fail address 2 LFSR random User defined Early Early data [63:32] data [63:32] (2nd burst data) LFSR random Early data [31:0] Fail address 4 Or Late data [63:32] Failure bit location accumulator User defined Early data [31:0] (2nd burst data) User defined Late data [63:32] (1st burst data) MBDATA4 31:0 58h Fail address 1 MBDATA3 31:0 54h Late data [63:32] Failure bit location accumulator 194 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Description by mode (note: MBCSR.dtype, MBCSR.mbdata and MBCSR.enable288 select mode) Reg Bit Offset Fixed Data Pattern Late data [31:0] Failure bit location accumulator 144 bit User Defined Pattern Fail address 3 Or Late data [31:0] Failure bit location accumulator Fail address 2 Or Early data [63:32] Failure bit location accumulator Fail address 1 Or Early data [31:0] Failure bit location accumulator Circular Shift Fail address 3 Or Late data [31:0] Failure bit location accumulator Fail address 2 Or Early data [63:32] Failure bit location accumulator Fail address 1 Or Early data [31:0] Failure bit location accumulator LFSR Fail address 3 Or Late data [31:0] Failure bit location accumulator Fail address 2 Or Early data [63:32] Failure bit location accumulator Fail address 1 Or Early data [31:0] Failure bit location accumulator 288 bit User defined pattern User defined Late data [31:0] (1st burst data) MBDATA2 31:0 50h MBDATA1 31:0 4Ch Early data [63:32] Failure bit location accumulator User defined Early data [63:32] (1st burst data) MBDATA0 31:0 48h Early data [31:0] Failure bit location accumulator User defined Early data [31:0] (1st burst data) Note: In the later half part of data burst length 8 test, 144 bits or 288 bits user-defined data pattern will be repeat as the same sequence of burst length 4. 14.5.2.3.1 MBDATA Failure Address Mapping To compress the failure address into 32 bits, bits that are always zero are removed from the logging. These removed bits include AutoPrecharge Column address [10] and least significant bits assumed by burst length. Table 14-11. MBDATA Failure Address Register Correspondence to DRAM Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 see description below Column and Chunk Bank Row BL4: 1 bit chunk indicates the location of 2 failure burst data chunks. The above Column plus Chunk is equal to DRAM column address as the following: Table 14-12. BL4 Column and Chunk Correspondence to DRAM Address Register Bit Location DRAM Col Address Data Chunk 1 2 1 4 1 1 1 3 1 0 1 2 9 1 1 8 9 7 8 6 7 5 6 4 5 3 4 2 3 1 2 1 X 0 • where the auto-precharge address bit 10 is assumed zero • since data is logged in 144 bits (two chunks), address bit zero is not needed BL8: 2 bit chunk indicates the location of 4 failure burst data chunks. The above Column plus Chunk is equal to DRAM column address as the following: Intel® 6400/6402 Advanced Memory Buffer Datasheet 195 Registers Table 14-13. BL8 Column and Chunk Correspondence to DRAM Address Register Bit Location DRAM Col Address Data Chunk 12 11 10 9 8 9 7 8 6 7 5 6 4 5 3 4 2 3 2 1 X 1 0 14 13 12 11 • where the auto-precharge address bit 10 is assumed zero • since data is logged in 144 bits (two chunks), Data chunk address bit zero is not needed 14.5.2.4 MB_START_ADDR: Memory Test Start Address MB_END_ADDR row and column address must be larger than MB_START_ADDR row and column address in either increasing or deceasing address mode. During FastX, FastY and FastXY operation, only one memory bank is tested. Specify the desired bank in MB_START_ADDR[2:0]. MB_END_ADDR[2:0] is ignored. This register is only used when MBCSR.atype = 2b’10, and when MBCSR.algo is non-zero. Device: NodeID Function: 3 Offset: 9Ch Bit 31:16 15 14:3 Attr RWST RV RWST Default 0000h 0 0000h Description ROW: MemBIST Start Row Address 15:0 Reserved COL: MemBIST Start Column Address BL8 [14:3] Column Address 15:11, 9:3 BL4 [14:3] Column Address 14:11, 9:2 BA: MemBIST Start Bank Address 2:0 2:0 RWST 000 14.5.2.5 MB_END_ADDR: Memory Test End Address This register is only used when MBCSR.atype = 2b’10, and when MBCSR.algo is non-zero. Device: NodeID Function: 3 Offset: A0h Bit 31:16 15 14:3 Attr RWST RV RWST Default 0000h 0 0000h Description ROW: MemBIST End Row Address 15:0 Reserved COL: MemBIST End Column Address BL8 [14:3] Column Address 15:11, 9:3 BL4 [14:3] Column Address 14:11, 9:2 BA: MemBIST End Bank Address 2:0 2:0 RWST 000 196 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.5.2.6 MBLFSRSED: Memory Test Circular Shift and LFSR Seed Device: NodeID Function: 3 Offset: A4h Bit 31:0 Attr RWST Default 0000h Description DMBLFSRSED:MemBIST LFSR Seed This 32 bit register will be used as the initial data seed for LFSR or Circular shift data pattern. 14.5.2.7 MBFADDRPTR: Memory Test failure Address Pointer Register Device: NodeID Function: 3 Offset: A8h Bit 31:0 Attr RWST Default 0000h Description DMBFADDRPTR: This 32 bit register designates which MemBIST failures to log in the available failure address locations. The default value of this register is zero. It means MemBIST always logs beginning with the first failure. If it is programmed to hex A (10 in decimal), MemBIST will log failures starting from the11th failure. The corresponding MB_ERR_DATA0 register will log corrupted data in the first designated failure address. Note: this register does not affect the MBDATA failure bit location accumulators. 14.5.2.8 MB_ERR_DATA00: Memory Test Error Data 0 Bytes [3:0] Stores the first 32 bits of the 1st 144 bit failure data Research: compare all register[definitions to table.] Device: NodeID Function: 3 Offset: B0h Bit 31:0 Attr RWST Default 0000h DATA: Early failure data [31:0] Description 14.5.2.9 MB_ERR_DATA01: Memory Test Error Data 0 Bytes [7:4] Stores the second 32 bits of the 1st 144 bit failure data. Device: NodeID Function: 3 Offset: B4h Bit 31:0 Attr RWST Default 0000h DATA: Early failure data [63:32] Description Intel® 6400/6402 Advanced Memory Buffer Datasheet 197 Registers 14.5.2.10 MB_ERR_DATA02: Memory Test Error Data 0 Bytes [11:8] Stores the third 32 bits of the 1st 144 bit failure data. Device: NodeID Function: 3 Offset: B8h Bit 31:0 Attr RWST Default 0000h DATA: Late failure data [31:0] Description 14.5.2.11 MB_ERR_DATA03: Memory Test Error Data 0 Bytes [15:12] Stores the fourth 32 bits of the 1st 144 bit failure data. Device: NodeID Function: 3 Offset: BCh Bit 31:0 Attr RWST Default 0000h DATA: Late failure data [63:32] Description 14.5.2.12 MB_ERR_DATA04: Memory Test Error Data 0 Bytes [17:16] Stores the last 16 bits of the 1st 144 bit failure data. Device: NodeID Function: 3 Offset: C0h Bit 15:0 Attr RWST Default 0000h Description DATA: Late failure data [71:64] & Early failure data [71:64] 14.5.2.13 MB_ERR_DATA10: Memory Test Error Data 1 Bytes [3:0] Stores the first 32 bits of the 2nd 144 bit failure data. Device: NodeID Function: 3 Offset: C4h Bit 31:0 Attr RWST Default 0000h DATA: Early failure data [31:0] Description 14.5.2.14 MB_ERR_DATA11: Memory Test Error Data 1 Bytes [7:4] Stores the second 32 bits of the 2nd 144 bit failure data. Device: NodeID Function: 3 Offset: C8h Bit 31:0 Attr RWST Default 0000h DATA: Early failure data [63:32] Description 198 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.5.2.15 MB_ERR_DATA12: Memory Test Error Data 1 Bytes [11:8] Stores the third 32 bits of the 2nd 144 bit failure data. Device: NodeID Function: 3 Offset: CCh Bit 31:0 Attr RWST Default 0000h DATA: Late failure data [31:0] Description 14.5.2.16 MB_ERR_DATA13: Memory Test Error Data 1 Bytes [15:12] Stores the fourth 32 bits of the 2nd 144 bit failure data. Device: NodeID Function: 3 Offset: D0h Bit 31:0 Attr RWST Default 0000h DATA: Late failure data [63:32] Description 14.5.2.17 MB_ERR_DATA14: Memory Test Error Data 1 Bytes [17:16] Stores the last 16 bits of the 2nd 144 bit failure data. Device: NodeID Function: 3 Offset: D4h Bit 15:0 Attr RWST Default 0000h Description DATA: Late failure data [71:64] & Early failure data [71:64] 14.5.2.18 MB_ERR_DATA20: Memory Test Error Data 2 Bytes [3:0] Stores the first 32 bits of the 3rd 144 bit failure data. Device: NodeID Function: 3 Offset: D8h Bit 31:0 Attr RWST Default 0000h DATA: Early failure data [31:0] Description 14.5.2.19 MB_ERR_DATA21: Memory Test Error Data 2 Bytes [7:4] Stores the second 32 bits of the 3rd 144 bit failure data. Device: NodeID Function: 3 Offset: DCh Bit 31:0 Attr RWST Default 0000h DATA: Early failure data [63:32] Description Intel® 6400/6402 Advanced Memory Buffer Datasheet 199 Registers 14.5.2.20 MB_ERR_DATA22: Memory Test Error Data 2 Bytes [11:8] Stores the third 32 bits of the 3rd 144 bit failure data. Device: NodeID Function: 3 Offset: E0h Bit 31:0 Attr RWST Default 0000h DATA: Late failure data [31:0] Description 14.5.2.21 MB_ERR_DATA23: Memory Test Error Data 2 Bytes [15:12] Stores the fourth 32 bits of the 3rd 144 bit failure data. Device: NodeID Function: 3 Offset: E4h Bit 31:0 Attr RWST Default 0000h DATA: Late failure data [63:32] Description 14.5.2.22 MB_ERR_DATA24: Memory Test Error Data 2 Bytes [17:16] Stores the last 16 bits of the 3rd 144 bit failure data. Device: NodeID Function: 3 Offset: E8h Bit 15:0 Attr RWST Default 0000h Description DATA: Late failure data [71:64] & Early failure data [71:64] 14.5.2.23 MB_ERR_DATA30: Memory Test Error Data 3 Bytes [3:0] Stores the first 32 bits of the 4th 144 bit failure data. 14.5.2.24 MB_ERR_DATA31: Memory Test Error Data 3 Bytes [7:4] Stores the second 32 bits of the 4th 144 bit failure data Device: NodeID Function: 3 Offset: F0h Bit 31:0 Attr RWST Default 0000h DATA: Early failure data [63:32] Description 14.5.2.25 MB_ERR_DATA32: Memory Test Error Data 3 Bytes [11:8] Stores the third 32 bits of the 4th 144 bit failure data. Device: NodeID Function: 3 Offset: F4h Bit 31:0 Attr RWST Default 0000h DATA: Late failure data [31:0] Description 200 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.5.2.26 MB_ERR_DATA33: Memory Test Error Data 3 Bytes [15:12] Stores the fourth 32 bits of the 4th 144 bit failure data. Device: NodeID Function: 3 Offset: F8h Bit 31:0 Attr RWST Default 0000h DATA: Late failure data [63:32] Description 14.5.2.27 MB_ERR_DATA34: Memory Test Error Data 3 Bytes [17:16] Stores the last 16 bits of the 4th 144 bit failure data. Device: NodeID Function: 3 Offset: FCh Bit 15:0 Attr RWST Default 0000h Description DATA: Late failure data [71:64] & Early failure data [71:64] 14.5.3 14.5.3.1 Thermal Sensor Registers TEMPLO: Temperature Low Trip Point Low trip point. Device: NodeID Function: 3 Offset: 80h Bit 7:0 Attr RWST Default FFh Description TEMPLO: Low threshold trip point 14.5.3.2 TEMPMID: Temperature Mid Trip Point Mid trip point. Device: NodeID Function: 3 Offset: 81h Bit 7:0 Attr RWST Default FFh Description TEMPMID: Mid threshold trip point 14.5.3.3 TEMPHI: Temperature High Trip Point High trip point. Device: NodeID Function: 3 Offset: 82h Bit 7:0 Attr RWST Default FFh Description TEMPHI: High threshold trip point Intel® 6400/6402 Advanced Memory Buffer Datasheet 201 Registers 14.5.3.4 UPDATED: Update Temp Diff Bit Take new temperature sample and update the temp diff bit (INCREASING). Device: NodeID Function: 3 Offset: 83h Bit 7:1 0 Attr RV RWS Default 00h 0 reserved UPDATE: Write ‘1’ = a. latch current temperature from the TEMP register for comparison on next UPDATE and b. update INCREASING bit of TEMPSTAT register based on the current temperature and the last latched temperature; c. Automatically clears this bit to ‘0’ after INCREASING bit is updated; Write ‘0’ - no effect Description 14.5.3.5 TEMPSTAT: Thermal Sensor Status Register This register controls and reports temperature status. Device: NodeID Function: 3 Offset: 84h Bit 7:6 5 Attr RV RWST Default 0 0 Reserved NoAutoUpdate ‘1’ = turns off update of temp stat values so that forced values written in by firmware are not overwritten ‘0’ = overtemp trip bits are continuously and automatically updated as normal and increasing bit is updated through UPDATE register mechanism INCREASING ‘1’ = Temperature has increased since the last time UPDATE bit was set in UPDATED register. ‘0’ = Temperature has not increased since the last time UPDATE bit was set in UPDATED register. This is reflected as the Rising/Falling value in the Thermal Trip field of northbound FBD status 0. OVERTEMPHI ‘1’ = Temperature is above or equal to TEMPHI.TRIP ‘0’ = Temperature is below TEMPHI.TRIP OVERTEMPMID ‘1’ = Temperature is above or equal to TEMPMID.TRIP ‘0’ = Temperature is below TEMPMID.TRIP This is reflected in the Thermal Trip value of northbound FBD status 0 OVERTEMPLO ‘1’ = Temperature is above or equal to TEMPLO.TRIP ‘0’ = Temperature is below TEMPLO.TRIP This is reflected in the Thermal Trip value of northbound FBD status 0 TEMPHIENABLE ‘1’ = Allow OVERTEMPHI=1 to shut down the DDR channel, drop DDR commands, log an error, and take FBD links to EI. ‘0’ = OVERTEMPHI=1 only logs an error. Description 4 RW 0 3 RWST 0 2 RWST 0 1 RWST 0 0 RWST 0 202 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.5.3.6 TEMP: Temperature A/D Current temperature reading. This 8-bit value with 0.5 degree of resolution is continuously and automatically kept up to date by AMB hardware. Device: NodeID Function: 3 Offset: 85h Bit 7:0 Attr RO Default 00h Description DEGREES: Current temperature - binary encode 0 - 127.5 degrees C 14.6 14.6.1 14.6.1.1 Implementation Specific DDR Initialization and Calibration Registers (Function 4) DDR Calibration DCALCSR: DCAL Control and Status Device: NodeID Function: 4 Offset: 40h Bit 31 Attr RWS Default 0 Description START: Start Operation When set to 1 by software, the operation selected by the dcalcsr.opcode is initiated. Hardware clears this bit when the operation is complete. FAIL: Completion Status 1xx = Fail, 0xx = Pass BASPAT: This controls which data pattern is used for the DQS Delay calibration. Setting this field enables the use of the basic data pattern selected by the DCALCSR.PATTERN bits. When cleared, the extended data pattern specified in the DDQSCVDP and DDQSCADP registers is used. RSTREGSS: Reset DCALDATA CSR in single step calibration mode. This bit should be set during the first step of a single step calibration. It will enable hardware to clear all registers and status bits during the calibration step the same way hardware does on the first step of an automatic “all passes” calibration. CHSEL: This field defines bus folding. This function is obsolete and is not supported. SGLSTP: Single Step Calibration Operation Applies only to Receive enable, DQS cal, and I/O loopback “1” = Single step - a single step of the algorithm selected by the OPCODE is run by hardware. No data analysis is run. “0” = All passes - all steps of the algorithm selected by the OPCODE is run by hardware including data analysis. CS: Rank select This field corresponds to the chip select outputs: CS[1:0]. Setting a bit in this field will cause the corresponding CS pin to drive low when commands are issued on the DDR bus. This field Applies to NOP, Refresh, Precharge all, and MRS/EMRS commands. It also applies to Receive Enable, and DQS Delay cal in single step mode. Reserved A0_DQSCAL: revert to A0 DQSCAL algorithm 30:28 RW 0 27 RW 0 26 RW 00 25:24 23 RW RW 0 0 22:21 RW 00 20 19 RV RW 0 0 Intel® 6400/6402 Advanced Memory Buffer Datasheet 203 Registers Device: NodeID Function: 4 Offset: 40h Bit 18:16 Attr RW Default 000 Description PATTERN: Basic data pattern for DQS cal and I/O loopback. This sets the burst length 4 pattern for a nibble of data. The pattern is repeated for BL8. This pattern is replicated on all nibbles of the data bus. “000” = F > 0 > F > 0 “001” = 0 > F > 0 > F “010” = A > 5 > A > 5 “011” = 5 > A > 5 > A “100” = C > 3 > C > 3 “101” = 3 > C > 3 > C “110” = 9 > 6 > 9 > 6 “111” = 6 > 9 > 6 > 9 DARWPR: Disable FIFO reset in single pass mode. Applies only to Receiver enable, DQS cal, and I/O loopback. When set to 1, this bit inhibits the core to DDR cluster reset signal generated during the cal/hvm modes listed above. This prevents the DDR cluster synchronizer FIFO write pointer and data latches from being reset so that they can be read out of the cluster using the error monitor function. The reset signal can only be disabled in single step mode. When the ALLP bit is set to 1, the DARWPR bit has no effect. OPMODS: Operation modifiers OPCODE: “0000” = NOP “0001” = Refresh “0010” = Pre-Charge “0011” = MRS/EMRS “0101” = Automatic DQS Delay Calibration “1100” = Automatic Receive Enable Calibration “1101” = Self-Refresh Entry All other settings are reserved 15 RW 0 14:4 3:0 RW RW 000h 0h 14.6.1.2 DCALADDR: DCAL Address Register Device: NodeID Function: 4 Offset: 44h Bit 31:0 Attr RW Default Description 0000_0000h DCALADDR: DCAL Address and Other Information Based on Opcode. 204 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Table 14-14. Functional Characteristics of DCALADDR Bit NOP, Refresh, Pre-Charge, MRS/EMRS, and Self-Refresh Entry Commands initiated by DCALCSR DRAM Address Bus 15:0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRAM Bank Address Bus 2:0 Intel® 6400/6402 Advanced Memory Buffer Datasheet 205 Registers 14.6.1.3 DCALDATA[71:0]: DCAL Data Registers Device: NodeID Function: 4 Offset: 8Fh - 48h Bit 7:0 Attr RW Default 00h Description DCALDATA: DCAL Data and Other Information Based on Opcode. Table 14-15. Functional Characteristics of DCALDATA for Calibration Algorithms (Sheet 1 of 2) Byte 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 Receive Enable Preamble status DQS17 rank1 First edge position DQS17 rank1 Preamble status DQS8 rank1 First edge position DQS8 rank1 Preamble status DQS16 rank1 First edge position DQS16 rank1 Preamble status DQS7 rank1 First edge position DQS7 rank1 Preamble status DQS15 rank1 First edge position DQS15 rank1 Preamble status DQS6 rank1 First edge position DQS6 rank1 Preamble status DQS14 rank1 First edge position DQS14 rank1 Preamble status DQS5 rank1 First edge position DQS5 rank1 Preamble status DQS13 rank1 First edge position DQS13 rank1 Preamble status DQS4 rank1 First edge position DQS4 rank1 Preamble status DQS12 rank1 First edge position DQS12 rank1 Preamble status DQS3 rank1 First edge position DQS3 rank1 Preamble status DQS11 rank1 First edge position DQS11 rank1 Preamble status DQS2 rank1 First edge position DQS2 rank1 Preamble status DQS10 rank1 First edge position DQS10 rank1 Preamble status DQS1 rank1 First edge position DQS1 rank1 Preamble status DQS9 rank1 DQS Cal Max delay DQS17 rank1 Min delay DQS17 rank1 Max delay DQS8 rank1 Min delay DQS8 rank1 Max delay DQS16 rank1 Min delay DQS16 rank1 Max delay DQS7 rank1 Min delay DQS7 rank1 Max delay DQS15 rank1 Min delay DQS15 rank1 Max delay DQS6 rank1 Min delay DQS6 rank1 Max delay DQS14 rank1 Min delay DQS14 rank1 Max delay DQS5 rank1 Min delay DQS5 rank1 Max delay DQS13 rank1 Min delay DQS13 rank1 Max delay DQS4 rank1 Min delay DQS4 rank1 Max delay DQS12 rank1 Min delay DQS12 rank1 Max delay DQS3 rank1 Min delay DQS3 rank1 Max delay DQS11 rank1 Min delay DQS11 rank1 Max delay DQS2 rank1 Min delay DQS2 rank1 Max delay DQS10 rank1 Min delay DQS10 rank1 Max delay DQS1 rank1 Min delay DQS1 rank1 Max delay DQS9 rank1 206 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Table 14-15. Functional Characteristics of DCALDATA for Calibration Algorithms (Sheet 2 of 2) Byte 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Enable First edge position DQS9 rank1 Preamble status DQS0 rank1 First edge position DQS0 rank1 Preamble status DQS17 rank0 First edge position DQS17 rank0 Preamble status DQS8 rank0 First edge position DQS8 rank0 Preamble status DQS16 rank0 First edge position DQS16 rank0 Preamble status DQS7 rank0 First edge position DQS7 rank0 Preamble status DQS15 rank0 First edge position DQS15 rank0 Preamble status DQS6 rank0 First edge position DQS6 rank0 Preamble status DQS14 rank0 First edge position DQS14 rank0 Preamble status DQS5 rank0 First edge position DQS5 rank0 Preamble status DQS13 rank0 First edge position DQS13 rank0 Preamble status DQS4 rank0 First edge position DQS4 rank0 Preamble status DQS12 rank0 First edge position DQS12 rank0 Preamble status DQS3 rank0 First edge position DQS3 rank0 Preamble status DQS11 rank0 First edge position DQS11 rank0 Preamble status DQS2 rank0 First edge position DQS2 rank0 Preamble status DQS10 rank0 First edge position DQS10 rank0 Preamble status DQS1 rank0 First edge position DQS1 rank0 Preamble status DQS9 rank0 First edge position DQS9 rank0 Preamble status DQS0 rank0 First edge position DQS0 rank0 DQS Cal Min delay DQS9 rank1 Max delay DQS0 rank1 Min delay DQS0 rank1 Max delay DQS17 rank0 Min delay DQS17 rank0 Max delay DQS8 rank0 Min delay DQS8 rank0 Max delay DQS16 rank0 Min delay DQS16 rank0 Max delay DQS7 rank0 Min delay DQS7 rank0 Max delay DQS15 rank0 Min delay DQS15 rank0 Max delay DQS6 rank0 Min delay DQS6 rank0 Max delay DQS14 rank0 Min delay DQS14 rank0 Max delay DQS5 rank0 Min delay DQS5 rank0 Max delay DQS13 rank0 Min delay DQS13 rank0 Max delay DQS4 rank0 Min delay DQS4 rank0 Max delay DQS12 rank0 Min delay DQS12 rank0 Max delay DQS3 rank0 Min delay DQS3 rank0 Max delay DQS11 rank0 Min delay DQS11 rank0 Max delay DQS2 rank0 Min delay DQS2 rank0 Max delay DQS10 rank0 Min delay DQS10 rank0 Max delay DQS1 rank0 Min delay DQS1 rank0 Max delay DQS9 rank0 Min delay DQS9 rank0 Max delay DQS0 rank0 Min delay DQS0 rank0 Intel® 6400/6402 Advanced Memory Buffer Datasheet 207 Registers DCALDATA Receiver Enable “First edge position” byte detail Bit 7:0 Description At the end of a successful calibration, this register holds the DRRTC setting that enables the DQS receiver as close as possible to but no earlier than the first rising DQS transition after the preamble. At the start of the calibration, this register is loaded with a value of 0xFF. During the calibration, while the “strobe toggle status” bit is low, this register will be updated with the DRRTC value for the current calibration step if the DQS is found to have a value of zero. After “strobe toggle status” goes high, this register will be updated with the DRRTC value when the DQS is found to have a value of one at a calibration step. This register will no longer be updated after the “preamble found status” bit goes high, so that it will retain the position of the rising DQS edge following immediately after the preamble. DCALDATA Receiver Enable “Preamble status” byte detail Bit 7 Description Strobe toggle status. Hardware sets this bit if a valid high pulse is found in the strobe waveform. The requirement is (DCALDATA.First_edge_position - last receiver enable delay value) > RCVENAC.HWIDTH Preamble found status. Hardware sets this bit if the “preamble found” bit asserts at any time during the calibration. Preamble found. Last receiver enable delay value meets or exceeds the preamble width requirement setting. Hardware sets this bit if: (DCALDATA.First_edge_position - last receiver enable delay value) > RCVENAC.PWIDTH Count of “lows” minus count of “highs” found during one set of repeated tests at the last receiver enable delay setting. See DCALCSR opmods field for a description of the repeat test function. 6 5 4:0 DCALDATA DQS Cal Max Delay detail Bit 7:6 5:0 reserved At the end of a successful calibration, this field will hold the maximum DQS delay setting that results in correct data capture in the DDR I/O capture flop. This is the right edge of the DQ data eye. During the calibration, this field is updated with the DQS delay setting at each calibration step until the minimum delay setting is found and a subsequent failure to capture correct read data occurs. Description Table 14-16. Functional Characteristics of DCALDATA for HVM Algorithms Byte 71:3 6 35 34 33 32 31 30 Not used First “All Bits Failed” position and Status DQS17 First “Any Bit Failed” Position and Status DQS17 First “All Bits Failed” position and Status DQS8 First “Any Bit Failed” Position and Status DQS8 First “All Bits Failed” position and Status DQS16 First “Any Bit Failed” Position and Status DQS16 Core Counter DQS16 Core Counter DQS8 I/O Loopback Not used Core Counter DQS17 DLL BIST 208 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Table 14-16. Functional Characteristics of DCALDATA for HVM Algorithms Byte 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I/O Loopback First “All Bits Failed” position and Status DQS7 First “Any Bit Failed” Position and Status DQS7 First “All Bits Failed” position and Status DQS15 First “Any Bit Failed” Position and Status DQS15 First “All Bits Failed” position and Status DQS6 First “Any Bit Failed” Position and Status DQS6 First “All Bits Failed” position and Status DQS14 First “Any Bit Failed” Position and Status DQS14 First “All Bits Failed” position and Status DQS5 First “Any Bit Failed” Position and Status DQS5 First “All Bits Failed” position and Status DQS13 First “Any Bit Failed” Position and Status DQS13 First “All Bits Failed” position and Status DQS4 First “Any Bit Failed” Position and Status DQS4 First “All Bits Failed” position and Status DQS12 First “Any Bit Failed” Position and Status DQS12 First “All Bits Failed” position and Status DQS3 First “Any Bit Failed” Position and Status DQS3 First “All Bits Failed” position and Status DQS11 First “Any Bit Failed” Position and Status DQS11 First “All Bits Failed” position and Status DQS2 First “Any Bit Failed” Position and Status DQS2 First “All Bits Failed” position and Status DQS10 First “Any Bit Failed” Position and Status DQS10 First “All Bits Failed” position and Status DQS1 First “Any Bit Failed” Position and Status DQS1 First “All Bits Failed” position and Status DQS9 First “Any Bit Failed” Position and Status DQS9 First “All Bits Failed” position and Status DQS0 First “Any Bit Failed” Position and Status DQS0 Core Counter DQS0 Core Counter DQ9 Core Counter DQS1 Core Counter DQS10 Core Counter DQS2 Core Counter DQS11 Core Counter DQS3 Core Counter DQS12 Core Counter DQS4 Core Counter DQS13 Core Counter DQS5 Core Counter DQS14 Core Counter DQS6 Core Counter DQS15 DLL BIST Core Counter DQS7 DCALDATA I/O Loopback “Any Bit Failed” detail Bit 7 6 5:0 Description First “First Any bit Failed” Nibble. This bit is set if the nibble associated with this register is one of the first to fail to capture data correctly during the test. reserved At the end of the test, this field will contain the minimum DQS delay setting that results in one or more bits of a burst to be captured incorrectly. Intel® 6400/6402 Advanced Memory Buffer Datasheet 209 Registers DCALDATA I/O Loopback “All Bits Failed” detail Bit 7 6 5:0 Description Last “First All Bits Failed” Nibble. This bit is set if the nibble associated with this register is one of the last to capture an entire data burst incorrectly during the test. reserved At the end of the test, this field will contain the minimum DQS delay setting that results all bits of a burst to be captured incorrectly. DCALDATA DLL BIST Core Counter detail Bit 15:0 Description At the end of the test this two byte register will contain the number of core cycles counted from the time the associated DLL delay line outputs a “terminal count” number of self-oscillation cycles. The terminal count is defined by the DDBISTLM.TCOUNT register. 14.6.1.4 DDBISTLM: DDR DLL BIST Limits This register contains test limits for DDR DLL BIST. Device: NodeID Function: 4 Offset: 90h Bit 23:16 15:0 Attr RWST RWST Default 0Fh 000Fh Description TCOUNT: DLL delay line output terminal count CVAR: core count variation limit 14.6.1.5 RCVENAC: Receiver Enable Algorithm Control This register contains controls for the preamble detection algorithm of the automatic receiver enable logic. RCVENAC.PWIDTH is used to determine if a “low” pulse in a DQS waveform is wide enough to be a preamble. RCVENAC.POFFSET is subtracted from the DCALDATA first edge position result and programmed into the DRRTC registers. Device: NodeID Function: 4 Offset: 94h Bit 23:16 Attr RWST Default 18h Description PWIDTH: Minimum preamble width limit, used to detect if a low pulse in a DQS waveform is wide enough to be a valid preamble. The default corresponds to 3/4 of a DRAM clock cycle Reserved HWIDTH: Minimum high pulse width limit, used to detect if a high pulse in a DQS waveform is wide enough to indicate a strobe is toggling in a valid manner. The default corresponds to 1/4 of a DRAM clock cycle. Reserved POFFSET: Preamble center offset from first rising edge, used to position the DQS receiver enable relative to the preamble edge location recorded in the DCALDATA registers. The default value corresponds to 1/2 of a DRAM clock cycle. 15:14 13:8 RV RWST 0h 08h 7:6 5:0 RV RWST 0h 10h 210 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.6.1.6 DSRETC: DRAM Self-Refresh Extended Timing and Control This register sets the timing of operations to different ranks while the auto-refresh FSM controls the DRAM command bus. This allows power intensive commands to be staggered. This register also contains the count for the auto-refresh FSM handshake time out. The FSM will wait a maximum of the time out count before taking control of the bus and issuing the command sequence to put the DRAMs into self-refresh. The RSTREQERR bit of the DSREFTC CSR will be set if the time out count is reached. Device: NodeID Function: 4 Offset: 98h Bit 31:24 23:16 15:8 7:0 Attr RV RWST RWST RWST Default 0h 14h 14h FFh Reserved DRSRENT: dual rank self-refresh entry timing - stagger of commands between ranks DRARTIM: dual rank auto-refresh timing- stagger of commands between ranks TREQERR: reset handshake time out count (counts in x16 of core clock) If times out - forces DRAMs into self-reset even if no handshake received from MemBIST or other logic after link goes into fast reset Description 14.6.1.7 DQSFAIL There are two DQSFAIL registers that contain a total of 36 individual DQS failure status bits. There is one status bit for each DQS signal pair on each rank. These bits are set automatically by hardware during the receiver enable calibration if a valid DQS waveform is not detected. Hardware will not clear any bits that are set prior to the calibration even if a valid waveform is detected. Hardware uses the DQSFAIL information to exclude calibration data during the data gathering portion and/or the data analysis portion of the both the receiver enable and DQS delay calibrations. This prevents a failed DQS pin from corrupting the calibration of neighboring functional DQS pins that may share internal logic resources with a failing DQS pin. 14.6.1.8 DQSFAIL1: DQS Failure Configuration Register 1 Device: NodeID Function: 4 Offset: 9Ch Bit 7:4 3 2 1 0 Attr RV RWST RWST RWST RWST Default 0h 0 0 0 0 Reserved r1dqs17: rank 1 r1dqs08: rank 1 r1dqs16: rank 1 r1dqs07: rank 1 Description Intel® 6400/6402 Advanced Memory Buffer Datasheet 211 Registers 14.6.1.9 DQSFAIL0: DQS Failure Configuration Register 0 Device: NodeID Function: 4 Offset: A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Attr RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST RWST Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r1dqs15: rank 1 r1dqs06: rank 1 r1dqs14: rank 1 r1dqs05: rank 1 r1dqs13: rank 1 r1dqs04: rank 1 r1dqs12: rank 1 r1dqs03: rank 1 r1dqs11: rank 1 r1dqs02: rank 1 r1dqs10: rank 1 r1dqs01: rank 1 r1dqs09: rank 1 r1dqs00: rank 1 r0dqs17: rank 0 r0dqs08: rank 0 r0dqs16: rank 0 r0dqs07: rank 0 r0dqs15: rank 0 r0dqs06: rank 0 r0dqs14: rank 0 r0dqs05: rank 0 r0dqs13: rank 0 r0dqs04: rank 0 r0dqs12: rank 0 r0dqs03: rank 0 r0dqs11: rank 0 r0dqs02: rank 0 r0dqs10: rank 0 r0dqs01: rank 0 r0dqs09: rank 0 r0dqs00: rank 0 Description 14.6.1.10 Note: DRRTC: Receive Enable Reference Output Timing Control Registers These registers have to be saved and restored on S3. 212 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers The DRRTC is a set of three registers with DQS receiver enable window timing control for each byte on the DDR data bus. There is a single control for each byte for both ranks. A correct register setting will delay the start of the enable window so that it coincides with the middle of the DQS pre-amble. Enabling the window before or after the pre-amble would cause valid DQS edges to be missed or invalid edges or noise to be received. The range of the enable delay, controlled by the DRRTC registers, is eight cycles, with a granularity defined by the SPDPAR06CUR.MASTCNTL register. The delay is measured from the AMC core clock edge that launches a “read” command on the DDR command bus. The minimum delay is equal to the DDR SDRAM read latency defined in the DRC.CL and DRC.AL register fields. The maximum delay is the read latency plus eight cycles. In addition to these major sources of delay, there is also a small “uncompensated delay” as shown in the formulas below. The RCVEN fields of the DRRTC register control the delay as follows: bits [7:5] control whole clock increments, bits [4:3] control in quarter clock increments, and bits [2:0] control the sub-quarter cycle increments. Setting RCVEN to 0x0 produces the minimum delay, and 0xFF sets the maximum delay. The sub-quarter cycle delay is defined by the equations and “RCVEN_OUT” lookup table below: Delay_Uncomp = 100ps; Note: estimate only Delay Element = (quarter CMDCLK period - Delay_Uncomp) / ( MASTCNTL + 0.5) sub quarter cycle delay = Delay_Uncomp + (Delay Element * RCVEN_OUT[2:0]) RCVEN_OUT Lookup Table SPDPAR06CUR MASTCNTL] 7 6 5 4 3 2 1 0 DRRTC RCVEN [2:0] 7 7 6 5 4 3 2 1 0 6 6 5 4 4 3 2 1 0 5 5 4 3 2 2 1 0 5 4 4 3 3 2 1 1 0 4 3 3 2 2 1 1 0 0 3 2 2 1 1 1 0 0 0 2 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 For example, if the SPDPAR06CUR.MASTCNTL is set to 0x7, the receiver enable delay can be varied over eight cycle in 256 steps, one step for each DRRTC RCVEN setting. If SPDPAR06CUR.MASTCNTL is set to 0x3, however, the number of steps is reduced to 128, such that half of the DRRTC RCVEN settings do not produce an increase in delay from the previous setting. Intel® 6400/6402 Advanced Memory Buffer Datasheet 213 Registers 14.6.1.11 DRRTC00: Receive Enable Reference Output Timing Control Register This register determines DQS12, 3, 11, 2, 10, 1, 9, & 0 input buffer enable timing delay Device: NodeID Function: 4 Offset: A4h Bit 31:24 23:16 15:8 7:0 Attr RWST RWST RWST RWST Default 20h 20h 20h 20h Description RCVEN1203: receiver enable delay for DQS12 and 3 RCVEN1102: receiver enable delay for DQS11 and 2 RCVEN1001: receiver enable delay for DQS10 and 1 RCVEN0900: receiver enable delay for DQS9 and 0 14.6.1.12 DRRTC01: Receive Enable Reference Output Timing Control Register This register determines DQS16, 7, 15, 6, 14, 5, 13, & 4 input buffer enable timing delay. Device: NodeID Function: 4 Offset: A8h Bit 31:24 23:16 15:8 7:0 Attr RWST RWST RWST RWST Default 20h 20h 20h 20h Description RCVEN1607: receiver enable delay for DQS16 and 7 RCVEN1506: receiver enable delay for DQS15 and 6 RCVEN1405: receiver enable delay for DQS14 and 5 RCVEN1304: receiver enable delay for DQS13 and 4 14.6.1.13 DRRTC02: Receive Enable Reference Output Timing Control Register This register determines DQS17 & 8 input buffer enable timing delay. Device: NodeID Function: 4 Offset: C4h Bit 7:0 Attr RWST Default 20h Description RCVEN1708: receiver enable delay for DQS17 and 8 14.6.1.14 DQS Calibration Registers The DQSOFCS is a group of six registers that control the fine delay used to center DQS edges to the DQ data eye during read operations. There is a delay entry for each nibble of the DDR data bus for each rank. The coarse delay is controlled by the DRAMDLLC register. The equations for the fine and coarse delays are shown below. Note that “Delay Element” and “Delay_Uncomp” are defined in the DRRTC register section. Also note that there is a separate coarse delay control for each “chunk” of the DDR I/O cluster as defined in the DRAMDLLC register section. slvlen_not_at_max[m] = DRAMDLLC.SLVLENm[2:0] < 7; where m is the DDR I/O cluster chunk number increment_slvlen[i,n] = slvlen_not_at_max AND ( DQSOFCSi.DQSn[3:0] > 7 ); where i and n are the DQSOFCS register and DQS field numbers respectively 214 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers slvlen[i,m,n] = DRAMDLLC.SLVLENm[2:0] + increment_slvlen[i,n] Programable_Delay[i,m,n] = ( Delay Element ) * ( slvlen[i,m,n] + 0.5 + DQSOFCSi.DQSn[2:0]/8 ) DQS_Delay[i,m,n] = Delay_Uncomp + Programmable_Delay[i,m,n] Note: these registers may have to be saved and restored on S3 14.6.1.15 DQSOFCS00: DQS Calibration Register This register determines DQS12, 3, 11, 2, 10, 1, 9, & 0 fine DQS delay when reading from rank 0. Device: NodeID Function: 4 Offset: B4h Bit 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 Attr RWST RWST RWST RWST RWST RWST RWST RWST Default 0h 0h 0h 0h 0h 0h 0h 0h DQS12: Fine delay DQS03: Fine delay DQS11: Fine delay DQS02: Fine delay DQS10: Fine delay DQS01: Fine delay DQS09: Fine delay DQS00: Fine delay Description 14.6.1.16 DQSOFCS01: DQS Calibration Register This register determines DQS16, 7, 15, 6, 14, 5, 13, & 4 fine DQS delay when reading from rank 0. Device: NodeID Function: 4 Offset: B8h Bit 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 Attr RWST RWST RWST RWST RWST RWST RWST RWST Default 0h 0h 0h 0h 0h 0h 0h 0h DQS16: Fine delay DQS07: Fine delay DQS15: Fine delay DQS06: Fine delay DQS14: Fine delay DQS05: Fine delay DQS13: Fine delay DQS04: Fine delay Description Intel® 6400/6402 Advanced Memory Buffer Datasheet 215 Registers 14.6.1.17 DQSOFCS02: DQS Calibration Register This register determines DQS17 & 8 fine DQS delay when reading from rank 0. Device: NodeID Function: 4 Offset: C6h Bit 7:4 3:0 Attr RWST RWST Default 0h 0h DQS17: Fine DLL delay DQS08: Fine DLL delay Description 14.6.1.18 DQSOFCS10: DQS Calibration Register This register determines DQS12, 3, 11, 2, 10, 1, 9, & 0 fine DQS delay when reading from rank 1. Device: NodeID Function: 4 Offset: BCh Bit 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 Attr RWST RWST RWST RWST RWST RWST RWST RWST Default 0h 0h 0h 0h 0h 0h 0h 0h DQS12: Fine delay DQS03: Fine delay DQS11: Fine delay DQS02: Fine delay DQS10: Fine delay DQS01: Fine delay DQS09: Fine delay DQS00: Fine delay Description 14.6.1.19 DQSOFCS11: DQS Calibration Register This register determines DQS16, 7, 15, 6, 14, 5, 13, & 4 fine DQS delay when reading from rank 1. . Device: NodeID Function: 4 Offset: C0h Bit 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 Attr RWST RWST RWST RWST RWST RWST RWST RWST Default 0h 0h 0h 0h 0h 0h 0h 0h DQS16: Fine delay DQS07: Fine delay DQS15: Fine delay DQS06: Fine delay DQS14: Fine delay DQS05: Fine delay DQS13: Fine delay DQS04: Fine delay Description 216 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.6.1.20 DQSOFCS12: DQS Calibration Register This register determines DQS17 & 8 fine DQS delay when reading from rank 1. Device: NodeID Function: 4 Offset: C7h Bit 7:4 3:0 Attr RWST RWST Default 0h 0h DQS17: Fine DLL delay DQS08: Fine DLL delay Description 14.6.1.21 WPTRTC DDR I/O Write Pointer Timing The two WPTRTC registers control the fine delay of the DDR I/O FIFO write pointers. The formulas for delay shown in the DQSOFCS and DRRTC register sections are identical to the write pointer delay formulas. To find the WPTRTC portion of write pointer delay, use the DQSOFCS formulas, and substitute WPTRTC fields for all the DQSOFCS fields. The only difference in the application of these formulas is that there is only one WPTRTC field per byte of the DDR I/O, whereas the DQSOFCS has a field per nibble per rank. The total write pointer delay, measured from the same reference point as the DQS receiver enable timing, is equal to the DQS receiver enable timing, including the quarter clock and sub-quarter clock delays, plus one full clock cycle, plus the coarse and fine DRAMDLLC.SLVLEN/WPTRTC delays calculated with the formulas from the DQSOFCS register section. 14.6.1.22 WPTRTC0: Write Pointer Timing Control 0 This register determines the DDR I/O FIFO write pointer fine delay timing for all DQS signals except DQS17 and DQS8 when reading from rank 0 or rank 1. Device: NodeID Function: 4 Offset: CCh Bit 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 Attr RWST RWST RWST RWST RWST RWST RWST RWST Default 0h 0h 0h 0h 0h 0h 0h 0h Description DQS1607: DQS16 and DQS7 write pointer fine delay DQS1506: DQS15 and DQS6 write pointer fine delay DQS1405: DQS14 and DQS5 write pointer fine delay DQS1304: DQS13 and DQS4 write pointer fine delay DQS1203: DQS12 and DQS3 write pointer fine delay DQS1102: DQS11 and DQS2 write pointer fine delay DQS1001: DQS10 and DQS1 write pointer fine delay DQS0900: DQS9 and DQS0 write pointer fine delay Intel® 6400/6402 Advanced Memory Buffer Datasheet 217 Registers 14.6.1.23 WPTRTC1: Write Pointer Timing Control 1 This register determines the DDR I/O FIFO write pointer fine delay timing for DQS17 and DQS8 signals when reading from rank 0 or rank 1. Device: NodeID Function: 4 Offset: D0h Bit 7:4 3:0 Attr RV RWST Default 0h 0h Reserved DQS01708: Rank 0 DQS17 and DQS8 write pointer fine delay Description 14.6.1.24 DDQSCVDP and DDQSCADP This set of 4 registers defines two 64 bit long data patterns used in the DQS Delay Calibration. They are only used when DCALCSR.BASPAT is low. The 64 bit patterns cover a data burst that is 32 DRAM clock cycles long. The DDQSCVDP registers define the “victim” pattern, and the DDQSCADP defines the “aggressor” pattern. The victim pattern is applied to one bit of each byte of the DDR data bus for 32 clock cycles, and the aggressor pattern is applied to all other bits. The victim pattern is applied in turn to each bit of each byte, creating a complete data pattern that is 8*32 data cycles long. 14.6.1.25 DDQSCVDP0: DQS DELAY CAL PATTERN 0 This register defines the last 32 bits of the 64 bit long “victim” data pattern. Device: NodeID Function: 4 Offset: D4h Bit 31:0 Attr RW Default aaaa0a05h ENABLE: Description 14.6.1.26 DDQSCVDP1: DQS DELAY CAL PATTERN 1 This register defines the first 32 bits of the 64 bit long “victim” data pattern. Device: NodeID Function: 4 Offset: D8h Bit 31:0 Attr RW Default 5b339c5dh ENABLE: Description 14.6.1.27 DDQSCADP0: DQS DELAY CAL PATTERN 0 This register defines the last 32 bits of the 64 bit long “aggressor” data pattern. Device: NodeID Function: 4 Offset: DCh Bit 31:0 Attr RW Default aaabffffh ENABLE: Description 218 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.6.1.28 DDQSCADP1: DQS DELAY CAL PATTERN 1 This register defines the first 32 bits of the 64 bit long “aggressor” data pattern. Device: NodeID Function: 4 Offset: E0h Bit 31:0 Attr RW Default db339ce1h ENABLE: Description 14.6.2 14.6.2.1 Memory Interface Control DIOMON: DDR I/O Monitor This register monitors the legsel output of the DDR I/O topcdat chunk and controls the A/D converter in the DDR I/O used to monitor analog voltage levels. Device: NodeID Function: 4 Offset: F0h Bit 15 14:12 11:8 7 6 5:0 Attr RW RWST RWST RWST RV RWST Default 0 0h 0h 0h 0h 00h Description ENABLE: Enable A/D converter and update vresult BIASSEL: A/D converter input selection LEGSELOUT: Legsel output of topcdat chunk DIOPWR: Reserved VRESULT: A/D converter output 14.6.2.2 ODTZTC: On-Die Termination Timing Control This register controls the enable and disable timing of the on-die termination on DQ and DQS pins. Timing can be adjusted in whole clock increments, or enabled statically. The ETIMR and DTIMR fields are added in hardware to the SPDPAR13CUR.ODTZ_ETIMR and SPDPAR13CUR.ODTZ_DTIMR register fields to control termination timing during reads. The DRRTC register is also used to align the enable/disable time to when read DQ/DQS signals are expected to arrive at the input pins. The combined default values of the ODTZTC and SPDPAR13CUR fields enable termination 1/2 DRAM clock cycle before the leading edge of the read DQS preamble arrives at the DQS pin, and keeps termination enabled for 5 clock cycles in BL4 mode, and 7 cycles in BL8 mode. The DDR I/O circuits automatically disable on-die termination when the DQ/DQS pins are driving. The default register values enable termination during writes at the same time that the pins are driving, so termination is effectively off during writes. Device: NodeID Function: 4 Offset: F4h Bit 15 14:12 11 Attr RWST RWST RV Default 0 0h 0 Description TIMORIDE: timing override. On-Die termination always on during read operations and when the bus is idle DTIMW: disable time after write data Reserved Intel® 6400/6402 Advanced Memory Buffer Datasheet 219 Registers Device: NodeID Function: 4 Offset: F4h Bit 10:8 7:4 3:0 Attr RWST RWST RWST Default 0h 0h 0h Description DTIMR: disable time after read data ETIMW: enable time before write data ETIMR: enable time before read data 14.6.2.3 DRAMISCTL: Miscellaneous DRAM DDR Cluster Control Device: NodeID Function: 4 Offset: F8h Bit 31:13 12 11 10 9 8 7:0 Attr RV RWST RW RW RW RW RWST Default 0000h 1 0 0 0 0 11h Reserved VOXSTART: Enable the voltage output crossing control loop in the DDR I/O. This bit is AND’ed with the SPDPAR1011CUR.vox_start bit. AVMODE: analog validation mode OCDLOADENABLE: calibration load placed on incoming signals for DDR2 DRAM OCD calibration OCDPOLSEL: set for pull up calibration, clear for pull down OCDRCOMPEN: VREFSEL: vref selection Description Details of DRAMISCTL VREF Field Settin g TBD Description 14.6.2.4 DDR2ODTC: DDR2 DRAM On-Die Termination Control The DDR2ODTC controls the behavior of the ODT output (one ODT output per command bus copy). There is a separate field to control the behavior for reads to rank0, reads to rank1, writes to rank0, and writes to rank1. Only the lsb of each field is used, and the msb has no effect. When an lsb of a field is set to one, the ODT pins will drive high, at the appropriate time relative to data on the DDR bus, when the selected transaction (read or write) is issued to the selected rank (0 or 1). If a field is set to 0, the ODT output continues to drive low during the transaction, as it does during idle cycles. Device: NodeID Function: 4 Offset: FCh Bit 7:6 Attr RWST Default 0h Description R1ODTWR: ODT control during writes to CS1 x1: ODT pins will drive high x0: ODT pins remain driving low R1ODTRD: ODT control during reads to CS1 R0ODTWR: ODT control during writes to CS0 5:4 3:2 RWST RWST 0h 0h 220 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 4 Offset: FCh Bit 1:0 Attr RWST Default 0h Description R0ODTRD: ODT control during reads to CS0 14.6.2.5 DRAMDLLC: DDR I/O DLL Control The formulas that show how the SLVLEN fields affect DQS delay timing are shown in the DQSOFCS register definition section. The SLVLEN fields are set by hardware during the DQS delay calibration. There are five SLVLEN fields, one for each “chunk”, or two bytes, of the DDR I/O DQ pins. The SLVBYP bit can be toggled to reset the master DLL’s in the DDR I/O. Device: NodeID Function: 4 Offset: C8h Bit 23:22 21 20:18 17:15 14:12 11:9 8:6 5:0 Attr RV RW RWST RWST RWST RWST RWST RV Default 00h 0h 3h 3h 3h 3h 3h 00h Reserved SLVBYP: DQS delay bypass SLVLEN4: dqs17 & 8 coarse DQS delay SLVLEN3: dqs16, 7, 15, & 6 coarse DQS delay SLVLEN2: dqs14, 5, 13, & 4 coarse DQS delay SLVLEN1: dqs12, 3, 11, & 2 coarse DQS delay SLVLEN0: dqs10, 1, 9, & 0 coarse DQS delay Reserved Description 14.6.3 14.6.3.1 Firmware Support Registers FIVESREG: Fixed 5’s Pattern Constant value used for debug. Device: NodeID Function: 4 Offset: E8h Bit 31:0 Attr RO Default 55555555h Description FIVES: Hardwired to 5’s for read-return 14.6.3.2 AAAAREG: Fixed A’s Pattern Constant value used for debug. Device: NodeID Function: 4 Offset: ECh Bit 31:0 Attr RO Default AAAAAAAAh Description AAAAS: Hardwired to A’s for read-return Intel® 6400/6402 Advanced Memory Buffer Datasheet 221 Registers 14.7 14.7.1 14.7.1.1 . DFX Registers (Function 5) Transparent Mode Registers TRANSCFG: Transparent Mode Configuration This register enables and controls FBD DFX transparent mode features. Device: NodeID Function: 5 Offset: 3Ch Bit 31:29 28 27 26 25:24 Attr RV RWST RWST RWST RWST Default 0h 0 0 0 00 Reserved ENDOUT: enable data output on transparent data/status pins when set, output status when clear LGFBITS: log bits that fail the compare when set, log raw read data when clear. LGFFAIL: log first failure in any burst position. BSTPOS: burst position to log data/failed bits from when LGFFAIL bit is not set. 0 = first burst in bl4 or bl8 mode 1 = last burst of bl4, second burst of bl8 2 = third burst of bl8 3 = last burst of bl8 DRAMRD: byte of data bus selected to be output on transparent data/status pins when ENDOUT bit is set. 8= DQS 17 and DQS 8 7= DQS 16 and DQS 7 ... 0 = DQS 9 and DQS 0 DRAMWR: byte of data bus selected to receive transparent write data, and byte of data bus to be compared against transparent read data. Fh = all bytes 8= DQS 17 and DQS 8 7= DQS 16 and DQS 7 ... 0 = DQS 9 and DQS 0 DFTDATA: default data for bytes not selected by the DRAMWR field. This field has early/even data in the upper 8 bits, and late/odd data in the lower 8 bits. Description 23:20 RWST 0h 19:16 RWST 0h 15:0 RWST 0000h 14.7.1.2 TRANDERR[8:0]: Transparent Mode Data Error Logs This register stores data returned from DRAM byte groups on failing transparent mode tests. Device: NodeID Function: 5 Offset: 50h, 4Eh, 4Ch, 4Ah, 48h,46h, 44h, 42h, 40h Bit 15:8 7:0 Attr RWST RWST Default 00h 00h LATE_DATA: EARLY_DATA: Description 14.7.1.3 TRANSCTRL: Transparent Mode Control 222 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers This register enables and controls FBD DFX transparent mode features. Device: NodeID Function: 5 Offset: 80h Bit 7:1 0 Attr RV RWST Default 00h 0 Reserved ENTRNSPMODE: Transparency Mode Enable 1 - Enables Transparency Mod Description 14.7.2 14.7.2.1 Logic Analyzer Interface (LAI) Registers LAI: LAI Operation Modes This register controls and reports the AMB’s LAI mode and Qual controls. Device: NodeID Function: 5 Offset: B8h Bit 31:16 15 Attr RV RWST Default 0000h 0 Reserved RAWMODE: data connected to LAI 0: LAI outputs contain initialization state information prior to L0S then lane data after L0S 1: LAI outputs connected to FBD data inputs even though valid timing is not present Reserved QUALMODE: Assert Qual for all non-filtered frames, or only assert Qual for all non-filtered frames between start and stop events. 0: Ignore Qual start/stop events 1: Assert Qual after a start event, and deassert Qual after a stop events FILTERSYNC: Filter the frame (do not assert Qual) if the frame is a sync. 0: Disable sync filtering 1: Enable sync filtering Reserved QUALPERIOD: Additional number of frames Qual remains asserted Power-on default to 63 Description 14 13 RV RWST 0 0 12 RWST 0 11:6 5:0 RV RWST 00h 3Fh 14.7.2.2 SBMATCHU: Upper Southbound Match Register This register sets the upper 8 bits of data match for three southbound commands. Device: NodeID Function: 5 Offset: BCh Bit 31:24 23:16 Attr RV RWST Default 00h 00h Reserved CMD2: Upper 8 bits [39:32] of southbound command 2 Description Intel® 6400/6402 Advanced Memory Buffer Datasheet 223 Registers Device: NodeID Function: 5 Offset: BCh Bit 15:8 7:0 Attr RWST RWST Default 00h 00h Description CMD1: Upper 8 bits [39:32] of southbound command 1 CMD0: Upper 8 bits [39:32] of southbound command 0 Match and Mask bit numbering of SB frames is as follows: • where N= 0 for slot A, 4 for slot B and 8 for slot C Table 14-17. Bit Locations for SB Match and Mask Xfr\lane 0+N 1+N 2+N 3+N 9 B36 B37 B38 B39 8 B32 B33 B34 B35 7 B28 B29 B30 B31 6 B24 B25 B26 B27 5 B20 B21 B22 B23 4 B16 B17 B18 B19 3 B12 B13 B14 B15 B8 B9 B10 B11 2 B4 B5 B6 B7 1 B0 B1 B2 B3 0 14.7.2.3 SBMATCHL0: Lower Southbound Match Register 0 This register sets the lower 32 bits of data match for match southbound command 0. Device: NodeID Function: 5 Offset: C0h Bit 31:0 Attr RWST Default 00004000h Description CMD: Lower 32bits [31:0] of southbound command power on default = match Synch 14.7.2.4 SBMATCHL1: Lower Southbound Match Register 1 This register sets the lower 32 bits of data match for match southbound command 1. Device: NodeID Function: 5 Offset: C4h Bit 31:0 Attr RWST Default 00100000h Description CMD: Lower 32bits [31:0] of southbound command power on default = match Activate 224 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.7.2.5 SBMATCHL2: Lower Southbound Match Register 2 This register sets the lower 32 bits of data match for match southbound command 2. Device: NodeID Function: 5 Offset: C8h Bit 31:0 Attr RWST Default 00014000h Description CMD: Lower 32bits [31:0] of southbound command power on default = match Write Config Reg 14.7.2.6 SBMASKU: Upper Southbound Mask Register This register sets the upper 8 bits of data mask for three southbound commands. Device: NodeID Function: 5 Offset: CCh Bit 31:24 23:16 Attr RV RWST Default 00h 00h Reserved CMDMASK2: Upper 8 bits [39:32] of southbound command 2 mask 0: Do not include this bit in match comparison 1: Include this bit in match comparison CMDMASK1: Upper 8 bits [39:32] of southbound command 1 mask 0: Do not include this bit in match comparison 1: Include this bit in match comparison CMDMASK0: Upper 8 bits [39:32] of southbound command 0 mask 0: Do not include this bit in match comparison 1: Include this bit in match comparison Description 15:8 RWST 00h 7:0 RWST 00h 14.7.2.7 SBMASKL0: Lower Southbound Mask Register 0 This register sets the lower 32 bits of data mask for match southbound command 0. Device: NodeID Function: 5 Offset: D0h Bit 31:0 Attr RWST Default 031FC000h Description CMDMASK: Lower 32bits [31:0] of southbound command mask. 0: Do not include this bit in match comparison 1: Include this bit in match comparison power on default = match Sync Intel® 6400/6402 Advanced Memory Buffer Datasheet 225 Registers 14.7.2.8 SBMASKL1: Lower Southbound Mask Register 1 This register sets the lower 32 bits of data mask for match southbound command 1. Device: NodeID Function: 5 Offset: D4h Bit 31:0 Attr RWST Default 00100000h Description CMDMASK: Lower 32bits [31:0] of southbound command mask. 0: Do not include this bit in match comparison 1: Include this bit in match comparison power on default = match Activate 14.7.2.9 SBMASKL2: Lower Southbound Mask Register 2 This register sets the lower 32 bits of data mask for match southbound command 2. Device: NodeID Function: 5 Offset: D8h Bit 31:0 Attr RWST Default 001FC000h Description CMDMASK: Lower 32bits [31:0] of southbound command mask. 0: Do not include this bit in match comparison 1: Include this bit in match comparison power on default = match Write Config Reg 14.7.2.10 MMEVENTSEL: Match/Mask Event Selection Register Selects 1 of 13 local match events described below for promotion to local event select. Three local events MMEVENT[2:0] can be associated with one of these local match events. Device: NodeID Function: 5 Offset: DCh Bit 15:12 11:8 7:4 3:0 Attr RV RWST RWST RWST Default 0h 2h Ah 3h Reserved MMEVENT2SEL: default: match pattern 0 to slot A only for sync MMEVENT1SEL: default: match pattern 1 to slot A, B, or C for activate MMEVENT0SEL: default: match pattern 2 to slot B only for write config reg Description . MM Event 15:13 12 Reserved Description FRAMEMATCH Bit pattern in slot A matches SBMATCH/SBMASK 0 AND Bit pattern in slot B matches SBMATCH/SBMASK 1 AND Bit pattern in slot C matches SBMATCH/SBMASK 2 226 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers MM Event 11 10 9 8 7 6 5 4 3 2 1 0 Description SLOTMATCH0 Command in slot A, B, or C matches SBMATCH/SBMASK 0 SLOTMATCH1 Command in slot A, B, or C matches SBMATCH/SBMASK 1 SLOTMATCH2 Command in slot A, B, or C matches SBMATCH/SBMASK 2 SLOTCMATCH0 Command in slot C matches SBMATCH/SBMASK 0 SLOTCMATCH1 Command in slot C matches SBMATCH/SBMASK 1 SLOTCMATCH2 Command in slot C matches SBMATCH/SBMASK 2 SLOTBMATCH0 Command in slot B matches SBMATCH/SBMASK 0 SLOTBMATCH1 Command in slot B matches SBMATCH/SBMASK 1 SLOTBMATCH2 Command in slot B matches SBMATCH/SBMASK 2 SLOTAMATCH0 Command in slot A matches SBMATCH/SBMASK 0 SLOTAMATCH1 Command in slot A matches SBMATCH/SBMASK 1 SLOTAMATCH2 Command in slot A matches SBMATCH/SBMASK 2 14.7.2.11 EVENTSEL0: Event Selection Register In LAI mode, selects 1 of 32 local events (see EVENT register) for 2 uses (Qual Start and Qual Stop) and sets programmable delay for QualStop. In Normal mode, selects local event for 2 uses (error injection and NB in-band event signaling) and sets programmable delay for error injection. Device: NodeID Function: 5 Offset: E0h Bit 31:21 20:15 Attr RV RWST Default 00h 3Fh Reserved QUALSTOPDELAY: in LAI Mode Additional number of clocks QualStop is delayed before use (0 to 63) Power-on default to 63 INJERRORDELAY: in Normal Mode Additional number of clocks INJERROR is delayed before use (0 to 63) Power-on default to 63 INBAND: in LAI Mode No effect. Northbound in-band debug events can not be asserted in LAI mode INBAND: in Normal Mode If selected event occurs, assert the northbound in-band event bit in next sync status 0 return and in FBDS0.S3 Description 14:10 RW 00h Intel® 6400/6402 Advanced Memory Buffer Datasheet 227 Registers Device: NodeID Function: 5 Offset: E0h Bit 9:5 Attr RWST Default 00h Description QUALSTART: in LAI Mode If selected event occurs, enable assertion of Qual until next QUALSTOP QUALSTOP: in LAI Mode • If selected event occurs, disable assertion of Qual until next QUALSTART INJERROR: in Normal Mode • If selected event occurs, inject error selected by EICNTL 4:0 RWST 00h 14.7.2.12 EVENTSEL1: Event Selection Register Selects 1 of 32 local events (see EVENT register) for each of six events transmitted to the LAI interface (events[5:0]). Device: NodeID Function: 5 Offset: E4h Bit 31:30 29:25 Attr RV RWST Default 00 0Ah Reserved LAITRIGGER5: Local event selected and transmitted to LAI as TRIGGER5 Default on power on to MM[1] event= Activate on any command LAITRIGGER4: Local event selected and transmitted to LAI as TRIGGER4 Default on power on to MM[2] event= Sync command in slot A LAITRIGGER3: Local event selected and transmitted to LAI as TRIGGER3 Default on power on to select in-band debug event 3 LAITRIGGER2: Local event selected and transmitted to LAI as TRIGGER2 Default on power on to select in-band debug event 2 LAITRIGGER1: Local event selected and transmitted to LAI as TRIGGER1 Default on power on to select in-band debug event 1 LAITRIGGER0: Local event selected and transmitted to LAI as TRIGGER0 Default on power on to select in-band debug event 0 Description 24:20 RWST 0Bh 19:15 RWST 13h 14:10 RWST 12h 9:5 RWST 11h 4:0 RWST 10h 14.7.2.13 EVENTSEL2: Event Selection Register Selects 1 of 32 local events (see EVENT register) for each of five events transmitted to the LAI interface (events[10:6]). Device: NodeID Function: 5 Offset: E8h Bit 31:30 Attr RV Default 00 Reserved Description 228 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 5 Offset: E8h Bit 29:25 24:20 Attr RV RWST Default 00h 04h Reserved LAITRIGGER10: Local event selected and transmitted to LAI as TRIGGER10 Default on power on to SB Unit Testing State detect LAITRIGGER9: Local event selected and transmitted to LAI as TRIGGER9 Default on power on to SB CRC error detect LAITRIGGER8: Local event selected and transmitted to LAI as TRIGGER8 Default on power on to Event Bus[1] event LAITRIGGER7: Local event selected and transmitted to LAI as TRIGGER7 Default on power on to Event Bus[0] event LAITRIGGER6: Local event selected and transmitted to LAI as TRIGGER6 Default on power on to MM[0] event= Write Register in command slot B Description 19:15 RWST 1Ah 14:10 RWST 0Dh 9:5 RWST 0Ch 4:0 RWST 09h 14.7.2.14 EVENT: Local LAI Event Register This register sets a bit if a local event is hit. Except for QUALFLAG, most local event signal internal to the AMB may assert for only one cycle. The event bits in this register remain set once asserted so that the history of the event being set is not lost. Note: The 5-bit select fields in the EVENTSEL0, EVENTSEL1, EVENTSEL2 and EVBUS registers use the bit mapping of this register to identify which local event to select. • For example, if EVENTSEL1.laitrigger0[4:0] = 26 decimal then trigger0 is connected to the SB CRC error event. • For example, if EVENTSEL1.laitrigger0[4:0] = 12 decimal then trigger0 is connected to the inbound EVBus[0] event, and so forth. Device: NodeID Function: 5 Offset: F0h Bit 31 30:25 Attr RWCST RWCST Default 0 00h Spare: ERROR EVENTS: • SB/NB failover[25], when unmasked: • SB CRC error[26], • thermal overload[27], • clock training violation (< 6 transitions in 512 UI) [28], • unimplemented register access[29], • other implementation specific errors[30] set on event and cleared by writing QUALFLAG: INBANDEV: SB link in-band EV[7:0] set on event and cleared by writing Description 24 23:16 RWCST RWCST 0 00h Intel® 6400/6402 Advanced Memory Buffer Datasheet 229 Registers Device: NodeID Function: 5 Offset: F0h Bit 15:12 11:9 8:1 Attr RWCST RWCST RWST Default 0h 0h 0h Description EV: Event Bus EV[3:0] set on event and cleared by writing MMEVENT: MMEVENT[2:0] selected by MMEVENTSEL set on event and cleared by writing LINKST: FBD Link State: Disable[1], calibrate[2], training[3], testing[4], pollling[5], config[6], l0[7], L0s or recalibrate[8] One hot encoding of FBD link state NULL: Null Event: Bit never set 0 RO 0 14.7.3 14.7.3.1 Error Injection Registers EICNTL: Error Injection Control This register controls the AMB error injection logic. Device: NodeID Function: 5 Offset: FCh Bit 7 Attr RW Default 0 Description EIEN:Error Injection Enable 1= Error Injection enabled 0= Error Injection disabled EITYPE: Type of error injection 111 = Reserved; 110 = Reserved 101 = Force NB Error bit on next Status return 100 = Force Alert on event 011 = Reserved 010 =Reserved 001= Corrupt NB CRC on event 000= No error injection Reserved 6:4 RW 000 3:0 RV 0h 14.7.3.2 STUCKL: Stuck “ON” FBD Lanes This register selects FBD Lanes to be stuck at “Electrical Idle” following a write to this register. Device: NodeID Function: 5 Offset: FEh Bit 7:4 3:0 Attr RV RWST Default 0h Fh Reserved NBSTUCK: NB Lane to be driven to EI to simulate a failed lane • 0h = lane 0: Dh = lane 13 and > 13 = NOP Description 230 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.8 14.8.1 Bring-up and Debug Registers (Function 6) SPAD[1:0]: Scratch Pad These bits have no effect upon the operation of the AMB. They are intended to be used by software for tracking changes in AMB state. These two registers are in different functions. Device: NodeID Function: 7, 6 Offset: 7Ch Bit 31:0 Attr RW Default 0000_0000h Description FREE: These bits are available for software definition. 14.8.2 14.8.2.1 Southbound FBD Intel® Interconnect BIST Registers SBFIBPORTCTL: Southbound FBD Intel® Interconnect BIST Port Control Register This register controls the operation of the Intel® Interconnect BIST (Intel® IBIST) logic. Please refer to Fully-Buffered DIMM DFx Specification for detailed description of the operation of Intel IBIST. Device: NodeID Function: 6 Offset: 80h Bit 31:24 23 Attr RV RWST Default 00h 0 Reserved SBNBMAP: Loopback mapping bit This bit will be sent during TS1 to the slave to specify which lanes needs to be looped back. Actual lanes looped back is specified in the FBD Architecture Spec. CMMSTR: Compliance Measurement Mode start This puts the Intel IBIST logic in CMM mode and Intel IBIST TX engine will start transmitting Intel IBIST patterns. ERRCNT: Error Counter Total number of frames with errors that were encountered by this port. ERRLNNUM: Error Lane Number This points to the first lane that encountered an error. If more than one lane reports an error in a cycle, the most significant lane number that reported the error will be logged. ERRSTAT: Port Error Status When Intel IBIST is started, status goes to 01 until first start delimiter is received and then goes to 00 until the end or to10 if an error occurs. 00: No error. 01: Did not receive first start delimiter. 10: Transmission error (first error). 11: Reserved for future use AUTOINVSWPEN: Auto Inversion sweep enable This bit enables the inversion shift register to continuously rotate the pattern in the FIBTXSHFT and FIBRXSHFT registers. 0: Disable Auto-inversion 1: Enable Auto-inversions Description 22 RWST 0 21:12 11:8 RWCST ROST 000h 0h 7:6 RWCST 00 5 RWST 0 Intel® 6400/6402 Advanced Memory Buffer Datasheet 231 Registers Device: NodeID Function: 6 Offset: 80h Bit 4 Attr RWST Default 0 Description STOPONERR: Stop IBIST on Error 0: Do not stop on error, only update error counter 1: Stop on error LOOPCON: Loop forever 0: No looping 1: Loop forever COMPLETE: IBIST done flag This bit is set when the receive engine is done checking. 0: Not done 1: Done MSTRMD: Master Mode Enable When this bit is set along with IBISTR, the Intel IBIST transmit engine is enabled to transmit Intel IBIST patterns. 0: Disable Master mode. 1: Enable master mode. IBISTR: IBIST Start When set, Intel IBIST starts transmitting after the TS1 header is recognized during the next link initialization sequence. and MSTRMD bit is set.This bit also enables the receive engine to start looking for the start delimiter during TS1 training set. This bit is reset when Intel IBIST receiver is done. The Intel IBIST transmit and receive engines can be stopped by setting this bit to 0. 0: Stop IBIST transmitter 1: Start IBIST transmitter 3 RWST 0 2 RWCST 0 1 RWST 0 0 RWST 0 14.8.2.2 SBFIBPGCTL: SB Intel IBIST Pattern Generator Control Register This register contains bits to control the operation of the Intel IBIST pattern generator. All counts are in 24 bit increments. Device: NodeID Function: 6 Offset: 84h Bit 31:26 Attr RWST Default 0Fh Description OVRLOOPCNT: Overall Loop Count 0h: Reserved 1h:3Fh: Number of times to loop all the patterns. CNSTGENCNT: Constant Generator Loop Counter 00h: Disable constant generator output 01h: 1Fh The number of times the constant generator counter pattern should loop before going to the next component. Each count represents 24 bits of 1’s or 0’s. CNSTGENSET: Constant Generator Setting 0: Generate 0 1: Generate 1 MODLOOPCNT: Modulo-N Loop Counter Each count represents 24 bits of the pattern specified by MODPERIOD. 00h: Disable Pattern Output 01h: 7Fh The number of times the Pattern Buffer should loop before going to the next component. 25:21 RWST 00h 20 RWST 0 19:13 RWST 0Fh 232 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers Device: NodeID Function: 6 Offset: 84h Bit 12:10 Attr RWST Default 001b Description MODPERIOD: Period of the Modulo-N counter Each encoding transmits a 24-bit pattern as specified below. All other encodings are reserved. 001: L/2 - 0101_0101_0101_0101_0101_0101 010: L/4 - 0011_0011_0011_0011_0011_0011 011: L/6 - 0001_1100_0111_0001_1100_0111 100: L/8 - 0000_1111_0000_1111_0000_1111 110: L/24 - 0000_0000_0000_1111_1111_1111 PATTLOOPCNT: Pattern Buffer Loop Counter 00h: Disable Pattern Output 01h: 7Fh The number of times the Pattern Buffer (FIBPATTBUF1) should be repeated before going to the next component. PTGENORD: Pattern Generation Order 000: Pattern Store + Modulo N Cntr + Constant Generator 001: Pattern Store + Constant Generator + Modulo N Cntr 010: Modulo N Cntr + Pattern Store + Constant Generator 011: Modulo N Cntr + Constant Generator + Pattern Store 100: Constant Generator + Pattern Store + Modulo N Cntr 101: Constant Generator + Modulo N Cntr + Pattern Store 110: Reserved 111: Reserved 9:3 RWST 0Fh 2:0 RWST 000 14.8.2.3 SBFIBPATTBUF1: SB Intel IBIST Pattern Buffer 1 Register This register contains the pattern bits used in Intel IBIST operations. Only the least significant 24 bits are used. This user specified pattern goes out on to the link with the least-significant 12 bits as the first frame and the most significant 12 bits as the second frame. Device: NodeID Function: 6 Offset: 88h Bit 31:24 23:0 RV RWST Attr Default 00h 02ccfdh Reserved IBPATBUF: IBIST Pattern Buffer Pattern buffer storing the default and the user programmable pattern. Default: 02ccfdh Description 14.8.2.4 SBFIBTXMSK: SB Intel IBIST Transmitter Mask Register This register enables Intel IBIST operations for individual lanes. This mask only applies to transmitters and not receivers. Device: NodeID Function: 6 Offset: 8Ch Bit 31:10 9:0 Attr RV RWST Default 000000h 3FFh Reserved TXMASK: Selects which channels to enable for testing. Description Intel® 6400/6402 Advanced Memory Buffer Datasheet 233 Registers 14.8.2.5 SBFIBRXMSK: SB Intel IBIST Receiver Mask Register This register enables Intel IBIST operations for individual lanes. This mask only applies to receivers and not transmitters. Device: NodeID Function: 6 Offset: 90h Bit 31:10 9:0 Attr RV RWST Default 000000h 3FFh Reserved RXMASK: Selects which channels to enable for testing. Description 14.8.2.6 SBFIBTXSHFT: SB Intel IBIST Transmitter Inversion Shift Register Each bit in this register enables inverting the patterns that is driven on corresponding lanes. If AUTOINVSWPEN bit is set in port control register, the TXINVSHFT field is rotated left at the completion of each pattern buffer set. Device: NodeID Function: 6 Offset: 94h Bit 31:10 9:0 Attr RV RWST Default 000000h 3FFh Reserved TXINVSHFT: Transmitter Inversion Shift Register. Description 14.8.2.7 SBFIBRXSHFT: SB Intel IBIST Receiver Inversion Shift Register Each bit in this register enables inverting the patterns that is received on corresponding lanes. If AUTOINVSWPEN bit is set in port control register, the RXINVSHFT field is rotated left at the completion of each pattern buffer set. Device: NodeID Function: 6 Offset: 98h Bit 31:10 9:0 Attr RV RWST Default 000000h 3FFh Reserved RXINVSHFT: Receiver Inversion Shift Register. Description 14.8.2.8 SBFIBRXLNERR: SB Intel IBIST Receiver Lane Error Status This records the error status from each lane. Device: NodeID Function: 6 Offset: 9Ch Bit 31:10 9:0 Attr RV ROST Default 000000h 000h Reserved RXERRSTAT: Receiver Error Status Description 234 Intel® 6400/6402 Advanced Memory Buffer Datasheet Registers 14.8.2.9 SBFIBPATTBUF2: SB Intel IBIST Pattern Buffer 2 Register This optional register contains the pattern bits used in Intel IBIST operations. Only the least significant 24 bits are used. This user specified pattern goes out on to the link with the least-significant 12 bits as the first frame and the most significant 12 bits as the second frame. Device: NodeID Function: 6 Offset: A0h Bit 31:24 23:0 Attr RV RWST Default 00h fd3302h Reserved IBPATBUF2: IBIST Pattern Buffer 2 Pattern buffer storing the default and the user programmable pattern. Default: fd3302h Description 14.8.2.10 SBFIBPATT2EN: SB Intel IBIST Pattern Buffer 2 Enable This optional register specifies which lanes will carry the pattern specified in SBFIBPATTBUFF2. Device: NodeID Function: 6 Offset: A4h Bit 31:10 9:0 Attr RV RWST Default 00h 000h Reserved SBFIBPATT2EN: IBIST Pattern Buffer 2 enable Per lane enable for driving pattern buffer 2. Description 14.8.2.11 SBFIBINIT: SB Intel IBIST Initialization Register This register control southbound Intel IBIST Testing. Device: NodeID Function: 6 Offset: B0h Bit 31 30:21 20:13 Attr RV RWST RWST Default 0 0c8h 01h Reserved SBTS0CNT: Southbound TS0 Count Number of TS0 sequences to transmit. SBTS1CNT: Southbound TS1 Count Number of TS1 sequences to transmit. If TS1CNT[7] = 1; (TS1CNT >= 128) Intel IBIST will loop forever If TS1CNT[7] = 0; (TS1CNT = 128) Intel IBIST will loop forever If TS1CNT[7] = 0; (TS1CNT