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651

651

  • 厂商:

    INTEL

  • 封装:

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    651 - Intel Pentium 4 Processor - Intel Corporation

  • 数据手册
  • 价格&库存
651 数据手册
Intel® Pentium® 4 Processor 6x1∆ Sequence Datasheet – On 65 nm Process in the 775-land LGA Package supporting Hyper-Threading Technology and Intel® 64 architecture January 2007 Document Number: 310308-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Pentium® 4 Processor 6x1 sequence may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ∆ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. 1 Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting Hyper-Threading Technology and an HT Technology enabled chipset, BIOS, and an operating system. Performance will vary depending on the specific hardware and software you use. See for information including details on which processors support HT Technology. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Not all specified units of this processor support Enhanced HALT State and Enhanced Intel SpeedStep® Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information. Intel, Pentium, Intel NetBurst Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006 Intel Corporation. 2 Datasheet Contents 1 Introduction ....................................................................................................... 9 1.1 1.2 Terminology ..................................................................................................... 10 1.1.1 Processor Packaging Terminology ............................................................. 10 References ....................................................................................................... 11 Power and Ground Lands.................................................................................... 13 Decoupling Guidelines ........................................................................................ 13 2.2.1 VCC Decoupling ...................................................................................... 13 2.2.2 VTT Decoupling ...................................................................................... 13 2.2.3 FSB Decoupling...................................................................................... 14 Voltage Identification ......................................................................................... 14 Reserved, Unused, and TESTHI Signals ................................................................ 16 Voltage and Current Specification ........................................................................ 17 2.5.1 Absolute Maximum and Minimum Ratings .................................................. 17 2.5.2 DC Voltage and Current Specification ........................................................ 18 2.5.3 VCC Overshoot ....................................................................................... 21 2.5.4 Die Voltage Validation ............................................................................. 22 Signaling Specifications...................................................................................... 22 2.6.1 FSB Signal Groups.................................................................................. 23 2.6.2 GTL+ Asynchronous Signals..................................................................... 25 2.6.3 Processor DC Specifications ..................................................................... 25 2.6.3.1 GTL+ Front Side Bus Specifications ............................................. 28 Clock Specifications ........................................................................................... 29 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 29 2.7.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 30 2.7.3 Phase Lock Loop (PLL) and Filter .............................................................. 30 2.7.4 BCLK[1:0] Specifications ......................................................................... 32 Package Mechanical Drawing............................................................................... 33 Processor Component Keep-Out Zones ................................................................. 37 Package Loading Specifications ........................................................................... 37 Package Handling Guidelines............................................................................... 37 Package Insertion Specifications.......................................................................... 38 Processor Mass Specification ............................................................................... 38 Processor Materials............................................................................................ 38 Processor Markings............................................................................................ 38 Processor Land Coordinates ................................................................................ 39 Processor Land Assignments ............................................................................... 41 Alphabetical Signals Reference ............................................................................ 64 Processor Thermal Specifications ......................................................................... 75 5.1.1 Thermal Specifications ............................................................................ 75 5.1.2 Thermal Metrology ................................................................................. 79 Processor Thermal Features ................................................................................ 79 5.2.1 Thermal Monitor..................................................................................... 79 5.2.2 Thermal Monitor 2 .................................................................................. 80 5.2.3 On-Demand Mode .................................................................................. 81 5.2.4 PROCHOT# Signal .................................................................................. 82 2 Electrical Specifications ............................................................................... 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 Package Mechanical Specifications .................................................................. 33 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 5 Land Listing and Signal Descriptions ............................................................... 41 4.1 4.2 5.1 5.2 Thermal Specifications and Design Considerations ....................................... 75 Datasheet 3 5.2.5 5.2.6 5.2.7 THERMTRIP# Signal ................................................................................82 TCONTROL and Fan Speed Reduction ...........................................................82 Thermal Diode........................................................................................82 6 Features ..............................................................................................................85 6.1 6.2 Power-On Configuration Options ..........................................................................85 Clock Control and Low Power States .....................................................................85 6.2.1 Normal State .........................................................................................86 6.2.2 HALT and Enhanced HALT Powerdown States..............................................86 6.2.2.1 HALT Powerdown State ..............................................................86 6.2.2.2 Enhanced HALT Powerdown State................................................87 6.2.3 Stop Grant State ....................................................................................87 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant Snoop State...........................................................................88 6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................88 6.2.4.2 Enhanced HALT Snoop State .......................................................88 Mechanical Specifications ....................................................................................89 7.1.1 Boxed Processor Cooling Solution Dimensions.............................................89 7.1.2 Boxed Processor Fan Heatsink Weight .......................................................91 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly...............................................................................91 Electrical Requirements ......................................................................................91 7.2.1 Fan Heatsink Power Supply ......................................................................91 Thermal Specifications........................................................................................93 7.3.1 Boxed Processor Cooling Requirements......................................................93 Mechanical Specifications ....................................................................................96 8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions..................................96 8.1.2 Boxed Processor Thermal Module Assembly Weight .....................................98 8.1.3 Boxed Processor Support and Retention Module (SRM) ................................98 Electrical Requirements ......................................................................................99 8.2.1 Thermal Module Assembly Power Supply ....................................................99 Thermal Specifications...................................................................................... 101 8.3.1 Boxed Processor Cooling Requirements.................................................... 101 8.3.2 Variable Speed Fan ............................................................................... 102 Logic Analyzer Interface (LAI) ........................................................................... 105 9.1.1 Mechanical Considerations ..................................................................... 105 9.1.2 Electrical Considerations ........................................................................ 105 7 Boxed Processor Specifications ........................................................................89 7.1 7.2 7.3 8 Balanced Technology Extended (BTX) Boxed Processor Specifications ..... 95 8.1 8.2 8.3 9 Debug Tools Specifications .............................................................................. 105 9.1 4 Datasheet Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and for 775_VR_CONFIG_06 Processors...................................................................... 21 VCC Overshoot Example Waveform ............................................................................. 22 Phase Lock Loop (PLL) Filter Requirements .................................................................. 31 Processor Package Assembly Sketch ........................................................................... 33 Processor Package Drawing Sheet 1 of 3 ..................................................................... 34 Processor Package Drawing Sheet 2 of 3 ..................................................................... 35 Processor Package Drawing Sheet 3 of 3 ..................................................................... 36 Processor Top-Side Markings Example ........................................................................ 38 Processor Land Coordinates and Quadrants (Top View) ................................................. 39 land-out Diagram (Top View – Left Side) ..................................................................... 42 land-out Diagram (Top View – Right Side) ................................................................... 43 Thermal Profile for 775_VR_CONFIG_05A Processors .................................................... 77 Thermal Profile for 775_VR_CONFIG_06 Processors ...................................................... 78 Case Temperature (TC) Measurement Location ............................................................ 79 Thermal Monitor 2 Frequency and Voltage Ordering ...................................................... 81 Processor Low Power State Machine ........................................................................... 86 Mechanical Representation of the Boxed Processor ....................................................... 89 Space Requirements for the Boxed Processor (Side View; applies to all four side views) .... 90 Space Requirements for the Boxed Processor (Top View)............................................... 90 Space Requirements for the Boxed Processor (Overall View) .......................................... 91 Boxed Processor Fan Heatsink Power Cable Connector Description .................................. 92 Baseboard Power Header Placement Relative to Processor Socket ................................... 93 Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 1 View) .......................................................................................................... 94 Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 2 View) .......................................................................................................... 94 Mechanical Representation of the Boxed Processor with a Type I TMA ............................. 95 Mechanical Representation of the Boxed Processor with a Type II TMA ............................ 96 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes ....... 97 Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume ....... 98 Assembly Stack Including the Support and Retention Module ......................................... 99 Boxed Processor TMA Power Cable Connector Description ............................................ 100 Balanced Technology Extended (BTX) Mainboard Power Header Placement (Hatched Area) ...................................................................................................... 101 Boxed Processor TMA Set Points............................................................................... 102 Datasheet 5 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 References ..............................................................................................................11 Voltage Identification Definition ..................................................................................15 Absolute Maximum and Minimum Ratings ....................................................................17 Voltage and Current Specification ...............................................................................18 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and for 775_VR_CONFIG_06 Processors ......................................................................20 VCC Overshoot Specifications......................................................................................21 FSB Signal Groups ....................................................................................................23 Signal Characteristics................................................................................................24 Signal Reference Voltages .........................................................................................24 GTL+ Signal Group DC Specifications ..........................................................................25 GTL+ Asynchronous Signal Group DC Specifications ......................................................25 PWRGOOD and TAP Signal Group DC Specifications.......................................................26 VTTPWRGD DC Specifications .....................................................................................27 BSEL[2:0] and VID[5:0] DC Specifications ...................................................................27 BOOTSELECT DC Specifications ..................................................................................27 GTL+ Bus Voltage Definitions .....................................................................................28 Core Frequency to FSB Multiplier Configuration.............................................................29 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................30 Front Side Bus Differential BCLK Specifications .............................................................32 Processor Loading Specifications.................................................................................37 Package Handling Guidelines......................................................................................37 Processor Materials ...................................................................................................38 Alphabetical Land Assignments...................................................................................44 Numerical Land Assignment .......................................................................................54 Signal Description (Sheet 1 of 9) ................................................................................64 Processor Thermal Specifications for 775_VR_CONFIG_05A Processors ............................76 Processor Thermal Specifications for 775_VR_CONFIG_06 Processors ..............................76 Thermal Profile for 775_VR_CONFIG_05A Processors.....................................................77 Thermal Profile for 775_VR_CONFIG_06 Processors ......................................................78 Thermal “Diode” Parameters using Diode Model ............................................................83 Thermal “Diode” Parameters using Transistor Model ......................................................83 Thermal “Diode” ntrim and Diode_Correction_Offset.......................................................84 Thermal Diode Interface ............................................................................................84 Power-On Configuration Option Signals .......................................................................85 Fan Heatsink Power and Signal Specifications ...............................................................92 TMA Power and Signal Specifications ......................................................................... 100 TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors ............ 103 § 6 Datasheet Revision History Revision No. -001 -002 • • Initial release Description Date of Release January 2006 January 2007 Added Intel Pentium 4 processor 651, 641, and 631 at 65 W. § Datasheet 7 Intel® Pentium® 4 Processor 6x1 Sequence • Available at 3.6 GHz, 3.40 GHz, 3.20 GHz, and 3 GHz • Supports Hyper-Threading Technology1 (HT Technology) for all frequencies with 800 MHz front side bus (FSB) • Supports Intel® 64 architecture • Supports Execute Disable Bit capability • Binary compatible with applications running on previous members of the Intel microprocessor line • Intel NetBurst® microarchitecture • FSB frequency at 800 MHz • Hyper-Pipelined Technology • Advance Dynamic Execution • Very deep out-of-order execution • Enhanced branch prediction • Optimized for 32-bit applications running on advanced 32-bit operating systems • 16-KB Level 1 data cache • 2-MB Advanced Transfer Cache (on-die, fullspeed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC) • 144 Streaming SIMD Extensions 2 (SSE2) instructions • 13 Streaming SIMD Extensions 3 (SSE3) instructions • Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance • Power Management capabilities • System Management mode • Multiple low-power states • 8-way cache associativity provides improved cache hit rate on load/store operations • 775-land Package The Intel® Pentium® 4 processor family supporting Hyper-Threading Technology1 (HT Technology) delivers Intel's advanced, powerful processors for desktop PCs and entry-level workstations that are based on the Intel NetBurst® microarchitecture. The Pentium 4 processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments. Intel® 64 architecture enables the Intel® Pentium® processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. §§ 8 Datasheet Introduction 1 Introduction The Intel® Pentium® 4 processors 6x1 sequence are the first single-core desktop processors on the 65 nm process. The Pentium 4 processor uses Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket. Note: Note: In this document, unless otherwise specified, the Intel® Pentium® 4 processor 6x1 sequence refers to Intel Pentium 4 processors 661, 651, 641, 631. In this document the Intel® Pentium® 4 processor 6x1 sequence on 65 nm process in the 775-land package will be referred to as the “Pentium 4 processor,” or simply “the processor.” The Pentium 4 processor supports Intel® 64 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of Intel 64 architecture. Further details on the 64-bit extension architecture and programming model are in the Intel® Extended Memory 64 Technology Software Developer Guide at http://developer.intel.com/technology/64bitextensions/. The Pentium 4 processor supports Hyper-Threading Technology1. Hyper-Threading Technology allows a single, physical processor to function as two logical processors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architecture state with its own set of generalpurpose registers and control registers to provide increased system responsiveness in multitasking environments and headroom for next generation multithreaded applications. Intel recommends enabling Hyper-Threading Technology with Microsoft Windows* XP Professional or Windows* XP Home, and disabling Hyper-Threading Technology via the BIOS for all previous versions of Windows operating systems. For more information on Hyper-Threading Technology, see http://www.intel.com/products/ ht/hyperthreading_more.htm. Refer to Section 6.1 for Hyper-Threading Technology configuration details. The Pentium 4 processor’s Intel NetBurst® microarchitecture front side bus (FSB) uses a split-transaction, deferred reply protocol like previous Intel® Pentium® 4 processors. The Intel NetBurst microarchitecture FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8.5 GB/s. Intel will enable support components for the Pentium 4 processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. The Pentium 4 processor also include the Execute Disable Bit capability previously available in Intel® Itanium® processors. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel® 64 and IA-32 Architecture Software Developer’s Manual for more detailed information. Datasheet 9 Introduction The processor includes an address bus powerdown capability that removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor. Enhanced Intel® SpeedStep® technology allows trade-offs to be made between performance and power consumptions. This may lower average power consumption (in conjunction with OS support). 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level). Front Side Bus refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O. 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: • Intel® Pentium® 4 processor on 65 nm process in the 775-land package — Processor in the FC-LGA6 package with a 2 MB L2 cache. • Processor — For this document, the term processor is the generic form of the Intel® Pentium® 4 processor 6x1 sequence on 65 nm process in the 775-land package. • Keep-out zone — The area on or near the processor that system design can not utilize. • Intel® 945G/945GZ/945P/945PL Express chipsets — Chipset that supports DDR and DDR2 memory technology for the Pentium 4 processor. • Processor core — Processor core die with integrated L2 cache. • LGA775 socket — The Pentium 4 processor mates with the system board through a surface mount, 775-land, LGA socket. • Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. • Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket. • FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. • Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from 10 Datasheet Introduction packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. • Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied. 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document Intel® Pentium® 4 Processor 6x1 Sequence Specification Update Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical Design Guidelines NOTE: Refer to this document for 86 W processors. Intel® Core™2 Duo Desktop Processor E6000 Sequence and Intel® Pentium® 4 Processor 6x1 Sequence Thermal and Mechanical Design Guidelines NOTE: Refer To this document for 65 W processors. Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket LGA775 Socket Mechanical Design Guide Balanced Technology Extended (BTX) System Design Guide Intel® 64 and IA-32 Architecture Software Developer’s Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/design/ Pentium4/guides/302356.htm http://www.intel.com/design/ Pentium4/guides/302666.htm http://www.formfactors.org http://www.intel.com/design/ processor/designex/ 313685.htm Location http://www.intel.com/design/ pentium4/specupdt/ 310309.htm http://www.intel.com/design/ pentiumXE/designex/ 306830.htm §§ Datasheet 11 Introduction 12 Datasheet Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The Pentium 4 processor has 226 VCC (power), 24 VTT and 273 VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands. Twenty-four (24) signals are denoted as VTT, that provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 4. 2.2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4. Failure to do so can result in timing violations or reduced lifetime of the component. 2.2.1 VCC Decoupling VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for further information. 2.2.2 VTT Decoupling Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors. Datasheet 13 Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.3 Voltage Identification The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC lands (see Chapter 2.5.3 for VCC overshoot specifications). Refer to Table 14 for the DC specifications for these signals. A minimum voltage for each processor frequency is provided in Table 4. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 4. Refer to the Intel® Pentium® 4 Processor Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced HALT State). The processor uses 6 voltage identification signals, VID[5:0], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for further details. The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 4 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 5 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands. The VRM or VRD used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 4 and Table 5. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for further details. 14 Datasheet Electrical Specifications Table 2. Voltage Identification Definition VID 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 VR output off VR output off 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 VID5 VID4 VID3 VID2 VID1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 VID5 VID4 VID3 VID2 VID1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Datasheet 15 Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands. In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 7 for details on GTL+ signals that do not include on-die termination. Unused active high inputs, should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected; however, this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (RTT). For details, see Table 16. TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die termination. Inputs and utilized outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor that matches the nominal trace impedance. The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group: • TESTHI[1:0] • TESTHI[7:2] • TESTHI8 – cannot be grouped with other TESTHI signals • TESTHI9 – cannot be grouped with other TESTHI signals • TESTHI10 – cannot be grouped with other TESTHI signals • TESTHI11 – cannot be grouped with other TESTHI signals • TESTHI12 – cannot be grouped with other TESTHI signals • TESTHI13 – cannot be grouped with other TESTHI signals However, using boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used. 16 Datasheet Electrical Specifications 2.5 2.5.1 Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. Table 3. Absolute Maximum and Minimum Ratings Symbol VCC VTT TC TSTORAGE NOTES: Parameter Core voltage with respect to VSS FSB termination voltage with respect to VSS Processor case temperature Processor storage temperature Min –0.3 –0.3 See Chapter 5 –40 Max 1.55 1.55 See Chapter 5 85 Unit V V °C °C 3, 4, 5 Notes1,2 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the longterm reliability of the device. For functional operation, refer to the processor case temperature specifications. 4. This rating applies to the processor and does not include any tray or packaging. 5. Failure to adhere to this specification can affect the long term reliability of the processor. Datasheet 17 Electrical Specifications 2.5.2 Table 4. Symbol VID Range DC Voltage and Current Specification Voltage and Current Specification Parameter VID Processor number VCC for 775_VR_CONFIG_05A Refer to Table 5 and Figure 1 Min 1.200 Typ — Max 1.3375 Unit V Notes1, 3 2 VCC 661 651 641 631 Processor number 661 651 641 3.6 GHz 3.4 GHz 3.2 GHz 3 GHz ICC for 775_VR_CONFIG_05A 3.6 GHz 3.4 GHz 3.2 GHz 3 GHz ICC for 775_VR_CONFIG_06 3.4 GHz 3.2 GHz 3 GHz ICC Stop-Grant for 775_VR_CONFIG_05A 3.6 GHz 3.4 GHz 3.2 GHz 3 GHz ICC Stop-Grant for 775_VR_CONFIG_06 3.4 GHz 3.2 GHz 3 GHz ICC Enhanced Halt for 775_VR_CONFIG_05A 3.6 GHz 3.4 GHz 3.2 GHz 3 GHz ICC Enhanced Auto HALT for 775_VR_CONFIG_06 3.4 GHz 3.2 GHz 3 GHz V 4, 5, 6 — — 100 100 100 100 A 7 ICC 631 Processor number 651 641 631 Processor number 661 651 641 — — 65 65 65 — — 50 50 50 50 A 8,9,10,11 ISGNT 631 Processor number 651 641 631 Processor number 661 651 641 631 Processor number 651 641 631 40 40 40 40 40 40 40 A 8,10,11 IENHANCED_ AUTO_HALT 25 25 25 — 1.14 — 1.20 ICC 1.26 A V 12 13, 14 ITCC VTT ICC TCC active FSB termination voltage (DC + AC specifications) 18 Datasheet Electrical Specifications Table 4. Symbol Voltage and Current Specification Parameter DC Current that may be drawn from VTT_OUT_LEFT and VTT_OUT_RIGHT per pin Steady-state FSB termination current Power-up FSB termination current ICC for PLL lands ICC for I/O PLL land ICC for GTLREF Min Typ Max Unit Notes1, 2 VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT ITT_POWER-UP ICC_VCCA ICC_VCCIOPLL ICC_GTLREF NOTES: — — — — — — — — — — — — 580 3.5 4.5 35 26 200 mA A A mA mA µA 15, 16 15, 17 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. 3. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced HALT State). 4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information. 5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. 6. Refer to Table 5 and Figure 1 for the minimum, typical, and maximum VCC allowed for a given current. The 7. ICC_MAX is specified at VCC_MAX. 8. The current specified is also for AutoHALT State. 9. ICC Stop-Grant is specified at VCC_MAX. 10.ISGNT and IENHANCED_AUTO_HALT are specified at VCC_TYP and TC = 50 °C. 11.These parameters are based on design characterization and are not tested. 12.The maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the assertion of PROCHOT#) is the same as the maximum ICC for the processor. 13.VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land. 14.Baseboard bandwidth is limited to 20 MHz. 15. This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket to determine the total ITT drawn by the system. 16.This is a steady-state ITT current specification, which is applicable when both VTT and VCC are high. 17.This is a power-up peak current specification that is applicable when VTT is high and VCC is low. processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. Datasheet 19 Electrical Specifications Table 5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and for 775_VR_CONFIG_06 Processors Voltage Deviation from VID Setting (V)1,2,3,4 ICC (A) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Maximum Voltage 1.7 mΩ 0.000 -0.009 -0.017 -0.026 -0.034 -0.043 -0.051 -0.060 -0.068 -0.077 -0.085 -0.094 -0.102 -0.111 -0.119 -0.128 -0.133 -0.145 -0.153 -0.162 -0.170 Typical Voltage 1.75 mΩ -0.019 -0.028 -0.037 -0.045 -0.054 -0.063 -0.072 -0.080 -0.089 -0.098 -0.107 -0.115 -0.124 -0.133 -0.142 -0.150 -0.156 -0.168 -0.177 -0.185 -0.194 Minimum Voltage 1.8 mΩ -0.038 -0.047 -0.056 -0.065 -0.074 -0.083 -0.092 -0.101 -0.110 -0.119 -0.128 -0.137 -0.146 -0.155 -0.164 -0.173 -0.178 -0.191 -0.200 -0.209 -0.218 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.5.3. 2. This table is intended to aid in reading discrete points on Figure 1. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification for the Pentium 4 processor is required to ensure reliable processor operation. 20 Datasheet Electrical Specifications Figure 1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and for 775_VR_CONFIG_06 Processors Icc [A] 0 VID - 0.000 VID - 0.019 VID - 0.038 VID - 0.057 VID - 0.076 VID - 0.095 Vcc [V] VID - 0.114 Vcc Typical VID - 0.133 VID - 0.152 Vcc Minimum VID - 0.171 VID - 0.190 VID - 0.209 VID - 0.228 10 20 30 40 50 60 70 80 90 100 Vcc Maximum NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.5.3. 2. This loadline specification shows the deviation from the VID set point. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for socket loadline guidelines and VR implementation details. 2.5.3 VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands. Table 6. VCC Overshoot Specifications Symbol VOS_MAX TOS_MAX NOTES: Parameter Magnitude of VCC overshoot above VID Time duration of VCC overshoot above VID Min — — Max 0.050 25 Unit V µs Figure 2 2 Notes 1 1 1. Adherence to these specifications for the Pentium 4 processor is required to ensure reliable processor operation. Datasheet 21 Electrical Specifications Figure 2. VCC Overshoot Example Waveform Example Overshoot Waveform VID + 0.050 VOS Voltage (V) VID TOS Time TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.5.4 Die Voltage Validation Overshoot events on the processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. 2.6 Signaling Specifications Most processor front side bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families. The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 16 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals. 22 Datasheet Electrical Specifications 2.6.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals that are dependent on the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals that are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 7 identifies which signals are common clock, source synchronous, and asynchronous. Table 7. FSB Signal Groups (Sheet 1 of 2) Signal Group GTL+ Common Clock Input GTL+ Common Clock I/O Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR# Signals REQ[4:0]#, A[16:3]#3 GTL+ Source Synchronous I/O Synchronous to assoc. strobe A[35:17]# 3 Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# GTL+ Strobes GTL+ Asynchronous Input GTL+ Asynchronous Output GTL+ Asynchronous Input/Output TAP Input Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, STPCLK#, PWRGOOD FERR#/PBE#, IERR#, THERMTRIP# PROCHOT# Synchronous to TCK TCK, TDI, TMS, TRST# Datasheet 23 Electrical Specifications Table 7. FSB Signal Groups (Sheet 2 of 2) Signal Group TAP Output FSB Clock Type Synchronous to TCK Clock TDO BCLK[1:0], ITP_CLK[1:0]2 VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF[1:0], COMP[5:4,1:0], RESERVED, TESTHI[13:0], THERMDA, THERMDC, VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, BSEL[2:0], SKTOCC#, DBR#2, VTTPWRGD, BOOTSELECT, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], MSID[1:0], FCx, IMPSEL Signals1 Power/Other NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details. . Table 8. Signal Characteristics Signals with RTT A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOTSELECT1, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#, MSID[1:0]1, PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#, IMPSEL1 Open Drain Signals2 THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#, TDO, LL_ID[1:0], FCx 1. These signals have a 500–5000 Ω pull-up to VTT rather than on-die termination. 2. Signals that do not have RTT, nor are actively driven to their high-voltage level. Signals with No RTT A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0], COMP[5:4,1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0], THERMDA, THERMDC, THERMTRIP#, VID[5:0], VTTPWRGD, GTLREF[1:0], TCK, TDI, TMS, TRST#, VTT_SEL NOTES: Table 9. Signal Reference Voltages GTLREF BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY# VTT/2 BOOTSELECT, VTTPWRGD, A20M#, IGNNE#, INIT#, MSID[1:0], PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1, TMS1, TRST#1 1. These signals also have hysteresis added to the reference voltage. See Table 12 for more NOTES: information. 24 Datasheet Electrical Specifications 2.6.2 GTL+ Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the outputs are not actively driven high (during a logical 0-to-1 transition) by the processor. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order for the processor to recognize the proper signal state. See Section 2.6.3 for the DC specifications for the GTL+ Asynchronous signal groups. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 2.6.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. Table 10. GTL+ Signal Group DC Specifications Parameter Input Low Voltage Input High Voltage Output High Voltage Output Low Current Input Leakage Current Output Leakage Current Buffer On Resistance Min 0.0 GTLREF + (0.10 * VTT) 0.90*VTT N/A N/A N/A 6 Max GTLREF – (0.10 * VTT) VTT VTT VTT_MAX/ [(0.50*RTT_MIN)+(RON_MIN)] ± 200 ± 200 12 Unit V V V A µA µA W 6 Symbol VIL VIH VOH IOL ILI ILO RON 1. 2. 3. 4. 5. Notes1 2, 3 3, 4, 5 5, 6 7 Unless otherwise noted, all specifications in this table apply to all processor frequencies. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. The VTT referred to in these specifications is the instantaneous VTT. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality specifications. 6. Leakage to VSS with land held at VTT. 7. Leakage to VTT with land held at 300 mV. NOTES: Table 11. GTL+ Asynchronous Signal Group DC Specifications Parameter Input Low Voltage Input High Voltage Output High Voltage Output Low Current Min 0.0 VTT/2 + (0.10 * VTT) 0.90*VTT — Max VTT/2 – (0.10 * VTT) VTT VTT VTT/ [(0.50*RTT_MIN)+(RON_MIN)] Unit V V V A Notes1 2, 3 3, 4, 5, 6 5, 6, 7 8 Symbol VIL VIH VOH IOL Datasheet 25 Electrical Specifications Table 11. GTL+ Asynchronous Signal Group DC Specifications Parameter Input Leakage Current Output Leakage Current Buffer On Resistance Min N/A N/A 6 Max ± 200 ± 200 12 Unit µA µA W Notes1 9 Symbol ILI ILO RON 10 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals, VIH = GTLREF + (0.10 * VTT) and VIL= GTLREF – (0.10 * VTT). 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality specifications. 6. The VTT referred to in these specifications refers to instantaneous VTT. 7. All outputs are open drain. 8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 9. Leakage to VSS with land held at VTT. 10.Leakage to VTT with land held at 300 mV. . NOTES: Table 12. PWRGOOD and TAP Signal Group DC Specifications Parameter Input Hysteresis PWRGOOD Input lowto-high threshold voltage TAP Input low-to-high threshold voltage PWRGOOD Input highto-low threshold voltage TAP Input high-to-low threshold voltage VOH IOL ILI ILO RON Output High Voltage Output Low Current Input Leakage Current Output Leakage Current Buffer On Resistance Min 120 0.5 * (VTT + VHYS_MIN + 0.24) 0.5 * (VTT + VHYS_MIN) 0.4 * VTT 0.5 * (VTT – VHYS_MAX) N/A — — — 6 Max 396 0.5 * (VTT + VHYS_MAX + 0.24) 0.5 * (VTT + VHYS_MAX) 0.6 * VTT 0.5 * (VTT – VHYS_MIN) VTT 22.2 ± 200 ± 200 12 Unit mV V Notes1, 3 2 Symbol VHYS 4, 5 VT+ V 4 V 4 VT- V V mA µA µA W 4 4, 6 7 8 9 1. 2. 3. 4. 5. 6. 7. NOTES: The VTT referred to in these specifications refers to instantaneous VTT. 0.24 V is defined at 20% of nominal VTT of 1.2 V. The TAP signal group must meet the signal quality specifications. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 8. Leakage to Vss with land held at VTT. 9. Leakage to VTT with land held at 300 mV. VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT, for all TAP inputs. Unless otherwise noted, all specifications in this table apply to all processor frequencies. All outputs are open drain. 26 Datasheet Electrical Specifications Table 13. VTTPWRGD DC Specifications Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Min — 0.9 Typ — — Max 0.3 — Unit V V Table 14. BSEL[2:0] and VID[5:0] DC Specifications Symbol Parameter Max 120 120 2.4 200 VTT(max) Unit Ω Ω mA µA V 3 Notes1, 2 RON (BSEL) Buffer On Resistance RON (VID) IOL ILO VTOL Buffer On Resistance Max Land Current Output Leakage Current Voltage Tolerance 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to VSS with land held at 2.5 V. NOTES: Table 15. BOOTSELECT DC Specifications Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Min — 0.96 Typ — — Max 0.24 — Unit V V Notes 1 1 1. These parameters are not tested and are based on design simulations. NOTES: Datasheet 27 Electrical Specifications 2.6.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 16 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. Table 16. GTL+ Bus Voltage Definitions Symbol GTLREF_PU GTLREF_PD RPULLUP Parameter GTLREF pull up resistor GTLREF pull down resistor On die pull-up for BOOTSELECT signal 60 Ω Platform Termination Resistance 50 Ω Platform Termination Resistance 60 Ω Platform Termination COMP[1:0] COMP Resistance 50 Ω Platform Termination COMP Resistance 60 Ω Platform Termination COMP[5:4] COMP Resistance 50 Ω Platform Termination COMP Resistance Min 124 * 0.99 210 * 0.99 500 51 39 59.8 49.9 * 0.99 59.8 49.9 * 0.99 Typ 124 210 — 60 50 60.4 49.9 60.4 49.9 Max 124 * 1.01 210 * 1.01 5000 66 55 61 49.9 * 1.01 61 49.9 * 1.01 Units Ω Ω Ω Ω Ω Ω Ω Ω Ω Notes1 2 2 3 4 RTT 4 5 5 5 5 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each 3. These pull-ups are to VTT. 4. RTT is the on-die termination resistance measured at VTT/2 of the GTL+ output driver. The IMPSEL pin is used to select a 50 Ω or 60 Ω buffer and RTT value. 5. COMP resistance must be provided on the system board with 1% resistors. COMP[1:0] resistors are to VSS. COMP[5:4] resistors are to VTT. NOTES: GTLREF land). 28 Datasheet Electrical Specifications 2.7 2.7.1 Clock Specifications Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Pentium 4 processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 17 for the processor supported ratios. The processor uses a differential clocking implementation. For more information on processor clocking, contact your Intel representative. Table 17. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency 1/12 1/13 1/14 1/15 1/16 1/17 1/18 1/19 1/20 1/21 1/22 1/23 1/24 1/25 Core Frequency (200 MHz BCLK/ 800 MHz FSB) 2.40 GHz 2.60 GHz 2.80 GHz 3 GHz 3.20 GHz 3.40 GHz 3.60 GHz 3.80 GHz 4 GHz 4.20 GHz 4.40 GHz 4.60 GHz 4.80 GHz 5 GHz Notes1,2 1. Individual processors operate only at or below the rated frequency. 2. Listed frequencies are not necessarily committed production frequencies. NOTES: Datasheet 29 Electrical Specifications 2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 18 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Pentium 4 processor will operate at an 800 MHz FSB frequency (selected by a 200 MHz BCLK[1:0] frequency). For more information about these signals, refer to Section 4.2. Table 18. BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 L L L L H H H H BSEL1 L L H H H H L L BSEL0 L H H L L H H L FSB Frequency RESERVED RESERVED RESERVED 200 MHz RESERVED RESERVED RESERVED RESERVED 2.7.3 Phase Lock Loop (PLL) and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators for the Pentium 4 processor silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VTT. The AC low-pass requirements, with input at VTT are as follows: • < 0.2 dB gain in pass band • < 0.5 dB attenuation in pass band < 1 Hz • > 34 dB attenuation from 1 MHz to 66 MHz • > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 3. 30 Datasheet Electrical Specifications . Figure 3. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB –0.5 dB Forbidden Zone Forbidden Zone –28 dB –34 dB DC 1 Hz Passband fpeak 1 MHz 66 MHz High Frequency Band fcore Filter_Spec NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 4. fcore represents the maximum core frequency supported by the platform. Datasheet 31 Electrical Specifications 2.7.4 Table 19. BCLK[1:0] Specifications Front Side Bus Differential BCLK Specifications Parameter Input Low Voltage Input High Voltage Absolute Crossing Point Relative Crossing Point Range of Crossing Points Overshoot Undershoot Ringback Margin Threshold Region Min -0.150 0.660 0.250 0.250 + 0.5(VHavg – 0.700) N/A N/A -0.300 0.200 VCROSS – 0.100 Typ 0.000 0.700 N/A N/A N/A N/A N/A N/A N/A Max N/A 0.850 0.550 0.550 + 0.5(VHavg – 0.700) 0.140 VH + 0.3 N/A N/A VCROSS + 0.100 Unit V V V V V V V V V 6 7 8 9 2, 3 3, 4, 5 Symbol VL VH VCROSS(abs) VCROSS(rel) ∆VCROSS VOS VUS VRBM VTM Notes1 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 4. VHavg is the statistical average of the VH measured by the oscilloscope. 5. VHavg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix* oscilloscopes. 6. Overshoot is defined as the absolute value of the maximum voltage. 7. Undershoot is defined as the absolute value of the minimum voltage. 8. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. NOTES: §§ 32 Datasheet Package Mechanical Specifications 3 Package Mechanical Specifications The Pentium 4 processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 4 shows a sketch of the processor package components and how they are assembled together. Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket. The package components shown in Figure 4 include the following: • • • • • Integrated Heat Spreader (IHS) Thermal Interface Material (TIM) Processor core (die) Package substrate Capacitors Figure 4. Processor Package Assembly Sketch Core (die) IHS Substrate TIM Capacitors LGA775 Socket System Board NOTE: 1. Socket and motherboard are included for reference and are not part of processor package. 3.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 5 and Figure 6. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: • • • • • • • Package reference with tolerances (total height, length, width, etc.) IHS parallelism and tilt Land dimensions Top-side and back-side component keep-out dimensions Reference datums All drawing dimensions are in mm [in]. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines (see Section 1.2). Datasheet 33 Package Mechanical Specifications Figure 5. Processor Package Drawing Sheet 1 of 3 34 Datasheet Package Mechanical Specifications Figure 6. Processor Package Drawing Sheet 2 of 3 Datasheet 35 Package Mechanical Specifications Figure 7. Processor Package Drawing Sheet 3 of 3 36 Datasheet Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 5 and Figure 6 for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in. 3.3 Package Loading Specifications Table 20 provides dynamic and static load specifications for the processor package. These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions. . Table 20. Processor Loading Specifications Parameter Static Dynamic Minimum 80 N [17 lbf] — Maximum 311 N [70 lbf] 756 N [170 lbf] Notes 1, 2, 3 1, 3, 4 NOTES: 1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS. 2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement. 3.4 Package Handling Guidelines Table 21 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 21. Package Handling Guidelines Parameter Shear Tensile Torque Maximum Recommended 311 N [70 lbf] 111 N [25 lbf] 3.95 N-m [35 lbf-in] Notes 1, 2 2, 3 2, 4 NOTES: 1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface. 2. These guidelines are based on limited testing for design characterization. 3. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface. 4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface. Datasheet 37 Package Mechanical Specifications 3.5 Package Insertion Specifications The Pentium 4 processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the Pentium 4 processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.7 Table 22. Processor Materials Table 22 lists some of the package components and associated materials. Processor Materials Component Integrated Heat Spreader (IHS) Substrate Substrate Lands Material Nickel Plated Copper Fiber Reinforced Resin Gold Plated Copper 3.8 Processor Markings Figure 8 shows the topside markings on the processor. This diagram is to aid in the identification of the Pentium 4 processor. Figure 8. Processor Top-Side Markings Example Brand Processor Number/ S-Spec/ Country of Assy Frequency/L2 Cache/Bus/ 775_VR_CONFIG_05x FPO INTEL m © ‘05 XXXXXXXX 641 SLxxx [COO] 3.20GHZ/2M/800/05A [FPO] Unique Unit Identifier ATPO Serial # ATPO S/N 2-D Matrix Mark 38 Datasheet Package Mechanical Specifications 3.9 . Processor Land Coordinates Figure 9 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 9. Processor Land Coordinates and Quadrants (Top View) VCC / VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W Socket 775 Quadrants Top View V U T R P N M L K J H G F E D C B A Address/ Common Clock/ Async 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VTT / Clocks Data §§ Datasheet 39 Package Mechanical Specifications 40 Datasheet Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 10 and Figure 11. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 is a listing of all processor lands ordered alphabetically by land (signal) name. Table 24 is also a listing of all processor lands; the ordering is by land number. Datasheet 41 Land Listing and Signal Descriptions Figure 10.land-out Diagram (Top View – Left Side) 30 AN VCC VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS 29 VCC VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS 28 VSS VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS 27 VSS VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS 26 VCC VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VSS 25 VCC VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VSS 24 VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS 23 VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VSS 22 VCC VCC VCC VCC VCC VCC VCC VCC VCC 21 VCC VCC VCC VCC VCC VCC VCC VCC VCC 20 VSS VSS VSS VSS VSS VSS VSS VSS VSS 19 VCC VCC VCC VCC VCC VCC VCC VCC VCC 18 VCC VCC VCC VCC VCC VCC VCC VCC VCC 17 VSS VSS VSS VSS VSS VSS VSS VSS VSS 16 VSS VSS VSS VSS VSS VSS VSS VSS VSS 15 VCC VCC VCC VCC VCC VCC VCC VCC VCC AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VCC VCC VCC DP3# DP0# VCC H BSEL1 BSEL2 FC15 BSEL0 RSVD VSS VSS BCLK1 VSS VSS VSS VSS VSS VSS D47# VSS D45# D46# VSS D63# D62# 22 VSS D44# D43# D42# VSS D58# D59# VSS 21 VSS VSS VSS D35# D38# D39# VSS D54# D57# VSS 18 VSS D36# D37# VSS D49# DSTBP3# VSS D56# 17 DP2# D32# VSS D34# RSVD VSS D55# DSTBN3# 16 DP1# D31# D30# D33# VSS D51# D53# VSS 15 G F E D C B A TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# RSVD RSVD FC9 VCCIO PLL VSSA VCCA 23 DSTBN2# DSTBP2# D41# VSS D48# DBI3# VSS RSVD 20 VSS D40# DBI2# VSS D60# D61# 19 BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 VSS VTT VTT VTT VTT 28 VSS VTT VTT VTT VTT 27 VSS VTT VTT VTT VTT 26 VSS VTT VTT VTT VTT 25 FC10 VSS VSS VSS VSS 24 VTT VTT VTT VTT 30 VTT VTT VTT VTT 29 42 Datasheet Land Listing and Signal Descriptions Figure 11.land-out Diagram (Top View – Right Side) 14 VCC VCC VCC VCC VCC VCC VCC VCC VCC 13 VSS VSS VSS VSS VSS VSS VSS VSS VSS 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC 11 VCC VCC VCC VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS 9 VCC VCC VCC VCC VCC VCC VCC VCC VCC 8 VCC VCC VCC VCC VCC VCC VCC VCC SKTOCC# VCC VCC VCC VCC 7 FC16 FC12 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 6 5 4 VSS_ SENSE VSS VID5 VID4 VSS A32# A30# A28# RSVD VSS RSVD A26# A21# 3 VCC_ SENSE VID2 VSS ITP_CLK0 ITP_CLK1 VSS BPM5# VSS FC18 BINIT# VSS MCERR# VSS 2 VSS VID0 1 VSS VSS AN AM AL AK AJ AH AG AF AE AD AC AB AA VSS_MB_ VCC_MB_ REGULATION REGULATION VTTPWRGD VID3 FC8 A35# VSS A29# VSS RSVD A22# VSS A17# VSS FC11 VID1 VSS A34# A33# A31# A27# VSS ADSTB1# A25# A24# A23# PROCHOT# THERMDA VSS BPM0# RSVD BPM3# BPM4# VSS BPM2# DBR# IERR# LL_ID1 THERMDC BPM1# VSS TRST# TDO TCK TDI TMS VSS VTT_OUT_ RIGHT BOOT SELECT MSID0 MSID1 VSS COMP1 FC2 TESTHI11 PWRGOOD VSS LINT1 LINT0 VTT_OUT_ LEFT GTLREF0 VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A19# A18# VSS A10# VSS ADSTB0# A4# VSS REQ2# VSS REQ3# REQ4# VSS A16# A14# A12# A9# VSS RSVD RSVD A5# A3# VSS REQ1# A20# VSS A15# A13# A11# A8# VSS RSVD A7# A6# REQ0# VSS FC17 TESTHI1 VSS AP1# VSS FERR#/ PBE# INIT# VSS STPCLK# VSS A20M# FC22 VSS TESTHI12 LL_ID0 AP0# COMP5 VSS SMI# IGNNE# THERMTRIP# TESTHI13 VSS COMP4 Y W V U T R P N M L K J H VSS D29# D28# VSS RSVD D52# VSS D50# 14 VSS D27# VSS D26# D25# VSS FC19 COMP0 13 VSS DSTBN1# D24# DSTBP1# VSS D14# D13# VSS 12 VSS DBI1# D23# VSS D15# D11# VSS D9# 11 VSS RSVD VSS D21# D22# VSS D10# D8# 10 VSS D16# D18# D19# VSS RSVD DSTBP0# VSS 9 VSS BPRI# D17# VSS D12# DSTBN0# VSS DBI0# 8 VSS DEFER# VSS RSVD D20# VSS D6# D7# 7 VSS RSVD IMPSEL RSVD VSS D3# D5# VSS 6 TESTHI10 FC7 RS1# FC20 VSS D1# VSS D4# 5 RSP# TESTHI9 VSS HITM# HIT# VSS D0# D2# 4 VSS TESTHI8 BR0# TRDY# VSS LOCK# RS0# RS2# 3 GTLREF1 FC1 FC5 VSS ADS# BNR# DBSY# VSS 2 G F E RSVD DRDY# VSS D C B A 1 Datasheet 43 Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A3# A30# A31# A32# A33# A34# A35# A4# A5# A6# A7# A8# A9# ADS# ADSTB0# ADSTB1# AP0# AP1# Land Signal Buffer # Type U6 T4 U5 U4 V5 V4 W5 AB6 W6 Y6 Y4 K3 AA4 AD6 AA5 AB5 AC5 AB4 AF5 AF4 AG6 L5 AG4 AG5 AH4 AH5 AJ5 AJ6 P6 M5 L4 M4 R4 T5 D2 R6 AD5 U2 U3 Direction Table 23.Alphabetical Land Assignments Land Name BCLK0 BCLK1 BINIT# BNR# BOOTSELECT BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPRI# BR0# BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP4 COMP5 D0# D1# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D2# D20# D21# D22# D23# D24# D25# Land Signal Buffer # Type F28 G28 Clock Clock Direction Input Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Asynch GTL+ Input AD3 Common Clock Input/Output C2 Y1 AJ2 AJ1 Common Clock Input/Output Power/Other Input Common Clock Input/Output Common Clock Input/Output AD2 Common Clock Input/Output AG2 Common Clock Input/Output AF2 Common Clock Input/Output AG3 Common Clock Input/Output G8 F3 G29 H30 G30 A13 T1 J2 T2 B4 C5 B10 C11 D8 B12 C12 D11 G9 F8 F9 E9 A4 D7 E10 D10 F11 F12 D13 Common Clock Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Common Clock Input/Output Source Synch Input/Output Source Synch Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Input Input Input Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output 44 Datasheet Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name D26# D27# D28# D29# D3# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D4# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D5# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D6# D60# Land Signal Buffer # Type E13 G13 F14 G14 C6 F15 G15 G16 E15 E16 G18 G17 F17 F18 E18 A5 E19 F20 E21 F21 G21 E22 D22 G22 D20 D17 B6 A14 C15 C14 B15 C18 B16 A17 B18 C21 B21 B7 B19 Direction Table 23.Alphabetical Land Assignments Land Name D61# D62# D63# D7# D8# D9# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# DEFER# DP0# DP1# DP2# DP3# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FC1 FC11 FC12 FC15 FC16 FC2 FC5 FC7 FC8 FC10 FC17 FC22 FC19 Land Signal Buffer # Type A19 A22 B22 A7 A10 A11 A8 G11 D19 C20 AC2 B2 G7 J16 Direction Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Output Common Clock Input/Output Common Clock Input Common Clock Input/Output H15 Common Clock Input/Output H16 Common Clock Input/Output J17 C1 C8 G12 G20 A16 B9 E12 G19 C17 G2 AM5 AM7 H29 AN7 R1 F2 G5 AK6 E24 Y3 J3 B13 Common Clock Input/Output Common Clock Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Output Output Output Input Input Output Output Output Output Output Output Datasheet 45 Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name FC18 FC20 FC9 FERR#/PBE# GTLREF0 GTLREF1 HIT# HITM# IERR# IGNNE# IMPSEL INIT# ITP_CLK0 ITP_CLK1 LINT0 LINT1 LL_ID0 LL_ID1 LOCK# MCERR# MSID0 MSID1 PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Land Signal Buffer # Type AE3 E5 D23 R3 H1 H2 D4 E4 AB2 N2 F6 P3 AK3 AJ3 K1 L1 V2 AA2 C3 Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Direction Output Output Output Output Input Input Table 23.Alphabetical Land Assignments Land Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET# RS0# RS1# RS2# RSP# SKTOCC# SMI# STPCLK# TCK TDI TDO TESTHI0 TESTHI1 TESTHI10 TESTHI11 TESTHI12 TESTHI13 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8 TESTHI9 THERMDA THERMDC THERMTRIP# TMS TRDY# Land Signal Buffer # Type E6 E7 F23 F29 G10 G6 N4 N5 P5 G23 Common Clock B3 F5 A3 H4 AE8 P2 M3 AE1 AD1 AF1 F26 W3 H5 P1 W2 L2 F25 G25 G27 G26 G24 F24 G3 G4 AL1 AK1 M2 AC1 E3 Common Clock Common Clock Common Clock Common Clock Power/Other Asynch GTL+ Asynch GTL+ TAP TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ TAP Common Clock Output Input Input Input Input Input Input Input Output Input Input Input Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Direction Common Clock Input/Output Common Clock Input/Output Asynch GTL+ Asynch GTL+ Power/Other Asynch GTL+ TAP TAP Asynch GTL+ Asynch GTL+ Power/Other Power/Other Output Input Input Input Input Input Input Input Output Output Common Clock Input/Output AB3 Common Clock Input/Output W1 V1 AL2 N1 K4 J5 M6 K6 J6 A20 AC4 AE4 AE6 AH2 C9 D1 D14 D16 E23 Power/Other Power/Other Output Output Asynch GTL+ Input/Output Power/Other Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output 46 Datasheet Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Signal Buffer # Type AG1 AA8 AB8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD8 AE11 AE12 AE14 AE15 AE18 AE19 AE21 AE22 AE23 AE9 AF11 AF12 AF14 AF15 AF18 AF19 AF21 AF22 TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Input Table 23.Alphabetical Land Assignments Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Signal Buffer # Type AF8 AF9 AG11 AG12 AG14 AG15 AG18 AG19 AG21 AG22 AG25 AG26 AG27 AG28 AG29 AG30 AG8 AG9 AH11 AH12 AH14 AH15 AH18 AH19 AH21 AH22 AH25 AH26 AH27 AH28 AH29 AH30 AH8 AH9 AJ11 AJ12 AJ14 AJ15 AJ18 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 47 Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Signal Buffer # Type AJ19 AJ21 AJ22 AJ25 AJ26 AJ8 AJ9 AK11 AK12 AK14 AK15 AK18 AK19 AK21 AK22 AK25 AK26 AK8 AK9 AL11 AL12 AL14 AL15 AL18 AL19 AL21 AL22 AL25 AL26 AL29 AL30 AL8 AL9 AM11 AM12 AM14 AM15 AM18 AM19 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 23.Alphabetical Land Assignments Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Signal Buffer # Type AM21 AM22 AM25 AM26 AM29 AM30 AM8 AM9 AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 AN25 AN26 AN29 AN30 AN8 AN9 J10 J11 J12 J13 J14 J15 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 48 Datasheet Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Signal Buffer # Type J29 J30 J8 J9 K23 K24 K25 K26 K27 K28 K29 K30 K8 L8 M23 M24 M25 M26 M27 M28 M29 M30 M8 N23 N24 N25 N26 N27 N28 N29 N30 N8 P8 R8 T23 T24 T25 T26 T27 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 23.Alphabetical Land Assignments Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_MB_ REGULATION VCC_SENSE VCCA VCCIOPLL VID0 VID1 VID2 Land Signal Buffer # Type T28 T29 T30 T8 U23 U24 U25 U26 U27 U28 U29 U30 U8 V8 W23 W24 W25 W26 W27 W28 W29 W30 W8 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y8 AN5 AN3 A23 C23 AM2 AL5 AM3 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Direction Datasheet 49 Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name VID3 VID4 VID5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type AL6 AK4 AL4 B1 B11 B14 B17 B20 B24 B5 B8 A12 A15 A18 A2 A21 A24 A6 A9 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA6 AA7 AB1 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output Output Table 23.Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type AB7 AC3 AC6 AC7 AD4 AD7 AE10 AE13 AE16 AE17 AE2 AE20 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE5 AE7 AF10 AF13 AF16 AF17 AF20 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF6 AF7 AG10 AG13 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 50 Datasheet Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type AG16 AG17 AG20 AG23 AG24 AG7 AH1 AH10 AH13 AH16 AH17 AH20 AH23 AH24 AH3 AH6 AH7 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23 AJ24 AJ27 AJ28 AJ29 AJ30 AJ4 AJ7 AK10 AK13 AK16 AK17 AK2 AK20 AK23 AK24 AK27 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 23.Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type AK28 AK29 AK30 AK5 AK7 AL10 AL13 AL16 AL17 AL20 AL23 AL24 AL27 AL28 AL3 AL7 AM1 AM10 AM13 AM16 AM17 AM20 AM23 AM24 AM27 AM28 AM4 AN1 AN10 AN13 AN16 AN17 AN2 AN20 AN23 AN24 AN27 AN28 C10 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 51 Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type C13 C16 C19 C22 C24 C4 C7 D12 D15 D18 D21 D24 D3 D5 D6 D9 E11 E14 E17 E2 E20 E25 E26 E27 E28 E29 E8 F10 F13 F16 F19 F22 F4 F7 G1 H10 H11 H12 H13 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 23.Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type H14 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H3 H6 H7 H8 H9 J4 J7 K2 K5 K7 L23 L24 L25 L26 L27 L28 L29 L3 L30 L6 L7 M1 M7 N3 N6 N7 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 52 Datasheet Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type P23 P24 P25 P26 P27 P28 P29 P30 P4 P7 R2 R23 R24 R25 R26 R27 R28 R29 R30 R5 R7 T3 T6 T7 U1 U7 V23 V24 V25 V26 V27 V28 V29 V3 V30 V6 V7 W4 W7 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 23.Alphabetical Land Assignments Land Name VSS VSS VSS VSS_MB_ REGULATION VSS_SENSE VSSA VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT_OUT_LEFT VTT_OUT_RIGHT VTT_SEL VTTPWRGD Land Signal Buffer # Type Y2 Y5 Y7 AN6 AN4 B23 B25 B26 B27 B28 B29 B30 A25 A26 A27 A28 A29 A30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30 J1 AA1 F27 AM6 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Input Output Output Direction Datasheet 53 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A3 A30 A4 A5 A6 A7 A8 A9 AA1 AA2 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 Land Name D08# D09# VSS COMP0 D50# VSS DSTBN3# D56# VSS D61# VSS RESERVED VSS D62# VCCA VSS VTT VTT VTT VTT VTT RS2# VTT D02# D04# VSS D07# DBI0# VSS VTT_OUT_RIGHT LL_ID1 VSS VSS VSS VSS VSS VSS VSS VSS VSS Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Input Signal Buffer Type Direction Table 24.Numerical Land Assignment Land # AA4 AA5 AA6 Land Name A21# A23# VSS VSS VCC VSS IERR# VSS VSS VSS VSS VSS VSS VSS MCERR# VSS A26# A24# A17# VSS VCC TMS DBR# VCC VCC VCC VCC VCC VCC VCC VSS VCC RESERVED A25# VSS VSS VCC TDI BPM2# VCC Source Synch Input/Output Power/Other Power/Other Power/Other TAP Input Signal Buffer Type Direction Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Input Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Output AA7 AA8 AB1 AB2 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB3 AB30 AB4 AB5 AB6 AB7 AB8 AC1 AC2 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC3 AC30 AC4 AC5 AC6 AC7 AC8 AD1 AD2 AD23 Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Common Clock Input/Output Power/Other 54 Datasheet Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # AD24 AD25 AD26 AD27 AD28 AD29 AD3 AD30 AD4 AD5 AD6 AD7 AD8 AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE3 AE30 AE4 AE5 AE6 Land Name VCC VCC VCC VCC VCC VCC BINIT# VCC VSS ADSTB1# A22# VSS VCC TCK VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VCC VSS VSS VSS VSS VSS VSS FC18 VSS RESERVED VSS RESERVED Power/Other Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Direction Table 24.Numerical Land Assignment Land # AE7 AE8 AE9 AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF4 AF5 AF6 AF7 AF8 AF9 AG1 AG10 AG11 AG12 AG13 AG14 AG15 Land Name VSS SKTOCC# VCC TDO VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC BPM4# VSS VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS A28# A27# VSS VSS VCC VCC TRST# VSS VCC VCC VSS VCC VCC Signal Buffer Type Power/Other Power/Other Power/Other TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Output Direction Datasheet 55 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # AG16 AG17 AG18 AG19 AG2 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG3 AG30 AG4 AG5 AG6 AG7 AG8 AG9 AH1 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH2 AH20 AH21 AH22 AH23 AH24 Land Name VSS VSS VCC VCC BPM3# VSS VCC VCC VSS VSS VCC VCC VCC VCC VCC BPM5# VCC A30# A31# A29# VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC RESERVED VSS VCC VCC VSS VSS Power/Other Power/Other Power/Other Power/Other Power/Other Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 24.Numerical Land Assignment Land # AH25 AH26 AH27 AH28 AH29 AH3 AH30 AH4 AH5 AH6 AH7 AH8 AH9 AJ1 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ2 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ3 AJ30 AJ4 AJ5 AJ6 Land Name VCC VCC VCC VCC VCC VSS VCC A32# A33# VSS VSS VCC VCC BPM1# VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC BPM0# VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS ITP_CLK1 VSS VSS A34# A35# Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Input Direction 56 Datasheet Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # AJ7 AJ8 AJ9 AK1 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK2 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK3 AK30 AK4 AK5 AK6 AK7 AK8 AK9 AL1 AL10 AL11 AL12 AL13 AL14 AL15 Land Name VSS VCC VCC THERMDC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS ITP_CLK0 VSS VID4 VSS FC8 VSS VCC VCC THERMDA VSS VCC VCC VSS VCC VCC Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Power/Other Output Input Direction Table 24.Numerical Land Assignment Land # AL16 AL17 AL18 AL19 AL2 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL3 AL30 AL4 AL5 AL6 AL7 AL8 AL9 AM1 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM2 AM20 AM21 AM22 AM23 AM24 Land Name VSS VSS VCC VCC PROCHOT# VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VSS VCC VID5 VID1 VID3 VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VID0 VSS VCC VCC VSS VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Direction Datasheet 57 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # AM25 AM26 AM27 AM28 AM29 AM3 AM30 AM4 AM5 AM6 AM7 AM8 AM9 AN1 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN2 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN3 AN30 AN4 AN5 Land Name VCC VCC VSS VSS VCC VID2 VCC VSS FC11 VTTPWRGD FC12 VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC_SENSE VCC VSS_SENSE VCC_MB_ REGULATION Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Input Output Output Direction Table 24.Numerical Land Assignment Land # AN6 AN7 AN8 AN9 B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B3 B30 B4 B5 B6 B7 B8 B9 C1 C10 C11 C12 C13 C14 Land Name VSS_MB_ REGULATION FC16 VCC VCC VSS D10# VSS D13# FC19 VSS D53# D55# VSS D57# D60# DBSY# VSS D59# D63# VSSA VSS VTT VTT VTT VTT VTT RS0# VTT D00# VSS D05# D06# VSS DSTBP0# DRDY# VSS D11# D14# VSS D52# Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Input Output Direction Output Output 58 Datasheet Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # C15 C16 C17 C18 C19 C2 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C3 C30 C4 C5 C6 C7 C8 C9 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 Land Name D51# VSS DSTBP3# D54# VSS BNR# DBI3# D58# VSS VCCIOPLL VSS VTT VTT VTT VTT VTT LOCK# VTT VSS D01# D03# VSS DSTBN0# RESERVED RESERVED D22# D15# VSS D25# RESERVED VSS RESERVED D49# VSS DBI2# ADS# D48# VSS D46# FC9 Source Synch Input/Output Power/Other Source Synch Input/Output Common Clock Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Signal Buffer Type Direction Table 24.Numerical Land Assignment Land # D24 D25 D26 D27 D28 D29 D3 D30 D4 D5 D6 D7 D8 D9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E2 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E3 E4 E5 E6 E7 Land Name VSS VTT VTT VTT VTT VTT VSS VTT HIT# VSS VSS D20# D12# VSS D21# VSS DSTBP1# D26# VSS D33# D34# VSS D39# D40# VSS VSS D42# D45# RESERVED FC10 VSS VSS VSS VSS VSS TRDY# HITM# FC20 RESERVED RESERVED Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input Output Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Direction Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Common Clock Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Common Clock Input/Output Power/Other Output Datasheet 59 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # E8 E9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F2 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F3 F4 F5 F6 F7 F8 F9 G1 G10 G11 G12 G13 G14 G15 G16 G17 G18 Land Name VSS D19# VSS D23# D24# VSS D28# D30# VSS D37# D38# VSS FC5 D41# D43# VSS RESERVED TESTHI7 TESTHI2 TESTHI0 VTT_SEL BCLK0 RESERVED BR0# VSS RS1# IMPSEL VSS D17# D18# VSS RESERVED DBI1# DSTBN1# D27# D29# D31# D32# D36# D35# Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Common Clock Input/Output Power/Other Common Clock Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Input Input Power/Other Power/Other Power/Other Power/Other Clock Input Input Input Output Input Signal Buffer Type Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Common Clock Input Direction Table 24.Numerical Land Assignment Land # G19 G2 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G3 G30 G4 G5 G6 G7 G8 G9 H1 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H2 H20 H21 H22 H23 H24 H25 H26 H27 Land Name DSTBP2# FC1 DSTBN2# D44# D47# RESET# TESTHI6 TESTHI3 TESTHI5 TESTHI4 BCLK1 BSEL0 TESTHI8 BSEL2 TESTHI9 FC7 RESERVED DEFER# BPRI# D16# GTLREF0 VSS VSS VSS VSS VSS DP1# DP2# VSS VSS VSS GTLREF1 VSS VSS VSS VSS VSS VSS VSS VSS Common Clock Common Clock Input Input Signal Buffer Type Direction Source Synch Input/Output Power/Other Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Common Clock Power/Other Power/Other Power/Other Power/Other Clock Power/Other Power/Other Power/Other Power/Other Source Synch Input Input Input Input Input Input Output Input Output Input Output Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input 60 Datasheet Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # H28 H29 H3 H30 H4 H5 H6 H7 H8 H9 J1 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J2 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J3 J30 J4 J5 J6 J7 J8 J9 Land Name VSS FC15 VSS BSEL1 RSP# TESTHI10 VSS VSS VSS VSS VTT_OUT_LEFT VCC VCC VCC VCC VCC VCC DP0# DP3# VCC VCC COMP4 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC FC22 VCC VSS REQ1# REQ4# VSS VCC VCC Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Output Input Output Output Input Input Output Direction Table 24.Numerical Land Assignment Land # K1 K2 K23 K24 K25 K26 K27 K28 K29 K3 K30 K4 K5 K6 K7 K8 L1 L2 L23 L24 L25 L26 L27 L28 L29 L3 L30 L4 L5 L6 L7 L8 M1 M2 M23 M24 M25 M26 M27 M28 Land Name LINT0 VSS VCC VCC VCC VCC VCC VCC VCC A20M# VCC REQ0# VSS REQ3# VSS VCC LINT1 TESTHI13 VSS VSS VSS VSS VSS VSS VSS VSS VSS A06# A03# VSS VSS VCC VSS THERMTRIP# VCC VCC VCC VCC VCC VCC Signal Buffer Type Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Asynch GTL+ Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Input Input Direction Input Datasheet 61 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # M29 M3 M30 M4 M5 M6 M7 M8 N1 N2 N23 N24 N25 N26 N27 N28 N29 N3 N30 N4 N5 N6 N7 N8 P1 P2 P23 P24 P25 P26 P27 P28 P29 P3 P30 P4 P5 P6 P7 P8 Land Name VCC STPCLK# VCC A07# A05# REQ2# VSS VCC PWRGOOD IGNNE# VCC VCC VCC VCC VCC VCC VCC VSS VCC RESERVED RESERVED VSS VSS VCC TESTHI11 SMI# VSS VSS VSS VSS VSS VSS VSS INIT# VSS VSS RESERVED A04# VSS VCC Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Input Input Input Signal Buffer Type Power/Other Asynch GTL+ Power/Other Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Direction Table 24.Numerical Land Assignment Land # R1 R2 R23 R24 R25 R26 R27 R28 R29 R3 R30 R4 R5 R6 R7 R8 T1 T2 T23 T24 T25 T26 T27 T28 T29 T3 T30 T4 T5 T6 T7 T8 U1 U2 U23 U24 U25 U26 U27 U28 Land Name FC2 VSS VSS VSS VSS VSS VSS VSS VSS FERR#/PBE# VSS A08# VSS ADSTB0# VSS VCC COMP1 COMP5 VCC VCC VCC VCC VCC VCC VCC VSS VCC A11# A09# VSS VSS VCC VSS AP0# VCC VCC VCC VCC VCC VCC Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Output Direction Input 62 Datasheet Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # U29 U3 U30 U4 U5 U6 U7 U8 V1 V2 V23 V24 V25 V26 V27 V28 V29 V3 V30 V4 V5 V6 V7 V8 W1 W2 W23 W24 W25 W26 W27 W28 W29 W3 W30 W4 W5 Land Name VCC AP1# VCC A13# A12# A10# VSS VCC MSID1 LL_ID0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A15# A14# VSS VSS VCC MSID0 TESTHI12 VCC VCC VCC VCC VCC VCC VCC TESTHI1 VCC VSS A16# Signal Buffer Type Power/Other Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Input Output Input Output Output Direction Table 24.Numerical Land Assignment Land # W6 W7 W8 Y1 Y2 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y3 Y30 Y4 Y5 Y6 Y7 Y8 Land Name A18# VSS VCC BOOTSELECT VSS VCC VCC VCC VCC VCC VCC VCC FC17 VCC A20# VSS A19# VSS VCC Signal Buffer Type Direction Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Input Datasheet 63 Land Listing and Signal Descriptions 4.2 Table 25. Alphabetical Signals Reference Signal Description (Sheet 1 of 9) Name Type Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See Section 6.1 for more details. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. Input/ Output ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB0# ADSTB1# A[35:3]# Input/ Output A20M# Input ADS# AP[1:0]# Input/ Output AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins/lands of all processor FSB agents. The following table defines the coverage model of these signals. Request Signals A[35:24]# A[23:3]# REQ[4:0]# Subphase 1 AP0# AP1# AP1# Subphase 2 AP1# AP0# AP0# 64 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins/lands of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# activation. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the FSB and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# Input/ Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. This input is required to determine whether the processor is installed in a platform that supports the Pentium 4 processor. The processor will not operate if this signal is low. This input has a weak internal pull-up to VCC. BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[5:0]# Input/ Output BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. These signals do not have on-die termination. Refer to Section 2.5.2 for termination requirements. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#. BCLK[1:0] Input BINIT# Input/ Output BOOTSELECT Input BPRI# Input Datasheet 65 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 18 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations, refer to Chapter 2. COMP[1:0] must be terminated to VSS on the system board using precision resistors. COMP[5:4] must be terminated to VTT on the system board using precision resistors. D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#. Quad-Pumped Signal Groups D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DBI# 0 1 2 3 BR0# Input/ Output BSEL[2:0] Output COMP[5:4,1:0] Analog Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. 66 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. DBI[3:0]# Input/ Output DBI[3:0] Assignment To Data Bus Bus Signal DBI3# DBI2# DBI1# DBI0# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]# DBR# Output DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins/lands on all processor FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents. DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins/lands of all processor FSB agents. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#. Signals Associated Strobe DSTBN0# DSTBN1# DSTBN2# DSTBN3# DBSY# Input/ Output DEFER# Input DP[3:0]# Input/ Output DRDY# Input/ Output DSTBN[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Datasheet 67 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description DSTBP[3:0]# are the data strobes used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# FCx Other Associated Strobe DSTBP0# DSTBP1# DSTBP2# DSTBP3# FC signals are signals that are available for compatibility with other processors. FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/ PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel® 64 and IA-32 Architecture Software Developer’s Manual and the Intel Processor Identification and the CPUID Instruction application note. GTLREF[1:0] determine the signal reference level for GTL+ input signals. GTLREF is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination. Refer to Section 2.5.2 for termination requirements. FERR#/PBE# Output GTLREF[1:0] Input Input/ Output Input/ Output HIT# HITM# IERR# Output 68 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. IMPSEL Input IMPSEL input will determine whether the processor uses a 50 Ω or 60 Ω buffer. This pin must be tied to GND on 50Ω platforms and left as NC on 60Ω platforms. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands of all processor FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these signals as LINT[1:0] is the default configuration. LL_ID[1:0] Output The LL_ID[1:0] signals are used to select the correct loadline slope for the processor. LL_ID[1:0] = 00 for the Pentium 4 processor. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# de-asserted. This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock. IGNNE# Input INIT# Input ITP_CLK[1:0] Input LINT[1:0] Input LOCK# Input/ Output Datasheet 69 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: MCERR# Input/ Output • • • • Enabled or disabled. Asserted, if configured, for internal errors along with IERR#. Asserted, if configured, by the request initiator of a bus transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 3: System Programming Guide. MSID[1:0] (input) MSID0 is used to indicate to the processor whether the platform supports 775_VR_CONFIG_05B processors. A 775_VR_CONFIG_05B processor will only boot if it’s MSID0 pin is electrically low. A 775_VR_CONFIG_05A processor will ignore this input. MSID1 must be electrically low for the processor to boot. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system de-asserts PROCHOT#. See Section 5.2.4 for more details. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# (Request Command) must connect the appropriate pins/lands of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity checking of these signals. MSID[1:0] Input PROCHOT# Input/ Output PWRGOOD Input REQ[4:0]# Input/ Output 70 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1. This signal does not have on-die termination and must be terminated on the system board. RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents. RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins/lands of all processor FSB agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent ensuring correct parity. SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the de-assertion of RESET#, the processor will tri-state its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. RESET# Input RSP# Input SMI# Input STPCLK# Input TCK TDI TDO Input Input Output Datasheet 71 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description TESTHI[13:0] must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a resistor for proper processor operation. See Section 2.4 for more details. Thermal Diode Anode. See Section 5.2.7. Thermal Diode Cathode. See Section 5.2.7. In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 µs of the assertion of PWRGOOD (provided VTTPWRGD, VTT, and VCC are asserted) and is disabled on de-assertion of PWRGOOD (if VTTPWRGD, VTT, or VCC are not valid, THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains latched until PWRGOOD, VTTPWRGD, VTT or VCC is de-asserted. While the de-assertion of the PWRGOOD, VTTPWRGD, VTT or VCC signal will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 µs of the assertion of PWRGOOD (provided VTTPWRGD, VTT, and VCC are asserted). TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. VCC are the power lands for the processor. The voltage supplied to these lands is determined by the VID[5:0] pins. VCCA provides isolated power for the internal processor core PLLs. VCCIOPLL provides isolated power for internal processor FSB PLLs. VCC_SENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure voltage near the silicon with little noise. This land is provided as a voltage regulator feedback sense point for VCC. It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775. TESTHI[13:0] THERMDA THERMDC Input Other Other THERMTRIP# Output TMS TRDY# TRST# VCC VCCA VCCIOPLL VCC_SENSE Input Input Input Input Input Input Output VCC_MB_ REGULATION Output 72 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description VID[5:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See Table 2 for definitions of these signals. The VR must supply the voltage that is requested by the signals, or disable itself. VSS are the ground pins for the processor and should be connected to the system ground plane. VSSA is the isolated ground for internal PLLs. VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. This land is provided as a voltage regulator feedback sense point for VSS. It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775. Miscellaneous voltage supply. Output VTT_OUT_RIGHT VTT_SEL VTTPWRGD Output Input The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to VTT on the motherboard. The VTT_SEL signal is used to select the correct VTT voltage level for the processor. This land is connected internally in the package to VTT. The processor requires this input to determine that the VTT voltages are stable and within specification. VID[5:0] Output VSS VSSA VSS_SENSE Input Input Output VSS_MB_ REGULATION VTT VTT_OUT_LEFT Output §§ Datasheet 73 Land Listing and Signal Descriptions 74 Datasheet Thermal Specifications and Design Considerations 5 5.1 Thermal Specifications and Design Considerations Processor Thermal Specifications The Pentium 4 processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on the boxed processor. 5.1.1 Thermal Specifications To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (TC) specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 26. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). The Pentium 4 processor uses a methodology for managing processor temperatures that is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed will be based on the temperature reported by the processor’s Thermal Diode. If the diode temperature is greater than or equal to TCONTROL, then the processor case temperature must remain at or below the temperature as specified by the thermal profile. If the diode temperature is less than TCONTROL, then the case temperature is permitted to exceed the thermal profile; but the diode temperature must remain at or below TCONTROL. Systems that implement fan speed control must be designed to take these conditions into account. Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) and the Processor Power Characterization Methodology for the details of this methodology. Datasheet 75 Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to Section 5.2. In all cases the Thermal Monitor or Thermal Monitor 2 feature must be enabled for the processor to remain within specification. Table 26. Processor Thermal Specifications for 775_VR_CONFIG_05A Processors Processor Number 631 641 651 661 Core Frequency (GHz) 3 GHz 3.20 GHz 3.40 GHz 3.60 GHz Thermal Design Power (W) 86 86 86 86 Minimum TC (°C) 5 5 5 5 Maximum TC (°C) See Table 28 and Figure 12 See Table 28 and Figure 12 See Table 28 and Figure 12 See Table 28 and Figure 12 Notes 1, 2 1, 2 1, 2 1, 2 1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate. 2. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the maximum TC will vary depending on the TDP of the individual processor. Refer to Table 28 and Figure 12 for the allowed combinations of power and TC. NOTES: Table 27. Processor Thermal Specifications for 775_VR_CONFIG_06 Processors Processor Number 631 641 651 Core Frequency (GHz) 3 GHz 3.20 GHz 3.40 GHz Thermal Design Power (W) 65 65 65 Minimum TC (°C) 5 5 5 Maximum TC (°C) Notes See Table 29and Figure 13 1, 2 1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate. 2. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the maximum TC will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table for the allowed combinations of power and TC. NOTES: 76 Datasheet Thermal Specifications and Design Considerations Table 28. Thermal Profile for 775_VR_CONFIG_05A Processors Power (W) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 Maximum TC (°C) 44.3 44.9 45.5 46.0 46.6 47.2 47.8 48.4 48.9 49.5 50.1 50.7 51.3 51.8 52.4 Power (W) 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 Maximum TC (°C) 53.0 53.6 54.2 54.7 55.3 55.9 56.5 57.1 57.6 58.2 58.8 59.4 60.0 60.5 61.1 Power (W) 60 62 64 66 68 70 72 74 76 78 80 82 84 86 Maximum TC (°C) 61.7 62.3 62.9 63.4 64.0 64.6 65.2 65.8 66.3 66.9 67.5 68.1 68.7 69.2 Figure 12. Thermal Profile for 775_VR_CONFIG_05A Processors 70.0 65.0 y = 0.29x + 44.3 60.0 Tcase (C) 55.0 50.0 45.0 40.0 0 10 20 30 40 Power (W) 50 60 70 80 Datasheet 77 Thermal Specifications and Design Considerations Table 29. Thermal Profile for 775_VR_CONFIG_06 Processors Power (W) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Maximum Tc (°C) 43.6 44.2 44.9 45.5 46.2 46.8 47.4 48.1 48.7 49.4 50.0 50.6 51.3 51.9 52.6 53.2 53.8 Power (W) 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Maximum Tc (°C) 54.5 55.1 55.8 56.4 57.0 57.7 58.3 59.0 59.6 60.2 60.9 61.5 62.2 62.8 63.4 64.1 Figure 13. Thermal Profile for 775_VR_CONFIG_06 Processors 70.0 y = 0.32x + 43.6 65.0 60.0 Tcase (C) 55.0 50.0 45.0 40.0 0 10 20 30 40 Power (W) 50 60 70 80 78 Datasheet Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 14 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). Figure 14. Case Temperature (TC) Measurement Location Measure TC at this point (geometric center of the package) 37.5 mm 37.5 mm 5.2 5.2.1 Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. When the Thermal Monitor feature is enabled and a high temperature situation exists (i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will not be off for more than 3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. Datasheet 79 Thermal Specifications and Design Considerations With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature; this may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines. 5.2.2 Thermal Monitor 2 The Pentium 4 processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor. When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor is that contained in the IA32_PERF_STS MSR and the VID is the one specified in Table 4. These parameters represent normal system operation. The second operating point consists of both a lower operating frequency and voltage. When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 µs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts are latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see Table 4). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 15 for an illustration of this ordering. 80 Datasheet Thermal Specifications and Design Considerations Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 fMAX fTM2 VID VIDTM2 Temperature Frequency VID PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. Note that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode. 5.2.3 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the Pentium 4 processor must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL MSR) is written to a '1', the processor immediately reduces its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5% on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. Datasheet 81 Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the Intel® 64 and IA-32 Architecture Software Developer’s Manuals for specific register and programming details. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for details on implementing the bi-directional PROCHOT# feature. 5.2.5 THERMTRIP# Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. 5.2.6 TCONTROL and Fan Speed Reduction TCONTROL is a temperature specification based on a temperature reading from the thermal diode. The value for TCONTROL will be calibrated in manufacturing and configured for each processor. When TDIODE is above TCONTROL, TC must be at or below TC-MAX as defined by the thermal profile in Table 28 and Figure 12; otherwise, the processor temperature can be maintained at TCONTROL (or lower) as measured by the thermal diode. The purpose of this feature is to support acoustic optimization through fan speed control. Contact your Intel representative for further details and documentation. 5.2.7 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal "diode", with its collector shorted to Ground. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control. Table 30, Table 31, Table 32, and Table 33 provide the "diode" parameter and interface specifications. Two different sets of "diode" parameters are listed in Table 30 and Table 31. The Diode Model parameters (Table 30) apply to traditional thermal sensors that use the Diode Equation to determine the 82 Datasheet Thermal Specifications and Design Considerations processor temperature. Transistor Model parameters (Table 31) have been added to support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. This thermal "diode" is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. Table 30. Thermal “Diode” Parameters using Diode Model Symbol IFW n RT 1. 2. 3. 4. Parameter Forward Bias Current Diode Ideality Factor Series Resistance Min 5 1.000 2.79 Typ — 1.009 4.52 Max 200 1.050 6.24 Unit µA Ω Notes 1 2, 3, 4 2, 3, 5 NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Characterized across a temperature range of 50 – 80 °C. Not 100% tested. Specified by design characterization. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW = IS * (e qVD/nkT –1) where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature. RT, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N] where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic charge. Table 31. Thermal “Diode” Parameters using Transistor Model Symbol IFW IE nQ Beta RT 1. 2. 3. 4. 5. Parameter Forward Bias Current Emitter Current Transistor Ideality Min 5 5 0.997 0.391 Typ — — 1.001 — 4.52 Max 200 200 1.005 0.760 6.24 Unit µA µA — — Ω Notes 1, 2 3, 4, 5 3, 4 3, 6 Series Resistance 2.79 NOTES: Characterized across a temperature range of 50 – 80 °C. Not 100% tested. Specified by design characterization. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current: Same as IFW in Table 30. Intel does not support or recommend operation of the thermal diode under reverse bias. IC = IS * (e qVBE/nQkT –1) Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin). 6. The series resistance, RT, provided in the Diode Model Table (Table 30) can be used for more accurate readings as needed. When calculating a temperature based on thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although some are capable of also measuring the series resistance. Calculating the temperature is then Datasheet 83 Thermal Specifications and Design Considerations accomplished using the equations listed under Table 30. In most temperature sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode the ideality value (also called ntrim) will be 1.000. Given that most diodes are not perfect, the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. If the processors diode ideality deviates from that of ntrim, each calculated temperature will be offset by a fixed amount. This temperature offset can be calculated with the equation: Terror(nf) = Tmeasured X (1 – nactual/ntrim) Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing device. To improve the accuracy of diode based temperature measurements, a new register (Tdiode_Offset) has been added to processor that will contain thermal diode characterization data. During manufacturing each processors thermal diode will be evaluated for its behavior relative to a theoretical diode. Using the equation above, the temperature error created by the difference between ntrim and the actual ideality of the particular processor will be calculated. This value (Tdiode_Offset) will be programmed in to the new diode correction MSR and when added to the Tdiode_Base value can be used to correct temperatures read by diode based temperature sensing devices. If the ntrim value used to calculate Tdiode_Offset differs from the ntrim value used in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Tdiode_Offset can be adjusted by calculating nactual and then recalculating the offset using the actual ntrim as defined in the temperature sensor manufacturers' datasheet. The Diode_Base value and ntrim used to calculate the Diode_Correction_Offset are listed in Table 32. Table 32. Thermal “Diode” ntrim and Diode_Correction_Offset Symbol ntrim Diode_Base Parameter Diode ideality used to calculate Diode_Offset 1.008 0 Unit — °C Table 33. Thermal Diode Interface Signal Name THERMDA THERMDC Land Number AL1 AK1 Signal Description diode anode diode cathode §§ 84 Datasheet Features 6 6.1 Features Power-On Configuration Options Several configuration options can be configured by hardware. The Pentium 4 processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 34. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset. Table 34. Power-On Configuration Option Signals Configuration Option Output tristate Execute BIST In Order Queue pipelining (set IOQ depth to 1) Disable MCERR# observation Disable BINIT# observation APIC Cluster ID (0-3) Disable bus parking Disable Hyper-Threading Technology Symmetric agent arbitration ID RESERVED Signal1,2 SMI# INIT# A7# A9# A10# A[12:11]# A15# A31# BR0# A[6:3]#, A8#, A[14:13]#, A[16:35]# 1. Asserting this signal during RESET# will select the corresponding option. 2. Address signals not identified in this table as configuration options should not be asserted during RESET#. NOTES: 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 16 for a visual representation of the processor low power states. Datasheet 85 Features Figure 16. Processor Low Power State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Normal State Normal execution INIT#, BINIT#, INTR, NMI, SMI#, RESET#, FSB interrupts Enhanced HALT or HALT State BCLK running Snoops and interrupts allowed S As TP se C L rte K# d S D TP e- C as LK se # rte d STPCLK# Asserted STPCLK# De-asserted Snoop Event Occurs Snoop Event Serviced Enhanced HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Stop Grant State BCLK running Snoops and interrupts allowed Snoop Event Occurs Snoop Event Serviced Stop Grant Snoop State BCLK running Service snoops to caches 6.2.1 Normal State This is the normal operating state for the processor. 6.2.2 HALT and Enhanced HALT Powerdown States The Pentium 4 processor supports the HALT or Enhanced HALT powerdown state. The Enhanced HALT Powerdown state is configured and enabled via the BIOS. The Enhanced HALT state must be enabled via the BIOS for the processor to remain within its specifications. The Enhanced HALT state is a lower power state as compared to the Stop Grant State. If Enhanced HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the following sections for details about the HALT and Enhanced HALT states. 6.2.2.1 HALT Powerdown State HALT is a low power state entered when all the logical processors have executed the HALT or MWAIT instructions. When one of the logical processors executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. 86 Datasheet Features The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume III: System Programmer's Guide for more information. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Enhanced HALT Powerdown State Enhanced HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the logical processors executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The processor will automatically transition to a lower frequency and voltage operating point before entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID. While in Enhanced HALT state, the processor will process bus snoops. The processor exits the Enhanced HALT state when a break event occurs. When the processor exits the Enhanced HALT state, it will first transition the VID to the original value and then change the bus ratio back to the original value. 6.2.3 Stop Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop Grant state. The event will be latched and can be serviced by software upon exit from the Stop Grant state. RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4). While in the Stop-Grant State, SMI#, INIT#, BINIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. Datasheet 87 Features While in Stop-Grant state, the processor will process a FSB snoop. 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the following sections for details on HALT Snoop State, Grant Snoop State and Enhanced HALT Snoop State. 6.2.4.1 HALT Snoop State, Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop Grant state or HALT Power Down state, as appropriate. 6.2.4.2 Enhanced HALT Snoop State The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID operating point of the Enhanced HALT state. While in the Enhanced HALT Snoop State, snoops are handled the same way as in the HALT Snoop State. After the snoop is serviced the processor will return to the Enhanced HALT state. §§ 88 Datasheet Boxed Processor Specifications 7 Boxed Processor Specifications The Intel Pentium 4 processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed Pentium 4 processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed Pentium 4 processor. This chapter is particularly important for OEMs that manufacture baseboards for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. Figure 17 shows a mechanical representation of a boxed Pentium 4 processor. Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for further guidance. Mechanical Representation of the Boxed Processor Figure 17. NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. 7.1 7.1.1 Mechanical Specifications Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium 4 processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 17 shows a mechanical representation of the boxed Pentium 4 processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 18 (Side View), and Figure 19 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 23 and Figure 24. Note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning. Datasheet 89 Boxed Processor Specifications Figure 18. Space Requirements for the Boxed Processor (Side View; applies to all four side views) 95.0 [3.74] 81.3 [3.2] 10.0 [0.39] 25.0 [0.98] B dP Sid Vi Figure 19. Space Requirements for the Boxed Processor (Top View) 95.0 [3.74] 95.0 [3.74] NOTES: 1. The boxed Pentium 4 processor in the 775-land package cooling solution with clip is currently under development and, at this time, is preliminary. The diagrams shown may not reflect the final product. 2. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. 90 Datasheet Boxed Processor Specifications Figure 20. Space Requirements for the Boxed Processor (Overall View) 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly. 7.2 7.2.1 Electrical Requirements Fan Heatsink Power Supply The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 21. Baseboards must provide a matched power header to support the boxed processor. Table 35 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open-collector output that pulses at a rate of two pulses per fan revolution. A baseboard pull-up resistor provides VOH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The fan heatsink receives a PWM signal from the motherboard from the fourth pin of the connector labeled as CONTROL. Note: The boxed processor’s fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. Datasheet 91 Boxed Processor Specifications The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 22 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 4.33 inches from the center of the processor socket. Figure 21. Boxed Processor Fan Heatsink Power Cable Connector Description Pin 1 2 3 4 Signal GND +12 V SENSE CONTROL Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard. 1234 Table 35. Fan Heatsink Power and Signal Specifications Description +12 V: 12 volt fan power supply IC: Peak Fan current draw Fan start-up current draw Fan start-up current draw maximum duration SENSE: SENSE frequency CONTROL — — — — 21 1.1 — — 2 25 1.5 2.2 1.0 — 28 A A Second pulses per fan revolution kHz 1 Min 10.2 Typ 12 Max 13.8 Unit V Notes 2 ,3 1. Baseboard should pull this pin up to 5 V with a resistor. 2. Open Drain Type, Pulse Width Modulated. 3. Fan will have a pull-up resistor to 4.75 V, maximum 5.25 V. NOTES: 92 Datasheet Boxed Processor Specifications Figure 22. Baseboard Power Header Placement Relative to Processor Socket B R110 [4.33] C 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is in Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the specifications in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 23 and Figure 24 illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 38 °C. A Thermally Advantaged Chassis with an Air Guide 1.1 is recommended to meet the 38 °C requirement. Again, meeting the processor's temperature specification is the responsibility of the system integrator. Note: The processor fan is the primary source of airflow for cooling the VCC voltage regulator. Dedicated voltage regulator cooling components may be necessary if the selected fan is not capable of keeping regulator components below maximum rated temperatures. Datasheet 93 Boxed Processor Specifications Figure 23. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 1 View) Figure 24. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 2 View) §§ 94 Datasheet Balanced Technology Extended (BTX) Boxed Processor Specifications 8 Balanced Technology Extended (BTX) Boxed Processor Specifications The Intel Pentium 4 processors will be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from largely standard components. The boxed Intel Pentium 4 processor will be supplied with a cooling solution known as the Thermal Module Assembly (TMA). Each processor will be supplied with one of the two available types of TMAs – Type I or Type II. This chapter documents motherboard and system requirements for both the TMAs that will be supplied with the boxed Pentium 4 processor in the 775-land package. This chapter is particularly important for OEMs that manufacture motherboards for system integrators. Figure 25 shows a mechanical representation of a boxed Pentium 4 processor in the 775-land package with a Type I TMA. Figure 26 illustrates a mechanical representation of a boxed Pentium 4 processor in the 775-land package with Type II TMA. Note: Note: Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designer’s responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for further guidance. Mechanical Representation of the Boxed Processor with a Type I TMA Figure 25. NOTE: The duct, clip, heatsink, and fan can differ from this drawing representation but the basic shape and size will remain the same. Datasheet 95 Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 26. Mechanical Representation of the Boxed Processor with a Type II TMA NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but the basic shape and size will remain the same. 8.1 8.1.1 Mechanical Specifications Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Intel Pentium 4 processor TMA. The boxed processor will be shipped with an unattached TMA. Figure 27 shows a mechanical representation of the boxed Pentium 4 processor in the 775-land package for Type I TMA. Figure 28 shows a mechanical representation of the boxed Pentium 4 processor in the 775-land package for Type II TMA. The physical space requirements and dimensions for the boxed processor with assembled fan thermal module are shown. 96 Datasheet Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 27. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Datasheet 97 Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 28. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. 8.1.2 Boxed Processor Thermal Module Assembly Weight The boxed processor thermal module assembly for Type I BTX will not weigh more than 1200 grams. The boxed processor thermal module assembly for Type II BTX will not weigh more than 1200 grams. See Chapter 5 and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and thermal module assembly requirements. 8.1.3 Boxed Processor Support and Retention Module (SRM) The boxed processor TMA requires an SRM assembly provided by the chassis manufacturer. The SRM provides the attach points for the TMA and provides structural support for the board by distributing the shock and vibration loads to the chassis base pan. The boxed processor TMA will ship with the heatsink attach clip assembly, duct and screws for attachment. The SRM must be supplied by the chassis hardware vendor. See the Support and Retention Module (SRM) External Design Requirements 98 Datasheet Balanced Technology Extended (BTX) Boxed Processor Specifications Document, Balanced Technology Extended (BTX) System Design Guide, and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for more detailed information regarding the support and retention module and chassis interface and keepout zones. Figure 29 illustrates the assembly stack including the SRM. Figure 29. Assembly Stack Including the Support and Retention Module Thermal Module Assembly • Heatsink & Fan • Clip • Structural Duct Motherboard SRM Chassis Pan 8.2 8.2.1 Electrical Requirements Thermal Module Assembly Power Supply The boxed processor's Thermal Module Assembly (TMA) requires a +12 V power supply. The TMA will include power cable to power the integrated fan and will plug into the 4-wire fan header on the baseboard. The power cable connector and pinout are shown in Figure 30. Baseboards must provide a compatible power header to support the boxed processor. Table 36 contains specifications for the input and output signals at the TMA. The TMA outputs a SENSE signal, which is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The TMA receives a Pulse Width Modulation (PWM) signal from the motherboard from the 4th pin of the connector labeled as CONTROL. Datasheet 99 Balanced Technology Extended (BTX) Boxed Processor Specifications Note: The boxed processor’s TMA requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the TMA power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 31 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 4.33 inches from the center of the processor socket. Figure 30. Boxed Processor TMA Power Cable Connector Description Pin 1 2 3 4 Signal GND +12 V SENSE CONTROL Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard. 1234 Boxed Proc PwrCable Table 36. TMA Power and Signal Specifications Description +12 V: 12 volt fan power supply IC: Peak Fan current draw Fan start-up current draw Fan start-up current draw maximum duration SENSE: SENSE frequency CONTROL — — — — 21 1.0 — — 2 25 1.5 2.0 1.0 — 28 A A Second pulses per fan revolution kHz 1 Min 10.2 Typ 12 Max 13.8 Unit V Notes 2 ,3 1. Baseboard should pull this pin up to 5 V with a resistor. 2. Open Drain Type, Pulse Width Modulated. 3. Fan will have a pull-up resistor to 4.75 V, maximum 5.25 V. NOTES: 100 Datasheet Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 31. Balanced Technology Extended (BTX) Mainboard Power Header Placement (Hatched Area) 8.3 Thermal Specifications This section describes the cooling requirements of the thermal module assembly solution used by the boxed processor. 8.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a TMA. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor case temperature specification is in Chapter 5. The boxed processor TMA is able to keep the processor temperature within the specifications in Table 26 for chassis that provide good thermal management. For the boxed processor TMA to operate properly, it is critical that the airflow provided to the TMA is unimpeded. Airflow of the TMA is into the duct and out of the rear of the duct in a linear flow. Blocking the airflow to the TMA inlet reduces the cooling efficiency and decreases fan life. Filters will reduce or impede airflow which will result in a reduced performance of the TMA. The air temperature entering the fan should be kept below 35.5°C. Again, meeting the processor's temperature specification is the responsibility of the system integrator. Datasheet 101 Balanced Technology Extended (BTX) Boxed Processor Specifications In addition, Type I TMA must be used with Type I chassis only and Type II TMA with Type II chassis only. Type I TMA will not fit in a Type II chassis due to the height difference. In the event a Type II TMA is installed in a Type I chassis, the gasket on the chassis will not seal against the Type II TMA and poor acoustic performance will occur as a result. 8.3.2 Variable Speed Fan The boxed processor fan will operate at different speeds over a short range of temperatures based on a thermistor located in the fan hub area. This allows the boxed processor fan to operate at a lower speed and noise level while thermistor temperatures are low. If the thermistor senses a temperatures increase beyond a lower set point, the fan speed will rise linearly with the temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so do fan noise levels. These set points are represented in Figure 32 and Table 37. The internal chassis temperature should be kept below 35.5ºC. Meeting the processor’s temperature specification (see Chapter 5) is the responsibility of the system integrator. Note: The motherboard must supply a constant +12 V to the processor’s power header to ensure proper operation of the variable speed fan for the boxed processor (refer to Table 37) for the specific requirements). Boxed Processor TMA Set Points Figure 32. Higher Set Point Highest Noise Level Increasing Fan Speed & Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature (Degrees C) 102 Datasheet Balanced Technology Extended (BTX) Boxed Processor Specifications Table 37. TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors Boxed Processor TMA Set Point (ºC) Boxed Processor Fan Speed When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds. Recommended maximum internal chassis temperature for worst-case operating environment. When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed. 1 Notes X ≤ 23 1 Y = 29 Z ≥ 35.5 1. Set point variance is approximately ±1°C from Thermal Module Assembly to Thermal Module Assembly. NOTES: If the boxed processor TMA 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (see CONTROL in Table 36) and remote thermal diode measurement capability, the boxed processor will operate as described in the following paragraphs. As processor power has increased, the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage. The 4-wire PWM controlled fan in the TMA solution provides better control over chassis acoustics. It allows better granularity of fan speed and lowers overall fan speed than a voltage-controlled fan. Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on a combination of actual processor temperature and thermistor temperature. If the 4-wire PWM controlled fan in the TMA solution is connected to a 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control see the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). §§ Datasheet 103 Balanced Technology Extended (BTX) Boxed Processor Specifications 104 Datasheet Debug Tools Specifications 9 9.1 Debug Tools Specifications Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Pentium 4 processor systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Pentium 4 processor systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a Pentium 4 processor system that can make use of an LAI: mechanical and electrical. 9.1.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI. 9.1.2 Electrical Considerations The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides. §§ Datasheet 105 Debug Tools Specifications 106 Datasheet

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