82443ZX

Intel® 440ZX AGPset: 82443ZX Host Bridge/Controller Datasheet November 1998 Order Number: 290650-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The 82443ZX chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1997-1998 *Third-party brands and names are the property of their respective owners. 82443ZX Host Bridge Datasheet Intel 82443ZX Features • Processor/host bus support — Optimized for Pentium® II processor at 100 MHz system bus frequency; Support for 66 MHz — In-order transaction and dynamic deferred transaction support — Desktop optimized GTL+ bus driver technology (gated GTL+ receivers for reduced power) Integrated DRAM controller — 8 to 256Mbytes — Supports 2 double-sided DIMMs (4 rows memory) — 64-bit data interface — Unbuffered SDRAM (Synchronous) DRAM Support (x1-1-1 access @ 66 MHz, x-1-1-1 access @ 100 MHz) — Enhanced SDRAM Open Page Architecture Support for 16- and 64-Mbit DRAM devices with 2k, 4k and 8k page sizes — PCI Rev. 2.1, 3.3V and 5V, 33MHz interface compliant — PCI Parity Generation Support — Data streaming support from PCI to DRAM — Delayed Transaction support for PCI-DRAM Reads — Supports concurrent CPU, AGP and PCI transactions to main memory • AGP interface — Supports single AGP compliant device (AGP-66/133 3.3V device) — AGP Specification Rev 1.0 compliant — AGP-data/transaction flow optimized arbitration mechanism — AGP side-band interface for efficient request pipelining without interfering with the data streams — AGP-specific data buffering — Supports concurrent CPU, AGP and PCI transactions to main memory — AGP high-priority transactions (“expedite”) support Power Management Functions — Stop Clock Grant and Halt special cycle translation (host to PCI Bus) — Dynamic power down of idle DRAM rows — Independent, internal dynamic clock gating reduces average power dissipationt Packaging/Voltage — 492 Pin BGA — 3.3V core and mixed 3.3V and GTL I/O Supporting I/O Bridge — System Management Bus (SMB) with support for DIMM Serial Presence Detect (SPD) — PCI-ISA Bridge (PIIX4E) — 3.3V core and mixed 5V, 3.3V I/O and interface to the 2.5V CPU signals via open-drain output buffers • • • PCI bus interface • • The Intel® 440ZX AGPset is intended for the Pentium® II processor platform and emerging 3D graphics/multimedia applications. The 82443ZX Host Bridge provides a Host-to-PCI bridge, optimized DRAM controller and data path, and an Accelerated Graphic Port (AGP) interface. AGP is a high performance, component level interconnect targeted at 3D graphics applications and is based on a set of performance enhancements to PCI. The I/O subsystem portion of the Intel® 440ZX AGPset platform is based on the 82371EB (PIIX4E), a highly integrated version of the Intel’s PCI-ISA bridge family. The Intel 82443ZX may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request. 82443ZX Host Bridge Datasheet iii Intel 82443ZX Simplified Block Diagram A[31:3]# ADS# BPRI# BNR# CPURST# DBSY# DEFER# HD[63:0]# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# DRDY# RS[2:0]# RASA[5:0]/CSA[5:0]# RASB[5:0]/CSB[5:0]# CKE[3:2]/CSA[7:6]# CKE[5:4]/CSB[7:6]# CASA[7:0]/DQMA[7:0] CASB[5,1]/DQMB[5,1] GCKE/CKE1 SRAS[B,A]# CKE0/FENA SCAS[B,A]# MAA[13:0] MAB[13,12#,11#,10,9#:0#] WEA# WEB# MD[63:0] MECC[7:0] AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# DEVSEL# PAR SERR# PLOCK# STOP# PHOLD# PHLDA# PREQ[3:0]# PGNT[3:0]# Host Interface PCI Bus Interface (PCI #0) DRAM Interface AGP Interface GAD[31:0] GC/BE[3:0]# GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GREQ# GGNT# GPAR PIPE# SBA[7:0] RBF# STOP# ST[2:0] ADSTB_A ADSTB_B SBSTB HCLKIN PCLKIN GTLREF[B:A] AGPREF VTT[B:A] REF5V PCIRST# CRESET# BREQ0# TESTIN# GCLKO GCLKIN DCLKO DCLKWR Clocks, Reset, Test, and Misc. Power Mgnt CLKRUN# BXPWROK BX_BLK.VSD iv 82443ZX Host Bridge Datasheet Contents 1 2 Architectural Overview ...............................................................................................1-1 Signal Description ......................................................................................................2-1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 3.1 Host Interface Signals...................................................................................2-1 DRAM Interface ............................................................................................2-3 PCI Interface (Primary) .................................................................................2-5 Primary PCI Sideband Interface ...................................................................2-6 AGP Interface Signals...................................................................................2-7 Clocks, Reset, and Miscellaneous ................................................................2-9 Power-Up/Reset Strap Options...................................................................2-10 I/O Mapped Registers ...................................................................................3-2 3.1.1 CONFADD—Configuration Address Register..................................3-2 3.1.2 CONFDATA—Configuration Data Register .....................................3-3 3.1.3 PM2_CTL—ACPI Power Control 2 Control Register .......................3-4 PCI Configuration Space Access..................................................................3-4 3.2.1 Configuration Space Mechanism Overview .....................................3-5 3.2.2 Routing the Configuration Accesses to PCI or AGP ........................3-5 3.2.3 PCI Bus Configuration Mechanism Overview ..................................3-6 3.2.3.1 Type 0 Access ....................................................................3-6 3.2.3.2 Type 1 Access ....................................................................3-6 3.2.4 AGP Bus Configuration Mechanism Overview ................................3-6 3.2.5 Mapping of Configuration Cycles on AGP .......................................3-7 Host-to-PCI Bridge Registers (Device 0) ......................................................3-8 3.3.1 VID—Vendor Identification Register (Device 0).............................3-10 3.3.2 DID—Device Identification Register (Device 0) .............................3-10 3.3.3 PCICMD—PCI Command Register (Device 0) ..............................3-11 3.3.4 PCISTS—PCI Status Register (Device 0) .....................................3-12 3.3.5 RID—Revision Identification Register (Device 0) ..........................3-13 3.3.6 SUBC—Sub-Class Code Register (Device 0) ...............................3-13 3.3.7 BCC—Base Class Code Register (Device 0) ................................3-13 3.3.8 MLT—Master Latency Timer Register (Device 0)..........................3-14 3.3.9 HDR—Header Type Register (Device 0) .......................................3-14 3.3.10 APBASE—Aperture Base Configuration Register (Device 0)........3-14 3.3.11 SVID—Subsystem Vendor Identification Register (Device 0)........3-15 3.3.12 SID—Subsystem Identification Register (Device 0).......................3-16 3.3.13 CAPPTR—Capabilities Pointer Register (Device 0) ......................3-16 3.3.14 NBXCFG—NBX Configuration Register (Device 0) .......................3-16 3.3.15 DRAMC—DRAM Control Register (Device 0) ...............................3-19 3.3.16 DRAMT—DRAM Timing Register (Device 0) ................................3-20 3.3.17 PAM[6:0]—Programmable Attribute Map Registers (Device 0)3-20 3.3.18 DRB[0:7]—DRAM Row Boundary Registers (Device 0) ................3-22 3.3.19 FDHC—Fixed DRAM Hole Control Register (Device 0) ................3-24 3.3.20 MBSC—Memory Buffer Strength Control Register (Device 0).......................................................................................3-25 Register Description...................................................................................................3-1 3.2 3.3 82443ZX Host Bridge Datasheet v 3.4 3.3.21 SMRAM—System Management RAM Control Register (Device 0) ......................................................................................3-27 3.3.22 ESMRAMC—Extended System Management RAM Control Register (Device 0) ........................................................................3-28 3.3.23 RPS—SDRAM Row Page Size Register (Device 0)......................3-29 3.3.24 SDRAMC—SDRAM Control Register (Device 0) ..........................3-29 3.3.25 PGPOL—Paging Policy Register (Device 0) .................................3-31 3.3.26 PMCR—Power Management Control Register (Device 0) ............3-32 3.3.27 SCRR—Suspend CBR Refresh Rate Register (Device 0) ............3-33 3.3.28 EAP—Error Address Pointer Register (Device 0)..........................3-33 3.3.29 ERRCMD—Error Command Register (Device 0) ..........................3-34 3.3.30 ERRSTS—Error Status Register (Device 0)..................................3-35 3.3.31 ACAPID—AGP Capability Identifier Register (Device 0) ...............3-36 3.3.32 AGPSTAT—AGP Status Register (Device 0) ................................3-36 3.3.33 AGPCMD—AGP Command Register (Device 0)...........................3-37 3.3.34 AGPCTRL—AGP Control Register (Device 0) ..............................3-38 3.3.35 APSIZE—Aperture Size Register (Device 0) .................................3-39 3.3.36 ATTBASE—Aperture Translation Table Base Register (Device 0) ......................................................................................3-39 3.3.37 MBFS—Memory Buffer Frequency Select Register (Device 0) ......................................................................................3-40 3.3.38 BSPAD—BIOS Scratch Pad Register (Device 0) ..........................3-41 3.3.39 DWTC—DRAM Write Thermal Throttling Control Register (Device 0) ......................................................................................3-42 3.3.40 DRTC—DRAM Read Thermal Throttling Control Register (Device 0) ......................................................................................3-43 3.3.41 BUFFC—Buffer Control Register (Device 0) .................................3-44 PCI-to-PCI Bridge Registers (Device 1) .....................................................3-45 3.4.1 VID1—Vendor Identification Register (Device 1)...........................3-46 3.4.2 DID1—Device Identification Register (Device 1) ...........................3-46 3.4.3 PCICMD1—PCI-to-PCI Command Register (Device 1) ................3-47 3.4.4 PCISTS1—PCI-to-PCI Status Register (Device 1) ........................3-48 3.4.5 RID1—Revision Identification Register (Device 1) ........................3-48 3.4.6 SUBC1—Sub-Class Code Register (Device 1) .............................3-49 3.4.7 BCC1—Base Class Code Register (Device 1) ..............................3-49 3.4.8 MLT1—Master Latency Timer Register (Device 1)........................3-49 3.4.9 HDR1—Header Type Register (Device 1) .....................................3-50 3.4.10 PBUSN—Primary Bus Number Register (Device 1)......................3-50 3.4.11 SBUSN—Secondary Bus Number Register (Device 1) .................3-50 3.4.12 SUBUSN—Subordinate Bus Number Register (Device 1) ............3-51 3.4.13 SMLT—Secondary Master Latency Timer Register (Device 1)3-51 3.4.14 IOBASE—I/O Base Address Register (Device 1) ..........................3-51 3.4.15 IOLIMIT—I/O Limit Address Register (Device 1) ...........................3-52 3.4.16 SSTS—Secondary PCI-to-PCI Status Register (Device 1) ...........3-52 3.4.17 MBASE—Memory Base Address Register (Device 1)...................3-53 3.4.18 MLIMIT—Memory Limit Address Register (Device 1)....................3-53 3.4.19 PMBASE—Prefetchable Memory Base Address Register (Device 1) ......................................................................................3-54 3.4.20 PMLIMIT—Prefetchable Memory Limit Address Register (Device 1) ......................................................................................3-54 3.4.21 BCTRL—PCI-to-PCI Bridge Control Register (Device 1) ..............3-55 vi 82443ZX Host Bridge Datasheet 4 Functional Description ...............................................................................................4-1 4.1 System Address Map....................................................................................4-1 4.1.1 Memory Address Ranges ................................................................4-2 4.1.1.1 Compatibility Area...............................................................4-3 4.1.1.2 Extended Memory Area ......................................................4-4 4.1.1.3 AGP Memory Address Range.............................................4-5 4.1.1.4 AGP DRAM Graphics Aperture...........................................4-6 4.1.1.5 System Management Mode (SMM) Memory Range...........4-6 4.1.2 Memory Shadowing .........................................................................4-8 4.1.3 I/O Address Space...........................................................................4-8 4.1.4 AGP I/O Address Mapping...............................................................4-8 4.1.5 Decode Rules and Cross-Bridge Address Mapping ........................4-9 4.1.5.1 PCI Interface Decode Rules ...............................................4-9 4.1.5.2 AGP Interface Decode Rules ..............................................4-9 4.1.5.3 Legacy VGA Ranges ........................................................4-10 Host Interface..............................................................................................4-10 4.2.1 Host Bus Device Support...............................................................4-10 4.2.2 Symmetric Multiprocessor (SMP) Protocol Support.......................4-13 4.2.3 In-Order Queue Pipelining .............................................................4-13 4.2.4 Frame Buffer Memory Support (USWC) ........................................4-14 DRAM Interface ..........................................................................................4-14 4.3.1 DRAM Organization and Configuration..........................................4-14 4.3.1.1 Configuration Mechanism For DIMMS ..............................4-15 4.3.2 DRAM Address Translation and Decoding ....................................4-16 4.3.3 SDRAMC Register Programming ..................................................4-18 4.3.4 DRAMT Register Programming .....................................................4-19 4.3.5 SDRAM Paging Policy ...................................................................4-19 PCI Interface ...............................................................................................4-20 AGP Interface .............................................................................................4-20 Data Integrity Support .................................................................................4-20 4.6.0.1 Non-ECC (Default Mode of Operation) .............................4-20 4.6.1 CPU Bus Integrity ..........................................................................4-20 4.6.2 PCI Bus Integrity ............................................................................4-20 System Clocking .........................................................................................4-21 Power Management....................................................................................4-21 4.8.1 Overview ........................................................................................4-21 4.8.2 82443ZX Reset ..............................................................................4-23 4.8.2.1 CPU Reset ........................................................................4-24 4.8.2.2 CPU Clock Ratio Straps....................................................4-24 4.8.2.3 82443ZX Straps ................................................................4-24 4.8.3 Clock Control Functions .................................................................4-25 4.8.4 SDRAM Power Down Mode...........................................................4-25 4.8.5 SMRAM..........................................................................................4-25 82443ZX Pinout ............................................................................................5-1 Package Dimensions ....................................................................................5-8 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5 Pinout and Package Information................................................................................5-1 5.1 5.2 82443ZX Host Bridge Datasheet vii Figures 1-1 3-1 3-2 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 Intel® 440ZX AGPset System Block Diagram...............................................1-2 82443ZX PCI Bus Hierarchy.........................................................................3-5 SDRAM DIMMs and Corresponding DRB Registers ..................................3-23 Memory System Address Space ..................................................................4-2 Typical Intel® 440ZX AGPset System Clocking..........................................4-21 Reset CPURST# in a Desktop System When PCIRST# Asserted .............4-24 External Glue Logic Drives CPU Clock Ratio Straps ..................................4-24 82443ZX Pinout (Top View–left side) ...........................................................5-2 82443ZX Pinout (Top View–right side) .........................................................5-3 82443ZX BGA Package Dimensions—Top and Side Views ........................5-8 82443ZX BGA Package Dimensions—Bottom Views ..................................5-9 Tables 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 3-1 3-2 3-3 3-4 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 5-1 5-2 Host Interface Signals...................................................................................2-1 Host Signals Not supported by the 82443ZX................................................2-3 DRAM Interface Signals ...............................................................................2-3 Primary PCI Interface Signals.......................................................................2-5 Primary PCI Sideband Interface Signals ......................................................2-6 AGP Interface Signals ..................................................................................2-7 Clocks, Reset, and Miscellaneous ................................................................2-9 Power Management Interface.......................................................................2-9 Reference Pins ...........................................................................................2-10 Strapping Options .......................................................................................2-11 82443ZX Register Map — Device 0 .............................................................3-8 Attribute Bit Assignment .............................................................................3-21 PAM Registers and Associated Memory Segments ...................................3-21 82443ZX Configuration Space—Device 1 ..................................................3-45 Memory Segments and their Attributes ........................................................4-3 SMRAM Decoding ........................................................................................4-7 SMRAM Range Decode ...............................................................................4-7 SMRAM Decode Control ..............................................................................4-7 Host Bus Transactions Supported By 82443ZX .........................................4-11 Host Responses supported by the 82443ZX ..............................................4-12 Host Special Cycles with 82443ZX .............................................................4-13 Sample Of Possible Mix And Match Options For 4 Row/2 DIMM Configurations ..................................................................................4-15 Data Bytes on DIMM Used for Programming DRAM Registers..................4-16 Supported Memory Configurations .............................................................4-17 MA Muxing vs. DRAM Address Split ..........................................................4-18 Programmable SDRAM Timing Parameters ...............................................4-18 EDO DRAM Timing Parameters .................................................................4-19 Low Power Mode ........................................................................................4-22 AGPset Reset .............................................................................................4-23 Reset Signals..............................................................................................4-23 82443ZX Alphabetical BGA Pin List .............................................................5-4 82443ZX Package Dimensions (492 BGA) ..................................................5-9 viii 82443ZX Host Bridge Datasheet Architectural Overview 1 The Intel® 440ZX AGPset includes the 82443ZX Host Bridge and the 82371EB PIIX4E for the I/O subsystem. The 82443ZX functions and capabilities include: • • • • • • Support for single Pentium II processor configurations 64-bit GTL+ based Host Bus Interface 32-bit Host address Support 64-bit Main Memory Interface with optimized support for SDRAM at 100 and 66/60 MHz 32-bit Primary PCI Bus Interface (PCI) with integrated PCI arbiter AGP Interface (AGP) with 133 MHz data transfer capability configurable as a Secondary PCI Bus • Extensive Data Buffering between all interfaces for high throughput and concurrent operations • Support for 66MHz-only or for 66MHz/100MHz host/DRAM bus frequency Figure 1-1 shows a block diagram of a typical platform based on the Intel® 440ZX AGPset. The 82443ZX host bus interface supports a single Pentium II processor at a host/DRAM bus frequency of 66MHz. Also available is an 82443ZX which supports a host/DRAM bus at 66MHz/100MHz. The physical interface design is based on the GTL+ specification optimized for the desktop. The 82443ZX provides an optimized 64-bit DRAM interface. This interface is implemented as a 3.3Vonly interface that supports only 3V DRAM technology. Two copies of the MA, and CS# signals drive a maximum of two DIMMs each; providing unbuffered high performance at 100 MHz. The 82443ZX provides interface to PCI operating at 33 MHz. This interface implementation is compliant with PCI Rev 2.1 Specification. The 82443ZX AGP interface implementation is based on Rev 1.0 of the AGP Specification. The AGP interface supports 133 MHz data transfer rates and can be used as a Secondary PCI interface operating at 66 MHz/3.3V supporting only a single PCI agent. The 82443ZX is designed to support the PIIX4E I/O bridge. PIIX4E is a highly integrated multifunctional component supporting the following functions and capabilities: • PCI Rev 2.1 compliant PCI-ISA Bridge with support for both 3.3V and 5V 33 MHz PCI operations • • • • Enhanced DMA controller and Interrupt Controller and Timer functions Integrated IDE controller with Ultra DMA/33 support USB host interface with support for 2 USB ports System Management Bus (SMB) with support for DIMM Serial PD 82443ZX Host Bridge Datasheet 1-1 Architectural Overview Figure 1-1. Intel® 440ZX AGPset System Block Diagram Pentium® I I Processor Video - DVD - Camera - VCR Host Bus - VMI - Video Capture 66/100 MHz Graphics Device 2X AGP Bus 82443ZX Host Bridge Main Memory 3.3V EDO & SDRAM Support Display Graphics Local Memory Encoder TV PCI Slots Primary PCI Bus (PCI Bus #0) Video BIOS System MGMT (SM) Bus 2 IDE Ports (Ultra DMA/33) 82371EB (PIIX4E) (PCI-to-ISA Bridge) USB USB ISA Bus System BIOS sys_blk.vsd 2 USB Ports ISA Slots Host Interface The Pentium II processor supports a second level cache via a back-side bus (BSB) interface. All control for the L2 cache is handled by the processor. The 82443ZX provides bus control signals and address paths for transfers between the processors front-side bus (host bus), PCI bus, AGP and main memory. The 82443ZX supports a 4-deep in-order queue (i.e., supports pipelining of up to 4 outstanding transaction requests on the host bus). Due to the system concurrency requirements, along with support for pipelining of address requests from the host bus, the 82443ZX supports request queuing for all three interfaces (Host, AGP and PCI). Host-initiated I/O cycles are decoded to PCI, AGP or PCI configuration space. Host-initiated memory cycles are decoded to PCI, AGP (prefetchable or non-prefetchable memory space) or DRAM (including AGP aperture memory). For memory cycles (host, PCI or AGP initiated) that target the AGP aperture space in DRAM, the 82443ZX translates the address using the AGP address translation table. Other host cycles forwarded to AGP are defined by the AGP address map. 1-2 82443ZX Host Bridge Datasheet Architectural Overview PCI and AGP initiated cycles that target the AGP graphics aperture are also translated using the AGP aperture translation table. AGP-initiated cycles that target the AGP graphics aperture mapped in main memory do not require a snoop cycle on the host bus, since the coherency of data for that particular memory range will be maintained by the software. DRAM Interface The 82443ZX integrates a DRAM controller that supports a 64-bit main memory interface. The DRAM controller supports the following features: • DRAM type: Extended Data Out (EDO) or Synchronous (SDRAM) DRAM controller optimized for dual-bank SDRAM organization on a row by row basis • • • • • Memory Size: 8 MB to 256MB with 4 memory rows (two DIMMs) Addressing Type: Symmetrical and Asymmetrical addressing Memory Modules supported: Single and double density 3.3V DIMMs DRAM device technology: 16 Mbit and 64 Mbit DRAM Speeds: 60 ns for EDO and 100/66 MHz for synchronous memory (SDRAM). The Intel® 440ZX AGPset also provides DIMM plug-and-play support via Serial Presence Detect (SPD) mechanism using the SMBus interface. AGP Interface The 82443ZX AGP implementation is compatible with the following: • The Accelerated Graphics Port Specification, Rev 1.0 • Accelerated Graphics Port Memory Performance Specification, Rev 1.0 (4/12/96) The 82443ZX supports only a synchronous AGP interface coupling to the 82443ZX core frequency. The AGP interface can reach a theoretical ~500 MByte/sec transfer rate (i.e., using 133 MHz AGP compliant devices). PCI Interface The 82443ZX PCI interface is 3.3V (5V tolerant), 33 MHz Rev. 2.1 compliant and supports up to four external PCI bus masters in addition to the I/O bridge (PIIX4/PIIX4E). The PCI-to-DRAM interface can reach over 100 MByte/sec transfer rate for streaming reads and over 120 MBytes/sec for streaming writes. System Clocking The 82443ZX operates the host interface at 66MHz or at 66MHz/100 MHz, the SDRAM/core at 66MHz or at 66MHz/100MHz, PCI at 33 MHz and AGP at 66/133 MHz. 82443ZX Host Bridge Datasheet 1-3 Signal Description Signal Description This chapter provides a detailed description of 443ZX signals. The signals are arranged in functional groups according to their associated interface. 2 The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I O OD I/OD I/O Input pin Output pin Open Drain Output pin. This pin requires a pullup to the VCC of the processor core Input / Open Drain Output pin. This pin requires a pullup to the VCC of the processor core Bi-directional Input/Output pin The signal description also includes the type of buffer used for the particular signal: GTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details PCI AGP PCI bus interface signals. These signals are compliant with the PCI 3.3V and 5.0V Signaling Environment DC and AC Specifications AGP interface signals. These signals are compatible with AGP 3.3V Signaling Environment DC and AC Specifications CMOS The CMOS buffers are Low Voltage TTL compatible signals. These are 3.3V only. 2.1 Host Interface Signals Table 2-1. Host Interface Signals (Sheet 1 of 2) Name Type O GTL+ I/O GTL+ I/O GTL+ Description CPU Reset. The CPURST# pin is an output from the 82443ZX. The 82443ZX generates this signal based on the PCIRST# input (from PIIX4E) and also the SUSTAT# pin in mobile mode. The CPURST# allows the CPUs to begin execution in a known state. Address Bus: A[31:3]# connect to the CPU address bus. During CPU cycles, the A[31:3]# are inputs. Host Data: These signals are connected to the CPU data bus. Note that the data signals are inverted on the CPU bus. CPURST# A[31:3]# HD[63:0]# 82443ZX Host Bridge Datasheet 2-1 Signal Description Table 2-1. Host Interface Signals (Sheet 2 of 2) Name ADS# BNR# Type I/O GTL+ I/O GTL+ O GTL+ O GTL+ I/O GTL+ O GTL+ I/O GTL+ I/O GTL+ I/O GTL+ I GTL+ Description Address Strobe: The CPU bus owner asserts ADS# to indicate the first of two cycles of a request phase. Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to dynamically control the CPU bus pipeline depth. Priority Agent Bus Request: The 82443ZX is the only Priority Agent on the CPU bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Symmetric Agent Bus Request: Asserted by the 82443ZX when CPURST# is asserted to configure the symmetric bus agents. BREQ0# is negated 2 host clocks after CPURST# is negated. Data Bus Busy: Used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: The 82443ZX generates a deferred response as defined by the rules of the 82443ZX’s dynamic defer policy. The 82443ZX also uses the DEFER# signal to indicate a CPU retry response. Data Ready: Asserted for each cycle that data is transferred. Hit: Indicates that a caching agent holds an unmodified version of the requested line. Also driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. Also driven in conjunction with HIT# to extend the snoop window. Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic, i.e. no PCI or AGP snoopable access to DRAM is allowed when HLOCK# is asserted by the CPU. Request Command: Asserted during both clocks of request phase. In the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type. The transactions supported by the 82443ZX Host Bridge are defined in the Host Interface section of this document. Host Target Ready: Indicates that the target of the CPU transaction is able to enter the data transfer phase. Response Signals: Indicates type of response according to the following the table: RS[2:0] 000 001 010 011 100 101 110 111 Response type Idle state Retry response Deferred response Reserved (not driven by 82443ZX) Hard Failure (not driven by 82443ZX) No data response Implicit Writeback Normal data response BPRI# BREQ0# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# I/O GTL+ I/O GTL+ HTRDY# RS[2:0]# I/O GTL+ NOTE: 1. All of the signals in the host interface are described in the CPU External Bus Specification. The preceding table highlights 82443ZX specific uses of these signals. 2-2 82443ZX Host Bridge Datasheet Signal Description Table 2-2 lists the CPU bus interface signals which are NOT supported by the Intel® 440BX AGPset. Table 2-2. Host Signals Not supported by the 82443ZX Signal A[35:32]# AERR# AP[1:0]# BINIT# DEP[7:0]# IERR# INIT# BERR# RP# RSP# Function Address Address Parity Error Address Parity Bus Initialization Data Bus ECC/Parity Internal Error Soft Reset Bus Error Request Parity Response Parity Signal Not Supported By 82443ZX Extended addressing (over 4 GB) Parity protection on address bus Parity protection on address bus Checking for bus protocol violation and protocol recovery mechanism Enhanced data bus integrity Direct internal error observation via IERR# pin Implemented by PIIX4E, BIST supported by external logic. Unrecoverable error without a bus protocol violation Parity protection on ADS# and PREQ[4:0]# Parity protection on RS[2:0]# 2.2 DRAM Interface Table 2-3. DRAM Interface Signals (Sheet 1 of 2) Name RASA[3:0]# /CSA[3:0]# RASB[3:0]# /CSB[3:0]# O CMOS Type Description Row Address Strobe (EDO): These signals are used to latch the row address on the MAxx lines into the DRAMs. Each signal is used to select one DRAM row. These signals drive the DRAM array directly without any external buffers. Chip Select (SDRAM): For the memory row configured with SDRAM these pins perform the function of selecting the particular SDRAM components during the active state. Note that there are 2 copies of RAS# per physical memory row to improve the loading. CKE is used to dynamically power down inactive SDRAM rows. CKE[3:2] O CMOS Note that there are 2 copies of CS# per physical memory row to reduce the loading. Column Address Strobe A-side (EDO): The CASA[7:0]# signals are used to latch the column address on the MA[13:0] lines into the DRAMs of the A half of the memory array. These are active low signals that drive the DRAM array directly without external buffering. Input/Output Data Mask A-side (SDRAM): These pins control the A half of the memory array and act as synchronized output enables during read cycles and as a byte enables during write cycles. CASA[7:0]# /DQMA[7:0] O CMOS 82443ZX Host Bridge Datasheet 2-3 Signal Description Table 2-3. DRAM Interface Signals (Sheet 2 of 2) Name Type Description Global CKE (SDRAM): Global CKE is normally used in an 82443BX 4 DIMM configuration requiring power down mode for the SDRAM. External logic must be used to implement this function in an 82443BX. This function is not supportrd in an 82443ZX. GCKE/CKE1 O CMOS SDRAM Clock Enable (CKE1): In mobile mode, SDRAM Clock Enable is used to signal a self-refresh or power-down command to an SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive SDRAM rows. The combination of SDRAMPWR (SDRAM register) and MMCONFIG (DRAMC register) determine the functioning of the CKE signals. Refer to the DRAMC register (Section 3.3.15, “DRAMC—DRAM Control Register (Device 0)” on page 3-19) for more details. SDRAM Row Address Strobe (SDRAM): The SRAS[A]# signal is a copy of the same logical SRASx signal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals. SDRAM Clock Enable 0 (CKE0). In mobile mode, CKE0 SDRAM Clock Enable is used to signal a self-refresh or power-down command to an SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive SDRAM rows. FET Enable (FENA): In a 4 DIMM configuration. FENA is used to select the proper MD path through the FET switches (refer to Section 4.3, “DRAM Interface” on page 4-14 for more details). This function is not supported in the 82443ZX. SDRAM Column Address Strobe (SDRAM): The SCAS[A]# signal is a copy of the same logical SCASx signal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals. SRAS[A]# O CMOS CKE0/FENA O CMOS SCAS[A]# MAA[13:0] STRAP5 STRAP4 STRAP3 STRAP2 STRAP1 STRAP0 WEA# O CMOS O CMOS Memory Address(EDO/SDRAM): MAA[13:0] are used to provide the row and column address to DRAM. Each MAA[13:0] line has a programmable buffer strength to optimize for different signal loading conditions. STRAP[5:0] are described in Table 2-10, Strapping Options. O CMOS Write Enable Signal (EDO/SDRAM): WE# is asserted during writes to DRAM. The WE# lines have a programmable buffer strength to optimize for different signal loading conditions. Memory Data (EDO/SDRAM): These signals are used to interface to the DRAM data bus. MD [63:0] I/O CMOS 2-4 82443ZX Host Bridge Datasheet Signal Description 2.3 PCI Interface (Primary) Table 2-4. Primary PCI Interface Signals (Sheet 1 of 2) Name Type Description PCI Address/Data: These signals are connected to the PCI address/data bus. Address is driven by the 82443ZX with FRAME# assertion, data is driven or received in the following clocks. When the 82443ZX acts as a target on the PCI Bus, the AD[31:0] signals are inputs and contain the address during the first clock of FRAME# assertion and input data (writes) or output data (reads) on subsequent clocks. Device Select: Device select, when asserted, indicates that a PCI target device has decoded its address as the target of the current access. The 82443ZX asserts DEVSEL# based on the DRAM address range or AGP address range being accessed by a PCI initiator. As an input it indicates whether any device on the bus has been selected. Frame: FRAME# is an output when the 82443ZX acts as an initiator on the PCI Bus. FRAME# is asserted by the 82443ZX to indicate the beginning and duration of an access. The 82443ZX asserts FRAME# to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is negated, the transaction is in the final data phase. FRAME# is an input when the 82443ZX acts as a PCI target. As a PCI target, the 82443ZX latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which it samples FRAME# active. Initiator Ready: IRDY# is an output when 82443ZX acts as a PCI initiator and an input when the 82443ZX acts as a PCI target. The assertion of IRDY# indicates the current PCI Bus initiator's ability to complete the current data phase of the transaction. Command/Byte Enable: PCI Bus Command and Byte Enable signals are multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as byte enables. The byte enables determine which byte lanes carry meaningful data. PCI Bus command encoding and types are listed below. C/BE[3:0]# 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Reserved (Dual Address Cycle) Memory Read Line Memory Write and Invalidate AD[31:0] I/O PCI DEVSEL# I/O PCI FRAME# I/O PCI IRDY# I/O PCI C/BE[3:0]# I/O PCI PAR I/O PCI Parity: PAR is driven by the 82443ZX when it acts as a PCI initiator during address and data phases for a write cycle, and during the address phase for a read cycle. PAR is driven by the 82443ZX when it acts as a PCI target during each data phase of a PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#. Lock: PLOCK# indicates an exclusive bus operation and may require multiple transactions to complete. When PLOCK# is asserted, non-exclusive transactions may proceed. The 82443ZX supports lock for CPU initiated cycles only. PCI initiated locked cycles are not supported. Target Ready: TRDY# is an input when the 82443ZX acts as a PCI initiator and an output when the 82443ZX acts as a PCI target. The assertion of TRDY# indicates the target agent's ability to complete the current data phase of the transaction. PLOCK# I/O PCI I/O PCI TRDY# 82443ZX Host Bridge Datasheet 2-5 Signal Description Table 2-4. Primary PCI Interface Signals (Sheet 2 of 2) Name Type Description System Error: The 82443ZX asserts this signal to indicate an error condition. The SERR# assertion by the 82443ZX is enabled globally via SERRE bit of the PCICMD register. SERR# is asserted under the following conditions: In an ECC configuration, the 82443ZX asserts SERR#, for single bit (correctable) ECC errors or multiple bit (non-correctable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any ECC errors received during initialization should be ignored. • The 82443ZX asserts SERR# for one clock when it detects a target abort during 82443ZX initiated PCI cycle. I/O PCI • The 82443ZX can also assert SERR# when a PCI parity error occurs during the address or data phase. • The 82443ZX can assert SERR# when it detects a PCI address or data parity error on AGP. • The 82443ZX can assert SERR# upon detection of access to an invalid entry in the Graphics Aperture Translation Table. • The 82443ZX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture and outside of main DRAM range (i.e. in the 640k - 1M range or above TOM). • The 82443ZX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture. • The 82443ZX asserts SERR# for one clock when it detects a target abort during 82443ZX initiated AGP cycle. STOP# I/O PCI Stop: STOP# is an input when the 82443ZX acts as a PCI initiator and an output when the 82443ZX acts as a PCI target. STOP# is used for disconnect, retry, and abort sequences on the PCI Bus. SERR# NOTE: 1. All PCI interface signals conform to the PCI Rev 2.1 specification. 2.4 Primary PCI Sideband Interface Table 2-5. Primary PCI Sideband Interface Signals Name Type I PCI O PCI I PCI O PCI Description PCI Hold: This signal comes from the PIIX4E. It is the PIIX4E request for PCI bus ownership. The 82443ZX will flush and disable the CPU-to-PCI write buffers before granting the PIIX4E the PCI bus via PHLDA#. This prevents bus deadlock between PCI and ISA. PCI Hold Acknowledge: This signal is driven by the 82443ZX to grant PCI bus ownership to the PIIX4E after CPU-PCI post buffers have been flushed and disabled. PCI Bus Request: PREQ[3:0]# are the PCI bus request signals used as inputs by the internal PCI arbiter. PCI Grant: PGNT[3:0]# are the PCI bus grant output signals generated by the internal PCI arbiter. PHOLD# PHLDA# PREQ[3:0]# PGNT[3:0]# 2-6 82443ZX Host Bridge Datasheet Signal Description 2.5 AGP Interface Signals There are 17 new signals added to the normal PCI group of signals that together constitute the AGP interface. The sections below describe their operation and use, and are organized in five groups: • • • • • AGP Addressing Signals AGP Flow Control Signals AGP Status Signals AGP Clocking Signals - Strobes PCI Signals Table 2-6. AGP Interface Signals (Sheet 1 of 2) Name Type Description AGP Sideband Addressing Signals1 Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be queued by the target. The master queues one request each rising clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are queued across the AD bus. PIPE# is a sustained tri-state signal from masters (graphics controller) and is an input to the 82443ZX. Note that initial AGP designs may not use PIPE#. Sideband Address: This bus provides an additional bus to pass address and command to the 82443ZX from the AGP master. Note that, when sideband addressing is disabled, these signals are isolated (no external/internal pull-ups are required). AGP Flow Control Signals Read Buffer Full. This signal indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted the 82443ZX is not allowed to return low priority read data to the AGP master on the first block. RBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data then it is not required to implement this signal. AGP Status Signals Status Bus: This bus provides information from the arbiter to a AGP Master on what it may do. ST[2:0] only have meaning to the master when its GGNT# is asserted. When GGNT# is deasserted these signals have no meaning and must be ignored. 000 Indicates that previously requested low priority read data is being returned to the master. 001 Indicates that previously requested high priority read data is being returned to the master. O AGP 010 Indicates that the master is to provide low priority write data for a previously queued write command. 011 Indicates that the master is to provide high priority write data for a previously queued write command. PIPE# I AGP SBA[7:0] I AGP RBF# I AGP ST[2:0] 100 Reserved 101 Reserved 110 Reserved 111 Indicates that the master has been given permission to start a bus transaction. The master may queue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME#. ST[2:0] are always an output from the 82443ZX and an input to the master. 82443ZX Host Bridge Datasheet 2-7 Signal Description Table 2-6. AGP Interface Signals (Sheet 2 of 2) Name Type Description AGP Clocking Signals - Strobes ADSTB_A I/O AGP I/O AGP I AGP AD Bus Strobe A: This signal provides timing for double clocked data on the AD bus. The agent that is providing data drives this signal. This signal requires an 8.2K ohm external pull-up resistor. AD Bus Strobe B: This signal is an additional copy of the AD_STBA signal. This signal requires an 8.2K ohm external pull-up resistor. Sideband Strobe: THis signal provides timing for a side-band bus. This signal requires an 8.2K ohm external pull-up resistor. AGP FRAME# Protocol SIgnals (similar to PCI) 2 GFRAME# I/O AGP Graphics Frame: Same as PCI. Not used by AGP. GFRAME# remains deasserted by its own pull up resistor. Graphics Initiator Ready: New meaning. GIRDY# indicates the AGP compliant master is ready to provide all write data for the current transaction. Once IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The assertion of IRDY# for reads indicates that the master is ready to transfer to a subsequent block (32 bytes) of read data. The master is never allowed to insert wait states during the initial data transfer (32 bytes) of a read transaction. However, it may insert wait states after each 32 byte block is transferred. ADSTB_B SBSTB GIRDY# I/O AGP (There is no GFRAME# -- GIRDY# relationship for AGP transactions.) Graphics Target Ready: New meaning. GTRDY# indicates the AGP compliant target is ready to provide read data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on both read and write transactions. Graphics Stop: Same as PCI. Not used by AGP. Graphics Device Select: Same as PCI. Not used by AGP. Graphics Request: Same as PCI. (Used to request access to the bus to initiate a PCI or AGP request.) Graphics Grant: Same meaning as PCI but additional information is provided on ST[2:0]. The additional information indicates that the selected master is the recipient of previously requested read data (high or normal priority), it is to provide write data (high or normal priority), for a previously queued write command or has been given permission to start a bus transaction (AGP or PCI). Graphics Address/Data: Same as PCI. Graphics Command/Byte Enables: Slightly different meaning. Provides command information (different commands than PCI) when requests are being queued when using PIPE#. Provide valid byte information during AGP write transactions and are not used during the return of read data. Graphics Parity: Same as PCI. Not used on AGP transactions, but used during PCI transactions as defined by the PCI specification. GTRDY# I/O AGP GSTOP# GDEVSEL# GREQ# I/O AGP I/O AGP I AGP O AGP I/O AGP I/O AGP I/O AGP GGNT# GAD[31:0] GC/BE[3:0]# GPAR NOTE: 1. AGP Sideband Addressing Signals. The above table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset. 2-8 82443ZX Host Bridge Datasheet Signal Description 2. PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For transactions on the AGP interface carried using PCI protocol these signals completely preserve PCI semantics. The exact role of all PCI signals during AGP transactions is in Table 2-6. 3. The LOCK# signal is not supported on the AGP interface (even for PCI operations). 4. PCI signals described in Table 2-4 behave according to PCI 2.1 specifications when used to perform PCI transactions on the AGP Interface. 2.6 Clocks, Reset, and Miscellaneous Table 2-7. Clocks, Reset, and Miscellaneous Name HCLKIN Type I CMOS I CMOS O CMOS I CMOS I CMOS I CMOS O CMOS O CMOS I CMOS PCI Clock In: This is a buffered PCI clock reference that is synchronously derived by an external clock synthesizer component from the host clock. This clock is used by all of the 82443ZX logic that is in the PCI clock domain. . DCLKO SDRAM Clock Out: 66 or 100 MHz SDRAM clock reference. It feeds an external buffer clock device that produces multiple copies for the DIMMs. SDRAM Write Clock: Feedback reference from the external SDRAM clock buffer. This clock is used by the 82443ZX when writing data to the SDRAM array. Note: See the Design Guide for routing constraints. PCI Reset: When asserted, this signal will reset the 82443ZX logic. All PCI output and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1 specifications. AGP Clock In: The GCLKIN input is a feedback reference from the GCLKOUT signal. AGP Clock Out: The frequency is 66 MHz. The GCLKOUT output is used to feed both the reference input pin on the 82443ZX and the AGP compliant device. Delayed CPU Reset: CRESET# is a delayed copy of CPURST#. This signal is used to control the multiplexer for the CPU strap signals. CRESET# is delayed from CPURST# by two host clocks. Note: This pin requires an external pull-up resistor. If not used, no pull up is required. TESTIN# Test Input: This pin is used for manufacturing, and board level test purposes. Note: This pin has an internal 50K ohm pull-up. Description Host Clock In: This pin receives a buffered host clock. This clock is used by all of the 82443ZX logic that is in the Host clock domain. PCLKIN DCLKWR PCIRST# GCLKIN GCLKO CRESET# Table 2-8. Power Management Interface Name Type Description Primary PCI Clock Run: The 82443ZX requests the central resource (PIIX4E) to start or maintain the PCI clock by the assertion of CLKRUN#. The 82443ZX tristates CLKRUN# upon deassertion of PCIRST# (since CLK is running upon deassertion of reset). If connected to PIIX4E an external 2.7K Ohm pull-up is required for Desktop, Mobile requires (8.2k–10K) pull-up. Otherwise, a 100 Ohm pull down is required. BX Power OK: BXPWROK input must be connected to the PWROK signal that indicates valid power is applied to the 82443ZX. CLKRUN# I/OD CMOS I CMOS BXPWROK 82443ZX Host Bridge Datasheet 2-9 Signal Description Table 2-9. Reference Pins Name GTLREF[B:A] VTT[B:A] VCC VSS REF5V AGPREF GTL Buffer voltage reference input GTL Threshold voltage for early clamps Power pin @ 3.3V Ground PCI 5V reference voltage (for 5V tolerant buffers) External Input Reference Description 2.7 Power-Up/Reset Strap Options Table 2-10 is the list of all power-up options that are loaded into the 82443ZX during cold reset. The 82443ZX is required to float all the signals connected to straps during cold reset and keep them floated for a minimum of 4 host clocks after the end of cold reset sequence. Cold reset sequence is performed when the 82443ZX power is applied. Note: All signals used to select power-up strap options are connected to either internal pull-down or pullup resistors of minimum 50K ohms (maximum is 150K). That selects a default mode on the signal during reset. To enable different modes, external pull ups or pull downs (the opposite of the internal resistor) of approximately 10K ohm can be connected to particular signals. These pull up or pull down resistors should be connected to the 3.3V power supply. During normal operation of the 82443ZX, the paths from GND or Vcc to internal strapping resistors are disabled to effectively disable the resistors. In these cases, the STRAPx lines are driven by the 82443ZX to a valid voltage levels. Note: Note that when resuming from suspend, even while PCIRST# is active, the STRAPx lines remain driven by the 82443ZX and the strapping latches maintain the value stored during the cold reset. This first column in Table 2-10 lists the signal that is sampled to obtain the strapping option. The second column shows which register the strapping option is loaded into. The third column is a description of what functionality the strapping selects. The GTL+ signals are connected to the VTT through the normal pull-ups. CPU bus straps controlled by the 82443ZX (e.g. A7# and A15#), are driven active at least six clocks prior to the active-to-inactive edge of CPURST# and driven inactive four clocks after the active-to-inactive edge of the CPURST#. 2-10 82443ZX Host Bridge Datasheet Signal Description Table 2-10. Strapping Options Signal MAB13# STRAP5 NBXCFG[13] Register Name[bit] Reserved. Host Frequency Select: If STRAP5 is strapped to 0, the host bus frequency is 60/ 66 MHz. If STRAP5 is strapped to 1, the host bus frequency is 100 MHz. An internal pull-down is used to provide the default setting of 66 MHz. In-Order Queue Depth Enable. If STRAP4 is strapped to 0 during the rising edge of PCIRST#, then the 82442BX will drive A7# low during the CPURST# deassertion. This forces the CPU bus to be configured for non-pipelined operation. STRAP4 NBXCFG[2] If STRAP4 is strapped to 1 (default), then the 82443ZX does not drive the A7# low during reset, and A7# is sampled in default non-driven state (i.e. pulled-up as far as GTL+ termination is concerned) then the maximum allowable queue depth by the CPU bus protocol is selected (i.e., 8). Note that internal pull-up is used to provide pipelined bus mode as a default. Quick Start Select. The value on this pin at reset determines which stop clock mode is used. STRAP3 PMCR[3] STRAP3 = 0 (default) for normal stop clock mode. If STRAP3 = 1 during the rising edge of PCIRST#, then the 82443ZX will drive A15# low during CPURST# deassertion. This will configure the CPU for Quick Start mode of operation. Note that internal pull-down is used to provide normal stop clock mode as a default. AGP Disable: When strapped to a 1, the AGP interface is disabled, all AGP signals are tri-stated and isolated. When strapped to a 0 (default), the AGP interface is enabled. STRAP2 PMCR[1] When MMCONFIG is strapped active, we require that AGP_DISABLE is also strapped active. When MMCONFIG is strapped inactive, AGP_DISABLE can be strapped active or inactive but IDSEL_REDIRECT (bit 16 in NBXCFG register) must never be activated. This signal has an internal pull-down resistor. MAB8# Reserved. Memory Module Configuration, MMCONFIG: When strapped to a 1, the 82443ZX configures its DRAM interface in a 430-TX compatible manner. These unused inputs are isolated while unused outputs are tri-stated: RASB[3:0]#/ CSB[3:0]#, CKE[3:2], GCKE/CKE1, MAA[13:0], DCLKO. STRAP1 DRAMC[5] When strapped to a 0 (default), the 82443ZX DRAM signal are used normally. IDSEL_REDIRECT (bit 16 in NBXCFG register) is programmed by BIOS, before it begins with device enumeration process. The combination of SDRAMPWR (SDRAMC register) and MMCONFIG (DRAMC register) determine the functioning of the CKE signals. Refer to the DRAMC register for more details. Note that internal pull-down is used to set the DRAM interface to a normal configuration, as a default. Host Bus Buffer Mode Select: When strapped 0, the desktop GTL+ 66 MHz or 100 MHz host bus buffers are used (default). STRAP0 none When strapped ‘1’, the mobile Low Power GTL+ 66 MHz host bus buffers are selected. Note that an internal pull-down is used to set the host bus buffers to a desktop configuration as a default in the 82443ZX. An external pull-up therefore is needed for mobile systems using the 82443BX or 82443DX. A[15]# A7# none none Quick Start Select. The value on A15# sampled at the rising edge of CPURST# will reflect if the quick start/stop clock mode is enabled in the processors. In-order Queue Depth Status. The value on A[7]# sampled at the rising edge of CPURST# reflects if the IOQD is set to 1 or maximum allowable by the CPU bus. Description NOTE: 1. Proper strapping must be used to define logical values for these signals. Default value “0”, or “1” provided by the internal pull-up or pull-down resistor can be overridden by the external pull-up, or pull-down resistor. 82443ZX Host Bridge Datasheet 2-11 Register Description Register Description 3 The 82443ZX contains two sets of software accessible registers, accessed via the Host CPU I/O address space: 1. Control registers that are I/O mapped into the CPU I/O space. These registers control access to PCI and AGP configuration space. 2. Internal configuration registers residing within the 82443ZX, partitioned into two logical device register sets (“logical” since they reside within a single physical device). The first register set is dedicated to Host-to-PCI Bridge functionality. This set (device 0) controls PCI interface operations, DRAM configuration, and other chip-set operating parameters and optional features. The second register set (device 1) is dedicated to Host-to-AGP Bridge functions (controls AGP interface configurations and operating parameters). The following nomenclature is used for register access attributes. RO R/W R/WC Read Only. If a register is read only, writes to this register have no effect. Read/Write. A register with this attribute can be read and written Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. Read/Write Once. A register bit with this attribute can be written to only once after power up. After the first write, the bit becomes read only. Read/Write/Lock. This register includes a lock bit. Once the lock bit has been set to 1, the register becomes read only. R/WO R/WL The 82443ZX supports PCI configuration space access using the mechanism denoted as Configuration Mechanism #1 in the PCI specification. The 82443ZX internal registers (both I/O Mapped and Configuration registers) are accessible by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of CONFADD which can only be accessed as a Dword. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field). Some of the 82443ZX registers described in this section contain reserved bits. These bits are labeled "Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note: Software does not need to perform read, merge, write operation for the configuration address register. In addition to reserved bits within a register, the 82443ZX contains address locations in the configuration space of the Host-to-PCI Bridge entity that are marked either "Reserved" or “Intel Reserved”. The 82443ZX responds to accesses to “Reserved” address locations by completing the host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Writes to “Reserved” registers have no effect on the 82443ZX Host Bridge Datasheet 3-1 Register Description 82443ZX. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel Reserved” registers may return a non-zero value. Software should not write to reserved configuration locations in the device-specific region (above address offset 3Fh) Upon reset, the 82443ZX sets its internal configuration registers to predetermined default states. However, there are a few exceptions to this rule. 1. When a reset occurs during the POS/STR state, several configuration bits are not reset to their default state. These bits are noted in the following register description. 2. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the 82443ZX registers accordingly. 3.1 I/O Mapped Registers The 82443ZX contains three registers that reside in the CPU I/O address space − the Configuration Address (CONFADD) Register, the Configuration Data (CONFDATA) Register, and the Power Management Control Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window. 3.1.1 CONFADD—Configuration Address Register I/O Address: Default Value: Access: Size: 0CF8h Accessed as a Dword 00000000h Read/Write 32 bits CONFADD is a 32 bit register accessed only when referenced as a Dword. A Byte or Word reference will "pass through" the Configuration Address Register onto the PCI bus as an I/O cycle. The CONFADD register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended. 3-2 82443ZX Host Bridge Datasheet Register Description Bit 31 30:24 Descriptions Configuration Enable (CFGE). When this bit is set to 1 accesses to PCI configuration space are enabled. If this bit is reset to 0 accesses to PCI configuration space are disabled. Reserved. Bus Number. When the Bus Number is programmed to 00h the target of the Configuration Cycle is either the 82443ZX or the PCI Bus that is directly connected to the 82443ZX, depending on the Device Number field. A type 0 Configuration Cycle is generated on PCI if the Bus Number is programmed to 00h and the 82443ZX is not the target. If the Bus Number is non-zero a type 1 configuration cycle is generated on PCI or AGP with the Bus Number mapped to AD[23:16] during the address phase. Device Number. This field selects one agent on the PCI bus selected by the Bus Number. During a Type 1 Configuration cycle this field is mapped to AD[15:11]. During a Type 0 Configuration Cycle this field is decoded and one bit among AD[31:11] is driven to a 1. The 82443ZX is always Device Number 0 for the Host-to-PCI bridge entity and Device Number 1 for the Host- AGP entity. Therefore, the 82443ZX internally references the AD11 and AD12 pins as corresponding IDSELs for the respective devices during PCI configuration cycles. NOTE: The AD11 and AD12 must not be connected to any other PCI bus device as IDSEL signals. Function Number. This field is mapped to AD[10:8] during PCIx configuration cycles. This allows the configuration registers of a particular function in a multi-function device to be accessed. The 82443ZX only responds to configuration cycles with a function number of 000b; all other function number values attempting access to the 82443ZX (Device Number = 0 and 1, Bus Number = 0) will generate a master abort. Register Number. This field selects one register within a particular Bus, Device, and Function as specified by the other fields in the Configuration Address Register. This field is mapped to AD[7:2] during PCI configuration cycles. Reserved. 23:16 15:11 10:8 7:2 1:0 3.1.2 CONFDATA—Configuration Data Register I/O Address: Default Value: Access: Size: 0CFCh 00000000h Read/Write 32 bits CONFDATA is a 32 bit read/write window into configuration space. The portion of configuration space that is referenced by CONFDATA is determined by the contents of CONFADD. Bit 31:0 Descriptions Configuration Data Window (CDW). If bit 31 of CONFADD is 1 any I/O reference that falls in the CONFDATA I/O space will be mapped to configuration space using the contents of CONFADD. 82443ZX Host Bridge Datasheet 3-3 Register Description 3.1.3 PM2_CTL—ACPI Power Control 2 Control Register I/O Address: Default Value: Access: Size: 0022h 00h Read/Write 8 bits This register is used to disable both the PCI and AGP arbiters in the 82443ZX to prevent any external bus masters from acquiring the PCI or AGP bus. Any currently running PCI cycles will terminate properly. Accesses to this register are controlled by the Power Management Control Register (Offset 7Ah). When bit 6 of the PMCR is set to ‘1’, the ACPI Register at I/O location 0022h is enabled. When bit 6 is set to ‘0’, I/O accesses to location 0022h are forwarded to PCI or AGP (if within programmable IO range). Bit 7:1 Reserved Primary PCI and AGP Arbiter Request Disable (ARB_DIS). When this bit is set to 1, the 82443ZX will not respond to any PCI REQ# signals, AGP requests, or PHOLD# from PIIX4E going active until this bit is set back to 0. Only External AGP and PCI requests are masked from the arbiters. If the PIIX is in passive release mode, masking will not occur until an active release is seen via PHLDA# assertion. This prevents possible deadlock. ARB_DIS has no effect on AGP side band signals or AGP data transfer requests. Description 0 3.2 PCI Configuration Space Access The 82443ZX implementation manifests two PCI devices within a single physical component body: • Device 0 = Host-to-PCI Bridge = PCI bus #0 interface, Main Memory Controller, Graphics Aperture controller, 82443ZX specific AGP control registers. • Device 1 = Host-to-AGP interface = “Virtual” PCI-to-PCI Bridge, including AGP address space mapping, normal PCI interface, and associated AGP sideband signal control. Corresponding configuration registers for both devices are mapped as devices residing on PCI (bus 0). Configuration register layout and functionality for the Device #0 should be inspected carefully, as new features added to the 82443ZX initiated a reasonable level of change relative to other proliferation’s of the Pentium® Pro processor AGPsets (i.e. 440FX, 440LX). Configuration registers of the 82443ZX Device #1 are based on the normal configuration space template of a PCIto-PCI Bridge as described in the PCI to PCI Bridge Architecture Specification. Figure 3-1shows the PCI bus hierarchy for the 82443ZX). In the PCI bus hierarchy, the primary PCI bus is the highest level bus in the hierarchy and is PCI bus #0. The PCI-to-PCI bridge function provides access to the AGP/PCI bus 0. This bus is below the primary bus in the PCI bus hierarchy and is represented as PCI Bus #1. 3-4 82443ZX Host Bridge Datasheet Register Description Figure 3-1. 82443ZX PCI Bus Hierarchy CPU 82443ZX Host Bridge Host-to-PCI Bridge PCI Bus #0 Virtual Host-to-PCI Bridge AGP Device PCI Bus #1 – AGP 3.2.1 Configuration Space Mechanism Overview The 82443ZX supports two bus interfaces: PCI (referenced as Primary PCI) and AGP (referenced as AGP). The AGP interface is treated as a second PCI bus from the configuration point of view. The following sections describe the configuration space mapping mechanism associated with both buses. Note: The configuration space for device #1 is controlled by the AGP_DIS bit in the PMCR register. When the AGP_DIS bit (PMCR[1]) is set to 0, the configuration space for device #1 is enabled, and the registers for device #1 are accessible through the configuration mechanism defined below. When the AGP_DIS bit (PMCR[1]) is set to 1, the configuration space for device #1 is disabled. All configuration cycles (reads and writes) to device #1 of bus 0 will cause the master abort status bit for device #0/ bus 0 to be set. Configuration read cycles will return data of all 1’s. Configuration write cycles will have no effect on the registers. 3.2.2 Routing the Configuration Accesses to PCI or AGP Routing of configuration accesses to AGP is controlled via PCI-to-PCI bridge normal mechanism using information contained within the PRIMARY BUS NUMBER, the SECONDARY BUS NUMBER, and the SUBORDINATE BUS NUMBER registers of the Host-to-AGP internal “virtual” PCI-to-PCI bridge device. Detailed description of the mechanism for translating CPU I/O bus cycles to configuration cycles on one of the two buses is described below. To distinguish between PCI configuration cycles targeting the two logical device register sets supported in the 82443ZX, this document refers to the Host-to-PCI bridge PCI interface as PCI and the Host- AGP PCI interface as AGP. 82443ZX Host Bridge Datasheet 3-5 Register Description 3.2.3 PCI Bus Configuration Mechanism Overview The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the CPU. Configuration space is supported by a mapping mechanism implemented within the chip-set. The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The 82443ZX supports only Mechanism #1. The configuration access mechanism makes use of the CONFADD Register and CONFDATA Register. To reference a configuration register a Dword I/O write cycle is used to place a value into CONFADD that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONFADD[31] must be 1 to enable a configuration cycle. CONFDATA then becomes a window into the four bytes of configuration space specified by the contents of CONFADD. Any read or write to CONFDATA will result in the Host Bridge translating CONFADD into a PCI configuration cycle. 3.2.3.1 Type 0 Access If the Bus Number field of CONFADD is 0, a Type 0 Configuration cycle is performed on PCI (i.e. bus #0). CONFADD[10:2] is mapped directly to AD[10:2]. The Device Number field of CONFADD is decoded onto AD[31:11]. The Host-to-PCI Bridge entity within the 82443ZX is accessed as Device #0 on the PCI bus segment. The Host- /AGP Bridge entity within the 82443ZX is accessed as Device #1 on the PCI bus segment. To access Device #2, the 82443ZX will assert AD13, for Device #3 will assert AD14, and so forth up to Device #20 for which will assert AD31. Only one AD line is asserted at a time. All device numbers higher than 20 cause a type 0 configuration access with no IDSEL asserted, which will result in a Master Abort. 3.2.3.2 Type 1 Access If the Bus Number field of CONFADD is non-zero, then a Type 1 Configuration cycle is performed on PCI bus (i.e. bus #0). CONFADD[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to 01 to indicate a Type 1 Configuration cycle. All other lines are driven to 0. 3.2.4 AGP Bus Configuration Mechanism Overview This mechanism is compatible with PCI mechanism #1 supported for the PCI bus as defined above. The configuration mechanism is the same for both accessing AGP or PCI-only devices attached to the AGP interface. 3-6 82443ZX Host Bridge Datasheet Register Description 3.2.5 Mapping of Configuration Cycles on AGP From the AGPset configuration perspective, AGP is seen as another PCI bus interface residing on a Secondary Bus side of the “virtual” PCI-to-PCI bridge referred to as the 82443ZX Host- AGP bridge. On the Primary bus side, the “virtual” PCI-to-PCI bridge is attached to the BUS #0 referred to in this document as the PCI interface. The “virtual” PCI-to-PCI bridge entity is used to map Type #1 PCI Bus Configuration cycles on PCI onto Type #0 or Type #1 configuration cycles on the AGP interface. Type 1 configuration cycles on PCI that have a BUS-NUMBER that matches the SECONDARYBUS-NUMBER of the “virtual” PCI to PCI bridge will be translated into Type 0 configuration cycles on the AGP interface. Type 1 configuration cycles on PCI that have a BUS-NUMBER that is behind the “virtual” P2P bridge will be translated into Type 1 configuration cycles on the AGP interface. Note: The PCI bus supports a total of 21 devices by mapping bits 15:11 of the CONFADD to the IDSEL lines on AD[31:11]. For secondary PCI busses (including the AGP bus), only 16 devices are supported by mapping bits 15:11 of the CONFADD to the IDSEL lines (AD[31:16]). To prepare for mapping of the configuration cycles on AGP the initialization software will go through the following sequence: 1. Scan all devices residing on the PCI bus (i.e., Bus #0) using Type 0 configuration accesses. 2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. This process will include the configuration of the “virtual” PCI-to-PCI Bridge within the 82443ZX used to map the AGP address space in a software specific manner. 82443ZX Host Bridge Datasheet 3-7 Register Description 3.3 Host-to-PCI Bridge Registers (Device 0) Table 3-1 shows the 82443ZX configuration space for device #0. Table 3-1. 82443ZX Register Map — Device 0 (Sheet 1 of 2) Address Offset 00–01h 02–03h 04–05h 06–07h 08 09 0Ah 0Bh 0Ch 0Dh 0Eh 10–13h 14–2Bh 2C–2Dh 2E–2Fh 30–33h 34h 35–4Fh 50–53h 54–56h 57h 58h 59–5Fh 60–67h 68h 69–6Eh 6F–70h 71h 72h 73h 74–75h 76–77h 78–79h 7Ah 7B–7Ch 7D–7Fh Register Symbol VID DID PCICMD PCISTS RID — SUBC BCC — MLT HDR APBASE — SVID SID — CAPPTR — NBXCFG — DRAMC DRAMT PAM[6:0] DRB[7:0] FDHC MBSC — — SMRAM ESMRAMC RPS SDRAMC PGPOL PMCR SCRR — Register Name Vendor Identification Device Identification PCI Command Register PCI Status Register Revision Identification Reserved Sub-Class Code Base Class Code Reserved Master Latency Timer Header Type Aperture Base Address Reserved Subsystem Vendor Identification Subsystem Identification Reserved Capabilities Pointer Reserved 440BX Configuration Reserved DRAM Control DRAM Timing Programmable Attribute Map (7 registers) DRAM Row Boundary (8 registers) Fixed DRAM Hole Control Memory Buffer Strength Control Reserved Intel Reserved System Management RAM Control Extended System Management RAM Control. SDRAM Row Page Size SDRAM Control Register Paging Policy Register Power Management Control Register Suspend CBR Refresh Rate Register Reserved Default Value 8086h 7190h/7192h 0006h 0210h/0200h 00/01h/02h 00h 00h 06h 00h 00h 00h 00000008h 00h 00h 00h 00h A0h/00h 00h [0000h]:[00S0_00 00_000S_0S00b] 00h 00S0_0000b 03h 00h 01h 00h 0000-0000-0000h 00h 1Fh 02h 38h 0000h 0000h 00h 0000_S0S0b 0038h 00h Access RO RO R/W RO, R/WC RO — RO RO — R/W RO R/W,RO — R/WO R/WO — RO — R/W — R/W R/W R/W R/W R/W R/W — — R/W R/W R/W R/W R/W R/W R/W — 3-8 82443ZX Host Bridge Datasheet Register Description Table 3-1. 82443ZX Register Map — Device 0 (Sheet 2 of 2) Address Offset 80–83h 84–8Fh 90h 91–92h 93h 94–97h 98–99h 9Ah 9B–9Fh A0–A3h A4–A7h A8–ABh AC–AFh B0–B3h B4h B5–B7h B8–BBh BCh BDh BE–BFh C0–C3h C4–C7h C8h C9h CA–CCh CD–CFh D0–D7h D8–DFh E0–E7h E8–EFh F0–F1h F2–F7h F8–FBh FC–FFh NOTES: DWTC DRTC BUFFC — — — Register Symbol EAP — ERRCMD ERRSTS — — — — — ACAPID AGPSTAT AGPCMD — AGPCTRL APSIZE — ATTBASE — — — — — — — MBFS — BSPAD Register Name Error Address Pointer Register Reserved Error Command Register Error Status Register Reserved Intel Reserved Intel Reserved Intel Reserved Reserved AGP Capability Identifier AGP Status Register AGP Command Register Reserved AGP Control Register) Aperture Size Control Register Reserved Aperture Translation Table Reserved Reserved Reserved Intel Reserved Intel Reserved Intel Reserved Intel Reserved Memory Buffer Frequency Select Reserved BIOS Scratch Pad Intel Reserved DRAM Write Thermal Throttling Control DRAM Read Thermal Throttling Control Buffer Control Register Intel Reserved Intel Reserved Intel Reserved Default Value 00000000h 00h 80h 0000h 00h 00006104h 0500h 00h — 00100002h 00000000h 1F000203h 00000000h 00h 00000000h 00h 00h 00000000h — — 00h 00000000h 00000000h 18h 0Ch 000000h 00h 00...00h 000....000h 000....000h 000....000h 0000h 0000F800h 00000F20h 00000000h Access RO, R/WC — R/W R/WC, RO R/W — — — — RO RO RW — R/W R/W — R/W — — — — — — — R/W — R/W — R/W/L R/W/L R/W/L — — — 1. The ‘S’ symbol represents the strapping option. 2. Write operations must not be attempted to the Intel Reserved registers. 82443ZX Host Bridge Datasheet 3-9 Register Description 3.3.1 VID—Vendor Identification Register (Device 0) Address Offset: Default Value: Attribute: Size: 00–01h 8086h Read Only 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 Description Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 3.3.2 DID—Device Identification Register (Device 0) Address Offset: Default Value: Attribute: Size: 02–03h 7190h/7192h Read Only 16 bits This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect. Bit Description Device Identification Number. This is a 16 bit value assigned to the 82443ZX Host-to-PCI Bridge Function #0. 15:0 7190h = When the AGP_DIS bit (PMCR[1]) is set to 0, the DID =7190h. 7192h = When the AGP_DIS bit is set to 1, the DID = 7192h. 3-10 82443ZX Host Bridge Datasheet Register Description 3.3.3 PCICMD—PCI Command Register (Device 0) Address Offset: Default: Access: Size 04–05h 0006h Read/Write 16 bits This 16-bit register provides basic control over the 82443ZX PCI interface ability to respond to PCI cycles. The PCICMD Register enables and disables the SERR# signal, 82443ZX response to PCI special cycles, and enables and disables PCI bus master accesses to main memory. Bit 15:10 9 Reserved. Fast Back-to-Back. Fast back-to-back cycles to different PCI targets are not implemented by the 82443ZX. 0 = Hardwired to 0. SERR# Enable (SERRE). Note that this bit only controls SERR# for the PCI bus. Device #1 has its own SERRE bit to control error reporting for the bus conditions occurred on the AGP bus. Two control bits are used in a logical OR manner to control SERR# pin driver. 8 1 = If this bit is set to a 1, the 82443ZX’s SERR# signal driver is enabled and SERR# is asserted when an error condition occurs, and the corresponding bit is enabled in the ERRCMD register. The error status is reported in the ERRSTS and PCISTS registers. Also, if this bit is set and the 82443ZX’s PCI parity error reporting is enabled by the PERRE bit located in this register, then the 82443ZX will report address and data parity errors (when it is potential target). 0 = SERR# is never driven by the 82443ZX. 7 Address/Data Stepping. Not implemented (hardwired to 0). Parity Error Enable (PERRE). Note that the PERR# signal is not implemented by the 82443ZX. 1 = Enable. Address and data parity errors are reported via SERR# mechanism (if enabled via SERRE bit). 6 0 = Disable. Address and data parity errors are not reported via the 82443ZX SERR# signal. (NOTE: Other types of error conditions can be still signaled via SERR# mechanism.) NOTE: The 82443ZX PCI bus interface is still required to generate parity even if parity error reporting is disabled via this bit. 5 4 3 Reserved. Memory Write and Invalidate Enable. The 82443ZX never uses this command. 0 = Hardwired to 0. Special Cycle Enable. The 82443ZX ignores all special cycles generated on the PCI. 0 = Hardwired to 0. Bus Master Enable (BME). The 82443ZX does not support disabling of its bus master capability on the PCI Bus. 1 = Hardwired to 1, permitting the 82443ZX to function as a PCI Bus master. 1 Memory Access Enable (MAE). This bit enables/disables PCI master access to main memory (DRAM). The 82443ZX always allows PCI master access to main memory. 1 = Hardwired to 1. 0 I/O Access Enable (IOAE). The 82443ZX does not respond to PCI bus I/O cycles. 0 = Hardwired to 0. Descriptions 2 82443ZX Host Bridge Datasheet 3-11 Register Description 3.3.4 PCISTS—PCI Status Register (Device 0) Address Offset: Default Value: Access: Size: 06–07h 0210h/0200h Read Only, Read/Write Clear 16 bits PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target abort on the PCI bus. PCISTS also indicates the DEVSEL# timing that has been set by the 82443ZX hardware for target responses on the PCI bus. Bits [15:12] and bit 8 are read/write clear and bits [10:9] are read only. Bit Descriptions Detected Parity Error (DPE). Note that the function of this bit is not affected by the PERRE bit. PERR# is not implemented in the 82443ZX. 15 1 = Indicates 82443ZX’s detection of a parity error in the address or data phase of PCI bus transactions. 0 = Software sets DPE to 0 by writing a 1 to this bit. Signaled System Error (SSE). 14 1 = This bit is set to 1 when the 82443ZX asserts SERR# for any enabled error condition under device 0. 0 = Software sets SSE to 0 by writing a 1 to this bit. Received Master Abort Status (RMAS). Note that Master abort is the normal and expected termination of PCI special cycles. 13 1 = When the 82443ZX terminates a PCI bus transaction (82443ZX is a PCI master) with an unexpected master abort, this bit is set to 1. 0 = Software resets this bit to 0 by writing a 1 to it. Received Target Abort Status (RTAS). 12 1 = When a 82443ZX-initiated PCI transaction is terminated with a target abort, RTAS is set to 1. The 82443ZX also asserts SERR# if enabled in the ERRCMD register. 0 = Software resets RTAS to 0 by writing a 1 to it. 11 Signaled Target Abort Status (STAS). The 82443ZX does not generate target abort. 0 = Hardwired to a 0 DEVSEL# Timing (DEVT). This 2-bit field indicates the timing of the DEVSEL# signal when the 82443ZX responds as a target on PCI, and indicates the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle. 01 = Medium (hardwired to 01) 8 Data Parity Detected (DPD). 82443ZX does not implement the PERR# pin. However, data parity errors are still detected and reported on SERR# (if enabled by SERRE and PERRE). 0 = Hardwired to 0 7 6:5 4 3:0 Fast Back-to-Back (FB2B). The 82443ZX as a target does not support fast back-to-back transactions on the PCI bus. 0 = Hardwired to 0 Reserved. Capability List (CLIST). 1 = When the AGP DIS bit (PMCR[1]) is set to 0, this bit is set to 1. 0 = When the AGP DIS bit (PMCR[1]) is set to 1, this bit is set 0. Reserved. 10:9 3-12 82443ZX Host Bridge Datasheet Register Description 3.3.5 RID—Revision Identification Register (Device 0) Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits This register contains the revision number of the 82443ZX Function #0. These bits are read only and writes to this register have no effect. Bit Description Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the 82443ZX Function #0. B-1 = 02h 7:0 3.3.6 SUBC—Sub-Class Code Register (Device 0) Address Offset: Default Value: Access: Size: 0Ah 00h Read Only 8 bits This register contains the Sub-Class Code for the 82443ZX Function #0. This code is 00h indicating a Host Bridge device. The register is read only. Bit 7:0 Description Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into which the 82443ZX falls. The code is 00h indicating a Host Bridge. 3.3.7 BCC—Base Class Code Register (Device 0) Address Offset: Default Value: Access: Size: 0Bh 06h Read Only 8 bits This register contains the Base Class Code of the 82443ZX Function #0. This code is 06h indicating a Bridge device. This register is read only. Bit 7:0 Description Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the 82443ZX. This code has the value 06h, indicating a Bridge device. 82443ZX Host Bridge Datasheet 3-13 Register Description 3.3.8 MLT—Master Latency Timer Register (Device 0) Address Offset: Default Value: Access: Size: 0Dh 00h Read/Write 8 bits This register controls the amount of time that 82443ZX can burst data on the PCI Bus as a PCI master. The MLT[2:0] bits are reserved and assumed to be 0 when determining the Count Value. Bit Description Master Latency Timer Count Value for PCI Bus Access. MLT is an 8-bit register that controls the amount of time the 82443ZX, as a PCI bus master, can burst data on the PCI Bus. The default value of MLT is 00h and disables this function. For example, if the MLT is programmed to 18h, then the value is 24 PCI clocks. Reserved. 7:3 2:0 3.3.9 HDR—Header Type Register (Device 0) Offset: Default: Access: Size: 0Eh 00h Read Only 8 bits This register identifies the header layout of the configuration space. Bit 7:0 Descriptions Header Type (HEADT). This read only field always returns 0 when read. Writes have no affect on this field. 3.3.10 APBASE—Aperture Base Configuration Register (Device 0) Offset: Default: Access: Size: 10–13h 00000008h Read/Write, Read Only 32 bits The APBASE is a normal PCI Base Address register that is used to request the base of the Graphics Aperture. The normal PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to “0” or behave as hardwired to “0”). To allow for flexibility (of the aperture) an additional register called APSIZE is used as a “back-end” register to control which bits of the APBASE will behave as hardwired to “0”. This register will be programmed by the 82443ZX specific BIOS code that will run before any of the generic configuration software is run. Note: Bit 9 of the NBXCFG register is used to prevent accesses to the aperture range before this register is initialized by the configuration software and appropriate translation table structure has been established in the main memory. 3-14 82443ZX Host Bridge Datasheet Register Description Bit Description Upper Programmable Base Address bits (R/W). These bits are used to locate the range size selected via lower bits 27:4. Default = 0000b Lower “Hardwired”/Programmable Base Address bits. These bits behave as a “hardwired” or as a programmable depending on the contents of the APSIZE register as defined below: 27 r/w r/w r/w r/w r/w 26 r/w r/w r/w r/w r/w 0 0 25 r/w r/w r/w r/w 0 0 0 24 r/w r/w r/w 0 0 0 0 23 r/w r/w 0 0 0 0 0 22 r/w 0 0 0 0 0 0 Aperture Size 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB 256 MB 31:28 27:22 r/w 0 Bits 27:22 are controlled by the bits 5:0 of the APSIZE register in the following manner: If bit APSIZE[5]=0 then APBASE[27]=0 and if APSIZE[5]=1 then APBASE[27]=r/w (read/write). The same applies correspondingly to other bits. Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., all bits respond as “hardwired” to 0). This provides a default to the maximum aperture size of 256 MB. The 82443ZX specific BIOS is responsible for selecting smaller size (if required) before PCI configuration software runs and establishes the system address map. 21:4 3 Hardwired to “0”. This forces minimum aperture size selected by this register to be 4MB. Prefetchable (RO). This bit is hardwired to “1” to identify the Graphics Aperture range as a prefetchable ( i.e., the device returns all bytes on reads regardless of the byte enables), and the 82443ZX may merge processor writes into this range without causing errors. Type (RO). These bits determine addressing type and they are hardwired to “00” to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space. Memory Space Indicator (RO). Hardwired to “0” to identify aperture range as a memory range. 2:1 0 3.3.11 SVID—Subsystem Vendor Identification Register (Device 0) Offset: Default: Access: Size: Bit 15:0 2C–2Dh 0000h Read/Write Once 16 bits Description Subsystem Vendor ID (R/WO). This value is used to identify the vendor of the subsystem. The default value is 00h. This field should be programmed during boot-up. After this field is written once, it becomes read only. 82443ZX Host Bridge Datasheet 3-15 Register Description 3.3.12 SID—Subsystem Identification Register (Device 0) Offset: Default: Access: Size: Bit 15:0 2E–2Fh 0000h Read/Write Once 16 bits Description Subsystem ID (R/WO). This value is used to identify a particular subsystem. The default value is 00h. This field should be programmed during boot-up. After this field is written once, it becomes read only. 3.3.13 CAPPTR—Capabilities Pointer Register (Device 0) Offset: Default: Access: Size: 34h A0h/00h Read Only 8 bits The CAPPTR provides the offset that is the pointer to the location where the AGP normal registers are located. Bit Description Pointer to the start of AGP normal register block. 7:0 A0h = When the AGP_DIS bit (PMCR[1]) is set to 0, the value in this field is A0h. 00h = When the AGP_DIS bit (PMCR[1]) is set to 1, this field is set to 00h. 3.3.14 NBXCFG—NBX Configuration Register (Device 0) Offset: Default: Access: Size: Bit SDRAM Row Without ECC. 31:24 These bits should all be set to “0”. The 82443ZX does not support ECC. 50–53h bits 31–16: 0000h bits 15–0: 00S0-0000-000S-0S00b Read/Write, Read Only for strapping options 32 bits Description 23:19 Reserved Host Bus Fast Data Ready Enable (HBFDRE). 18 0 = Assertion of DRAM data on host bus occurs one clock after sampling snoop results. (default) 1 = Assertion of DRAM data on host bus occurs on the same clock the snoop result is being sampled. This mode is faster by one clock cycle. 3-16 82443ZX Host Bridge Datasheet Register Description Bit ECC - EDO Static Drive Mode 17 Description This bit should be set to “0”. The 82443ZX does not support ECC. IDSEL_REDIRECT. This is a programmable option to make the 82443ZX compatible with 430TX base design. For CPU initiated configuration cycles to PCI, Device 1 which are targeted to the 82443ZX’s host to AGP bridge: 0 = When set to ‘0’ (default), IDSEL1 (or AD12) is allocated to this bridge. The external AD12 is never activated. CPU initiated configuration cycles to BUS0, DEVICE7 are targeted a PCI bus device that its IDSEL input is connected to IDSEL7 (AD18). 1 = When set to ‘1’, IDSEL7 (or AD18) is allocated to this bridge. Since it is internal in the 82443ZX, the external AD18 is never activated. CPU initiated configuration cycles to BUS0, DEVICE7 are targeted a PCI bus device that its IDSEL input is connected to IDSEL1 (AD12). In some 430TX based systems, this is connected to PIIX4E. Note that CPU initiated configuration cycles to other PCI buses or other devices are normally mapped and are not affected. WSC# Handshake Disable This bit should be set to “1” for single processor use. The 82443ZX does not support the I/O APIC or dual processors. Intel Reserved. Host/DRAM Frequency. These bits are used to determine the host and DRAM frequency. Bit 13 is set by an external strapping option at reset. These bits are also used to select the required refresh rate. These bits apply to both SDRAM and EDO, with the exception that setting “00” for 100MHz is illegal for an EDO system. 13:12 00 = 100MHz 01 = Reserved 10 = 66MHz 11 = Reserved AGP to PCI Access Enable. When PHLDA# is active or there is an outstanding passive release transaction pending: 1) this bit is set to 1 and the 82443ZX allows AGP to PCI traffic, or 2) this bit is set to 0 (default) and the 82443ZX blocks AGP to PCI traffic. The AGP to PCI traffic must not target the ISA bus. 1 = Enable 0 =Disable PCI Agent to Aperture Access Disable. This bit is used to prevent access to the aperture from the PCI side. 10 1 = Disable 0 = Enable (default). If this bit is “0” (default) and bit 9 = 1, accesses to the aperture are enabled for the PCI side. Note: This bit is don’t care if bit 9 of this register = 0. Aperture Access Global Enable. This bit is used to prevent access to the aperture from any port (CPU, PCI or AGP) before aperture range is established by the configuration software and appropriate translation table in the main DRAM has been initialized. Default is “0”. It must be set after system is fully configured for aperture accesses. 1 = Enable. Note that this bit globally controls accesses to the aperture. Once enabled, bit 10 provides the next level of control for accesses originated from the PCI side. 0 = Disable 16 15 14 11 9 82443ZX Host Bridge Datasheet 3-17 Register Description Bit Description DRAM Data Integrity Mode (DDIM) (R/W). These bits select one of 4 DRAM data integrity modes. These bits should be set to “00” because the 82443ZX does not support ECC. Not applicable in the 82443ZX. MDA Present (MDAP). This bit is used to indicate the presence of a secondary monochrome adapter on the PCI bus, while the primary graphics controller is on the AGP bus. This bit works in conjunction with the VGA_EN bit (Register 3E, bit 3 of device 1) as follows: VGA_EN 0 MDAP X 0 1 Description All VGA cycles are sent to PCI. PCI master cycles to the VGA range are not claimed by the 82443ZX. All VGA cycles are sent to AGP. PCI master writes to VGA range are claimed by the 82443ZX and forwarded to the AGP bus. All VGA cycles are sent to AGP, except for cycles in the MDA range (or the aliased ranges defined below). PCI master writes in the VGA range (outside of the MDA range) are claimed by the 82443ZX and forwarded to AGP. PCI and AGP master read/writes to the MDA range are ignored by the 82443ZX. 8:7 6 5 1 1 The MDA ranges are a subset of the VGA ranges as follows: Memory: 0B0000h–0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh 4 3 Reserved/Default. USWC Write Post During I/O Bridge Access Enable (UWPIO) (R/W). 1 = Enable. Host USWC writes to PCI memory are posted. 0 = Disable. Posting of USWC is not allowed. In-Order Queue Depth (IOQD) (RO). This bit reflects the value sampled on A7# on the deassertion of the CPURST#. It indicates the depth of the Pentium® Pro processor bus in-order queue (i.e., level of Pentium Pro processor bus pipelining). 1 = In-order queue = maximum. If A7# is sampled “1” (i.e,. undriven on the Pentium Pro processor bus), the depth of the Pentium Pro processor bus in-order queue is configured to the maximum allowed by the Pentium Pro processor protocol (i.e., 8). However, the actual maximum supported by the 82443ZX is 4, and it is controlled by the 82443ZX’s Pentium Pro processor interface logic using the BNR# signaling mechanism. 0 = A7# is sampled asserted (i.e., “0”). The depth of the Pentium Pro processor bus in-order queue is set to 1 (i.e., no pipelining support on the Pentium Pro processor bus). NOTE: During reset, A7# can be driven either by the 82443ZX or by an external source as defined by the strapping option on the MAB11# pin. 1:0 Reserved. 2 3-18 82443ZX Host Bridge Datasheet Register Description 3.3.15 DRAMC—DRAM Control Register (Device 0) Address Offset: Default Value: Access: Size: Bit 7:6 Reserved. Module Mode Configuration (MMCONFIG). This bit is set by an external strapping option. The combination of this bit and the SDRAMPWR bit (SDRAMC register) determine the functioning of the CKE signals as defined as follows: SDRAMPWR 0 5 X 1 1 0 MMCONFIG 0 CKE Operation 3 DIMM, CKE[5:0] driven, self-refresh entry staggered. SDRAM dynamic power down available. 3 DIMM, CKE0 only, self-refresh entry not staggered. SDRAM dynamic power down unavailable. 4 DIMM, GCKE only, self-refresh entry staggered. SDRAM dynamic power down unavailable. 57h 00S0_0000b Read/Write 8 bits Description NOTE: Under MMCONFIG mode, the AGP must be disabled. 4 Not Applicable in the 82443ZX. DRAM Type (DT). This field indicates the DRAM type used to populate the entire array. When set to 0, EDO timings are used for all cycles to main memory. When set to 1, SDRAM timings are used for all cycles to memory. EDO and SDRAM cannot be mixed within a system. 3 0 = EDO 1 = SDRAM DRAM Refresh Rate (DRR). The DRAM refresh rate is adjusted according to the frequency selected by this field. Disabling the refresh cycle (000) results in the eventual loss of DRAM data. Changing DRR value will reset the refresh request timer. This field is used in conjunction with the SDRAM frequency bits in the NBXCFG register to determine the correct load value for the refresh timer. 000 = Refresh Disabled 001 = 15.6 us 2:0 010 = 31.2 us 011 = 62.4 us 100 = 124.8 us 101 = 249.6 us 110 = Reserved 111 = Reserved NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’. 82443ZX Host Bridge Datasheet 3-19 Register Description 3.3.16 DRAMT—DRAM Timing Register (Device 0) Address Offset: Default Value: Access: Size: 58h 03h Read/Write 8 bits This 8-bit register controls main memory DRAM timings. Refer to the DRAM section for details regarding the DRAM timings programmed in this register. Bit 7:2 Reserved. EDO RASx# Wait State (RWS). When RWS = 1, one additional wait state is inserted before RAS# is asserted for row misses. This provides one clock of additional MAX[13:0] setup time to RASx# assertion. This bit does not affect page misses since the MAX[13:0] lines are setup several clocks in advance of RAS# assertion for page misses. 0 = 1 tASR 1 = 2 tASR EDO CASx# Wait State (CWS). When CWS = 1, one additional wait state is inserted before the assertion of the first CASx# for page hit cycles. This allows one additional clock of MA setup time to the CASx# for the leadoff page hit cycle. Page miss and row miss timings are not affected by this bit. 0 = 1 Tasc 1 = 2 Tasc Description 1 0 3.3.17 PAM[6:0]—Programmable Attribute Map Registers (Device 0) Address Offset: Default Value: Attribute: 59h (PAM0) – 5Fh (PAM6) 00h Read/Write The 82443ZX allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the Pentium Pro processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to both host accesses and PCI initiator accesses to the PAM areas. These attributes are: RE Read Enable. When RE = 1, the host read accesses to the corresponding memory segment are claimed by the 82443ZX and directed to main memory. Conversely, when RE = 0, the host read accesses are directed to PCI. Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are claimed by the 82443ZX and directed to main memory. Conversely, when WE = 0, the host write accesses are directed to PCI. WE The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field. The four bits that control each region have the same encoding and are defined in Table 3-2. 3-20 82443ZX Host Bridge Datasheet Register Description Table 3-2. Attribute Bit Assignment Bits [7, 3] Reserved x Bits [6, 2] Reserved x Bits [5, 1] WE 0 Bits [4, 0] RE 0 Description Disabled. DRAM is disabled and all accesses are directed to PCI. The 82443ZX does not respond as a PCI target for any read or write access to this area. Read Only. Reads are forwarded to DRAM and writes are forwarded to PCI for termination. This write protects the corresponding memory segment. The 82443ZX will respond as a PCI target for read accesses but not for any write accesses. Write Only. Writes are forwarded to DRAM and reads are forwarded to the PCI for termination. The 82443ZX will respond as a PCI target for write accesses but not for any read accesses. Read/Write. This is the normal operating mode of main memory. Both read and write cycles from the host are claimed by the 82443ZX and forwarded to DRAM. The 82443ZX will respond as a PCI target for both read and write accesses. x x 0 1 x x 1 0 x x 1 1 As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to write only. The BIOS is shadowed by first doing a read of that address. This read is forwarded to the expansion bus. The host then does a write of the same address, which is directed to main memory. After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Table 3-3 shows the PAM registers and the associated attribute bits: Table 3-3. PAM Registers and Associated Memory Segments PAM Reg PAM0[3:0] PAM0[7:4] PAM1[3:0] PAM1[7:4] PAM2[3:0] PAM2[7:4] PAM3[3:0] PAM3[7:4] PAM4[3:0] PAM4[7:4] PAM5[3:0] PAM5[7:4] PAM6[3:0] PAM6[7:4] R R R R R R R R R R R R R Attribute Bits Reserved R R R R R R R R R R R R R WE WE WE WE WE WE WE WE WE WE WE WE WE RE RE RE RE RE RE RE RE RE RE RE RE RE 0F0000h – 0FFFFFh 0C0000h – 0C3FFFh 0C4000h – 0C7FFFh 0C8000h – 0CBFFFh 0CC000h – 0CFFFFh 0D0000h – 0D3FFFh 0D4000h – 0D7FFFh 0D8000h – 0DBFFFh 0DC000h – 0DFFFFh 0E0000h – 0E3FFFh 0E4000h – 0E7FFFh 0E8000h – 0EBFFFh 0EC000h – 0EFFFFh BIOS Area ISA Add-on BIOS¹ ISA Add-on BIOS¹ ISA Add-on BIOS¹ ISA Add-on BIOS¹ ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension Memory Segment Comments Offset 59h 59h 5Ah 5Ah 5Bh 5Bh 5Ch 5Ch 5Dh 5Dh 5Eh 5Eh 5Fh 5Fh NOTE: 1. The C0000h to CFFFFh segment can be used for SMM space if enabled by the SMRAM register 82443ZX Host Bridge Datasheet 3-21 Register Description DOS Application Area (00000h–9FFFh) The DOS area is 640 KB and it is further divided into two parts. The 512 KB area at 0 to 7FFFFh is always mapped to the main memory controlled by the 82443ZX, while the 128 KB address range from 080000 to 09FFFFh can be mapped to PCI or to main DRAM. By default this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to PCI) via 82443ZX’s FDHC configuration register. Video Buffer Area (A0000h–BFFFFh) This 128 KB area is not controlled by attribute bits. The host-initiated cycles in this region are always forwarded to either PCI or AGP unless this range is accessed in SMM mode. Routing of accesses is controlled by the Legacy VGA control mechanism of the “virtual” PCI-to-PCI bridge device embedded within the 82443ZX. This area can be programmed as SMM area via the SMRAM register. When used as a SMM space this range can not be accessed from PCI or AGP. Expansion Area (C0000h–DFFFFh) This 128 KB area is divided into eight 16 KB segments which can be assigned with different attributes via PAM control register as defined by Table 3-3. Extended System BIOS Area (E0000h–EFFFFh) This 64 KB area is divided into four 16 KB segments which can be assigned with different attributes via PAM control register as defined by the Table 3-3. System BIOS Area (F0000h–FFFFFh) This area is a single 64 KB segment which can be assigned with different attributes via PAM control register as defined by the Table 3-3. 3.3.18 DRB[0:7]—DRAM Row Boundary Registers (Device 0) Address Offset: Default Value: Access: Size: 60h (DRB0) – 67h (DRB7) 01h Read/Write 8 bits/register The 82443ZX supports 4 physical rows of DRAM. The width of a row is 64 bits. The DRAM Row Boundary Registers define upper and lower addresses for each DRAM row. Contents of these 8-bit registers represent the boundary addresses in 8 MB granularity. For example, a value of 01h indicates 8 MB. 60h DRB0 = Total memory in row0 (in 8 MB) 61h DRB1 = Total memory in row0 + row1 (in 8 MB) 62h DRB2 = Total memory in row0 + row1 + row2 (in 8 MB) 63h DRB3 = Total memory in row0 + row1 + row2 + row3 (in 8 MB) 64h-67h: Not Applicable The DRAM array can be configured with single or double-sided DIMMs using 2MX8, 4Mx16, or 8Mx8 parts. Each register defines an address range that will cause a particular CS# line (or RAS# in the EDO case) to be asserted (e.g., if the first DRAM row is minus 8 MB, then accesses within the 0 to 8 MByte range will cause CSx0#/RASx0# to be asserted). The DRAM Row Boundary 3-22 82443ZX Host Bridge Datasheet Register Description (DRB) Registers are programmed with an 8-bit upper address limit value. This upper address limit is compared to bits [30:23] of the requested address, for each row, to determine if DRAM is being targeted. Note: DRAM is selected only if address[31:30] are zero. Bit Description Row Boundary Address. This 8-bit value is compared against address lines A[30:23] to determine the upper address limit of a particular row (i.e., DRB minus previous DRB = row size). NOTE: When PCIRST# assertion occurs during POS/STR, these bits are not reset to ‘01h’. 7:0 Row Boundary Address These 8 bit values represent the upper address limits of the four rows (i.e., this row minus previous row = row size). Unpopulated rows have a value equal to the previous row (row size = 0). DRB3 reflects the maximum amount of DRAM in the system. The top of memory is determined by the value written into DRB3. Note: The 82443ZX supports a maximum of 256MB of DRAM. As an example of a general purpose configuration where four physical rows are configured for either single-sided or double-sided DIMMs, the memory array would be configured like the one shown in Figure 3-2. In this configuration, the 82443ZX drives four CS# signals directly to the DIMM rows. If single-sided DIMMs are populated, the even CS# signals are used and the odd CS#s are not connected. If double-sided DIMMs are used, all four CS# signals are used per DIMM. Figure 3-2. SDRAM DIMMs and Corresponding DRB Registers CSA3#/CSB3# CSA2#/CSB2# CSA1#/CSB1# CSA0#/CSB0# DIMM1 – Back DIMM1 – Front DIMM0 – Back DIMM0 – Front DRB3 DRB2 DRB1 DRB0 82443ZX Host Bridge Datasheet 3-23 Register Description The following 2 examples describe how the DRB Registers are programmed for cases of singlesided and double-sided DIMMs on a motherboard. Example #1 Single-sided DIMMs Assume a total of 16 MB of DRAM are required using single-sided 1MB x 64 DIMMs. In this configuration, two DIMMs are required. DRB0 = 01h DRB1 = 01h DRB2 = 02h DRB3 = 02h populated (1 DIMM, 8 Mbyte this row) empty row populated (1 DIMM, 8 Mbyte this row) empty row Example #2 Mixed Single-/Double-sided DIMMs As another example, consider a system that is initially shipped with 8 MB of memory using a 1M x 64 DIMM and that an additional 64MB of memory array is used to upgrade toa total of 72 MB of memory. This can be handled by further populating the array with one 8M x 64 double-sided DIMM (two rows), yielding a total of 72 MB of DRAM. The DRB Registers are programmed as follows: DRB0 = 01h DRB1 = 01h DRB2 = 05h DRB3 = 09h populated with 8 MB, 1MB x 64 single-sided DIMM empty row populated with 32 MB, 1/2 of 8M x 64 DIMM populated with 32 MB, the other 1/2 of 8M x 64 DIMM 3.3.19 FDHC—Fixed DRAM Hole Control Register (Device 0) Address Offset: Default Value: Access: Size: 68h 00h Read/Write 8 bits This 8-bit register controls 2 fixed DRAM holes: 512 KB – 640 KB and 15 MB –16 MB. Bit Description Hole Enable (HEN). This field enables a memory hole in DRAM space. Host cycles matching an enabled hole are passed on to PCI. PCI cycles matching an enabled hole will be ignored by the 82443ZX (no DEVSEL#). NOTE: A selected hole is not remapped. 7:6 00 = None 01 = 512 KB–640 KB (128 KB bytes) 10 = 15 MB – 16 MB (1 MB byte) 11 = Reserved 5:0 Reserved. 3-24 82443ZX Host Bridge Datasheet Register Description 3.3.20 MBSC—Memory Buffer Strength Control Register (Device 0) Address Offset: Default Value: Access: Size: 69–6Eh 000000000000h Read/Write 48 bits This register programs the various DRAM interface signal buffer strengths, based on non-mixed memory configurations of DRAM type (EDO or SDRAM), DRAM density (x8, x16, or x32), DRAM technology (16MB or 64 MB), and rows populated. Note that x4 DRAM is not supported. Note: The choice of 100 MHz or 66 MHz buffer is independent of bus frequency. It is possible to select a 100 MHz memory buffer even though the bus frequency is 66 MHz (and vice versa). Bit 47:40 Reserved MAA[13:0], WEA#, SRASA#, SCASA# Buffer Strengths. This field sets the buffer strength for the MAA[13:0], WEA#, SRASA#, SCASA# pins. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz) Not Applicable in the 82443ZX. MD [63:0] Buffer Strength Control 2. 4 DIMM FET Configuration: This field sets the buffer strength for the MD[63:0] path that is connected to DIMM2 and DIMM3. The buffer strength is programmable based on the SDRAM load in detected in DIMM slots 2&3. This path is enabled when FENA is asserted (High) by the 82443ZX. 3 DIMM & 4 DIMM non-FET Configuration: This field should be programmed to the same value as MD[63:0] Buffer Strength Control 1. This buffer strength is programmable based upon the SDRAM load detected in all DIMM connectors. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (100 MHz only) MD [63:0] Buffer Strength Control 1. 4 DIMM FET Configuration: This field sets the buffer strength for the MD[63:0] path that is connected to DIMM0 and DIMM1. The buffer strength is programmable based upon the SDRAM load in detected in DIMM slots 0&1. This path is enabled when FENA is asserted (Low) by the 82443ZX. 3 DIMM & 4 DIMM non-FET Configurations: The buffer strength is programmable based upon the SDRAM load detected in all DIMM connectors. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (100 MHz only) Not Applicable in the 82443ZX. CSA7#/CKE3 Buffer Strength. This field sets the buffer strength for CSA7#/CKE3 pins. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz) Not Applicable in the 82443ZX. Description 39:38 37:36 35:34 33:32 31:26 25:24 23:22 82443ZX Host Bridge Datasheet 3-25 Register Description Bit Description CSA6#/CKE2 Buffer Strength. This field sets the buffer strength for CSA6#/CKE2pins. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz) Not Applicable in the 82443ZX. CSA3#/RASA3#, CSB3#/RASB3# Buffer Strength. This field sets the buffer strength for the CSA3#/RASA3#, CSB3#/RASB3# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz) CSA2#/RASA2#, CSB2#/RASB2# Buffer Strength. This field sets the buffer strength for the CSA2#/RASA2#, CSB2#/RASB2# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz) CSA1#/RASA1#, CSB1#/RASB1# Buffer Strength. This field sets the buffer strength for the CSA1#/RASA1#, CSB1#/RASB1# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz) CSA0#/RASA0#, CSB0#/RASB0# Buffer Strength. This field sets the buffer strength for the CSA0#/RASA0#, CSB0#/RASB0# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz) DQMA5/CASA5# Buffer Strength. This field sets the buffer strength for the DQMA5/CASA5# pins. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz only) DQMA1/CASA1# Buffer Strength. This field sets the buffer strength for the DQMA1/CASA1# pin. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz) Not Applicable in the 82443ZX. DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# Buffer Strength. This field sets the buffer strength for the DQMA[7:6]/CASA[7:6]#, DQMA[4:2]/CASA[4:2]#, and the DQMA[0]/CASA[0]# pins. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz) CKE1/GCKE Buffer Strength. This field sets the buffer strength for the CKE1 pin. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz) CKE0/FENA Buffer Strength. This field sets the buffer strength for the CKE0/FENA pin. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz) 21:20 19:18 17 16 15 14 13:12 11:10 9:6 5:4 3:2 1:0 3-26 82443ZX Host Bridge Datasheet Register Description 3.3.21 SMRAM—System Management RAM Control Register (Device 0) Address Offset: Default Value: Access: Size: 72h 02h Read/Write 8 bits The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set. Bit 7 Reserved SMM Space Open (D_OPEN). When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When D_LCK is set to a 1, D_OPEN is reset to 0 and becomes read only. SMM Space Closed (D_CLS). When D_CLS = 1 SMM space DRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space DRAM. This will allow SMM software to reference "through" SMM space to update the display even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. SMM Space Locked (D_LCK). When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN, H_SMRAM_EN, TSEG_SZ, TSEG_EN and DRB7 become read only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a power-on reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. Global SMRAM Enable (G_SMRAME). If G_SMRAME is set to a 1 and H_SMRAM_EN is set to 0, then Compatible SMRAM functions are enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function this bit has be set to 1. Refer to the section on SMM for more details. Once D_LCK is set, this bit becomes read only. Compatible SMM Space Base Segment (C_BASE_SEG) (RO). This field programs the location of SMM space. "SMM DRAM" is not remapped. It is simply "made visible" if the conditions are right to access SMM space, otherwise the access is forwarded to PCI. 010 = Hardwired to 010 to indicate that the 82443ZX supports the SMM space at A0000h–BFFFFh. Description 6 5 4 3 2:0 82443ZX Host Bridge Datasheet 3-27 Register Description 3.3.22 ESMRAMC—Extended System Management RAM Control Register (Device 0) Address Offset: Default Value: Access: Size: 73h 38h Read/Write 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 Mbyte. Bit Description H_SMRAM_EN (H_SMRAME). Controls the SMM memory space location (i.e above 1 Mbyte or below 1 Mbyte). 1 = When G_SMRAME is 1 and H SMRAME is set to 1, the High SMRAM memory space is enabled, the Compatible SMRAM memory is disabled, and accesses in the 0A0000h to 0FFFFFh range are forwarded to PCI, while SMRAM accesses from 100A0000h to 100FFFFFh are remapped to DRAM address A0000h to FFFFFh 0 = When G SMRAME is set to a 1 and H SMRAM EN is set to 0, then the Compatible SMRAM space is enabled. Once D_LCK is set, this bit becomes read only. E_SMRAM_ERR (E_SMERR). 6 1 = This bit is set when CPU accesses the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. 0 = It is software’s responsibility to clear this bit. The software must write a 1 to this bit to clear it. 5 4 3 SMRAM_Cache (SM_CACHE). This bit is forced to ‘1’ by 82443ZX. SMRAM_L1_EN (SM_L1). This bit is forced to ‘1’ by 82443ZX. SMRAM_L2_EN (SM_L2). This bit is forced to ‘1’ by 82443ZX. TSEG_SZ[1:0] (T_SZ). Selects the size of the TSEG memory block, if enabled. This memory is taken from the top of DRAM space (i.e., TOM - TSEG_SZ), which is no longer claimed by the memory controller (all accesses to this space are sent to the PCI bus if TSEG_EN is set). The physical address for the extended SMRAM memory appears is from (256M + TOM - TSEG_SZ) to (256M + TOM). This address is remapped to DRAM address (TOM - TSEG_SZ) to TOM. This field decodes as follows: 2:1 00 = (TOM–128KB) to TOM 01 = (TOM–256KB) to TOM 10 = (TOM–512KB) to TOM 11 = (TOM–1MB) to TOM Once D_LCK is set, this bit becomes read only. TSEG_EN (T_EN). Enabling of SMRAM memory (TSEG, 128 KB, 256 KB, 512 KB or 1 MB of additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK is set, this bit becomes read only. 7 0 3-28 82443ZX Host Bridge Datasheet Register Description 3.3.23 RPS—SDRAM Row Page Size Register (Device 0) Address Offset: Default Value: Access: Size: 74h–75h 0000h Read/Write 16 bits This register sets the row page size for SDRAM only. For EDO memory, the page size is fixed at 2 KB. Bit Description Page Size (PS). Each pair of bits in this register indicate the page size used for one row of DRAM. The encoding of the two bit fields. Bits[1:0] 00 01 10 11 RPS bits 1:0 3:2 5:4 7:6 9:15 Page Size 2 KB 4 KB 8 KB Reserved Corresponding DRB register DRB[0], row 0 DRB[1], row 1 DRB[2], row 2 DRB[3], row 3 Not Applicable in the 82443ZX. 15:0 3.3.24 SDRAMC—SDRAM Control Register (Device 0) Address Offset: Default Value: Access: Size: Bit 15:10 9:8 Reserved Idle/Pipeline DRAM Leadoff Timing (IPDLT). Adds a clock delay to the lead-off clock count when bits 9:8 are set to 01. All other settings are illegal. 76h–77h 00h Read/Write 16 bits Description 82443ZX Host Bridge Datasheet 3-29 Register Description Bit Description SDRAM Mode Select (SMS). These bits allow the 82443ZX to drive various commands to the SDRAMs. These special modes are intended for initialization at power up. SMS 000 001 Mode Normal SDRAM Operation. (default) NOP Command Enable. In this mode all CPU cycles to SDRAM result in NOP Command on the SDRAM interface. 010 All Banks Precharge Enable. In this mode all CPU cycles to SDRAM result in an All Banks Precharge Command on the SDRAM interface. 011 Mode Register Set Enable. In this mode all CPU cycles to SDRAM result in a mode register set command on the SDRAM interface. The Command is driven on the MAx[13:0] lines. MAx[2:0] must always be driven to 010 for burst of 4 mode. MA3 must be driven to 1 for interleave wrap type. MAx4 needs to be driven to the value programmed in the CAS# Latency bit. MAx[6:5] should always be driven to 01. MAx[12:7] must be driven to 000000. BIOS must calculate and drive the correct host address for each row of memory such that the correct command is driven on the MAx[12:0] lines. 100 CBR Enable. In this mode all CPU cycles to SDRAM result in a CBR cycle on the SDRAM interface. 101 Reserved. 110 Reserved. 111 Reserved. Note: BIOS must take into consideration MAB inversion when programming for 3 and 4 DIMM. Not Applicable in the 82443ZX. Leadoff Command Timing (LCT). These bits control when the SDRAM command pins (SRASx#, SCASx# and WEx#) and CSx# are considered valid on leadoffs for CPU cycles. 0 = 4 CS# Clock 1 = 3 CS# Clock The LCT Bit should be initialized by BIOS as recommended below: • Desktop platforms running at 100 MHz should leave the LCT bit set to its default value of 0. • Desktop platforms running at 66 MHz should leave the LCT bit set to its default value of 0, if load on either MAA or MAB signals is > 9. Otherwise, set the LCT bit to 1, if load on both MAA and MAB is ≤ 9. • Mobile platforms will be run at 66MHz and should set the LCT bit to 1. CAS# Latency (CL). This bit controls the number of CLKs between when a read command is sampled by the SDRAMs and when the 82443ZX samples read data from the SDRAMs. If a given row is populated with a registered SDRAM DIMM, an extra clock is inserted between the read command the when the 82443ZX samples read data. For a registered DIMM with CL=2, this bit should be set to 1. 0 = 3 DCLK CAS# latency. 1 = 2 DCLK CAS# latency. SDRAM RAS# to CAS# Delay (SRCD). This bit controls the number of DCLKs from a Row Activate command to a read or write command. 7:5 4 3 2 1 0 = 3 clocks will be inserted between a row activate command and either a read or write command. 1 = 2 clocks will be inserted between a row activate and either a read or write command. SDRAM RAS# Precharge (SRP). This bit controls the number of DCLKs for RAS# precharge. 0 = 3 clocks of RAS# precharge. 1 = 2 clocks of RAS# precharge. 0 3-30 82443ZX Host Bridge Datasheet Register Description 3.3.25 PGPOL—Paging Policy Register (Device 0) Address Offset: Default Value: Access: Size: Bit 78–79h 0000h Read/Write 16 bits Description 15:8 Banks per Row (BPR). Each bit in this field corresponds to one row of the memory array. Bit 15 corresponds to row 7 while bit 8 corresponds to row 0. These bits are defined only for SDRAM systems and define whether the corresponding row has a two bank implementation or a four bank implementation. Those with two banks (bit=0) can have up to two pages open at any given time. Those with four banks (bit=1) can have up to four pages open at any time. Note that the bits referencing empty rows are ‘don’t care’. 0 = 2 banks 1 = 4 banks 7:5 4 Reserved. Intel Reserved. DRAM Idle Timer (DIT). This field determines the number of clocks that the DRAM controller will remain in the idle state before precharging all pages. This field is used for both EDO and SDRAM memory systems. 0000 = 0 clocks 0001 = 2 clocks 0010 = 4 clocks 3:0 0011 = 8 clocks 0100 = 10 clocks 0101 = 12 clocks 0110 = 16 clocks 0111 = 32 clocks 1XXX = Infinite (pages are not closed for idle condition). 82443ZX Host Bridge Datasheet 3-31 Register Description 3.3.26 PMCR—Power Management Control Register (Device 0) Address Offset: Default Value: Access Size Bit Power Down SDRAM Enable (PDSE). 7 1 = Enable. When PDSE=1, an SDRAM row in idle state will be issued a power down command. The SDRAM row will exit power down mode only when there is a request to access this particular row. 0 = Disable ACPI Control Register Enable (SCRE). 6 1 = Enable. The ACPI control register in the 82443ZX is enabled, and all CPU cycles to IO address 0022h are handled by the 82443ZX and are not forwarded to PCI. 0 = Disable (default). All CPU cycles to IO address 0022h are passed on to the PCI bus. Suspend Refresh Type (SRT). This bit determines what type of EDO DRAM refresh is used during Power On Suspend (POS/STR) or Suspend to RAM modes. SRT has no effect on SDRAM refresh. 5 1 = Self refresh mode 0 = CBR fresh mode NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’. Normal Refresh Enable (NREF_EN). This bit is used to enable normal refresh operation following a POS/STR state. After coming out of reset the software must set this bit before doing an access to memory. 1 = Enable 0 = Disable Quick Start Mode (QSTART) (RO). 3 1 = Quick start mode of operation is enabled for the processor. This mode is entered using a strapping option that is sampled by the 82443ZX and the CPU during reset. This register bit is Read Only and a configuration write to it is ignored. Gated Clock Enable (GCLKEN). GCLKEN enables internal dynamic clock gating in the 82443ZX when a AGPset “IDLE” state occurs. This happens when the 82443ZX detects an idle state on all its buses. 1 = Enable 0 = Disable AGP Disable (AGP_DIS). This register bit is Read Only and a configuration write to it is ignored. 1 1 = Disable. The AGP interface and the clocks of AGP associated logic are permanently disabled. This mode is entered using a strapping option that is sampled by the 82443ZX during reset. 0 = Enable CPU reset without PCIRST enable (CRst_En). This bit enables the 82443ZX to assert CPU reset without an incoming PCIRST#. This option allows the reset of the processor when the system is coming out of POS state. Defaults to ‘0’ upon PCIRST# assertion. 0 1 = Enable 0 = Disable NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’. 7Ah 0000_S0S0b Read/Write 8 Bits Description 4 2 3-32 82443ZX Host Bridge Datasheet Register Description 3.3.27 SCRR—Suspend CBR Refresh Rate Register (Device 0) Address Offset: Default Value: Access Size Bit 15:13 Reserved. Suspend CBR refresh Rate Auto Adjust Enable (SRRAEN). SRRAEN bit is cleared to its default during cold reset only. It is not affected by PCIRST# during resume from suspend. 0 = Disable (default). Indicates that the suspend CBR refresh rate is not updated by the 82443ZX hardware to track the system operating conditions. In this case, it is expected that BIOS will set the SRR to reflect the worst case operating conditions so that minimum refresh rate will be provided. 1 = Enable. Indicates that the 82443ZX hardware adjusts the suspend refresh rate according to system operating conditions by comparing the number of OSCCLKs in a given time. This mode allows the system to dynamically adjust the refresh rate and thus minimize suspend power consumption while guaranteeing required refresh rate. Suspend CBR Refresh Rate (SRR). The rate is loaded into the counter which counts down on OSCCLK rising edges. When it expires, a suspend CBR refresh request is triggered. This bit field may be loaded by BIOS to reflect the desirable refresh rate. In addition, the 82443ZX will update it automatically, when the above SRRAEN = 1. In either case, the register is accessible for read and write operation at all times. 11:0 • This 12-bit field provides a dynamic range greater than the maximum CBR refresh rate that is supported of 249.6uSEC. • SRR bit field is cleared to its default during cold reset only. It is not affected by PCIRST# during resume from suspend. • The default value of this register is 038h, or 56 decimal. It represents a 15.5uS time between refreshes with the slowest corner OSCCLK cycle time of 270nS. 7Bh–7Ch 0038h Read/Write 16 Bits Description 12 3.3.28 EAP—Error Address Pointer Register (Device 0) Address Offset: Default Value: Access Size Bit 80–83h 00000000h Read Only, Read/Write-Clear 32 Bits Description 31:12 Error Address Pointer (EAP) (RO). This field is used to store the 4 KB block of main memory of which an error (single bit or multi-bit error) has occurred. Note that this field represents the address of the first error occurrence after bits 1:0 have been cleared by software. Once bits 1:0 are set to a value different than 00b, as a result of an error, this bit field is locked and doesn't change as a result of a new error. Reserved. Multiple Bit Error (MBE) (R/WC). This bit indicates that a multi-bit ECC error has occurred, and the address has been logged in bits 31:12. The EAP register is locked until the CPU clears this bit by writing a 1. Software uses bits 1:0 to detect whether the logged error address is for Single or Multi bit error, since both Single and Multiple Error bits of the Error Status register can be set. Once software completes the error processing, a value of ‘1’ is written to this bit field to clear the value (back to 0) and unlock the error logging mechanism. Note: Any ECC errors received during initialization should be ignored. Single Bit Error (SBE) (R/WC). 1 = Indicates that a single bit ECC error has occurred, and the address has been logged in bits 31:12. The EAP register is locked until the CPU clears this bit by writing a 1. Note: Any ECC errors received during initialization should be ignored. 11:2 1 0 82443ZX Host Bridge Datasheet 3-33 Register Description 3.3.29 ERRCMD—Error Command Register (Device 0) Address Offset: Default Value: Access: Size: 90h 80h Read/Write 8 bits This 8-bit register controls the 82443ZX responses to various system errors. The actual assertion of SERR# is enabled via the PCI Command register. Bit Description SERR# on AGP Non-Snoopable Access Outside of Graphics Aperture. When enabled and bit 10 of ERRSTS registers transitions from 0 to 1 (during an AGP access to the address outside of the graphics aperture) then an SERR# assertion event will be generated. 1 = Enable (default). 0 = Disable. SERR# on Invalid AGP DRAM Access. AGP non-snoopable READ accesses to locations outside the graphics aperture and outside the main DRAM range (i.e., in 640 KB – 1 MB range or above top of memory) are invalid. When this bit is set, bit 9 of the ERRSTS will be set and SERR# will be asserted, read accesses are not directed to main memory or the aperture range. 1 = Enable. 0 = Disable reporting of this condition via SERR#. SERR# on Access to Invalid Graphics Aperture Translation Table Entry. When enabled, the 82443ZX sets bit 8 of the ERRSTS and asserts SERR# following a read or write access to an invalid entry in the Graphics Aperture Translation Table residing in main memory. 1 = Enable. 0 = Disable reporting of this condition via SERR#. SERR# on Receiving Target Abort. 4 1 = Enable. The 82443ZX asserts SERR# on receiving a target abort on either the PCI or AGP. 0 = Disable. The 82443ZX does not assert SERR# on receipt of a target abort. SERR# on Detected Thermal Throttling Condition. 3 1 = Enable. The 82443ZX asserts SERR# when thermal throttling condition is detected for either the read or the write function. 0 = The 82443ZX does not assert SERR# for thermal throttling. SERR# Assertion Mode. 2 1 = SERR# is a level mode signal. Systems that connect SERR# to EXTSMI# for error reporting should set this bit to 1. 0 = SERR# is asserted for 1 PCI clock (normal PCI mode). (default) SERR# on Receiving Multiple or Single Bit ECC Error. 1:0 These bits should be set to “00” in the 82443ZX. 7 6 5 3-34 82443ZX Host Bridge Datasheet Register Description 3.3.30 ERRSTS—Error Status Register (Device 0) Address Offset: Default Value: Access: Size: 91–92h 0000h Read Only, Read/Write Clear 16 bits This 16-bit register is used to report error conditions via the SERR# mechanism. SERR# is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD register). Bit 15:13 12 Reserved. Read thermal Throttling Condition. 1 = Read thermal throttling condition occurred. 0 = Software writes “1” to clear this bit. Default=0 Write Thermal Throttling Condition. 1 = Write thermal throttling condition occurred. 0 = Software writes “1” to clear this bit. Default=0 AGP non-snoopable access outside of Graphics Aperture. 1 = AGP access occurred to the address that is outside of the graphics aperture range. 0 = Software writes “1” to clear this bit. Default=0 Invalid AGP non-snoopable DRAM read access (R/WC). 1 = AGP non-snoopable READ access was attempted outside of the graphics aperture and outside of main memory (i.e,. in 640 KB – 1 MB range or above top of memory). 0 = Software must write a “1” to clear this status bit. Access to Invalid Graphics Aperture Translation Table Entry (AIGATT) (R\WC). 1 = An invalid translation table entry was returned in response to a graphics aperture read or write access. 0 = Software must write a “1” to clear this bit. Not Applicable in the 82443ZX. Description 11 10 9 8 7:0 82443ZX Host Bridge Datasheet 3-35 Register Description 3.3.31 ACAPID—AGP Capability Identifier Register (Device 0) Address Offset: Default Value: Access: Size: A0–A3h 00100002h/00000000h Read Only 32 bits This register provides normal identifier for AGP capability. Bit 31:24 Reserved Major AGP Revision Number. This field provides a major revision number of AGP specification to which this version of the 82443ZX conforms. When the AGP DIS bit (PMCR[1]) is set to 0, this number is set to value of “0001b” (i.e., implying Rev 1.x). When the AGP DIS bit (PMCR[1]) is set to 1, This number is set to “0000b”. Minor AGP Revision Number. These bits provide a minor revision number of AGP specification to which this version of 82443ZX conforms. This number is hardwired to value of “0000” (i.e., implying Rev x.0). Together with major revision number this field identifies 82443ZX as an AGP REV 1.0 compliant device. Next Capability Pointer. AGP capability is the first and the last capability described via the capability pointer mechanism. 0s = Hardwired to 0s to indicate the end of the capability linked list. 7:0 AGP Capability ID. This field identifies the linked list item as containing AGP registers. When the AGP DIS bit (PMCR[1]) is set to 0, this field has a value of 0000_0010b assigned by the PCI SIG. When the AGP DIS bit (PMCR[1]) is set to 1, this field has a value of 00h. Description 23:20 19:16 15:8 3.3.32 AGPSTAT—AGP Status Register (Device 0) Address Offset: Default Value: Access: Size: A4–A7h 1F000203h Read Only 32 bits This register reports AGP compliant device capability/status. Bit 31:24 23:10 9 8:2 Description AGP Maximum Request Queue Depth (RO). This field is hardwired to 1Fh to indicate a maximum of 32 outstanding AGP command requests can be handled by the 82443ZX. Reserved AGP Side Band Addressing Supported. This bit indicates that the 82443ZX supports side band addressing. It is hardwired to 1. Reserved AGP Data Transfer Type Supported (R/W). Bit 0 identifies if AGP compliant device supports 1x data transfer mode and bit 1 identifies if AGP compliant device supports 2x data transfer mode. Configuration software will update this field by setting only one bit that corresponds to the capability of AGP master (after that capability has been verified by accessing the same functional register within the AGP masters configuration space). 1:0 00 = Not allowed 01 = 1x data transfer mode supported 10 = 2x data transfer mode supported 11 = (default) NOTE: The selected data transfer mode apply to both AD bus and SBA bus. 3-36 82443ZX Host Bridge Datasheet Register Description 3.3.33 AGPCMD—AGP Command Register (Device 0) Address Offset: Default Value: Access: Size: A8–ABh 00000000h Read/Write 32 bits This register provides control of the AGP operational parameters. Bit 31:10 9 Reserved. AGP Side Band Enable. This bit enables the side band addressing mechanism. 1 = Enable. 0 = Disable. AGP Enable. When disabled, the 82443ZX ignores all AGP operations, including the sync cycle. Any AGP operations received while this bit is set to 1 is serviced even if this bit is reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being delivered in 1X mode the command will be issued. When this bit is set to 1 the 82443ZX will respond to AGP operations delivered via PIPE#, or to operations delivered via SBA if the AGP Side Band Enable bit is also set to 1. The AGP parameters in the AGPCMD and AGPCTRL registers must be set prior to setting this bit ‘1’. With the exception of the GTLB_ENABLE (bit 7, AGPCTRL), and ATTBASE register (offset B8h), which can be modified dynamically. 1 = Enable. 0 = Disable. 7:2 Reserved. AGP Data Transfer Rate. One (and only one) bit in this field must be set to indicate the desired data transfer rate (Bit 0 for 1X, Bit 1 for 2X). The same bit must be set on both master and target. Configuration software will update this field by setting only one bit that corresponds to the capability of AGP master (after that capability has been verified by accessing the same functional register within the AGP masters configuration space.) 1:0 00 = default 01 = 1x data transfer rate. 10 = 2x data transfer rate. 11 = Illegal NOTE: This field applies to AD and SBA buses. Description 8 82443ZX Host Bridge Datasheet 3-37 Register Description 3.3.34 AGPCTRL—AGP Control Register (Device 0) Address Offset: Default Value: Access: Size: B0–B3h 00000000h Read/Write 32 bits This register provides for additional control of the AGP interface. Bit 31:16 Reserved. Snoopable Writes In Order With AGP Reads Disable (AGPDCD). When set to 0 (default), the 82443ZX maintains ordering between snoopable write cycles and AGP reads. When set to 1, the 82443ZX handles the AGP reads and snoopable writes as independent streams. 15 AGPDCD (Bit 15) 0 0 1 1 14 Reserved Graphics Aperture Write-AGP Read Synchronization Enable (AGPRSE). When this bit is set the 82443ZX will ensure that all writes posted in the Global Write Buffer to the Graphics Aperture are retired to DRAM before the 82443ZX will initiate any CPU-to-AGP cycle. This can be used to ensure synchronization between the CPU and AGP master. The AGPDCD bit description defines the interaction between the AGPRSE bit and the AGPDCD bit. 1 = Enable 0 = Disable (Default) 12:8 7 6:0 Reserved GTLB Enable (and GTLB Flush Control). 1 = Enable. Normal operations of the Graphics Translation Lookaside Buffer. 0 = Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry. Reserved. AGPRSE (Bit 13) 0 1 0 1 Description DWB is visible to AGP reads. DWB flushes only when address hit. Illegal. Illegal DWB flushes when write to AGP occurs Description 13 3-38 82443ZX Host Bridge Datasheet Register Description 3.3.35 APSIZE—Aperture Size Register (Device 0) Address Offset: Default Value: Access: Size: B4h 00h Read/Write 8 bits This register determines the effective size of the Graphics Aperture used for a particular 82443ZX configuration. This register can be updated by the 82443ZX-specific BIOS configuration sequence before the PCI normal bus enumeration sequence takes place. If the register is not updated, a default value selects an aperture of maximum size (i.e., 256 MB). The size of the table that will correspond to a 256 MB aperture is not practical for most applications and, therefore, these bits must be programmed to a smaller practical value that forces adequate address range to be requested via the APBASE register from the PCI configuration software. Bit 7:6 Reserved. Graphics Aperture Size (APSIZE) (R/W). Each bit in APSIZE[5:0] operates on similarly ordered bits in APBASE[27:22] of the Aperture Base configuration register. When a particular bit of this field is “0”, it forces the similarly ordered bit in APBASE[27:22] to behave as “hardwired” to 0. When a particular bit of this field is set to “1”, it allows corresponding bit of the APBASE[27:22] to be read/ write accessible. Only the following combinations are allowed: 11 1111 = 4 MB 11 1110 = 8 MB 11 1100 = 16 MB 5:0 11 1000 = 32 MB 11 0000 = 64 MB 10 0000 = 128 MB 00 0000 = 256MB Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., all bits respond as “hardwired” to 0). This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b and while enabling APBASE[27:25] as read/write programmable. Description 3.3.36 ATTBASE—Aperture Translation Table Base Register (Device 0) Address Offset: Default Value: Access: Size: B8–BBh 00000000h Read/Write 32 bits This register provides the starting address of the Graphics Aperture Translation Table base located in the main DRAM. The ATTBASE register may be dynamically changed. Note: The address provided via ATTBASE is 4KB aligned. Bit 31:12 11:0 Description Aperture Translation Table Base Address. Bits 31:12 correspond to address bits 31:12, respectively. This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main memory. Reserved. 82443ZX Host Bridge Datasheet 3-39 Register Description 3.3.37 MBFS—Memory Buffer Frequency Select Register (Device 0) Address Offset: Default Value: Access: Size: CA–CCh 000000h Read/Write 24 bits The settings in this register enable the 100 MHz or 66 MHz buffers for each of the following signal groups. Note: The choice of 100 MHz or 66 MHz buffer is independent of bus frequency. It is possible to select a 100 MHz memory buffer even though the bus frequency is 66 MHz (and vice versa). Bit 23 Reserved MAA[13:0], WEA#, SRASA#, SCASA# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for MAA[13:0], WEA#, SRASA#, SCASA#. 22 0 = 66 MHz 1 = 100 MHz 21 Not Applicable in the 82443ZX . MD [63:0] (100 MHz/66 MHz buffer select bit [Control 2]). This bit enables either 100 MHz or 66 MHz buffers for MD [63:0] [Control 2]. (Refer to the corresponding MBSC register for programming details). 0 = 66 MHz 1 = 100 MHz MD [63:0] (100 MHz/66 MHz buffer select bit [Control 1]). This bit enables either 100 MHz or 66 MHz buffers for MD [63:0] [Control 1]. (Refer to the corresponding MBSC register for programming details). 0 = 66 MHz 1 = 100 MHz 18:16 Not Applicable in the 82443ZX. CSA7#/CKE3 (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CSA7#/CKE3. 15 0 = 66 MHz 1 = 100 MHz 14 Not Applicable in the 82443ZX . CSA6#/CKE2 (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CSA6#/CKE2. 13 0 = 66 MHz 1 = 100 MHz 12:11 Not Applicable in the 82443ZX. CSA3#/RASA3#, CSB3#/RASB3# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CSA3#/RASA3#, CSB3#/RASB3#. 10 0 = 66 MHz 1 = 100 MHz CSA2#/RASA2#, CSB2#/RASB2# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CSA2#/RASA2#, CSB2#/RASB2#. 9 0 = 66 MHz 1 = 100 MHz Description 20 19 3-40 82443ZX Host Bridge Datasheet Register Description Bit Description CSA1#/RASA1#, CSB1#/RASB1# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CSA1#/RASA1#, CSB1#/RASB1#. 8 0 = 66 MHz 1 = 100 MHz CSA0#/RASA0#, CSB0#/RASB0# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CSA0#/RASA0#, CSB0#/RASB0#. 7 0 =66 MHz 1 = 100 MHz DQMA5/CASA5# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for DQMA5/CASA5#. 6 0 = 66 MHz 1 = 100 MHz DQMA1/CASA1# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for DQMA1/CASA1#. 5 0 = 66 MHz 1 = 100 MHz Not Applicable in the 82443ZX. DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for DQMA[7:6]/CASA[7:6]#, DQMA[4:2]/CASA[4:2]#, and the DQMA[0]/CASA[0]#. 0 = 66 MHz 1 = 100 MHz CKE1/GCKE (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers forCKE1. 4:3 2 1 0 = 66 MHz 1 = 100 MHz CKE0/FENA (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CKE0/FENA. 0 0 = 66 MHz 1 = 100 MHz 3.3.38 BSPAD—BIOS Scratch Pad Register (Device 0) Address Offset: Default Value: Access: Size: D0–D7h 0000-0000-0000-0000h Read/Write 64 bits This register provides 8 bytes general purpose read/write registers for the BIOS to perform the configuration routine. The 82443ZX will provide this 8 byte register in the PCI configuration space of the 82443ZX device0 on bus 0. The registers in this range will be defined as read/write and will be initialized to all 0’s after PCIRST#. The BIOS will can access these registers through the normal PCI configuration register mechanism, accessing 1,2 or 4 bytes in every data access. Bit 64:0 BIOS Work Space. Description 82443ZX Host Bridge Datasheet 3-41 Register Description 3.3.39 DWTC—DRAM Write Thermal Throttling Control Register (Device 0) Offset: Default: Access: Size: E0h–E7h 0000_0000_0000_0000h Read/Write/Lock 64 bits A locking mechanism is included to protect contents of this register as well as the DRAM Read Thermal Throttling Control register described below. Bits Description Throttle Lock (TLOCK). This bit secures the DRAM thermal throttling control registers. 63 1 = All configuration register bits in E0h–E7h and E8h–EFh (read throttle control) become readonly. 0 = Default 62:46 45:38 Reserved Global DRAM Write Sampling Window (GDWSW). This 8-bit value is multiplied by 4 to define the length of time in milliseconds (0–1020) over which the number of QWords written is counted. Global QWord Threshold (GQT). The 12-bit value held in this field is multiplied by 2^15 to arrive at the number of QWords that must be written within the Global DRAM Write Sampling Window in order to cause the thermal throttling mechanism to be invoked. Throttle Time (TT). This value provides a multiplier between 0 and 63 which specifies how long thermal throttling remains in effect as a number of Global DRAM Write Sampling Windows. For example, if GDWSW is programmed to 1000_0000b and TT is set to 01_0000b, then thermal throttling will be performed for ~2 seconds once invoked (128 ms * 16). Throttle Monitoring Window (TMW). The value in this register is padded with four 0’s to specify a window of 0–2047 DRAM CLKs with 16 clock granularity. While the thermal throttling mechanism is invoked, DRAM writes are monitored during this window—if the number of QWords written during the window reaches the Throttle QWord Maximum, then write requests are blocked for the remainder of the window. Throttle QWord Maximum (TQM). The Throttle QWord Maximum defines the maximum number of QWords between 0–1023 which are permitted to be written to DRAM within one Throttle Monitoring Window while the thermal throttling mechanism is in effect. DRAM Write Throttle Mode. Normal DRAM write monitoring and thermal throttling operation are enabled when bits 2:0 are set to 100. All other combinations are Intel Reserved. 2:0 000-011 = Intel Reserved 100 = Normal Operations 101-111 = Intel Reserved 37:26 25:20 19:13 12:3 3-42 82443ZX Host Bridge Datasheet Register Description 3.3.40 DRTC—DRAM Read Thermal Throttling Control Register (Device 0) Offset: Default: Access: Size: E8h–EFh 0000_0000_0000_0000h Read/Write/Lock 64 Bits The contents of this register are protected by making the bits read-only once a ‘1’ is written to the Throttle Lock bit (bit 63 of configuration register E0–E7h) Bits 63:46 45:38 Reserved Global DRAM Read Sampling Window (GDRSW). This 8-bit value is multiplied by 4 to define the length of time in milliseconds (0–1020) over which the number of QWords read from DRAM is counted. Global Read QWord Threshold (GRQT). The 12-bit value held in this field is multiplied by 2^15 to arrive at the number of QWords that must be written within the Global DRAM Read Sampling Window in order to cause the thermal throttling mechanism to be invoked. Read Throttle Time (RTT). This value provides a multiplier between 0 and 63 which specifies how long read thermal throttling remains in effect as a number of Global DRAM Read Sampling Windows. For example, if GDRSW is programmed to 1000_0000b and RTT is set to 01_0000b, then read thermal throttling will be performed for ~2 seconds once invoked (128 ms * 16). Read Throttle Monitoring Window (RTMW). The value in this register is padded with 4 0’s to specify a window of 0–2047 DRAM CLKs with 16 clock granularity. While the thermal throttling mechanism is invoked, DRAM reads are monitored during this window—if the number of QWords read during the window reaches the Throttle QWord Maximum, then Host and PCI read requests, as well as all AGP requests, are blocked for the remainder of the window. Read Throttle QWord Maximum (RTQM). The Read Throttle QWord Maximum defines the maximum number of QWords between 0–1023 which are permitted to be read from DRAM within one Read Throttle Monitoring Window while thermal throttling mechanism is in effect. DRAM Read Throttle Mode. Normal DRAM read monitoring and thermal throttling operation are enabled when bits 2:0 are set to 100. All other combinations are Intel Reserved. 2:0 000-011 = Intel Reserved 100 = Normal Operations 101-111 = Intel Reserved Description 37:26 25:20 19:13 12:3 82443ZX Host Bridge Datasheet 3-43 Register Description 3.3.41 BUFFC—Buffer Control Register (Device 0) Offset: Default: Access: Size: F0–F1h 0000h Read/Write 16 bits The Jam Latch design provides the AGP sub-system with a variable strength, to better accommodate the clamping requirements. The Jam Latch Register should be enabled by the BIOS during the resume sequence from STR, if these Jam Latch control bits had been enabled before the STR was executed. Bit 15:10 Reserved. AGP Jam Latch Strength Select. Bit 9 = 1; Enable strong pull-up 9:6 Bit 8 = 1; Enable weak pull-up Bit 7 = 1; Enable strong pull-down Bit 6 = 1; Enable weak pull-down 5:0 Intel Reserved. Description 3-44 82443ZX Host Bridge Datasheet Register Description 3.4 PCI-to-PCI Bridge Registers (Device 1) The configuration space for device #1 is controlled by the AGP_DIS bit in the PMCR register. Note: When AGP_DIS = 0, the configuration space for device #1 is enabled, and the registers defined below are accessible through the configuration mechanism defined in the first section of this document. When the AGP_DIS = 1, the configuration space for device #1 is disabled. All configuration cycles (reads and writes) to device #1 of bus 0 will cause the master abort status bit for device #0/ bus 0 to be set. Configuration read cycles will return data of all 1’s. Configuration write cycles will have no effect on the registers. Note: Table 3-4. 82443ZX Configuration Space—Device 1 Address Offset 00–01h 02–03h 04–05h 06–07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0F–17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1E–1Fh 20–21h 22–23h 24–25h 26–27h 28–3Dh 3Eh 3F–FFh Register Symbol VID1 DID1 PCICMD1 PCISTS1 RID1 — SUBC1 BCC1 — MLT1 HDR1 — PBUSN SBUSN SUBUSN SMLT IOBASE IOLIMIT SSTS MBASE MLIMIT PMBASE PMLIMIT — BCTRL — Register Name Vendor Identification Device Identification PCI Command Register PCI Status Register Revision Identification Reserved Sub-Class Code Base Class Code Reserved Master Latency Timer Header Type Reserved Primary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Bus Master Latency Timer I/O Base Address Register I/O Limit Address Register Secondary PCI-to-PCI Status Register Memory Base Address Register Memory Limit Address Register Prefetchable Memory Base Address Reg. Prefetchable Memory Limit Address Reg. Reserved Bridge Control Register Reserved Default Value 8086h 7191h 0000h 0220h 00/01h 00h 04h 06h 00h 00h 01h 00h 00h 00h 00h 00h F0h 00h 02A0h FFF0h 0000h FFF0h 0000h 0 80h 00h Access RO RO R/W RO, R/WC RO — RO RO — R/W RO — RO R/W R/W R/W R/W R/W R/WC, RO R/W R/W R/W R/W c R/W — 82443ZX Host Bridge Datasheet 3-45 Register Description 3.4.1 VID1—Vendor Identification Register (Device 1) Address Offset: Default Value: Attribute: Size: 00–01h 8086h Read Only 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 Description Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 3.4.2 DID1—Device Identification Register (Device 1) Address Offset: Default Value: Attribute: Size: 02–03h 7191h Read Only 16 bits This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Description Device Identification Number. This is a 16 bit value assigned to the 82443ZX device #1. 82443ZX device #1 DID =7191h. 3-46 82443ZX Host Bridge Datasheet Register Description 3.4.3 PCICMD1—PCI-to-PCI Command Register (Device 1) Address Offset: Default: Access: Size Bit 15:10 9 Reserved. Fast Back-to-Back: Not Applicable. Hardwired to 0. SERR# Enable (SERRE1). When enabled the SERR# signal driver (common for PCI and AGP) is enabled for error conditions that occur on AGP.If both SERRE and SERRE1 are reset to 0, then SERR# is never driven by the 82443ZX. Also, if this bit is set and the Parity Error Response Enable Bit (Dev 01h, Register 3Eh, Bit 0) is set, then the 82443ZX will report ADDRESS and DATA parity errors on AGP. 1 = Enable. 0 = Disable. 7 6 5 4 3 2 1 0 Address/Data Stepping. Not applicable. Hardwired to 0. Parity Error Enable (PERRE1). Hardwired to 0. Reserved. Memory Write and Invalidate Enable: Not applicable. However, supported as a read/write bit to avoid the problems with normal PCI-to-PCI Bridge configuration software. Special Cycle Enable: Not applicable. However, supported as a read/write bit to avoid the problems with normal PCI-to-PCI Bridge configuration software. Bus Master Enable (BME1): Not applicable. However, supported as a read/write bit to avoid the problems with normal PCI-to-PCI Bridge configuration software. Memory Access Enable (MAE1): Not applicable. However, supported as a read/write bit to avoid the problems with normal PCI-to-PCI Bridge configuration software. I/O Access Enable (IOAE1): Not applicable. However, supported as a read/write bit to avoid the problems with normal PCI-to-PCI Bridge configuration software. 04–05h 0000h Read/Write 16 bits Descriptions 8 82443ZX Host Bridge Datasheet 3-47 Register Description 3.4.4 PCISTS1—PCI-to-PCI Status Register (Device 1) Address Offset: Default Value: Access: Size: 06–07h 0220h Read Only, Read/Write Clear 16 bits PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the “virtual” PCI-to-PCI bridge embedded within the 82443ZX. Bit 15 14 13 12 11 10:9 8 7 6 5 4:0 Descriptions Detected Parity Error (DPE1). Not Applicable. Hardwired to 0. Reserved. Received Master Abort Status (RMAS1). Not Applicable. Hardwired to 0. Received Target Abort Status (RTAS1). Not Applicable. Hardwired to 0. Signaled Target Abort Status (STAS1). Not Applicable. Hardwired to 0. DEVSEL# Timing (DEVT1). Not Applicable. Hardwired to “01b”. Data Parity Detected (DPD1). Not Applicable. Hardwired to 0. Fast Back-to-Back (FB2B1). Not Applicable. Hardwired to 0. Reserved. 66/60 MHz Capability. Hardwired to “1”. Reserved. 3.4.5 RID1—Revision Identification Register (Device 1) Address Offset: Default Value: Access: Size: 08h 00/01h Read Only 8 bits This register contains the revision number of the 82443ZX device #1. These bits are read only and writes to this register have no effect. For the A-0 Stepping, this value is 00h. Bit Description Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the 82443ZX device #1. 02h = B1 stepping 7:0 3-48 82443ZX Host Bridge Datasheet Register Description 3.4.6 SUBC1—Sub-Class Code Register (Device 1) Address Offset: Default Value: Access: Size: 0Ah 04h Read Only 8 bits This register contains the Sub-Class Code for the 82443ZX device #1. This code is 04h indicating a PCI-to-PCI Bridge device. The register is read only. Bit Description Sub-Class Code (SUBC1). This is an 8-bit value that indicates the category of Bridge into which the 82443ZX falls. 04h = Host Bridge. 7:0 3.4.7 BCC1—Base Class Code Register (Device 1) Address Offset: Default Value: Access: Size: 0Bh 06h Read Only 8 bits This register contains the Base Class Code of the 82443ZX device #1. This code is 06h indicating a Bridge device. This register is read only. Bit Description Base Class Code (BASCC). This is an 8-bit value that indicates the Base Class Code for the 82443ZX device #1. 06h = Bridge device. 7:0 3.4.8 MLT1—Master Latency Timer Register (Device 1) Address Offset: Default Value: Access: Size: 0Dh 00h Read/Write 8 bits This functionality is not applicable. It is described here since these bits should be implemented as a read/write to comply with the normal PCI-to-PCI bridge configuration software. Bit 7:3 2:0 Description Not applicable but support read/write operations. (Reads return previously written data.) Reserved. 82443ZX Host Bridge Datasheet 3-49 Register Description 3.4.9 HDR1—Header Type Register (Device 1) Offset: Default: Access: Size: 0Eh 01h Read Only 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 Descriptions Header Type (HEADT). This read only field always returns 01h when read. Writes have no effect. 3.4.10 PBUSN—Primary Bus Number Register (Device 1) Offset: Default: Access: Size: 18h 00h Read Only 8 bits This register identifies that “virtual” PCI-to-PCI bridge is connected to bus #0. Bit 7:0 Bus Number. Hardwired to “0”. Descriptions 3.4.11 SBUSN—Secondary Bus Number Register (Device 1) Offset: Default: Access: Size: 19h 00h Read /Write 8 bits This register identifies the bus number assigned to the second bus side of the “virtual” PCI-to-PCI bridge i.e. to AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP. Bit 7:0 Bus Number. Programmable Default “0”. Descriptions 3-50 82443ZX Host Bridge Datasheet Register Description 3.4.12 SUBUSN—Subordinate Bus Number Register (Device 1) Offset: Default: Access: Size: 1Ah 00h Read /Write 8 bits This register identifies the subordinate bus (if any) that resides at the level below AGP.This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP. Bit 7:0 Bus Number. Programmable. Descriptions 3.4.13 SMLT—Secondary Master Latency Timer Register (Device 1) Address Offset: Default Value: Access: Size: 1Bh 00h Read/Write 8 bits This register control the bus tenure of the 82443ZX on AGP the same way the Device 0 MLT controls the access to the PCI bus. Bit 7:3 2:0 Description Secondary MLT Counter Value. The default is 0s (i.e,. SMLT disabled) Reserved. 3.4.14 IOBASE—I/O Base Address Register (Device 1) Address Offset: Default Value: Access: Size: 1Ch F0h Read/Write 8 bits This register control the CPU to AGP I/O access routing based on the following formula: IO_BASE=< address =