82541

82541 Family of Gigabit Ethernet Controllers Networking Silicon - 82541(PI/GI/EI) Datasheet Product Features ■ ■ ■ PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — CLK_RUN# signal — 3.3 V (5 V tolerant PCI signaling) MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers PHY Specific — Integrated for 10/100/1000 Mb/s full- and half-duplex operation — IEEE 802.3ab Auto-Negotiation and PHY compliance and compatibility — State-of-the-art DSP architecture implements digital adaptive equalization, echo and crosstalk cancellation — Automatic polarity detection — Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds ■ ■ ■ ■ Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation and advanced packed filtering — IEEE 802.1Q VLAN tag insertion and stripping and packet filtering for up to 4096 VLAN tags — Jumbo frame support up to 16 KB — Intelligent Interrupt generation (multiple packets per interrupt) Manageability — On-chip SMBus 2.0 port — ASF 1.0 and 2.0 — Compliance with PCI Power Management v1.1/ACPI v2.0 — Wake on LAN* (WoL) support — Smart Power Down mode when no signal is detected on the wire — Power Save mode switches link speed from 1000 Mb/s down to 10 or 100 Mb/s when on battery power Additional Device — Four programmable LED outputs — On-chip power regulator control circuitry — BIOS LAN Disable pin — JTAG (IEEE 1149.1) Test Access Port built in silicon (3.3 V, 5 V tolerant PCI signaling) Lead-freea 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at 1.8 V > 1.2V. This is important to avoid stress in the ESD protection circuits. After 3.3 V reaches 10% of its final value, all voltage rails (1.8 V and 1.2 V) have 150 ms to reach their final operating values. 3.3V Supply Voltage Ramp Parameter Rise Time Monotonicity Slope Operational Range Ripple Overshoot Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth equal to 50 MHz Maximum voltage allowed 3 Min 0.1 Max 100 0 28800 3.6 70 4 Unit ms mV V/s V mV V Table 3. Table 4. 1.8V Supply Voltage Ramp Symbol Rise Time Monotonicity Slope Operational Range Ripple Ripple Overshoot Parameter Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at frequency below 1 MHz Minimum voltage ripple at frequency below 1 MHz Maximum voltage allowed 1.55 2.2 1.71 Min 0.1 Max 100 0 57600 1.89 280 Unit ms mV V/s V mVpk-to-pk V V 20 Networking Silicon — 82541(PI/GI/EI) Table 4. 1.8V Supply Voltage Ramp Output Capacitance Input Capacitance Capacitance ESR Ictrl_18 Capacitance range when using PNP circuit Capacitance range when using PNP circuit Equivalent series resistance of output capacitancea Maximum output current rating to CTRL18 4.7 4.7 5 20 20 100 20 µF µF mΩ mA a. Tantalum capacitors must not be used. Table 5. 1.2V Supply Voltage Ramp Symbol Rise Time Monotonicity Slope Operational Range Ripple Ripple Overshoot Output Capacitance Input Capacitance Capacitance ESR Ictrl_12 Parameter Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at frequency below 1 MHz Maximum voltage ripple at frequency below 1 MHz Maximum voltage allowed Capacitance range when using PNP circuit Capacitance range when using PNP circuit Equivalent series resistance of output capacitancea Maximum output current rating to CTRL12 4.7 4.7 5 1 1.45 20 20 100 20 1.14 Min 0.025 0 38400 1.26 180 Max Unit ms mV V/s V mVpk-to-pk V V µF µF mΩ mA a. Tantalum capacitors must not be used. 21 82541(PI/GI/EI) — Networking Silicon 4.3 Table 6. DC Specifications DC Characteristics Symbol VDD (3.3) VDD (1.8) VDD (1.2) Parameter DC supply voltage on 3.3 V pins DC supply voltage on 1.8 V pins DC supply voltage on 1.2 V pins Condition Min 3.00 1.71a 1.14c Typ 3.3 1.8 1.2 Max 3.60 1.89b 1.26d Units V V V a. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.67 V. b. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is 1.926 V. c. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.12 V. d. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is 1.284 V. Table 7. Power Specifications - D0a D0a unplugged no link Typ Icc (mA)a 3.3 V 1.8 V 1.2 V Total Device Power 3 mA 14 mA 30 mA Max Icc (mA)b 5 mA 15 mA 35 mA @10 Mbps Typ Icc (mA)a 5 mA 85 mA 85 mA Max Icc (mA)b 10 mA 85 mA 90 mA @100 Mbps Typ Icc (mA)a 13 mA 110 mA 90 mA Max Icc (mA)b 15 mA 115 mA 100 mA @ 1000 Mbps Typ Icc (mA)a 30 mA 315 mA 380 mA Max Icc (mA)b 40 mA 320 mA 400 mA 75 mW 85 mW 270 mW 295 mW 350 mW 380 mW 1.1 W 1.2 W a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface. 22 Networking Silicon — 82541(PI/GI/EI) Table 8. Power Specifications - D3cold D3cold - wake-up enableda D3cold-wake disabled unplugged link Typ Icc (mA)b 3.3 V 1.8 V 1.2 V Total Device Power 2 mA 14 mA 21 mA Max Icc (mA)c 3 mA 15 mA 25 mA @10 Mbps Typ Icc (mA)a 2 mA 20 mA 30 mA Max Icc (mA)b 3 mA 25 mA 35 mA @100 Mbps Typ Icc (mA)a 2 mA 110 mA 80 mA Max Icc (mA)b 3 mA 115 mA 85 mA Typ Icc (mA)a 4 mA 1 mA 7 mA Max Icc (mA)b 5 mA 2 mA 10 mA 60 mW 70 mW 80 mW 100 mW 300 mW 320 mW 25 mW 35 mW a. At 1000 Mbps, power consumption is not shown since the controller switches to the 10/100 Mbps state before entering D3 to conserve power. b. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. c. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface. Table 9. Power Specifications D(r) Uninitialized D(r) Uninitialized (FLSH_SO/LAN_DISABLE# = 0) Typ Icc (mA) 3.3 V 1.8 V 1.2 V Total Device Power 5 mA 1 mA 12 mA Max Icc (mA) 10 mA 2 mA 15 mA 35 mW 23 82541(PI/GI/EI) — Networking Silicon Table 10. Power Specifications - Complete Subsystem Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits D3cold wake disabled Typ Icc (mA)a 3.3 V 1.8 V 1.2 V Sub-system Power 4 1 7 40 mW Max Icc (mA)b 5 2 10 60 mW D3cold wakeenabled @ 10 Mbps Typ Icc (mA)a 2 20 30 175 mW Max Icc (mA)b 3 25 35 210 mW D3cold wakeup enabled @ 100 Mbps Typ Icc (mA)a 6 110 80 650 mW Max Icc (mA)b 7 115 85 685 mW D0 @10 Mbps active Typ Icc (mA)a 7 85 85 585 mW Max Icc (mA)b 12 85 90 620 mW D0 @100 Mbps active Typ Icc (mA)a 19 110 90 725 mW Max Icc (mA)b 21 115 100 780 mW D0 @ 1000 Mbps active Typ Icc (mA)a 36 315 380 2.4 W Max Icc (mA)b 46 320 400 2.5 W a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface. Table 11. I/O Characteristics (Sheet 1 of 2) Symbol Parameter Condition 3.3 V PCI VIH Input high voltage SMB Non-SMBa VIL Input low voltage SMB Input current Input with pulldown resistor (50 K Ω) Inputs with pull-up resistor (50 K Ω) 0 < VIN < VDD (3.3) VIN = VDD (3.3) VSS -10 28 0.8 10 191 µA 2.1 VSS VDD (3.3) or VIO 0.3 * VDD (3.3) V Min 0.5 * VDD (3.3) Typ Max VDD (3.3) or VIO V Units IIN VIN = VSS 3.3 V PCIb -28 -191 2.09 100 * VOUT mA IOL Output low current 0 ≤ VOUT ≤ 3.6V 0 ≤ VOUT ≤ 1.3V 1.3V ≤ VOUT ≤ 3.6V 48 * VOUT 5.7 * VOUT+ 55 24 Networking Silicon — 82541(PI/GI/EI) Table 11. I/O Characteristics (Sheet 2 of 2) (Continued) Symbol Parameter Condition 0 ≤ (VDD-VOUT) ≤ 3.6V Output high current: 0 ≤ (VDD-VOUT) ≤ 1.2V 1.2V ≤ (VDD-VOUT) ≤ 1.9V 1.9V ≤ (VDD-VOUT) ≤ 3.6V VOH Output high voltage: 3.3 V PCI VOL Output low voltage: 3.3 V PCI IOZ IOS CIN Off-state output leakage current Output short circuit current Input capacitancec Input and bidirectional buffers 8 IOL = 1500 mA VO = VDD or VSS -10 0.1 * VDD (3.3) 10 -250 pF µA IOH = -500 mA 0.9 * VDD (3.3) V -32 * (VDD VOUT) -11 * (VDD VOUT)-25.2 -1.8 * (VDD VOUT)-42.7 V Min Typ Max -74 * (VDD VOUT) Units IOH mA a. This is only applicable to the 82541PI. The maximum VIL is 0.6 V for the following pins: A13, C5, C8, J4, L7, L13, L12, M8, M12, M13, N10, N11, N13, N14, P9, and P13. b. This is only applicable to the 82541PI. c. VDD (3.3) = 0 V; TA = 25 C; f = 1 Mhz 4.4 AC Characteristics Table 12. AC Characteristics: 3.3 V Interfacing Symbol CLK Parameter Clock frequency in PCI mode Min Typ Max 66 Unit MHz Table 13. 25 MHz Clock Input Requirements Specifications Symbol f0 df0 Dc tr tf Jptp Frequency Frequency variation Duty cycle Rise time Fall time Clock jitter (peak-to-peak) a Parameter Min Typ 25 -50 40 +30 60 5 5 250 Max Units MHz ppm % ns ns ps 25 82541(PI/GI/EI) — Networking Silicon Table 13. 25 MHz Clock Input Requirements Specifications Symbol Cin T Aptp Vcm Parameter Min Input capacitance Operating temperature Input clock amplitude (peak-to-peak) Clock common mode 1.0 1.2 0.6 Typ 20 70 1.3 Max pF °C V V Units a. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000BASE-T Standard (at least 105 clock edges, filtered by HPF with cut off frequency 5000 Hz). Table 14. Reference Crystal Specification Requirements Specification Vibrational Mode Nominal Frequency Fundamental 25.000 MHz at 25° C • ±30 ppm recommended Frequency Tolerance • ±30 ppm required for the 82541GI/EI • ±50 ppm across the entire operating temperature range (required by IEEE specifications) Temperature Stability Calibration Mode Load Capacitance Shunt Capacitance Equivalent Series Resistance Drive Level Aging • ±50 ppm at 0° C to 70° C • ±30 ppm at 0° C to 70° C (required for the 82541GI/EI) Parallel • 16 pF to 20 pF • 18 pF (required for the 82541GI/EI) 6 pF maximum • 50 Ω maximum • 20 Ω maximum (required for the 82541GI/EI) 0.5 mW maximum ±5 ppm per year maximum Value Table 15. Link Interface Clock Requirements Symbol fGTXa Parameter GTX_CLK frequency Min Typ 125 Max Unit MHz a. GTX_CLK is used externally for test purposes only. Table 16. EEPROM Interface Clock Requirements Symbol fSK SPI EEPROM Clock 2 MHz Parameter Microwire EEPROM Clock Min Typ Max 1 Unit MHz 26 Networking Silicon — 82541(PI/GI/EI) AC Test Loads for General Output Pins Symbol CL CL CL CL TDO PME#, SDP[3:0] EEDI, EESK LED[3:0] Signal Name Value 10 16 18 20 Units pF pF pF pF Figure 3. AC Test Loads for General Output Pins CL 4.5 Timing Specifications Table 17. PCI Bus Interface Clock Parameters PCI 66 MHz Symbol TCYC TH TL Parametera Min CLK cycle time CLK high time CLK low time CLK slew rate RST# slew rate b PCI 33 MHz Units Min 30 11 11 Max ns ns ns 4 V/ns mV/ns Max 30 15 6 6 1.5 50 4 1 50 a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown. b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot render a monotonic signal to appear bouncing in the switching range. 27 82541(PI/GI/EI) — Networking Silicon Figure 4. AC Test Loads for General Output Pins Tcyc 3.3 V Clock Th 0.6 Vcc 0.4 Vcc p-to-p (minimum) 0.5 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc Tl Table 18. PCI Bus Interface Timing Parameters PCI 66MHz Symbol Parameter Min TVAL TVAL(ptp) TON TOFF TSU TSU(ptp) TH CLK to signal valid delay: bussed signals CLK to signal valid delay: pointto-point signals Float to active delay Active to float delay Input setup time to CLK: bussed signals Input setup time to CLK: point-topoint signals Input hold time from CLK 3 5 0 2 2 2 14 7 10, 12 0 Max 6 6 Min 2 2 2 28 Max 11 12 ns ns ns ns ns ns ns PCI 33 MHz Units NOTES: 1. Output timing measurements are as shown. 2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed. 3. Input timing measurements are as shown. 28 Networking Silicon — 82541(PI/GI/EI) Figure 5. AC Test Loads for General Output Pins VTH CLK VTEST VTL Output Delay _ output current < leakage current VTEST VSTEP (3.3 V Signalling) Tri-State Output TON T OFF Figure 6. AC Test Loads for General Output Pins VTH CLK VTEST VTL TSU VTH Input VTL VTEST Input Valid VTEST VMAX TH Table 19. PCI Bus Interface Timing Measurement Conditions Symbol VTH VTL VTEST Parameter Input measurement test voltage (high) Input measurement test voltage (low) Output measurement test voltage Input signal slew rate PCI 66 MHz 3.3 v 0.6 * VCC 0.2 * VCC 0.4 * VCC 1.5 Unit V V V V/ns 29 82541(PI/GI/EI) — Networking Silicon Figure 7. TVAL (max) Rising Edge Test Load Pin 1/2 inch max. Test Point 25Ω 10 pF Figure 8. TVAL (max) Falling Edge Test Load Pin 1/2 inch max. Test Point 10 pF 25Ω VCC Figure 9. TVAL (min) Test Load Pin 1/2 inch max. Test Point 1kΩ 10 pF 1kΩ VCC 30 Networking Silicon — 82541(PI/GI/EI) Figure 10. TVAL Test Load (PCI 5 V Signaling Environment) Pin 1/2 inch max. Test Point 50 pF NOTE: 50 pF load used for maximum times. Minimum times are specified with 0 pF load. Table 20. Link Interface Rise and Fall Times Symbol TR TF TR TF Parameter Clock rise time Clock fall time Data rise time Data fall time Condition 0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 V to 2.0 V 2.0 V to 0.8 V Min 0.7 0.7 0.7 0.7 Max Unit ns ns ns ns Figure 11. Link Interface Rise/Fall Timing 2.0 V 0.8 V TR TF 31 82541(PI/GI/EI) — Networking Silicon Table 21. EEPROM Link Interface Clock Requirements Symbol Parametera Microwire EESK pulse width TPW SPI EESK pulse width a. The EEPROM clock is derived from a 125 MHz internal clock. TPERIOD x Min Typ TPERIOD x 64 32 Max Unit ns ns Table 22. EEPROM Link Interface Clock Requirements Symbol TDOS TDOH Parametera EEDO setup time EEDO hold time Min TCYC*2 0 Typ Max Unit ns ns a. The EEDO setup and hold time is a function of the PCI bus clock cycle time but is referenced to O_EESK. 32 Networking Silicon — 82541(PI/GI/EI) 5.0 Package and Pinout Information This section describes the 82541(PI/GI/EI) device physical characteristics. The pin number-tosignal mapping is indicated beginning with Table 14. 5.1 Package Information The 82541(PI/GI/EI) device is a 196-lead plastic ball grid array (BGA) measuring 15 mm by 15 mm. The package dimensions are detailed below. The nominal ball pitch is 1 mm. 1.56 +/-0.19 0.85 30 o 0.40 +/-0.10 0.32 +/-0.04 Seating Plate Figure 11. 82541(PI/GI/EI) Mechanical Specifications Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. 33 82541(PI/GI/EI) — Networking Silicon Detail Area 0.45 Solder Resist Opening 0.60 Metal Diameter Figure 12. 196 PBGA Package Pad Detail As illustrated in Figure 12, the Ethernet controller package uses solder mask defined pads. The copper area is 0.60 mm and the opening in the solder mask is 0.45 mm. The nominal ball sphere diameter is 0.50 mm. 34 Networking Silicon — 82541(PI/GI/EI) 5.2 Thermal Specifications The 82541(PI/GI/EI) device is specified for operation when the ambient temperature (TA) is within the range of 0° C to 70° C. TC (case temperature) is calculated using the equation: TC = TA + P (θJA - θJC) TJ (junction temperature) is calculated using the equation: TJ = TA + P θJA P (power consumption) is calculated by using the typical ICC, as indicated in Table 7 of Section 4.0, and nominal VCC. The preliminary thermal resistances are shown in Table 13. Table 13. Thermal Characteristics Symbol Parameter Preliminary Value at specified airflow (m/s) 0 θJA θJC Thermal resistance, junction-to-ambient Thermal resistance, junction-to-case 29 11.1 1 25.0 11.1 2 23.5 11.1 C/Watt C/Watt Units Thermal resistances are determined empirically with test devices mounted on standard thermal test boards. Real system designs may have different characteristics due to board thickness, arrangement of ground planes, and proximity of other components. The case temperature measurements should be used to assure that the 82541(PI/GI/EI) device is operating under recommended conditions. 35 82541(PI/GI/EI) — Networking Silicon 5.3 Pinout Information Table 14. PCI Address, Data and Control Signals Signal AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] Pin N7 M7 P6 P5 N5 M5 P4 N4 P3 N3 N2 M1 M2 M3 L1 L2 Signal AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] PAD[28] AD[29] AD[30] AD[31] Pin K1 E3 D1 D2 D3 C1 B1 B2 B4 A5 B5 B6 C6 C7 A8 B8 Signal C/BE#[0] C/BE#[1] C/BE#[2] C/BE#[3] PAR FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL VIO Pin M4 L3 F3 C4 J1 F2 F1 G3 H1 H3 A4 G2 Table 15. PCI Arbitration Signals Signal REQ# GNT# Pin C3 J3 Table 16. Interrupt Signals Signal INTA# Pin H2 Table 17. System Signals Signal CLK M66EN Pin G1 C2 RST# CLK_RUN# Signal Pin B9 C8 36 Networking Silicon — 82541(PI/GI/EI) Table 18. Error Reporting Signals Signal SERR# Pin A2 Signal PERR# Pin J2 Table 19. Power Management Signals Signal PME# LAN_PWR_GOOD Pin A6 A9 Signal AUX_PWR Pin J12 Table 20. SMB Signals Signal SMBCLK Pin A10 Signal SMBDATA Pin C9 Signal SMB_ALERT# Pin B10 Table 21. Serial EEPROM Interface Signals Signal EESK EEDO Pin M10 N10 EEDI EEMODE Signal Pin P10 J4 Signal EECS Pin P7 Table 22. Serial FLASH Interface Signals Signal FLSH_SCK FLSH_SO/LAN_DISABLE# Pin N9 P9 Signal FLSH_SI Pin M11 Signal FLSH_CE# Pin M9 Table 23. LED Signals Signal LED0 / LINK_UP# LED1 / ACTIVITY# Pin A12 C11 Signal LED2 / LINK100# LED3 / LINK1000# Pin B11 B12 37 82541(PI/GI/EI) — Networking Silicon Table 24. Other Signals Signal SDP[0] SDP[1] N14 P13 Pin Signal SDP[2] SDP[3] N13 M12 Pin Table 25. IEEE Test Signals Signal IEEE_TESTPin D14 Signal IEEE_TEST+ Pin B14 Table 26. PHY Signals Signal MDI[0]MDI[0]+ MDI[1]MDI[1]+ C14 C13 E14 E13 Pin Signal MDI[2]MDI[2]+ MDI[3]MDI[3]+ F14 F13 H14 H13 Pin Signal XTAL1 XTAL2 K14 J14 Pin Table 27. Test Interface Signals Signal JTAG_TCK JTAG_TDI Pin L14 M13 Signal JTAG_TDO JTAG_TMS Pin M14 L12 Signal JTAG_TRST# TEST Pin L13 A13 Table 28. Digital Power Signals (Sheet 1 of 2) Signal 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V A3 A7 A11 E1 K3 K4 K13 N6 N8 Pin 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Signal G5 G6 H5 H6 H7 H8 J10 J11 J5 Pin 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Signal J9 K10 K11 K5 K6 K7 K8 K9 L10 Pin 38 Networking Silicon — 82541(PI/GI/EI) Table 28. Digital Power Signals (Sheet 2 of 2) (Continued) Signal 3.3V 3.3V P2 P12 Pin 1.2V 1.2V 1.2V Signal J6 J7 J8 Pin 1.2V 1.2V 1.2V Signal L4 L5 L9 Pin Table 29. Analog Power Signals Signal ANALOG_1.2V ANALOG_1.2V ANALOG_1.2V ANALOG_1.2V E11 E12 G13 H11 Pin Signal ANALOG_1.8V ANALOG_1.8V PLL_1.2V PLL_1.2V D11 G12 G4 H4 Pin Signal CLKR_1.8V XTAL_1.8V D12 J13 Pin Table 30. Grounds and No Connect Signals Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin B3 B7 C10 D5 D6 D7 D8 E10 E2 E5 E6 E7 E8 E9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal Pin F10 F4 F5 F6 F7 F8 F9 G10 G7 G8 G9 H10 H9 K2 Signal VSS VSS VSS VSS VSS VSS AVSS AVSS AVSS AVSS AVSS AVSS NC NC Pin L11 L6 M6 N1 N12 P8 C12 D13 F11 G11 G14 K12 A1 A14 Signal NC NC NC NC NC NC RSVD_NC RSVD_NC RSVD_NC RSVD_NC RSVD_NC RSVD_VSS RSVD_VSS Pin D10 D9 H12 L8 P1 P14 C5 L7 M8 N11 F12 D4 E4 Table 31. Voltage Regulation Control Signals Signal CTRL18 Pin B13 Signal CTRL12 Pin P11 39 82541(PI/GI/EI) — Networking Silicon Table 32. Signal Names in Pin Order (Sheet 1 of 6) Signal Name NC SERR# 3.3V IDSEL AD[25] PME# 3.3V AD[30] LAN_PWR_GOOD SMBCLK 3.3V LED0 / LINK_UP# TEST NC AD[22] AD[23] VSS AD[24] AD[26] AD[27] VSS AD[31] RST# SMB_ALERT# LED2 / LINK100# LED3 / LINK1000# CTRL18 IEEE_TEST+ AD[21] M66EN REQ# C/BE#[3] RSVD_NC Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 40 Networking Silicon — 82541(PI/GI/EI) Table 32. Signal Names in Pin Order (Sheet 2 of 6) (Continued) Signal Name AD[28] AD[29] CLK_RUN# SMBDATA VSS LED1 / ACTIVITY# AVSS MDI[0]+ MDI[0]AD[18] AD[19] AD[20] RSVD_VSS VSS VSS VSS VSS NC NC ANALOG_1.8V CLKR_1.8V AVSS IEEE_TEST3.3V VSS AD[17] RSVD_VSS VSS VSS VSS VSS VSS VSS ANALOG_1.2V ANALOG_1.2V Pin C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 41 82541(PI/GI/EI) — Networking Silicon Table 32. Signal Names in Pin Order (Sheet 3 of 6) (Continued) Signal Name MDI[1]+ MDI[1]IRDY# FRAME# C/BE#[2] VSS VSS VSS VSS VSS VSS VSS AVSS RSVD_NC MDI[2]+ MDI[2]CLK VIO TRDY# PLL_1.2V 1.2V 1.2V VSS VSS VSS VSS AVSS ANALOG_1.8V ANALOG_1.2V AVSS STOP# INTA# DEVSEL# PLL_1.2V 1.2V Pin E13 E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 42 Networking Silicon — 82541(PI/GI/EI) Table 32. Signal Names in Pin Order (Sheet 4 of 6) (Continued) Signal Name 1.2V 1.2V 1.2V VSS VSS ANALOG_1.2V NC MDI[3]+ MDI[3]PAR PERR# GNT# EEMODE 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AUX_PWR XTAL_1.8V XTAL2 AD[16] VSS 3.3V 3.3V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AVSS Pin H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 43 82541(PI/GI/EI) — Networking Silicon Table 32. Signal Names in Pin Order (Sheet 5 of 6) (Continued) Signal Name 3.3V XTAL1 AD[14] AD[15] C/BE#[1] 1.2V 1.2V VSS RSVD_NC NC 1.2V 1.2V VSS JTAG_TMS JTAG_TRST# JTAG_TCK AD[11] AD[12] AD[13] C/BE#[0] AD[5] VSS AD[1] RSVD_NC FLSH_CE# EESK FLSH_SI SDP[3] JTAG_TDI JTAG_TDO VSS AD[10] AD[9] AD[7] AD[4] Pin K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 44 Networking Silicon — 82541(PI/GI/EI) Table 32. Signal Names in Pin Order (Sheet 6 of 6) (Continued) Signal Name 3.3V AD[0] 3.3V FLSH_SCK EEDO RSVD_NC VSS SDP[2] SDP[0] NC 3.3V AD[8] AD[6] AD[3] AD[2] EECS VSS FLSH_SO EEDI CTRL12 3.3V SDP[1] NC Pin N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 45 82541(PI/GI/EI) — Networking Silicon 5.4 A 1 NC Visual Pin Assignments B AD[22] C AD[21] D AD[18] E 3.3V F IRDY# G CLK H STOP# J PAR K AD[16] L AD[14] M AD[11] N VSS P NC 2 SERR# AD[23] M66EN AD[19] VSS FRAME# VIO INTA# PERR# VSS AD[15] AD[12] AD[10] 3.3V 3 3.3V VSS REQ# AD[20] AD[17] C/BE#[2] TRDY# DVSEL# GNT# 3.3V C/B3#[1] AD[13] AD[9] AD[8] 4 IDSEL AD[24] C/BE#[3] RSVD_ VSS RSVD_ VSS VSS PLL_ 1.2V PLL_ 1.2V EEMODE 3.3V 1.2V C/BE#[0] AD[7] AD[6] 5 AD[25] AD[26] RSVD_ NC VSS VSS VSS 1.2V 1.2V 1.2V 1.2V 1.2V AD[5] AD[4] AD[3] 6 PME# AD[27] AD[28] VSS VSS VSS 1.2V 1.2V 1.2V 1.2V VSS VSS 3.3V AD[2] 7 3.3V VSS AD[29] VSS VSS VSS VSS 1.2V 1.2V 1.2V RSVD_ NC AD[1] AD[0] EECS 8 AD[30] AD[31] CLK_ RUN# VSS VSS VSS VSS 1.2V 1.2V 1.2V NC RSVD_ NC 3.3V VSS 9 LAN_ PWR_ GOOD RST# SMBDATA NC VSS VSS VSS VSS 1.2V 1.2V 1.2V FLSH_ CE# FLSH_ SCK FLSH_ SO 10 SMBCLK SMB_ ALERT VSS NC VSS VSS VSS VSS 1.2V 1.2V 1.2V EESK EEDO EEDI 11 3.3V LED2/ LINK 100# LED3/ LINK 1000# LED1/ ACTIVITY# ANALOG_ 1.8V ANALOG_ 1.2V AVSS AVSS ANALOG_ 1.2V 1.2V 1.2V VSS FLSH_ SI RSVD_ NC CTRL12 12 LED0/ LINK_ UP# AVSS CLKR_ 1.8V ANALOG_ 1.2V RSVD_ NC ANALOG_ 1.8V NC AUX_ PWR AVSS JTAG_ TMS SDP[3] VSS 3.3V 13 TEST CTRL18 MDI[0]+ AVSS MDI[1]+ MDI[2]+ ANALOG_ 1.2V MDI[3]+ XTAL_ 1.8V 3.3V JTAG_ TRST# JTAG_ TDI SDP[2] SDP[1] 14 NC IEEE_ TEST+ MDI[0]- IEEE_ TEST- MDI[1]- MDI[2]- AVSS MDI[3]- XTAL2 XTAL1 JTAG_ TCK JTAG_ TDO SDP[0] NC Figure 13. Visual Pin Assignments 46