82573 Family of GbE Controllers
Datasheet
Product Features
PCIe*
— — — — x1 PCIe* interface on ICH7 or MCH devices Peak bandwidth: 2 Gb/s per direction Power management High bandwidth density per pin
Manageability
MAC
— Optimized transmit and receive queues — IEEE 802.3x compliant flow control with software controlled pause times and threshold values — Caches up to 64 packet descriptors per queue — Programmable host memory receive buffers (256 bytes to 16 KB) and cache line size (16 bytes to 256 bytes) — 32 KB configurable transmit and receive FIFO buffer — Mechanism available for reducing interrupts generated by transmit and receive operation — Descriptor ring management hardware for transmit and receive — Optimized descriptor fetching and write-back mechanisms — Wide, pipelined internal data path architecture
— Intel® Active Management Technology (Intel® AMT) support (82573E only) — Alerting Standards Format 2.0 and advanced pass through support (82573E/V only) — Boot ROM Preboot eXecution Environment (PXE) Flash interface support — Compliance with PCI Power Management 1.1 and Advanced Configuration and Power Interface (ACPI) 2.0 register set compliant — Wake on LAN support
Additional
PHY
— Integrated PHY for 10/100/1000 Mb/s full and half duplex operation — IEEE 802.3ab auto negotiation support — IEEE 802.3ab PHY compliance and compatibility
— Three activity and link indication outputs that directly drive LEDs — Programmable LEDs — Internal PLL for clock generation that can use a 25 MHz crystal — Power saving feature for the 82573L. During the L1 and L2 link states, the 82573L asserts the Clock Request signal (CLKREQ#) to indicate that its PCIe* reference clock can be gated — On-chip power control circuitry — Loopback capabilities — JTAG (IEEE 1149.1) Test Access Port (TAP) built in silicon
Technology
— DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation Host Offloading
— Lead-free 196-pin Thin and Fine Pitch Ball Grid Array (TF-BGA) package — Operating temperature: 0° C to 70° C (with external regulators) — Operating temperature: 0° to 55° C (with ondie 2.5V regulator) — Storage temperature -40° C to 125° C
— Transmit and receive IP, TCP and UDP checksum off-loading capabilities — Transmit TCP segmentation, IPv6 offloading, and advanced packet filtering — IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags — Descriptor ring management hardware for transmit and receive
Order Number: 315514-002 Revision 2.5
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Legal Lines and Disclaimers
Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. IMPORTANT - PLEASE READ BEFORE INSTALLING OR USING INTEL® PRE-RELEASE PRODUCTS. Please review the terms at http://www.intel.com/netcomms/prerelease_terms.htm carefully before using any Intel® pre-release product, including any evaluation, development or reference hardware and/or software product (collectively, “Pre-Release Product”). By using the Pre-Release Product, you indicate your acceptance of these terms, which constitute the agreement (the “Agreement”) between you and Intel Corporation (“Intel”). In the event that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. The 82573 GbE Controllers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/ products/ht/Hyperthreading_more.htm for additional information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Intel Corporation. All Rights Reserved.
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Datasheet—82573
Contents
1.0 Introduction .............................................................................................................. 7 1.1 Document Scope ................................................................................................. 8 1.2 Reference Documents .......................................................................................... 8 1.3 82573 Architecture ............................................................................................. 9 1.4 Product Codes for the 82573............................................................................... 10 Signal Descriptions .................................................................................................. 10 2.1 Signal Type Definitions....................................................................................... 10 2.2 PCIe* Data Signals ............................................................................................ 11 2.3 PCIe* Miscellaneous Signals ............................................................................... 11 2.4 Non-Volatile Memory Interface Signals ................................................................. 12 2.5 Miscellaneous Signals ........................................................................................ 12 2.5.1 Reset and Power-down Signals................................................................. 12 2.5.2 System Management Bus (SMBus) Signals................................................. 13 2.5.3 LED Signals ........................................................................................... 13 2.5.4 Other Signals......................................................................................... 13 2.6 PHY Analog and Crystal Signals ........................................................................... 14 2.7 Test Signals...................................................................................................... 15 2.7.1 MAC Test Signals.................................................................................... 15 2.7.2 PHY Test Signals .................................................................................... 15 2.7.3 Other Test Signals .................................................................................. 15 2.8 Power Signals ................................................................................................... 16 2.8.1 Power Support Signals ............................................................................ 16 2.8.2 Digital and Analog Power Supply Signals ................................................... 16 2.9 Grounds and No Connects .................................................................................. 16 Voltage, Temperature, and Timing Specifications .................................................... 17 3.1 Absolute Maximum Ratings ................................................................................. 17 3.2 Recommended Operating Conditions .................................................................... 17 3.3 Power Supply Connections .................................................................................. 17 3.3.1 External LVR Power Delivery .................................................................... 18 3.3.2 Power Sequencing with External Regulators ............................................... 19 3.3.3 Internally Generated Power Delivery ......................................................... 20 3.3.4 Internal LVR Power Sequencing ................................................................ 21 3.4 DC and AC Specifications.................................................................................... 25 3.5 External Interfaces ............................................................................................ 28 3.5.1 Crystal.................................................................................................. 28 3.5.2 External Clock Oscillator ......................................................................... 28 3.5.3 Non-Volatile Memory (NVM) Interface: EEPROM ......................................... 29 Package and Pinout Information ............................................................................. 30 4.1 Package Information.......................................................................................... 30 4.2 Thermal Specifications ....................................................................................... 32 4.3 Pinout Information ............................................................................................ 33 4.3.1 PCIe Bus Interface Signals....................................................................... 33 4.3.2 Non-Volatile Memory Interface Signals ...................................................... 34 4.3.3 Miscellaneous Signals ............................................................................. 34 4.3.4 PHY Signals ........................................................................................... 35 4.3.5 Test Signals........................................................................................... 35 4.3.6 Power Supply Signals.............................................................................. 36 4.4 Visual Pin Assignments....................................................................................... 38
2.0
3.0
4.0
3
82573—Datasheet
Figures
1 2 3 4 5 6 7 8 9 82573 Block Diagram................................................................................................. 9 Minimum Requirements for Power Supply Sequencing ...................................................20 Power Supply Sequencing..........................................................................................21 82573 2.5V and 1.2V LVR Schematic ..........................................................................25 External Clock Oscillator Connectivity to the 82573 .......................................................29 82573 Controller TF-BGA Package Ball Pad Dimensions..................................................30 82573 Mechanical Specifications .................................................................................31 82573E and 82573V Gigabit Ethernet Controller Pinout..................................................38 82573L Gigabit Ethernet Controller Pinout....................................................................39
4
Datasheet—82573
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Absolute Maximum Ratings ....................................................................................... 17 Recommended Operating Conditions........................................................................... 17 3.3V External Supply Voltage Ramp and Sequencing Recommendations .......................... 18 2.5V External Supply Voltage Ramp and Sequencing Recommendations .......................... 18 1.2V External Supply Voltage Ramp and Sequencing Recommendations .......................... 19 3.3V Internal Power Supply Parameters ...................................................................... 20 82573 Bill of Materials (BOM) of Components for Internal Regulator................................ 22 2.5V Internal LVR Specification .................................................................................. 22 1.2V Internal LVR Specification .................................................................................. 23 PNP Specification ..................................................................................................... 23 82573E and 82573V Maximum Measured External Power Characteristics ......................... 25 82573E and 82573V Typical Measured External Power Characteristics ............................. 26 82573E and 82573V 2.5V Internal Power Regulator Numbers......................................... 26 82573L Maximum Measured Power Characteristics ....................................................... 27 82573L Measured Power Characteristics ...................................................................... 27 DC Specifications ..................................................................................................... 27 LED DC Specifications............................................................................................... 28 Crystal Specifications................................................................................................ 28 Specification for External Clock Oscillator .................................................................... 29 NVM Interface Timing Specifications for EEPROM .......................................................... 29 Thermal Resistance Values ........................................................................................ 33 PCIe Data Signals .................................................................................................... 33 PCI Express Miscellaneous Signals .............................................................................. 34 Non-Volatile Memory Interface Signals........................................................................ 34 Reset and Power-down Signals .................................................................................. 34 SMBus Signals ......................................................................................................... 34 LED Signals............................................................................................................. 34 Other Signals .......................................................................................................... 34 Analog and Crystal Signals ........................................................................................ 35 82573E/V MAC Test Signals....................................................................................... 35 82573L MAC Test Signals .......................................................................................... 35 PHY Test Interface Signals ........................................................................................ 35 82573E/V Other Test Signals ..................................................................................... 36 Power Support Signals .............................................................................................. 36 Power Signals.......................................................................................................... 36 Ground Signals ........................................................................................................ 37 82573E/V No Connect Signals.................................................................................... 37 82573L No Connect Signals ....................................................................................... 37
5
82573—Datasheet
Revision History
Date Jan 2007
Revision 2.5
Description Updated the PHY_REF signal description in Section 2.6. Added document order number. Corrected the AUX_PWR pin (C6) description for the 82573E/V. Updated Table 18 “Crystal Specifications”. Updated the visual pin assignments for the 82573L. Major edit all sections. Chapter 1, Introduction, corrected note. 3.5.1, Removed line item 3.5.2, Corrected title Heading Revised Section 3.3, ’PCIe Miscellaneous Signals", updated Intel logo. Added Section 5.2, ’Thermal Specifications".” Integrated 82573L information into this document. Initial public release.
Oct 2006
2.4
August 2006 June 2006 Feb 2006 Sept 2005 June 2005
2.3 2.2 2.1 2.0 1.5
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Datasheet—82573
1.0
Note:
Introduction
Unless specifically noted, 82573 refers to the Intel® 82573E, 82573V and 82573L GbE controllers. 82573 GbE controllers are single, compact components with integrated Gigabit Ethernet Media Access Control (MAC) and Physical Layer (PHY) functions. These devices use PCIe* architecture (Revision 1.0a). For desktop, workstation, and value server network designs with critical space constraints, the 82573 enables a GbE implementation in a very small area. The 82573 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab, respectively). In addition to managing MAC and PHY Ethernet layer functions, the 82573 manages PCIe* packet traffic across its transaction, link, and physical and logical layers. The 82573E contains a dedicated microcontroller for manageability with an on-board Intel® Active Management Technology (Intel® AMT) enabling network. This enables manageability implementations required by information technology personnel for outof-band management, remote troubleshooting and recovery, asset management, and non-volatile storage. Intel® AMT is the first step towards a complete Intel® CrossPlatform Manageability Program (Intel® CPMP), which is a business and technology initiative to deliver consistent management capabilities, protocols, and interfaces across all Intel platforms. The 82573E and 82573V GbE controllers have an integrated System Management Bus (SMBus) port enabling industry standards, such as the Alert Standard Forum (ASF) 2.0. With SMBus, management packets can be routed to or from a management processor. In addition, integrated ASF 2.0 circuitry provides alerting and capabilities with standardized interfaces. The 82573 with PCIe* architecture is designed for high performance and low memory latency. The device is optimized to connect to a system I/O Control Hub (ICH7) using one PCIe* lane. Alternatively, the 82573 is able to connect to a Memory Control Hub (MCH) device with a PCIe* interface. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82573 efficiently handles packets with minimum latency by combining a parallel and pipelined logic architecture optimized for GbE and independent transmit and receive queues. The 82573 also includes advanced interrupt handling features and uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors per queue cached on chip. A 32-KB on-chip packet buffer maintains superior performance. In addition, using hardware acceleration, the 82573 offloads tasks from the host (for example, TCP/UDP/IP checksum calculations and TCP segmentation). The 82573L features low power management. During the L1 and L2 link states, the 82573L asserts the Clock Request signal (CLKREQ#) to indicate that its PCIe* reference clock can be gated. The 82573 is packaged in a 15 mm X 15 mm, 196-Ball Grid Array (BGA).
7
82573—Datasheet
1.1
Document Scope
This document contains targeted datasheet specifications for the 82573 GbE controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
1.2
Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: • IEEE Standard 802.3, 2000 Edition. Institute of Electrical and Electronics Engineers (IEEE). • PCI Express Base Specification, Revision 1.0a. PCI Special Interest Group. • PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest Group. • PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group. • Intel Ethernet Controller Timing Device Selection Guide. Intel Corporation. • 82573 NVM Map and Programming Information Guide. Intel Corporation. • 82573/82562 Dual Footprint Design Guide. Intel Corporation. • PCIe* Family of Gigabit Ethernet Controllers Software Developer’s Manual. Intel Corporation. • 82573 Family GbE Controllers Specification Update. Intel Corporation.
8
Datasheet—82573
1.3
Figure 1.
82573 Architecture
82573 Block Diagram
PCIe* Core
NVM
Slave Access Logic
DMA Function Descriptor Management 32 KB Packet RAM
Control Status Logic
Transmit Switch
Manageability (82573E/ 82573V VLA only) N
Receive Filters
Statistics
MAC
PHY
Note:
The 82573L does not support manageability.
9
82573—Datasheet
1.4
Product Codes for the 82573
Device Top Marking Leaded/ Unleaded Product Features 82573E with Intel® AMT includes: • Intel® AMT • ASF 2.0 • Advanced Pass Through (APT) 82573E with Intel® AMT includes: • Intel® AMT • ASF 2.0 • APT 82573V Baseline includes: • ASF 2.0 • APT 82573V Baseline includes: • ASF 2.0 • APT 82573L: • Low-power • No management 82573L: • Low-power • No management
82573E
RC82573E
Leaded
82573E
PC82573E
Lead Free
82573V
RC82573V
Leaded
82573V
PC82573V
Lead Free
82573L
RC82573L
Leaded
82573L
PC82573L
Lead Free
2.0
2.1
Signal Descriptions
Signal Type Definitions
The signals of the 82573 are electrically defined as follows:
Name I O I/O TS Input Standard input only digital signal. Output Standard output only digital signal. I/O Standard I/O digital signal. Tri-state Bi-directional three-state digital input/output signal. Open Drain Wired-OR with other agents. The signaling agent asserts the open drain signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor might require two or three clock periods to fully restore the signal to the de-asserted state. Analog PCIe, SerDes, or PHY analog signal. Power Power connection, voltage reference, or other reference connection. Definition
OD
A P
10
Datasheet—82573
Name B PU PD Input Bias Pull Up This signal requires a pull-up resistor. Pull Down This signal requires a pull-down resistor.
Definition
2.2
PCIe* Data Signals
Signal Type Name and Function PCIe Differential Reference Clock The reference clock is furnished by the system and has a 300 ppm frequency tolerance. It is used as reference clock for PCIe transmit and receive circuitry and is used by the PCIe core PLL to generate 125 MHz and 250 MHz clocks for the PCIe* core logic. PCIe* Serial Data Output These signals connect to corresponding PERn and PERp signals on a system motherboard or a PCIe* connector. Series AC coupling capacitors are required at the 82573 device end. The PCIe* differential outputs are clocked at 2.5 Gb/s. PCIe Serial Data Input These signals connect to corresponding PETn and PETp signals on a system motherboard or a PCIe* connector. The PCIe* differential inputs are clocked at 2.5 Gb/s.
PE_CLKn PE_CLKp
A(In)
PE_T0n PE_T0p
A(0ut)
PE_R0n PE_R0p
A(In)
2.3
PCIe* Miscellaneous Signals
Signal PE_RST# Type I Name and Function Reset This signal indicates whether or not the PCIe* power and clock are available. Wake This signal is driven to zero when it receives a wake-up packet and either the PME enable bit of the Power Management Control/Status Register is set to 1b or the Advanced Power Management enabled bit of the Wake Up Control Register equals 1b. Auxiliary Power Present AUX_PRESENT must be pulled up to 3.3V standby power if the 82573 is powered from standby supplies. This signal must be pulled down if auxiliary power is not used. Clock Request. The Clock Request (CLKREQ#) signal is located at ball P9 of the 82573L. When it is sampled high, this open-drain signal alerts the system that the 82573L does not need the PCIe* differential reference clock. During normal operation, the 82573L keeps CLKREQ# asserted (low), and the system supplies this clock to the device on the PE_CLKp and PE_CLKn signals. The 82573L deasserts CLKREQ# (high) when it is in an electrical idle state (L1 and L2), and the system might choose to continue supplying the reference clock or gate it conserving platform power. The CLKREQ# signal should be connected to the clock driver that supplies the 82573L PCIe* clock. If other devices use the same CLKREQ# signal, a pull-up resistor should be used to ensure that no device pulls this signal low when it is powered off.
PE_WAKE#
OD
AUX_ PRESENT (AUX_PWR)1
I
CLKREQ# (82573L only)
OD
1. This signal is used in all three devices and has the same functionality but is denoted as AUX_PRESENT in the 82573E/V and AUX_PWR in the 82573L.
11
82573—Datasheet
2.4
Non-Volatile Memory Interface Signals
Signal Type Name and Function NVM Serial Data Output The data output pin is used for input to the non-volatile memory device. This pin is occasionally used as input during arbitration. This signal has an internal pull-up resistor. NVM Serial Data Input The data input pin is used for output from the non-volatile memory device to the 82573. This signal has an internal pull-up resistor. NVM Serial Clock The serial clock provides the clock rate for the memory interface. NVM Chip Enable This signal is used to enable the device. This signal has an internal pull-up resistor. NVM Arbitration Request. This signal is used to request use of the NVM interface. NVM Protection Enable. This pin should be connected to ground to disable NVM protection; otherwise, NVM protection is enabled. This signal has an internal pull-up resistor. NVM Device Type If the device uses a Flash, this pin should be connected to a pull-down resistor. If the 82573 is connected to an EEPROM, this pin can be connected to an external pull-up resistor. This signal has an internal pull-up resistor of 30 KΩ ±50%. NVM Shared Enable This pin should be connected to a pull-down resistor to enable sharing of SPI Flash with ICH. This signal has an internal pull-up resistor.
NVM_SI
I/O
NVM_SO
I O TS I/O O
NVM_SK NVM_CS# NVM_REQ
NVM_PROT
I/PU
NVM_TYPE
I/PU
NVM_SHARED#
I/PU
2.5
2.5.1
Miscellaneous Signals
Reset and Power-down Signals
Signal Type Name and Function LAN Power Good This signal indicates that stable power is available to the 82573. When the signal is low, LAN_PWR_GOOD acts as a master reset of the entire device. LAN_PWR_GOOD should be connected to a power supervisor driven from auxiliary power. The signal should go active approximately 80 ms after all power rails are within their operating ranges. A PCIe* reset must only occur after LAN Power Good is active. Device Off This asynchronously disables the 82573, including voltage regulator control outputs if selected in external control.
LAN_PWR_ GOOD
I
DEVICE_OFF#
I
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Datasheet—82573
2.5.2
Note:
System Management Bus (SMBus) Signals1
The signals listed in the following table should not be connected when using an 82573L. Refer to the 82573/82562 Dual Footprint Design Guide reference schematics for more information.
Signal SMB_CLK SMB_DAT SMB_ALRT#/ ASF_PWR_ GOOD Type I/O I/O Name and Function SMBus Clock The SMBus Clock signal is an open drain signal for the serial SMBus interface. SMBus Data The SMB Data signal is an open drain signal for the serial SMBus interface. SMBus Alert/PCI Power Good The SMBus Alert signal is an open drain signal for serial SMBus interface. In ASF mode, this signal acts as the PCI Power Good input signal.
I/O
2.5.3
LED Signals
Signal LED0# LED1# LED2# Type O O O Name and Function LED0 This pin provides a signal for programmable LED indication. LED1 This pin provides a signal for programmable LED indication. LED2 This pin provides a signal for programmable LED indication.
2.5.4
Other Signals
Signal THERMn THERMp FUSEV Type O P Name and Function Thermal Test Pins These pins are used for thermal testing. They can be connected to test points. Fuse Supply This should be connected to 2.5V for normal operation.
1. The 82573L does not support the System Management Bus (SMBus).
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82573—Datasheet
2.6
PHY Analog and Crystal Signals
Signal Type Name and Function Media Dependent Interface [0] 1000BASE-T: In MDI configuration, MDIp0/MDIn0 corresponds to BI_DA+/-, and in MDI-X configuration, MDIp0/MDIn0 corresponds to BI_DB+/-. 100BASE-TX: In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and in MDI-X configuration, MDIp0/MDIn0 is used for the receive pair. 10BASE-T: In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and in MDI-X configuration, MDIp0/MDIn0 is used for the receive pair. Media Dependent Interface [1] 1000BASE-T: In MDI configuration, MDIp1/MDIn1 corresponds to BI_DB+/-, and in MDI-X configuration, MDIp1/MDIn1 corresponds to BI_DA+/-. 100BASE-TX: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used for the transmit pair. 10BASE-T: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used for the transmit pair. Media Dependent Interface [2] 1000BASE-T: In MDI configuration, MDIp2/MDIn2 corresponds to BI_DC+/-, and in MDI-X configuration, MDIp2/MDIn2 corresponds to BI_DD+/-. 100BASE-TX: Unused. 10BASE-T: Unused. Media Dependent Interface [3] 1000BASE-T: In MDI configuration, MDIp3/MDIn3 corresponds to BI_DD+/-, and in MDI-X configuration, MDIp3/MDIn3 corresponds to BI_DC+/-. 100BASE-TX: Unused. 10BASE-T: Unused. Reference Input This signal is used as the analog reference input for the PHY. It should be connected to a pull-down, 4.99 K Ω, 1% resistor. Crystal One The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel resonant crystal with a frequency tolerance of 30 ppm. The other end of the crystal should be connected to XTAL2. Crystal Two Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
MDI0n MDI0p
A
MDI1n MDI1p
A
MDI2n MDI2p
A
MDI3n MDI3p
A
PHY_REF
A
XTAL1
I
XTAL2
O
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Datasheet—82573
2.7
2.7.1
Test Signals
MAC Test Signals
Signal TEST_EN Type I Name and Function Factory Test Pin A 1 KΩ pull-down resistor should be attached to ground from this pin for normal operation. Alternate 125 MHz Clock This signal should not be connected. This signal has an internal pull-up resistor. JTAG Test Access Port Clock This signal has an internal pull-down resistor. JTAG Test Access Port Test Data In This signal has an internal pull-up resistor. JTAG Test Access Port Test Data Out JTAG Test Access Port Mode Select This signal has an internal pull-up resistor. Clock View The Clock View signal is an output for the clock signals required for IEEE testing. This signal has an internal pull-up resistor. Test Pin[16:0] These test pins are for the 82573E/V only. These signals have internal pull-up resistor. For normal operation, these pins should be left unconnected. Test Pin[10:0] These test pins are for the 82573L only. These signals have internal pull-up resistor. For normal operation, these pins should be left unconnected.
ALT_CLK125 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
NC I I O/OD I
CLK_VIEW
NC
TEST[16:0] for the 82573E/V TEST[10:0] for the 82573L
Rsvd
2.7.2
PHY Test Signals
Signal PHY_HSDACn PHY_HSDACp (82573E/V) PHY_TESTn PHY_TESTp (82573L only)1 PHY_TSTPT Type Name and Function
A(Out)
PHY Differential Test Port These signals are used for factory test purposes only.
PHY Test Port This signal is used for factory test purposes only. This pin must be left unconnected for normal operation.
1. These signals are used in all three devices and have the same functionality but are denoted as PHY_HSDACn and PHY_HSDACp in the 82573E/V and PHY_TESTn and PHY_TESTp in the 82573L.
2.7.3
Other Test Signals
Signal SDP[3:0] Type NC Name and Function These signals are used for factory test purposes only and have internal pull-up resistors.
15
82573—Datasheet
2.8
2.8.1
Power Signals
Power Support Signals
Signal Type Name and Function 2.5V Control This is the voltage control signal for external 2.5V. It is only active when the EN25REG signal is low (disabled). When external 2.5V and 1.2V supplies are used, CTRL_25 can be left floating or can be connected to ground through a 3.3 KΩ resistor. 1.2V Control This is the voltage control signal for external 1.2V. When external 2.5V and 1.2V supplies are used, CTRL_12 can be left floating or can be connected to ground through a 3.3 KΩ resistor. Enable 2.5V Regulator When this signal is high, the internal 2.5V regulator is enabled. When it is low, the internal 2.5V regulator is disables and the CTRL_25 signal is active. This signal should be pulled up to the 3.3V power rail.
CTRL_25
P
CTRL_12
P
EN25REG
I/PU
2.8.2
Digital and Analog Power Supply Signals
Signal VCC33 Type P Name and Function 3.3V Power Supply This signal is used for I/O circuits. 2.5V Analog Power Supply These signals are used for PHY analog, PHY I/O, PCIe* analog and phase lock loop circuits. All 2.5V pins should be connected to a single power supply. 1.2V Digital Power Supply These signals are used for core digital, PHY digital, PCIe* digital and clock circuits. All 1.2V pins should be connected to a single power supply. IREG25_IN 3.3V power supply for internal 2.5V regulator. When external 2.5V and 1.2V supplies are used, IREG25_IN should be connected to 3.3V. VCC25_OUT 2.5V output supply from internal power supply. When external 2.5V and 1.2V supplies are used, VCC25_OUT can be left floating.
VCC25
P
VCC12 IREG25_IN (82573E/V) VCC3.3_REG25 (82573L only)1 VCC25_OUT
P
P
P
1. This signal is used in all three devices and has the same functionality but is denoted as IREG25_IN for the 82573E/V and VCC3.3_REG25 for the 82573L.
2.9
Grounds and No Connects
Signal Type Name and Function Ground These signals connect to ground. VSS is also referred to as GND. No Connect These pins are reserved by Intel and might have factory test functions. For normal operation, do not connect any circuitry to these pins. Do not connect pull-up or pull-down resistors.
VSS
P
NC
16
Datasheet—82573
3.0
3.1
Table 1.
Voltage, Temperature, and Timing Specifications
Absolute Maximum Ratings
Absolute Maximum Ratings1
Symbol Tstg VCC (3.3) VCC (2.5) VCC (1.2) Vin AVin RPUD Parameter Storage temperature DC supply voltage on 3.3V pins with respect to VSS DC supply voltage on 2.5V pins with respect to VSS2 DC supply voltage on 1.2V pins with respect to VSSb Input voltage (digital inputs) Analog input voltage (digital inputs) Pull-up/pull-down Resistor Value Min -40 -0.3 -0.3 -0.3 -1.0 -1.0 15 Max 125 6.6 5.0 2.4 VCC (3.3) + 0.3 (less than 6.6 V) VCC (2.5) + 0.3 (less than 5.0 V) 50 Unit °C V V V V V KΩ
1. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded for an indefinite duration. These values should not be used as the limits for normal device operations. This specification is not guaranteed by design or simulations. 2. During normal device power up and power down, the 2.5V and 1.2V supplies must not ramp before the 3.3V.
3.2
Table 2.
Recommended Operating Conditions
Recommended Operating Conditions
Symbol Parameter Operating Temperature with external regulators Operating temperature with on-die 2.5V regulator Periphery Voltage Range Core Digital Voltage Range Analog VDD Range 3.3 V ± 3% 1.2 V ± 5% 2.5 V ± 5% Condition Min 0 0 3.0 1.14 2.375 3.3 1.2 2.5 Typical Max 70 55 3.6 1.26 2.625 Units °C °C V V V
TOP
VPERIF VD VA
3.3
Power Supply Connections
There are three options in providing power to the 82573: • Connecting the 82573 to three external power supplies with nominal voltages of 3.3V, 2.5V, and 1.2V. This is covered in Section 3.3.1. • Powering the 82573 with only an external 3.3V supply and using internal power regulators from the 82573 combined with external PNP transistors to supply the 2.5V and 1.2V levels. This is covered in Section 3.3.3. • Using the 2.5V internal (on-die) regulator combined with an external PNP transistor to supply the 1.2V level. This is covered in Section 3.3.3.
17
82573—Datasheet
3.3.1
External LVR Power Delivery
The following power supply requirements apply to designs where the 82573 is supplied by external voltage regulators. These systems do not use the internal regulator logic built into the 82573 as described in Section 3.3.3.
Table 3.
3.3V External Supply Voltage Ramp and Sequencing Recommendations
Parameter Rise Time Monotonicity Slope Operational Range Ripple Overshoot Capacitance Description Rise time from 10% to 90% Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Minimum = (0.8 * Vmin) / (Maximum Rise Time) Maximum = (0.8 * Vmax) / (Minimum Rise Time) Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth of 50 MHz Maximum voltage allowed2 Minimum capacitance 25 3 Min 5 Max 1001 300 1500 3.6 100 660 Unit ms mV mV/ms V mVpk-pk mV µF
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. 2. Excessive overshoot can affect long term reliability.
Table 4.
2.5V External Supply Voltage Ramp and Sequencing Recommendations
Parameter Rise Time Monotonicity Slope Operational Range Operational Range Ripple Undershoot Overshoot Output Capacitance Input Capacitance Capacitance ESR ICTRL Description Rise time from 10% to 90% Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Minimum = (0.8 * Vmin) / (Maximum Rise Time) Maximum = (0.8 * Vmax) / (Minimum Rise Time) Voltage range for normal operating conditions Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth of 50 MHz Maximum voltage allowed will not exceed 10% of nominal supply Maximum voltage allowed2 Capacitance range when using a PNP circuit Capacitance range when using a PNP circuit Equivalent series resistance of output capacitance3 Maximum output current rating with respect to CTRL_25 4.7 4.7 10 20 480 25 mV µF µF mΩ mA 2.375 -5 Min 2.5 Max 100
1
Unit ms mV mV/ms V % mVpk-pk
200 1500 2.625 +5 60
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. 2. Excessive overshoot can affect long term reliability. 3. Tantalum capacitors must not be used.
18
Datasheet—82573
Table 5.
1.2V External Supply Voltage Ramp and Sequencing Recommendations
Parameter Rise Time Monotonicity Slope Operational Range Operational Range Ripple Undershoot Overshoot Output Capacitance Input Capacitance Capacitance ESR ICTRL Description Rise time from 10% to 90% Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Minimum = (0.8 * Vmin) / (Maximum Rise Time) Maximum = (0.8 * Vmax) / (Minimum Rise Time) Voltage range for normal operating conditions Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth of 50 MHz Maximum voltage allowed will not exceed 10% of nominal supply Maximum voltage allowed2 Capacitance range when using a PNP circuit Capacitance range when using a PNP circuit Equivalent series resistance of output capacitance3 4.7 4.7 10 20 500 25 mV µF µF mΩ mA 1.14 -5 Min 1.51 120 1500 1.26 +5 60 Max Unit ms mV mV/ms V % mVpk-pk
Maximum output current rating with respect to CTRL_12
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. 2. Excessive overshoot can affect long term reliability. 3. Tantalum capacitors must not be used.
3.3.2
Power Sequencing with External Regulators
The following power-on and power-off sequence should be applied when external power supplies are in use. Designs must comply with the required power sequence to avoid risk of either latch-up or forward biased internal diodes. Generally, the 82573 power sequencing should power up the three power rails in the following order: 3.3V 2.5V 1.2V. However, if this general guideline is not followed, there are specific requirements that must be adhered to. These requirements are listed in the following two subsections.
3.3.2.1
External LVR Power Up Sequencing and Tracking
Sequencing of the external supplies during power up might be necessary to ensure that the 82573 is not electrically overstressed and does not latch-up. These requirements are shown in Figure 2. The 82573 core voltage (1.2V) cannot exceed the 3.3V supply by more than 0.5 V at any time during the power up. The 82573 core voltage (1.2V) cannot exceed the 2.5V supply by more than 0.5 V at any time during the power up. The core voltage is not required to begin ramping before the 3.3V or the 2.5V supply. The 82573 analog voltage (2.5V) can not exceed the 3.3V supply by more than 0.5 V at any time during the power up. The analog voltage is not required to begin ramping before the 3.3V supply.
19
82573—Datasheet
Figure 2.
Minimum Requirements for Power Supply Sequencing
3.3V 2.5V Max Difference ≤ 0.3 V 3.3V 2.5V 1.2V (Core Supply) 1.2V (Core Supply) Max Difference ≤ 0.3 V Max Difference ≤ 0.3 V
Max Difference ≤ 0.3 V
• If the 1.2V and 2.5V rails power up before 3.3V, they should never exceed the 3.3V supply by more than 0.3 V. • At power down, all three supplies should be turned off simultaneously. If the 3.3V supply powers down first, the 1.2V and 2.5V supplies must never exceed the 3.3V supply by more than 0.3 V.
3.3.2.2
External LVR Power Down Sequencing
There are no specific power down sequencing and tracking requirements for the 82573 silicon. The risk of latch-up or electrical overstress is small since the only charge storing in decoupling capacitors is left in the system.
3.3.3
Internally Generated Power Delivery
The 82573 has two internal linear voltage regulator controllers. The controllers use external transistors to generate 2 of the 3 required voltages: 2.5V (nominal) and 1.2V (nominal). These two voltages are stepped down from a 3.3V source.
Table 6.
3.3V Internal Power Supply Parameters
Parameter Rise Time Monotonicity Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any given time between 10% and 90% Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Voltage range for normal operating conditions Maximum voltage ripple (peak to peak) Maximum overshoot allowed Maximum overshoot allowed duration. (At that time delta voltage should be lower than 5 mV from steady state voltage) Min 5 300 Max Units ms mV
Slope
-
1500
mV/ms
Operational Range Ripple1 Overshoot Overshoot Settling Time
3.0 -
3.6 100 660
V mV mV
-
3
ms
1. The peak to peak output rippled is measured at 20 MHz bandwidth within the operational range.
20
Datasheet—82573
3.3.4
Internal LVR Power Sequencing
All supplies should rise monotonically. Sequencing of the supplies is controlled by the 82573.
3.3.4.1
Power Up Sequencing and Tracking
During power up, the sequencing and tracking of the internally controlled supplies (2.5V and 1.2V) are controlled by the 82573. No specific motherboard requirements are necessary to prevent electrical overstress or latch-up. The 82573 analog voltage (2.5V) never exceeds the 3.3V supply at any time during the power up. This is because the 2.5V supply is generated from the 3.3V supply when the internal voltage regulator control logic is being used. Figure 3 shows the internal LVR circuit. The 2.5V supply tracks the 3.3V ramp. The 82573 core voltage (1.2V) never exceeds the 3.3V at any time during the power up. This is because the 2.5V supply is generated from the 3.3V supply when the internal voltage regulator control logic is being used. Figure 3 shows the internal LVR circuit. The 1.2V ramp is delayed internally to prevent it from exceeding the 2.5V and 3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp. The delay is approximated by Tramp(3.3V)*0.25 < Tdelay(1.2V) < Tramp(3.3V)*0.75. Tramp is defined to the ramp rate of the 3.3V input to the internal voltage regulator circuit.
Figure 3.
Power Supply Sequencing Voltage 3.3V 2.5V 1.2V LAN_PWR_GOOD
0
Minimum 80 ms
Time
• It is recommended that the voltage on a lower voltage rail never exceed the voltage on a higher voltage rail during power on. • There are no minimum time requirements between the voltage rails as long as they power up in sequence: 3.3V → 2.5V → 1.2V. • All 3 supplies must be stable for at least 80 ms before LAN_PWR_GOOD is asserted. 100 ms is preferable if possible. • A PCIe* reset must occur after LAN Power Good is active.
3.3.4.2
Internal LVR Power Down Sequencing
There are no specific power down sequencing and tracking requirements for the 82573 device. The risk of latch-up or electrical overstress is small because the only charge storing in decoupling capacitors is left in the system.
21
82573—Datasheet
3.3.4.3
Table 7.
Internal Voltage Regulators Components for the 82573
82573 Bill of Materials (BOM) of Components for Internal Regulator
Recommended Component Description Quantity Manufacturer PNP Transistor For 1.2V LVR PNP Transistor For 2.5V LVR Part Number Package
1
Philips
BCP-69-16
SOT-223
1
Philips
BCP-69-16
SOT-223
3.3.4.4
Table 8.
2.5V Internal LVR Specification
2.5V Internal LVR Specification1
Value Parameter Minimum Input Voltage Input Voltage Slew Rate Input Capacitance Input Capacitance ESR Load Current Output Voltage Tolerance Output Capacitance Output Capacitance ESR Current Consumption During Power Up Current Consumption During Power Down Maximum Undershoot Peak to Peak Output Ripple PSRR External PNP hFE 100 1 -5 4.7 10 0.5 0.5 < 10 120 20 3.0 5 4.7 10 +5 Maximum 3.6 V ms µF mΩ A % µF mΩ mA mA % mV dB of nominal supply ±60 mV at 20 MHz bandwidth VOUT = 2.500 V Units Comments
1. The use of tantalum capacitors is not recommended.
22
Datasheet—82573
3.3.4.5
Table 9.
1.2V Internal LVR Specification
1.2V Internal LVR Specification1
Value Parameter Minimum Input Voltage Input Voltage Slew Rate Input Capacitance Input Capacitance ESR Load Current Output Voltage Tolerance Output Capacitance Output Capacitance ESR Current Consumption During Power Up Current Consumption During Power Down Maximum Undershoot Peak to Peak Output Ripple PSRR External PNP hFE 100 1 -5 4.7 10 0.5 0.5 < 10 120 20 3.0 5 4.7 10 +5 Maximu m 3.6 Units Comments
V ms µF mΩ A % µF mΩ mA mA % mV dB of nominal supply ±60 mV at 20 MHz bandwidth VOUT = 1.200 V
1. The use of tantalum capacitors is not recommended.
3.3.4.6
Table 10.
PNP Transistor Specification for Internal LVR
PNP Specification (Sheet 1 of 2)
Symbol Vce,sat Ic(max) Ib Vbe Tjmax Description Collector-Emitter Saturation Voltage Collector Current, Maximum Sustained Base Current, Maximum Sustained Base-Emitter on Voltage Maximum Junction Temperature Min Max 0.5 1000 10 1 125 Units V mA mA V °C
23
82573—Datasheet
Table 10.
PNP Specification (Sheet 2 of 2)
Symbol Power Dissipation hFE fT Description Maximum Total Power Dissipation DC Current Gain Current Gain Product Bandwidth Min 100 10 Max 1.35 Units W MHz
3.3.4.7
Internal LVR Board Schematic
When using the internal voltage regulator controllers built into the 82573, resistors might need to be placed in series with the emitter in order to prevent the PNP transistors from overheating. These series resistors dissipate a portion of the power that would otherwise be dissipated by the PNP devices. The value and power rating of the resistors must be carefully chosen to balance thermal limits against the PNP characteristics against total current draw. The regulator must never drop below the minimum Vce and out of the linear region. The effective resistance of the pass resistors should equal approximately 1 Ω and have a combined power dissipation rating of 0.5 Watts for the 82573. Figure 4 shows the recommended implementation.
24
Datasheet—82573
Figure 4.
82573 2.5V and 1.2V LVR Schematic
2.5V Voltage Regulator
Install when using the Integrated 2.5V Voltage Regulator with External Pass Transistor. Do not install if on- die 2.5V regulator is used. Q3 Requires HeatSink surface pad of 0.5'' x 0.5'' min. Intel recommends using 40uF at the emitter of Q3 on the 3.3V rail. Use ceramic capacitors.
1 ohm is not needed for R60 for 82573L. 0 ohm may be used instead. 82573L only designs may connect C23 directly to 2.5V.
1.2V Voltage Regulator
Q4 Requires Heat-Sink surface pad of 0.5'' x 0.5'' min.
Intel recommends using 40uF at the emitter of Q4 on the 3.3V rail. Use ceramic capacitors.
1 ohm is not needed for R61 for 82573L. 0 ohm may be used instead. 82573L only designs can connect C29 directly to 1.2V.
3.4
Table 11.
DC and AC Specifications
82573E and 82573V Maximum Measured External Power Characteristics1
System State S0 Link State 1000 Mbps Active (Maximum Power) 82573E Power (mW) with Intel® AMT 1548 82573V Power (mW) without Intel® AMT 1426
1. Maximum conditions refer to fast silicon, high temperature and nominal VCC.
25
82573—Datasheet
Table 12.
82573E and 82573V Typical Measured External Power Characteristics1
System State Link State 1000 Mb/s: Intel® AMT (82573E only) 1000 Mb/s Active 1000 Mb/s Idle S0 100 Mb/s Active 100 Mb/s Idle 10 Mb/s Active 10 Mb/s Idle No Link (SPD) 100 Mb/s Idle (wake) Sx 10 Mb/s Idle (wake) No Link (no wake) Device Off 3.3V Current (mA) 12 12 12 11 11 7 7 3 11 7 3 3 2.5V Current (mA) 297 297 276 130 107 167 76 40 104 72 364 42d 1.2V Current (mA) 551 490 380 144.5 101 125.5 82 73 93.5 74.5 64.5 48.5 82573E/V Power (mW)2 3 1443.3 1370.1 1185.6 534.7 425 591.2 311.5 197.5 408.5 292.5 177.3 173.1
1. Maximum conditions refer to fast silicon, high temperature and nominal VCC. 2. For 10/100 Mb/s non-stress mode with Intel® AMT, add 12 mW to this number (for example, using IDE-R functionality). 3. For 10/100 Mb/s stress mode active Intel® AMT, add 120 mW to this number (for example, using IDE-R functionality). 4. The current use is slightly higher in the device off state than in the no link state. This occurs since a PHY reset is required in the device off state, which overrides the PHY power down.
Table 13.
82573E and 82573V 2.5V Internal Power Regulator Numbers
System State Link State 3.3V Current (mA) 313 313 294 142 119 173 84 44 116 80 40 45 2.5V Current (mA) (on-die 2.5V regulator) Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal 1.2V Current (mA) 607 506 404 145 101 126 83 73 94 75 64 49 82573E/V Power (mW) 1760 1638 1453 642 513 722 376 233 493 354 209 207
1000 Mb/s: Active with Full Management 1000 Mb/s Active 1000 Mb/s Idle S0 100 Mb/s Active 100 Mb/s Idle 10 Mb/s Active 10 Mb/s Idle D0 No Link (SPD) D3 100 Mb/s Idle (wake) Sx D3 10 Mb/s Idle (wake) D3 No Link (no wake) Device Off
26
Datasheet—82573
Table 14.
82573L Maximum Measured Power Characteristics1
System State S0 Link State 1000 Mb/s Active (Maximum Power) 82573L (mW) 1296
1. Maximum conditions refer to fast silicon, high temperature and nominal VCC.
Table 15.
82573L Measured Power Characteristics
System State Link State 1000 Mb/s Active 1000 Mb/s Idle 100 Mb/s Active S0 100 Mb/s Idle 10 Mb/s Active 10 Mb/s Idle D0 No Link (SPD) D3 100 Mb/s Idle (wake) Sx D3 10 Mb/s Idle (wake) D3 No Link (no wake) 3.3V Current (mA) 14.8 14.8 14.0 14.2 10.5 10.3 6.2 14.2 10.5 6.2 2.5V Current (mA) 288.5 243.2 121.3 78.8 169 143.5 7.0 78.8 45.7 7.3 1.2V Current (mA) 372.5 294.0 111.5 58.5 118 91.8 12.3 49.3 31.0 12.2 82573L Power (mW) 1217 1010 483 314 504 194 53 303 186 53
Table 16.
DC Specifications
Symbol Vih Vil Vhy Voh Vol Ilkg Rpup/ Rpdn Cin/out Cout Parameter Input High Voltage Input Low Voltage Input Hysteresis Output High Voltage Output Low Voltage Input Leakage Current Internal Pull Up and Pull Down Resistor Pin Capacitance Output Pin Capacitance Input and bi-directional buffer Output only buffer 0 < Vin < VCCP 15 100 2.4 0.4 ±50 50 2.5 2.0 Condition Min 2.0 0.8 Max Unit V V mV V V µA KΩ pF pF
27
82573—Datasheet
Table 17.
LED DC Specifications
Symbol Voh Vol Ioz Ios Cin/out Parameter1 Output High Voltage Output Low Voltage 3-state Output Leakage Current Output Short Current Pin Capacitance2 at 12 mA at 12 mA Voh = VDD or VSS VDD = 3.6 V, Vo = VDD, VDD = 3.6 V, Vo = VSS Input and bi-directional buffer 2.5 Condition Min 2.4 0.4 ±10 Max Unit V V mV µA pF
1. Outputs are inputs/outputs in test mode. 2. This parameter is characterized but not tested.
3.5
3.5.1
External Interfaces
Crystal
The quartz crystal is strongly recommended as a low cost and high performance choice with the 82573 device. Quartz crystals are the mainstay of frequency control components and are available from numerous vendors in many package types with various specification options.
Table 18.
Crystal Specifications
Parameter Name Frequency Vibration mode Frequency Tolerance Temperature Tolerance Operating Temperature Equivalent Series Resistance (ESR) Load Capacitance Shunt Capacitance Max Drive Level Nominal Drive Level Aging Board Capacitance External Capacitors Board Resistance Symbol fo ∆f/fo at 25 °C ∆f/fo Topr Rs Cload Co DL DL f/fo Cs C1, C2 Rs Recommended Value 25.000 MHz Fundamental ±30 ppm ±30 ppm 0 °C to +70 °C 40 Ω 20 pF 6 pF 500 µW 200 µW ±5 ppm per year 4 pF 22 pF 0.1 Ω 1Ω 1 mW 500 µW ±5 ppm per year
1
Max/Min Range -
Conditions at 25 °C at 25 °C -
50 Ω (max)
at 25 MHz -
1. This value can change up to 10%.
3.5.2
External Clock Oscillator
If an external oscillator is used to provide a clock to the 82573, the connection shown in the figure below must be used. The XTAL2 output signal of the 82573 must not be connected. The XTAL1 input signal receives the output of the oscillator directly. AC coupling is not recommended.
28
Datasheet—82573
Figure 5.
External Clock Oscillator Connectivity to the 82573
82573
82563EB/82564EB XTAL2 XTAL1 3.3V
Table 19.
Specification for External Clock Oscillator
Parameter Name Frequency Swing Frequency Tolerance Operating Temperature Aging Symbol fo Vp-p ∆f/fo Topr ∆f/fo Value 25.0 MHz 3.3 ± 0.3 V ±30 ppm -20 °C to +70 °C ±5 ppm per year Conditions at 25 °C 0 °C to +70 °C 0 °C to +70 °C -
3.5.3
Table 20.
Non-Volatile Memory (NVM) Interface: EEPROM
NVM Interface Timing Specifications for EEPROM (Sheet 1 of 2)
Symbol tSCK tRU tFI tWH tWH tCS tCSS tCSH tSU tH tV Parameter SCK clock frequency Input rise time Input fall time SCK high time
1
Min 0
Typ 2 2.5 2.5
Max 2.1 2 2
Units MHz µs µs ns ns ns ns ns ns ns
200 200 250 250 250 50 50 0
250 250
SCK low timea CS high time CS setup time CS hold time Data-in setup time Data-in hold time Output Valid
200
ns
29
82573—Datasheet
Table 20.
NVM Interface Timing Specifications for EEPROM (Sheet 2 of 2)
Symbol tHO tDIS tWC 1. 50% duty cycle. Parameter Output hold time Output disable time Write cycle time Min 0 250 10 Typ Max Units ns ns ms
4.0
Package and Pinout Information
This section describes the 82573 physical characteristics and pin-to-signal mapping.
4.1
Package Information
The 82573 device is a lead-free 196-pin thin and Fine Pitch Ball Grid Array (TF-BGA) measuring 15 mm by 15 mm. The nominal ball pitch is 1.0 mm.
Figure 6.
82573 Controller TF-BGA Package Ball Pad Dimensions
Detail Area
0.4 mm Solder Resist Opening
0.55 mm Metal Diameter
30
Datasheet—82573
Figure 7.
82573 Mechanical Specifications
31
82573—Datasheet
4.2
Thermal Specifications
The case temperature (TC) is calculated using the equation: TC = TA + P (⎝JA - ⎝JC) Junction temperature (TJ) is calculated using the equation: TJ = TA + P ⎝JA The power consumption (P) is calculated by using the typical ICC and nominal VCC where TA represents the ambient temperature. The thermal resistances are listed in Table 21.
32
Datasheet—82573
Table 21.
Thermal Resistance Values
Value at Specified Airflow (m/s) Symbol TJ ⎝JA ⎝JC Parameter 0 Maximum junction temperature Thermal resistance, junction-toambient Thermal resistance, junction-tocase 127.1 26.0 6.1 1 122.1 23.7 6.1 2 119.3 22.4 6.1 3 117.5 21.6 6.1 C C/Watt C/Watt Units
Thermal resistances are determined empirically with test devices mounted on standard thermal test boards. Real system designs may have different characteristics due to board thickness, arrangement of ground planes, and proximity of other components. The case temperature measurements should be used to assure that the 82573 is operating under recommended conditions. The use of a heat sink device is not required.
4.3
4.3.1
Table 22.
Pinout Information
PCIe Bus Interface Signals
PCIe Data Signals
Signal PE_CLKn PE_CLKp G2 G1 Pin Signal PE_T0n PE_T0p C1 D1 Pin Signal PE_R0n PE_R0p F1 F2 Pin
33
82573—Datasheet
Table 23.
PCI Express Miscellaneous Signals
Signal Pin Signal Pin Signal AUX_PRESENT (82573E/V) / AUX_PWR (82573L)1 Pin
PE_RST#
P7
PE_WAKE#
P10
C6
CLKREQ# (82573L only)
P9
1. This signal is used in all three devices and has the same functionality but is denoted as AUX_PRESENT in the 82573E/V or AUX_PWR in the 82573L.
4.3.2
Table 24.
Non-Volatile Memory Interface Signals
Non-Volatile Memory Interface Signals
Signal NVM_SI NVM_SO NVM_SK A9 B9 C9 Pin Signal NVM_CS# NVM_REQ NVM_PROT B10 B4 A5 Pin Signal NVM_TYPE NVM_SHARED# A6 D3 Pin
4.3.3
Table 25.
Miscellaneous Signals
Reset and Power-down Signals
Signal LAN_PWR_GOOD P5 Pin Signal DEVICE_OFF# L7 Pin Signal Pin
Table 26.
SMBus Signals
Signal SMB_CLK P11 Pin Signal SMB_DAT Pin M11 Signal SMB_ALRT#/ ASF_PWR_ GOOD N11 Pin
Table 27.
LED Signals
Signal LED0# B11 Pin Signal LED1# C11 Pin Signal LED2# A12 Pin
Table 28.
Other Signals
Signal THERMn L2 Pin Signal THERMp L3 Pin Signal Pin
34
Datasheet—82573
4.3.4
Table 29.
PHY Signals
Analog and Crystal Signals
Signal MDI0n MDI0p MDI1n MDI1p C14 C13 E14 E13 Pin Signal MDI2n MDI2p MDI3n MDI3p F14 F13 H14 H13 Pin Signal PHY_REF XTAL1 XTAL2 D12 K14 J14 Pin
4.3.5
Table 30.
Test Signals
82573E/V MAC Test Signals1
Signal TEST_EN ALT_CLK125 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS CLK_VIEW TEST0 A13 N10 N5 P4 P6 N4 L14 H1 Pin Signal TEST1 TESTPT2 TESTPT3 TESTPT4 TEST5 TEST6 TEST7 TEST8 H2 H3 J1 J2 J3 K1 L1 M1 Pin Signal TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 (82573E/V only) TEST15 (82573E/V only) TEST16 (82573E/V only) M3 N2 P1 N3 M8 P9 E3 A14 Pin
1. These test signals do not apply to the 82573L.
Table 31.
82573L MAC Test Signals1
Signal TEST_EN ALT_CLK125 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS A13 N10 N5 P4 P6 N4 Pin Signal CLK_VIEW TEST0 TEST1 TESTPT2 TESTPT3 TESTPT4 L14 H1 H2 H3 J1 J2 Pin TEST5 TEST6 TEST7 TEST8 TEST9 Signal J3 K1 L1 M1 M3 Pin
1. These test signals do not apply to the 82573E or 82573V devices.
Table 32.
PHY Test Interface Signals
Signal PHY_HSDACn B13 Pin Signal PHY_HSDACp B12 Pin Signal PHY_TSTPT B14 Pin
35
82573—Datasheet
Table 33.
82573E/V Other Test Signals1
Signal SDP[0] SDP[3] A8 C7 Pin Signal SDP[1] B8 Pin Signal SDP[2] C8 Pin
1. These test signals do not apply to the 82573L.
4.3.6
Table 34.
Power Supply Signals
Power Support Signals
Signal CTRL_25 A4 Pin Signal CTRL_12 P3 Pin Signal EN25REG B5 Pin
Table 35.
Power Signals
Signal VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 IREG25_IN IREG25_IN FUSEV VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 A7 D9 F3 J4 M10 N6 N8 P2 P12 A2 A3 M2 A11 B6 G3 G5 H4 H5 J5 Pin VCC25 VCC25 VCC25 VCC25 VCC25 VCC25_OUT VCC25_OUT VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 Signal J12 K13 L12 M4 N7 B1 B2 A10 C4 C5 F12 G6 G12 G13 H6 H7 H8 H11 H12 Pin VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 Signal J6 J7 J8 J9 J10 J11 K3 K4 K5 K6 K7 K8 K9 K10 K11 L5 L9 L10 Pin
36
Datasheet—82573
Table 36.
Ground Signals
Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A1 B3 C2 C10 C12 D2 D4 D5 D6 D7 D8 D13 E2 E4 Pin VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal E5 E6 E7 E8 E9 E10 F4 F5 F6 F7 F8 F9 F10 F11 Pin VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal G4 G7 G8 G9 G10 G11 G14 H9 H10 K2 N1 N12 P8 Pin
Table 37.
82573E/V No Connect Signals1
Signal NC NC NC NC NC NC NC NC NC B7 C3 D10 D11 D14 E1 E11 E12 J13 Pin NC NC NC NC NC NC NC NC NC Signal K12 L4 L6 L8 L11 L13 M5 M6 M7 Pin NC NC NC NC NC NC NC NC NC Signal M9 M12 M13 M14 N9 N13 N14 P13 P14 Pin
1. These test signals do not apply to the 82573L.
Table 38.
82573L No Connect Signals1 (Sheet 1 of 2)
Signal NC NC NC NC NC NC NC NC A8 A14 B7 B8 C3 C7 C8 D10 Pin NC NC NC NC NC NC NC NC Signal E12 J13 K12 L4 L6 L8 L11 L13 Pin NC NC NC NC NC NC NC NC Signal M9 M12 M13 M14 N2 N3 N9 N13 Pin
37
82573—Datasheet
Table 38.
82573L No Connect Signals1 (Sheet 2 of 2)
Signal NC NC NC NC NC D11 D14 E1 E3 E11 Pin NC NC NC NC Signal M5 M6 M7 M8 Pin NC NC NC NC Signal N14 P1 P13 P14 Pin
1. These test signals do not apply to the 82573E or 82573V devices.
4.4
A 1
VSS
Visual Pin Assignments
B
VCC25_ OUT
C
PE_T0n
D
PE_TR0p
E
NC
F
PE_R0n
G
PE_CLKp
H
TEST0
J
TEST3
K
TEST6
L
TEST7
M
TEST8
N
VSS
P
TEST11
2
IREG25_IN
VCC25_ OUT
VSS
VSS
VSS
PE_R0p
PE_CLKn
TEST1
TEST4
VSS
THERMn
FUSEV
TEST10
VCC33
3
IREG25_IN
VSS
NC
NVM_ SHARED
TEST15
VCC33
VCC25
TEST2
TEST5
VCC12
THERMp
TEST9
TEST12
CTRL_12
4
CTRL_25
NVM_REQ
VCC12
VSS
VSS
VSS
VSS
VCC25
VCC33
VCC12
NC
VCC25
JTAG_TMS
JTAG_TDI
5
NVM_ PROT
EN25REG
VCC12
VSS
VSS
VSS
VCC25
VCC25
VCC25
VCC12
VCC12
NC
JTAG_ TCK
LAN_PWR_ GOOD
6
NVM_ TYPE
VCC25
AUX_ PRESENT
VSS
VSS
VSS
VCC12
VCC12
VCC12
VCC12
NC
NC
VCC33
JTAG_TDO
7
VCC33
NC
SDP[3]
VSS
VSS
VSS
VSS
VCC12
VCC12
VCC12
DEVICE_ OFF#
NC
VCC25
PE_RST#
8
SDP[0]
SDP[1]
SDP[2]
VSS
VSS
VSS
VSS
VCC12
VCC12
VCC12
NC
TEST13
VCC33
VSS
9
NVM_SI
NVM_SO
NVM_SK
VCC33
VSS
VSS
VSS
VSS
VCC12
VCC12
VCC12
NC
NC
TEST14
10
VCC12
NVM_CS#
VSS
NC
VSS
VSS
VSS
VSS
VCC12
VCC12
VCC12
VCC33
ALT_CLK125
PE_WAKE#
11
VCC25
LED0#
LED1#
NC
NC
VSS
VSS
VCC12
VCC12
VCC12
NC
SMB_DAT
SMB_ALRT#/ ASF_PWR_ GOOD
SMB_CLK
12
LED2#
PHY_ HSDACp
VSS
PHY_REF
NC
VCC12
VCC12
VCC12
VCC25
NC
VCC25
NC
VSS
VCC33
13
TEST_EN
PHY_ HSDACn
MDI0p
VSS
MDI1p
MDI2p
VCC12
MDI3p
NC
VCC25
NC
NC
NC
NC
14
TEST16
PHY_ TSTPT
MDI0n
NC
MDI1n
MDI2n
VSS
MDI3n
XTAL2
XTAL1
CLK_VIEW
NC
NC
NC
Figure 8.
82573E and 82573V Gigabit Ethernet Controller Pinout
38
Datasheet—82573
Figure 9.
82573L Gigabit Ethernet Controller Pinout
A 1
VSS
B
VCC25_ OUT
C
PE_T0n
D
PE_TR0p
E
NC
F
PE_R0n
G
PE_CLKp
H
TEST0
J
TEST3
K
TEST6
L
TEST7
M
TEST8
N
VSS
P
NC
2
VCC3.3_ REG25
VCC25_ OUT
VSS
VSS
VSS
PE_R0p
PE_CLKn
TEST1
TEST4
VSS
THERMn
FUSEV
TEST10
VCC33
3
VCC3.3_ REG25
VSS
NC
NVM_ SHARED
NC
VCC33
VCC25
TEST2
TEST5
VCC12
THERMp
TEST9
NC
CTRL_12
4
CTRL_25
NVM_REQ
VCC12
VSS
VSS
VSS
VSS
VCC25
VCC33
VCC12
NC
VCC25
JTAG_TMS
JTAG_TDI
5
NVM_ PROT
EN25REG
VCC12
VSS
VSS
VSS
VCC25
VCC25
VCC25
VCC12
VCC12
NC
JTAG_ TCK
LAN_PWR_ GOOD
6
NVM_ TYPE
VCC25
AUX_PWR
VSS
VSS
VSS
VCC12
VCC12
VCC12
VCC12
NC
NC
VCC33
JTAG_TDO
7
VCC33
NC
NC
VSS
VSS
VSS
VSS
VCC12
VCC12
VCC12
DEVICE_ OFF#
NC
VCC25
PE_RST#
8
NC
NC
NC
VSS
VSS
VSS
VSS
VCC12
VCC12
VCC12
NC
NC
VCC33
VSS
9
NVM_SI
NVM_SO
NVM_SK
VCC33
VSS
VSS
VSS
VSS
VCC12
VCC12
VCC12
NC
NC
CLK_REQ#
10
VCC12
NVM_CS#
VSS
NC
VSS
VSS
VSS
VSS
VCC12
VCC12
VCC12
VCC33
ALT_CLK125
PE_WAKE#
11
VCC25
LED0#
LED1#
NC
NC
VSS
VSS
VCC12
VCC12
VCC12
NC
RSVD
RSVD
RSVD
12
LED2#
PHY_ HSDACp
VSS
PHY_REF
NC
VCC12
VCC12
VCC12
VCC25
NC
VCC25
NC
VSS
VCC33
13
TEST_EN
PHY_ HSDACn
MDI0p
VSS
MDI1p
MDI2p
VCC12
MDI3p
NC
VCC25
NC
NC
NC
NC
14
NC
PHY_ TSTPT
MDI0n
NC
MDI1n
MDI2n
VSS
MDI3n
XTAL2
XTAL1
CLK_VIEW
NC
NC
NC
39
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