Intel® 82801BA I/O Controller Hub 2 (ICH2) and Intel® 82801BAM I/O Controller Hub 2 Mobile (ICH2-M)
Datasheet
October 2000
Order Number: 290687-002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 (ICH2-M) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN and Wake on LAN are results of the IBM/Intel Advanced Manageability Alliance and are trademarks of IBM Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2000 *Third-party brands and names are the property of their respective owners.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Intel® 82801BA/M ICH2/ICH2-M Features
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PCI Bus I/F — Supports PCI at 33 MHz — Supports PCI Rev 2.2 Specification — 133 MByte/sec maximum throughput — Supports up to 6 master devices on PCI — One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller) Integrated LAN Controller — WfM 2.0 Compliant — Interface to discrete LAN Connect component — 10/100 Mbit/sec Ethernet support — 1 Mbit/sec HomePNA* support Integrated IDE Controller — Independent timing of up to 4 drives — Ultra ATA/100/66/33, BMIDE and PIO modes — Read transfers up to 100MB/s, Writes to 89 MB/s — Separate IDE connections for Primary and Secondary cables — Implements Write Ping-Pong Buffer for faster write performance — Tri-state modes to enable mobile swap bay (82801BAM ICH2-M) USB — 2 UHCI Host Controllers with a total of 4 ports — USB 1.1 compliant — Supports wake-up from sleeping states S1–S4 — Supports legacy Keyboard/Mouse software AC'97 Link for Audio and Telephony CODECs — AC’97 2.1 compliant — Independent bus master logic for 5 channels (PCM In/Out, Mic Input, Modem In/Out) — Separate independent PCI functions for Audio and Modem — Support for up to six channels of PCM audio output (full AC3 decode) — Supports wake-up events Interrupt Controller — Support up to 8 PCI interrupt pins — Supports PCI 2.2 Message-Based Interrupts — Two cascaded 82C59 — Integrated I/O APIC capability — 15 interrupts supported in 8259 mode, 24 supported in I/O APIC mode — Supports Serial Interrupt Protocol — Supports Front-Side Bus interrupt delivery 1.8 V operation with 3.3 V I/O — 5V tolerant buffers on IDE, PCI, USB Overcurrent and Legacy signals GPIO — TTL, Open-Drain, Inversion Timers Based on 82C54 — System timer, Refresh request, Speaker tone output
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Power Management Logic — ACPI 1.0 compliant — ACPI-defined power states - C1–C2, S3–S5 (82801BA ICH2) - C1–C3, S1, S3–S5 (82801BAM ICH2-M) — Support for “Intel® SpeedStep™ technology” processor power control (82801BAM ICH2-M) — PCI CLKRUN# support (82801BAM ICH2-M) — ACPI Power Management Timer — PCI PME# support — SMI# generation — All registers readable/restorable for proper resume from 0V suspend states — Support for APM-based legacy power management for non-ACPI implementations External Glue Integration — Integrated Pull-up, Pull-down and Series Termination resistors on IDE and processor interface Enhanced Hub I/F buffers improve routing flexibility (Not available with all Memory Controller Hubs) Firmware Hub (FWH) I/F supports BIOS memory size up to 8 MBs Low Pin count (LPC) I/F — Allows connection of legacy ISA and X-Bus devices such as Super I/O — Supports two Master/DMA devices. Enhanced DMA Controller — Two cascaded 8237 DMA controllers — PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs — Supports LPC DMA — Supports DMA Collection Buffer to provide Type-F DMA performance for all DMA channels Real-Time Clock — 256-byte battery-backed CMOS RAM — Hardware implementation to indicate century rollover System TCO Reduction Circuits — Timers to generate SMI# and Reset upon detection of system hang — Timers to detect improper processor reset — Integrated processor frequency strap logic SM Bus — Host interface allows processor to communicate via SM Bus — Slave interface allows an external Microcontroller to access system resources — Compatible with most 2-Wire components that are also I2C compatible Supports ISA bus via external PCI-ISA Bridge 360-pin EBGA package
Shading,as is shown here, indicates differences between the two components.
The Intel® 82801BA ICH2 and 82801BAM ICH2-M may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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Intel® 82801BA (ICH2) and 82801BAM (ICH2-M) Simplified Block Diagram
AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ[0:4]# REQ5#/REQB#/GPIO1 REQA#/GPIO0 GNT[0:4]# GNT5#/GNTB#/GPIO17 GNTA#/GPIO16 PCICLK PCIRST# PLOCK# SERR# PME# (ICH2-M)CLKRUN# PDCS1# SDCS1# PDCS3# SDCS3# PDA[2:0] SDA[2:0] PDD[15:0] SDD[15:0] PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY THRM# SLP_S3 SLP_S5# PWROK PWRBTN# RI# RSMRST# SUS_STAT#/LPCPD# SUSCLK RSM_PWROK (ICH2) or LAN_PWROK (ICH2-M) VRMPWRGD / VGATE (ICH2-M) SLP_S1# (ICH2-M) C3_STAT#/GPIO[21] (ICH2-M) AGPBUSY# (ICH2-M) STP_PCI# (ICH2-M) STP_CPU# (ICH2-M) BATLOW# (ICH2-M) CPUPERF# (ICH2-M) SSMUXSEL (ICH2-M) AC_RST# AC_SYNC AC_BIT_CLK AC_SDOUT AC_SDIN0 AC_SDIN1 HL11:0] HL_STB HL_STB# HLCOMP
IDE Interface PCI Interface
A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD SERIRQ PIRQ[A:D]# PIRQ[H:E]/GPIO[5:2] IRQ[14:15] APICCLK APICD[1:0] USBP1P USBP1N USBP0P USBP0N OC[3:0]#
Processor Interface
Power Mgnt.
Interrupt AC'97 Link
USB Hub Interface
RTCX1 RTCX2
RTC
Firmware Hub
CLK14 CLK48 CLK66 SPKR RTCRST# (ICH2) TP0 FS0 GPIO[13:11,8:6,4:3,1:0] GPIO[23:16] GPIO[28:24] EE_SHCLK EE_DIN EE_DOUT EE_CS
FWH[3:0]/LAD[3:0] FWH[4]/LFRAME# LAD[3:0]/FWH[4] LFRAME#/FWH[4] LDRQ[0:1]# SMBDATA SMBCLK SMBALERT#/GPIO[11] INTRUDER# SMLINK[1:0] LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC
Clocks LPC Interface Misc. Signals SMBus Interface General Purpose I/O
System Mgnt.
System Mgnt.
System Mgnt.
Note: 1. The GPIO signals listed above represent the GPIO signals for the 82801BA ICH2. Some of these signals are not implemented in the 82801BAM ICH2-M. See Signal Description Chapter for details.
blk_ich2-ich2m
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
System Configuration
Processor
G raphics C ontroller
H ost C ontroller
M ain M em ory
H ub Interface PCI Slots SM Bus D evice(s) SM Bus PCI Bus
AC '97 C odec(s) (optional)
AC '97 2.1 I/O C ontroller H ub 2 82801BA (ICH 2) and 82801BAM (ICH 2-M ) 4xUSB G PIO PC I Agent ISA Bridge (optional)
ATA/100/66/33 4 ID E D rives
M oon2 D ocking Bridge (optional) (ICH 2-M ) LPC I/F
LAN C ontroller
Super I/O (required) FW H
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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Contents
1 Introduction ................................................................................................................1-1 1.1 1.2 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 About this Document ....................................................................................1-1 Overview.......................................................................................................1-3 Hub Interface to Host Controller ...................................................................2-1 Link to LAN Connect.....................................................................................2-1 EEPROM Interface .......................................................................................2-2 Firmware Hub Interface ................................................................................2-2 PCI Interface.................................................................................................2-2 IDE Interface.................................................................................................2-5 LPC Interface................................................................................................2-6 Interrupt Interface .........................................................................................2-6 USB Interface ...............................................................................................2-7 Power Management Interface.......................................................................2-7 Processor Interface.......................................................................................2-9 SMBus Interface .........................................................................................2-10 System Management Interface...................................................................2-10 Real Time Clock Interface ..........................................................................2-11 Other Clocks ...............................................................................................2-11 Miscellaneous Signals ................................................................................2-11 AC’97 Link ..................................................................................................2-12 General Purpose I/O...................................................................................2-12 Power and Ground......................................................................................2-13 Pin Straps ...................................................................................................2-14 2.20.1 Functional Straps ...........................................................................2-14 2.20.2 Test Signals ...................................................................................2-15 2.20.2.1 Test Mode Selection.......................................................2-15 2.20.2.2 Test Straps (82801BA ICH2 only) ..................................2-15 2.20.3 External RTC Circuitry ...................................................................2-16 2.20.4 V5REF / Vcc3_3 Sequencing Requirements .................................2-16 Power Planes................................................................................................3-1 Integrated Pull-Ups and Pull-Downs.............................................................3-1 IDE Integrated Series Termination Resistors ...............................................3-2 Output and I/O Signals Planes and States ...................................................3-2 Power Planes for Input Signals.....................................................................3-6
Signal Description......................................................................................................2-1
3
Power Planes and Pin States ....................................................................................3-1 3.1 3.2 3.3 3.4 3.5
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System Clock Domains..............................................................................................4-1
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Functional Description ...............................................................................................5-1 5.1 Hub Interface to PCI Bridge (D30:F0)...........................................................5-1 5.1.1 PCI Bus Interface.............................................................................5-1 5.1.2 PCI-to-PCI Bridge Model .................................................................5-2 5.1.3 IDSEL to Device Number Mapping ..................................................5-2 5.1.4 SERR# Functionality........................................................................5-2 5.1.5 Parity Error Detection.......................................................................5-4 5.1.6 Standard PCI Bus Configuration Mechanism ..................................5-5 5.1.7 PCI Dual Address Cycle (DAC) Support (82801BA ICH2 only) .......................................................................5-6 LAN Controller (B1:D8:F0)............................................................................5-6 5.2.1 LAN Controller Architectural Overview ............................................5-7 5.2.2 LAN Controller PCI Bus Interface ....................................................5-9 5.2.2.1 Bus Slave Operation.........................................................5-9 5.2.2.2 Bus Master Operation.....................................................5-10 5.2.3 CLOCKRUN# Signal (82801BAM ICH2-M only)............................5-13 5.2.3.1 PCI Power Management ................................................5-13 5.2.3.2 PCI Reset Signal ............................................................5-15 5.2.3.3 Wake-up Events .............................................................5-15 5.2.3.4 Wake on LAN (Preboot Wake-up) ..................................5-16 5.2.4 Serial EEPROM Interface ..............................................................5-17 5.2.5 CSMA/CD Unit ...............................................................................5-19 5.2.6 Media Management Interface ........................................................5-20 5.2.7 TCO Functionality ..........................................................................5-20 LPC Bridge (w/ System and Management Functions) (D31:F0).................5-20 5.3.1 LPC Interface .................................................................................5-21 5.3.1.1 LPC Cycle Types............................................................5-21 5.3.1.2 Start Field Definition .......................................................5-22 5.3.1.3 Cycle Type / Direction (CYCTYPE + DIR)......................5-22 5.3.1.4 Size.................................................................................5-22 5.3.1.5 SYNC..............................................................................5-23 5.3.1.6 SYNC Time-out ..............................................................5-23 5.3.1.7 SYNC Error Indication ....................................................5-23 5.3.1.8 LFRAME# Usage............................................................5-24 5.3.1.9 I/O Cycles .......................................................................5-25 5.3.1.10 Bus Master Cycles..........................................................5-25 5.3.1.11 LPC Power Management ...............................................5-25 5.3.1.12 Configuration and ICH2 Implications ..............................5-25 DMA Operation (D31:F0) ............................................................................5-26 5.4.1 Channel Priority .............................................................................5-26 5.4.2 Address Compatibility Mode ..........................................................5-27 5.4.3 Summary of DMA Transfer Sizes ..................................................5-27 5.4.4 Autoinitialize...................................................................................5-28 5.4.5 Software Commands .....................................................................5-29 PCI DMA .....................................................................................................5-30 5.5.1 PCI DMA Expansion Protocol ........................................................5-30 5.5.2 PCI DMA Expansion Cycles ..........................................................5-32 5.5.3 DMA Addresses .............................................................................5-32 5.5.4 DMA Data Generation....................................................................5-32 5.5.5 DMA Byte Enable Generation........................................................5-33 5.5.6 DMA Cycle Termination .................................................................5-33 5.5.7 LPC DMA .......................................................................................5-33
5.2
5.3
5.4
5.5
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5.6
5.7
5.8
5.9
5.10
5.5.8 Asserting DMA Requests...............................................................5-33 5.5.9 Abandoning DMA Requests ..........................................................5-34 5.5.10 General Flow of DMA Transfers ....................................................5-35 5.5.11 Terminal Count ..............................................................................5-35 5.5.12 Verify Mode....................................................................................5-35 5.5.13 DMA Request Deassertion ............................................................5-36 5.5.14 SYNC Field / LDRQ# Rules ...........................................................5-37 8254 Timers (D31:F0).................................................................................5-38 5.6.1 Timer Programming .......................................................................5-38 5.6.2 Reading from the Interval Timer ....................................................5-39 8259 Interrupt Controllers (PIC) (D31:F0) ..................................................5-41 5.7.1 Interrupt Handling ..........................................................................5-42 5.7.1.1 Generating Interrupts .....................................................5-42 5.7.1.2 Acknowledging Interrupts ...............................................5-42 5.7.1.3 Hardware/Software Interrupt Sequence .........................5-43 5.7.2 Initialization Command Words (ICWx) ...........................................5-43 5.7.3 Operation Command Words (OCW) ..............................................5-44 5.7.4 Modes of Operation .......................................................................5-45 5.7.5 Masking Interrupts .........................................................................5-47 5.7.6 Steering PCI Interrupts ..................................................................5-47 Advanced Interrupt Controller (APIC) (D31:F0) ..........................................5-48 5.8.1 Interrupt Handling ..........................................................................5-48 5.8.2 Interrupt Mapping...........................................................................5-49 5.8.3 APIC Bus Functional Description...................................................5-50 5.8.3.1 Physical Characteristics of APIC....................................5-50 5.8.3.2 APIC Bus Arbitration ......................................................5-50 5.8.3.3 Bus Message Formats ...................................................5-51 5.8.4 PCI Message-Based Interrupts......................................................5-56 5.8.4.1 Theory of Operation .......................................................5-56 5.8.4.2 Registers and Bits Associated with PCI Interrupt Delivery ..........................................................................5-56 5.8.5 Front-Side Interrupt Delivery..........................................................5-57 5.8.5.1 Theory of Operation .......................................................5-57 5.8.5.2 Edge-Triggered Operation..............................................5-57 5.8.5.3 Level-Triggered Operation .............................................5-57 5.8.5.4 Registers Associated with Front-Side Bus Interrupt Delivery ..........................................................................5-58 5.8.5.5 Interrupt Message Format ..............................................5-58 Serial Interrupt (D31:F0) .............................................................................5-60 5.9.1 Start Frame....................................................................................5-60 5.9.2 Data Frames ..................................................................................5-60 5.9.3 Stop Frame ....................................................................................5-61 5.9.4 Specific Interrupts not Supported via SERIRQ ..............................5-61 5.9.5 Data Frame Format .......................................................................5-62 Real Time Clock (D31:F0) ..........................................................................5-63 5.10.1 Update Cycles ...............................................................................5-63 5.10.2 Interrupts........................................................................................5-64 5.10.3 Lockable RAM Ranges ..................................................................5-64 5.10.4 Century Rollover ............................................................................5-64 5.10.5 Clearing Battery-Backed RTC RAM...............................................5-64
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5.11
5.12
Processor Interface (D31:F0)......................................................................5-66 5.11.1 Processor Interface Signals ...........................................................5-66 5.11.1.1 A20M# ............................................................................5-66 5.11.1.2 INIT#...............................................................................5-66 5.11.1.3 FERR#/IGNNE# (Coprocessor Error).............................5-67 5.11.1.4 NMI .................................................................................5-67 5.11.1.5 STPCLK# and CPUSLP# Signals ..................................5-68 5.11.1.6 CPUPWRGOOD Signal..................................................5-68 5.11.2 Dual Processor Issues (82801BA ICH2 only) ................................5-68 5.11.2.1 Signal Differences (82801BA ICH2 only) .......................5-68 5.11.2.2 Power Management (82801BA ICH2 only) ....................5-68 5.11.3 Speed Strapping for Processor......................................................5-69 Power Management (D31:F0).....................................................................5-71 5.12.1 ICH2 and System Power States ....................................................5-72 5.12.2 System Power Planes....................................................................5-74 5.12.3 ICH2 Power Planes........................................................................5-74 5.12.4 SMI#/SCI Generation.....................................................................5-74 5.12.5 Dynamic Processor Clock Control .................................................5-77 5.12.5.1 Throttling Using STPCLK# .............................................5-78 5.12.5.2 Transition Rules Among S0/Cx and Throttling States ....5-78 5.12.6 Dynamic PCI Clock Control (82801BAM ICH2-M) .........................5-79 5.12.6.1 Conditions for Stopping the PCI Clock (82801BAM ICH2-M) ......................................................5-79 5.12.6.2 Conditions for Maintaining the PCI Clock (82801BAM ICH2-M) ......................................................5-79 5.12.6.3 Conditions for Stopping the PCI Clock (82801BAM ICH2-M) ......................................................5-79 5.12.6.4 Conditions for Re-Starting the PCI Clock (82801BAM ICH2-M) ......................................................5-80 5.12.6.5 Other Causes of CLKRUN# Going Active (82801BAM ICH2-M) ......................................................5-80 5.12.6.6 LPC Devices and CLKRUN# (82801BAM ICH2-M) .......5-80 5.12.7 Sleep States...................................................................................5-81 5.12.7.1 Initiating Sleep State.......................................................5-81 5.12.7.2 Exiting Sleep States .......................................................5-81 5.12.7.3 Sx–G3–Sx, Handling Power Failures .............................5-83 5.12.8 Thermal Management....................................................................5-84 5.12.8.1 THRM# Signal ................................................................5-84 5.12.8.2 THRM# Initiated Passive Cooling...................................5-84 5.12.8.3 THRM# Override Software Bit ........................................5-84 5.12.8.4 Processor-Initiated Passive Cooling (Via Programmed Duty Cycle on STPCLK#)..................5-85 5.12.8.5 Active Cooling.................................................................5-85 5.12.9 Intel® SpeedStep™ Technology Protocol (82801BAM ICH2-M only)..............................................................5-85 5.12.9.1 Intel® SpeedStep™ Technology Processor Requirements (82801BAM ICH2-M)...............................5-86 5.12.9.2 Intel® SpeedStep™ Technology States (82801BAM ICH2-M) ......................................................5-86 5.12.9.3 Voltage Regulator Interface (82801BAM ICH2-M) .........5-87
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5.13
5.14 5.15
5.16
5.12.10 Event Input Signals and Their Usage ............................................5-87 5.12.10.1 PWRBTN# — Power Button...........................................5-87 5.12.10.2 RI# — Ring Indicate .......................................................5-88 5.12.10.3 PME# — PCI Power Management Event.......................5-88 5.12.10.4 AGPBUSY# (82801BAM ICH2-M) .................................5-88 5.12.11 Alt Access Mode ............................................................................5-89 5.12.11.1 Write Only Registers with Read Paths in Alternate Access Mode ..................................................5-89 5.12.11.2 PIC Reserved Bits ..........................................................5-91 5.12.11.3 Read Only Registers with Write Paths in Alternate Access Mode ..................................................5-91 5.12.12 System Power Supplies, Planes, and Signals ...............................5-91 5.12.13 Clock Generators ...........................................................................5-93 5.12.13.1 Clock Control Signals from ICH2-M to Clock Synthesizer (82801BAM ICH2-M only) ..........................5-93 5.12.14 Legacy Power Management Theory of Operation .........................5-94 5.12.14.1 Desktop APM Power Management (82801BA ICH2 only) .....................................................5-94 5.12.14.2 Mobile APM Power Management (82801BAM ICH2-M only) ..............................................5-94 System Management (D31:F0)...................................................................5-95 5.13.1 Theory of Operation.......................................................................5-95 5.13.2 Alert on LAN* .................................................................................5-96 General Purpose I/O...................................................................................5-98 IDE Controller (D31:F1) ..............................................................................5-99 5.15.1 PIO Transfers ................................................................................5-99 5.15.2 Bus Master Function ....................................................................5-101 5.15.3 Ultra ATA/33 Protocol ..................................................................5-105 5.15.4 Ultra ATA/66 Protocol ..................................................................5-107 5.15.5 Ultra ATA/100 Protocol ................................................................5-107 5.15.6 Ultra ATA/33/66/100 Timing ........................................................5-107 5.15.7 Mobile IDE Swap Bay (82801BAM ICH2-M only) ........................5-107 USB Controller (Device 31:Functions 2 and 4) .........................................5-108 5.16.1 Data Structures in Main memory .................................................5-108 5.16.1.1 Frame List Pointer ........................................................5-108 5.16.1.2 Transfer Descriptor (TD) ..............................................5-109 5.16.1.3 Queue Head (QH) ........................................................5-113 5.16.2 Data Transfers To/From Main Memory........................................5-114 5.16.2.1 Executing the Schedule................................................5-114 5.16.2.2 Processing Transfer Descriptors ..................................5-114 5.16.2.3 Command Register, Status Register, and TD Status Bit Interaction ....................................................5-115 5.16.2.4 Transfer Queuing .........................................................5-116 5.16.3 Data Encoding and Bit Stuffing....................................................5-119 5.16.4 Bus Protocol ................................................................................5-120 5.16.4.1 Bit Ordering ..................................................................5-120 5.16.4.2 SYNC Field...................................................................5-120 5.16.4.3 Packet Field Formats ...................................................5-120 5.16.4.4 Address Fields..............................................................5-121 5.16.4.5 Frame Number Field ....................................................5-122 5.16.4.6 Data Field .....................................................................5-122 5.16.4.7 Cyclic Redundancy Check (CRC) ................................5-122
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
5.17
5.18
5.19
5.16.5 Packet Formats............................................................................5-123 5.16.5.1 Token Packets..............................................................5-123 5.16.5.2 Start of Frame Packets.................................................5-123 5.16.5.3 Data Packets ................................................................5-124 5.16.5.4 Handshake Packets......................................................5-124 5.16.5.5 Handshake Responses ................................................5-125 5.16.6 USB Interrupts .............................................................................5-125 5.16.6.1 Transaction Based Interrupts .......................................5-125 5.16.6.2 Non-Transaction Based Interrupts................................5-127 5.16.7 USB Power Management ............................................................5-127 5.16.8 USB Legacy Keyboard Operation................................................5-128 SMBus Controller Functional Description (D31:F3) ..................................5-130 5.17.1 Host Controller .............................................................................5-130 5.17.1.1 Command Protocols .....................................................5-131 5.17.1.2 I2C Behavior .................................................................5-136 5.17.1.3 Heartbeat for Use With the External LAN Controller ....5-136 5.17.2 Bus Arbitration .............................................................................5-137 5.17.3 Interrupts / SMI# ..........................................................................5-137 5.17.4 SMBALERT#................................................................................5-138 5.17.5 SMBus Slave Interface ................................................................5-138 AC’97 Controller Functional Description (Audio D31:F5, Modem D31:F6)5-142 5.18.1 AC-link Overview .........................................................................5-143 5.18.2 AC-Link Low Power Mode ...........................................................5-151 5.18.3 AC‘97 Cold Reset ........................................................................5-152 5.18.4 AC‘97 Warm Reset ......................................................................5-152 5.18.5 System Reset...............................................................................5-153 Firmware Hub Interface ............................................................................5-154 5.19.1 Field Definitions ...........................................................................5-154 5.19.2 Protocol........................................................................................5-155 PCI Devices and Functions...........................................................................6-1 PCI Configuration Map..................................................................................6-2 I/O Map .........................................................................................................6-2 6.3.1 Fixed I/O Address Ranges...............................................................6-3 6.3.2 Variable I/O Decode Ranges ...........................................................6-5 Memory Map .................................................................................................6-6 6.4.1 Boot-Block Update Scheme.............................................................6-7 PCI Configuration Registers (B1:D8:F0).......................................................7-1 7.1.1 VID—Vendor ID Register (LAN Controller—B1:D8:F0) ...................7-2 7.1.2 DID—Device ID Register (LAN Controller—B1:D8:F0) ...................7-2 7.1.3 PCICMD—PCI Command Register (LAN Controller—B1:D8:F0) ............................................................7-2 7.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0) ...........7-3 7.1.5 REVID—Revision ID Register (LAN Controller—B1:D8:F0) ............7-3 7.1.6 SCC—Sub-Class Code Register (LAN Controller—B1:D8:F0) ............................................................7-4 7.1.7 BCC—Base-Class Code Register (LAN Controller—B1:D8:F0) ............................................................7-4 7.1.8 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0) ........7-4
6
Register and Memory Mapping..................................................................................6-1 6.1 6.2 6.3
6.4 7
LAN Controller Registers (B1:D8:F0).........................................................................7-1 7.1
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7.2
PMLT—PCI Master Latency Timer Register (LAN Controller—B1:D8:F0) ............................................................7-4 7.1.10 HEADTYP—Header Type Register (LAN Controller—B1:D8:F0) ............................................................7-5 7.1.11 CSR_MEM_BASE CSR—Memory-Mapped Base Address Register (LAN Controller—B1:D8:F0)..............................................7-5 7.1.12 CSR_IO_BASE—CSR I/O-Mapped Base Address Register (LAN Controller—B1:D8:F0) ............................................................7-5 7.1.13 SVID—Subsystem Vendor ID (LAN Controller—B1:D8:F0) ............7-6 7.1.14 SID—Subsystem ID (LAN Controller—B1:D8:F0) ...........................7-6 7.1.15 CAP_PTR—Capabilities Pointer (LAN Controller—B1:D8:F0) ........7-6 7.1.16 INT_LN—Interrupt Line Register (LAN Controller—B1:D8:F0)........7-7 7.1.17 INT_PN—Interrupt Pin Register (LAN Controller—B1:D8:F0).........7-7 7.1.18 MIN_GNT—Minimum Grant Register (LAN Controller—B1:D8:F0) ............................................................7-7 7.1.19 MAX_LAT—Maximum Latency Register (LAN Controller—B1:D8:F0) ............................................................7-7 7.1.20 CAP_ID—Capability ID Register (LAN Controller—B1:D8:F0)........7-8 7.1.21 NXT_PTR—Next Item Pointer (LAN Controller—B1:D8:F0) ...........7-8 7.1.22 PM_CAP—Power Management Capabilities (LAN Controller—B1:D8:F0) ............................................................7-8 7.1.23 PMCSR—Power Management Control/Status Register (LAN Controller—B1:D8:F0) ............................................................7-9 7.1.24 DATA—Data Register (LAN Controller—B1:D8:F0) ........................7-9 LAN Control / Status Registers (CSR) ........................................................7-10 7.2.1 System Control Block Status Word Register .................................7-11 7.2.2 System Control Block Command Word Register ...........................7-12 7.2.3 System Control Block General Pointer Register ............................7-14 7.2.4 PORT Register ..............................................................................7-14 7.2.5 EEPROM Control Register ............................................................7-15 7.2.6 Management Data Interface (MDI) Control Register .....................7-16 7.2.7 Receive DMA Byte Count Register................................................7-16 7.2.8 Early Receive Interrupt Register ....................................................7-17 7.2.9 Flow Control Register ....................................................................7-18 7.2.10 Power Management Driver (PMDR) Register................................7-19 7.2.11 General Control Register ...............................................................7-19 7.2.12 General Status Register ................................................................7-20 7.2.13 Statistical Counters ........................................................................7-20 PCI Configuration Registers (D30:F0) ..........................................................8-1 8.1.1 VID—Vendor ID Register (HUB-PCI—D30:F0) ...............................8-2 8.1.2 DID—Device ID Register (HUB-PCI—D30:F0)................................8-2 8.1.3 CMD—Command Register (HUB-PCI—D30:F0).............................8-3 8.1.4 PD_STS—Primary Device Status Register (HUB-PCI—D30:F0) ........................................................................8-4 8.1.5 REVID—Revision ID Register (HUB-PCI—D30:F0) ........................8-4 8.1.6 SCC—Sub-Class Code Register (HUB-PCI—D30:F0)....................8-5 8.1.7 BCC—Base-Class Code Register (HUB-PCI—D30:F0)..................8-5 8.1.8 PMLT—Primary Master Latency Timer Register (HUB-PCI—D30:F0) ........................................................................8-5 8.1.9 HEADTYP—Header Type Register (HUB-PCI—D30:F0)................8-5
7.1.9
8
Hub Interface to PCI Bridge Registers (D30:F0) .......................................................8-1 8.1
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8.1.10 PBUS_NUM—Primary Bus Number Register (HUB-PCI—D30:F0) ........................................................................8-6 8.1.11 SBUS_NUM—Secondary Bus Number Register (HUB-PCI—D30:F0) ........................................................................8-6 8.1.12 SUB_BUS_NUM—Subordinate Bus Number Register (HUB-PCI—D30:F0) ........................................................................8-6 8.1.13 SMLT—Secondary Master Latency Timer Register (HUB-PCI—D30:F0) ........................................................................8-6 8.1.14 IOBASE—I/O Base Register (HUB-PCI—D30:F0) ..........................8-7 8.1.15 IOLIM—I/O Limit Register (HUB-PCI—D30:F0) ..............................8-7 8.1.16 SECSTS—Secondary Status Register (HUB-PCI—D30:F0)...........8-8 8.1.17 MEMBASE—Memory Base Register (HUB-PCI—D30:F0) .............8-9 8.1.18 MEMLIM—Memory Limit Register (HUB-PCI—D30:F0) .................8-9 8.1.19 PREF_MEM_BASE—Prefetchable Memory Base Register (HUB-PCI—D30:F0) ........................................................................8-9 8.1.20 PREF_MEM_MLT—Prefetchable Memory Limit Register (HUB-PCI—D30:F0) ......................................................................8-10 8.1.21 IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-PCI—D30:F0) ......................................................................8-10 8.1.22 IOLIM_HI—I/O Limit Upper 16 Bits Register (HUB-PCI—D30:F0) ......................................................................8-10 8.1.23 INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0) ..............8-10 8.1.24 BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0) .....8-11 8.1.25 BRIDGE_CNT2—Bridge Control Register 2 (HUB-PCI—D30:F0) ......................................................................8-11 8.1.26 CNF—ICH2 Configuration Register (HUB-PCI—D30:F0) .............8-12 8.1.27 MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0) ......8-12 8.1.28 PCI_MAST_STS—PCI Master Status Register (HUB-PCI—D30:F0) ......................................................................8-13 8.1.29 ERR_CMD—Error Command Register (HUB-PCI—D30:F0) ........8-13 8.1.30 ERR_STS—Error Status Register (HUB-PCI—D30:F0)................8-14 9 LPC Interface Bridge Registers (D31:F0) ..................................................................9-1 9.1 PCI Configuration Registers (D31:F0) ..........................................................9-1 9.1.1 VID—Vendor ID Register (LPC I/F—D31:F0) ..................................9-2 9.1.2 DID—Device ID Register (LPC I/F—D31:F0) ..................................9-2 9.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ................9-3 9.1.4 PCISTS—PCI Device Status (LPC I/F—D31:F0) ............................9-4 9.1.5 REVID—Revision ID Register (LPC I/F—D31:F0)...........................9-4 9.1.6 PI—Programming Interface (LPC I/F—D31:F0) ..............................9-5 9.1.7 SCC—Sub-Class Code Register (LPC I/F—D31:F0) ......................9-5 9.1.8 BCC—Base-Class Code Register (LPC I/F—D31:F0) ....................9-5 9.1.9 HEADTYP—Header Type Register (LPC I/F—D31:F0) ..................9-5 9.1.10 PMBASE—ACPI Base Address (LPC I/F—D31:F0)........................9-6 9.1.11 ACPI_CNTL—ACPI Control (LPC I/F—D31:F0)..............................9-6 9.1.12 BIOS_CNTL (LPC I/F—D31:F0) ......................................................9-7 9.1.13 TCO_CNTL—TCO Control (LPC I/F—D31:F0) ...............................9-7 9.1.14 GPIOBASE—GPIO Base Address (LPC I/F—D31:F0) ...................9-8 9.1.15 GPIO_CNTL—GPIO Control (LPC I/F—D31:F0) ............................9-8 9.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control (LPC I/F—D31:F0) ...........................................................................9-8 9.1.17 SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0) ................9-9
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9.2
9.3
9.4
9.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control (LPC I/F—D31:F0) ...........................................................................9-9 9.1.19 D31_ERR_CFG—Device 31 Error Configuration Register (LPC I/F—D31:F0) .........................................................................9-10 9.1.20 D31_ERR_STS—Device 31 Error Status Register (LPC I/F—D31:F0) .........................................................................9-10 9.1.21 PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0) .....9-11 9.1.22 GEN_CNTL—General Control Register (LPC I/F—D31:F0) .........9-11 9.1.23 GEN_STS—General Status (LPC I/F—D31:F0)............................9-13 9.1.24 RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0).....9-14 9.1.25 COM_DEC—LPC I/F Communication Port Decode Ranges (LPC I/F—D31:F0) .........................................................................9-14 9.1.26 FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges (LPC I/F—D31:F0) .........................................................................9-15 9.1.27 SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F—D31:F0) .........................................................................9-15 9.1.28 FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—D31:F0) .........................................................................9-16 9.1.29 GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/F—D31:F0) .........................................................................9-17 9.1.30 LPC_EN—LPC I/F Enables (LPC I/F—D31:F0) ............................9-17 9.1.31 FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0).............9-19 9.1.32 GEN2_DEC—LPC I/F Generic Decode Range 2 (LPC I/F—D31:F0) .........................................................................9-20 9.1.33 FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0).............9-20 9.1.34 FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—D31:F0) .........................................................................9-21 9.1.35 FUNC_DIS—Function Disable Register (LPC I/F—D31:F0) .........9-22 DMA I/O Registers......................................................................................9-23 9.2.1 DMABASE_CA—DMA Base and Current Address Registers .......9-24 9.2.2 DMABASE_CC—DMA Base and Current Count Registers...........9-25 9.2.3 DMAMEM_LP—DMA Memory Low Page Registers .....................9-25 9.2.4 DMACMD—DMA Command Register ...........................................9-26 9.2.5 DMASTS—DMA Status Register...................................................9-26 9.2.6 DMA_WRSMSK—DMA Write Single Mask Register.....................9-27 9.2.7 DMACH_MODE—DMA Channel Mode Register...........................9-27 9.2.8 DMA Clear Byte Pointer Register ..................................................9-28 9.2.9 DMA Master Clear Register ...........................................................9-28 9.2.10 DMA_CLMSK—DMA Clear Mask Register ...................................9-28 9.2.11 DMA_WRMSK—DMA Write All Mask Register .............................9-29 Timer I/O Registers.....................................................................................9-30 9.3.1 TCW—Timer Control Word Register .............................................9-30 9.3.1.1 RDBK_CMD—Read Back Command ............................9-31 9.3.1.2 LTCH_CMD—Counter Latch Command ........................9-31 9.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register ..........9-32 9.3.3 Counter Access Ports Register......................................................9-32 8259 Interrupt Controller (PIC) Registers ...................................................9-33 9.4.1 Interrupt Controller I/O MAP ..........................................................9-33 9.4.2 ICW1—Initialization Command Word 1 Register ...........................9-34 9.4.3 ICW2—Initialization Command Word 2 Register ...........................9-35 9.4.4 ICW3—Master Controller Initialization Command Word 3 Register .........................................................................................9-35
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9.4.5
9.5
9.6
9.7
9.8
ICW3—Slave Controller Initialization Command Word 3 Register..........................................................................................9-36 9.4.6 ICW4—Initialization Command Word 4 Register ...........................9-36 9.4.7 OCW1—Operational Control Word 1 (Interrupt Mask) Register ....9-36 9.4.8 OCW2—Operational Control Word 2 Register ..............................9-37 9.4.9 OCW3—Operational Control Word 3 Register ..............................9-38 9.4.10 ELCR1—Master Controller Edge/Level Triggered Register ..........9-39 9.4.11 ELCR2—Slave Controller Edge/Level Triggered Register ............9-40 Advanced Interrupt Controller (APIC) .........................................................9-41 9.5.1 APIC Register Map ........................................................................9-41 9.5.2 IND—Index Register ......................................................................9-41 9.5.3 DAT—Data Register ......................................................................9-42 9.5.4 IRQPA—IRQ Pin Assertion Register .............................................9-42 9.5.5 EOIR—EOI Register ......................................................................9-43 9.5.6 ID—Identification Register .............................................................9-43 9.5.7 VER—Version Register .................................................................9-44 9.5.8 ARBID—Arbitration ID Register .....................................................9-44 9.5.9 BOOT_CONFIG—Boot Configuration Register .............................9-44 9.5.10 Redirection Table...........................................................................9-45 Real Time Clock Registers .........................................................................9-47 9.6.1 I/O Register Address Map..............................................................9-47 9.6.2 Indexed Registers ..........................................................................9-47 9.6.2.1 RTC_REGA—Register A................................................9-48 9.6.2.2 RTC_REGB—Register B (General Configuration) .........9-49 9.6.2.3 RTC_REGC—Register C (Flag Register) ......................9-50 9.6.2.4 RTC_REGD—Register D (Flag Register) ......................9-50 Processor Interface Registers.....................................................................9-51 9.7.1 NMI_SC—NMI Status and Control Register ..................................9-51 9.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) ....................9-52 9.7.3 PORT92—Fast A20 and Init Register............................................9-52 9.7.4 COPROC_ERR—Coprocessor Error Register ..............................9-52 9.7.5 RST_CNT—Reset Control Register ..............................................9-53 Power Management Registers (D31:F0) ....................................................9-54 9.8.1 Power Management PCI Configuration Registers (D31:F0) ..........9-54 9.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0) ..................................................9-54 9.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0) ..................................................9-56 9.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register (PM—D31:F0) ..................................................9-57 9.8.1.4 GPI_ROUT—GPI Routing Control Register (PM—D31:F0) ................................................................9-57 9.8.1.5 TRP_FWD_EN—IO Monitor Trap Forwarding Enable Register (PM—D31:F0)......................................9-58 9.8.1.6 MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range Register for Devices 4–7 (PM—D31:F0) ........................9-59 9.8.1.7 MON_TRP_MSK—I/O Monitor Trap Range Mask Register for Devices 4–7 (PM—D31:F0) ........................9-59 9.8.2 APM I/O Decode ............................................................................9-60 9.8.2.1 APM_CNT—Advanced Power Management Control Port Register ......................................................9-60 9.8.2.2 APM_STS—Advanced Power Management Status Port Register .......................................................9-60
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9.9
9.10
Power Management I/O Registers.................................................9-61 9.8.3.1 PM1_STS—Power Management 1 Status Register.......9-62 9.8.3.2 PM1_EN—Power Management 1 Enable Register........9-64 9.8.3.3 PM1_CNT—Power Management 1 Control Register .....9-65 9.8.3.4 PM1_TMR—Power Management 1 Timer Register .......9-66 9.8.3.5 PROC_CNT—Processor Control Register .....................9-66 9.8.3.6 LV2—Level 2 Register ...................................................9-67 9.8.3.7 LV3—Level 3 Register (82801BAM ICH2-M) .................9-67 9.8.3.8 PM2_CNT—Power Management 2 Control (82801BAM ICH2-M)......................................................9-68 9.8.3.9 GPE0_STS—General Purpose Event 0 Status Register ..........................................................................9-68 9.8.3.10 GPE0_EN—General Purpose Event 0 Enables Register ..........................................................................9-70 9.8.3.11 GPE1_STS—General Purpose Event 1 Status Register ..........................................................................9-71 9.8.3.12 GPE1_EN—General Purpose Event 1 Enable Register ..........................................................................9-72 9.8.3.13 SMI_EN—SMI Control and Enable Register ..................9-72 9.8.3.14 SMI_STS—SMI Status Register ....................................9-74 9.8.3.15 MON_SMI—Device Monitor SMI Status and Enable Register ..........................................................................9-75 9.8.3.16 DEVACT_STS—Device Activity Status Register ...........9-76 9.8.3.17 DEVTRAP_EN—Device Trap Enable Register ..............9-77 9.8.3.18 BUS_ADDR_TRACK—Bus Address Tracker Register ..9-78 9.8.3.19 BUS_CYC_TRACK—Bus Cycle Tracker Register .........9-78 9.8.3.20 SS_CNT— SpeedStep™ Control Register (82801BAM ICH2-M)......................................................9-78 System Management TCO Registers (D31:F0) ..........................................9-79 9.9.1 TCO Register I/O Map ...................................................................9-79 9.9.2 TCO1_RLD—TCO Timer Reload and Current Value Register......9-79 9.9.3 TCO1_TMR—TCO Timer Initial Value Register ............................9-80 9.9.4 TCO1_DAT_IN—TCO Data In Register ........................................9-80 9.9.5 TCO1_DAT_OUT—TCO Data Out Register..................................9-80 9.9.6 TCO1_STS—TCO1 Status Register..............................................9-80 9.9.7 TCO2_STS—TCO2 Status Register..............................................9-82 9.9.8 TCO1_CNT—TCO1 Control Register............................................9-83 9.9.9 TCO2_CNT—TCO2 Control Register............................................9-83 9.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................9-84 9.9.11 TCO_WDSTATUS—TCO2 Control Register .................................9-84 9.9.12 SW_IRQ_GEN—Software IRQ Generation Register.....................9-84 General Purpose I/O Registers (D31:F0) ...................................................9-85 9.10.1 GPIO Register I/O Address Map....................................................9-87 9.10.2 GPIO_USE_SEL—GPIO Use Select Register ..............................9-87 9.10.3 GP_IO_SEL—GPIO Input/Output Select Register ........................9-88 9.10.4 GP_LVL—GPIO Level for Input or Output Register.......................9-89 9.10.5 GPO_BLINK—GPO Blink Enable Register....................................9-90 9.10.6 GPI_INV—GPIO Signal Invert Register.........................................9-91
9.8.3
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10
IDE Controller Registers (D31:F1) ...........................................................................10-1 10.1 PCI Configuration Registers (IDE—D31:F1)...............................................10-1 10.1.1 VID—Vendor ID Register (IDE—D31:F1) ......................................10-2 10.1.2 DID—Device ID Register (IDE—D31:F1) ......................................10-2 10.1.3 CMD—Command Register (IDE—D31:F1) ...................................10-2 10.1.4 STS—Device Status Register (IDE—D31:F1) ...............................10-3 10.1.5 RID—Revision ID Register (HUB-PCI—D30:F0) ...........................10-3 10.1.6 PI—Programming Interface (IDE—D31:F1)...................................10-3 10.1.7 SCC—Sub Class Code (IDE—D31:F1) .........................................10-4 10.1.8 BCC—Base Class Code (IDE—D31:F1) .......................................10-4 10.1.9 MLT—Master Latency Timer (IDE—D31:F1).................................10-4 10.1.10 BM_BASE—Bus Master Base Address Register (IDE—D31:F1) ...............................................................................10-4 10.1.11 IDE_SVID—Subsystem Vendor ID (IDE—D31:F1) .......................10-5 10.1.12 IDE_SID—Subsystem ID (IDE—D31:F1) ......................................10-5 10.1.13 IDE_TIM—IDE Timing Register (IDE—D31:F1) ............................10-5 10.1.14 SLV_IDETIM—Slave (Drive 1) IDE Timing Register (IDE—D31:F1) ...............................................................................10-7 10.1.15 SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1) ...............................................................................10-8 10.1.16 SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1) ...............................................................................10-8 10.1.17 IDE_CONFIG—IDE I/O Configuration Register.............................10-9 Bus Master IDE I/O Registers (D31:F1)....................................................10-11 10.2.1 BMIC[P,S]—Bus Master IDE Command Register .......................10-11 10.2.2 BMIS[P,S]—Bus Master IDE Status Register ..............................10-12 10.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register .10-12 PCI Configuration Registers (D31:F2/F4) ...................................................11-1 11.1.1 VID—Vendor Identification Register (USB—D31:F2/F4) ...............11-1 11.1.2 DID—Device Identification Register (USB—D31:F2/F4) ...............11-2 11.1.3 CMD—Command Register (USB—D31:F2/F4) .............................11-2 11.1.4 STA—Device Status Register (USB—D31:F2/F4) ........................11-3 11.1.5 RID—Revision Identification Register (USB—D31:F2/F4) ............11-3 11.1.6 PI—Programming Interface (USB—D31:F2/F4) ............................11-3 11.1.7 SCC—Sub Class Code Register (USB—D31:F2/F4) ....................11-4 11.1.8 BCC—Base Class Code Register (USB—D31:F2/F4) ..................11-4 11.1.9 BASE—Base Address Register (USB—D31:F2/F4)......................11-4 11.1.10 SVID—Subsystem Vendor ID (USB—D31:F2/F4).........................11-4 11.1.11 SID—Subsystem ID (USB—D31:F2/F4)........................................11-5 11.1.12 INTR_LN—Interrupt Line Register (USB—D31:F2/F4) .................11-5 11.1.13 INTR_PN—Interrupt Pin Register (USB—D31:F2/F4)...................11-5 11.1.14 SB_RELNUM—Serial Bus Release Number Register (USB—D31:F2/F4).........................................................................11-5 11.1.15 USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register (USB—D31:F2/F4) ..........................................................11-6 11.1.16 USB_RES—USB Resume Enable Register (USB—D31:F2/F4).........................................................................11-7 USB I/O Registers.......................................................................................11-8 11.2.1 USBCMD—USB Command Register ............................................11-8 11.2.2 USBSTA—USB Status Register ..................................................11-11
10.2
11
USB Controller Registers.........................................................................................11-1 11.1
11.2
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11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 12 12.1
USBINTR—Interrupt Enable Register..........................................11-12 FRNUM—Frame Number Register..............................................11-12 FRBASEADD—Frame List Base Address ...................................11-13 SOFMOD—Start of Frame Modify Register.................................11-13 PORTSC[0,1]—Port Status and Control Register........................11-14
SMBus Controller Registers (D31:F3) .....................................................................12-1 PCI Configuration Registers (SMBUS—D31:F3)........................................12-1 12.1.1 VID—Vendor Identification Register (SMBUS—D31:F3)...............12-1 12.1.2 DID—Device Identification Register (SMBUS—D31:F3) ...............12-1 12.1.3 CMD—Command Register (SMBUS—D31:F3).............................12-2 12.1.4 STA—Device Status Register (SMBUS—D31:F3) ........................12-2 12.1.5 RID—Revision ID Register (SMBUS—D31:F3).............................12-3 12.1.6 PI—Programming Interface (SMBUS—D31:F3)............................12-3 12.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3)....................12-3 12.1.8 BCC—Base Class Code Register (SMBUS—D31:F3) ..................12-3 12.1.9 SMB_BASE—SMBus Base Address Register (SMBUS—D31:F3) ........................................................................12-4 12.1.10 SVID—Subsystem Vendor ID (SMBUS—D31:F2/F4) ...................12-4 12.1.11 SID—Subsystem ID (SMBUS—D31:F2/F4) ..................................12-4 12.1.12 INTR_LN—Interrupt Line Register (SMBUS—D31:F3) .................12-4 12.1.13 INTR_PN—Interrupt Pin Register (SMBUS—D31:F3) ..................12-5 12.1.14 HOSTC—Host Configuration Register (SMBUS—D31:F3) ...........12-5 SMBus I/O Registers ..................................................................................12-6 12.2.1 HST_STS—Host Status Register ..................................................12-7 12.2.2 HST_CNT—Host Control Register ................................................12-8 12.2.3 HST_CMD—Host Command Register...........................................12-9 12.2.4 XMIT_SLVA—Transmit Slave Address Register ...........................12-9 12.2.5 HST_D0—Data 0 Register.............................................................12-9 12.2.6 HST_D1—Data 1 Register.............................................................12-9 12.2.7 BLOCK_DB—Block Data Byte Register ......................................12-10 12.2.8 RCV_SLVA—Receive Slave Address Register ...........................12-10 12.2.9 SLV_DATA—Receive Slave Data Register .................................12-10 12.2.10 SMLINK_PIN_CTL—SMLINK Pin Control Register.....................12-11 12.2.11 SMBUS_PIN_CTL—SMBus Pin Control Register .......................12-11 AC’97 Audio PCI Configuration Space (D31:F5) ........................................13-1 13.1.1 VID—Vendor Identification Register (Audio—D31:F5) ..................13-1 13.1.2 DID—Device Identification Register (Audio—D31:F5)...................13-2 13.1.3 PCICMD—PCI Command Register (Audio—D31:F5) ...................13-2 13.1.4 PCISTS—PCI Device Status Register (Audio—D31:F5)...............13-3 13.1.5 RID—Revision Identification Register (Audio—D31:F5)................13-3 13.1.6 PI—Programming Interface Register (Audio—D31:F5) .................13-3 13.1.7 SCC—Sub Class Code Register (Audio—D31:F5) .......................13-4 13.1.8 BCC—Base Class Code Register (Audio—D31:F5)......................13-4 13.1.9 HEDT—Header Type Register (Audio—D31:F5) ..........................13-4 13.1.10 NAMBAR—Native Audio Mixer Base Address Register (Audio—D31:F5) ............................................................................13-5 13.1.11 NABMBAR—Native Audio Bus Mastering Base Address Register (Audio—D31:F5)..............................................................13-5 13.1.12 SVID—Subsystem Vendor ID Register (Audio—D31:F5)..............13-6
12.2
13
AC’97 Audio Controller Registers (D31:F5).............................................................13-1 13.1
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
13.2
13.1.13 SID—Subsystem ID Register (Audio—D31:F5).............................13-6 13.1.14 INTR_LN—Interrupt Line Register (Audio—D31:F5) .....................13-6 13.1.15 INTR_PN—Interrupt Pin Register (Audio—D31:F5) ......................13-7 AC’97 Audio I/O Space (D31:F5)................................................................13-7 13.2.1 x_BDBAR—Buffer Descriptor Base Address Register ..................13-9 13.2.2 x_CIV—Current Index Value Register .........................................13-10 13.2.3 x_LVI—Last Valid Index Register ................................................13-10 13.2.4 x_SR—Status Register ................................................................13-11 13.2.5 x_PICB—Position In Current Buffer Register ..............................13-12 13.2.6 x_PIV—Prefetched Index Value Register ....................................13-12 13.2.7 x_CR—Control Register ..............................................................13-13 13.2.8 GLOB_CNT—Global Control Register.........................................13-14 13.2.9 GLOB_STA—Global Status Register ..........................................13-15 13.2.10 CAS—Codec Access Semaphore Register .................................13-16 AC’97 Modem PCI Configuration Space (D31:F6) .....................................14-1 14.1.1 VID—Vendor Identification Register (Modem—D31:F6) ...............14-1 14.1.2 DID—Device Identification Register (Modem—D31:F6) ................14-2 14.1.3 PCICMD—PCI Command Register (Modem—D31:F6) ................14-2 14.1.4 PCISTA—Device Status Register (Modem—D31:F6) ...................14-3 14.1.5 RID—Revision Identification Register (Modem—D31:F6) .............14-3 14.1.6 PI—Programming Interface Register (Modem—D31:F6) ..............14-3 14.1.7 SCC—Sub Class Code Register (Modem—D31:F6).....................14-4 14.1.8 BCC—Base Class Code Register (Modem—D31:F6) ...................14-4 14.1.9 HEDT—Header Type Register (Modem—D31:F6)........................14-4 14.1.10 MMBAR—Modem Mixer Base Address Register (Modem—D31:F6) .........................................................................14-4 14.1.11 MBAR—Modem Base Address Register (Modem—D31:F6) ........14-5 14.1.12 SVID—Subsystem Vendor ID (Modem—D31:F6) .........................14-5 14.1.13 SID—Subsystem ID (Modem—D31:F6) ........................................14-6 14.1.14 INTR_LN—Interrupt Line Register (Modem—D31:F6) ..................14-6 14.1.15 INT_PIN—Interrupt Pin (Modem—D31:F6) ...................................14-6 AC’97 Modem I/O Space (D31:F6) .............................................................14-7 14.2.1 x_BDBAR—Buffer Descriptor List Base Address Register ............14-8 14.2.2 x_CIV—Current Index Value Register ...........................................14-9 14.2.3 x_LVI—Last Valid Index Register ..................................................14-9 14.2.4 x_SR—Status Register ................................................................14-10 14.2.5 x_PICB—Position In Current Buffer Register ..............................14-11 14.2.6 x_PIV—Prefetch Index Value Register ........................................14-11 14.2.7 x_CR—Control Register ..............................................................14-11 14.2.8 GLOB_CNT—Global Control Register.........................................14-12 14.2.9 GLOB_STA—Global Status Register ..........................................14-13 14.2.10 CAS—Codec Access Semaphore Register .................................14-14 Pinout..........................................................................................................15-1 Package Information .................................................................................15-14
14
AC’97 Modem Controller Registers (D31:F6) ..........................................................14-1 14.1
14.2
15
Pinout and Package Information..............................................................................15-1 15.1 15.2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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16
Electrical Characteristics .........................................................................................16-1 16.1 16.2 16.3 16.4 16.5 Absolute Maximum Ratings ........................................................................16-1 Functional Operating Range.......................................................................16-1 D.C. Characteristics....................................................................................16-2 A.C. Characteristics ....................................................................................16-7 Timing Diagrams.......................................................................................16-18 Test Mode Description................................................................................17-1 Tri-state Mode.............................................................................................17-2 XOR Chain Mode........................................................................................17-2 17.3.1 XOR Chain Testability Algorithm Example ....................................17-2 17.3.1.1 Test Pattern Consideration for XOR Chain 4 .................17-3
17
Testability.................................................................................................................17-1 17.1 17.2 17.3
A B
I/O Register Index..................................................................................................... A-1 Register Bit Index ..................................................................................................... B-1
xx
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Figures
2-1 2-2 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 15-1 15-2 15-3 15-4 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 Required External RTC Circuit....................................................................2-16 Example V5REF Sequencing Circuit ..........................................................2-16 ICH2 and System Clock Domains................................................................4-1 Conceptual System Clock Diagram (82801BA ICH2 and 82801BAM ICH2-M)......................................................................................4-2 Primary Device Status Register Error Reporting Logic.................................5-3 Secondary Status Register Error Reporting Logic ........................................5-3 NMI# Generation Logic .................................................................................5-4 Integrated LAN Controller Block Diagram.....................................................5-7 64-Word EEPROM Read Instruction Waveform .........................................5-17 LPC Interface Diagram ...............................................................................5-21 Typical Timing for LFRAME# ......................................................................5-24 Abort Mechanism ........................................................................................5-24 ICH2 DMA Controller ..................................................................................5-26 DMA Serial Channel Passing Protocol .......................................................5-30 DMA Request Assertion Through LDRQ# ..................................................5-34 Coprocessor Error Timing Diagram ............................................................5-67 Signal Strapping..........................................................................................5-70 Intel® SpeedStep™ Block Diagram (82801BAM ICH2-M only) ..................5-85 Physical Region Descriptor Table Entry ...................................................5-101 Transfer Descriptor ...................................................................................5-109 Example Queue Conditions ......................................................................5-116 USB Data Encoding ..................................................................................5-119 USB Legacy Keyboard Flow Diagram ......................................................5-128 ICH2 Based AC’97 2.1..............................................................................5-143 AC’97 2.1 Controller-Codec Connection...................................................5-144 AC-link Protocol ........................................................................................5-145 AC-link Powerdown Timing.......................................................................5-151 SDIN Wake Signaling ...............................................................................5-152 FWH Memory Cycle Preamble .................................................................5-155 Single Byte Read ......................................................................................5-155 Single Byte Write ......................................................................................5-156 ICH2 82801BA and ICH2-M 82801BAM Ballout (Top view — Left side) ................................................................................15-2 ICH2 82801BA and ICH2-M 82801BAM Ballout (Top view — Right side)..............................................................................15-3 ICH2 / ICH2-M Package (Top and Side Views) ........................................15-14 ICH2 / ICH2-M Package (Bottom View)....................................................15-15 Clock Timing .............................................................................................16-18 Valid Delay From Rising Clock Edge ........................................................16-18 Setup And Hold Times ..............................................................................16-18 Float Delay................................................................................................16-18 Pulse Width...............................................................................................16-19 Output Enable Delay.................................................................................16-19 IDE PIO Mode...........................................................................................16-19 IDE Multiword DMA...................................................................................16-20 Ultra ATA Mode (Drive Initiating a Burst Read) ........................................16-20 Ultra ATA Mode (Sustained Burst)............................................................16-21 Ultra ATA Mode (Pausing a DMA Burst)...................................................16-21
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 16-20 16-21 16-22 16-23 16-24 16-25 16-26 16-27 16-28 17-1 17-2
Ultra ATA Mode (Terminating a DMA Burst) ............................................16-22 USB Rise and Fall Times..........................................................................16-22 USB Jitter..................................................................................................16-22 USB EOP Width........................................................................................16-23 SMBus Transaction ..................................................................................16-23 SMBus Time-out .......................................................................................16-23 Power Sequencing and Reset Signal Timings (82801BA ICH2 only)................................................................................16-24 Power Sequencing and Reset Signal Timings (82801BAM ICH2-M only).........................................................................16-24 1.8V/3.3V Power Sequencing...................................................................16-25 G3 (Mechanical Off) to S0 Timings (82801BA ICH2 only)........................16-25 G3 (Mechanical Off) to S0 Timings (82801BAM ICH2-M only) ................16-26 S0 to S1 to S0 Timings (82801BA ICH2 only) ..........................................16-26 S0 to S1 to S0 Timings (82801BAM ICH2-M only) ...................................16-27 S0 to S5 to S0 Timings (82801BA ICH2 only) ..........................................16-27 S0 to S5 to S0 Timings (82801BAM ICH2-M only) ...................................16-28 C0 to C2 to C0 Timings ............................................................................16-28 C0 to C3 to C0 Timings (82801BAM ICH2-M only) ..................................16-29 Test Mode Entry (XOR Chain Example).....................................................17-1 Example XOR Chain Circuitry ....................................................................17-2
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Tables
1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 3-1 3-2 3-3 3-4 3-5 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 Industry Specifications ..................................................................................1-1 PCI Devices and Functions...........................................................................1-3 Hub Interface Signals....................................................................................2-1 LAN Connect Interface Signals.....................................................................2-1 EEPROM Interface Signals...........................................................................2-2 Firmware Hub Interface Signals....................................................................2-2 PCI Interface Signals ....................................................................................2-2 IDE Interface Signals ....................................................................................2-5 LPC Interface Signals ...................................................................................2-6 Interrupt Signals............................................................................................2-6 USB Interface Signals...................................................................................2-7 Power Management Interface Signals ..........................................................2-7 Processor Interface Signals ..........................................................................2-9 SM Bus Interface Signals............................................................................2-10 System Management Interface Signals ......................................................2-10 Real Time Clock Interface...........................................................................2-11 Other Clocks ...............................................................................................2-11 Miscellaneous Signals ................................................................................2-11 AC’97 Link Signals......................................................................................2-12 General Purpose I/O Signals ......................................................................2-12 Power and Ground Signals .........................................................................2-13 Functional Strap Definitions ........................................................................2-14 Test Mode Selection ...................................................................................2-15 ICH2 Power Planes.......................................................................................3-1 Integrated Pull-Up and Pull-Down Resistors.................................................3-1 IDE Series Termination Resistors.................................................................3-2 Power Plane and States for Output and I/O Signals.....................................3-3 Power Plane for Input Signals.......................................................................3-6 Type 0 Configuration Cycle Device Number Translation ..............................5-5 I/O Control Hub 2 EEPROM Address Map .................................................5-18 LPC Cycle Types Supported.......................................................................5-21 Start Field Bit Definitions.............................................................................5-22 Cycle Type Bit Definitions ...........................................................................5-22 Transfer Size Bit Definition .........................................................................5-22 SYNC Bit Definition.....................................................................................5-23 ICH2 Response to Sync Failures................................................................5-23 DMA Transfer Size......................................................................................5-28 Address Shifting in 16-bit I/O DMA Transfers .............................................5-28 DMA Cycle vs. I/O Address ........................................................................5-32 PCI Data Bus vs. DMA I/O Port Size ..........................................................5-32 DMA I/O Cycle Width vs. BE[3:0]#..............................................................5-33 Counter Operating Modes...........................................................................5-39 Interrupt Controller Core Connections ........................................................5-41 Interrupt Status Registers ...........................................................................5-42 Content of Interrupt Vector Byte .................................................................5-42 APIC Interrupt Mapping ..............................................................................5-49 Arbitration Cycles........................................................................................5-50 APIC Message Formats..............................................................................5-51 EOI Message ..............................................................................................5-51
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5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 5-55 5-56 5-57 5-58 5-59 5-60 5-61 5-62 5-63 5-64 5-65 5-66 5-67 5-68 5-69 5-70 5-71 5-72
Short Message............................................................................................5-52 APIC Bus Status Cycle Definition ...............................................................5-53 Lowest Priority Message (Without Focus Processor) .................................5-54 Remote Read Message ..............................................................................5-55 Interrupt Message Address Format ............................................................5-58 Interrupt Message Data Format..................................................................5-59 Stop Frame Explanation .............................................................................5-61 Data Frame Format ....................................................................................5-62 Configuration Bits Reset By RTCRST# Assertion ......................................5-65 INIT# Going Active......................................................................................5-67 NMI Sources ...............................................................................................5-67 DP Signal Differences (82801BA ICH2 only)..............................................5-68 Frequency Strap Behavior Based on Exit State .........................................5-69 Frequency Strap Bit Mapping .....................................................................5-69 General Power States for Systems using ICH2..........................................5-72 State Transition Rules for ICH2 ..................................................................5-73 System Power Plane ..................................................................................5-74 Causes of SMI# and SCI ............................................................................5-75 Break Events ..............................................................................................5-77 Sleep Types................................................................................................5-81 Causes of Wake Events .............................................................................5-82 GPI Wake Events .......................................................................................5-82 Sleep State Exit Latencies..........................................................................5-83 Transitions Due To Power Failure ..............................................................5-83 Transitions Due to Power Button ................................................................5-87 Transitions Due to RI# signal......................................................................5-88 Write Only Registers with Read Paths in Alternate Access Mode..............5-89 PIC Reserved Bits Return Values...............................................................5-91 Register Write Accesses in Alternate Access Mode...................................5-91 ICH2 Clock Inputs.......................................................................................5-93 Alert on LAN* Message Data......................................................................5-97 IDE Transaction Timings (PCI Clocks) .....................................................5-100 Interrupt/Active Bit Interaction Definition...................................................5-103 UltraATA/33 Control Signal Redefinitions.................................................5-105 Frame List Pointer Bit Description ............................................................5-108 TD Link Pointer .........................................................................................5-109 TD Control and Status ..............................................................................5-110 TD Token ..................................................................................................5-112 TD Buffer Pointer ......................................................................................5-112 Queue Head Block....................................................................................5-113 Queue Head Link Pointer .........................................................................5-113 Queue Element Link Pointer.....................................................................5-113 Command Register, Status Register and TD Status Bit Interaction .........5-115 Queue Advance Criteria ...........................................................................5-117 USB Schedule List Traversal Decision Table ...........................................5-118 PID Format ...............................................................................................5-120 PID Types .................................................................................................5-121 Address Field............................................................................................5-121 Endpoint Field...........................................................................................5-122 Token Format ...........................................................................................5-123 SOF Packet ..............................................................................................5-123
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-73 5-74 5-75 5-76 5-77 5-78 5-79 5-80 5-81 5-82 5-83 5-84 5-85 5-86 5-87 5-88 5-89 5-90 5-91 5-92 6-1 6-2 6-3 6-4 7-1 7-2 7-3 7-4 7-5 7-6 8-1 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 10-1 10-2 11-1 11-2 11-3 12-1
Data Packet Format ..................................................................................5-124 Bits maintained in low power states..........................................................5-127 USB Legacy Keyboard State Transitions..................................................5-129 Quick Protocol...........................................................................................5-131 Send / Receive Byte Protocol ...................................................................5-131 Write Byte/Word Protocol..........................................................................5-132 Read Byte/Word Protocol .........................................................................5-132 Process Call Protocol................................................................................5-133 Block Read/Write Protocol ........................................................................5-135 I2C Block Read .........................................................................................5-136 Slave Write Cycle Format .........................................................................5-139 Slave Write Registers ...............................................................................5-139 Command Types.......................................................................................5-140 Read Cycle Format ...................................................................................5-140 Data Values for Slave Read Registers .....................................................5-141 Featured Supported by ICH2 ....................................................................5-142 AC’97 Signals ...........................................................................................5-144 Input Slot 1 Bit Definitions.........................................................................5-149 Output Tag Slot 0......................................................................................5-150 AC-link state during PCIRST# ..................................................................5-153 PCI Devices and Functions...........................................................................6-2 Fixed I/O Ranges Decoded by ICH2.............................................................6-3 Variable I/O Decode Ranges ........................................................................6-5 Memory Decode Ranges from Processor Perspective .................................6-6 PCI Configuration Map (LAN Controller—B1:D8:F0)....................................7-1 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM ......................................................................................................7-6 Data Register Structure ..............................................................................7-10 ICH2 Integrated LAN Controller CSR Space ..............................................7-10 Self-Test Results Format ............................................................................7-15 Statistical Counters .....................................................................................7-20 PCI Configuration Map (HUB-PCI—D30:F0) ................................................8-1 PCI Configuration Map (LPC I/F—D31:F0)...................................................9-1 DMA Registers............................................................................................9-23 PIC Registers..............................................................................................9-33 APIC Direct Registers .................................................................................9-41 APIC Indirect Registers...............................................................................9-41 RTC I/O Registers.......................................................................................9-47 RTC (Standard) RAM Bank ........................................................................9-47 PCI Configuration Map (PM—D31:F0) .......................................................9-54 APM Register Map......................................................................................9-60 ACPI and Legacy I/O Register Map............................................................9-61 TCO I/O Register Map ................................................................................9-79 Summary of GPIO Implementation .............................................................9-85 Registers to Control GPIO ..........................................................................9-87 PCI Configuration Map (IDE—D31:F1).......................................................10-1 Bus Master IDE I/O Registers...................................................................10-11 PCI Configuration Map (USB—D31:F2/F4) ................................................11-1 USB I/O Registers.......................................................................................11-8 Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation........................................................................11-10 PCI Configuration Registers (SMBUS—D31:F3)........................................12-1
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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12-2 13-1 13-2 13-3 14-1 14-2 14-3 15-1 15-2 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 17-1 17-2 17-3 17-4 17-5 17-6 17-7 A-1 A-2
SMB I/O Registers ......................................................................................12-6 PCI Configuration Map (Audio—D31:F5) ...................................................13-1 ICH2 Audio Mixer Register Configuration...................................................13-7 Native Audio Bus Master Control Registers ...............................................13-9 PCI Configuration Map (Modem—D31:F6).................................................14-1 ICH2 Modem Mixer Register Configuration ................................................14-7 Modem Registers........................................................................................14-8 ICH2 82801BA Alphabetical Ball List by Signal Name ...............................15-4 ICH2-M 82801BAM Alphabetical Ball List by Signal Name ........................15-9 ICH2-M Power Consumption Measurements .............................................16-2 DC Characteristic Input Signal Association ................................................16-2 DC Input Characteristics.............................................................................16-3 DC Characteristic Output Signal Association .............................................16-4 DC Output Characteristics ..........................................................................16-5 Other DC Characteristics ............................................................................16-6 Clock Timings .............................................................................................16-7 PCI Interface Timing ...................................................................................16-9 IDE PIO & Multiword DMA Mode Timing ..................................................16-10 Ultra ATA Timing (Mode 0, Mode 1, Mode 2) ...........................................16-11 Ultra ATA Timing (Mode 3, Mode 4, Mode 5) ...........................................16-11 Universal Serial Bus Timing......................................................................16-12 IOAPIC Bus Timing...................................................................................16-13 SMBus Timing ..........................................................................................16-13 AC’97 Timing ............................................................................................16-13 LPC Timing ...............................................................................................16-14 Miscellaneous Timings .............................................................................16-14 Power Sequencing and Reset Signal Timings..........................................16-14 Power Management Timings ....................................................................16-16 Test Mode Selection ...................................................................................17-1 XOR Test Pattern Example ........................................................................17-2 XOR Chain #1 (RTCRST# Asserted for 4 PCI Clocks while PWROK Active) ..........................................................................................17-4 XOR Chain #2 (RTCRST# Asserted for 5 PCI clocks while PWROK Active) ..........................................................................................17-5 XOR Chain #3 (RTCRST# Asserted for 6 PCI Clocks while PWROK Active) ..........................................................................................17-6 XOR Chain #4 (RTCRST# Asserted for 7 PCI Clocks while PWROK Active) ..........................................................................................17-7 Signals Not in XOR Chain ..........................................................................17-8 ICH2 Fixed I/O Registers............................................................................. A-1 ICH2 Variable I/O Registers ........................................................................ A-6
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Revision History
Revision -001 -002 Initial Release. • Edits throughout for clarity • Added ICH2-M: Initial Release Description Date June 2000 October 2000
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Introduction
Introduction
1
The Intel® 82801BA ICH2 and Intel® 82801BAM ICH2-M are a highly integrated multifunctional I/O Controller Hubs that provide the interface to the PCI Bus and integrate many of the functions needed in today’s PC platforms. The 82801BA is intended for desktop applications and the 82801BAM is intended for mobile applications. This datasheet provides a detailed description of the 82801BA and 82801BAM functions and capabilities including, signals, registers, on-chip functional units, interfaces, pinout, packaging, electrical characteristics, and testability. Unless otherwise specified, all non-shaded areas describe the functionality of both components. In the non-shaded areas, the term "ICH2" refers to both the 82801BA and 82801BAM components. Shading, as is shown here, indicates differences between the two components. In the shaded areas ICH2 refers to the 82801BA and ICH2-M refers to the 82801BAM.
1.1
About this Document
This datasheet is intended for Original Equipment Manufacturers and BIOS vendors creating ICH2-based products. This document assumes a working knowledge of the vocabulary and principles of USB, IDE, AC’97, SMBus, PCI, ACPI, LAN, and LPC. Although some details of these features are described within this document, refer to the individual industry specifications listed in Table 1-1 for the complete details.
Table 1-1. Industry Specifications
Specification LPC AC’97 WfM SMBus PCI USB ACPI Location http://developer.intel.com/design/pcisets/lpc/ http://developer.intel.com/pc-supp/platform/ac97/ http://developer.intel.com/ial/WfM/usesite.htm http://www.sbs-forum.org/specs.htm http://pcisig.com/specs.htm http://www.usb.org http://www.teleport.com/~acpi/
Chapter 1. Introduction Chapter 1 introduces the ICH2 and provides information on document organization. This chapter also describes the key features of the ICH2 and provides a brief description of the major functions. Chapter 2. Signal Description Chapter 2 provides a detailed description of each ICH2 signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals. Chapter 3. Power Planes and Pin States Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. Chapter 4. System Clock Domains Chapter 4 provides a list of each clock domain associated with the ICH2 in an ICH2-based system.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
1-1
Introduction
Chapter 5. Functional Description Chapter 5 provides a detailed description of the functions in the ICH2. All PCI buses, devices and functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function. This datasheet abbreviates buses as B0 and B1, devices as D8, D30 and D31 and functions as F0, F1, F2, F3, F4, F5 and F6. For example Device 31 Function 5 is abbreviated as D31:F5, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the ICH2’s external PCI bus is typically Bus 1; however, it may be assigned a different number depending on system configuration. Chapter 6. Register, Memory and I/O Address Maps Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory ranges decoded by the ICH2. Chapter 7. LAN Controller Registers Chapter 7 provides a detailed description of all registers that reside in the ICH2’s integrated LAN Controller. The integrated LAN Controller resides on the ICH2’s external PCI bus (typically Bus 1) at Device 8, Function 0 (B1:D8:F0). Chapter 8. Hub Interface to PCI Bridge Registers Chapter 8 provides a detailed description of all registers that reside in the Hub Interface to PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0). Chapter 9. LPC Bridge Registers Chapter 9 provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the ICH2 including DMA, Timers, Interrupts, CPU Interface, GPIO, Power Management, System Management and RTC. Chapter 10. IDE Controller Registers Chapter 10 provides a detailed description of all registers that reside in the IDE controller. This controller resides at Device 31, Function 1 (D31:F1). Chapter 11. USB Controller Registers Chapter 11 provides a detailed description of all registers that reside in the two USB controllers. These controllers reside at Device 31, Functions 2 and 4 (D31:F2/F4). Chapter 12. SMBus Controller Registers Chapter 12 provides a detailed description of all registers that reside in the SMBus controller. This controller resides at Device 31, Function 3 (D31:F3). Chapter 13. AC’97 Audio Controller Registers Chapter 13 provides a detailed description of all registers that reside in the audio controller. This controller resides at Device 31, Function 5 (D31:F5). Note that this section of the datasheet does not include the native audio mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. Chapter 14. AC’97 Modem Controller Registers Chapter 14 provides a detailed description of all registers that reside in the modem controller. This controller resides at Device 31, Function 6 (D31:F6). Note that this section of the datasheet does not include the modem mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. Chapter 15. Pinout and Package Information Chapter 15 provides the ball assignment for the 360 EBGA package. The chapter also provides the physical dimensions and characteristics of the 360 EBGA package. Chapter 16. Electrical Characteristics Chapter 16 provides the AC and DC characteristics including timing diagrams. Chapter 17. Testability Chapter 17 provides details about the implementation of test modes on the ICH2. Index There are indexes listing registers and register bits.
1-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Introduction
1.2
Overview
The ICH2 provides extensive I/O support. Functions and capabilities include:
• • • • • • • • • • • •
PCI Rev 2.2 compliant with support for 33 MHz PCI operations. PCI slots ( supports up to 6 Req/Gnt pairs) ACPI Power Management Logic Support Enhanced DMA Controller, Interrupt Controller, and Timer Functions Integrated IDE controller supports Ultra ATA100/66/33) USB host interface with support for 4 USB ports; 2 host controllers Integrated LAN Controller System Management Bus (SMBus) with additional support for I2C devices AC’97 2.1 Compliant Link for Audio and Telephony codecs (up to 6 channels) Low Pin Count (LPC) interface Firmware Hub (FWH) interface support Alert On LAN* (AOL) and Alert On LAN 2 (AOL2)*
The ICH2 incorporates a variety of PCI functions that are divided into two logical devices (30 and 31) on PCI Bus 0 and one device on Bus 1. Device 30 is the Hub Interface-To-PCI bridge. Device 31 contains all the other PCI functions, except the LAN Controller as shown in Table 1-2. The LAN controller is located on Bus 1. Table 1-2. PCI Devices and Functions
Bus:Device:Function Bus 0:Device 30:Function 0 Function Description Hub Interface to PCI Bridge PCI to LPC Bridge (includes: DMA, Timers, compatible interrupt controller, APIC, RTC, processor interface control, power management control, System Management control, and GPIO control) IDE Controller USB Controller #1 SMBus Controller USB Controller #2 AC’97 Audio Controller AC’97 Modem Controller LAN Controller
Bus 0:Device 31:Function 0
Bus 0:Device 31:Function 1 Bus 0:Device 31:Function 2 Bus 0:Device 31:Function 3 Bus 0:Device 31:Function 4 Bus 0:Device 31:Function 5 Bus 0:Device 31:Function 6 Bus 1:Device 8:Function 0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
1-3
Introduction
The following sub-sections provide an overview of the ICH2 capabilities.
Hub Architecture
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become significant. With the addition of AC’97 and Ultra ATA/100, coupled with the existing USB, I/O requirements could impact PCI bus performance. The chipset’s hub interface architecture ensures that the I/O subsystem; both PCI and the integrated I/O features (IDE, AC’97, USB, etc.), will receive adequate bandwidth. By placing the I/O bridge on the hub interface (instead of PCI), the hub architecture ensures that both the I/O functions integrated into the ICH2 and the PCI peripherals obtain the bandwidth necessary for peak performance.
PCI Interface
The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals are 5V tolerant, except PME#. The ICH2 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH2 requests.
IDE Interface (Bus Master capability and synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and CD ROMs. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 14 Mbytes/sec and Bus Master IDE transfers up 100 Mbytes/sec. It does not consume any ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers. The ICH2’s IDE system contains two independent IDE signal channels. They can be electrically isolated independently. They can be configured to the standard primary and secondary channels (four devices). There are integrated series resistors on the data and control lines (see Section 5.15, “IDE Controller (D31:F1)” on page 5-99 for details).
Low Pin Count (LPC) Interface
The ICH2 implements an LPC Interface as described in the LPC 1.0 specification. The Low Pin Count (LPC) Bridge function of the ICH2 resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, Interrupt Controllers, Timers, Power Management, System Management, GPIO, and RTC. Note that in the current chipset platform, the Super I/O (SIO) component has migrated to the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs.
1-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Introduction
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support fast Type-F transfers. The ICH2 supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA DMA. LPC DMA and PC/PCI DMA use the ICH2’s DMA controller. The PC/PCI protocol allows PCI-based peripherals to initiate DMA cycles by encoding requests and grants via two PC/PCI REQ#/GNT# pairs. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit channels. Channel 4 is reserved as a generic bus master request. The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for these three counters. The ICH2 provides an ISA-Compatible interrupt controller that incorporates the functionality of two 82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the ICH2 supports a serial interrupt scheme. All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the circuit.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible interrupt controller (PIC) described in the previous section, the ICH2 incorporates the Advanced Programmable Interrupt Controller (APIC). While the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in either a uni-processor or multi-processor system.
Enhanced Universal Serial Bus (USB) Controller
The USB controller provides enhanced support for the Universal Host Controller Interface (UHCI). This includes support that allows legacy software to use a USB-based keyboard and mouse. The ICH2 is USB Revision 1.1 compliant. The ICH2 contains two USB Host Controllers. Each Host Controller includes a root hub with two separate USB ports each, for a total of 4 USB ports. See Section 5.16, “USB Controller (Device 31:Functions 2 and 4)” on page 5-108 for details.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
1-5
Introduction
LAN Controller
The ICH2’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed data transfers over the PCI bus. Its bus master capabilities enable the component to process highlevel commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN Controller to transmit data with minimum interframe spacing (IFS). The LAN Controller can operate in either full duplex or half duplex mode. In full duplex mode the LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. See Section 5.2, “LAN Controller (B1:D8:F0)” on page 5-6 for details.
RTC
The ICH2 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a separate 3V lithium battery that provides up to 7 years of protection. The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information. The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance.
GPIO
Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on ICH2 configuration.
Enhanced Power Management
The ICH2’s power management functions include enhanced clock control, local and global monitoring support for 14 individual devices, and various low-power (suspend) states (e.g., Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management circuit permits software-independent entrance to low-power states. The ICH2 contains full support for the Advanced Configuration and Power Interface (ACPI) Specification. For the ICH2-M 82801BAM, the Intel® SpeedStep™ technology feature enables a mobile system to operate in multiple processor performance/thermal states and to transition smoothly between them. The internal processor clock setting and processor supply voltage setting determines these states. The ICH2-M supports one Low Power mode and one High Performance mode. The ICH2-M’s PCI clock can be dynamically controlled independent of any other low-power state (Dynamic PCI Clock control).
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Introduction
System Management Bus (SMBus)
The ICH2 contains an SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented (e.g., the I2C Read that allows the ICH2 to perform block reads of I2C devices). The ICH2’s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The host controller supports seven SMBus interface command protocols for communicating with SMBus slave devices (see System Management Bus Specifications, Rev 1.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, and Block Read/Write.
Manageability
The ICH2 integrates several functions designed to manage the system and lower the total cost of ownership (TC0) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.
• TCO Timer. The ICH2’s integrated programmable TC0 Timer is used to detect system locks.
The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock.
• Processor Present Indicator. The ICH2 looks for the processor to fetch the first instruction
after reset. If the processor does not fetch the first instruction, the ICH2 will reboot the system at the safe-mode frequency multiplier.
• ECC Error Reporting. When detecting an ECC error, the host controller has the ability to
send one of several messages to the ICH2. The host controller can instruct the ICH2 to generate either an SMI#, NMI, SERR#, or TCO interrupt.
• Function Disable. The ICH2 provides the ability to disable the following functions: AC’97
Modem, AC’97 Audio, IDE, USB, or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disable functions.
• Intruder Detect. The ICH2 provides an input signal (INTRUDER#) that can be attached to a
switch that is activated by the system case being opened. The ICH2 can be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal.
• SMBus. The ICH2 integrates an SMBus controller that provides an interface to manage
peripherals (e.g., serial presence detection (SPD) or RIMMs and thermal sensors).
• Alert-On-LAN*. The ICH2 supports Alert-On-LAN* and Alert-On-LAN* 2. In response to a
TCO event (intruder detect, thermal event, processor not booting) the ICH2 sends a message over the SMBus. A LAN controller can decode this SMBus message and send a message over the network to alert the network manager.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
1-7
Introduction
AC’97 2.1 Controller
The Audio Codec ’97 (AC’97) specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or both an AC and an MC. The AC’97 specification defines the interface between the system logic and the audio or modem codec, known as the AC’97 Digital Link. The ICH2’s AC’97 (with the appropriate codecs) not only replaces ISA audio and modem functionality, but also improves overall platform integration by incorporating the AC’97 digital link. The use of the ICH2-integrated AC’97 digital link reduces cost and eases migration from ISA. By using an audio codec, the AC’97 digital link allows for cost-effective, high-quality, integrated audio on Intel’s chipset-based platform. In addition, an AC’97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC’97. The ICH2-integrated digital link allows several external codecs to be connected to the ICH2. The system designer can provide audio with an audio codec, a modem with a modem codec, or an integrated audio/modem codec. The digital link is expanded to support two audio codecs or a combination of an audio and modem codec. The modem implementations for different countries must be taken into consideration, because telephone systems may vary. By using a split design, the audio codec can be on-board and the modem codec can be placed on a riser. Intel is developing an AC’97 digital link connector. With a single integrated codec, or AMC, both audio and modem can be routed to a connector near the rear panel, where the external ports can be located. The digital link in the ICH2 is compliant with revision 2.1 of the AC’97, so it supports two codecs with independent PCI functions for audio and modem. Microphone input and left and right audio channels are supported for a high quality, two-speaker audio solution. Wake on Ring from Suspend also is supported with the appropriate modem codec. The ICH2 expands the audio capability with support for up to six channels of PCM audio output (full AC3 decode). Six-channel audio consists of Front Left, Front Right, Back Left, Back Right, Center, and Woofer, for a complete surround-sound effect. ICH2 has expanded support for two audio codecs on the AC’97 digital link.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Signal Description
Signal Description
2
This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I O OD I/O Input Pin Output Pin Open Drain Output Pin. Bi-directional Input / Output Pin.
2.1
Hub Interface to Host Controller
Table 2-1. Hub Interface Signals
Name HL[11:0] HL_STB HL_STB# HLCOMP Type I/O I/O I/O I/O Hub Interface Signals Hub Interface Strobe: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface Strobe Complement: Second of the two differential strobe signals. Hub Interface Compensation: Used for hub interface buffer compensation. Description
2.2
Link to LAN Connect
Table 2-2. LAN Connect Interface Signals
Name LAN_CLK Type I Description LAN Interface Clock: This signal is driven by the LAN Connect component. The frequency range is 0.8 MHz to 50 MHz. Received Data: The LAN Connect component uses these signals to transfer data and control information to the integrated LAN Controller. These signals have integrated weak pull-up resistors. Transmit Data: The integrated LAN Controller uses these signals to transfer data and control information to the LAN Connect component. LAN Reset/Sync: The LAN Connect component’s Reset and Sync signals are multiplexed onto this pin.
LAN_RXD[2:0]
I
LAN_TXD[2:0] LAN_RSTSYNC
O O
82801BA ICH2 and 82801BAM ICH2-M Datasheet
2-1
Signal Description
2.3
EEPROM Interface
Table 2-3. EEPROM Interface Signals
Name EE_SHCLK EE_DIN EE_DOUT EE_CS Type O I O O Description EEPROM Shift Clock: EE_SHCLK is the serial shift clock output to the EEPROM. EEPROM Data In: EE_DIN transfers data from the EEPROM to the ICH2. This signal has an integrated pull-up resistor. EEPROM Data Out: EE_DOUT transfers data from the ICH2 to the EEPROM. EEPROM Chip Select: EE_CS is a chip-select signal to the EEPROM.
2.4
Firmware Hub Interface
Table 2-4. Firmware Hub Interface Signals
Name FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# Type I/O I/O Description Firmware Hub Signals: These signals are muxed with LPC address signals. Firmware Hub Signals: This signal is muxed with LPC LFRAME# signal.
2.5
PCI Interface
Table 2-5. PCI Interface Signals
Name Type Description PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The ICH2 drives all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the Byte Enables. C/BE[3:0]# Command Type 0000 0001 0010 0011 0110 0111 1010 1011 1100 1110 1111 Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write and Invalidate
AD[31:0]
I/O
C/BE[3:0]#
I/O
All command encodings not shown are reserved. The ICH2 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Signal Description
Table 2-5. PCI Interface Signals (Continued)
Name Type Description Device Select: The ICH2 asserts DEVSEL# to claim a PCI transaction. As an output, the ICH2 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH2 address or an address destined for the hub interface (main memory or AGP). As an input, DEVSEL# indicates the response to an ICH2initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the ICH2 until driven by a target device. Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the ICH2 when the ICH2 is the target, and FRAME# is an output from the ICH2 when the ICH2 is the Initiator. FRAME# remains tri-stated by the ICH2 until driven by an Initiator. Initiator Ready: IRDY# indicates the ICH2's ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the ICH2 has valid data present on AD[31:0]. During a read, it indicates the ICH2 is prepared to latch data. IRDY# is an input to the ICH2 when the ICH2 is the Target and an output from the ICH2 when the ICH2 is an Initiator. IRDY# remains tri-stated by the ICH2 until driven by an Initiator. Target Ready: TRDY# indicates the ICH2's ability as a Target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the ICH2, as a Target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the ICH2, as a Target is prepared to latch data. TRDY# is an input to the ICH2 when the ICH2 is the Initiator and an output from the ICH2 when the ICH2 is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated by the ICH2 until driven by a target. Stop: STOP# indicates that the ICH2, as a Target, is requesting the Initiator to stop the current transaction. STOP# causes the ICH2, as an Initiatior, to stop the current transaction. STOP# is an output when the ICH2 is a target and an input when the ICH2 is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until driven by the ICH2. Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the ICH2 counts the number of 1s within the 36 bits plus PAR and the sum is always even. The ICH2 always calculates PAR on 36 bits, regardless of the valid byte enables. The ICH2 generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase. The ICH2 drives and tri-states PAR identically to the AD[31:0] lines except that the ICH2 delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all ICH2 initiated transactions. PAR is an output during the data phase (delayed one clock) when the ICH2 is the Initiator of a PCI write transaction, and when it is the target of a read transaction. ICH2 checks parity when it is the target of a PCI write transaction. If a parity error is detected, the ICH2 sets the appropriate internal status bits, and has the option to generate an NMI# or SMI#. Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The ICH2 drives PERR# when it detects a parity error. The ICH can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). PCI Requests: The ICH2 supports up to 6 masters on the PCI bus. REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1]. Note: REQ[0]# is programmable to have improved arbitration latency for supporting PCI-based 1394 controllers.
DEVSEL#
I/O
FRAME#
I/O
IRDY#
I/O
TRDY#
I/O
STOP#
I/O
PAR
I/O
PERR#
I/O
REQ[0:4]# REQ[5]# / REQ[B]# / GPIO[1] I
82801BA ICH2 and 82801BAM ICH2-M Datasheet
2-3
Signal Description
Table 2-5. PCI Interface Signals (Continued)
Name GNT[0:4]# GNT[5]# / GNT[B]# / GPIO[17]# O Type Description PCI Grants: The ICH2 supports up to 6 masters on the PCI bus. GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can instead be used as a GPIO. Pull-up resistors are not required on these signals. If pullups are used, they should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an internal pullup. PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. . Note:For 82801BAM ICH2-M, this clock does not stop based on the STP_PCI# signal. The PCI Clock only stops based on SLP_S1# or SLP_S3#. PCI Reset: ICH2 asserts PCIRST# to reset devices that reside on the PCI bus. The ICH2 asserts PCIRST# during power-up and when S/W initiates a hard reset sequence through the RC (CF9h) register. The ICH2 drives PCIRST# inactive a minimum of 1 ms after PWROK is driven active. The ICH2 drives PCIRST# active a minimum of 1 ms when initiated through the RC register. PCI Lock: PLOCK# indicates an exclusive bus operation and may require multiple transactions to complete. ICH2 asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. 82801BA ICH2: PLOCK# is ignored when PCI masters are granted the bus. 82801BAM ICH2-M: Devices on the PCI bus (other than the ICH2-M) are not permitted to assert the PLOCK# signal. SERR# I System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the ICH2 has the ability to generate an NMI, SMI#, or interrupt. PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1–S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the ICH2 may drive PME# active due to an internal wake event. The ICH2 will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. PCI Clock Run: For the ICH2-M, CLKRUN# is used to support PCI Clock Run protocol. This signal connects to PCI devices that need to request clock re-start or prevention of clock stopping. PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by devices such as PCI-based Super I/O or audio codecs that need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI requests, these signals can be used as General Purpose Inputs. Instead, REQ[B]# can be used as the 6th PCI bus request. PC/PCI DMA Acknowledges [A:B]: This grant serializes an ISA-like DACK# for the purpose of running DMA/ISA master cycles over the PCI bus. This is used by devices such as PCI-based Super/IO or audio codecs which need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the 6th PCI bus master grant output. These signal have internal pull-up resistors.
PCICLK
I
PCIRST#
O
PLOCK#
I/O
PME#
I
CLKRUN# (ICH2-M only) REQ[A]# / GPIO[0] REQ[B]# / REQ[5]# / GPIO[1] GNT[A]# / GPIO[16] GNT[B]# / GNT[5]# / GPIO[17]
I/O
I
O
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Signal Description
2.6
IDE Interface
Table 2-6. IDE Interface Signals
Name PDCS1#, SDCS1# PDCS3#, SDCS3# PDA[2:0], SDA[2:0] PDD[15:0], SDD[15:0] Type O Description Primary and Secondary IDE Device Chip Selects for 100 Range: These signals are for the ATA command register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Chip Select for 300 Range: These signals are for the ATA control register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Address: These output signals are connected to the corresponding signals on the primary or secondary IDE connectors. They are used to indicate which byte in either the ATA command block or control block is being addressed. Primary and Secondary IDE Device Data: These signals directly drive the corresponding signals on the primary or secondary IDE connector. There is a weak internal pull-down resistor on PDD[7] and SDD[7]. Primary and Secondary IDE Device DMA Request: These input signals are directly driven from the DRQ signals on the primary or secondary IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function. They are not associated with any AT-compatible DMA channel. There is a weak internal pull-down resistor on these signals. Primary and Secondary IDE Device DMA Acknowledge: These signals directly drive the DAK# signals on the primary and secondary IDE connectors. Each signal is asserted by the ICH2 to indicate to the IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel. Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data on the PDD or SDD lines. Data is latched by the ICH2 on the deassertion edge of PDIOR# or SDIOR#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). O SDIOR# Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, ICH2 drives valid data on rising and falling edges of PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, ICH2 deasserts PRDMARDY# or SRDMARDY# to pause burst data transfers. Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the PDD or SDD lines. Data is latched by the IDE device on the deassertion edge of PDIOW# or SDIOW#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). Primary and Secondary Disk Stop (Ultra DMA): ICH2 asserts this signal to terminate a burst. Primary and Secondary I/O Channel Ready (PIO): This signal keeps the strobe active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer than the minimum width. It adds wait states to PIO transfers. I SIORDY Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, ICH2 latches data on rising and falling edges of this signal from the disk. Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is deasserted by the disk to pause burst data transfers.
O
O
I/O
PDDREQ, SDDREQ
I
PDDACK#, SDDACK#
O
PDIOR#
PDIOW# O SDIOW#
PIORDY
82801BA ICH2 and 82801BAM ICH2-M Datasheet
2-5
Signal Description
2.7
LPC Interface
Table 2-7. LPC Interface Signals
Name LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[1:0]# Type I/O O Description LPC Multiplexed Command, Address, Data: Internal pull-ups are provided. LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LPC Serial DMA/Master Request Inputs: These signals are used to request DMA or bus master access. Typically, they are connected to external Super I/O device. An internal pull-up resistor is provided on these signals.
I
2.8
Interrupt Interface
Table 2-8. Interrupt Signals
Name SERIRQ Type I/O Description Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the ISA interrupts. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. I/OD In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the ISA interrupts. If not needed for interrupts, PIRQ[G:F] can be used as GPIO. Interrupt Request 14:15: These interrupt inputs are connected to the IDE drives. IRQ14 is used by the drives connected to the primary controller and IRQ15 is used by the drives connected to the secondary controller. APIC Clock: The APIC clock runs at 33.333 MHz. APIC Data: These bi-directional open drain signals are used to send and receive data over the APIC bus. As inputs, the data is valid on the rising edge of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK.
PIRQ[D:A]#
I/OD
PIRQ[H]#, PIRQ[G:F]# / GPIO[4:3], PIRQ[E]#
IRQ[14:15] APICCLK APICD[1:0]
I I I/OD
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Signal Description
2.9
USB Interface
Table 2-9. USB Interface Signals
Name USBP0P, USBP0N, USBP1P, USBP1N USBP2P, USBP2N, USBP3P, USBP3N OC[3:0]# Type Description Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1 (USB Controller 1).
I/O
I/O
Universal Serial Bus Port 3:2 Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 2 and 3 (USB Controller 2). Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred.
I
2.10
Power Management Interface
Table 2-10. Power Management Interface Signals
Name THRM# Type I Description Thermal Alarm: THRM# is an active low signal generated by external hardware to start the hardware clock throttling mode. This signal can also generate an SMI# or an SCI. S1 Sleep Control: Clock synthesizer or power plane control. This signal connects to clock synthesizer’s PWRDWN# signal. An optional use is to shut off power to non-critical systems when in the S1 (Powered On Suspend), S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. S3 Sleep Control: Power plane control. This signal is used to shut off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk) or S5 (Soft Off) states. S5 Sleep Control: Power plane control. This signal is used to shut power off to all non-critical systems when in the S4 (Suspend To Disk) or S5 (Soft Off) states. Power OK: When asserted, PWROK is an indication to the ICH2 that core power and PCICLK have been stable for at least 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the ICH2 asserts PCIRST#. Resume Well Power OK: When asserted, this signal is an indication to the ICH2 that the resume well power (VccSus3_3, VccSus1_8) has been stable for at least 10 ms. LAN Power OK: When asserted, this signal is an indication to the ICH2-M that the LAN Controller power (VccLAN3_3, VccLAN1_8) has been stable for at least 10 ms. Power Button: The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state with only the PWRBTN# available as a wake event. Override will occur even if the system is in the S1-S4 states. This signal has an internal pull-up resistor. Ring Indicate: From the modem interface. This signal can be enabled as a wake event; this is preserved across power failures. Resume Well Reset: RSMRST# is used for resetting the resume power plane logic.
SLP_S1# (ICH2-M only)
O
SLP_S3#
O
SLP_S5#
O
PWROK
I
RSM_PWROK (ICH2 0nly) LAN_PWROK (ICH2-M only)
I
I
PWRBTN#
I
RI# RSMRST#
I I
82801BA ICH2 and 82801BAM ICH2-M Datasheet
2-7
Signal Description
Table 2-10. Power Management Interface Signals
Name Type Description Suspend Status: This signal is asserted by the ICH2 to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC interface. C3_STAT#: This ICH2-M signal is typically configured as C3_STAT#. It is used for indicating to an AGP device that a C3 state transition is beginning or ending. If C3_STAT# functionality is not required, this signal can be used as a GPO. Suspend Clock: This signal is an output of the RTC generator circuit and is used by other chips for the refresh clock.
SUS_STAT# / LPCPD#
O
C3_STAT# / GPIO[21] (ICH2-M only) SUSCLK VRMPWRGD (ICH2) VRMPWRGD/ VGATE (ICH2-M) VGATE / VRMPWRGD (ICH2-M only)
O
O
I
VRM Power Good (ICH2 and ICH2-M): VRMPWRGD should be connected to be the processor’s VRM Power Good. VRM Power Good Gate (ICH2-M): VGATE is used for Intel® SpeedStepTM technology support. It is an output from the processor’s voltage regulator to indicate that the voltage is stable. This signal can go inactive during a Intel® SpeedStepTM transition. In non-Intel® SpeedStepTM technology systems this signal should be connected to the processor VRM Power Good. AGP Bus Busy: This signal supports the C3 state. It provides an indication that the AGP device is busy. When this signal is asserted, the BM_STS bit will be set. If this functionality is not needed, this signal may be configured as a GPI. Stop PCI Clock: This signal is an output to the external clock generator to turn off the PCI clock. It is used to support PCI CLKRUN# protocol. If this functionality is not needed, this signal can be configured as a GPO. Stop CPU Clock: Output to the external clock generator to turn off the processor clock. It is used to support the C3 state. If this functionality is not needed, this signal can be configured as a GPO. Battery Low: Input from battery to indicate that there is insufficient power to boot the system. Assertion prevents wake from S1–S5 state. This signal can also be enabled to cause an SMI# when asserted. In desktop configurations this signal should be pulled high to VccSUS. CPU Performance: This signal is used for Intel® SpeedStepTM technology support. It selects which power state to put the processo in. If this functionality is not needed, this signal can be configured as a GPO. This is an open-drain output signal and requires an external pull-up to the processor I/O voltage. SpeedStep Mux Select: This signal is used for Intel® SpeedStepTM technology support. It selects the voltage level for the processor. If this functionality is not needed, this signal can be configured as a GPO.
I
AGPBUSY# (ICH2-M only) STP_PCI# (ICH2-M only) STP_CPU# (ICH2-M only)
I
O
O
BATLOW# (ICH2-M only)
I
CPUPERF# (ICH2-M only)
OD
SSMUXSEL (ICH2-M only)
O
2-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Signal Description
2.11
Processor Interface
Table 2-11. Processor Interface Signals
Name Type Description Mask A20: A20M# goes active based on setting the appropriate bit in the Port 92h register, or based on the A20GATE signal. Speed Strap: During the reset sequence, ICH2 drives A20M# high if the corresponding bit is set in the FREQ_STRP register. Processor Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. The ICH2 can optionally assert the CPUSLP# signal when going to the S1 state. Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the ICH2 coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is asserted, the ICH2 generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the ICH2 coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register is written, the IGNNE# signal is not asserted. Speed Strap: During the reset sequence, ICH2 drives IGNNE# high if the corresponding bit is set in the FREQ_STRP register. INIT# O Initialization: INIT# is asserted by the ICH2 for 16 PCI clocks to reset the processor. ICH2 can be configured to support processor BIST. In that case, INIT# will be active when PCIRST# is active. Processor Interrupt: INTR is asserted by the ICH2 to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. Speed Strap: During the reset sequence, ICH2 drives INTR high if the corresponding bit is set in the FREQ_STRP register. Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the processor. The ICH2 can generate an NMI when either SERR# or IOCHK# is asserted. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control Register. Speed Strap: During the reset sequence, ICH2 drives NMI high if the corresponding bit is set in the FREQ_STRP register. SMI# O System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the ICH2 in response to one of many enabled hardware or software events. Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH2 in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock.
A20M#
O
CPUSLP#
O
FERR#
I
IGNNE#
O
INTR
O
NMI
O
STPCLK#
O
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2-9
Signal Description
Table 2-11. Processor Interface Signals (Continued)
Name Type Description Keyboard Controller Reset Processor: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the ICH2’s other sources of INIT#. When the ICH2 detects the assertion of this signal, INIT# is generated for 16 PCI clocks.. Note 82801BA ICH2: The 82801BA ignores RCIN# assertion during transitions to the S3, S4 and S5 states. 82801BAM ICH2-M: The 82801BAM ignores RCIN# assertion during transitions to the S1, S3, S4 and S5 states. A20GATE I A20 Gate: This signal is from the keyboard controller. It acts as an alternative method to force the A20M# signal active. A20GATE saves the external OR gate needed with various other PCIsets. Processor Power Good (82801BA ICH2): This signal should be connected to the processor’s PWRGOOD input. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH2’s PWROK and VRMPWRGD signals. CPUPWRGD OD CPU Power Good (82801BAM ICH2-M): This signal should be connected to the processor’s PWRGOOD input. For Intel® SpeedStep™ technology support, this signal is kept high during a Intel® SpeedStep™ technology state transition to prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH2-M’s PWROK and VGATE / VRMPWRGD signals.
RCIN#
I
2.12
SMBus Interface
Table 2-12. SM Bus Interface Signals
Name SMBDATA SMBCLK SMBALERT#/ GPIO[11] Type I/OD I/OD I Description SMBus Data: External pull-up is required. SMBus Clock: External pull-up is required. SMBus Alert: This signal is used to wake the system or generate an SMI#. If not used for SMBALERT#, it can be used as a GPI.
2.13
System Management Interface
Table 2-13. System Management Interface Signals
Name INTRUDER# Type I Description Intruder Detect: This signal can be set to disable system if box detected open. This signal’s status is readable, so it can be used like a GPI if the Intruder Detection is not needed. System Management Link: These signals are an SMBus link to an optional external system management ASIC or LAN controller. External pull-ups are required. Note that SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1] corresponds to an SMBus Data signal.
SMLINK[1:0]
I/OD
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Signal Description
2.14
Real Time Clock Interface
Table 2-14. Real Time Clock Interface
Name RTCX1 RTCX2 Type Special Special Description Crystal Input 1: This signal is connected to the 32.768 KHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 KHz crystal. If no external crystal is used, then RTCX2 should be left floating.
2.15
Other Clocks
Table 2-15. Other Clocks
Name Type Description Oscillator Clock: CLK14 is used for 8254 timers and runs at 14.31818 MHz. CLK14 I 82801BA ICH2: This clock is permitted to stop during S3 (or lower) states. 82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states. 48 MHz Clock: CLK48 is used to for the USB controller and runs at 48 MHz. CLK48 I 82801BA ICH2: This clock is permitted to stop during S3 (or lower) states. 82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states. 66 MHz Clock: CLK66 is used to for the hub interface and runs at 66 MHz. CLK66 I 82801BA ICH2: This clock is permitted to stop during S3 (or lower) states. 82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states.
2.16
Miscellaneous Signals
Table 2-16. Miscellaneous Signals
Name Type Description Speaker: The SPKR signal is the output of counter 2 and is internally "ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its output state is 1. Note: SPKR is sampled at the rising edge of PWROK as a functional strap. See Section 2.20.1for more details. RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). This signal is also used to enter the test modes documented in Section 2.20.2. Note: Clearing CMOS in an ICH2-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Test Point (82801BA ICH2): This signal must have an external pull-up to VccSus3_3. Functional Strap: This signal is reserved for future use. There is an internal pullup resistor on this signal.
SPKR
O
RTCRST#
I
TP0 (ICH2 0nly) FS0
I I
82801BA ICH2 and 82801BAM ICH2-M Datasheet
2-11
Signal Description
2.17
AC’97 Link
Name AC_RST# AC_SYNC AC_BIT_CLK Type O O I Description AC97 Reset: Master H/W reset to external Codec(s) AC97 Sync: 48 KHz fixed rate sample sync to the Codec(s) AC97 Bit Clock: 12.288 MHz serial data clock generated by the external Codec(s). See Note. AC97 Serial Data Out: Serial TDM data output to the Codec(s) AC_SDOUT AC_SDIN[1:0] O I Note: AC_SDOUT is sampled at the rising edge of PWROK as a functional strap. See Section 2.20.1 for more details. AC97 Serial Data In 0: Serial TDM data inputs from the Codecs. See Note.
Table 2-17. AC’97 Link Signals
NOTE: If the ACLINK Shutoff bit in the AC’97 Global Control Register (See Section 13.2.8) is set to 1, internal pull-down resistors will be enabled on AC_BIT_CLK and AC_SDATA_IN[1:0]. If ACLINK Shutoff is cleared to 0, these pull-down resistors are disabled. If there is no codec down on the system board, the two signals AC_SDIN[1:0] should be pulled down externally with a resistor to ground.
2.18
General Purpose I/O
Name GPIO[31:29] GPIO[28:27] GPIO[26] GPIO[25] GPIO[24] (ICH2 only) GPIO[23] (ICH2 only) GPIO[22] (ICH2 only) GPIO[21] GPIO[20:18] (ICH2 only) GPIO[17:16] GPIO[15:14] GPIO[13:12] GPIO[11] GPIO[10:9] GPIO[8] GPIO[7] GPIO[6] (ICH2 only) Type O I/O I/O I/O I/O O OD O O Not implemented. Can be input or output. Resume power well. Unmuxed. Not implemented. Can be input or output. Resume power well. Not Muxed. Can be input or output. Resume power well. Fixed as Output only. Main power well. Fixed as Output only. Main power well. Open-drain output. Fixed as Output only. Main power well. Fixed as Output only. Main power well. Fixed as Output only. Main Power Well. Can instead be used for PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#. Integrated pull-up resistor. Not implemented. Fixed as Input only. Resume Power Well. Not muxed. Fixed as Input only. Resume Power Well. Can instead be used for SMBALERT#. Not implemented. Fixed as Input only. Resume Power Well. Not muxed. Fixed as Input only. Main power well. Not muxed. Fixed as Input only. Main power well. Description
Table 2-18. General Purpose I/O Signals
O I I I I I I I
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Signal Description
Table 2-18. General Purpose I/O Signals (Continued)
Name GPIO[5] GPIO[4:3] GPIO[2] GPIO[1:0] I I Type Not implemented. Fixed as Input only. Main power well. Can be used instead as PIRQ[G:F]#. Not implemented. Fixed as Input only. Main Power Well. Can instead be used for PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#. Description
2.19
Power and Ground
Name Vcc3_3 Vcc1_8 V5REF HUBREF Description 3.3V supply for Core well I/O buffers. This power may be shut off in S3, S5 or G3 states. 1.8V supply for Core well logic. This power may be shut off in S3, S5 or G3 states. Reference for 5V tolerance on Core well inputs. This power may be shut off in S3, S5 or G3 states. 0.9V reference for the hub interface. This power may be shut off in S3, S5 or G3 states. 3.3V supply for Resume well I/O buffers. This power is not expected to be shut off unless power is removed. VccSus3_3 • 82801BA ICH2: The system is unplugged. • 82801BAM ICH2-M: The main battery is removed or completely drained and AC power is not available. 1.8V supply for Resume well logic. This power is not expected to be shut off unless power is removed. VccSus1_8 • 82801BA ICH2: The system is unplugged. • 82801BAM ICH2-M: The main battery is removed or completely drained and AC power is not available. Reference for 5V tolerance on Resume well inputs. This power is not expected to be shut off unless power is removed. V5REF_SUS • 82801BA ICH2: The system is unplugged. Note that V5REF_SUS only affects 5V tolerance for the USB OC[3:0]# pins and can be connected to VccSUS3_3 if 5V tolerance on these signals is not required. • 82801BAM ICH2-M: The main battery is removed or completely drained and AC power is not available. 3.3V (can drop to 2.0V min. in G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained. VccRTC Note: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an ICH2-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. 3.3V supply for LAN Connect interface buffers. This is a separate power plane that may or may not be energized in S3–S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1. 1.8V supply for LAN controller logic. This is a separate power plane that may or may not be energized in S3–S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1. RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is mirrored throughout the oscillator and buffer circuitry. See Section 2.20.3. Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface outputs. Grounds.
Table 2-19. Power and Ground Signals
VccLAN3_3 (ICH2-M only) VccLAN1_8 (ICH2-M only) VBIAS V_CPU_IO Vss
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2-13
Signal Description
2.20
2.20.1
Pin Straps
Functional Straps
The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least 4 PCI clocks prior to the time it is sampled.
Table 2-20. Functional Strap Definitions
Signal Usage When Sampled Rising Edge of PWROK Comment The signal has a weak internal pull-down. If the signal is sampled high, the ICH2 sets the processor speed strap pins for safe mode. Refer to processor specification for speed strapping definition. The status of this strap is readable via the SAFE_MODE bit (bit 2, D31: F0, Offset D4h). System designers should include a placeholder for a pull-down resistor on EE_DOUT but do not populate the resistor. System designers should include a placeholder for a pull-down resistor on FS[0] but do not populate the resistor. The signal has a weak internal pull-up. If the signal is sampled low, the system is strapped to the “Top-Swap” mode (ICH2 will invert A16 for all cycles targeting FWH BIOS space). The status of this strap is readable via the Top-Swap bit (bit 13, D31: F0, Offset D4h). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT[A]# being pulled down. If this signal is sampled high (via an external pull-up to VCC1_8), the normal hub interface buffer mode will be selected. If this signal is sampled low (via an external pull-down), the enhanced hub interface buffer mode will be selected. See the specific platform design guide for resistor values and routing guidelines for each hub interface mode. The signal has a weak internal pull-up. If the signal is sampled low, the system is strapped to the “No Reboot” mode (ICH2 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h).
AC_SDOUT
SAFE MODE
EE_DOUT FS[0]
Reserved Reserved
GNT[A]#
Top-Swap Override
Rising Edge of PWROK
HLCOMP
Enhanced Hub Interface Mode
During PCIRST# assertion
SPKR
No Reboot
Rising Edge of PWROK
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Signal Description
2.20.2
2.20.2.1
Test Signals
Test Mode Selection
When PWROK is active (high), driving RTCRST# low for a number of PCI clocks (33 MHz) will activate a particular test mode as specified in Table 2-21.
Note:
RTCRST# may be driven low any time after PCIRST is inactive. Refer to Chapter 17, “Testability” for a detailed description of the ICH2 test modes.
Table 2-21. Test Mode Selection
Number of PCI Clocks RTCRST# driven low after PWROK active 24 Test Mode No Test Mode Selected XOR Chain 1 XOR Chain 2 XOR Chain 3 XOR Chain 4 All “Z” Reserved. DO NOT ATTEMPT No Test Mode Selected
2.20.2.2
Test Straps (82801BA ICH2 only)
The ICH2’s TP[0] (Test Point) signal must be pulled to VccSus3_3 with an external pull-up resistor.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
2-15
Signal Description
2.20.3
External RTC Circuitry
To reduce RTC well power consumption, the ICH2 implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC and VBIAS. Figure 2-1 shows a schematic diagram of the circuitry required to condition these voltages to ensure correct operation of the ICH2 RTC.
Figure 2-1. Required External RTC Circuit
3.3V VCCSUS 1 kΩ 1 µF RTCX2 Vbatt 1 kΩ 32768 Hz Xtal R1 10 MΩ RTCX1 C1 0.047 uF C3 12.5 pF R2 10 MΩ VBIAS C2 12.5 pF VSSRTC Note: Capacitor C2 and C3 values are crystal-dependent. VCCRTC
2.20.4
V5REF / Vcc3_3 Sequencing Requirements
V5REF and V5REF_Sus are the reference voltages for 5V tolerance on inputs to the ICH2. V5REF and V5REF_Sus must power up before or simultaneous to Vcc3_3 and VccSus3_3 respectively, and must power down after or simultaneous to Vcc3_3 and VccSus3_3 respectively. Refer to Figure 2-2 for an example circuit schematic that may be used to ensure proper V5REF sequencing. Note that separate circuits must be implemented for both the Core and Suspend well supplies.
Figure 2-2. Example V5REF Sequencing Circuit
VCC Supply (3.3V) 1k
Schottky Diode
5V Supply
1 uF
To System
5VREF
To System
2-16
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Power Planes and Pin States
Power Planes and Pin States
3.1 Power Planes
3
Table 3-1. ICH2 Power Planes
Plane Main I/O (3.3V) Main Logic (1.8V) Resume I/O (3.3V Standby) Description Vcc3_3: Powered by the main power supply (or battery for the ICH2-M). When the system is in the S3, S4, S5, or G3 state, this plane is assumed to be shut off. Vcc1_8: Powered by the main power supply (or battery for the ICH2-M). When the system is in the S3, S4, S5, or G3 state, this plane is assumed to be shut off. VccSUS3_3: Powered by the main power supply (or battery for the ICH2-M) in S0–S1 states. Powered by the trickle power supply (or battery for the ICH2-M) when the system is in the S3, S4, S5, state. Assumed to be shut off only when in the G3 state (system is unplugged for the ICH2 or battery removed for the ICH2-M). VccSUS1_8: Powered by the main power supply (or battery for the ICH2-M) in S0–S1 states. Powered by the trickle power supply (or battery for the ICH2-M) when the system is in the S3, S4, S5, state. Assumed to be shut off only when in the G3 state (system is unplugged for the ICH2 or batter removed for the ICH2-M). V_CPU_IO: Powered by the main power supply via processor voltage regulator. When the system is in the S3, S4, S5, or G3 state, this plane is assumed to be shut off. VccLAN3_3: This is a separate power plane that may or may not be energized in S3 S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in the S0 and S1 states. VccLAN1_8: This is a separate power plane that may or may not be energized in S3 S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in the S0 and S1 states. VccRTC: When other power is available (from the main supply for the ICH2 or battery for the ICH2-M), external diode coupling will provide power to reduce the drain on the RTC battery. Assumed to operate from 3.3V down to 2.0V.
Resume Logic (1.8V Standby) Processor Interface (1.3 ~ 2.5V) LAN I/O (3.3V) (ICH2-M only) LAN Logic (1.8V) (ICH2-M only) RTC
3.2
Integrated Pull-Ups and Pull-Downs
Table 3-2. Integrated Pull-Up and Pull-Down Resistors
Signal EE_DIN EE_DOUT GNT[B:A]# / GNT[5]# / GPIO[17:16] LAD[3:0]# / FWH[3:0]# LDRQ[1:0] PME# PWRBTN# SPKR AC_BITCLK Resistor Type pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-down Nominal Value 24 KΩ 24 KΩ 24 KΩ 24 KΩ 24 KΩ 24 KΩ 24 KΩ 24 KΩ 20 KΩ Notes 1 1 1 1 1 1 1 1, 5 2, 6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
3-1
Power Planes and Pin States
Table 3-2. Integrated Pull-Up and Pull-Down Resistors (Continued)
Signal AC_SDIN[0] AC_SDIN[1] AC_SDOUT AC_SYNC LAN_RXD[2:0] PDD[7] / SDD[7] PDDREQ / SDDREQ Resistor Type pull-down pull-down pull-down pull-down pull-up pull-down pull-down Nominal Value 20 KΩ 20 KΩ 20 KΩ 20 KΩ 9 KΩ 5.9 KΩ 5.9 KΩ Notes 2, 6 2, 6 2, 6 2, 6 3 4 4
NOTES: 1. Simulation data shows that these resistor values can range from 18 KΩ to 42 KΩ. 2. Simulation data shows that these resistor values can range from 13 KΩ to 38 KΩ. 3. Simulation data shows that these resistor values can range from 6 KΩ to 14 KΩ. 4. Simulation data shows that these resistor values can range from 4.3 KΩ to 20 KΩ. 5. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. 6. This pull-down is only enabled when the ACLINK Shut Off bit in the AC’97 Global Control Register is set to 1.
3.3
IDE Integrated Series Termination Resistors
Table 3-3 shows the ICH2 IDE signals that have integrated series termination resistors.
Table 3-3. IDE Series Termination Resistors
Signal PDD[15:0], SDD[15:0], PDIOW#, SDIOW#, PDIOR#, PDIOW#, PDREQ, SDREQ, PDDACK#, SDDACK#, PIORDY, SIORDY, PDA[2:0], SDA[2:0], PDCS1#, SDCS1#, PDCS3#, SDCS3#, IRQ14, IRQ15 Integrated Series Termination Resistor Value
approximately 33 Ω (See Note)
NOTE: Simulation data indicates that the integrated series termination resistors are a nominal 33 Ω but can range from 31 Ω to 43 Ω.
3.4
Output and I/O Signals Planes and States
Table 3-4 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: “High-Z” Tri-state. ICH2 not driving the signal high or low. “High” ICH2 is driving the signal to a logic ‘1’ “Low” ICH2 is driving the signal to a logic ‘0’ “Defined” Driven to a level that is defined by the function (will be high or low) “Undefined” ICH2 is driving the signal, but the value is indeterminate. “Running” Clock is toggling or signal is transitioning because function not stopping “Off” The power plane is off, so ICH2 is not driving Note that the signal levels are the same in S4 and S5.
3-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Power Planes and Pin States
Table 3-4.
Signal Name
Power Plane and States for Output and I/O Signals
Power Plane Reset Signal During Reset Immediately after Reset C3 (ICH2-M) S1 S3 S4/S5
PCI Bus AD[31:0] C/BE#[3:0] CLKRUN# (ICH2-M) DEVSEL# FRAME# GNT[0:5]# GNT[A:B]# IRDY#, TRDY# PAR PCIRST# PERR# PLOCK# STOP# Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Resume I/O Main I/O Main I/O Main I/O PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# RSMRST# PCIRST# PCIRST# PCIRST# High-Z High-Z Low High-Z High-Z High High-Z High-Z High-Z Low High-Z High-Z High-Z Undefined Undefined Low High-Z High-Z High High High-Z Undefined High High-Z High-Z High-Z Defined Defined Defined High-Z High-Z High High High-Z Defined High High-Z High-Z High-Z High-Z High-Z High High High-Z Defined High High-Z High-Z High-Z Defined Defined Off Off Off Off Off Off Off Off Off Low Off Off Off Off Off Off Off Off Off Off Off Off Low Off Off Off
LPC Interface LAD[3:0] LFRAME# Main I/O Main I/O PCIRST# PCIRST# High High High High High High Defined High Off Off Off Off
LAN Connect and EEPROM Interface RSM_PWROK (ICH2) LAN_PWROK (ICH2-M) RSM_PWROK (ICH2) LAN_PWROK (ICH2-M) RSM_PWROK (ICH2) LAN_PWROK (ICH2-M) RSM_PWROK (ICH2) LAN_PWROK (ICH2-M) RSM_PWROK (ICH2) LAN_PWROK (ICH2-M)
EE_CS
LAN I/O
Low
Running
Defined
Defined
Note 4
Note 4
EE_DOUT
LAN I/O
High
Running
Defined
Defined
Note 4
Note 4
EE_SHCLK
LAN I/O
Low
Running
Defined
Defined
Note 4
Note 4
LAN_RSTSYNC
LAN I/O
High
Defined
Defined
Defined
Note 4
Note 4
LAN_TXD[2:0]
LAN I/O
Low
Defined
Defined
Defined
Note 4
Note 4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
3-3
Power Planes and Pin States
Table 3-4.
Signal Name
Power Plane and States for Output and I/O Signals (Continued)
Power Plane Reset Signal During Reset Immediately after Reset C3 (ICH2-M) S1 S3 S4/S5
IDE Interface PDA[2:0], SDA[2:0] PDCS1#, PDCS3# PDD[15:0], SDD[15:0] PDDACK#, SDDACK# PDIOR#, PDIOW# SDCS1#, SDCS3# SDIOR#, SDIOW# Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# Low High High-Z High High High High Interrupts PIRQ[A:H]# SERIRQ APICD[1:0] Main I/O Main I/O Main I/O PCIRST# PCIRST# PCIRST# High-Z High-Z High-Z High-Z High-Z High-Z Defined Running Running High-Z High-Z High-Z Off Off Off Off Off Off Undefined High High-Z High High High High Undefined High Defined High High High High Driven High High-Z Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off
USB Interface USBP[3:0][P:N] Resume I/O RSMRST# High-Z High-Z High-Z High-Z High-Z High-Z
Power Management CPUPERF# (ICH2-M) C3_STAT# / GPIO[21] (ICH2-M) SSMUXSEL (ICH2-M) SLP_S1# (ICH2-M) SLP_S3# SLP_S5# STP_PCI# (ICH2-M) STP_CPU# (ICH2-M) SUS_STAT# SUSCLK Main I/O Main I/O Main I/O Main I/O Resume I/O Resume I/O Main I/O Main I/O Resume I/O Resume I/O PCIRST# PCIRST# PCIRST# PCIRST# RSMRST# RSMRST# PCIRST# PCIRST# RSMRST# RSMRST# Processor Interface A20M# CPUPWRGD CPUSLP# IGNNE# INIT# INTR NMI SMI# STPCLK# CPU I/O Main I/O CPU I/O CPU I/O CPU I/O CPU I/O CPU I/O CPU I/O CPU I/O PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# See Note 1 See Note 3 High See Note 1 High See Note 1 See Note 1 High High High High-Z High High High Low Low High High Defined High-Z High High High Defined Defined Defined Low High High-Z Defined (ICH2) Low (ICH2-M) High High Low Low High Low Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off High-Z High Low High High High High High High High-Z High Low High High High High High High Running Defined Low Defined High High High Defined Low Defined Low Defined Low High High Low Low Low Off Off Off Low Low High Low Low Low Off Off Off Low Low Low Low Low Low
3-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Power Planes and Pin States
Table 3-4.
Signal Name
Power Plane and States for Output and I/O Signals (Continued)
Power Plane Reset Signal During Reset Immediately after Reset C3 (ICH2-M) S1 S3 S4/S5
SMBus Interface SMBCLK, SMBDATA Resume I/O RSMRST# High-Z High-Z Defined Defined Defined Defined
System Management Interface SMLINK[1:0] Resume I/O RSMRST# High-Z High-Z Defined Defined Defined Defined
Miscellaneous Signals SPKR Main I/O PCIRST# High-Z with internal pull-up AC’97 Interface AC_RST# AC_SDOUT AC_SYNC Resume I/O Main I/O Main I/O RSMRST# PCIRST# PCIRST# Low Low Low Low Running Running High Running Running Cold Reset Bit (High) Low Low Low Off Off Low Off Off Low Defined Defined Off Off
Unmuxed GPIO Signals GPIO[18] (ICH2) GPIO[19:20] (ICH2) GPIO[21] (ICH2) GPIO[22] (ICH2) GPIO[23] (ICH2) GPIO[24] (ICH2) GPIO[25] GPIO[27:28] Main I/O Main I/O Main I/O Main I/O Main I/O Resume I/O Resume I/O Resume I/O PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# RSMRST# RSMRST# RSMRST# High High High High-Z Low High-Z High-Z HIgh-Z See Note 2 High High High-Z Low High High High — — — — — — Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Off Off Off Off Off Defined Defined Defined Off Off Off Off Off Defined Defined Defined
.
NOTES: 1. ICH2 and ICH2-M: The ICH2/ICH2-M sets these signals at reset for processor frequency strap. 2. ICH2 and ICH2-M: GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH2 comes out of reset 3. ICH2 and ICH2-M: CPUPWRGD is an open-drain output that represents a logical AND of the ICH2’s VRMPWRGD (VGATE / VRMPWRGD for the ICH2-M) and PWROK signals and, thus, are driven low by ICH2/ICH2-M when either VRMPWRGD (VGATE / VRMPWRGD for the ICH2-M) or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z. 4. ICH2-M Only: LAN Connect and EEPROM signals will either be "Defined" or "Off" in S3–S5 states depending on whether or not the LAN power planes are active. 5. GPIO[24:25, 27:28] for the ICH2 and GPIO[25, 27:28] for the 82801BAM ICH2-M: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this point, they will be driven to their default (High) state.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
3-5
Power Planes and Pin States
3.5
Power Planes for Input Signals
Table 3-5 shows the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include:
• • • • •
High Low Static: Will be high or low, but will not change Driven: Will be high or low, and is allowed to change Running: For input clocks
Table 3-5. Power Plane for Input Signals
Signal Name BATLOW# (ICH2-M) A20GATE AC_BIT_CLK AC_SDIN[1:0] AGPBUSY# (ICH2-M) APICCLK CLK14 CLK48 CLK66 EE_DIN FERR# INTRUDER# IRQ[15:14] LAN_CLK RSM_PWROK (ICH2) LAN_PWROK (ICH2-M) LAN_RXD[2:0] LDRQ[0]# LDRQ[1]# OC[3:0]# PCICLK PDDREQ PIORDY PME# PWRBTN# PWROK RCIN# REQ[0:5]# REQ[B:A]# Power Well Resume I/O Main I/O Main I/O Resume I/O Main I/O Main I/O Main I/O Main I/O Main Logic LAN I/O Main I/O RTC Main I/O LAN I/O Driver During Reset Power Supply External Microcontroller AC’97 Codec AC’97 Codec AGP Component Clock Generator Clock Generator Clock Generator Clock Generator EEPROM component CPU External Switch IDE LAN Connect component External RC Circuit (ICH2) Power Supply (ICH2-M) LAN Connect component LPC Devices LPC Devices External Pull-Ups Clock Generator IDE Device IDE Device Internal Pull-Up Internal Pull-Up System Power Supply External Microcontroller PCI Master PC/PCI Devices C3 (ICH2-M) High Static Driven Driven Driven Running Running Running Running Driven Static Driven Driven Driven S1 High Static Low Low High Low Low Low Low Driven Static Driven Static Driven S3 High Low Low Low Low Low Low Low Low Note 1 Low Driven Low Note 1 S5 High Low Low Low Low Low Low Low Low Note 1 Low Driven Low Note 1
Resume I/O
High
High
Static
Static
LAN I/O Main I/O Main I/O Resume I/O Main I/O Main I/O Main I/O Resume I/O Resume I/O Main I/O Main I/O Main I/O Main I/O
Driven Driven Driven Driven Running Driven Static Driven Driven Driven High Driven Driven
Driven High High Driven Low Static Static Driven Driven Driven High Driven Driven
Note 1 Low Low Driven Low Low Low Driven Driven Low Low Low Low
Note 1 Low Low Driven Low Low Low Driven Driven Low Low Low Low
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
Power Planes and Pin States
Table 3-5. Power Plane for Input Signals (Continued)
Signal Name RI# RSMRST# RTCRST# SDDREQ SERR# SIORDY SMBALERT# THRM# VRMPWRGD (ICH2) VGATE / VRMPWRGD (ICH2-M)
.
Power Well Resume I/O RTC RTC Main I/O Main I/O Main I/O Resume I/O Main I/O Main I/O
Driver During Reset Serial Port Buffer External RC circuit External RC circuit IDE Drive PCI Bus Peripherals IDE Drive External pull-up Thermal Sensor CPU Voltage Regulator
C3 (ICH2-M) Driven High High Driven Driven Driven Driven Driven Driven
S1 Driven High High Static High Static Driven Driven High
S3 Driven High High Low Low Low Driven Low Low
S5 Driven High High Low Low Low Driven Low Low
Main I/O
CPU Voltage Regulator
Driven
High
Low
Low
NOTES: 1. LAN Connect and EEPROM signals will either be "Driven" or "Low" in S3–S5 states depending upon whether or not the LAN power planes are active.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
3-7
Power Planes and Pin States
This page is intentionally left blank
3-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
System Clock Domains
System Clock Domains
Table 4-1 shows the system clock domains. Figure 4-2 shows the assumed connection of the various system components, including the clock generator. For complete details of the system clocking solution, refer to the system’s clock generator component specification. Figure 4-1. ICH2 and System Clock Domains
Clock Domain ICH2 CLK66 Frequency Source Usage Hub interface, processor interface. AGP. 66 MHz Main Clock Generator 82801BA ICH2: It is shut off during S3 or below. 82801BAM ICH2-M: It is shut off during S1 or below. Free-running PCI Clock to ICH2/ICH2-M. ICH2 PCICLK 33 MHz Main Clock Generator
4
82801BA ICH2: This clock remains on during S0 and S1 state, and is expected to be shut off during S3 or below. 82801BAM ICH2-M: This clock remains on during S0 state, and is expected to be shut off during S1 or below.
System PCI
33 MHz
Main Clock Generator
PCI Bus, LPC I/F. These only go to external PCI and LPC devices. 82801BAM ICH2-M: These will stop based on CLKRUN# (and STP_PCI#) Super I/O, USB Controller. 82801BA ICH2: Expected to be shut off during S3 or below. 82801BAM ICH2-M: Expected to be shut off during S1 or below. Used for ACPI timer. 82801BA ICH2: Expected to be shut off during S3 or below. 82801BAM ICH2-M: Expected to be shut off during S1 or below. AC’97 Link. Generated by AC’97 CODEC. Can be shut off by codec in D3.
ICH2 CLK48
48 MHz
Main Clock Generator
ICH2 CLK14
14.31818 MHz
Main Clock Generator
ICH2 AC_BIT_CLK
12.288 MHz
AC’97 Codec
82801BA ICH2: Expected to be shut off during S3 or below. 82801BAM ICH2-M: Expected to be shut off during S1 or below.
RTC
32.768 kHz
ICH2
RTC, Power Management. ICH2 has its own oscillator. Always running, even in G3 state. Used for ICH2/ICH2-M processor interrupt messages. Runs at 33.33 MHz.
ICH2 APICCLK
33.33 MHz
Main Clock Generator
82801BA ICH2: Expected to be shut off during S3 or below. 82801BAM ICH2-M: Expected to be shut off during S1 or below. Generated by the LAN Connect component. 82801BA ICH2: Expected to be shut off during S3 or below. 82801BAM ICH2-M: Expected to be shut off during S1 or below.
LAN_CLK
0.8 to 50 MHz
LAN Connect Component
82801BA ICH2 and 82801BAM ICH2-M Datasheet
4-1
System Clock Domains
Figure 4-2. Conceptual System Clock Diagram (82801BA ICH2 and 82801BAM ICH2-M)
Processor(s) Hclock(s) (66/100/133 MHz)
HClock (66/100/133 MHz) AGP Clock (66 M Hz) AGP Clock (66 M Hz)
Host Controller
AGP
Mem ory
RDRAM Clock G enerator
66 MHz 2 33 MHz APIC CLK 14.31818 M Hz ICH2 48 MHz STP_CPU# (ICH2-M only) STP_PCI# (ICH2-M only) SLP_S1# (ICH2-M only) 2 or 3 Clock G enerator PCI Clocks (33 MHz) 14.31818 M Hz 48 MHz
12.288 MHz 50 MHz
AC'97 Codec(s) LAN Connect
32 kHz XTAL
SUSCLK# (32 kHz)
4-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Functional Description
Functional Description
5.1 Hub Interface to PCI Bridge (D30:F0)
5
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH2 implements the buffering and control logic between PCI and the hub interface. The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the hub interface. All register contents will be lost when core well power is removed.
5.1.1
PCI Bus Interface
The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals are 5V tolerant. The ICH2 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH2 requests. Note that most transactions targeted to the ICH2 will first appear on the external PCI bus before being claimed back by the ICH2. The exceptions are I/O cycles involving USB, IDE, and AC’97. These transactions will complete over the hub interface without appearing on the external PCI bus. Configuration cycles targeting USB, IDE or AC’97 will appear on the PCI bus. If the ICH2 is programmed for positive decode, the ICH2 will claim the cycles appearing on the external PCI bus in medium decode time. If the ICH2 is programmed for subtractive decode, the ICH2 will claim these cycles in subtractive time. If the ICH2 is programmed for subtractive decode, these cycles can be claimed by another positive decode agent out on PCI. This architecture enables the ability to boot off of a PCI card that positively decodes the boot cycles. To boot off a PCI card it is necessary to keep the ICH2 in subtractive decode mode. When booting off a PCI card, the BOOT_STS bit (bit 2, TCO2 Status Register) will be set. For the 82801BAM ICH2-M, devices on the ICH2-M PCI bus (other than the ICH2-M) are not permitted to assert the PLOCK# signal. Note: Note: The ICH2’s AC’97, IDE, and USB Controllers can not access PCI address ranges. PCI devices that cause long latencies (numerous retries) to processor-to-PCI Locked cycles may starve isochronous transfers between USB or AC’97 devices and memory. This will result in overrun or underrun, causing reduced quality of the isochronous data (e.g., audio). PCI configuration write cycles, initiated by the processor, with the following characteristics will be converted to a Special Cycle with the Shutdown message type.
Note:
• • • • •
Device Number (AD[15:11]) = ‘11111’ Function Number (AD[10:8]) = ‘111’ Register Number (AD[7:2]) = ‘000000’ Data = 00h Bus number matches secondary bus number
82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-1
Functional Description
Note:
If the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the ICH2 will not allow upstream requests to be performed until the cycle completion. This may be critical for isochronous buses that assume certain timing for their data flow (e.g., AC’97 or USB). Devices on these buses may suffer from underrun if the asynchronous traffic is too heavy. Underrun means that the same data is sent over the bus while ICH2 is not able to issue a request for the next data. Snoop cycles are not permitted while the front side bus is locked. Locked cycles are assumed to be rare. Locks by PCI targets are assumed to exist for a short duration (a few microseconds at most). If a system has a very large number of locked cycles and some that are very long, the system will definitely experience underruns and overruns. The units most likely to have problems are the AC'97 controller and the USB controller. Other units could get underruns/overruns, but are much less likely. The IDE controller (due to its stalling capability on the cable) should not get any underruns or overruns. The ICH2 was designed to provide high performance support to PCI peripherals using its data prefetch capabilities. If a PCI master is burst reading and is disconnected by the ICH2 to pre-fetch the requested cache line, the ICH2 will Delay Transaction the cycle while it prefetches more data, and give the bus to another agent. Once the bus is given back to this bus master, if it does not return with the successive previously requested read address, which was prefetched by the ICH2, the ICH2 will keep retrying the bus master until either it comes back for the prefetched data, or the Delayed Transaction Discard Timer expires (1024 PCI clocks) before discarding this prefetched data and servicing the request. This induces long latencies to PCI bus masters that behave this way. To reduce this latency, the Discard Timer Mode bit (D30:F0;CNF(50-51h):[bit-2]) can be set to 1. This will reduce the discard timer from 1024 PCI clocks (32 us) to 128 clocks (4 us) and improve latency for masters with this behavior.
Note:
Note:
5.1.2
PCI-to-PCI Bridge Model
From a software perspective, the ICH2 contains a PCI-to-PCI bridge. This bridge connects the hub interface to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH2 can have its decode ranges programmed by existing plug-and-play software such that PCI ranges do not conflict with AGP and graphics aperture ranges in the Host controller.
5.1.3
IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), the ICH2 asserts one address signal as an IDSEL. When accessing device 0, the ICH2 asserts AD16. When accessing Device 1, the ICH2 asserts AD17. This mapping continues up to device 15 where the ICH2 asserts AD31. Note that the ICH2’s internal functions (AC’97, IDE, USB, and PCI Bridge) are enumerated like they are on a separate PCI bus (the hub interface) from the external PCI bus. The integrated LAN Controller is Device 8 on the ICH2’s PCI bus and, hence, uses AD24 for IDSEL
5.1.4
SERR# Functionality
There are several internal and external sources that can cause SERR#. The ICH2 can be programmed to cause an NMI based on detecting that an SERR# condition has occurred. The NMI can also be routed to, instead, cause an SMI#. Note that the ICH2 does not drive the external PCI bus SERR# signal active onto the PCI bus. The external SERR# signal is an input into the ICH2 driven only by external PCI devices. The conceptual logic diagrams in Figure 5-1 and Figure 5-2 illustrate all sources of SERR#, along with their respective enable and status bits. Figure 5-3 shows how the ICH2 error reporting logic is configured for NMI# generation.
5-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Functional Description
Figure 5-1. Primary Device Status Register Error Reporting Logic
D30:F0 BRIDGE_CNT [Parity Error Response Enable] D30:F0 BRIDGE_CNT [SERR# Enable] PCI Address Parity Error D30:F0 CMD [SERR_EN] D30:F0 ERR_STS [SERR_DTT] D30:F0 CMD [SERR_EN]
AND AND
D30:F0 PD_STS [SSE]
OR
Delayed Transaction Timeout D30:F0 ERR_CMD [SERR_DTT_EN] SERR# Pin D30:F0 BRIDGE_CNT [SERR# Enable] D30:F0 ERR_CMD [SERR_RTA_EN] Received Target Abort
AND AND
AND
OR
AND
D30:F0 ERR_STS [SERR_RTA]
Figure 5-2. Secondary Status Register Error Reporting Logic
D30:F0 BRIDGE_CNT [SERR# Enable] AND D30:F0 SECSTS [SSE] AND
PCI Delayed Transaction Timeout D31:F0 D31_ERR_CFG [SERR_DTT_EN]
LPC Device Signaling an Error IOCHK# via SERIRQ TCO1_STS [HUBERR_STS] D31:F0 D31_ERR_CFG [SERR_RTA_EN] Received Target Abort OR
AND
82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-3
Functional Description
Figure 5-3. NMI# Generation Logic
NMI_SC [IOCHK_NMI_STS]
IOCHK From SERIRQ Logic NMI_SC [IOCHK_NMI_EN]
AND
NMI_SC [PCI_SERR_EN]
NMI_SC [SERR#_NMI_STS]
AND
D30:F0 SECSTS [SSE] D30:F0 PDSTS [SSE]
OR
TCO1_STS [HUBNMI_STS] TCO1_CNT [NMI_NOW] To NMI# Output and Gating Logic
OR OR
AND
Hub Interface Parity Error Detected
AND
D30:F0 CMD [Parity Error Response] PCI Parity Error detected during AC'97, IDE or USB Master Cycle D30:F0 PD_STS [DPD]
AND
D30:F0 BRIDGE_CNT [Parity Error Response Enable] D30:F0 SECSTS [DPD]
OR
NMI_EN [NMI_EN] PCI Parity Error detected during LPC or Legacy DMA Master Cycle D31:F0 PCICMD [PER]
AND
D31:F0 PCISTA [DPED]
5.1.5
Parity Error Detection
The ICH2 can detect and report different parity errors in the system. The ICH2 can be programmed to cause an NMI (or SMI# if NMI is routed to SMI#) based on detecting a parity error. The conceptual logic diagram in Figure 5-3 details all the parity errors that the ICH2 can detect, along with their respective enable bits, status bits, and the results. Note: If NMIs are enabled and parity error checking on PCI is also enabled, then parity errors cause an NMI. Some operating systems will not attempt to recover from this NMI, since it considers the detection of a PCI error to be a catastrophic event.
5-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Functional Description
5.1.6
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the ICH2. The PCI specification defines two mechanisms to access configuration space (Mechanism #1 and Mechanism #2). The ICH2 only supports Mechanism #1. Configuration cycles for PCI Bus #0 devices #2 through #31, and for PCI Bus numbers greater than 0 will be sent towards the ICH2 from the host controller. The ICH2 compares the non-zero Bus Number with the Secondary Bus Number and Subordinate Bus number registers of its P2P bridge to determine if the configuration cycle is meant for Primary PCI or a downstream PCI bus.
Type 0 to Type 0 Forwarding
When a Type 0 configuration cycle is received on the hub interface, the ICH2 forwards these cycles to PCI and then reclaims them. The ICH2 uses address bits AD[15:14] to communicate the ICH2 device numbers in Type 0 configuration cycles. If the Type 0 cycle on the hub interface specifies any device number other than 30 or 31, the ICH2 will not set any address bits in the range AD[31:11] during the corresponding transaction on PCI. Table 5-1 shows the device number translation. Table 5-1. Type 0 Configuration Cycle Device Number Translation
Device # In Hub Interface Type 0 Cycle 0 through 29 30 31 AD[31:11] During Address Phase of Type 0 Cycle on PCI 0000000000000000_00000b 0000000000000000_01000b 0000000000000000_10000b
The ICH2 logic generates single DWord configuration read and write cycles on the PCI bus. The ICH2 generates a Type 0 configuration cycle for configurations to the bus number matching the PCI bus. Type 1 configuration cycles are converted to Type 0 cycles in this case. If the cycle is targeting a device behind an external bridge, the ICH2 runs a Type 1 cycle on the PCI bus.
Type 1 to Type 0 Conversion
When the bus number for the Type 1 configuration cycle matches the PCI (Secondary) bus number, the ICH2 converts the address as follows:
• For device numbers 0 through 15, only one bit of the PCI address [31:16] is set. If the device
number is 0, AD[16] is set; if the device number is 1, AD[17] is set; etc.
• The ICH2 always drives 0s on bits AD[15:11] when converting Type 1 configurations cycles
to Type 0 configuration cycles on PCI.
• Address bits [10:1] are also passed unchanged to PCI. • Address bit [0] is changed to 0.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-5
Functional Description
5.1.7
PCI Dual Address Cycle (DAC) Support (82801BA ICH2 only)
The 82801BA ICH2 supports Dual Address Cycle (DAC) format on PCI for cycles from PCI initiators to main memory. This allows PCI masters to generate an address up to 44 bits. The size of the actual supported memory space will be determined by the memory controller and the processor. The DAC mode is only supported for PCI adapters and is not supported for any of the internal PCI masters (IDE, LAN, USB, AC’97, 8237 DMA, etc.). ICH2 does not support DAC for processorinitiated cycles. When a PCI master wants to initiate a cycle with an address above 4 GB, it follows the following behavioral rules (See PCI 2.2 Specification, section 3.9 for more details): 1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the DAC encoding on the C/BE# signals. This unique encoding is 1101. 2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low address. 3. On the second clock, the peripheral drives AD[31:0] with the high address. The address is right justified: A[43:32] appear on AD[12:0]. The value of AD[31:13] is expected to be 0, however the ICH2 will ignore these bits. C/BE# indicate the bus command type (Memory Read, Memory Write, etc.) 4. The rest of the cycle proceeds normally.
5.2
LAN Controller (B1:D8:F0)
The ICH2’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed data transfers over the PCI bus. Its bus master capabilities enable the component to process high level commands and perform multiple operations, which lowers processor utilization by offloading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN Controller to transmit data with minimum interframe spacing (IFS). The ICH2 integrated LAN Controller can operate in either full duplex or half duplex mode. In full duplex mode the LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. The integrated LAN Controller also includes an interface to a serial (4-pin) EEPROM. The EEPROM provides power-on initialization for hardware and software configuration parameters. From a software perspective, the integrated LAN Controller appears to reside on the secondary side of the ICH2’s virtual PCI-to-PCI Bridge (see Section 5.1.2). This is typically Bus 1; it may be assigned a different number depending on system configuration.
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Functional Description
Feature Summary
• Compliance with Advanced Configuration and Power Interface and PCI Power Management • • • • • • •
standards Support for wake-up on interesting packets and link status change Support for remote power-up using Wake on LAN* (WOL) technology Deep power-down mode support Support of Wired for Management (WfM) Rev 2.0 Backward compatible software with 82557, 82558 and 82559 TCP/UDP checksum offload capabilities Support for Intel’s Adaptive Technology
5.2.1
LAN Controller Architectural Overview
Figure 5-4 is a high level block diagram of the ICH2 integrated LAN Controller. It is divided into four main subsystems: a Parallel subsystem, a FIFO subsystem and the Carrier-Sense Multiple Access with Collision Detect (CSMA/CD) unit.
Figure 5-4. Integrated LAN Controller Block Diagram
EEPROM Interface
PCI Target and EEPROM Interface
3 Kbyte Tx FIFO
Four Channel Addressing Unit DMA Micromachine FIFO Control CSMA/CD Unit
PCI Interface
PCI Bus Interface Unit (BIU)
LAN Connect Interface
Data Interface Unit (DIU)
Dual Ported FIFO
3 Kbyte Rx FIFO
Parallel Subsystem Overview
The parallel subsystem is divided into several functional blocks: a PCI bus master interface, a micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/ EEPROM/ interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data (e.g., transmit, receive, and configuration data) and command and status parameters between these two blocks. The PCI bus master interface provides a complete interface to the PCI bus and is compliant with the PCI Bus Specification, Revision 2.2. The LAN Controller provides 32 bits of addressing and data, as well as the complete control interface to operate on the PCI bus. As a PCI target, it follows the PCI configuration format which allows all accesses to the LAN Controller to be automatically mapped into free memory and I/O space upon initialization of a PCI system. For processing of transmit and receive frames, the integrated LAN Controller operates as a master on the PCI bus, initiating zero wait state transfers for accessing these data parameters.
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Functional Description
The LAN Controller Control/Status Register Block is part of the PCI target element. The Control/ Status Register block consists of the following LAN Controller internal control registers: System Control Block (SCB), PORT, EEPROM Control and Management Data Interface (MDI) Control. The micromachine is an embedded processing unit contained in the LAN Controller that enables Adaptive Technology. The micromachine accesses the LAN Controller’s microcode ROM, working its way through the opcodes (or instructions) contained in the ROM to perform its functions. Parameters accessed from memory (e.g., pointers to data buffers) are also used by the micromachine during the processing of transmit or receive frames by the LAN Controller. A typical micromachine function is to transfer a data buffer pointer field to the LAN Controller’s DMA unit for direct access to the data buffer. The micromachine is divided into two units, Receive Unit and Command Unit that includes transmit functions. These two units operate independently and concurrently. Control is switched between the two units according to the microcode instruction flow. The independence of the Receive and Command units in the micromachine allows the LAN Controller to execute commands and receive incoming frames simultaneously, with no real-time processor intervention. The LAN Controller contains an interface to an external serial EEPROM. The EEPROM is used to store relevant information for a LAN connection such as node address, as well as board manufacturing and configuration information. Both read and write accesses to the EEPROM are supported by the LAN Controller. Information on the EEPROM interface is detailed in Section 5.2.4.
FIFO Subsystem Overview
The ICH2 LAN Controller FIFO subsystem consists of a 3 KB transmit FIFO and 3 KB receive FIFO. Each FIFO is unidirectional and independent of the other. The FIFO subsystem serves as the interface between the LAN Controller parallel side and the serial CSMA/CD unit. It provides a temporary buffer storage area for frames as they are either being received or transmitted by the LAN Controller, which improves performance: • Transmit frames can be queued within the transmit FIFO, allowing back-to-back transmission within the minimum Interframe Spacing (IFS). • The storage area in the FIFO allows the LAN Controller to withstand long PCI bus latencies without losing incoming data or corrupting outgoing data. • The ICH2 LAN Controller’s transmit FIFO threshold allows the transmit start threshold to be tuned to eliminate underruns while concurrent transmits are being performed. • The FIFO subsection allows extended PCI zero wait state burst accesses to or from the LAN Controller for both transmit and receive frames since the transfer is to the FIFO storage area rather than directly to the serial link. • Transmissions resulting in errors (collision detection or data underrun) are retransmitted directly from the LAN Controller’s FIFO, increasing performance and eliminating the need to re-access this data from the host system. • Incoming runt receive frames (in other words, frames that are less than the legal minimum frame size) can be discarded automatically by the LAN Controller without transferring this faulty data to the host system.
Serial CSMA/CD Unit Overview
The CSMA/CD unit of the ICH2 LAN Controller allows it to be connected to the 82562ET/EM 10/100 Mbps Ethernet LAN Connect components or the 82562EH 1 Mbps HomePNA*-compliant LAN Connect component. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. The CSMA/CD unit can also be placed in a full duplex mode which allows simultaneous transmission and reception of frames.
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Functional Description
5.2.2
LAN Controller PCI Bus Interface
As a Fast Ethernet Controller, the role of the ICH2 integrated LAN Controller is to access transmitted data or deposit received data. The LAN Controller, as a bus master device, initiates memory cycles via the PCI bus to fetch or deposit the required data. To perform these actions, the LAN Controller is controlled and examined by the processor via its control and status structures and registers. Some of these control and status structures reside in the LAN Controller and some reside in system memory. For access to the LAN Controller’s Control/ Status Registers (CSR), the LAN Controller acts as a slave (in other words, a target device). The LAN Controller serves as a slave also while the processor accesses the EEPROM.
5.2.2.1
Bus Slave Operation
The ICH2 integrated LAN Controller serves as a target device in one of the following cases:
• Processor accesses to the LAN Controller System Control Block (SCB) Control/Status
Registers (CSR)
• • • •
Processor accesses to the EEPROM through its CSR Processor accesses to the LAN Controller PORT address via the CSR Processor accesses to the MDI control register in the CSR PCI Configuration cycles
The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The LAN Controller treats accesses to these memory spaces differently.
Control/Status Register (CSR) Accesses
The integrated LAN Controller supports zero wait state single cycle memory or I/O mapped accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish this. Based on its needs, the software driver uses either memory or I/O mapping to access these registers. The LAN Controller provides 4 KB of CSR space, which includes the following elements:
• • • • •
System Control Block (SCB) registers PORT register EEPROM control register MDI control register Flow control registers
In the case of accessing the Control/Status Registers, the processor is the initiator and the LAN Controller is the target. Read Accesses: The processor, as the initiator, drives address lines AD[31:0], the command and byte enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. As a slave, the LAN Controller controls the TRDY# signal and provides valid data on each data access. The LAN Controller allows the processor to issue only one read cycle when it accesses the Control/Status Registers, generating a disconnect by asserting the STOP# signal. The processor can insert wait states by deasserting IRDY# when it is not ready.
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Functional Description
Write Accesses: The processor, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. It also provides the LAN Controller with valid data on each data access immediately after asserting IRDY#. The LAN Controller controls the TRDY# signal and asserts it from the data access. The LAN Controller allows the processor to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
Retry Premature Accesses
The LAN Controller responds with a retry to any configuration cycle accessing the LAN Controller before the completion of the automatic read of the EEPROM. The LAN Controller may continue to Retry any configuration accesses until the EEPROM read is complete. The LAN Controller does not enforce the rule that the retried master must attempt to access the same address again to complete any delayed transaction. Any master access to the LAN Controller after the completion of the EEPROM read will be honored.
Error Handling
Data Parity Errors: The LAN Controller checks for data parity errors while it is the target of the transaction. If an error was detected, the LAN Controller always sets the Detected Parity Error bit in the PCI Configuration Status register, bit 15. The LAN Controller also asserts PERR#, if the Parity Error Response bit is set (PCI Configuration Command register, bit 6). The LAN Controller does not attempt to terminate a cycle in which a parity error was detected. This gives the initiator the option of recovery. Target-Disconnect: The LAN Controller terminates a cycle in the following cases:
• After accesses to its CSR • After accesses to the configuration space
System Error: The LAN Controller reports parity error during the address phase using the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit are not set, the LAN Controller only sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set, the LAN Controller sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and asserts SERR# for one clock. The LAN Controller, when detecting system error, will claim the cycle if it was the target of the transaction and continue the transaction as if the address was correct. Note: The LAN Controller reports a system error for any error during an address phase, whether or not it is involved in the current transaction.
5.2.2.2
Bus Master Operation
As a PCI Bus Master, the ICH2 integrated LAN Controller initiates memory cycles to fetch data for transmission or deposit received data and for accessing the memory resident control structures. The LAN Controller performs zero wait state burst read and write cycles to the host main memory. For bus master cycles, the LAN Controller is the initiator and the host main memory (or the PCI host bridge, depending on the configuration of the system) is the target. The processor provides the LAN Controller with action commands and pointers to the data buffers that reside in host main memory. The LAN Controller independently manages these structures and initiates burst memory cycles to transfer data to and from them. The LAN Controller uses the
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Functional Description
Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line) command for burst accesses to control structures. For all write accesses to the control structure, the LAN Controller uses the Memory Write (MW) command. For write accesses to the data structure, the LAN Controller may use either the Memory Write or Memory Write and Invalidate (MWI) commands. Read Accesses: The LAN Controller performs block transfers from host system memory to perform frame transmission on the serial link. In this case, the LAN Controller initiates zero wait state memory read burst cycles for these accesses. The length of a burst is bounded by the system, the LAN Controller’s internal FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA Maximum Byte Count in the Configure command. The transmit DMA Maximum Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after a LAN Controller internal arbitration. The LAN Controller, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. The LAN Controller asserts IRDY# to support zero wait state burst cycles. The target signals the LAN Controller that valid data is ready to be read by asserting the TRDY# signal. Write Accesses: The LAN Controller performs block transfers to host system memory during frame reception. In this case, the LAN Controller initiates memory write burst cycles to deposit the data, usually without wait states. The length of a burst is bounded by the system and the LAN Controller’s internal FIFO threshold. The length of a write burst may also be bounded by the value of the Receive DMA Maximum Byte Count in the configure command. The Receive DMA Maximum Byte Count value indicates the maximum number of receive DMA PCI transfers that will be completed before the LAN Controller internal arbitration. The LAN Controller, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. The LAN Controller asserts IRDY# to support zero wait state burst cycles. The LAN Controller also drives valid data on AD[31:0] lines during each data phase (from the first clock and on). The target controls the length and signal’s completion of a data phase by deassertion and assertion of TRDY#. Cycle Completion: The LAN Controller completes (terminates) its initiated memory burst cycles in the following cases:
• Normal Completion: All transaction data has been transferred to or from the target device
(for example, host main memory).
• Backoff: Latency Timer has expired and the bus grant signal (GNT#) was removed from the • •
LAN Controller by the arbiter, indicating that the LAN Controller has been preempted by another bus master. Transmit or Receive DMA Maximum Byte Count: The LAN Controller burst has reached the length specified in the transmit or receive DMA Maximum Byte Count field in the Configure command block. Target Termination: The target may request to terminate the transaction with a targetdisconnect, target-retry, or target-abort. In the first two cases, the LAN Controller initiates the cycle again. In the case of a target-abort, the LAN Controller sets the Received Target-Abort bit in the PCI Configuration Status field (PCI Configuration Status register, bit 12) and does not re-initiate the cycle. Master Abort: The target of the transaction has not responded to the address initiated by the LAN Controller (in other words, DEVSEL# has not been asserted). The LAN Controller simply deasserts FRAME# and IRDY# as in the case of normal completion. Error Condition: In the event of parity or any other system error detection, the LAN Controller completes its current initiated transaction. Any further action taken by the LAN Controller depends on the type of error and other conditions.
• •
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Functional Description
Memory Write and Invalidate
The LAN Controller has four Direct Memory Access (DMA) channels. Of these four channels (the receive DMA channel) is used to deposit the large number of data bytes received from the link into system memory. The receive DMA uses both the Memory Write (MW) and the Memory Write and Invalidate (MWI) commands. To use MWI, the LAN Controller must guarantee the following: 1. Minimum transfer of one cache line 2. Active byte enable bits (or BE[3:0]# are all low) during MWI access 3. The LAN Controller may cross the cache line boundary only if it intends to transfer the next cache line too. To ensure the above conditions, the LAN Controller may use the MWI command only under the following conditions: 1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16 DWords. 2. The accessed address is cache line aligned. 3. The LAN Controller has at least 8 or 16 DWords of data in its receive FIFO. 4. There are at least 8 or 16 DWords of data space left in the system memory buffer. 5. The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1. 6. The MWI Enable bit in the LAN Controller Configure command should is set to 1. If any one of the above conditions does not hold, the LAN Controller will use the MW command. If a MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than CLS), then the LAN Controller terminates the MWI cycle at the end of the cache line. The next cycle will be either a MW or MWI cycle depending on the conditions listed above. If the LAN Controller started a MW cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the LAN Controller Configure command (byte 3, bit 3). If this bit is set, the LAN Controller terminates the MW cycle and attempts to start a new cycle. The new cycle is a MWI cycle if this bit is set and all of the above listed conditions are met. If the bit is not set, the LAN Controller continues the MW cycle across the cache line boundary if required.
Read Align
The Read Align feature enhances the LAN Controller’s performance in cache line oriented systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address may cause low performance. To resolve this performance anomaly, the LAN Controller attempts to terminate transmit DMA cycles on a cache line boundary and start the next transaction on a cache line aligned address. This feature is enabled when the Read Align Enable bit is set in the LAN Controller Configure command (byte 3, bit 2). If this bit is set, the LAN Controller operates as follows: • When the LAN Controller is almost out of resources on the transmit DMA (i.e., the transmit FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line boundary when possible. • When the arbitration counter’s feature is enabled (i.e., the Transmit DMA Maximum Byte Count value is set in the Configure command), the LAN Controller switches to other pending DMAs on cache line boundary only.
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Functional Description
Note:
This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. This feature should be used only when the CLS register in PCI Configuration space is set to 8 or 16. The LAN Controller reads all control data structures (including Receive Buffer Descriptors) from the first DWord (even if it is not required) to maintain cache line alignment. Error Handling Data Parity Errors: As an initiator, the LAN Controller checks and detects data parity errors that occur during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register, bit 6), the LAN Controller also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the LAN Controller during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
Note:
Note:
5.2.3
CLOCKRUN# Signal (82801BAM ICH2-M only)
The ICH2-M receives a free-running 33 MHz clock. It does not stop based on the CLKRUN# signal and protocol. When the LAN controller runs cycles on the PCI bus, the ICH2-M makes sure that the STP_PCI# signal is high indictating that the PCI clock is running. This is to make sure that any PCI tracker will not get confused by transactions on the PCI bus with its PCI clock stopped.
5.2.3.1
PCI Power Management
Enhanced support for the power management standard, PCI specification rev. 2.2, is provided in the ICH2 integrated LAN Controller. The LAN Controller supports a large set of wake-up packets and the capability to wake the system from a low power state on a link status change. The LAN Controller enables the host system to be in a sleep state and remain virtually connected to the network. After a power management event or link status change is detected, the LAN Controller will wake the host system. The sections below describe these events, the LAN Controller power states, and estimated power consumption at each power state.
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Functional Description
Power States
The LAN Controller contains power management registers for PCI and implements all four power states defined in the Power Management Network Device Class Reference Specification, Rev. 1.0. The four states, D0 through D3, vary from maximum power consumption at D0 to the minimum power consumption at D3. PCI transactions are only allowed in the D0 state, except for host accesses to the LAN Controller’s PCI configuration registers. The D1 and D2 power management states enable intermediate power savings while providing the system wake-up capabilities. In the D3 state, the LAN Controller can provide wake-up capabilities. Wake-up indications from the LAN Controller are provided by the Power Management Event (PME#) signal. • D0 Power State. As defined in the Network Device Class Reference Specification, the device is fully functional in the D0 power state. In this state, the LAN Controller receives full power and should be providing full functionality. In the LAN Controller the D0 state is partitioned into two substates, D0 Uninitialized (D0u) and D0 Active (D0a). D0u is the LAN Controller’s initial power state following a PCI RST#. While in the D0u state, the LAN Controller has PCI slave functionality to support its initialization by the host and supports Wake on LAN* mode. Initialization of the CSR, Memory, or I/O Base Address Registers (PCI Configuration space) switches the LAN Controller from D0u state to D0a state. In the D0a state, the LAN Controller provides its full functionality and consumes its nominal power. In addition, the LAN Controller supports wake on link status change (see Section 5.2.3.3). While it is active, the LAN Controller requires a nominal PCI clock signal (in other words, a clock frequency greater than 16 MHz) for proper operation. The LAN Controller supports a dynamic standby mode. In this mode, the LAN Controller is able to save almost as much power as it does in the static power-down states. The transition to or from standby is done dynamically by the LAN Controller and is transparent to the software. • D1 Power State. For a device to meet the D1 power state requirements, as specified in the Advanced Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus transmission or interrupts; however, bus reception is allowed. Therefore, device context may be lost and the LAN Controller does not initiate any PCI activity. In this state, the LAN Controller responds only to PCI accesses to its configuration space and system wake-up events. The LAN Controller retains link integrity and monitors the link for any wake-up events such as wake-up packets or link status change. Following a wake-up event, the LAN Controller asserts the PME# signal. • D2 Power State. The ACPI D2 power state is similar in functionality to the D1 power state. In addition to D1 functionality, the LAN Controller can provide a lower power mode with wakeon-link status change capability. The LAN Controller may enter this mode if the link is down while the LAN Controller is in the D2 state. In this state, the LAN Controller monitors the link for a transition from an invalid to a valid link. The sub-10 mA state due to an invalid link can be enabled or disabled by the PME_EN bit in the Power Management Driver Register (PMDR). The LAN Controller will consume in D2 10 mA regardless of the link status. It is the LAN Connect component that consumes much less power during link down, hence LAN Controller in this state can consume 2 seconds) occurs that
unconditionally forces throttling, independent of the THTL_EN bit. The throttling due to Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and system. The Thermal Override condition will end when THRM# goes inactive. Throttling due to the THRM# signal has higher priority than the software-initiated throttling. Throttling does not occur when the system is in a C2 state (C2 or C3 for the ICH2-M), even if Thermal override occurs.
5.12.5.2
Transition Rules Among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and throttling states:
• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because
the processor can only perform one register access at a time and Sleep states have higher priority than thermal throttling.
• When the SLP_EN bit is set (system going to a sleep state (S1–S5), the THTL_EN bit can be
internally treated as being disabled (no throttling while going to sleep state). Note that thermal throttling (based on THRM# signal) cannot be disabled in an S0 state. However, once the SLP_EN bit is set, the thermal throttling is shut off (since STPCLK# will be active in S1–S5 states).
• If the THTL_EN bit is set, and a Level 2 (Level 2 or Level 3 for the ICH2-M) read then occurs,
the system should immediately go and stay in a C2 (C2 or C3 for the ICH2-M) state until a break event occurs. A Level 2 (Level 2 or Level 3 for the ICH2-M) read has higher priority than the software-initiated throttling or thermal throttling.
• If Thermal Override is causing throttling and a Level 2 (Level 2 or Level 3 for the ICH2-M)
read then occurs, the system will stay in a C2 (C2 or C3 for the ICH2-M) state until a break event occurs. A Level 2 (Level 2 or Level 3 for the ICH2-M) read has higher priority than the Thermal Override.
• After an exit from a C2 (C2 or C3 for the ICH2-M) state (due to a Break event), and if the
THTL_EN bit is still set, or if a Thermal Override is still occurring, the system will continue to throttle STPCLK#. Depending on the time of the break event, the first transition on STPCLK# active can be delayed by up to one period.
• The Host controller must post Stop-Grant cycles in such a way that the processor gets an
indication of the end of the special cycle prior to the ICH2 observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a sufficient period after the processor observes the response phase.
• If in the C1 state and the STPCLK# signal goes active, the processor will generate a StopGrant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should return to the C1 state.
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Functional Description
5.12.6
Dynamic PCI Clock Control (82801BAM ICH2-M)
For the ICH2-M, the PCI clock can be dynamically controlled independent of any other lowpower state. This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile Design Guide, and is transparent to software. The Dynamic PCI Clock control is handled using the following signals:
• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run • STP_PCI#: Used to stop the system PCI clock
Note: The 33 MHz clock to the ICH2-M is “free-running” and is not affected by the STP_PCI# signal.
5.12.6.1
Conditions for Stopping the PCI Clock (82801BAM ICH2-M)
When there is a lack of PCI activity, the ICH2-M has the capability to stop the PCI clocks to conserve power. “PCI activity” is defined as any activity that requires the PCI clock to be running. Any of the following conditions indicates that it is NOT OK to stop the PCI clock:
• • • •
Cycles on PCI or LPC Cycles of any internal device that would need to go on the PCI bus Cycles using PC/PCI DMA SERIRQ activity
Behavioral Descripion
• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH2-M deassert
(drive high) CLKRUN# for 1 clock and then tri-state the signal.
5.12.6.2
Conditions for Maintaining the PCI Clock (82801BAM ICH2-M)
PCI master that wish to maintain the PCI clock running will observe the CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.
Behavioral Description
• When the ICH2-M has tri-stated the CLKRUN# signal after deasserting it, the ICH2-M then
checks to see if the signal has been re-asserted (externally).
• After observing the CLKRUN# signal asserted for 1 clock, the ICH2-M again starts asserting
the signal.
• If an internal device needs the PCI bus, the ICH2-M asserts the CLKRUN# signal. 5.12.6.3 Conditions for Stopping the PCI Clock (82801BAM ICH2-M)
Behavioral Description
• If no device re-asserts CLKRUN# once it has been deasserted for 3 clocks, the ICH2-M stops
the PCI clock by asserting the STP_PCI# signal to the clock synthesizer.
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Functional Description
5.12.6.4
Conditions for Re-Starting the PCI Clock (82801BAM ICH2-M)
Behavioral Description
• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started. • When the ICH2-M observes the CLKRUN# signal asserted for 1 (free running) clock, the
ICH2-M deasserts the STP_PCI# signal to the clock synthesizer within 4 (free running) clocks.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the ICH2-M
again starts driving CLKRUN# asserted. If an internal source requests the clock to be re-started, the ICH2-M re-asserts CLKRUN#, and simultaneously deasserts the STP_PCI# signal.
5.12.6.5
Other Causes of CLKRUN# Going Active (82801BAM ICH2-M)
The following causes the ICH2-M to assert and/or maintain the CLKRUN# signal active (low):
• PC/PCI activity, which is started by one of the REQx# signals going active. It is expected that
a PC/PCI device asserts CLKRUN# prior to starting the start bit on the REQ# signal. Once the start bit is recognized, the ICH2-M makes sure CLKRUN# goes active if it should go inactive during the sequence.
• SERIRQ activity, which is started by the SERIRQ signal going low (in Quiet mode), or the
SERIRQ logic being in the Continuous Mode. It is expected that a SERIRQ device asserts CLKRUN# prior to starting the start bit on the SEIRQ signal. Once the start bit is recognized, the ICH2-M makes sure CLKRUN# goes active if it should go inactive during the sequence.
• Any internal or external bus master request, including LPC masters. Once the master request
is detected (via PCI REQ or LPC LDRQ[1:0]#), the ICH2-M maintains CLKRUN# active until the end of the sequence. This includes: — Any PCI REQ# low — Bus Master or DMA request pending (having come in via LDRQ[1:0]#) — Any cycle coming down from hub interface1 to PCI — Any PCI cycle currently in progress. For example, cycle forward by the ICH2-M from the hub interface to PCI, and then claimed by ICH2-M's PCI-to-LPC logic. That cycle runs as a Delayed Transaction on PCI. CLKRUN# should stay low until the cycle completes (without Delayed Transaction).
• Any bus master below PCI that needs to run a cycle. This could include the Front-Side-Bus
interrupt logic for the I/O APIC (if it is downstream of PCI).
5.12.6.6
LPC Devices and CLKRUN# (82801BAM ICH2-M)
If an LPC device (of any type) needs the 33 MHz PCI clock (e.g., for LPC DMA or LPC serial interrupt), it can assert CLKRUN#. Note that LPC devices running DMA or bus master cycles do not need to assert CLKRUN#, since the ICH2-M asserts it on their behalf.
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5.12.7
Sleep States
The ICH2 directly supports different sleep states (S1–S5), which are entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the
processor can only perform one register access at a time. A request to Sleep always has higher priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note
that thermal throttling cannot be disabled, but setting the SLP_EN bit will disable thermal throttling (since S1–S5 sleep state has higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state indicates a
complete loss of power.
5.12.7.1
Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type in the
SLP_TYP field, and then setting the SLP_EN bit. The hardware will then attempt to gracefully put the system into the corresponding Sleep state by first going to a C2 (C2 or C3 for the ICH2-M) state. See Section 5.12.5 for details on going to the C2 (C2 or C3 for the ICH2-M) state.
• Pressing the PWRBTN# signal for more than 4 seconds to cause a Power Button Override
event. In this case the transition to the S5 state will be less graceful, since there will be no dependencies on observing Stop-Grant cycles from the processor or on clocks other than the RTC clock. Table 5-41. Sleep Types
Sleep Type S1 (ICH2 only) S1 (ICH2-M only) Comment ICH2 asserts the CPUSLP# signal. This lowers the processor’s power consumption. No snooping is possible in this state. ICH2-M asserts the SLP_S1# signal. This can be connected to the system clock generator to either put it into a low-power mode or to remove its power altogether. No snooping is possible in this state. ICH2 asserts SLP_S3# (ICH2-M asserts SLP_S1# and SLP_S3#). The SLP_S3# signal controls the power to non-critical circuits. Power is only be retained to devices needed to wake from this sleeping state, as well as to the memory. ICH2 asserts SLP_S3# and SLP_S5# (ICH2-M asserts SLP_S1#, SLP_S3# and SLP_S5#). The SLP_S5# signal shuts off the power to the memory subsystem. Only devices needed to wake from this state should be powered. Same as S4. ICH2 asserts SLP_S3# and SLP_S5# (ICH2-M asserts SLP_S1#, SLP_S3# and SLP_S5#). The SLP_S5# signal shuts off the power to the memory subsystem. Only devices needed to wake from this state should be powered.
S3
S4
S5
5.12.7.2
Exiting Sleep States
Sleep states (S10–S5) are exited based on Wake events. The Wake events will force the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the hard disk may be shut off during a sleep state, and have to be enabled via a GPIO pin before it can be used.
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Functional Description
Upon exit from the ICH2-controlled Sleep states, the WAK_STS bit will be set. The possible causes of Wake Events (and their restrictions) are shown in Table 5-42. Notes:
• If in the S5 state due to a powerbutton override, the only wake event is power button. • For the ICH2-M, if the BATLOW# signal is asserted, the ICH2-M will not attempt to wake
from an S1 (Mobile) – S5 state, even if the power button is pressed. This prevents the system from waking when the battery power is insufficient to wake the system. Wake events that occur while BATLOW# is asserted are latched by the ICH2-M, and the system wakes after BATLOW# is deasserted. Table 5-42. Causes of Wake Events
Cause RTC Alarm Power Button GPI[0:n] USB LAN RI# AC97 PME# GST Timeout SMBALERT# SMBus Slave Message States Can Wake From S1–S5 (Note 1) S1–S5 S1–S5 (Note 1) S1–S4 S1–S5 S1–S5 (Note 1) S1–S5 S1–S5 (Note 1) S1M S1–S4 S1–S5 How Enabled Set RTC_EN bit in PM1_EN Register Always enabled as Wake event GPE1_EN register Set USB1_EN and USB2_EN bits in GPE0_EN Register Will use PME#. Wake enable set with LAN logic. Set RI_EN bit in GPE0_EN Register Set AC97_EN bit in GPE0_EN Register Set PME_EN bit in GPE0_EN Register. Setting the GST Timeout range to a value other than 00h. SMB_WAK_EN in the GPE0 Register Always enabled as a Wake Event
NOTES: 1. This will be a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP bits via software.
It is important to understand that the various GPIs have different levels of functionality when used as wake events. The GPIs that reside in the core power well can only generate wake events from an S1 state. Also, only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in ACPI I/O space. Table 5-43 summarizes the use of GPIs as wake events. Table 5-43. GPI Wake Events
GPI GPI[7:0], GPI[23:16] GPI[15:8] Power Well Core Resume Wake From S1 S1–S5 ACPI Compliant Notes
The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design. Approximations are shown in Table 5-44. The time indicates from when the Wake event occurs (signal transition) to when the processor is allowed to start its first cycle (CPURST# goes inactive). There will be very large additional delays for the processor to execute sufficient amounts of BIOS to invoke the OS (such as coming out of S1–S3) or spinning up the hard drive (e.g., coming out of S4 or S5).
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Table 5-44. Sleep State Exit Latencies
State S1 S3 S4 S5 Latency function transaction Address + endpoint number in function -> host transaction Start of frame marker and frame number Address + endpoint number in host -> function transaction for setup to a control endpoint Data packet PID even Data packet PID odd Receiver accepts error free data packet Rx device cannot accept data or Tx device cannot send data Endpoint is stalled Host-issued preamble. Enables downstream bus traffic to low speed devices.
PIDs are divided into four coding groups: token, data, handshake, and special, with the first two transmitted PID bits (PID[1:0]) indicating which group. This accounts for the distribution of PID codes.
5.16.4.4
Address Fields
Function endpoints are addressed using two fields: the function address field and the endpoint field.
Table 5-69. Address Field
Bit 0 1 2 3 Data Sent ADDR 0 ADDR 1 ADDR 2 ADDR 3 Bit 4 5 6 Data Sent ADDR 4 ADDR 5 ADDR 6
Address Field
The function address (ADDR) field specifies the function, via its address, that is either the source or destination of a data packet, depending on the value of the token PID. As shown in Table 5-69, a total of 128 addresses are specified as ADDR[6:0]. The ADDR field is specified for IN, SETUP, and OUT tokens.
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Functional Description
Endpoint Field
An additional four-bit endpoint (ENDP) field, shown in Table 5-70, permits more flexible addressing of functions in which more than one sub-channel is required. Endpoint numbers are function specific. The endpoint field is defined for IN, SETUP, and OUT token PIDs only. Table 5-70. Endpoint Field
Bit 0 1 2 3 Data Sent ENDP 0 ENDP 1 ENDP 2 ENDP 3
5.16.4.5
Frame Number Field
The frame number field is an 11-bit field that is incremented by the host on a per frame basis. The frame number field rolls over upon reaching its maximum value of x7FFh and is sent only for SOF tokens at the start of each frame.
5.16.4.6
Data Field
The data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. Data bits within each byte are shifted out LSB first.
5.16.4.7
Cyclic Redundancy Check (CRC)
CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields are considered to be protected fields. The PID is not included in the CRC check of a packet containing CRC. All CRCs are generated over their respective fields in the transmitter before bit stuffing is performed. Similarly, CRCs are decoded in the receiver after stuffed bits have been removed. Token and data packet CRCs provide 100% coverage for all single and double bit errors. A failed CRC is considered to indicate that one or more of the protected fields is corrupted and causes the receiver to ignore those fields, and, in most cases, the entire packet.
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5.16.5
5.16.5.1
Packet Formats
Token Packets
Table 5-71 shows the field formats for a token packet. A token consists of a PID, specifying either IN, OUT, or SETUP packet type, and ADDR and ENDP fields. For OUT and SETUP transactions, the address and endpoint fields uniquely identify the endpoint that will receive the subsequent data packet. For IN transactions, these fields uniquely identify which endpoint should transmit a data packet. Only the ICH2 can issue token packets. IN PIDs define a data transaction from a function to the ICH2. OUT and SETUP PIDs define data transactions from the ICH2 to a function. Token packets have a five-bit CRC that covers the address and endpoint fields as shown above. The CRC does not cover the PID, which has its own check field. Token and SOF packets are delimited by an EOP after three bytes of packet field data. If a packet decodes as an otherwise valid token or SOF but does not terminate with an EOP after three bytes, it must be considered invalid and ignored by the receiver.
Table 5-71. Token Format
Packet PID ADDR ENDP CRC5 Width 8 bits 7 bits 4 bits 5 bits
5.16.5.2
Start of Frame Packets
Table 5-72 shows a start of frame (SOF) packet. SOF packets are issued by the host at a nominal rate of once every 1.00 ms. SOF packets consist of a PID indicating packet type followed by an 11bit frame number field. The SOF token comprises the token-only transaction that distributes a start of frame marker and accompanying frame number at precisely timed intervals corresponding to the start of each frame. All full speed functions, including hubs, must receive and decode the SOF packet. The SOF token does not cause any receiving function to generate a return packet; therefore, SOF delivery to any given function cannot be guaranteed. The SOF packet delivers two pieces of timing information. A function is informed that a start of frame has occurred when it detects the SOF PID. Frame timing sensitive functions, that do not need to keep track of frame number, need only decode the SOF PID; they can ignore the frame number and its CRC. If a function needs to track frame number, it must comprehend both the PID and the time stamp.
Table 5-72. SOF Packet
Packet PID Frame Number CRC5 Width 8 bits 11 bits 5 bits
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Functional Description
5.16.5.3
Data Packets
A data packet consists of a PID, a data field, and a CRC as shown in Table 5-73. There are two types of data packets identified by differing PIDs: DATA0 and DATA1. Two data packet PIDs are defined to support data toggle synchronization. Data must always be sent in integral numbers of bytes. The data CRC is computed over only the data field in the packet and does not include the PID, which has its own check field.
Table 5-73. Data Packet Format
Packet PID DATA CRC16 Width 8 bits 0–1023 bytes 16 bits
5.16.5.4
Handshake Packets
Handshake packets consist of only a PID. Handshake packets are used to report the status of a data transaction and can return values indicating successful reception of data, flow control, and stall conditions. Only transaction types that support flow control can return handshakes. Handshakes are always returned in the handshake phase of a transaction and may be returned, instead of data, in the data phase. Handshake packets are delimited by an EOP after one byte of packet field. If a packet is decoded as an otherwise valid handshake but does not terminate with an EOP after one byte, it must be considered invalid and ignored by the receiver. There are three types of handshake packets:
• ACK indicates that the data packet was received without bit stuff or CRC errors over the data
field and that the data PID was received correctly. An ACK handshake is applicable only in transactions in which data has been transmitted and where a handshake is expected. ACK can be returned by the host for IN transactions and by a function for OUT transactions.
• NAK indicates that a function was unable to accept data from the host (OUT) or that a
function has no data to transmit to the host (IN). NAK can only be returned by functions in the data phase of IN transactions or the handshake phase of OUT transactions. The host can never issue a NAK. NAK is used for flow control purposes to indicate that a function is temporarily unable to transmit or receive data, but will eventually be able to do so without need of host intervention. NAK is also used by interrupt endpoints to indicate that no interrupt is pending.
• STALL is returned by a function in response to an IN token or after the data phase of an OUT.
STALL indicates that a function is unable to transmit or receive data, and that the condition requires host intervention to remove the stall. Once a function’s endpoint is stalled, the function must continue returning STALL until the condition causing the stall has been cleared through host intervention. The host is not permitted to return a STALL under any condition.
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5.16.5.5
Handshake Responses
IN Transaction
A function may respond to an IN transaction with a STALL or NAK. If the token received was corrupted, the function issues no response. If the function can transmit data, it issues the data packet. The ICH2, as the USB host, can return only one type of handshake on an IN transaction, an ACK. If it receives a corrupted data or cannot accept data due to a condition such as an internal buffer overrun, it discards the data and issues no response.
OUT Transaction
A function may respond to an OUT transaction with a STALL, ACK, or NAK. If the transaction contained corrupted data, it will issue no response.
SETUP Transaction
Setup defines a special type of host to function data transaction which permits the host to initialize an endpoint’s synchronization bits to those of the host. Upon receiving a Setup transaction, a function must accept the data. Setup transactions cannot be STALLed or NAKed and the receiving function must accept the Setup transfer’s data. If a non-control endpoint receives a SETUP PID, it must ignore the transaction and return no response.
5.16.6
USB Interrupts
There are two general groups of USB interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from an ICH2 operation error. All transactionbased sources can be masked by software through the ICH2’s Interrupt Enable register. Additionally, individual transfer descriptors can be marked to generate an interrupt on completion. When the ICH2 drives an interrupt for USB, it drives the PIRQD# pin active for interrupts occurring due to ports 0 and 1 until all sources of the interrupt are cleared.
5.16.6.1
Transaction Based Interrupts
These interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. This guarantees that software can safely process through (Frame List Current Index -1) when it is servicing an interrupt.
CRC Error / Time-out
A CRC/Time-out error occurs when a packet transmitted from the ICH2 to a USB device or a packet transmitted from a USB device to the ICH2 generates a CRC error. The ICH2 is informed of this event by a time-out from the USB device or by the ICH2’s CRC checker generating an error on reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not respond to a transaction phase within 19 bit times of an EOP. Either of these conditions will cause the C_ERR field of the TD to decrement. When the C_ERR field decrements to zero, the following occurs:
• • • •
The Active bit in the TD is cleared The Stalled bit in the TD is set The CRC/Time-out bit in the TD is set. At the end of the frame, the USB Error Interrupt bit is set in the HC status register.
If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware interrupt is signaled to the system.
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Functional Description
Interrupt on Completion
Transfer Descriptors contain a bit that can be set to cause an interrupt on their completion. The completion of the transaction associated with that block causes the USB Interrupt bit in the HC Status Register to be set at the end of the frame in which the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit in the HC Status register is set to 1 at the end of the frame if the active bit in the TD is set to 0 (even if it was set to zero when initially read). If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a hardware interrupt is signaled to the system. The USB Interrupt bit in the HC Status register is set either when the TD completes successfully or because of errors. If the completion is because of errors, the USB Error bit in the HC Status register is also set.
Short Packet Detect
A transfer set is a collection of data which requires more than 1 USB transaction to completely move the data across the USB. An example might be a large print file which requires numerous TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion of the transfer set, even if there are active TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to set the USB Interrupt bit in the HC Status register at the end of the frame in which this event occurs. This feature streamlines the processing of input on these transfer types. If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred.
Serial Bus Babble
When a device transmits on the USB for a time greater than its assigned Max Length, it is said to be babbling. Since isochrony can be destroyed by a babbling device, this error results in the Active bit in the TD being cleared to 0 and the Stalled and Babble bits being set to one. The C_ERR field is not decremented for a babble. The USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware interrupt is signaled to the system. If an EOF babble was caused by the ICH2 (due to incorrect schedule for instance), the ICH2 forces a bit stuff error followed by an EOP and the start of the next frame.
Stalled
This event indicates that a device/endpoint returned a STALL handshake during a transaction or that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is signaled to the system.
Data Buffer Error
This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. This would generally be caused by the ICH2 not being able to access required data buffers in memory within necessary latency requirements. Either of these conditions causes the C_ERR field of the TD to be decremented. When C_ERR decrements to zero, the Active bit in the TD is cleared, the Stalled bit is set, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
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Bit Stuff Error
A bit stuff error results from the detection of a sequence of more that 6 ones in a row within the incoming data stream. This will cause the C_ERR field of the TD to be decremented. When the C_ERR field decrements to zero, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
5.16.6.2
Non-Transaction Based Interrupts
If an ICH2 process error or system error occur, the ICH2 halts and immediately issues a hardware interrupt to the system.
Resume Received
This event indicates that the ICH2 received a RESUME signal from a device on the USB bus during a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware interrupt will be signaled to the system allowing the USB to be brought out of the suspend state and returned to normal operation.
ICH2 Process Error
The HC monitors certain critical fields during operation to ensure that it does not process corrupted data structures. These include checking for a valid PID and verifying that the MaxLength field is less than 1280. If it detects a condition that would indicate that it is processing corrupted data structures, it immediately halts processing, sets the HC Process Error bit in the HC Status Register and signals a hardware interrupt to the system. This interrupt cannot be disabled through the Interrupt Enable Register.
Host System Error
The ICH2 sets this bit to 1 when a PCI Parity error, PCI Master Abort, or PCI Target Abort occurs. When this error occurs, the ICH2 clears the Run/Stop bit in the Command Register to prevent further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt Enable Register.
5.16.7
USB Power Management
The Host Controller can be put into a suspended state and its power can be removed. This requires that certain bits of information are retained in the resume power plane of the ICH2 so that a device on a port may wake the system. Such a device may be a fax-modem, that wakes up the machine to receive a fax or takes a voice message. The settings of the following bits in I/O space is maintained when the ICH2 enters the S3, S4 or S5 states.
Table 5-74. Bits maintained in low power states
Register Command Status Port Status and Control Offset 00h 02h 10h & 12h Bit 3 2 2 6 8 12 Description Enter Global Suspend Mode (EGSM) Resume Detect Port Enabled/Disabled Resume Detect Low Speed Device Attached Suspend
When the ICH2 detects a resume event on any of its ports, it sets the corresponding USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system wakes up and an SCI is generated.
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Functional Description
5.16.8
USB Legacy Keyboard Operation
When a USB keyboard is plugged into the system and a standard keyboard is not, the system may not boot and DOS legacy software will not run; this is because the keyboard is not identified. The ICH2 implements a series of trapping operations which snoop accesses that go to the keyboard controller and put the expected data from the USB keyboard into the keyboard controller.
Note:
The scheme described below assumes that the keyboard controller (8042 or equivalent) is on the LPC bus. This legacy operation is performed through SMM space. Figure 5-19 shows the Enable and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the Status Register. Because the enable is after the latch, it is possible to check for other events that didn't necessarily cause an SMI. It is the software's responsibility to logically AND the value with the appropriate enable bits. Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY# goes active) to ensure that the processor does not complete the cycle before the SMI is observed. This method is used on MPIIX and has been validated. The logic will also need to block the accesses to the 8042. If there is an external 8042, this is accomplished by not activating the 8042 CS. This is done by logically ANDing the 4 enables (60R, 60W, 64R, 64W) with the 4 types of accesses to determine if the 8042CS should go active. An additional term is required for the “Pass-through” case. The state table for the diagram is shown in Table 5-75.
Figure 5-19. USB Legacy Keyboard Flow Diagram
To Individual
KBC Accesses 60 READ S Clear SMI_60_R PCI Config Read, Write Comb. Decoder R EN_SMI_ON_60R D AND
"Caused By" "Bits"
SMI Same for 60W, 64R, 64W
OR
EN_PIRQD# AND
To PIRQD# To "Caused By" Bit
USB_IRQ S Clear USB_IRQ R EN_SMI_ON_IRQ D AND
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Table 5-75. USB Legacy Keyboard State Transitions
Current State IDLE IDLE IDLE IDLE IDLE Action 64h / Write 64h / Write 64h / Read 60h / Write 60h / Read Data Value D1h Not D1h N/A Don't Care N/A Next State GateState1 IDLE IDLE IDLE IDLE Comment Standard D1 command. Cycle passed through to 8042. SMI# doesn't go active. PSTATE goes to 1. Bit 3 in configuration Register determines if cycle passed through to 8042 and if SMI# generated. Bit 2 in configuration Register determines if cycle passed through to 8042 and if SMI# generated. Bit 1 in configuration Register determines if cycle passed through to 8042 and if SMI# generated. Bit 0 in configuration Register determines if cycle passed through to 8042 and if SMI# generated. Cycle passed through to 8042, even if trap enabled in Bit 1 in configuration Register. No SMI# generated. PSTATE remains 1. If data value is not DFh or DDh then the 8042 may chose to ignore it. Cycle passed through to 8042, even if trap enabled via Bit 3 in configuration Register. No SMI# generated. PSTATE remains 1. Stay in GateState1 because this is part of the doubletrigger sequence. Bit 3 in configuration space determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in configuration Register is set, then SMI# should be generated. This is an invalid sequence. Bit 0 in configuration Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in configuration Register is set, then SMI# should be generated. Just stay in same state. Generate an SMI# if enabled in Bit 2 of configuration Register. PSTATE remains 1. Standard end of sequence. Cycle passed through to 8042. PSTATE goes to 0. Bit 7 in configuration Space determines if SMI# should be generated. Improper end of sequence. Bit 3 in configuration Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in configuration Register is set, then SMI# should be generated. Just stay in same state. Generate an SMI# if enabled in Bit 2 of configuration Register. PSTATE remains 1. Improper end of sequence. Bit 1 in configuration Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in configuration Register is set, then SMI# should be generated. Improper end of sequence. Bit 0 in configuration Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in configuration Register is set, then SMI# should be generated.
GateState1
60h / Write
XXh
GateState2
GateState1
64h / Write
D1h
GateState1
GateState1
64h / Write
Not D1h
ILDE
GateState1
60h / Read
N/A
IDLE
GateState1
64h / Read
N/A
GateState1
GateState2
64 / Write
FFh
IDLE
GateState2
64h / Write
Not FFh
IDLE
GateState2
64h / Read
N/A
GateState2
GateState2
60h / Write
XXh
IDLE
GateState2
60h / Read
N/A
IDLE
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Functional Description
5.17
SMBus Controller Functional Description (D31:F3)
The ICH2 provides an SMBus Host Controller as well as an SMBus Slave Interface. The Host Controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The ICH2 is also capable of operating in a mode in which it can communicate with I2C compatible devices. The Slave Interface allows an external master to read from or write to the ICH2. Write cycles can be used to cause certain events or pass messages and the read cycles can be used to determine the state of various status bits. The ICH2’s internal Host Controller cannot access the ICH2’s internal Slave Interface. The ICH2 SMBus logic exists in Device 31:Function 3 configuration space and consists of a transmit data path and host controller. The transmit data path provides the data flow logic needed to implement the seven different SMBus command protocols and is controlled by the host controller. The ICH2 SMBus controller logic is clocked by RTC clock. The programming model of the host controller is combined into two portions: a PCI configuration portion and a system I/O mapped portion. All static configuration (e.g., the I/O base address) is done via the PCI configuration space. Real-time programming of the Host interface is done in system I/O space.
5.17.1
Host Controller
The SMBus Host Controller is used to send commands to other SMBus slave devices. Software sets up the host controller with an address, command, and, for writes, data, and then tells the controller to start. When the controller has finished transmitting data on writes, or receiving data on reads, it will generate an SMI# or interrupt, if enabled. The host controller supports 7 command protocols of the SMBus interface (see System Management Bus Specification, Rev 1.0): Quick Command, Send Byte, Receive Byte, Write Byte/ Word, Read Byte/Word, Process Call, and Block Read/Write. The SMBus Host Controller requires that the various data and command fields be setup for the type of command to be sent. When software sets the START bit, the SMBus Host Controller performs the requested transaction and interrupts the processor (or generate an SMI#) when the transaction is completed. Once a START command has been issued, the values of the “active registers” (Host Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read until the interrupt status bit (INTR) has been set (indicating the completion of the command). Any register values needed for computation purposes should be saved prior to issuing of a new command, as the SMBus Host Controller will update all registers while completing the new command. Using the SMB Host Controller to send commands to the ICH2's SMB slave port is not supported.
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5.17.1.1
Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to determine the progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the command completes successfully, the INTR bit is set in the Host Status Register. If the device does not respond with an acknowledge and the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the Host Control Register while the command is running, the transaction will stop and the FAILED bit will be set.
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent. The format of the protocol is shown in Table 5-76. Table 5-76. Quick Protocol
Bit 1 2:8 9 10 11 Description Start Condition Slave Address - 7 bits Read / Write Direction Acknowledge from slave Stop
Send Byte / Receive Byte
For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is stored in the DATA0 register. The Receive Byte is similar to a Send Byte; the only difference is the direction of data transfer. The format of the protocol is shown in Table 5-77. Table 5-77. Send / Receive Byte Protocol
Send Byte Protocol Bit 1 2:8 9 10 11:18 19 20 Start Slave Address - 7 bits Write Acknowledge from slave Command code - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 Start Slave Address - 7 bits Read Acknowledge from slave Data byte from slave NOT Acknowledge Stop Receive Byte Protocol Description
Write Byte/Word
The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data to be written. When programmed for a write byte/word command, the Transmit Slave Address, Device Command and Data0 Registers are sent. In addition, the Data1 Register is sent on a write word command. The format of the protocol is shown in Table 5-78.
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Table 5-78. Write Byte/Word Protocol
Write Byte Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29 Start Slave Address - 7 bits Write Acknowledge from slave Command code - 8 bits Acknowledge from slave Data Byte - 8 bits Acknowledge from Slave Stop Description Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38 Start Slave Address - 7 bits Write Acknowledge from slave Command code - 8 bits Acknowledge from slave Data Byte Low - 8 bits Acknowledge from Slave Data Byte High - 8 bits Acknowledge from slave Stop Write Word Protocol Description
Read Byte/Word
Reading data is slightly more complicated than writing data. First the ICH2 must write a command to the slave device. Then it must follow that command with a repeated start condition to denote a read from that device's address. The slave then returns 1 or 2 bytes of data. When programmed for the read byte/word command, the Transmit Slave Address and Device Command Registers are sent. Data is received into the DATA0 on the read byte, and the DAT0 and DATA1 registers on the read word. The format of the protocol is shown in Table 5-79. Table 5-79. Read Byte/Word Protocol
Read Byte Protocol Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Start Slave Address - 7 bits Write Acknowledge from slave Command code - 8 bits Acknowledge from slave Repeated Start Slave Address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT acknowledge Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48 Start Slave Address - 7 bits Write Acknowledge from slave Command code - 8 bits Acknowledge from slave Repeated Start Slave Address - 7 bits Read Acknowledge from slave Data Byte Low from slave - 8 bits Acknowledge Data Byte High from slave - 8 bits NOT acknowledge Stop Read Word Protocol Description
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Process Call
The process call is so named because a command sends data and waits for the slave to return a value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition. When programmed for the Process Call command, the ICH2 transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers. The format of the protocol is shown in Table 5-80. Note: For process call command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0.
Table 5-80. Process Call Protocol
Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38 39:45 46 47 48:55 56 57:64 65 66 Start Slave Address - 7 bits Write Acknowledge from Slave Command code - 8 bits Acknowledge from slave Data byte Low - 8 bits Acknowledge from slave Data Byte High - 8 bits Acknowledge from slave Repeated Start Slave Address - 7 bits Read Acknowledge from slave Data Byte Low from slave - 8 bits Acknowledge Data Byte High from slave - 8 bits NOT acknowledge Stop Description
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Block Read/Write
The Block Write begins with a slave address and a write condition. After the command code, the ICH2 issues a byte count which describes how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. Note that, unlike the PIIX4, which implements 32-byte buffer for Block Read/Write command, the ICH2 implements the Block Data Byte register (D31:F3, I/O offset 07h) for Block Read/Write command. When programmed for a block write command, the Transmit Slave Address, Host Command, and Data0 (count) registers are sent. Data is then sent from the Block Data Byte register. After the byte has been sent, the ICH2 sets the BYTE_DONE_STS bit in the Host Status register. If there are more bytes to send, software writes the next byte to the Block Data Byte register and also clears the BYTE_DONE_STS bit. The ICH2 then sends the next byte. When doing a block write, first poll the BYTE_DONE_STS register until it is set, then write the next byte, then clear the BYTE_DONE_STS register. On block read commands, after the byte count is stored in the DATA 0 register, the first data byte goes in the Block Data Byte Register; the ICH2 will then set the BYTE_DONE_STS bit and generate an SMI# or interrupt. The SMI# or interrupt handler reads the byte and then clears the BYTE_DONE_STS bit to allow the next byte to be read into the Block Data Byte register. Note that after receiving data byte N-1 of the block, the software needs to set the LAST_BYTE bit in the Host Control Register; this allows the ICH2 to send a NOT ACK (instead of an ACK) after receiving the last data byte (byte N) of the block. After each byte of a block message the ICH2 sets the BYTE_DONE_STS bit and generates an interrupt or SMI#. Software clears the BYTE_DONE_STS bit before the next transfer occurs. When the interrupt handler clears the BYTE_DONE_STS bit after the last byte has been transferred, the ICH2 sets the INTR bit and generates another interrupt to signal the end of the block transfer. Thus, for a block message of n bytes, the ICH2 generates n+1 interrupts. The interrupt handler needs to be implemented to handle all of these interrupts The format of the Block Read/Write protocol is shown in Table 5-81. Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly. The ICH2 still sends the number of bytes indicated in the DATA0 register. However, it does not send the contents of the Data 0 register as part of the message.
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l
Table 5-81. Block Read/Write Protocol
Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 ... ... ... ... Start Slave Address - 7 bits Write Acknowledge from slave Command code - 8 bits Acknowledge from slave Byte Count - 8 bits (Skip this step if I2C_En bit set) Acknowledge from Slave (Skip this step if I2C_EN bit set) Data Byte 1 - 8 bits Acknowledge from Slave Data Byte 2–8 bits Acknowledge from slave Data Bytes / Slave Acknowledges... Data Byte N - 8 bits Acknowledge from Slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 ... ... ... ... Start Slave Address - 7 bits Write Acknowledge from slave Command code - 8 bits Acknowledge from slave Repeated Start Slave Address - 7 bits Read Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data Byte 1 from slave - 8 bits Acknowledge Data Byte 2 from slave - 8 bits Acknowledge Data Bytes from slave/Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Stop Block Read Protocol Description
I2C Read This command allows the ICH2 to perform block reads to certain I2C devices (e.g., serial E2PROMs). The SMBus Block Read sends both the 7-bit address, as well as the Command field. This command field could be used as the extended 10-bit address for accessing I2C devices that use 10-bit addressing. However, this does not allow access to devices using the I2C “Combined Format” that has data bytes after the address. Typically, these data bytes correspond to an offset (address) within the serial memory chips. Note: This new command is supported independent of the setting of the I2C_EN bit. For I2C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. The format that is used for the new command is shown in Table 5-82:
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Table 5-82. I2C Block Read
Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38 39:45 46 47 48:55 56 57:64 65 Start Slave Address - 7 bits Write Acknowledge from slave Command code - 8 bits Acknowledge from slave Send DATA0 register Acknowledge from slave Send DATA1 register Acknowledge from slave Repeated start Slave Address - 7 bits Read Acknowledge from slave Data byte from slave Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data byte N from slave - 8 bits NOT Acknowledge Stop Description
The ICH2 continues reading data from the peripheral until the NAK is received.
5.17.1.2
I2C Behavior
When the I2C_EN bit is set, the ICH2 SMBus logic is instead set to communicate with I2C devices. This forces the following changes: 1. The Process Call command will skip the Command code (and its associated acknowledge) 2. The Block Write command will skip sending the Byte Count (DATA0) In addition, the ICH2 supports the new I2C Read command. This is independent of the I2C_EN bit.
5.17.1.3
Heartbeat for Use With the External LAN Controller
This method allows the ICH2 to send messages to an external LAN Controller when the processor is otherwise unable to do so. It uses the SMLINK I/F between the ICH2 and the external LAN Controller. The actual Heartbeat message is a Block Write. Only 8 bytes are sent.
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5.17.2
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low to signal a start condition. The ICH2 continuously monitors the SMBDATA line. When the ICH2 is attempting to drive the bus to a 1 by letting go of the SMBDATA line and it samples SMBDATA low, then some other master is driving the bus and the ICH2 stops transferring data. If the ICH2 sees that it has lost arbitration, the condition is called a collision. The ICH2 sets the BUS_ERR bit in the Host Status Register, and, if enabled, generates an interrupt or SMI#. The processor is responsible for restarting the transaction. When the ICH2 is a SMBus master, it drives the clock. When the ICH2 is sending address or command as an SMBus master or data bytes as a master on writes, it drives data relative to the clock it is also driving. It does not start toggling the clock until the start or stop condition meets proper setup and hold time. The ICH2 also guarantees minimum time between SMBus transactions as a master. The ICH2 supports the same arbitration protocol for both the SMBus and the System Management (SMLINK) interfaces.
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the ICH2, as an SMBus master, would like. They have the capability of stretching the low time of the clock. When the ICH2 attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. The ICH2 monitors the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. While the bus is still low, the high time counter must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data. The ICH2 SMBus Host Controller will never stretch the low period of the clock (SMBCLK). It always has the data to transfer on writes and it always has a spot for the data on reads. The SMLINK interface, however, always stretches the low period of the clock, effectively forcing transfers down to 16 KHz.
Bus Time Out (ICH2 as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an acknowledge or holds the clock lower than the allowed time-out time, the transaction times out. The ICH2 discards the cycle and sets the DEV_ERR bit. The time-out minimum is 25 ms. The time-out counter inside the ICH2 starts after the last bit of data is transferred by the ICH2 and it is waiting for a response. The 25 ms is a count of 800 RTC clocks.
5.17.3
Interrupts / SMI#
The ICH2 SMBus controller uses PIRQB# as its interrupt pin. However, the system can alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN bit.
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5.17.4
SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enabled and the signal is asserted, the ICH2 can generate an interrupt, an SMI#, or a wake event from S1-S4. To resume using SMBALERT#, the SMB_SMI_EN bit must be enabled to generate an SMI (see Section 12.1.14, “HOSTC—Host Configuration Register (SMBUS—D31:F3)” on page 12-5).
Note:
As long as SMBALERT# is enabled and asserted, the ICH2 will continue to assert PIRQ[B]# or SMI# (depending on the state of the SMB_SMI_EN bit). To avoid continuous SMIs or interrupts, the interrupt or SMI handler should: 1. Disable SMBALERT# by setting GPIO_USE_SEL[11] (GPIOBase + 00h, bit 11) 2. Use the SMBus Host Controller to service the peripheral that is asserting SMBALERT# (causing the device to deassert the signal) 3. Re-enable SMBALERT# by clearing GPIO_USE_SEL[11].
5.17.5
SMBus Slave Interface
The ICH2’s SMBus Slave interface is accessed via the SMLINK[1:0] signals. The slave interface allows the ICH2 to decode cycles and allows an external microcontroller to perform specific actions. Key features and capabilities include:
• Supports decode of two messages type: Write and Read • Receive Slave Address register: This is the address that the ICH2 decodes. A default value is
provided so that the slave interface can be used without the processor having to program this register.
• Receive Slave Data register in the SMBus I/O space that includes the data written by the
external microcontroller
• Registers that the external microcontroller can read to get the state of the ICH2. See Table 5-87 • Status bit to indicate that the SMBus logic caused an SMI# due to the reception of a message
that matched the slave address. See Section 9.8.3.14.
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Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH2 SMBus Slave I/F. The “Command” field (bits 11-18) indicate which register is being accessed. The Data field (bits 20-27) indicate the value that should be written to that register. The Write Cycle format is shown in Table 5-83. Table 5-84 lists the values associated with the registers. Table 5-83. Slave Write Cycle Format
Bits 1 2:8 9 10 Description Start Condition Slave Address - 7 bits Write ACK Driven by External Microcontroller External Microcontroller External Microcontroller ICH2 This field indicates which register will be accessed. See Table 5-84 below for the register definitions Must match value in Receive Slave Address register Always 0 Comment
11:18
Command
External Microcontroller
19 20:27 28 29
ACK Register Data ACK Stop
ICH2 External Microcontroller ICH2 External Microcontroller See Table 5-84 below for the register definitions
Table 5-84. Slave Write Registers
Register 0 1–3 4 5 6–7 8 9–FFh Function Command Register. See Table 65 below for legal values written to this register. Reserved Data Message Byte 0 Data Message Byte 1 Reserved Frequency Straps will be written on bits 3:0. Bits 7:4 should be 0, but will be ignored. Reserved
NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. The ICH2 overwrites the old value with any new value received. A race condition is possible where the new value is being written to the register just at the time it is being read. ICH2 will not attempt to cover this race condition (i.e., unpredictable results in this case).
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Table 5-85. Command Types
Command Type 0 Reserved WAKE/SMI#: Wake system if it is not already awake. If the system is already awake, an SMI# is generated. Note that the SMB_WAK_STS bit will be set by this command, even if the system is already awake. The SMI handler should then clear this bit. Unconditional Powerdown: This command sets the PWRBTNOR_STS bit and has the same effect as the Powerbutton Override occurring. This functionality depends upon the BIOS having cleared the PWRBTN_STS bit. Hard Reset without Cycling: This causes a hard reset of the system (does not include cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0. Hard Reset System: This causes a hard reset of the system (including cycling of the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1. Disable the TCO Messages. This command disables the ICH2 from sending Heartbeat and Event messages (as described in Section 5.13.2). Once this command has been executed, Heartbeat and Event message reporting can only be re-enabled by assertion and deassertion of the RSMRST# signal. WD RELOAD: Reload watchdog timer. Reserved Description
1
2
3
4
5
6 7–FFh
Format of Read Command
The external master performs Byte Read commands to the ICH2 SMBus Slave interface. The “Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register. Table 5-86 shows the Read Cycle format. Table 5-87 shows the register mapping for the data byte. Table 5-86. Read Cycle Format
Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Start Slave Address - 7 bits Write ACK Command code – 8 bits ACK Repeated Start Slave Address - 7 bits Read ACK Data Byte NOT ACK Stop Description Driven by External Microcontroller External Microcontroller External Microcontroller ICH2 External Microcontroller ICH2 External Microcontroller External Microcontroller External Microcontroller ICH2 ICH2 External Microcontroller ICH2 Value depends on register being accessed. See Table 5-87. Must match value in Receive Slave Address register Always 1 Indicates which register is being accessed. See Table 5-87. Must match value in Receive Slave Address register Always 0 Comment
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Table 5-87. Data Values for Slave Read Registers
Register 0 1 1 2 2 3 3 4 4 4 4 4 4 5 5 6 7 8 9–FFh Bits 7:0 2:0 7:3 3:0 7:4 5:0 7:6 0 1 2 3 6:4 7 0 7:1 7:0 7:0 7:0 7:0 Reserved. System Power State 000 = S0 001 = S1 010 = Reserved 011 = S3 100 = S4 101 = S5 110 = Reserved 111 = Reserved Reserved Frequency Strap Register Reserved Watchdog Timer current value Reserved 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. 1 = BTI Temperature Event occurred. This bit is set if the ICH2’s THRM# input signal is active. Need to take after polarity control. DOA processor status. This bit is 1 to indicate that the processor is dead. 1 = Watchdog timer expired. This bit is set if the ICH2’s TCO timers have timed out. Reserved. Will reflect the state of the ICH2’s GPIO[11]. Unprogrammed FWH bit. This bit will be 1 to indicate that the first BIOS fetch returned FFh, which indicates that the FWH is probably blank. Reserved Contents of the Message 1 register. See Section 9.9.10. Contents of the Message 2 register. See Section 9.9.10. Contents of the WDSTATUS register. See Section 9.9.11. Reserved Description
Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit - Address - Write bit sequence. When the ICH2 detects that the address matches the value in the Receive Slave Address register, it assumes that the protocol is always followed and ignores the Write bit (bit 9) and signal an Acknowledge during bit 10 (See Table 5-83 and Table 5-86). In other words, if a Start - Address - Read occurs (which is illegal for SMBus Read or Write protocol), and the address matches the ICH2’s Slave Address, the ICH2 will still grab the cycle. Also according to SMBus protocol, a Read cycle contains a Repeated Start - Address - Read sequence beginning at bit 20 (See Table 5-86). Once again, if the Address matches the ICH2’s Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Slave Read cycle. Note: An external microcontroller must not attempt to access the ICH2’s SMBus Slave logic until at least 1 second after both RTCRST# and RSMRST# are deasserted (high).
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5.18
Note:
AC’97 Controller Functional Description (Audio D31:F5, Modem D31:F6)
All references to AC’97 in this document refer to the AC’97 2.1 specification. For further information on the operation of the AC-link protocol, see the AC’97 specification. The ICH2 AC ‘97 Controller features include:
• Independent PCI functions for audio and modem. • Independent bus master logic for Mic input, PCM Audio input (2-channel stereo), PCM audio
output (2, 4 or 6-channel stereo), Modem input and Modem output.
• • • • •
.
16 bit sample resolution Multiple sample rates up to 48 KHz 16 GPIOs Single modem line Dual codec configuration with two SDIN pins
Table 5-88 shows a detailed list of features supported by the ICH2 AC’97 digital controller. Table 5-88. Featured Supported by ICH2
Feature Description • Isochronous low latency bus master memory interface • Scatter/gather support for word-aligned buffers in memory (all mono or stereo 16-bit data types are supported, no 8-bit data types are supported) • Data buffer size in system memory from 3 to 65535 samples per input System Interface • Data buffer size in system memory from 0 to 65535 samples per output • Independent PCI audio and modem functions with configuration and IO spaces • AC’97 codec registers are shadowed in system memory via driver (not PCI IO space) • AC’97 codec register accesses are serialized via semaphore bit in PCI IO space (new accesses are not allowed while a prior access is still in progress) • Power management via ACPI control methods Support for audio states: D0, D2, D3hot, D3cold Support for modem states: D0, D3hot, D3cold • SCI event generation for PCI modem function with wake-up from D3cold • Independent codec D3 w/ Link down event, synchronized via two bit semaphore (in PCI IO Space) • Read/write access to audio codec registers 00h-3Ah and vendor registers 5Ah–7Eh • 16-bit stereo PCM output, up to 48 kHz (L,R, Center, Sub-woofer, L-rear and R-rear channels on slots 3,4,6,7,8.9) • 16-bit stereo PCM input, up to 48 kHz (L,R channels on slots 3,4) PCI Audio Function • 16-bit mono mic in w/ or w/o mono mix, up to 48 kHz (L,R channel, slots 3,4) (mono mix supports mono hardware AEC reference for speakerphone) • 16-bit mono PCM input, up to 48 kHz from dedicated mic ADC (slot 6) (supports speech recognition or stereo hardware AEC ref for speakerphone) • During cold reset AC_RST# is held low until after POST and software deassertion of AC_RST# (supports passive PC_BEEP to speaker connection during POST)
Power Management
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Table 5-88. Featured Supported by ICH2 (Continued)
Feature Description • Read/write access to modem codec registers 3Ch-58h and vendor registers 5Ah–7Eh • 16-bit mono modem line1 output and input, up to 48 kHz (slot 5) PCI Modem function • Low latency GPIO[13:11,8:6,4:3,1:0] (GPIO[13:11,8:7,4:3,1:0] for the ICH2-M) via hardwired update between slot 12 and PCI IO register • Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT • SCI event generation on primary or secondary SDIN wake-up signal • AC’97 2.1 compliant AC-link interface • Variable sample rate output support via AC’97 SLOTREQ protocol (slots 3,4,5,6,7,8,9) AC-link • Variable sample rate input support via monitoring of slot valid tag bits (slots 3,4,5,6) • 3.3 V digital operation meets AC’97 2.1 DC switching levels • AC-Link IO driver capability meets AC‘97 2.1 dual codec specifications • Codec register status reads must be returned with data in the next AC-link frame, per AC’97 2.1 specification. • Dual codec addressing: All AC’97 codec register accesses are addressable to codec ID 00 (primary) or codec ID 01 (secondary) • Dual codec receive capability via primary and secondary SDIN pins (primary, secondary SDIN frames are internally validated, synchronized, and OR’d)
Multiple Codec
Note:
Throughout this document, references to D31:F5 indicate that the audio function exists in PCI Device 31, Function 5. References to D31:F6 indicate that the modem function exists in PCI Device 31, Function 6.
Figure 5-20. ICH2 Based AC’97 2.1
Audio In (Record)
PC
Audio Out (Playback) Modem Mic.
5.18.1
AC-link Overview
The ICH2 is an AC’97 2.1 compliant controller that communicates with companion codecs via a digital serial link called the AC-link. All digital audio/modem streams and command/status information is communicated over the AC-link. The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data streams, as well as control register accesses, employing a time division multiplexed (TDM) scheme. The AC-link architecture provides for data transfer through individual frames transmitted in a serial fashion. Each frame is divided into 12 outgoing and 12 incoming data streams, or slots. The architecture of the ICH2 AC-link allows a maximum of two codecs to be connected. Figure 5-21 shows a two codec topology of the AC-link for the ICH2.
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Figure 5-21. AC’97 2.1 Controller-Codec Connection
Digital AC '97 2.1 Controller
RESET# AC '97 2.1 controller section of the ICH2 SDIN 0 SDIN 1 SDOUT SYNC BIT_CLK Primary Codec
AC '97 / AC' 97 2.1 / AMC '97 2.1
AC '97 / MC '97 2.1 / AMC '97 2.1
Secondary Codec
The AC-link consists of a five signal interface between the controller and codec. Table 5-89 indicates the AC-link signal pins on the ICH2 and their associated power wells. Table 5-89. AC’97 Signals
Signal Name AC_RESET# AC_SYNC AC_BIT_CLK AC_SDOUT AC_SDIN 0 AC_SDIN 1 Type Output Output Input Output Input Input Power Well* Resume Core Core Core Resume Resume Description Master hardware reset 48 KHz fixed rate sample sync 12.288 MHz Serial data clock Serial output data Serial input data Serial input data
NOTE: Power well voltage levels are 3.3V
ICH2 core well outputs may be used as strapping options for the ICH2, sampled during system reset. These signals may have weak pull-ups/put-downs; however, this will not interfere with link operation. ICH2 inputs integrate weak put-downs to prevent floating traces when a secondary codec is not attached. When the Shut Off bit in the control register is set, all buffers will be turned off and the pins will be held in a steady state, based on these pull-ups/put-downs. BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the necessary clocking to support the twelve 20 bit time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link data samples each serial bit on the falling edge of BIT_CLK. Synchronization of all AC-link data transactions is signaled by the AC’97 controller via the AC_SYNC signal, as shown in Figure 5-22. The primary codec drives the serial bit clock onto the AC-link, which the AC’97 controller then qualifies with the AC_SYNC signal to construct data frames. AC_SYNC, fixed at 48 KHz, is derived by dividing down BIT_CLK. AC_SYNC remains
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high for a total duration of 16 BIT_CLKs at the beginning of each frame. The portion of the frame where AC_SYNC is high is defined as the tag phase. The remainder of the frame where AC_SYNC is low is defined as the data phase. Each data bit is sampled on the falling edge of BIT_CLK. Figure 5-22. AC-link Protocol
Tag Phase 20.8uS (48 KHz) SYNC BIT_CLK SDIN
End of previous Audio Frame Codec Ready 12.288 MHz 81.4 nS
Data Phase
slot(1) slot(2)
slot(12) "0"
"0"
"0"
19
0
19
0
19
0
19
0
Time Slot "Valid" Bits ("1" = time slot contains valid PCM
Slot 1
Slot 2
Slot 3
Slot 12
The ICH2 has two SDIN pins allowing a single or dual codec configuration. When two codecs are connected, the primary and secondary codecs can be connected to either SDIN line, however it is recommended that the primary codec be attached to SDIN [0]. The ICH2 does not distinguish between primary and secondary codecs on its SDIN[1:0] pins; however, the registers do distinguish between SDIN[0] and SDIN[1] for wake events, etc. The primary codec can be an AC (audio codec), MC (modem codec), or AMC (audio/modem codec) device. The secondary codec can be an AC, MC, or AMC device. The MC can be either on the primary or the secondary codec, while the AC can be either on the primary or the secondary codec, or BOTH the primary or the secondary codec. The ICH2 does not support optional test modes as outlined in the AC’97 specification.
AC-link Output Frame (SDOUT)
A new audio output frame begins with a low to high transition of AC_SYNC. AC_SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the codec samples the assertion of AC_SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new frame. On the next rising edge of BIT_CLK, the ICH2 transitions SDOUT into the first bit position of slot 0, or the valid frame bit. Each new bit position is presented to the AC-link on a rising edge of BIT_CLK, and subsequently sampled by the codec on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. The output frame data phase corresponds to the multiplexed bundles of all digital output data targeting codec DAC inputs and control registers. Each output frame supports up to twelve outgoing data time slots. The ICH2 generates 16 bit samples and, in compliance with the AC’97 specification, pads the 4 least significant bits of valid slots with zeros. The output data stream is sent with the most significant bit first and all invalid slots are stuffed with 0s. When mono audio sample streams are output from the ICH2, software must ensure both left and right sample stream time slots are filled with the same data.
Output Slot 0: Tag Phase
Slot 0 is considered the tag phase. The tag phase is a special 16 bit time slot wherein each bit conveys a valid tag for its corresponding time slot within the current frame. A one in a given bit position of slot 0 indicates that the corresponding time slot within the current frame has been
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assigned to a data stream and contains valid data. If a slot is tagged invalid with a zero in the corresponding bit position of slot 0, the ICH2 stuffs the corresponding slot with zeros during that slot’s active time. Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of the entire frame. If the valid frame bit is set to one, this indicates that the current frame contains at least one slot with valid data. When there is no transaction in progress, the ICH2 deasserts the frame valid bit. Note that after a write to slot 12, that slot always stays valid; therefore, the frame valid bit remains set. The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to distinguish between separate codecs on the link. Using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted across the link at its fixed 48 KHz frame rate. The codec can control the output sample rate of the ICH2 using the SLOTREQ bits as described in the AC’97 specification.
Output Slot 1: Command Address Port
The command port is used to control features and monitor status of AC‘97 functions including, but not limited to, mixer settings and power management. The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Output frame slot 1 communicates control register address and write/read command information. In the case of the split codec implementation, accesses to the codecs are differentiated by the driver using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh for the secondary codec. The differentiation on the link, however, is done via the codec ID bits. See Section for further details.
Output Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle as indicated in slot 1, bit 19. If the current command port operation is a read then the entire slot time stuffed with 0s by the ICH2. Bits [19:4] contain the write data. Bits [3:0] are reserved and are stuffed with zeros.
Output Slot 3: PCM Playback Left Channel
Output frame slot 3 is the composite digital audio left playback stream. Typically, this slot is composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH2 transmits sample streams of 16 bits and stuffs the remaining bits with zeros. Data in output slots 3 and 4 from the ICH2 should be duplicated by software if there is only a single channel out.
Output Slot 4: PCM Playback Right Channel
Output frame slot 4 is the composite digital audio right playback stream. Typically, this slot is composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH2 transmits sample streams of 16 bits and stuffs the remaining bits with zeros. Data in output slots 3 and 4 from the ICH2 should be duplicated by software if there is only a single channel out.
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Output Slot 5: Modem Codec
Output frame slot 5 contains modem DAC data. The modem DAC output supports 16 bit resolution. At boot time, if the modem codec is supported, the AC’97 controller driver determines the DAC resolution. During normal runtime operation the ICH2 stuffs trailing bit positions within this time slot with 0s.
Output Slot 6: PCM Playback Center Front Channel
When set up for 6 channel mode, this slot is used for the front center channel. The format is the same as Slots 3. If not set up for 6 channel mode, this channel will always be stuffed with 0s by ICH2.
Output Slots 7–8: PCM Playback Left and Right Rear Channels
When set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear Left and Right channels. The format for these two channels are the same as Slots 3 and 4.
Output Slot 9: Playback SubWoofer Channel
When set for 6 channel mode, this slot is used for the SubWoofer. The format is the same as Slots 3. If not set up for 6 channel mode, this channel will always be stuffed with 0s by ICH2.
Output Slots 10–11: Reserved
Output frame slots 10–11 are reserved and are always stuffed with 0s by the ICH2 AC’97 controller.
Output Slot 12: I/O Control
The 16 bits of DAA and GPIO control (output) and status (input) have been directly assigned to bits on slot 12 to minimize latency of access to changing conditions. The value of the bits in this slot are the values written to the GPIO control register at offset 54h and D4h (in the case of a secondary codec) in the modem codec I/O space. The following rules govern the usage of slot 12. 1. Slot 12 is marked invalid by default on coming out of AC-link reset and will remain invalid until a register write to 54h/D4h. 2. A write to offset 54h/D4h in codec I/O space will cause the write data to be transmitted on slot 12 in the next frame, with slot 12 marked valid, and the address/data information to also be transmitted on slots 1 and 2. 3. After the first write to offset 54h/D4h, slot 12 remains valid for all following frames. The data transmitted on slot 12 is the data last written to offset 54h/D4h. Any subsequent write to the register will cause the new data to be sent out on the next frame. 4. Slot 12 will get invalidated after the following events: PCI reset, AC'97 cold reset, warm reset, and hence a wake from S3, S4, or S5. Slot 12 will remain invalid until the next write to offset 54h/D4h.
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AC-link Input Frame (SDIN)
There are two SDIN lines on the ICH2 for use with a primary and secondary codec. Each SDIN pin can have a codec attached. Depending upon which codec (AC, MC, or AMC) is attached, various slots will be valid or invalid. The data slots on the two inputs must be completely orthogonal (except for the tag slot 0), that is, no two data slots at the same location will be valid on both lines. This precludes the use of two similar codecs (e.g., two ACs or MCs) which use the same time slots. The input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC’97 controller. As in the case for the output frame, each AC-link input frame consists of twelve time slots. A new audio input frame begins with a low-to-high transition of AC_SYNC. AC_SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the receiver samples the assertion of AC_SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the codec transitions SDIN into the first bit position of slot 0 (codec ready bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK and subsequently sampled by the ICH2 on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. SDIN data stream must follow the AC’97 specification and be MSB justified with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with zeros. SDIN data is sampled by the ICH2 on the falling edge of BIT_CLK.
Input Slot 0: Tag Phase
Input slot 0 consists of a codec ready bit (bit 15) and slot valid bits for each subsequent slot in the frame (bits [14:3]). The codec ready bit within slot 0 (bit 15) indicates whether the codec on the AC-link is ready for operation. If the codec ready bit in slot 0 is a zero, the codec is not ready for normal operation. When the AC-link codec ready bit is a 1, it indicates that the AC-link and codec control and status registers are in a fully operational state. The codec ready bits are visible through the Global Status register of the ICH2. Software must further probe the Powerdown Control/Status register in the codec to determine exactly which subsections, if any, are ready. Bits [14:3] in slot 0 indicate which slots of the input stream to the ICH2 contain valid data, just as in the output frame. The remaining bits in this slot are stuffed with zeros.
Input Slot 1: Status Address Port / Slot Request Bits
The status port is used to monitor status of codec functions including, but not limited to, mixer settings and power management. Slot 1 must echo the control register index, for historical reference, for the data to be returned in slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in slot 0. For multiple sample rate output, the codec examines its sample rate control registers, the state of its FIFOs, and the incoming SDOUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current audio input frame signal which output slots require data from the controller in the next audio output frame. For fixed 48 kHz operation the SLOTREQ bits are always set active (low) and a sample is transferred each frame. For multiple sample rate input, the tag bit for each input slot indicates whether valid data is present or not.
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Table 5-90. Input Slot 1 Bit Definitions
Bit 19 18:12 11 10 9 8 7 6 5 4:2 1:0 Reserved (Set to zero) Control Register Index (Stuffed with zeros if tagged invalid) Slot 3 Request: PCM Left Channel* Slot 4 Request: PCM Right Channel* Slot 5 Request: Modem Line 1 Slot 6 Request: PCM Center Channel* Slot 7 Request: PCM Left Surround* Slot 8 Request: PCM Right Surround* Slot 9 Request: PCM LFE Channel* Slot Request 10-12: Not Implemented Reserved (Stuffed with zeros) Description
NOTE: *Slot 3 Request and Slot 4 Request bits must be the same value, i.e. set or cleared in tandem. This is also true for the Slot 7 and Slot 8 Request bits, as well as the Slot 6 and Slot 9 Request bits.
As shown in Table 5-90, slot 1 delivers codec control register read address and multiple sample rate slot request flags for all output slots of the controller. When a slot request bit is set by the codec, the controller returns data in that slot in the next output frame. Slot request bits for slots 3 and 4 are always set or cleared in tandem (i.e., both are set or cleared). When set, the input slot 1 tag bit only pertains to Status Address Port data from a previous read. SLOTREQ bits are always valid independent of the slot 1 tag bit.
Input Slot 2: Status Data Port
The status data port receives 16-bit control register read data. Bit [19:4]: Control Register Read Data Bit [3:0]: Reserved.
Input Slot 3: PCM Record Left Channel
Input slot 3 is the left channel input of the codec. ICH2 supports 16 bit sample resolution. Samples transmitted to the ICH2 must be in left/right channel order.
Input Slot 4: PCM Record Right Channel
Input slot 4 is the right channel input of the codec. The ICH2 supports 16 bit sample resolution. Samples transmitted to the ICH2 must be in left/right channel order.
Input Slot 5: Modem Line
Input slot 5 contains MSB justified modem data. The ICH2 supports 16 bit sample resolution.
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Input Slot 6: Optional Dedicated Microphone Record Data
Input slot 6 is a third PCM system input channel available for dedicated use by a microphone. This input channel supplements a true stereo output that enables more precise echo cancellation algorithm for speakerphone applications. The ICH2 supports 16 bit resolution for slot 6 input.
Input Slots 7-11: Reserved
Input frame slots 7–11 are reserved for future use and should be stuffed with zeros by the codec, per the AC’97 specification.
Input Slot 12: I/O status
The status of the GPIOs configured as inputs are to be returned on this slot in every frame. The data returned on the latest frame is accessible to software by reading the register at offset 54h/D4h in the codec I/O space. Only the 16 MSBs are used to return GPI status. Bit 0 of this slot indicates the GPI status. When a GPI changes state, this bit gets set for one frame by the codec. This bit can cause an interrupt to the processor if enabled via the Global Control register. Reads from 54h/D4h are not transmitted across the link in slot 1 and 2. The data from the most recent slot 12 is returned on reads from offset 54h/D4h.
Register Access
In the ICH2 implementation of the AC-link, up to two codecs can be connected to the SDOUT pin. The following mechanism is used to address the primary and secondary codecs individually. The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in Table 5-91. Slot 1 is used to transmit the register address and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should be valid since only an address is transmitted. For I/O reads, only slot 1 valid bit is set; for I/O writes, both slots 1 and 2 valid bits are set. The secondary codec registers are accessed using slots 1 and 2 as described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bit 0 (bit 0 of slot 0) is set to 1. This allows the secondary codec to monitor the slot valid bits of slots 1and 2, and bit 0 of slot 0 to determine if the access is directed to the secondary codec. If the register access is targeted to the secondary codec, slot 1 and 2 will contain the address and data for the register access. Since slots 1 and 2 are marked invalid, the primary codec will ignore these accesses. Table 5-91. Output Tag Slot 0
Bit 15 14 13 12:3 2 1:0 Primary Access Example 1 1 1 X 0 00 Secondary Access Example 1 0 0 X 0 01 Frame Valid Slot 1 Valid, Command Address bit (Primary codec only) Slot 2 Valid, Command Data bit (Primary codec only) Slot 3-12 Valid Reserved Codec ID (00 reserved for primary; 01 indicate secondary) Description
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When accessing the codec registers, only one I/O cycle can be pending across the AC-link at any time. The ICH2 implements write posting on I/O writes across the AC-link (i.e., writes across the link are indicated as complete before they are actually sent across the link). To prevent a second I/O write from occurring before the first one is complete, software must monitor the CAS bit in the Codec Access Semaphore register which indicates that a codec access is pending. Once the CAS bit is cleared, then another codec access (read or write) can go through. The exception is reads to offset 54h/D4h (slot 12) which are returned immediately with the most recently received slot 12 data. Writes to offset 54h and D4h (primary and secondary codecs), get transmitted across the AC-link in slots 1 and 2 as a normal register access. Slot 12 is also updated immediately to reflect the data being written. The controller will not issue back-to-back reads. It must get a response to the first read before issuing a second. In addition, codec reads and writes are only executed once across the link, and are not repeated.
5.18.2
AC-Link Low Power Mode
The AC-link signals can be placed in a low power mode. When the AC‘97 Powerdown Register (26h), is programmed to the appropriate value, both BIT_CLK and SDIN will be brought to and held at a logic low voltage level.
Figure 5-23. AC-link Powerdown Timing
SYNC
BIT_CLK
SDOUT
slot 12 prev. frame
TAG
Write to 0x20
Data PR4
SDIN Note: BIT_CLK not to scale
slot 12 prev. frame
TAG
BIT_CLK and SDIN transition low immediately following a write to the Powerdown Register (26h) with PR4. When the AC‘97 controller driver is at the point where it is ready to program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. The AC‘97 controller also drives AC_SYNC, and SDOUT low after programming AC‘97 to this low power, halted mode. Once the codec has been instructed to halt BIT_CLK, a special wake up protocol must be used to bring the AC-link to the active mode since normal output and input frames can not be communicated in the absence of BIT_CLK. Once in a low power mode, the ICH2 provides three methods for waking up the AC-link; external wake event, cold reset and warm reset. Note: Before entering any low power mode where the link interface to the codec is expected to be powered down while the rest of the system is awake, the software must set the "Shut Off" bit in the control register.
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External Wake Event
Codecs can signal the controller to wake the AC-link and wake the system using SDIN. The minimum SDIN wake up pulse width is 1 us. The rising edge of SDIN[0] or SDIN[1] causes the ICH2 to sequence through an AC-link warm reset and set the AC97_STS bit in the GPE0_STS register to wake the system. The primary codec must wait to sample AC_SYNC high and low before restarting BIT_CLK as diagrammed in Figure 5-24. The codec that signaled the wake event must keep its SDIN high until it has sampled AC_SYNC having gone high, and then low. Figure 5-24. SDIN Wake Signaling
Power Down Frame SYNC BIT_CLK SDOUT SDIN
slot 12 prev. frame
Sleep State
Wake Event
New Audio Frame
TAG
Write to 0x20
Data PR4
TAG
Slot 1
Slot 2
slot 12 prev. frame
TAG
TAG
Slot 1
Slot 2
The AC-link protocol provides for a cold reset and a warm reset. The type of reset used depends on the system’s current power down state. Unless a cold or register reset (a write to the Reset register in the codec) is performed, wherein the AC‘97 codec registers are initialized to their default values, registers are required to keep state during all power down modes. Once powered down, activation of the AC-link via re-assertion of the AC_SYNC signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. When AC-link powers up, it indicates readiness via the codec ready bit.
5.18.3
AC‘97 Cold Reset
A cold reset is achieved by asserting AC_RST# for 1 us. By driving AC_RST# low, BIT_CLK, and SDOUT will be activated and all codec registers will be initialized to their default power on reset values. AC_RST# is an asynchronous AC‘97 input to the codec.
5.18.4
AC‘97 Warm Reset
A warm reset re-activates the AC-link without altering the current codec register values. A warm reset is signaled by driving AC_SYNC high for a minimum of 1 us in the absence of BIT_CLK. Within normal frames, AC_SYNC is a synchronous AC‘97 input to the codec. However, in the absence of BIT_CLK, AC_SYNC is treated as an asynchronous input to the codec used in the generation of a warm reset. The codec must not respond with the activation of BIT_CLK until AC_SYNC has been sampled low again by the codec. This will prevent the false detection of a new frame.
Note:
On receipt of wake up signalling from the codec, the digital controller will issue an interrupt if enabled. Software will then have to issue a warm or cold reset to the codec by setting the appropriate bit in the Global Control Register.
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5.18.5
System Reset
Table 5-92 indicates the states of the link during various system reset and sleep conditions.
Table 5-92. AC-link state during PCIRST#
Signal Power Plane I/O During PCIRST#/ Low Low Low Driven by codec Driven by codec After PCIRST#/ Low Running Running Running Running S1 Cold Reset bit (Hi) Low Low Low2,4 Low2,4 S3 S4/S5
AC_RST# AC_SDOUT AC_SYNC BIT_CLK SDIN[1:0]
Resume3 Core1 Core1 Core Resume
Output Output Output Input Input
Low Low Low Low2,4 Low2,4
Low Low Low Low2,4 Low2,4
NOTE: 1. ICH2 core well outputs are used as strapping options for the ICH2. They are sampled during system reset. These signals may have weak pull-ups/put-downs. The ICH2 outputs are driven to the appropriate level prior to AC_RST# being deasserted, preventing a codec from entering test mode. Straps are tied to the core well to prevent leakage during a suspend state. 2. The pull-down resistors on these signals are only enabled when the AC-Link Shut Off bit in the AC’97 Global Control Register is set to 1. All other times, the pull-down resistor is disabled. 3. AC_RST# will be held low during S3–S5. It cannot be programmed high during a suspend state. 4. BIT_CLK and SDIN[1:0] are driven low by the codecs during normal states. If the codec is powered during suspend states, it holds these signals low. However, if the codec is not present or not powered in suspend, external pull-down resistors are required.
The transition of AC_RST# to the deasserted state only occurs under driver control. In the S1sleep state, the state of the AC_RST# signal is controlled by the AC’97 Cold Reset# bit (bit 1) in the Global Control register. AC_RST# will be asserted (low) by the ICH2 under the following conditions: • RSMRST# (system reset, including the a reset of the resume well and PCIRST#) • Mechanical power up (causes PCIRST#) • Write to CF9h hard reset (causes PCIRST#) • Transition to S3/S4/S5 sleep states (causes PCIRST#) • Write to AC’97 Cold Reset# bit in the Global Control Register. Hardware will never deassert AC_RST# (i.e., never deasserts the Cold Reset# bit) automatically. Only software can deassert the Cold Reset# bit and, hence, the AC_RST# signal. This bit, while it resides in the core well, remains cleared upon return from S3/S4/S5 sleep states. The AC_RST# pin remains actively driven from the resume well as indicated.
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5.19
Firmware Hub Interface
This section describes the memory cycle type to be used on the Firmware Hub (FWH) interface. Below are the various types of cycles that are supported by the product.
Cycle Type FWH Memory Read FWH Memory Write Comment New chip select and addressing are used. New chip select and addressing are used.
5.19.1
Field Definitions
START
This one clock field indicates the start of a cycle. It is valid on the last clock that LFRAME# is sampled low. The two start fields that are used for the cycle are shown in the table below. If the start field that is sampled is not one of these values, then the cycle attempted is not a FWH Memory Cycle. It may be a valid memory cycle that the FWH component may wish to decode (i.e., it may be of the LPC memory cycle variety).
AD[3:0] 1101 1110 FWH Memory Read FWH Memory Write Indication
IDSEL (Device Select)
This one clock field is used to indicate which FWH component is being selected. The four bits transmitted over AD[3:0] during this clock are compared with values strapped onto pins on the FWH component. If there is a match, the FWH component will continue to decode the cycle to determine which bytes are requested on a read or which bytes to update on a write. If there is not a match, the FWH component may discard the rest of the cycle and go into a standby power state.
MSIZE (Memory Size)
The value ‘0000b’ is sent in this field. A value of ‘0000b’ corresponds to a single byte transfer. Other encodings of this field are reserved for future use.
MADDR (Memory Address)
This is a 7-clock field that provides a 28 bit memory address. This allows for up to 256 MB per memory device, for a total of a 4 GB addressable space. The address is transferred with the most significant nibble first.
SYNC
The SYNC protocol is the same as described in the LPC specification.
TAR
The TAR fields are the same as described in the LPC specification. Refer to this specification for further details.
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5.19.2
Protocol
The FWH Memory cycles use a sequence of events that start with a START field (LFRAME# active with appropriate AD[3:0] combination) and end with the data transfer. The following sections describe the cycles in detail.
Preamble
The initiation of the FWH Memory cycles is shown in Figure 5-25. The FWH Memory transaction begins with LFRAME# going low and a START field driven on AD[3:0]. For FWH Memory Read cycles, the START field must be ‘1101b’; for FWH Memory Write cycles, the START field must be ‘1110b’. Following the START field is the IDSEL field. This field acts like a chip select in that it indicates which device should respond to the current transaction. The next seven clocks are the 28bit address from where to begin reading in the selected device. Next, an MSIZE value of 0 indicates the master is requesting a single byte. Figure 5-25. FWH Memory Cycle Preamble
T1 CLK T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
FRAME# AD[3:0] START IDSEL 28 Bit Address MSIZE
Read Cycle (Single Byte)
For read cycles, after the pre-amble (described above), the host drives a TAR field to give ownership of the bus to the FWH. After the second clock of the TAR phase, the target device assumes the bus and begins driving SYNC values. When it is ready, it drives the low nibble, then the high nibble of data, followed by a TAR to give control back to the host. Figure 5-26. Single Byte Read
T1 CLK T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
FRAME#
AD[3:0]
Preamble
TAR
SYNC
D_Lo
D_Hi
TAR
fh d
Figure 5-26 shows a device that requires 3 SYNC clocks to access data. Since the access time can begin once the address phase has been completed, the two clocks of the TAR phase can be considered as part of the access time of the part. For example, a device with a 120 ns access time could assert ‘0101b’ for clocks 1 and 2 of the SYNC phase and ‘0000b’ for the last clock of the SYNC phase. This would be equivalent to 5 clocks worth of access time if the device started that access at the conclusion of the Preamble phase. Once SYNC is achieved, the device returns the data in two clocks and gives ownership of the bus back to the host with a TAR phase.
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Write Cycles (Single Byte)
All devices that support FWH memory write cycles must support single byte writes. FWH memory write cycles use the same preamble as FWH memory read cycles that is described above. Figure 5-27. Single Byte Write
T1 CLK T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
FRAME# AD[3:0] Preamble D_Lo D_Hi TAR
TAR
SYNC
Figure 5-27 shows an FWH memory write cycle where a single byte is transferred. The master asserts an MSIZE value of 0. After the address has been transferred, the 2 clock data phase begins. Following the data phase, bus ownership is transferred to the FWH component with a TAR cycle. Following the TAR phase, the device must assert a SYNC value of ‘0000b’ (ready) or ‘1010b’ (error) indicating the data has been received. Bus ownership is then given back to the master with another TAR phase. FWH Memory Writes only allow one clock for the SYNC phase. The TAR + SYNC + TAR phases at the end of FWH memory write cycles must be exactly 5 clocks.
Error Reporting
There is no error reporting over the FWH interface for FWH memory cycles. If an error occurs (e.g., an address out of range or an unsupported memory size), the cycle will continue from the host unabated. This is because these errors are the result of illegal programming, and there is no efficient error reporting method that can be done to counter the programming error. Therefore, the FWH component must not report the error conditions over the FWH interface. It must only report wait states and the ‘ready’ condition. It may choose to log the error internally to be debugged, but it must not signal an error through the FWH interface itself
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Register and Memory Mapping
Register and Memory Mapping
6
The ICH2 contains registers that are located in the processor’s I/O space and memory space and sets of PCI configuration registers that are located in PCI configuration space. This chapter describes the ICH2 I/O and memory maps at the register-set level. Register access is also described. Register-level address maps and Individual register bit descriptions are provided in the following chapters. The following notations and definitions are used in the register/instruction description chapters. RO Read Only. In some cases, If a register is read only, writes to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. Write Only. In some cases, If a register is write only, reads to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. Read/Write. A register with this attribute can be read and written. Read/Write Clear. A register bit with this attribute can be read and written. However, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. When ICH2 is reset, it sets its registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the ICH2 registers accordingly. Register bits that are highlighted in bold text indicate that the bit is implemented in the ICH2. Register bits that are not implemented or are rewired will remain in plain text.
WO
R/W R/WC Default
Bold
6.1
PCI Devices and Functions
The ICH2 incorporates a variety of PCI functions as shown in Table 6-1. These functions are divided into three logical devices (B0:D30, B0:D31 and B1:D8). D30 is the hub interface-to-PCI bridge, D31 contains the PCI-to-LPC Bridge, IDE Controller, USB Controllers, SMBus Controller and the AC’97 Audio and Model Controller functions. B1:D8 is the integrated LAN Controller. Note: From a software perspective, the integrated LAN Controller resides on the ICH2’s external PCI bus (See Section 5.1.2). This is typically Bus 1, but may be assigned a different number depending on system configuration. If a particular system platform does not want to support any one of Device 31’s Functions 1–6, they can individually be disabled. The integrated LAN Controller will be disabled if no Platform LAN Connect component is detected (See Section 5.2, “LAN Controller (B1:D8:F0)” on page 5-6). When a function is disabled, it does not appear at all to the software. A disabled function will not respond to any register reads or writes. This is intended to prevent software from thinking that a function is present (and reporting it to the end-user).
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Register and Memory Mapping
Table 6-1. PCI Devices and Functions
Bus:Device:Function Bus 0:Device 30:Function 0 Bus 0:Device 31:Function 0 Bus 0:Device 31:Function 1 Bus 0:Device 31:Function 2 Bus 0:Device 31:Function 3 Bus 0:Device 31:Function 4 Bus 0:Device 31:Function 5 Bus 0:Device 31:Function 6 Bus 1:Device 8:Function 0 Function Description Hub Interface to PCI Bridge PCI to LPC Bridge1 IDE Controller USB Controller #1 SMBus Controller USB Controller #2 AC’97 Audio Controller AC’97 Modem Controller LAN Controller
NOTES: 1. The PCI to LPC bridge contains registers that control LPC, Power Management, System Management, GPIO, processor interface, RTC, Interrupts, Timers, DMA.
6.2
PCI Configuration Map
Each PCI function on the ICH2 has a set of PCI configuration registers. The register address map tables for these register sets are included at the beginning of the chapter for the particular function. Configuration Space registers are accessed through configuration cycles on the PCI bus by the Host bridge using configuration mechanism #1 detailed in the PCI 2.1 specification. Some of the PCI registers contain reserved bits. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, write operation for the configuration address register. In addition to reserved bits within a register, the configuration space contains reserved locations. Software should not write to reserved PCI configuration locations in the device-specific region (above address offset 3Fh).
6.3
I/O Map
The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved. In some cases they can be disabled. Variable ranges can be moved and can also be disabled.
6-2
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Register and Memory Mapping
6.3.1
Fixed I/O Address Ranges
Table 6-2 shows the fixed I/O decode ranges from the processor perspective. Note that for each I/O range, there may be a separate behavior for reads and writes. The hub interface cycles that go to target ranges that are marked as “Reserved” are not decoded by the ICH2; they are passed to PCI. If a PCI master targets one of the fixed I/O target ranges, it will be positively decoded by the ICH2 in Medium speed. Refer to Table A-1 for a complete list of all fixed I/O registers. Address ranges that are not listed or marked “Reserved” are NOT decoded by the ICH2 (unless assigned to one of the variable ranges).
Table 6-2. Fixed I/O Ranges Decoded by ICH2
I/O Address 00h–08h 09h–0Eh 0Fh 10h–18h 19h–1Eh 1Fh 20h–21h 24h–25h 28h–29h 2Ch–2Dh 2Eh–2Fh 30h–31h 34h–35h 38h–39h 3Ch–3Dh 40h–42h 43h 4E–4F 50h–52h 53h 60h 61h 62h 63h 64h 65h 66h 67h 70h 71h 72h 73h 74h Read Target DMA Controller RESERVED DMA Controller DMA Controller RESERVED DMA Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller LPC SIO Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Timer/Counter RESERVED LPC SIO Timer/Counter RESERVED Microcontroller NMI Controller Microcontroller NMI Controller Microcontroller NMI Controller Microcontroller NMI Controller RESERVED5 RTC Controller RTC Controller RTC Controller RTC Controller Write Target DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller LPC SIO Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Timer/Counter Timer/Counter LPC SIO Timer/Counter Timer/Counter Microcontroller NMI Controller Microcontroller NMI Controller Microcontroller NMI Controller Microcontroller NMI Controller NMI and RTC Controller RTC Controller NMI and RTC Controller RTC Controller NMI and RTC Controller Internal Unit DMA DMA DMA DMA DMA DMA Interrupt Interrupt Interrupt Interrupt Forwarded to LPC Interrupt Interrupt Interrupt Interrupt PIT (8254) PIT Forwarded to LPC PIT PIT Forwarded to LPC processor I/F Forwarded to LPC processor I/F Forwarded to LPC processor I/F Forwarded to LPC processor I/F RTC RTC RTC RTC RTC
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Register and Memory Mapping
Table 6-2. Fixed I/O Ranges Decoded by ICH2 (Continued)
I/O Address 75h 76h 77h 80h 81h–83h 84h–86h 87h 88h 89h–8Bh 8Ch–8Eh 08Fh 90h–91h 92h 93h–9Fh A0h–A1h A4h–A5h A8h–A9h ACh–ADh B0h–B1h B2h–B3h B4h–B5h B8h–B9h BCh–BDh C0h–D1h D2h–DDh DEh–DFh F0h 170h–177h 1F0h–1F7h 376h 3F6h 4D0h–4D1h CF9h Read Target RTC Controller RTC Controller RTC Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller Reset Generator DMA Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Power Management Interrupt Controller Interrupt Controller Interrupt Controller DMA Controller RESERVED DMA Controller See Note 3 IDE Controller2 IDE Controller1 IDE Controller
2
Write Target RTC Controller NMI and RTC Controller RTC Controller DMA Controller and LPC or PCI DMA Controller DMA Controller and LPC or PCI DMA Controller DMA Controller and LPC or PCI DMA Controller DMA Controller and LPC or PCI DMA Controller DMA Controller Reset Generator DMA Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Power Management Interrupt Controller Interrupt Controller Interrupt Controller DMA Controller DMA Controller DMA Controller FERR#/IGNNE# / Interrupt Controller IDE Controller1 IDE Controller2 IDE Controller
1
Internal Unit RTC RTC RTC DMA DMA DMA DMA DMA DMA DMA DMA DMA processor I/F DMA Interrupt Interrupt Interrupt Interrupt Interrupt Power Management Interrupt Interrupt Interrupt DMA DMA DMA processor interface Forwarded to IDE Forwarded to IDE Forwarded to IDE Forwarded to IDE Interrupt processor interface
IDE Controller1 Interrupt Controller Reset Generator
IDE Controller2 Interrupt Controller Reset Generator
NOTES: 1. Only if IDE Standard I/O space is enabled for Primary Drive. Otherwise, the target is PCI. 2. Only if IDE Standard I/O space is enabled for Secondary Drive. Otherwise, the target is PCI. 3. If POS_DEC_EN bit is enabled, reads from F0h will not be decoded by the ICH2. If POS_DEC_EN is not enabled, reads from F0h will forward to LPC.
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Register and Memory Mapping
6.3.2
Variable I/O Decode Ranges
Table 6-3 shows the Variable I/O Decode Ranges. They are set using Base Address Registers (BARs) or other configuration bits in the various PCI configuration spaces. The PNP software (PCI or ACPI) can use their configuration mechanisms to set and adjust these values. When a cycle is detected on the hub interface, the ICH2 positively decodes the cycle. If the response is on the behalf of an LPC device, ICH2 will forward the cycle to the LPC interface. Refer to Table A-2 for a complete list of all variable I/O registers.
Warning:
The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges. Unpredictable results if the configuration software allows conflicts to occur. The ICH2 does not perform any checks for conflicts.
Table 6-3. Variable I/O Decode Ranges
Range Name ACPI IDE USB #1 SMBus AC’97 Audio Mixer AC’97 Bus Master AC’97 Modem Mixer TCO GPIO Parallel Port Serial Port 1 Serial Port 2 Floppy Disk Controller MIDI MSS SoundBlaster LAN USB #2 LPC Generic 1 LPC Generic 2 Monitors 4:7 Mappable Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space 96 Bytes above ACPI Base Anywhere in 64 KB I/O Space 3 ranges in 64 KB I/O Space 8 Ranges in 64 KB I/O Space 8 Ranges in 64 KB I/O Space 2 Ranges in 64 KB I/O Space 4 Ranges in 64 KB I/O Space 4 Ranges in 64 KB I/O Space 2 Ranges in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Size (Bytes) 64 16 32 16 256 64 256 32 64 8 8 8 8 2 8 32 64 32 128 16 16 Target Power Management IDE Unit USB Unit 1 SMB Unit AC’97 Unit AC’97 Unit AC’97 Unit TCO Unit GPIO Unit LPC Peripheral LPC Peripheral LPC Peripheral LPC Peripheral LPC Peripheral LPC Peripheral LPC Peripheral LAN Unit USB Unit 2 LPC Peripheral LPC Peripheral LPC Peripheral or Trap on PCI
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Register and Memory Mapping
6.4
Memory Map
Table 6-4 shows (from the processor perspective) the memory ranges that the ICH2 decodes. Cycles that arrive from the MCH will first be driven out on PCI. The ICH2 may then claim the cycle for it to be forwarded to LPC or claimed by the internal APIC. If subtractive decode is enabled, the cycle can be forwarded to LPC. PCI cycles generated by an external PCI master will be positively decoded unless it falls in the PCI-PCI bridge forwarding range (those addresses are reserved for PCI peer-to-peer traffic). If the cycle is not in the I/O APIC or LPC ranges, it will be forwarded up the hub interface to the Host Controller.
Table 6-4. Memory Decode Ranges from Processor Perspective
Memory Range 0000 0000h–000D FFFFh 0010 0000–TOM (Top of Memory) 000E 0000h–000F FFFFh FEC0 0000h–FEC0 0100h FFC0 0000h–FFC7 FFFFh FF80 0000h–FF87 FFFFh FFC8 0000h–FFCF FFFFh FF88 0000h–FF8F FFFFh FFD0 0000h–FFD7 FFFFh FF90 0000h–FF97 FFFFh FFD8 0000h–FFDF FFFFh FF98 0000h–FF9F FFFFh FFE0 000h–FFE7 FFFFh FFA0 0000h–FFA7 FFFFh FFE8 0000h–FFEF FFFFh FFA8 0000h–FFAF FFFFh FFF0 0000h–FFF7 FFFFh FFB0 0000h–FFB7 FFFFh FFF8 0000h–FFFF FFFFh FFB8 0000h–FFBF FFFFh FF70 0000h–FF7F FFFFh FF30 0000h–FF3F FFFFh FF60 0000h–FF6F FFFFh FF20 0000h–FF2F FFFFh FF50 0000h–FF5F FFFFh FF10 0000h–FF1F FFFFh FF40 0000h–FF4F FFFFh FF00 0000h–FF0F FFFFh Anywhere in 4 GB range All other Main Memory FWH I/O APIC inside ICH2 FWH FWH FWH FWH FWH FWH FWH Bit 0 in FWH Decode Enable Register Bit 1 in FWH Decode Enable Register Bit 2 in FWH Decode Enable Register is set Bit 3 in FWH Decode Enable Register is set Bit 4 in FWH Decode Enable Register is set Bit 5 in FWH Decode Enable Register is set Bit 6 in FWH Decode Enable Register is set. Always enabled. The top two 64 KB blocks of this range can be swapped as described in Section 6.4.1. Bit 3 in FWH Decode Enable 2 Register is set Bit 2 in FWH Decode Enable 2 Register is set Bit 1 in FWH Decode Enable 2 Register is set Bit 0 in FWH Decode Enable 2 Register is set Enable via BAR in Device 29:Function 0 (D110 LAN Controller) None TOM registers in Host Controller Bit 7 in FWH Decode Enable Register is set Target Dependency/Comments
FWH
FWH FWH FWH FWH D110 LAN Controller PCI
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Register and Memory Mapping
6.4.1
Boot-Block Update Scheme
The ICH2 supports a “Top-Block Swap” mode that has the ICH2 swap the top block in the FWH (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the “top-swap” enable bit is set, the ICH2 will invert A16 for cycles targeting FWH BIOS space. When this bit is 0, the ICH2 will not invert A16. This bit is automatically set to 0 by RTCRST#, but not by PCIRST#. The scheme is based on the concept that the top block is reserved as the “boot” block, and the block immediately below the top block is reserved for doing boot-block updates. The algorithm is: 1. Software copies the top block to the block immediately below the top 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the “Top-Block Swap” bit. This inverts A16 for cycles going to the FWH. Processor access to FFFF_0000 through FFFF_FFFF are directed to FFFF_0000 through FFFE_FFFF in the FWH. Processor accesses to FFFE_0000 through FFFE_FFFF are directed to FFFF_0000 through FFFF_FFFF. 4. Software erases the top block 5. Software writes the new top block 6. Software checks the new top block 7. Software clears the top-block swap bit If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the top-swap bit is backed in the RTC well. Note: The Top-Block Swap mode may be forced by an external strapping option (See Section 2.20.1). When Top-Block Swap mode is forced in this manner, the Top-Swap bit cannot be cleared by software. A re-boot with the strap removed will be required to exit a forced Top-Block Swap mode. top-Block Swap mode only affects accesses to the FWH BIOS space, not feature space. The Top Block Swap mode has no effect on accesses below FFFE_0000.
Note: Note:
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LAN Controller Registers (B1:D8:F0)
LAN Controller Registers (B1:D8:F0)
7
The ICH2 integrated LAN Controller appears to reside at PCI Device 8, Function 0 on the secondary side of the ICH2’s virtual PCI-to-PCI Bridge (See Table 5.1.2). This is typically Bus 1, but may be assigned a different number depending upon system configuration. The LAN Controller acts as both a master and a slave on the PCI bus. As a master, the LAN Controller interacts with the system main memory to access data for transmission or deposit received data. As a slave, some of the LAN Controller’s control structures are accessed by the host processor to read or write information to the on-chip registers. The processor also provides the LAN Controller with the necessary commands and pointers that allow it to process receive and transmit data.
7.1
Note:
.
PCI Configuration Registers (B1:D8:F0)
Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
Table 7-1. PCI Configuration Map (LAN Controller—B1:D8:F0)
Offset 00–01h 02–03h 04–05h 06–07h 08h 0Ah 0Bh 0Dh 0Eh 10–13h 14–17h 2C–2Dh 2E–2Fh 34h 3Ch 3Dh 3Eh 3Fh DCh DDh DE–DFh E0–E1h E3h Mnemonic VID DID PCICMD PCISTS REVID SCC BCC PMLT HEADTYP CSR_MEM_BASE CSR_IO_BASE SVID SID CAP_PTR INT_LN INT_PN MIN_GNT MAX_LAT CAP_ID NXT_PTR PM_CAP PMCSR DATA Register Name/Function Vendor ID Device ID PCI Device Command Register PCI Device Status Register Revision ID Sub Class Code Base Class Code PCI Master Latency Timer Header Type CSR Memory-mapped Base Address CSR I/O-mapped Base Address Subsystem Vendor ID Subsystem ID Capabilities Pointer Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Capability ID Next Item Pointer Power Management Capabilities Power Management Control/Status Data Default 8086h 2449h 0000h 0290h Note 1 00h 02h 00h 00h 0008h 0001h 0000h 0000h DCh 00h 01h 08h 38h 01h 00h FE21h (ICH2) 7E21 (ICH2-M) 0000h 00h Type RO RO R/W R/W RO RO RO R/W RO R/W R/W RO RO RO R/W RO RO RO RO RO RO R/W RO
NOTE: Refer to the Specification Update for the value of the Revision ID Register.
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LAN Controller Registers (B1:D8:F0)
7.1.1
VID—Vendor ID Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 15:0
00–01h 8086h
Attribute: Size:
Description
RO 16 bits
Vendor Identification Number. This is a 16-bit value assigned to Intel.
7.1.2
DID—Device ID Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 15:0
02–03h 2449h
Attribute: Size:
Description
RO 16 bits
Device Identification Number. This is a 16 bit value assigned to the ICH2 integrated LAN Controller.
7.1.3
PCICMD—PCI Command Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 15:10 9 Reserved. Fast Back to Back Enable (FBE)—RO. Hardwired to 0. The integrated LAN Controller will not run fast back-to-back PCI cycles. SERR# Enable (SERR_EN)—R/W. 1 = Enable. Allow SERR# to be generated. 0 = Disable. 7 Wait Cycle Control (WCC)—RO. Hardwired to 0. Not implemented. Parity Error Response (PER)—R/W 1 = The integrated LAN Controller will take normal action when a PCI parity error is detected. The generation of parity is also enabled on the hub interface. 0 = The LAN Controller will ignore PCI parity errors. 5 4 3 2 VGA Palette Snoop (VPS)—RO. Hardwired to 0. Not Implemented. Memory Write and Invalidate Enable (MWIE)—R/W. 0 = Disable. The LAN Controller will not use the Memory Write and Invalidate command. 1 = Enable. Special Cycle Enable (SCE)—RO. Hardwired to 0. The LAN Controller ignores special cycles. Bus Master Enable (BME)—R/W. 1 = Enable. The ICH2’s integrated may function as a PCI bus master. 0 = Disable. 1 Memory Space Enable (MSE)—R/W. 1 = Enable. The ICH2’s integrated LAN Controller will respond to the memory space accesses. 0 = Disable. 0 I/O Space Enable (IOE)—R/W. 1 = Enable. The ICH2’s integrated LAN Controller will respond to the I/O space accesses. 0 = Disable.
04–05h 0000h
Attribute: Size:
Description
RO, R/W 16 bits
8
6
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LAN Controller Registers (B1:D8:F0)
7.1.4
PCISTS—PCI Status Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit
06–07h 0290h
Attribute: Size:
Description
RO, R/WC 16 bits
15
Detected Parity Error (DPE)—R/WC. 1 = The ICH2’s integrated LAN Controller has detected a parity error on the PCI bus (will be set even if Parity Error Response is disabled in the PCI Command register). 0 = This bit is cleared by writing a 1 to the bit location. Signaled System Error (SSE)—R/WC. 1 = The ICH2’s integrated LAN Controller has asserted SERR#. (SERR# can be routed to cause NMI, SMI# or interrupt. 0 = This bit is cleared by writing a 1 to the bit location. Master Abort Status (RMA)—R/WC. 1 = The ICH2’s integrated LAN Controller (as a PCI master) has generated a master abort. 0 = This bit is cleared by writing a 1 to the bit location. Received Target Abort (RTA)—R/WC. 1 = The ICH2’s integrated LAN Controller (as a PCI master) has received a target abort. 0 = This bit is cleared by writing a 1 to the bit location. Signaled Target Abort (STA)—RO. Hardwired to 0. The device will never signal Target Abort. DEVSEL# Timing Status (DEV_STS)—RO. 01h = Medium timing. Data Parity Error Detected (DPED)—R/WC. 1 = All of the following three conditions have been met: 1.The LAN Controller is acting as bus master 2.The LAN Controller has asserted PERR# (for reads) or detected PERR# asserted (for writes) 3.The Parity Error Response bit in the LAN Controller’s PCI Command Register is set. 0 = This bit is cleared by writing a 1 to the bit location. Fast Back to Back (FB2B)—RO. Hardwired to 1. The device can accept fast back-to-back transactions. User Definable Features (UDF)—RO. Hardwired to 0. Not implemented. 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0. The device does not support 66MHz PCI. Capabilities List (CAP_LIST)—RO. 1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management. 0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power Management. Reserved.
14
13
12 11 10:9
8
7 6 5
4
3:0
7.1.5
REVID—Revision ID Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
08h 00h
Attribute: Size:
Description
RO 8 bits
Revision Identification Number. 8-bit value that indicates the revision number for the integrated LAN Controller. The three least significant bits in this register may be overridden by the ID and REV ID fields in the EEPROM.
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LAN Controller Registers (B1:D8:F0)
7.1.6
SCC—Sub-Class Code Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
0Ah 00h
Attribute: Size:
Description
RO 8 bits
Sub-Class Code. 8-bit value that specifies the sub-class of the device as an Ethernet controller.
7.1.7
BCC—Base-Class Code Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
0Bh 02h
Attribute: Size:
Description
RO 8 bits
Base Class Code. 8-bit value that specifies the base class of the device as a network controller.
7.1.8
CLS—Cache Line Size Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:5 Reserved. Cache Line Size (CLS)—RW. 00 = Memory Write and Invalidate (MWI) command will not be used by the integrated LAN Controller. 4:3 01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a value of 08h is written to this register). 10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a value of 10h is written to this register). 11 = Invalid. MWI command will not be used. 2:0 Reserved.
0Ch 00h
Attribute: Size:
Description
RW 8 bits
7.1.9
PMLT—PCI Master Latency Timer Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:3 2:0
0Dh 00h
Attribute: Size:
Description
RW 8 bits
Master Latency Timer Count (MLTC)—RW. Defines the number of PCI clock cycles that the integrated LAN Controller may own the bus while acting as bus master. Reserved.
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LAN Controller Registers (B1:D8:F0)
7.1.10
HEADTYP—Header Type Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7 6:0
0Eh 00h
Attribute: Size:
Description
RO 8 bits
Multi-function Device—RO. Hardwired to 0 to indicate a single function device. Header Type—RO. 7-bit field identifies the header layout of the configuration space as an Ethernet controller.
7.1.11
CSR_MEM_BASE CSR—Memory-Mapped Base Address Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value: 10–13h 0000 0008h Attribute: Size: R/W, RO 32 bits
Note:
The ICH2’s integrated LAN Controller requires one BAR for memory mapping. Software determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.
Bit 31:12 11:4 3 2:1 0 Description Base Address—R/W. Upper 20 bits of the base address provides 4 KB of memory-mapped space for the LAN Controller’s Control/Status Registers. Reserved. Pre-fetchable—RO. Hardwired to 0 to indicate that this is not a pre-fetchable memory-mapped address range. Type—RO. Hardwired to 00b to indicate the memory-mapped address range may be located anywhere in 32-bit address space. Memory-Space Indicator—RO. Hardwired to 0 to indicate that this base address maps to memory space.
7.1.12
CSR_IO_BASE—CSR I/O-Mapped Base Address Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value: 14–17h 0000 0001h Attribute: Size: R/W 32 bits
Note:
The ICH2’s integrated LAN Controller requires one BAR for memory mapping. Software determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.
Bit 31:16 15:6 5:1 0 Reserved. Base Address—R/W. Provides 64 bytes of I/O-mapped address space for the LAN Controller’s Control/Status Registers. Reserved. I/O Space Indicator—RO. Hardwired to 1 to indicate that this base address maps to I/O space. Description
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LAN Controller Registers (B1:D8:F0)
7.1.13
SVID—Subsystem Vendor ID (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 15:0 Subsystem Vendor ID—RO.
2C–2D 0000h
Attribute: Size:
Description
RO 16 bits
7.1.14
SID—Subsystem ID (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 15:0 Subsystem ID—RO.
2E–2Fh 0000h
Attribute: Size:
Description
RO 16 bits
Note:
The ICH2’s integrated LAN Controller provides support for configureable Subsystem ID and Subsystem Vendor ID fields. After reset, the LAN Controller automatically reads addresses Ah through Ch of the EEPROM. The LAN Controller checks bits 15:13 in the EEPROM word Ah, and functions according to Table 7-2.
Table 7-2. Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM
Bits 15:14 11b, 10b, 00b 01b 01b Bit 13 X 0b 1b Device ID 2449h 2449h Word Bh Vendor ID 8086h 8086h Word Ch Revision ID 00h 00h Word Ah, bits 10:8 Subsystem ID 0000h Word Bh Word Bh Subsystem Vendor ID 0000h Word Ch Word Ch
7.1.15
CAP_PTR—Capabilities Pointer (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
34h DCh
Attribute: Size:
Description
RO 8 bits
Capabilities Pointer (CAP_PTR)—RO. Hardwired to DCh to indicate the offset within configuration space for the location of the Power Management registers.
7-6
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LAN Controller Registers (B1:D8:F0)
7.1.16
INT_LN—Interrupt Line Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
3Ch 00h
Attribute: Size:
Description
R/W 8 bits
Interrupt Line (INT_LN)—R/W. Identifies the system interrupt line to which the LAN Controller’s PCI interrupt request pin (as defined in the Interrupt Pin Register) is routed.
7.1.17
INT_PN—Interrupt Pin Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
3Dh 01h
Attribute: Size:
Description
RO 8 bits
Interrupt Pin (INT_PN)—RO. Hardwired to 01h to indicate that the LAN Controller’s interrupt request is connected to PIRQA#. However, in the ICH2 implementation, when the LAN Controller interrupt is generated PIRQ[E]# will go active, not PIRQ[A]#.
7.1.18
MIN_GNT—Minimum Grant Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
3Eh 08h
Attribute: Size:
Description
RO 8 bits
Minimum Grant (MIN_GNT)—RO. Indicates the amount of time (in increments of 0.25 µs) that the LAN Controller needs to retain ownership of the PCI bus when it initiates a transaction.
7.1.19
MAX_LAT—Maximum Latency Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
3Fh 38h
Attribute: Size:
Description
RO 8 bits
Maximum Latency (MAX_LAT)—RO. Defines how often (in increments of 0.25 µs) the LAN Controller needs to access the PCI bus.
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LAN Controller Registers (B1:D8:F0)
7.1.20
CAP_ID—Capability ID Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
DCh 01h
Attribute: Size:
Description
RO 8 bits
Capability ID (CAP_ID)—RO. Hardwired to 01h to indicate that the ICH2’s integrated LAN Controller supports PCI Power Management.
7.1.21
NXT_PTR—Next Item Pointer (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
DDh 00h
Attribute: Size:
Description
RO 8 bits
Next Item Pointer (NXT_PTR)—RW. Hardwired to 00b to indicate that power management is the last item in the Capabilities list.
7.1.22
PM_CAP—Power Management Capabilities (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 15:11 10 9 8:6
DE–DFh FE22h
Attribute: Size:
Description
RO 16 bits
PME Support. Hardwired to 11111b. This 5-bit field indicates the power states in which the LAN Controller may assert PME#. The LAN Controller supports wake-up in all power states. D2 Support. Hardwired to 1 to indicate that the LAN Controller supports the D2 power state. D1 Support. Hardwired to 1 to indicate that the LAN Controller supports the D1 power state. Auxiliary Current. Hardwired to 000b to indicate that the LAN Controller implements the Data registers. The auxiliary power consumption is the same as the current consumption reported in the D3 state in the Data register. Device Specific Initialization (DSI). Hardwired to 1 to indicate that special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. DSI is required for the LAN Controller after D3-to-D0 reset. Reserved PME Clock. Hardwired to 0 to indicate that the LAN Controller does not require a clock to generate a power management event. Version. Hardwired to 010b to indicate that the LAN Controller complies with of the PCI Power Management Specification, Revision 1.1.
5 4 3 2:0
7-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LAN Controller Registers (B1:D8:F0)
7.1.23
PMCSR—Power Management Control/Status Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit
E0–E1h 0000h
Attribute: Size:
Description
RO, R/W, R/WC 16 bits
PME Status—R/WC. 1 = Set upon occurrence of a wake-up event, independent of the state of the PME Enable bit. 15 0 = Software clears this bit by writing a 1 to the bit location. This also deasserts the PME# signal and clears the PME status bit in the Power Management Driver Register. When the PME# signal is enabled, the PME# signal reflects the state of the PME status bit. Data Scale—RO. This field indicates the data register scaling factor. It equals 10b for registers zero through eight and 00b for registers nine through fifteen, as selected by the "Data Select" field. Data Select—R/W. This field is used to select which data is reported through the Data register and Data Scale field. PME Enable—R/W. This bit enables the ICH2’s integrated LAN controller to assert PME#. 1 = Enable PME# assertion when PME Status is set. 0 = The device will not assert PME#. 7:5 4 3:2 Reserved. Dynamic Data—RO. Hardwired to 0 to indicate that the device does not support the ability to monitor the power consumption dynamically. Reserved. Power State—R/W. This 2-bit field is used to determine the current power state of the integrated LAN Controller, and to put it into a new power state. The definition of the field values is as follows: 00 = D0 1:0 01 = D1 10 = D2 11 = D3
14:13 12:9
8
7.1.24
DATA—Data Register (LAN Controller—B1:D8:F0)
Offset Address: Default Value:
Bit 7:0
E3h 00h
Attribute: Size:
Description
RO 8 bits
Data Value. State dependent power consumption and heat dissipation data.
Note:
The data register is an 8-bit read only register that provides a mechanism for the ICH2’s integrated LAN Controller to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range of 0 to 2.55 W with 0.01 W resolution, scaled according to the Data Scale field in the PMCSR. The structure of the Data Register is given in Table 7-3.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
7-9
LAN Controller Registers (B1:D8:F0)
Table 7-3. Data Register Structure
Data Select 0 1 2 3 4 5 6 7 8 9–15 Data Scale 2 2 2 2 2 2 2 2 2 0 D0 Power Consumption D1 Power Consumption D2 Power Consumption D3 Power Consumption D0 Power Dissipated D1 Power Dissipated D2 Power Dissipated D3 Power Dissipated Common Function Power Dissipated Reserved Data Reported
7.2
LAN Control / Status Registers (CSR)
Table 7-4. ICH2 Integrated LAN Controller CSR Space
Offset 01h–00h 03h–02h 07h–04h 0Bh–08h 0Dh–0Ch 0Eh 0Fh 13h–10h 17h–14h 18h 1A–19h 1Bh 1Ch 1Dh 1Eh–3Ch Register Name/Function SCB Status Word SCB Command Word SCB General Pointer PORT Reserved EEPROM Control Register Reserved MDI Control Register Receive DMA Byte Count Early Receive Interrupt Flow Control Register PMDR General Control General Status Reserved Default 0000h 0000h 0000 0000h 0000 0000h — 00 — 0000 0000h 0000 0000h 00h 0000h 00h 00 N/A — Type R/WC R/W R/W R/W (special) — R/W — R/W (special) RO R/W R/W R/WC R/W RO —
7-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LAN Controller Registers (B1:D8:F0)
7.2.1
System Control Block Status Word Register
Offset Address: Default Value: 00–01h 0000h Attribute: Size: R/WC, RO 16 bits
The ICH2’s integrated LAN Controller places the status of its Command and Receive units and interrupt indications in this register for the processor to read.
Bit Description Command Unit (CU) Executed (CX)—R/WC. 1 = Interrupt signaled because the CU has completed executing a command with its interrupt bit set. 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 14 Frame Received (FR)—R/WC. 1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. CU Not Active (CNA)—R/WC. 1 = The Command Unit left the Active state or entered the Idle state. There are 2 distinct states of the CU. When configured to generate CNA interrupt, the interrupt will be activated when the CU leaves the Active state and enters either the Idle or the Suspended state. When configured to generate CI interrupt, an interrupt will be generated only when the CU enters the Idle state. 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. Receive Not Ready (RNR)—R/WC. 1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame Descriptor. 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. Management Data Interrupt (MDI)—R/WC. 1 = Set when a Management Data Interface read or write cycle has completed. The management data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data Interface Control register in the CSR). 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 10 Software Interrupt (SWI)—R/WC. 1 = Set when software generates an interrupt. 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 9 Early Receive (ER)—R/WC. 1 = Indicates the occurrence of an Early Receive Interrupt. 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 8 Flow control Pause (FCP)—R/WC. 1 = Indicates Flow Control Pause interrupt. 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. Command Unit Status (CUS)—RO. 7:6 00 = Idle 01 = Suspended 10 = LPQ (Low Priority Queue) active 11 = HPQ (High Priority Queue) active Receive Unit Status (RUS)—RO. 0000 = Idle 0001 = Suspended 0010 = No Resources 0011 = Reserved 0100 = Ready 0101 = Reserved 0110 = Reserved 0111 = Reserved Reserved. 1000 = Reserved 1001 = Suspended with no more RBDs 1010 = No resources due to no more RBDs 1011 = Reserved 1100 = Ready with no RBDs present 1101 = Reserved 1110 = Reserved 1111 = Reserved
15
13
12
11
5:2
1:0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
7-11
LAN Controller Registers (B1:D8:F0)
7.2.2
System Control Block Command Word Register
Offset Address: Default Value: 02–03h 0000h Attribute: Size: R/W 16 bits
The processor places commands for the Command and Receive units in this register. Interrupts are also acknowledged in this register.
Bit CX Mask—R/W. 15 0 = Interrupt not masked. 1 = Disable the generation of a CX interrupt. FR Mask—R/W. 14 0 = Interrupt not masked. 1 = Disable the generation of an FR interrupt. CNA Mask—R/W. 13 0 = Interrupt not masked. 1 = Disable the generation of a CNA interrupt. RNR Mask—R/W. 12 0 = Interrupt not masked. 1 = Disable the generation of an RNR interrupt. ER Mask—R/W. 11 0 = Interrupt not masked. 1 = Disable the generation of an ER interrupt. FCP Mask—R/W. 10 0 = Interrupt not masked. 1 = Disable the generation of an FCP interrupt. Software Generated Interrupt (SI)—WO. 9 0 = No Effect. 1 = Setting this bit causes the LAN Controller to generate an interrupt. Interrupt Mask (IM)—R/W. This bit enables or disables the LAN Controller’s assertion of the INTA# signal. This bit has higher precedence that the Specific Interrupt Mask bits and the SI bit. 0 = Enable the assertion of INTA#. 1 = Disable the assertion of INTA#. Description
8
7-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LAN Controller Registers (B1:D8:F0)
Bit
Description Command Unit Command (CUC). Valid values are listed below. All other values are Reserved. 0000 = NOP: Does not affect the current state of the unit. 0001 = CU Start: Start execution of the first command on the CBL. A pointer to the first CB of the CBL should be placed in the SCB General Pointer before issuing this command. The CU Start command should only be issued when the CU is in the Idle or Suspended states (never when the CU is in the active state), and all of the previously issued Command Blocks have been processed and completed by the CU. Sometimes it is only possible to determine that all Command Blocks are completed by checking that the Complete bit is set in all previously issued Command Blocks. 0010 = CU Resume: Resume operation of the Command unit by executing the next command. This command will be ignored if the CU is idle. 0011 = CU HPQ Start: Start execution of the first command on the high priority CBL. A pointer to the first CB of the HPQ CBL should be placed in the SCB General POinter before issuing this command.
7:4
0100 = Load Dump Counters Address: Tells the device where to write dump data when using the Dump Statistical Counters or Dump and Reset Statistical Counters commands. This command must be executed at least once before any usage of the Dump Statistical Counters or Dump and Reset Statistical Counters commands. The address of the dump area must be placed in the General Pointer register. 0101 = Dump Statistical Counters: Tells the device to dump its statistical counters to the area designated by the Load Dump Counters Address command. 0110 = Load CU Base: The device’s internal CU Base Register is loaded with the value in the CSB General Pointer. 0111 = Dump and Reset Statistical Counters: Tells the device to dump its statistical counters to the area designated by the Load Dump Counters Address command, and then to clear these counters. 1010 = CU Static Resume: Resume operation of the Command unit by executing the next command. This command will be ignored if the CU is idle. This command should be used only when the CU is in the Suspended state and has no pending CU Resume commands. 1011 = CU HPQ Resume: Resume execution of the first command on the HPQ CBL. this command will be ignored if the HPQ was never started.
3
Reserved. Receive Unit Command (RUC). Valid values are: 000 = NOP: Does not affect the current state of the unit. 001 = RU Start: Enables the receive unit. The pointer to the RFA must be placed in the SCB General POinter before using this command. The device pre-fetches the first RFD and the first RBD (if in flexible mode) in preparation to receive incoming frames that pass its address filtering. 010 = RU Resume: Resume frame reception (only when in suspended state). 011 = RCV DMA Redirect: Resume the RCV DMA when configured to "Direct DMA Mode." The buffers are indicated by an RBD chain which is pointed to by an offset stored in the General Pointer Register (this offset will be added to the RU Base).
2:0
100 = RU Abort: Abort RU receive operation immediately. 101 = Load Header Data Size (HDS): This value defines the size of the Header portion of the RFDs or Receive buffers. The HDS value is defined by the lower 14 bits of the SCB General Pointer, so bits 31:15 should always be set to zeros when using this command. Once a Load HDS command is issued, the device expects only to find Header RFDs, or be used in "RCV Direct DMA mode" until it is reset. Note that the value of HDS should be an even, non-zero number. 110 = Load RU Base: The device’s internal RU Base Register is loaded with the value in the SCB General Pointer. 111 = RBD Resume: Resume frame reception into the RFA. This command should only be used when the RU is already in the "No Resources due to no RBDs" state or the "Suspended with no more RBDs" state.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
7-13
LAN Controller Registers (B1:D8:F0)
7.2.3
System Control Block General Pointer Register
Offset Address: Default Value:
Bit 15:0
04–07h 0000 0000h
Attribute: Size:
Description
R/W 32 bits
SCB General Pointer. The SCB General Pointer register is programmed by software to point to various data structures in main memory depending on the current SCB Command word.
7.2.4
PORT Register
Offset Address: Default Value: 08–0Bh 0000 0000h Attribute: Size: R/W (special) 32 bits
The PORT interface allows the processor to reset the ICH2’s internal LAN Controller or perform an internal self test. The PORT DWord may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. The LAN Controller will only accept the command after the high byte (offset 0Bh) is written; therefore, the high byte must be written last.
Bit 31:4 Description Pointer Field. A 16-byte aligned address must be written to this field when issuing a Self-Test command to the PORT interface.The results of the Self Test will be written to the address specified by this field. PORT Function Selection. Valid values are listed below. All other values are Reserved. 0000 = PORT Software Reset: Completely resets the LAN Controller (all CSR and PCI registers). This command should not be used when the device is active. If a PORT Software Reset is desired, software should do a Selective Reset (described below), wait for the PORT register to be cleared (completion of the Selective Reset) and then issue the PORT Software Reset command. Software should wait approximately 10 µs after issuing this command before attempting to access the LAN Controller’s registers again. 0001 = Self Test: The Self-Test begins by issuing an internal Selective Reset followed by a general internal self-test of the LAN Controller. The results of the self-test are written to memory at the address specified in the Pointer field of this register. The format of the selftest result is shown in Table 7-5. After completing the self-test and writing the results to memory, the LAN Controller will execute a full internal reset and will re-initialize to the default configuration. Self-Test does not generate an interrupt of similar indicator to the host processor upon completion. 0010 = Selective Reset: Sets the CU and RU to the Idle state, but otherwise maintains the current configuration parameters (RU and CU Base, HDSSize, Error Counters, Configure information and Individual/Multicast Addresses are preserved). Software should wait approximately 10 µs after issuing this command before attempting to access the LAN Controller’s registers again.
3:0
7-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LAN Controller Registers (B1:D8:F0)
Table 7-5. Self-Test Results Format
Bit 31:13 12 11:6 5 4 3 Reserved General Self-Test Result. 0 = Pass 1 = Fail Reserved Diagnose Result. This bit provides the result of an internal diagnostic test of the Serial Subsystem. 0 = Pass 1 = Fail Reserved Register Result. This bit provides the result of a test of the internal Parallel Subsystem registers. 0 = Pass 1 = Fail ROM Content Result. This bit provides the result of a test of the internal microcode ROM. 2 1:0 0 = Pass 1 = Fail Reserved Description
7.2.5
EEPROM Control Register
Offset Address: Default Value: 0Eh 00h Attribute: Size: RO, R/W 8 bits
The EEPROM Control Register is a 16-bit field that enables a read from and a write to the external EEPROM.
Bit 7:4 Reserved EEPROM Serial Clock (EESK)—R/W. Toggling this bit clocks data into or out of the EEPROM. Software must ensure that this bit is toggled at a rate that meets the EEPROM component’s minimum clock frequency specification. 0 = Drives the ICH2’s EE_SHCLK signal low. 1 = Drives the ICH2’s EE_SHCLK signal high. EEPROM Chip Select (EECS)—R/W. 2 0 = Drives the ICH2’s EE_CS signal low, to disable the EEPROM. this bit must be set to 0 for a minimum of 1µs between consecutive instruction cycles. 1 = Drives the ICH2’s EE_CS signal high, to enable the EEPROM. EEPROM Serial Data In (EEDI)—WO. Note that this bit represents "Data In" from the perspective of the EEPROM device. The value of this bit is written to the EEPROM when performing write operations. EEPROM Serial Data Out (EEDO)—RO. Note that this bit represents "Data Out" from the perspective of the EEPROM device. This bit contains the value read from the EEPROM when performing read operations. Description
3
1
0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
7-15
LAN Controller Registers (B1:D8:F0)
7.2.6
Management Data Interface (MDI) Control Register
Offset Address: Default Value: 10–13h 0000 0000h Attribute: Size: R/W (special) 32 bits
The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and write bits from the LAN Connect component. This register may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. The LAN Controller will only accept the command after the high byte (offset 13h) is written; therefore, the high byte must be written last.
Bit 31:30 29 Description These bits are reserved and should be set to 00b. Interrupt Enable. 1 = Enables the LAN Controller to assert an interrupt to indicate the end of an MDI cycle. 0 = Disable. 28 Ready. 1 = Set by the LAN Controller at the end of an MDI transaction. 0 = Expected to be reset by software at the same time the command is written. Opcode. These bits define the opcode: 00 = Reserved 27:26 01 = MDI write 10 = MDI read 11 = Reserved 25:21 20:16 LAN Connect Address. This field of bits contains the LAN Connect address. LAN Connect Register Address. This field of bits contains the LAN Connect Register Address. Data. In a write command, software places the data bits in this field, and the LAN Controller transfers the data to the external LAN Connect component. During a read command, the LAN Controller reads these bits serially from the LAN Connect, and software reads the data from this location.
15:0
7.2.7
Receive DMA Byte Count Register
Offset Address: Default Value:
Bit 31:0
14–17h 0000 0000h
Attribute: Size:
Description
RO 32 bits
Receive DMA Byte Count—RO. Keeps track of how many bytes of receive data have been passed into host memory via DMA.
7-16
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LAN Controller Registers (B1:D8:F0)
7.2.8
Early Receive Interrupt Register
Offset Address: Default Value: 18h 00h Attribute: Size: R/W 8 bits
The Early Receive Interrupt register allows the internal LAN Controller to generate an early interrupt depending on the length of the frame. The LAN Controller will generate an interrupt at the end of the frame, regardless of whether or not Early Receive Interrupts are enabled. Note: It is recommended that software NOT utilize this register unless receive interrupt latency is a critical performance issue in that particular software environment. Using this feature may reduce receive interrupt latency, but will also result in the generation of more interrupts, which can degrade system efficiency and performance in some environments.
Bit Description Early Receive Count—R/W. When some non-zero value x is programmed into this register, the LAN controller sets the ER bit in the SCB Status Word Register and assert INTA# when the byte count indicates that there are x quadwords remaining to be received in the current frame (based on the Type/Length field of the received frame). No Early Receive interrupt will be generated if a value of 00h (the default value) is programmed into this register.
7:0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
7-17
LAN Controller Registers (B1:D8:F0)
7.2.9
Flow Control Register
Offset Address: Default Value:
Bit 15:13 12 Reserved FC Paused Low—RO. 1 = Set when the LAN Controller receives a Pause Low command with a value greater than zero. 0 = Cleared when the FC timer reaches zero, or a Pause frame is received. FC Paused—RO. 1 = Set when the LAN Controller receives a Pause command regardless of its cause (FIFO reaching Flow Control Threshold, fetching a Receive Frame Descriptor with its Flow Control Pause bit set, or software writing a 1 to the Xoff bit). 0 = Cleared when the FC timer reaches zero. 10 FC Full—RO. 1 = Set when the LAN Controller sends a Pause command with a value greater than zero. 0 = Cleared when the FC timer reaches zero. Xoff—R/W (special). This bit should only be used if the LAN Controller is configured to operate with IEEE frame-based flow control. 1 = Writing a 1 to this bit forces the Xoff request to 1 and causes the LAN Controller to behave as if the FIFO extender is full. This bit will also be set to 1 when an Xoff request due to an "RFD Xoff" bit. 0 = This bit can only be cleared by writing a 1 to the Xon bit (bit 8 in this register). Xon—WO. This bit should only be used if the LAN Controller is configured to operate with IEEE frame-based flow control. 1 = Writing a 1 to this bit resets the Xoff request to the LAN Controller, clearing bit 9 in this register. 0 = This bit always returns 0 on reads. 7:3 Reserved Flow Control Threshold—R/W. The LAN Controller can generate a Flow Control Pause frame when its Receive FIFO is almost full. The value programmed into this field determines the number of bytes still available in the Receive FIFO when the Pause frame is generated. Free Bytes Bits 2:0 in Receive FIFO Comment 2:0 000 001 010 011 100 101 110 111 0.50 KB 1.00 KB 1.25 KB 1.50 KB 1.75 KB 2.00 KB 2.25 KB 2.50 KB Fast system (recommended default)
19–1Ah 0000h
Attribute: Size:
Description
RO, R/W (special) 16 bits
11
9
8
Slow system
7-18
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LAN Controller Registers (B1:D8:F0)
7.2.10
Power Management Driver (PMDR) Register
Offset Address: Default Value: 1Bh 00h Attribute: Size: R/WC 8 bits
The ICH2’s internal LAN Controller provides an indication in the PMDR that a wake-up event has occurred.
Bit Description Link Status Change Indication—R/WC. 1 = The link status change bit is set following a change in link status. 0 = Software clears this bit by writing a 1 to the bit location. Magic Packet—R/WC. 1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-up disable bit in the configuration command and the PME Enable bit in the Power Management Control/ Status Register. 0 = Software clears this bit by writing a 1 to the bit location. Interesting Packet—R/WC. 1 = This bit is set when an “interesting” packet is received. Interesting packets are defined by the LAN Controller packet filters. 0 = Software clears this bit by writing a 1 to the bit location. 4:1 Reserved. PME Status—R/WC. This bit is a reflection of the PME Status bit in the Power Management Control/Status Register (PMCSR). 1 = Set upon a wake-up event, independent of the PME Enable bit. 0 = Software clears this bit by writing a 1 to the bit location. This also clears the PME Status bit in the PMCSR and deasserts the PME signal.
7
6
5
0
7.2.11
General Control Register
Offset Address: Default Value:
Bit 7:4
1Ch 00h
Attribute: Size:
Description
R/W 8 bits
Reserved. These bits should be set to 0000b. LAN Connect Software Reset—R/W. 1 = Software can set this bit to force a reset condition on the LAN Connect interface. 0 = Cleared by software to begin normal LAN Connect operating mode. Software must not attempt to access the LAN Connect interface for at least 1 ms after clearing this bit. Reserved. This bit should be set to 0. Deep Power-Down on Link Down Enable. 1 = Enable. The ICH2’s internal LAN Controller may enter a deep power-down state (sub 3 mA) in the D2 and D3 power states while the link is down. In this state, the LAN Controller does not keep link integrity. This state is not supported for point-to-point connection of two end stations. 0 = Disable Reserved.
3
2
1
0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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LAN Controller Registers (B1:D8:F0)
7.2.12
General Status Register
Offset Address: Default Value:
Bit 7:3 2 Reserved. Duplex Mode. This bit indicates the wire duplex mode. 1 = Full duplex 0 = Half duplex 1 Speed. This bit indicates the wire speed: 1 = 100 Mbps 0 = 10 Mbps 0 Link Status Indication. This bit indicates the status of the link: 1 = Valid 0 = Invalid
1Dh N/A
Attribute: Size:
Description
RO 8 bits
7.2.13
Statistical Counters
The ICH2’s integrated LAN Controller provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the LAN Controller when it completes the processing of a frame (i.e., when it has completed transmitting a frame on the link or when it has completed receiving a frame). The Statistical Counters are reported to the software on demand by issuing the Dump Statistical Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit Command (CUC) field.
Table 7-6. Statistical Counters
ID Counter Transmit Good Frames Transmit Maximum Collisions (MAXCOL) Errors Transmit Late Collisions (LATECOL) Errors Description This counter contains the number of frames that were transmitted properly on the link. It is updated only after the actual transmission on the link is completed, not when the frame was read from memory as is done for the Transmit Command Block status. This counter contains the number of frames that were not transmitted because they encountered the configured maximum number of collisions. This counter contains the number of frames that were not transmitted since they encountered a collision later than the configured slot time. A transmit underrun occurs because the system bus cannot keep up with the transmission. This counter contains the number of frames that were either not transmitted or retransmitted due to a transmit DMA underrun. If the LAN Controller is configured to retransmit on underrun, this counter may be updated multiple times for a single frame. This counter contains the number of frames that were transmitted by the LAN Controller despite the fact that it detected the deassertion of CRS during the transmission. This counter contains the number of frames that were deferred before transmission due to activity on the link. This counter contains the number of transmitted frames that encountered one collision.
0
4
8
12
Transmit Underrun Errors
16
Transmit Lost Carrier Sense (CRS) Transmit Deferred Transmit Single Collisions
20 24
7-20
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LAN Controller Registers (B1:D8:F0)
Table 7-6. Statistical Counters
ID 28 Counter Transmit Multiple Collisions Transmit Total Collisions Receive Good Frames Description This counter contains the number of transmitted frames that encountered more than one collision. This counter contains the total number of collisions that were encountered while attempting to transmit. This count includes late collisions and frames that encountered MAXCOL. This counter contains the number of frames that were received properly from the link. It is updated only after the actual reception from the link is completed and all the data bytes are stored in memory. This counter contains the number of aligned frames discarded because of a CRC error. This counter is updated, if needed, regardless of the Receive Unit state. The Receive CRC Errors counter is mutually exclusive of the Receive Alignment Errors and Receive Short Frame Errors counters. This counter contains the number of frames that are both misaligned (for example, CRS deasserts on a non-octal boundary) and contain a CRC error. The counter is updated, if needed, regardless of the Receive Unit state. The Receive Alignment Errors counter is mutually exclusive of the Receive CRC Errors and Receive Short Frame Errors counters. This counter contains the number of good frames discarded due to unavailability of resources. Frames intended for a host whose Receive Unit is in the No Resources state fall into this category. If the LAN Controller is configured to Save Bad Frames and the status of the received frame indicates that it is a bad frame, the Receive Resource Errors counter is not updated. This counter contains the number of frames known to be lost because the local system bus was not available. If the traffic problem persists for more than one frame, the frames that follow the first are also lost; however, because there is no lost frame indicator, they are not counted. This counter contains the number of frames that encountered collisions during frame reception. This counter contains the number of received frames that are shorter than the minimum frame length. The Receive Short Frame Errors counter is mutually exclusive to the Receive Alignment Errors and Receive CRC Errors counters. A short frame will always increment only the Receive Short Frame Errors counter. This counter contains the number of Flow Control frames transmitted by the LAN Controller. This count includes both the Xoff frames transmitted and Xon (PAUSE(0)) frames transmitted. This counter contains the number of Flow Control frames received by the LAN Controller. This count includes both the Xoff frames received and Xon (PAUSE(0)) frames received. This counter contains the number of MAC Control frames received by the LAN Controller that are not Flow Control Pause frames. These frames are valid MAC control frames that have the predefined MAC control Type value and a valid address but has an unsupported opcode. This counter contains the number of TCO packets received by the LAN Controller. This counter contains the number of TCO packets transmitted.
32
36
40
Receive CRC Errors
44
Receive Alignment Errors
48
Receive Resource Errors
52
Receive Overrun Errors Receive Collision Detect (CDT)
56
60
Receive Short Frame Errors
64
Flow Control Transmit Pause Flow Control Receive Pause Flow Control Receive Unsupported Receive TCO Frames Transmit TCO Frames
68
72
76 78
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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LAN Controller Registers (B1:D8:F0)
The Statistical Counters are initially set to zero by the ICH2’s integrated LAN Controller after reset. They cannot be preset to anything other than zero. The LAN Controller increments the counters by internally reading them, incrementing them and writing them back. This process is invisible to the processor and PCI bus. In addition, the counters adhere to the following rules:
• The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around
to 0.
• The LAN Controller updates the required counters for each frame. It is possible for more than
one counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The LAN Controller supports all mandatory and recommend statistics functions through the status of the receive header and directly through these Statistical Counters. The processor can access the counters by issuing a Dump Statistical Counters SCB command. This provides a “snapshot”, in main memory, of the internal LAN Controller statistical counters. The LAN Controller supports 21 counters. The dump could consist of the either 16, 19, or all 21 counters, depending on the status of the Extended Statistics Counters and TCO Statistics configuration bits in the Configuration command.
7-22
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Hub Interface to PCI Bridge Registers (D30:F0)
Hub Interface to PCI Bridge Registers 8 (D30:F0)
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH2 implements the buffering and control logic between PCI and the hub interface. The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the hub interface. All register contents will be lost when core well power is removed.
8.1
Note:
.
PCI Configuration Registers (D30:F0)
Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
Table 8-1. PCI Configuration Map (HUB-PCI—D30:F0)
Offset 00–01h 02–03h 04–05h 06–07h 08h 0Ah 0Bh 0Dh 0Eh 18h 19h 1Ah 1Bh 1Ch 1Dh 1E–1Fh 20–21h 22–23h 24–25h 26–27h 30–31h 32–33h Mnemonic VID DID CMD PD_STS REVID SCC BCC PMLT HEADTYP PBUS_NUM SBUS_NUM SUB_BUS_NUM SMLT IOBASE IOLIM SECSTS MEMBASE MEMLIM PREF_MEM_BAS E PREF_MEM_MLT IOBASE_HI IOLIMIT_HI Register Name/Function Vendor ID Device ID PCI Device Command Register PCI Device Status Register Revision ID Sub Class Code Base Class Code Primary Master Latency Timer Header Type Primary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Master Latency Timer IO Base Register IO Limit Register Secondary Status Register Memory Base Memory Limit Prefetchable Memory Base Prefetchable Memory Limit I/O Base Upper 16 Bits I/O Limit Upper 16 Bits Default 8086h 244Eh (ICH2) 2448h (ICH2-M) 0001h 0080h See Note 04h 06h 00h 01h 00h 00h 00h 00h F0h 00h 0280h FFF0h 0000h 0000h 0000h 0000h 0000h Type RO RO R/W R/W RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-1
Hub Interface to PCI Bridge Registers (D30:F0)
Table 8-1. PCI Configuration Map (HUB-PCI—D30:F0) (Continued)
Offset 3Ch 3E–3Fh 40h 50–51h 70h 82h 90h 92h Mnemonic INT_LINE BRIDGE_CNT BRIDGE_CNT2 CNF MTT PCI_MAST_STS ERR_CMD ERR_STS Register Name/Function Interrupt Line Bridge Control Bridge Control 2 ICH2 Configuration Register Multi-Transaction Timer PCI Master Status Error Command Register Error Status Register Default 00h 0000h 00 0000h 20h 00h 00h 00h Type RO R/W R/W R/W R/W R/W R/W R/W
NOTE: Refer to the Specification Update for the value of the Revision ID Register
8.1.1
VID—Vendor ID Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 15:0
00–01h 8086h
Attribute: Size:
Description
RO 16 bits
Vendor Identification Number—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.
8.1.2
DID—Device ID Register (HUB-PCI—D30:F0)
Offset Address: Default Value: 02–03h 244Eh (82801BA ICH2) 2448h (82801BAM ICH2-M)
Description Device Identification Number—RO. This is a 16 bit value assigned to the ICH2 hub interface to PCI bridge (i.e., Device #2).
Attribute: Size:
RO 16 bits
Bit 15:0
8-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.3
CMD—Command Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 15:10 9 Reserved. Fast Back to Back Enable (FBE)—RO. Hardwired to 0. The ICH2 does not support this capability. SERR# Enable (SERR_EN)—R/W. 1 = Enable the ICH2 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit (offset 06h, bit 14) is set. 0 = Disable. 7 6 5 4 3 Wait Cycle Control—RO. Hardwired to 0 .Parity Error Response—R/W. 1 = The ICH2 is allowed to report parity errors detected on the hub interface. 0 = The ICH2 will ignore parity errors on the hub interface. VGA Palette Snoop—RO. Hardwired to 0. Postable Memory Write Enable (PMWE)—RO. Hardwired to 0. Special Cycle Enable (SCE)—RO. Hardwired to 0 by P2P Bridge specification. Bus Master Enable (BME)—R/W. 1 = Allows the Hub interface-to-PCI bridge to accept cycles from PCI to run on the hub interface. Note: This bit does not affect the CF8h and CFCh I/O accesses. 0 = Disable 1 Memory Space Enable (MSE)—R/W. The ICH2 provides this bit as read/writable for software only. However, the ICH2 ignores the programming of this bit, and runs hub interface memory cycles to PCI. I/O Space Enable (IOE)—R/W. The ICH2 provides this bit as read/writable for software only. However, the ICH2 ignores the programming of this bit and runs hub interface I/O cycles to PCI that are not intended for USB, IDE, or AC’97.
04–05h 0001h
Attribute: Size:
Description
R/W 16 bits
8
2
0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-3
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.4
PD_STS—Primary Device Status Register (HUB-PCI—D30:F0)
Offset Address: Default Value: 06–07h 0080h Attribute: Size: R/WC 16 bits
For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no effect.
Bit Description Detected Parity Error (DPE)—R/WC. 1 = Indicates that the ICH2 detected a parity error on the hub interface. This bit gets set even if the Parity Error Response bit (offset 04, bit 6) is not set. 0 = Software clears this bit by writing a 1 to the bit location. Received System Error (SSE)—R/WC. 1 = An address, or command parity error, or special cycles data parity error has been detected on the PCI bus, and the Parity Error Response bit (D30:F0, Offset 04h, bit 6) is set. If this bit is set because of parity error and the D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, the ICH2 will generate an NMI (or SMI# if NMI routed to SMI#) 0 = Software clears this bit by writing a 1 to the bit location. 13 Received Master Abort (RMA)—R/WC. 1 = ICH2 received a master abort from the hub interface device. 0 = Software clears this bit by writing a 1 to the bit location. Received Target Abort (RTA)—R/WC. 1 = ICH2 received a target abort from the hub interface device. The TCO logic can cause an SMI#, NMI, or interrupt based on this bit getting set. 0 = Software clears this bit by writing a 1 to the bit location. 11 Signaled Target Abort (STA)—R/WC. 1 = ICH2 signals a target abort condition on the hub interface. 0 = Software clears this bit by writing a 1 to the bit location. 10:9 DEVSEL# Timing Status—RO. 00h = Fast timing. This register applies to the hub interface; therefore, this field does not matter. Data Parity Error Detected (DPD)—R/WC. Since this register applies to the hub interface, the ICH2 must interpret this bit differently than it is in the PCI specification. 1 = ICH2 detects a parity error on the hub interface and the Parity Error Response bit in the Command Register (offset 04h, bit 6) is set. 0 = Software clears this bit by writing a 1 to the bit location. 7 6 5 4:0 Fast Back to Back—RO. Hardwired to 1. User Definable Features (UDF)—RO. Hardwired to 0. 66 MHz Capable—RO. Hardwired to 0. Reserved.
15
14
12
8
8.1.5
REVID—Revision ID Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:0
08h See bit description
Attribute: Size:
Description
RO 8 bits
Revision Identification Number—RO. 8-bit value that indicates the revision number for the ICH2 hub interface to PCI bridge. Refer to the Specification Update for the value of the Revision ID Register.
8-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.6
SCC—Sub-Class Code Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:0
0Ah 04h
Attribute: Size:
Description
RO 8 bits
Sub-Class Code—RO. This 8-bit value indicates the category of bridge for the ICH2 hub interface to PCI bridge. The code is 04h indicating a PCI-to-PCI bridge.
8.1.7
BCC—Base-Class Code Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:0
0Bh 06h
Attribute: Size:
Description
RO 8 bits
Base Class Code—RO. This 8-bit value indicates the type of device for the ICH2 hub interface to PCI bridge. The code is 06h indicating a bridge device.
8.1.8
PMLT—Primary Master Latency Timer Register (HUB-PCI—D30:F0)
Offset Address: Default Value: 0Dh 00h Attribute: Size: RO 8 bits
This register does not apply to hub interface.
Bit 7:3 2:0 Master Latency Count. Not implemented. Reserved. Description
8.1.9
HEADTYP—Header Type Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7 6:0
0Eh 01h
Attribute: Size:
Description
RO 8 bits
Multi-function Device—RO. This bit is 0 to indicate a single function device. Header Type—RO. 8-bit field identifies the header layout of the configuration space, which is a PCIto-PCI bridge in this case.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-5
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.10
PBUS_NUM—Primary Bus Number Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:0
18h 00h
Attribute: Size:
Description
RO 8 bits
Primary Bus Number—RO. This field indicates the bus number of the hub interface and is hardwired to 00h.
8.1.11
SBUS_NUM—Secondary Bus Number Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:0
19h 00h
Attribute: Size:
Description
R/W 8 bits
Secondary Bus Number—R/W. This field indicates the bus number of PCI. Note that when this number is equal to the primary bus number (i.e., bus #0), the ICH2 will run hub interface configuration cycles to this bus number as Type 1 configuration cycles on PCI.
8.1.12
SUB_BUS_NUM—Subordinate Bus Number Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit
1A 00h
Attribute: Size:
Description
R/W 8 bits
7:0
Subordinate Bus Number—R/W. This field specifies the highest PCI bus number below the hub interface to PCI bridge. If a Type 1 configuration cycle from the hub interface does not fall in the Secondary-to-Subordinate Bus ranges of Device 30, the ICH2 indicates a master abort back to the hub interface.
8.1.13
SMLT—Secondary Master Latency Timer Register (HUB-PCI—D30:F0)
Offset Address: Default Value: 1Bh 00h Attribute: Size: R/W 8 bits
This Master Latency Timer (MLT) controls the amount of time that the ICH2 continues to burst data as a master on the PCI bus. When the ICH2 starts the cycle after being granted the bus, the counter is loaded and starts counting down from the assertion of FRAME#. If the internal grant to this device is removed, then the expiration of the MLT counter results in the deassertion of FRAME#. If the internal grant has not been removed, the ICH2 can continue to own the bus.
Bit 7:3 2:0 Description Master Latency Count—R/W. This 5-bit value indicates the number of PCI clocks, in 8-clock increments, that the ICH2 remains as master of the bus. Reserved.
8-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.14
IOBASE—I/O Base Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:4
1Ch F0h
Attribute: Size:
Description
R/W 8 bits
I/O Address Base bits [15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4 KB alignment. Bits 11:0 are assumed to be padded to 000h. I/O Addressing Capability—RO. This is hardwired to 0h, indicating that the hub interface to PCI bridge does not support 32-bit I/O addressing. This means that the I/O Base Register and I/O Limit Upper Address registers must be read only.
3:0
8.1.15
IOLIM—I/O Limit Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:4
1Dh 00h
Attribute: Size:
Description
R/W 8 bits
I/O Address Limit bits [15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4 KB alignment. Bits 11:0 are assumed to be padded to FFFh. I/O Addressing Capability—RO. This is hardwired to 0h, indicating that the hub interface-to-PCI bridge does not support 32-bit I/O addressing. This means that the I/O Base Register and I/O Limit Upper Address registers must be read only.
3:0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-7
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.16
SECSTS—Secondary Status Register (HUB-PCI—D30:F0)
Offset Address: Default Value: 1E–1Fh 0280h Attribute: Size: R/W 16 bits
For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no effect.
Bit Description Detected Parity Error (DPE)—R/WC. 1 = ICH2 detected a parity error on the PCI bus. 0 = Software clears this bit by writing a 1 to the bit position. 14 Received System Error (SSE)—R/WC. 1 = SERR# assertion is received on PCI. 0 = Software clears this bit by writing a 1 to the bit position. 13 Received Master Abort (RMA)—R/WC. 1 = Hub interface to PCI cycle is master-aborted on PCI. 0 = Software clears this bit by writing a 1 to the bit position. Received Target Abort (RTA)—R/WC. 1 = Hub interface to PCI cycle is target-aborted on PCI. For “completion required” cycles from the hub interface, this event should also set the Signaled Target Abort in the Primary Status Register in this device and the ICH2 must send the “target abort” status back to the hub interface. 0 = Software clears this bit by writing a 1 to the bit position. 11 10:9 Signaled Target Abort (STA)—RO. The ICH2 does not generate target aborts. DEVSEL# Timing Status—RO. 01h = Medium timing. Data Parity Error Detected (DPD)—R/WC. 1 = The ICH2 sets this bit when all of the following three conditions are met: - The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is set 8 - USB, AC’97 or IDE is a Master - PERR# asserts during a write cycle OR a parity error is detected internally during a read cycle 0 = Software clears this bit by writing a 1 to the bit position. 7 6 5 4:0 Fast Back to Back—RO. Hardwired to 1 to indicate that the PCI to hub interface target logic is capable of receiving fast back-to-back cycles. User Definable Features (UDF)—RO. Hardwired to 0. 66 MHz Capable—RO. Hardwired to 0. Reserved.
15
12
8-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.17
MEMBASE—Memory Base Register (HUB-PCI—D30:F0)
Offset Address: Default Value: 20–21h FFF0h Attribute: Size: R/W 16 bits
This register defines the base of the hub interface to PCI non-prefetchable memory range. Since the ICH2 forwards all hub interface memory accesses to PCI, the ICH2 only uses this information for determining when not to accept cycles as a target. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB boundary.
Bit 15:4 3:0 Description Memory Address Base—R/W. Defines the base of the memory range for PCI. These 12 bits correspond to address bits 31:20. Reserved.
8.1.18
MEMLIM—Memory Limit Register (HUB-PCI—D30:F0)
Offset Address: Default Value: 22–23h 0000h Attribute: Size: R/W 16 bits
This register defines the upper limit of the hub interface to PCI non-prefetchable memory range. Since the ICH2 will forward all hub interface memory accesses to PCI, the ICH2 will only use this information for determining when not to accept cycles as a target. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be aligned to a 1 MB boundary.
Bit 15:4 3:0 Description Memory Address Limit—R/W. Defines the top of the memory range for PCI. These 12 bits correspond to address bits 31:20. Reserved.
8.1.19
PREF_MEM_BASE—Prefetchable Memory Base Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 15:4 3:0
24h–25h 0000FFF0h
Attribute: Size:
Description
R/W 16-bit
Prefetchable Memory Address Base—R/W. Defines the base address of the prefetchable memory address range for PCI. These 12 bits correspond to address bits 31:20. Reserved. RO.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-9
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.20
PREF_MEM_MLT—Prefetchable Memory Limit Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 15:4 3:0
26h–27h 00000000h
Attribute: Size:
Description
R/W 16-bit
Prefetchable Memory Address Limit—RW. Defines the limit address of the prefetchable memory address range for PCI. These 12 bits correspond to address bits 31:20. Reserved. RO
8.1.21
IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 15:0
30–31h 0000h
Attribute: Size:
Description
RO 16 bits
I/O Address Base Upper 16 bits [31:16]—RO. Not supported; hardwired to 0.
8.1.22
IOLIM_HI—I/O Limit Upper 16 Bits Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 15:0
32–33h 0000h
Attribute: Size:
Description
RO 16 bits
I/O Address Limit Upper 16 bits [31:16]—RO. Not supported; hardwired to 0.
8.1.23
INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:0
3Ch 00h
Attribute: Size:
Description
RO 8 bits
Interrupt Line Routing—RO. Hardwired to 00h. The bridge does not generate interrupts, and interrupts from downstream devices are routed around the bridge.
8-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.24
BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 15:8 7 6 5 4 Reserved. Fast Back to Back Enable—RO. Hardwired to 0. The PCI logic will not generate fast back-to-back cycles on the PCI bus. Secondary Bus Reset—RO. hardwired to 0. The ICH2 does not follow the P2P bridge reset scheme; Software-controlled resets are implemented in the PCI-LPC device. Master Abort Mode—R/W. The ICH2 ignores this bit. However, this bit is read/write for software compatibility. The ICH2 must handle master aborts as if this bit is reset to 0. Reserved. VGA Enable—R/W. 1 = Enable. Indicates that the VGA device is on PCI. Therefore, the PCI to hub interface decoder will not accept memory cycles in the range A0000h–BFFFFh. Note that the ICH2 will never take I/O cycles in the VGA range from PCI. 0 = No VGA device on PCI. 2 ISA Enable—R/W. The ICH2 ignores this bit. However, this bit is read/write for software compatibility. Since the ICH2 forwards all I/O cycles that are not in the USB, AC’97, or IDE ranges to PCI, this bit would have no effect. SERR# Enable—R/W. 1 = Enable. If this bit is set AND bit 8 in CMD register (D30:F0 Offset 04h) is also set, the ICH2 sets the SSE bit in PD_STS register (D30:F0, offset 06h, bit 14) AND also generate an NMI (or SMI# if NMI routed to SMI) when the SERR# signal is asserted. 0 = Disable Parity Error Response Enable—R/W. 0 1 = Enable the hub interface to PCI bridge for parity error detection and reporting on the PCI bus. 0 = Disable
3E–3Fh 0000h
Attribute: Size:
Description
R/W 16 bits
3
1
8.1.25
BRIDGE_CNT2—Bridge Control Register 2 (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:1 0 Reserved PCI_DAC_EN—R/W. Allows ICH2 to recognize external PCI masters performing DAC on PCI. 0 = Disable. 1 = Enable.
40h 00h
Attribute: Size
Description
R/W 8 bits
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-11
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.26
CNF—ICH2 Configuration Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 15:10 9 Reserved. HP_PCI_EN—R/W. High Priority PCI Enable. 1 = Enables a mode where the REQ[0]#/GNT[0]# signal pair has a higher arbitration priority. 0 = All PCI REQ#/GNT pairs have the same arbitration priority. Hole Enable (15 MB–16 MB)—R/W. 1 = Enables the 15 MB to 16 MB hole in the DRAM. 0 = Disable Reserved. Discard Timer Mode. This bit shortens all of the Delayed Transaction discard timers to 128 PCI clocks. It controls how long the ICH2-M will wait before flushing previously requested prefetched read data due to a Delayed Transaction, and then servicing a different request. 0 = 1024 PCI clocks (32 us) (Default). 1 = 128 PCI clocks (4 us). 32-Clock Retry Enable—R/W. System BIOS must set this bit for PCI compliance. 1 = When a PCI device is running a locked memory read cycle, while all other bus masters are waiting to run locked cycles, concurrent with a LPC DMA transfer, this bit, when set allows the ICH2 to retry the locked memory read cycle. 0 = If this bit is not set, under the same circumstance, the bus will not be released since all other masters see the lock in use. Reserved.
50–51h 0000h
Attribute: Size:
Description
R/W 16 bits
8 7:3
2
1
0
8.1.27
MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0)
Offset Address: Default Value: 70h 20h Attribute: Size: R/W 8 bits
MTT is an 8-bit register that controls the amount of time that the ICH2’s arbiter allows a PCI initiator to perform multiple back-to-back transactions on the PCI bus. The ICH2’s MTT mechanism is used to guarantee a fair share of the Primary PCI bandwidth to an initiator that performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers). The number of clocks programmed in the MTT represents the guaranteed time slice (measured in PCI clocks) allotted to the current agent, after which the arbiter grants another agent that is requesting the bus. The MTT value must be programmed with 8 clock granularity in the same manner as MLT. For example, if the MTT is programmed to 18h, the selected value corresponds to the time period of 24 PCI clocks.The default value of MTT is 20h (32 PCI clocks). Note: Programming the MTT to a value of 00h disables this function, which could cause starvation issues for some PCI master devices. Programming of the MTT to anything less than 16 clocks will not allow the Grant-to-FRAME# latency to be 16 clocks. The MTT timer will time-out before the Grant-to-FRAME# trigger causing a re-arbitration.
Bit 7:3 2:0 Description Multi-Transaction Timer Count Value—R/W. This field specifies the amount of time that grant remains asserted to a master continuously asserting its request for multiple transfers. This field specifies the count in an 8-clock (PCI clock) granularity. Reserved.
8-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.28
PCI_MAST_STS—PCI Master Status Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit
82h 00h
Attribute: Size:
Description
R/WC 8 bits
7
Internal PCI Master Request Status (INT_MREQ_STS)—R/WC. 1 = The ICH2’s internal DMA controller or LPC has requested use of the PCI bus. 0 = Software clears this bit by writing a 1 to the bit position. Internal LAN Master Request Status (LAN_MREQ_STS)—R/WC. 1 = The ICH2’s internal LAN controller has requested use of the PCI bus. 0 = Software clears this bit by writing a 1 to the bit position. PCI Master Request Status (PCI_MREQ_STS)—R/WC. Allows software to see if a particular bus master has requested use of the PCI bus. For example, bit 0 will be set if ICH2 has detected REQ[0]# asserted and bit 5 will be set if ICH2 detected REQ[5]# asserted. 1 = The associated PCI master has requested use of the PCI bus. 0 = Software clears these bits by writing a 1 to the bit position.
6
5:0
8.1.29
ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
Offset Address: Default Value: Lockable: 90h 00h No Attribute: Size: Power Well: R/W 8-bit Core
This register configures the ICH2’s Device 30 responses to various system errors. The actual assertion of the internal SERR# (routed to cause NMI# or SMI#) is enabled via the PCI Command register.
Bit 7:3 2 Reserved. SERR# enable on receiving target abort (SERR_RTA_EN)—R/W. 1 = Enable. When SERR_EN is set, the ICH2 will report SERR# when SERR_RTA is set. 0 = Disable 1 0 SERR# enable on Delayed Transaction Time-out (SERR_DTT_EN)—R/W. 1 = Enable. When SERR_EN is set, the ICH2 will report SERR# when SERR_DTT is set. 0 = Disable. Reserved. Description
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-13
Hub Interface to PCI Bridge Registers (D30:F0)
8.1.30
ERR_STS—Error Status Register (HUB-PCI—D30:F0)
Offset Address: Default Value: Lockable: 92h 00h No Attribute: Size: Power Well: R/W 8-bit Core
This register records the cause of system errors in Device 30. The actual assertion of SERR# is enabled via the PCI Command register.
Bit 7:3 Reserved. SERR# Due to Received Target Abort (SERR_RTA)—R/W. 1 = The ICH2 sets this bit when the ICH2 receives a target abort. If SERR_EN, the ICH2 will also generate an SERR# when SERR_RTA is set. 0 = This bit is cleared by writing a 1. SERR# Due to Delayed Transaction Time-out (SERR_DTT)—R/W. 1 = When a PCI master does not return for the data within 1 ms of the cycle’s completion, the ICH2 clears the delayed transaction, and sets this bit. If both SERR_DTT_EN and SERR_EN are set, then ICH2 will also generate an SERR# when SERR_DTT is set. 0 = This bit is cleared by writing a 1. 0 Reserved. Description
2
1
8-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
LPC Interface Bridge Registers (D31:F0)
9
The LPC Bridge function of the ICH2 resides in PCI Device 31:Function 0. This function contains many other functional units (e.g., DMA and Interrupt Controllers, Timers, Power Management, System Management., GPIO, RTC, and LPC Configuration Registers). Registers and functions associated with other functional units (power management, GPIO, USB, IDE, etc.) are described in their respective sections.
9.1
Note:
.
PCI Configuration Registers (D31:F0)
Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
Table 9-1. PCI Configuration Map (LPC I/F—D31:F0)
Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 0Eh 40h–43h 44h 4Eh–4Fh 54h 58h–5Bh 5Ch 60h–63h 64h 68h–6Bh 88h 8Ah 90h–91h A0h–CFh Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC HEADT PMBASE ACPI_CNTL BIOS_CNTL TCO_CNTL GPIO_BASE GPIO_CNTL PIRQ[n]_ROUT SIRQ_CNTL PIRQ[n]_ROUT D31_ERR_CFG D31_ERR_STS PCI_DMA_C Vendor ID Device ID PCI Command Register PCI Device Status Register Revision ID Programming Interface Sub Class Code Base Class Code Header Type ACPI Base Address Register ACPI Control BIOS Control Register TCO Control GPIO Base Address Register GPIO Control Register PIRQ[A–D] Routing Control Serial IRQ Control Register PIRQ[E–H] Routing Control Device 31 Error configuration Register Device 31 Error Status Register PCI DMA Configuration Registers Power Management Registers See Section 9.8.1 Register Name Default 8086h 2440h (ICH2) 244Ch (ICH2-M) 000Fh 0280h See Note 00h 01h 06h 80h 00000001h 00h 0000h 00h 00000001h 00h 80808080h 10h 80808080h 00h 00h 0000h Type RO RO R/W R/W RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-1
LPC Interface Bridge Registers (D31:F0)
Table 9-1. PCI Configuration Map (LPC I/F—D31:F0) (Continued)
Offset D0h–D3h D4h–D7h D8h E0h E1h E2h E3h E4h–E5h E6h–E7h E8h–EBh ECh–EDh EEh–EFh F0h F2h Mnemonic GEN_CNTL GEN_STS RTC_CONF COM_DEC LPCFDD_DEC SND_DEC FWH_DEC_EN1 GEN1_DEC LPC_EN FWH_SEL1 GEN2_DEC FWH_SEL2 FWH_DEC_EN2 FUNC_DIS Register Name General Control General Status Real Time Clock Configuration LPC I/F COM Port Decode Ranges LPC I/F FDD & LPT Decode Ranges LPC I/F Sound Decode Ranges FWH Decode Enable 1 LPC I/F General 1 Decode Range LPC I/F Enables FWH Select 1 LPC I/F General 2 Decode Range FWH Select 2 FWH Decode Enable 2 Function Disable Register Default 00000000h 00000F00h 00h 00h 00h 00h FFh 0000h 00h 00112233h 0000h 5678h 0Fh 00h Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
NOTE: Refer to the Specification Update for the value of the Revision ID Register.
9.1.1
VID—Vendor ID Register (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 15:0
00–01h 8086h No
Attribute: Size: Power Well:
Description
RO 16-bit Core
Vendor ID Value. This is a 16 bit value assigned to Intel. Intel VID = 8086h
9.1.2
DID—Device ID Register (LPC I/F—D31:F0)
Offset Address: Lockable: Default Value: 02–03h No 2440h (82801BA ICH2) 244Ch (82801BAM ICH2-M) Attribute: Size: Power Well: RO 16-bit Core
Bit 15:0
Description Device ID Value. This is a 16 bit value assigned to the ICH2 LPC Bridge.
9-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.3
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 15:10 9 8 7 6 5 4 3 2 1 0 Reserved. Fast Back to Back Enable (FBE)—RO. Hardwired to 0. SERR# Enable (SERR_EN)—R/W. 1 = Enable. Allow SERR# to be generated. 0 = Disable. Wait Cycle Control (WCC)—RO. Hardwired to 0. Parity Error Response (PER)—R/W. 1 = The ICH will take normal action when a parity error is detected. 0 = No action is taken when detecting a parity error. VGA Palette Snoop (VPS)—RO. Hardwired to 0 Postable Memory Write Enable (PMWE)—RO. Hardwired to 0 Special Cycle Enable (SCE). Hardwired to 1. Bus Master Enable (BME)—RO. Hardwired to 1 to indicate that bus mastering can not be disabled for function 0 (DMA/ISA Master). Memory Space Enable (MSE)—RO. Hardwired to 1 to indicate that memory space can not be disabled for Function 0 (LPC I/F). I/O Space Enable (IOE)—RO. Hardwired to 1 to indicate that the I/O space cannot be disabled for function 0 (LPC I/F).
04–05h 000Fh No
Attribute: Size: Power Well:
Description
R/W 16-bit Core
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-3
LPC Interface Bridge Registers (D31:F0)
9.1.4
PCISTS—PCI Device Status (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit
06–07h 0280h No
Attribute: Size:16-bit Power Well:
Description
R/WC Core
15
Detected Parity Error (DPE)—R/W. 1 = PERR# signal goes active. Set even if the PER bit is 0. 0 = This bit is cleared by software writing a 1 to the bit position. Signaled System Error (SSE)—R/W. 1 = Set by the ICH2 if the SERR_EN bit is set and the ICH2 generates an SERR# on function 0. The ERR_STS register can be read to determine the cause of the SERR#. The SERR# can be routed to cause SMI#, NMI, or interrupt. 0 = This bit is cleared by software writing a 1 to the bit position. Master Abort Status (RMA)—R/W. 1 = ICH2 generated a master abort on PCI due to LPC I/F master or DMA cycles. 0 = This bit is cleared by software writing a 1 to the bit position. Received Target Abort (RTA)—R/W. 1 = ICH2 received a target abort during LPC I/F master or DMA cycles to PCI. 0 = This bit is cleared by software writing a 1 to the bit position. Signaled Target Abort (STA)—R/W. 1 = ICH2 generated a target abort condition on PCI cycles claimed by the ICH2 for ICH2 internal registers or for going to LPC I/F. 0 = This bit is cleared by software writing a 1 to the bit position. DEVSEL# Timing Status (DEV_STS)—RO. 01 = Medium Timing. Data Parity Error Detected (DPED)—R/WC. 1 = Set when all three of the following conditions are true: - The ICH2 is the initiator of the cycle, - The ICH2 asserted PERR# (for reads) or observed PERR# (for writes), and - The PER bit is set. 0 = This bit is cleared by software writing a 1 to the bit position. Fast Back to Back (FB2B)—RO. Always 1. Indicates ICH2 as a target can accept fast back-to-back transactions. User Definable Features (UDF). Hardwired to 0 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0 Reserved.
14
13
12
11
10:9
8
7 6 5 4:0
9.1.5
REVID—Revision ID Register (LPC I/F—D31:F0)
Offset Address: Default Value:
Bit 7:0
08h See bit description
Attribute: Size:
Description
RO 8 bits
Revision Identification Number. 8-bit value that indicates the revision number for the LPC bridge. For the A-0 stepping, this value is 00h. Refer to the Specification Update for the value of the Revision ID Register
9-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.6
PI—Programming Interface (LPC I/F—D31:F0)
Offset Address: Default Value:
Bit 7:0 Programming Interface Value.
09h 00h
Attribute: Size:
Description
RO 8 bits
9.1.7
SCC—Sub-Class Code Register (LPC I/F—D31:F0)
Offset Address: Default Value:
Bit 7:0
0Ah 01h
Attribute: Size:
Description
RO 8 bits
Sub-Class Code. This 8-bit value indicates the category of bridge for the LPC PCI bridge.
9.1.8
BCC—Base-Class Code Register (LPC I/F—D31:F0)
Offset Address: Default Value:
Bit 7:0
0Bh 06h
Attribute: Size:
Description
RO 8 bits
Base Class Code. This 8-bit value indicates the type of device for the LPC bridge. The code is 06h indicating a bridge device.
9.1.9
HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: Default Value:
Bit 7 6:0
0Eh 80h
Attribute: Size:
Description
RO 8 bits
Multi-function Device—RO. This bit is 1 to indicate a multi-function device. Header Type—RO. This 8-bit field identifies the header layout of the configuration space.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-5
LPC Interface Bridge Registers (D31:F0)
9.1.10
PMBASE—ACPI Base Address (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable: 40–43h 00000001h No Attribute: Size: Usage: Power Well: R/W 32-bit ACPI, Legacy Core
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. Can be mapped anywhere in the 64 KB I/O space on 128-byte boundaries.
Bit 31:16 15:7 6:1 0 Reserved. Base Address—R/W. Provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic. This is placed on a 128-byte boundary. Reserved. Resource Indicator—RO. Tied to 1 to indicate I/O space. Description
9.1.11
ACPI_CNTL—ACPI Control (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable: 44h 00h No Attribute: Size: Usage: Power Well:
Description Reserved. ACPI Enable (ACPI_EN)—R/W. 1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power management function is enabled. Note that the APM power management ranges (B2/B3h) are always enabled and are not affected by this bit. 0 = Disable. 3 Reserved. SCI IRQ Select (SCI_IRQ_SEL)—R/W. Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed to IRQ[9:11], and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ[20:23], and can be shared with other interrupts. 000 = IRQ9 001 = IRQ10 2:0 010 = IRQ11 011 = Reserved 100 = IRQ20 (Only available if APIC enabled) 101 = IRQ21 (Only available if APIC enabled) 110 = RQ22 (Only available if APIC enabled) 111 = IRQ23 (Only available if APIC enabled)
R/W 8-bit ACPI, Legacy Core
Bit 7:5
4
9-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.12
BIOS_CNTL (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 15:2 Reserved. BIOS Lock Enable (BLE)—R/W. 1 = Enables setting the BIOSWE bit to cause SMIs. 0 = Setting the BIOSWE will not cause SMIs. Once set, this bit can only be cleared by a PCIRST#. BIOS Write Enable (BIOSWE)—R/W. 1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written from a 0 to a 1 and BIOS lock Enable (BLE) is also set, an SMI# is generated. This ensures that only SMM code can update BIOS. 0 = Only read cycles result in FWH interface cycles.
4E–4Fh 0000h No
Attribute: Size: Power Well:
Description
R/W 16-bit Core
1
0
9.1.13
TCO_CNTL—TCO Control (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 7:4 3 Reserved. TCO Interrupt Enable (TCO_INT_EN)—R/W. This bit enables/disables the TCO interrupt. 1 = Enables TCO Interrupt, as selected by the TCO_INT_SEL field. 0 = Disables TCO interrupt. TCO Interrupt Select (TCO_INT_SEL)—R/W. Specifies which IRQ the TCO internally appears. If not using the APIC, the TCO interrupt must be routed to IRQ[9:11], and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ[20:23], and can be shared with other interrupt. Note that if the TCOSCI_EN bit is set (bit 6 in the GPE0_EN register), then the TCO interrupt will be sent to the same interrupt as the SCI, and the TCO_INT_SEL bits will have no meaning. When the TCO interrupt is mapped to APIC interrupts 10 or 11, the signal is, in fact, active high. When the TCO interrupt is mapped to IRQ[20, 21, or 22], the signal is active low and can be shared with PCI interrupts that may be mapped to the same signals (IRQs). 2:0 000 = IRQ9 001 = IRQ10 010 = IRQ11 011 = Reserved 100 = IRQ20 (Only available if APIC enabled) 101 = IRQ21 (Only available if APIC enabled) 110 = IRQ22 (Only available if APIC enabled) 111 = IRQ23 (Only available if APIC enabled)
54h 00h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-7
LPC Interface Bridge Registers (D31:F0)
9.1.14
GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 31:16 15:6 5:1 0 Reserved. Base Address—R/W. Provides the 64 bytes of I/O space for GPIO. Reserved. Resource Indicator—RO. Tied to 1 to indicate I/O space.
58h–5Bh 00000001h No
Attribute: Size: Power Well:
Description
R/W 32-bit Core
9.1.15
GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 7:5 Reserved. GPIO Enable (GPIO_EN)—R/W. This bit enables/disables decode of the I/O range pointed to by the GPIO base register and enables/disables the GPIO function. 1 = Enable 0 = Disable 3:0 Reserved.
5Ch 00h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
4
9.1.16
PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit
PIRQA–60h, PIRQB–61h, PIRQC–62h, PIRQD–63h 80h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
7
Interrupt Routing Enable (IRQEN)—R/W. Note that BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259.
6:4
Reserved. IRQ Routing—R/W. (ISA compatible) 0000 = Reserved 0001 = Reserved 0010 = Reserved 0011 = IRQ3 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 1000 = Reserved 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1100 = IRQ12 1101 = Reserved 1110 = IRQ14 1111 = IRQ15
3:0
9-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.17
SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit
64h 10h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
7
Serial IRQ Enable (SIRQEN)—R/W. 1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ. 0 = The buffer is input only and internally SERIRQ will be a 1. Serial IRQ Mode Select (SIRQMD)—R/W. For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one frame after coming out of reset before switching back to Quiet Mode. Failure to do so will result in the ICH2 not recognizing SERIRQ interrupts. 1 = The serial IRQ machine will be in continuous mode. 0 = The serial IRQ machine will be in quiet mode. Serial IRQ Frame Size (SIRQSZ)—R/W. Fixed field that indicates the size of the SERIRQ frame. In the ICH2, this field needs to be programmed to 21 frames (0100). This is an offset from a base of 17 which is the smallest data frame size. Start Frame Pulse Width (SFPW)—R/W. This is the number of PCI clocks that the SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the ICH2 will drive the start frame for the number of clocks specified. In quiet mode, the ICH2 will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral.
6
5:2
1:0
00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = Reserved
9.1.18
PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit
PIRQE–68h, PIRQF–69h, PIRQG–6Ah, PIRQH–6Bh 80h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
7
Interrupt Routing Enable (IRQEN)—R/W. Note that BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259.
6:4
Reserved. IRQ Routing—R/W. (ISA compatible) 0000 = Reserved 0001 = Reserved 0010 = Reserved 1000 = Reserved 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1100 = IRQ12 1101 = Reserved 1110 = IRQ14 1111 = IRQ15
3:0
0011 = IRQ3 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-9
LPC Interface Bridge Registers (D31:F0)
9.1.19
D31_ERR_CFG—Device 31 Error Configuration Register (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable: 88h 00h No Attribute: Size: Power Well: R/W 8-bit Core
.
This register configures the ICH2’s Device 31 responses to various system errors. The actual assertion of SERR# is enabled via the PCI Command register
Bit 7:3 2 Reserved. SERR# on Received Target Abort Enable (SERR_RTA_EN)—R/W. 1 = The ICH2 will generate SERR# when SERR_RTA is set if SERR_EN is set. 0 = Disable. No SERR# assertion on Received Target Abort. 1 0 SERR# on Delayed Transaction Time-out Enable (SERR_DTT_EN)—R/W. 1 = The ICH2 will generate SERR# when SERR_DTT bit is set if SERR_EN is set. 0 = Disable. No SERR# assertion on Delayed Transaction Time-out. Reserved Description
9.1.20
D31_ERR_STS—Device 31 Error Status Register (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable: 8Ah 00h No Attribute: Size: Power Well: R/WC 8-bit Core
This register configures the ICH2’s Device 31 responses to various system errors. The actual assertion of SERR# is enabled via the PCI Command register.
Bit 7:3 Reserved. SERR# Due to Received Target Abort (SERR_RTA)—R/WC. 1 = The ICH2 sets this bit when it receives a target abort. If SERR_EN, the ICH2 will also generate an SERR# when SERR_RTA is set. 0 = Software clears this bit by writing a 1 to the bit location. SERR# Due to Delayed Transaction Time-out (SERR_DTT)—R/WC. 1 = When a PCI master does not return for the data within 1 ms of the cycle’s completion, the ICH2 clears the delayed transaction and sets this bit. If both SERR_DTT_EN and SERR_EN are set, then ICH2 will also generate an SERR# when SERR_DTT is set. 0 = Software clears this bit by writing a 1 to the bit location. 0 Reserved. Description
2
1
9-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.21
PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit Channel 7 Select—R/W. 00 = Reserved 15:14 01 = PC/PCI DMA 10 = Reserved 11 = LPC I/F DMA 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Channel 6 Select—R/W. Same bit decode as for Channel 7 Channel 5 Select—R/W. Same bit decode as for Channel 7 Reserved. Channel 3 Select—R/W. Same bit decode as for Channel 7 Channel 2 Select—R/W. Same bit decode as for Channel 7 Channel 1 Select—R/W. Same bit decode as for Channel 7 Channel 0 Select—R/W. Same bit decode as for Channel 7
90h–91h 0000h No
Attribute: Size: Power Well:
Description
R/W 16-bit Core
9.1.22
GEN_CNTL—General Control Register (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 31:26 Reserved. REQ[5]#/GNT[5]# PC/PCI protocol select (PCPCIB_SEL)—R/W. 1 = When this bit is set to a 1, the PCI REQ[5]#/GNT[5]# signal pair will use the PC/PCI protocol as REQ[B]#/GNT[B]. The corresponding bits in the GPIO_USE_SEL register must also be set to a 0. If the corresponding bits in the GPIO_USE_SEL register are set to a 1, the signals will be used as a GPI and GPO. 0 = The REQ[5]#/GNT[5]# pins will function as a standard PCI REQ/GNT signal pair. Hide ISA Bridge (HIDE_ISA)—R/W. 1 = Software sets this bit to 1 to disable configuration cycle from being claimed by a PCI-to-ISA bridge. This prevents the operating system PCI PnP from getting confused by seeing two ISA bridges. It is required for the ICH2 PCI address line AD22 to connect to the PCI-to-ISA bridge’s IDSEL input. When this bit is 1, the ICH2 does not assert AD22 during configuration cycles to the PCI-to-ISA bridge. 0 = The ICH2 does not prevent AD22 from asserting during configuration cycles to the PCI-to-ISA bridge. 23:14 Reserved. Coprocessor Error Enable (COPR_ERR_EN)—R/W. 1 = When FERR# is low, ICH2 generates IRQ13 internally and holds it until an I/O write to port F0h. It will also drive IGNNE# active. 0 = FERR# will not generate IRQ13 nor IGNNE#. 12 Keyboard IRQ1 Latch Enable (IRQ1LEN)—R/W. 1 = The active edge of IRQ1 will be latched and held until a port 60h read. 0 = IRQ1 will bypass the latch.
D0h–D3h 00000000h No
Attribute: Size: Power Well:
Description
R/W 32-bit Core
25
24
13
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-11
LPC Interface Bridge Registers (D31:F0)
Bit
Description Mouse IRQ12 Latch Enable (IRQ12LEN)—R/W. 1 = The active edge of IRQ12 will be latched and held until a port 60h read. 0 = IRQ12 will bypass the latch. Reserved APIC Enable (APIC_EN)—R/W. 1 = Enables the internal I/O (x) APIC and its address decode. 0 = Disables internal I/O (x) APIC. Enables I/O (x) Extension Enable (XAPIC_EN)—R/W. Note that this bit is only valid if the AIPC_EN bit (bit 8) is also set to 1. 1 = Enables the extra features (beyond standard I/O APIC) associated with the I/O (x) APIC. 0 = The I/O (x) APIC extensions are not supported. Alternate Access Mode Enable (ALTACC_EN)—R/W. 1 = Alternate Access Mode Enable 0 = Alternate Access Mode Disabled (default). Alternate Access Mode allows reads to otherwise unreadable registers and writes otherwise unwriteable registers. Reserved. DMA Collection Buffer Enable (DCB_EN)—R/W. 1 = Enables DMA Collection Buffer (DCB) for LPC I/F and PC/PCI DMA. 0 = DCB disabled. Delayed Transaction Enable (DTE)—R/W. 1 = ICH2 enables delayed transactions for internal register, FWH, and LPC interface accesses. 0 = Delayed transactions disabled. Positive Decode Enable (POS_DEC_EN)—R/W. 1 = Enables ICH2 to only perform positive decode on the PCI bus.
11 10:9 81
71
6
5:3 2
1
0
0 = The ICH2 performs subtractive decode on the PCI bus and forward the cycles to LPC interface if not to an internal register or other known target on the LPC interface. Accesses to internal registers and to known LPC interface devices are still be positively decoded.
NOTES: 1. Rule 1: If bit 8 is 0, the ICH2 does not decode any of the registers associated with the I/O APIC or I/O (x) APIC. The state of bit 7 is a “Don’t Care” in this case. Rule 2: If bit 8 is 1 and bit 7 is 0, the ICH2 decodes the memory space associated with the I/O APIC, but not the extra registers associated with the I/O (x) APIC. Rule 3: If bit 8 is 1 and bit 7 is 1, the ICH2 decodes the memory space associated with both the I/O APIC and the I/O (x) APIC. This also enables PCI masters to write directly to the register to cause interrupts (PCI Message Interrupt). Note that there is no separate way to disable PCI Message Interrupts if the I/O (x) APIC is enabled. This is not considered necessary.
9-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.23
GEN_STS—General Status (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 31:14 Reserved. TOP_SWAP—R/W. 1 = ICH2 will invert A16 for cycles targeting FWH BIOS space (Does not affect accesses to FWH feature space). 0 = ICH2 will not invert A16. This bit is cleared by RTCRST# assertion, but not by any other type of reset. CPU BIST Enable (CPU_BIST_EN)—R/W. This bit is in the Resume Well and is reset by RSMRST# (not in the RTC Well and not reset by RTEST#). 1 = The INIT# signal is driven active when CPURST# is active. INIT# goes inactive with the same timings as the other processor interface signals (Hold Time after CPURST# inactive). Note that CPURST# is generated by the memory controller hub; however, the ICH2 has a hub interface special cycle that allows the ICH2 to control the assertion/deassertion of CPURST#. 0 = Disable. Processor Frequency Strap (FREQ_STRAP[3:0])—R/W. These bits determine the internal frequency multiplier of the processor. These bits can be reset to 1111 based on an external pin strap or via the RTCRST# input signal. Software must program this field based on the processor’s specified frequency. These bits are in the RTC well. This field is only writeable when SAFE_MODE (bit 2) is cleared to 0. SAFE_MODE is only cleared by a PWROK rising edge. 7:3 Reserved SAFE_MODE—RO. 1 = ICH2 sampled AC_SDOUT high on the rising edge of PWROK. ICH2 will force FREQ_STRAP[3:0] bits to all 1s (safe mode multiplier). 0 = ICH2 sampled AC_SDOUT low on the rising edge of PWROK. NO_REBOOT—R/W (special). 1 = ICH2 will disable the TCO Timer system reboot feature. This bit is set either by hardware when SPKR is sampled low on the rising edge of PWROK or by software writing a 1 to the bit. 0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO time-out). Note that this bit cannot be cleared while an external jumper is in place on the SPKR signal. 0 Reserved.
D4h–D7h 00000F0Xh No
Attribute: Size: Power Well:
Description
R/W 32-bit Core(0:7), RTC (8:15)
13
12
11:8
2
1
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-13
LPC Interface Bridge Registers (D31:F0)
9.1.24
RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 7:5 Reserved. Upper 128-byte Lock (U128LOCK)—R/W (special). 1 = Lock reads and writes to bytes 38h–3Fh in the upper 128 byte bank of the RTC CMOS RAM. Write cycles to this range will have no effect and read cycles will not return any particular guaranteed value. This is a write once register that can only be reset by a hardware reset. 0 = Access to these bytes in the upper CMOS RAM range have not been locked. Lower 128-byte Lock (L128LOCK)—R/W (special). 1 = Locks reads and writes to bytes 38h–3Fh in the lower 128 byte bank of the RTC CMOS RAM. Write cycles to this range will have no effect and read cycles will not return any particular guaranteed value. This is a write once register that can only be reset by a hardware reset. 0 = Access to these bytes in the lower CMOS RAM range have not been locked. 2 1:0 Upper 128-byte Enable (U128E)—R/W. 1 = Enables access to the upper 128 byte bank of RTC CMOS RAM. 0 = Disable. Reserved.
D8h 00h Yes
Attribute: Size: Power Well:
Description
R/W 8-bit Core
4
3
9.1.25
COM_DEC—LPC I/F Communication Port Decode Ranges (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 7 Reserved COMB Decode Range—R/W. This field determines which range to decode for the COMB Port. 000 = 3F8h–3FFh (COM1) 001 = 2F8h–2FFh (COM2) 010 = 220h–227h 011 = 228h–22Fh 100 = 238h–23Fh 101 = 2E8h–2EFh (COM4) 110 = 338h–33Fh 111 = 3E8h–3EFh (COM3) Reserved COMA Decode Range—R/W. This field determines which range to decode for the COMA Port. 000 = 3F8h–3FFh (COM1) 001 = 2F8h–2FFh (COM2) 010 = 220h–227h 011 = 228h–22Fh 100 = 238h–23Fh 101 = 2E8h–2EFh (COM4) 110 = 338h–33Fh 111 = 3E8h–3EFh (COM3)
E0h 00h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
6:4
3
2:0
9-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.26
FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 7:5 4 3:2 Reserved FDD Decode Range—R/W. Determines which range to decode for the FDD Port 0 = 3F0h–3F5h, 3F7h (Primary) 1 = 370h–2FFh (Secondary) Reserved LPT Decode Range—R/W. This field determines which range to decode for the LPT Port. 00 = 378h–37Fh and 778h–77Fh 1:0 01 = 278h–27Fh (port 279h is read only) and 678h–67Fh 10 = 3BCh–3BEh and 7BCh–7BEh 11 = Reserved
E1h 00h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
9.1.27
SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 7:6 Reserved MSS Decode Range—R/W. This field determines which range to decode for the Microsoft* Sound System (MSS). 00 = 530h–537h 5:4 01 = 604h–60Bh 10 = E80h–E87h 11 = F40h–F47h MIDI Decode Range—R/W. This bit determines which range to decode for the Midi Port. 3 2 0 = 330h–331h 1 = 300h–301h Reserved SB16 Decode Range—R/W. This field determines which range to decode for the Sound Blaster 16 (SB16) Port. 00 = 220h–233h 1:0 01 = 240h–253h 10 = 260h–273h 11 = 280h–293h
E2h 00h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-15
LPC Interface Bridge Registers (D31:F0)
9.1.28
FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—D31:F0)
Offset Address: Default Value: E3h FFh Attribute: Size: R/W 8 bits
This register determines which memory ranges will be decoded on the PCI bus and forwarded to the FWH. The ICH2 will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1.
Bit Description FWH Address Range Enable (FWH_F8_EN)—RO. Enables decoding two 512 KB FWH memory ranges and one 128 KB memory range. 1 = Enable the following ranges for the FWH FFF80000h–FFFFFFFFh FFB80000h–FFBFFFFFh 000E0000h–000FFFFFh FWH Address Range Enable (FWH_F0_EN)—R/W. Enables decoding two 512 KB FWH memory ranges. 6 0 = Disable. 1 = Enable the following ranges for the FWH: FFF00000h–FFF7FFFFh FFB00000h–FFB7FFFFh FWH Address Range Enable (FWH_E8_EN)—R/W. Enables decoding two 512 KB FWH memory ranges. 5 0 = Disable. 1 = Enable the following ranges for the FWH: FFE80000h–FFEFFFFh FFA80000h–FFAFFFFFh FWH Address Range Enable (FWH_E0_EN)—R/W. Enables decoding two 512 KB FWH memory ranges. 4 0 = Disable. 1 = Enable the following ranges for the FWH: FFE00000h–FFE7FFFFh FFA00000h–FFA7FFFFh FWH Address Range Enable (FWH_D8_EN)—R/W. Enables decoding two 512 KB FWH memory ranges. 3 0 = Disable. 1 = Enable the following ranges for the FWH FFD80000h–FFDFFFFFh FF980000h–FF9FFFFFh FWH Address Range Enable (FWH_D0_EN)—R/W. Enables decoding two 512 KB FWH memory ranges. 2 0 = Disable. 1 = Enable the following ranges for the FWH FFD00000h–FFD7FFFFh FF900000h–FF97FFFFh FWH Address Range Enable (FWH_C8_EN)—R/W. Enables decoding two 512 KB FWH memory ranges. 1 0 = Disable. 1 = Enable the following ranges for the FWH FFC80000h–FFCFFFFFh FF880000h–FF8FFFFFh FWH Address Range Enable (FWH_C0_EN)—R/W. Enables decoding two 512 KB FWH memory ranges. 0 0 = Disable. 1 = Enable the following ranges for the FWH FFC00000h–FFC7FFFFh FF800000h–FF87FFFFh
7
9-16
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.29
GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit
E4h–E5h 00h Yes
Attribute: Size: Power Well:
Description
R/W 16-bit Core
15:7
Generic I/O Decode Range 1 Base Address (GEN1_BASE)—R/W. This address is aligned on a 128-byte boundary, and must have address lines 31:16 as 0. Note that this generic decode is for I/O addresses only, not memory addresses. The size of this range is 128 bytes. Reserved. Generic Decode Range 1 Enable (GEN1_EN)—R/W. 0 = Disable. 1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
6:1 0
9.1.30
LPC_EN—LPC I/F Enables (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 15:14 Reserved Microcontroller Address Range Enable (CNF2_LPC_EN)—R/W. 13 0 = Disable. 1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used for a microcontroller. Super I/O Address Range Enable (CNF1_LPC_EN)—R/W. 12 0 = Disable. 1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used for Super I/O devices. Microcontroller Address Range Enable (MC_LPC_EN)—R/W. 11 0 = Disable. 1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used for a microcontroller. Microcontroller Address Range Enable (KBC_LPC_EN)—R/W. 10 0 = Disable. 1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used for a microcontroller. Game Port Address Range Enable (GAMEH_LPC_EN)—R/W. 9 0 = Disable. 1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is used for a gameport. Game Port Address Range Enable (GAMEL_LPC_EN)—R/W. 8 0 = Disable. 1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is used for a gameport.
E6h–E7h 00h Yes
Attribute: Size: Power Well:
Description
R/W 16-bit Core
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-17
LPC Interface Bridge Registers (D31:F0)
Bit
Description ADLIB Address Range Enable (ADLIB_LPC_EN)—R/W.
7
0 = Disable. 1 = Enables the decoding of the I/O locations 388h–38Bh to the LPC interface. MSS Address Range Enable (MSS_LPC_EN)—R/W. 0 = Disable. 1 = Enables the decoding of the MSS range to the LPC interface. This range is selected in the LPC_Sound Decode Range Register. MIDI Address Range Enable (MIDI_LPC_EN)—R/W. 0 = Disable. 1 = Enables the decoding of the MIDI range to the LPC interface. This range is selected in the LPC_Sound Decode Range Register. Sound Blaster Address Range Enable (SB16_LPC_EN)—R/W. 0 = Disable. 1 = Enables the decoding of the SB16 range to the LPC interface. This range is selected in the LPC_Sound Decode Range Register. FDD Address Range Enable (FDD_LPC_EN)—R/W. 0 = Disable. 1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register. LPT Address Range Enable (LPT_LPC_EN)—R/W. 0 = Disable. 1 = Enables the decoding of the LPT range to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register. COM B Address Range Enable (COMB_LPC_EN)—R/W. 0 = Disable. 1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the LPC_COM Decode Range Register. Com A Address Range Enable (COMA_LPC_EN)—R/W. 0 = Disable. 1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the LPC_COM Decode Range Register.
6
5
4
3
2
1
0
9-18
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.31
FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0)
Offset Address: Default Value:
Bit
E8h 00112233h
Attribute: Size:
Description
R/W 32 bits
31:28
FWH Address Range Select (FWH_F8_IDSEL)—RO. IDSEL for two 512 KB FWH memory ranges and one 128KB memory range. This field is fixed at 0000. The IDSEL in this field addresses the following memory ranges: FFF8 0000h–FFFF FFFFh FFB8 0000h–FFBF FFFFh 000E 0000h–000F FFFFh FWH Address Range Select (FWH_F0_IDSEL)—R/W. IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFF0 0000h–FFF7 FFFFh FFB0 0000h–FFB7 FFFFh FWH Address Range Select (FWH_E8_IDSEL)—R/W. IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE8 0000h–FFEF FFFFh FFA8 0000h–FFAF FFFFh FWH Address Range Select (FWH_E0_IDSEL)—R/W. IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE0 0000h–FFE7 FFFFh FFA0 0000h–FFA7 FFFFh FWH Address Range Select (FWH_D8_IDSEL)—R/W. IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD8 0000h–FFDF FFFFh FF98 0000h–FF9F FFFFh FWH Address Range Select (FWH_D0_IDSEL)—R/W. IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD0 0000h–FFD7 FFFFh FF90 0000h–FF97 FFFFh FWH Address Range Select (FWH_C8_IDSEL)—R/W. IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC8 0000h–FFCF FFFFh FF88 0000h–FF8F FFFFh FWH Address Range Select (FWH_C0_IDSEL)—R/W. IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC0 0000h–FFC7 FFFFh FF80 0000h–FF87 FFFFh
27:24
23:20
19:16
15:12
11:8
7:4
3:0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-19
LPC Interface Bridge Registers (D31:F0)
9.1.32
GEN2_DEC—LPC I/F Generic Decode Range 2 (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit
ECh–EDh 00h Yes
Attribute: Size: Power Well:
Description
R/W 16-bit Core
15:4
Generic I/O Decode Range 2 Base Address (GEN2_BASE)—R/W. This address is aligned on a 64-byte boundary and must have address lines 31:16 as 0. Note that this generic decode is for I/O addresses only; not memory addresses. The size of this range is 16 bytes. Reserved. Read as 0 Generic I/O Decode Range 2 Enable (GEN2_EN)—R/W. 0 = Disable. 1 = Accesses to the GEN2 I/O range will be forwarded to the LPC interface.
3:1 0
9.1.33
FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0)
Offset Address: Default Value:
Bit
EEh–EFh 4567h
Attribute: Size:
Description
R/W 32 bits
15:12
FWH Address Range Select (FWH_70_IDSEL)—R/W. IDSEL for two 1 MB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF70 0000h–FF7F FFFFh FF30 0000h–FF3F FFFFh FWH Address Range Select (FWH_60_IDSEL)—R/W. IDSEL for two 1 MB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF60 0000h–FF6F FFFFh FF20 0000h–FF2F FFFFh FWH Address Range Select (FWH_50_IDSEL)—R/W. IDSEL for two 1 MB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF50 0000h–FF5F FFFFh FF10 0000h–FF1F FFFFh FWH Address Range Select (FWH_40_IDSEL)—R/W. IDSEL for two 1 MB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF40 0000h–FF4F FFFFh FF00 0000h–FF0F FFFFh
11:8
7:4
3:0
9-20
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.1.34
FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—D31:F0)
Offset Address: Default Value: F0h 0Fh Attribute: Size: R/W 8 bits
This register determines which memory ranges are decoded on the PCI bus and forwarded to the FWH. The ICH2 subtractively decodes cycles on PCI unless POS_DEC_EN is set to 1.
Bit 7:4 Reserved. FWH Address Range Enable (FWH_70_EN)—R/W. Enables decoding two 1 MB FWH memory ranges. 3 0 = Disable. 1 = Enable the following ranges for the FWH FF70 0000h–FF7F FFFFh FF30 0000h–FF3F FFFFh FWH Address Range Enable (FWH_60_EN)—R/W. Enables decoding two 1 MB FWH memory ranges. 2 0 = Disable. 1 = Enable the following ranges for the FWH FF60 0000h–FF6F FFFFh FF20 0000h–FF2F FFFFh FWH Address Range Enable (FWH_50_EN)—R/W. Enables decoding two 1 MB FWH memory ranges. 1 0 = Disable. 1 = Enable the following ranges for the FWH FF50 0000h–FF5F FFFFh FF10 0000h–FF1F FFFFh FWH Address Range Enable (FWH_40_EN)—R/W. Enables decoding two 1 MB FWH memory ranges. 0 0 = Disable. 1 = Enable the following ranges for the FWH FF40 0000h–FF4F FFFFh FF00 0000h–FF0F FFFFh Description
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-21
LPC Interface Bridge Registers (D31:F0)
9.1.35
FUNC_DIS—Function Disable Register (LPC I/F—D31:F0)
Offset Address: Default Value: Lockable:
Bit 15:9 Reserved SMBus For BIOS (SMB_FOR_BIOS)—R/W. This bit is used in conjunction with bit 3 in this register. 8 0 = No effect. 1 = Allows the SMBus I/O space to be accessible by software when bit 3 in this register is set. The PCI configuration space is hidden in this case. Note that if bit 3 is set alone, the decode of both SMBus PCI configuration and I/O space will be disabled. Reserved AC’97 Modem Disable (F6_Disable)—R/W. Software sets this bit to disable the AC’97 modem controller function. BIOS must not enable I/O or memory address space decode, interrupt generation or any other functionality for functions that are to be disabled. 0 = AC’97 Modem is enabled 1 = AC’97 Modem is disabled AC’97 Audio Controller Disable (F5_Disable)—R/W. Software sets this bit to disable the AC’97 audio controller function. BIOS must not enable I/O or memory address space decode, interrupt generation or any other functionality for functions that are to be disabled. 0 = AC’97 audio controller is enabled 1 = AC’97 audio controller is disabled USB Controller 2 Disable (F4_Disable)—R/W. Software sets this bit to disable the USB Controller #2 function. BIOS must not enable I/O or memory address space decode, interrupt generation or any other functionality for functions that are to be disabled. 0 = USB Controller #2 is enabled 1 = USB Controller #2 is disabled SMBus Controller Disable (F3_Disable)—R/W. Software sets this bit to disable the SMBus Host Controller function. BIOS must not enable I/O or memory address space decode, interrupt generation or any other functionality for functions that are to be disabled. 0 = SMBus controller is enabled 1 = SMBus controller is disabled USB Controller 1 Disable (F2_Disable)—R/W. Software sets this bit to disable the USB Controller #1 function. BIOS must not enable I/O or memory address space decode, interrupt generation or any other functionality for functions that are to be disabled. 0 = USB Controller #1 is enabled 1 = USB Controller #1 is disabled IDE Controller Disable (F1_Disable)—R/W. Software sets this bit to disable the IDE controller function. BIOS must not enable I/O or memory address space decode, interrupt generation or any other functionality for functions that are to be disabled. 0 = IDE controller is enabled 1 = IDE controller is disabled 0 Reserved.
F2h 00h No
Attribute: Size: Power Well:
Description
R/W 16-bit Core
7
6
5
4
3
2
1
9-22
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.2
DMA I/O Registers
Table 9-2. DMA Registers
Port 00h 01h 02h 03h 04h 05h 06h 07h 08h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 80h 81h 82h 83h 84h–86h 87h 88h 89h 8Ah 8Bh 8Ch–8Eh 8Fh C0h C2h C4h C6h C8h CAh CCh Alias 10h 11h 12h 13h 14h 15h 16h 17h 18h Channel 0–3 DMA Status Register 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 90h 91h – 93h 94h–96h 97h 98h 99h 9Ah 9Bh 9Ch–9Eh 9Fh C1h C3h C5h C7h C9h CBh CDh Channel 0–3 DMA Write Single Mask Register Channel 0–3 DMA Channel Mode Register Channel 0–3 DMA Clear Byte Pointer Register Channel 0–3 DMA Master Clear Register Channel 0–3 DMA Clear Mask Register Channel 0–3 DMA Write All Mask Register Reserved Page Register Channel 2 DMA Memory Low Page Register Channel 3 DMA Memory Low Page Register Channel 1 DMA Memory Low Page Register Reserved Page Registers Channel 0 DMA Memory Low Page Register Reserved Page Register Channel 6 DMA Memory Low Page Register Channel 7 DMA Memory Low Page Register Channel 5 DMA Memory Low Page Register Reserved Page Registers Refresh Low Page Register Channel 4 DMA Base & Current Address Register Channel 4 DMA Base & Current Count Register Channel 5 DMA Base & Current Address Register Channel 5 DMA Base & Current Count Register Channel 6 DMA Base & Current Address Register Channel 6 DMA Base & Current Count Register Channel 7 DMA Base & Current Address Register Undefined 000001XXb 000000XXb Undefined Undefined Undefined 0Fh Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RO WO WO WO WO WO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Name/Function Channel 0 DMA Base & Current Address Register Channel 0 DMA Base & Current Count Register Channel 1 DMA Base & Current Address Register Channel 1 DMA Base & Current Count Register Channel 2 DMA Base & Current Address Register Channel 2 DMA Base & Current Count Register Channel 3 DMA Base & Current Address Register Channel 3 DMA Base & Current Count Register Channel 0–3 DMA Command Register Default Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Type R/W R/W R/W R/W R/W R/W R/W R/W WO
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-23
LPC Interface Bridge Registers (D31:F0)
Table 9-2. DMA Registers (Continued)
Port CEh D0h D4h D6h D8h DAh DCh DEh Alias CFh D1h Channel 4–7 DMA Status Register D5h D7h D9h DBh DDh DFh Channel 4–7 DMA Write Single Mask Register Channel 4–7 DMA Channel Mode Register Channel 4–7 DMA Clear Byte Pointer Register Channel 4–7 DMA Master Clear Register Channel 4–7 DMA Clear Mask Register Channel 4–7 DMA Write All Mask Register Undefined 000001XXb 000000XXb Undefined Undefined Undefined 0Fh RO WO WO WO WO WO R/W Register Name/Function Channel 7 DMA Base & Current Count Register Channel 4–7 DMA Command Register Default Undefined Undefined Type R/W WO
9.2.1
DMABASE_CA—DMA Base and Current Address Registers
I/O Address: Ch. #0 = 00h; Ch. #1 = 02h Ch. #2 = 04h; Ch. #3 = 06h Ch. #5 = C4h Ch. #6 = C8h Ch. #7 = CCh; Undef No Attribute: Size: RO 16-bit (per channel), but accessed in two 8-bit quantities Core
Default Value: Lockable:
Bit
Power Well:
Description
Base and Current Address—R/W. This register determines the address for the transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Address register and copied to the Current Address register. On reads, the value is returned from the Current Address register. 15:0 The address increments/decrements in the Current Address register after each transfer, depending on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will be reloaded from the Base Address register after a terminal count is generated. For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit location. Bit 15 will be shifted out. Therefore, if bit 15 was a 1, it will be lost. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first.
9-24
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.2.2
DMABASE_CC—DMA Base and Current Count Registers
I/O Address: Ch. #0 = 01h; Ch. #1 = 03h Ch. #2 = 05h; Ch. #3 = 07h Ch. #5 = C6h; Ch. #6 = CAh Ch. #7 = CEh; Undefined No Attribute: Size: R/W 16-bit (per channel), but accessed in two 8-bit quantities Core
Default Value: Lockable:
Bit
Power Well:
Description Base and Current Count—R/W. This register determines the number of transfers to be performed. The address specified points to two separate registers. On writes the value is stored in the Base Count register and copied to the Current Count register. On reads the value is returned from the Current Count register. The actual number of transfers is one more than the number programmed in the Base Count Register (i.e., programming a count of 4h results in 5 transfers). The count is decrements in the Current Count register after each transfer. When the value in the register rolls from zero to FFFFh, a terminal count is generated. If the channel is in auto-initialize mode, the Current Count register will be reloaded from the Base Count register after a terminal count is generated. For transfers to/from an 8-bit slave (channels 0–3), the count register indicates the number of bytes to be transferred. For transfers to/from a 16-bit slave (channels 5–7), the count register indicates the number of words to be transferred. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first.
15:0
9.2.3
DMAMEM_LP—DMA Memory Low Page Registers
I/O Address: Ch. #0 = 87h; Ch. #1 = 83h Ch. #2 = 81h; Ch. #3 = 82h Ch. #5 = 8Bh; Ch. #6 = 89h Ch. #7 = 8Ah; Undefined No
Default Value: Lockable:
Bit 7:0
Attribute: Size: Power Well:
Description
R/W 8-bit Core
DMA Low Page (ISA Address bits [23:16])—R/W. This register works in conjunction with the DMA controller's Current Address Register to define the complete 24-bit address for the DMA channel. This register remains static throughout the DMA transfer.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-25
LPC Interface Bridge Registers (D31:F0)
9.2.4
DMACMD—DMA Command Register
I/O Address: Default Value: Lockable:
Bit 7:5 Reserved. Must be 0. DMA Group Arbitration Priority—WO. Each channel group is individually assigned either fixed or rotating arbitration priority. At part reset, each group is initialized in fixed priority. 0 = Fixed priority to the channel group 1 = Rotating priority to the group. Reserved. Must be 0 DMA Channel Group Enable—WO. Both channel groups are enabled following part reset. 2 0 = Enable the DMA channel group. 1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is cascaded through channel 4. Reserved. Must be 0.
Ch. #0–3 = 08h; Ch. #4–7 = D0h Undefined No
Attribute: Size: Power Well:
Description
WO 8-bit Core
4
3
1:0
9.2.5
DMASTS—DMA Status Register
I/O Address: Default Value: Lockable:
Bit
Ch. #0–3 = 08h; Ch. #4–7 = D0h Undefined No
Attribute: Size: Power Well:
Description
RO 8-bit Core
7:4
Channel Request Status—RO. When a valid DMA request is pending for a channel, the corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the request status for channels 0 through 3. 4 = Channel 0 5 = Channel 1 (5) 6 = Channel 2 (6) 7 = Channel 3 (7) Channel Terminal Count Status—RO. When a channel reaches terminal count (TC), its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for cascade, so the TC bit response for channel 4 is irrelevant.
3:0
0 = Channel 0 1 = Channel 1 (5) 2 = Channel 2 (6) 3 = Channel 3 (7)
9-26
82801BA ICH2 and 82801BAM ICH2-M Datasheet
LPC Interface Bridge Registers (D31:F0)
9.2.6
DMA_WRSMSK—DMA Write Single Mask Register
I/O Address: Default Value: Lockable:
Bit 7:3 Reserved. Must be 0. Channel Mask Select—WO. 2 0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore, only one channel can be masked / unmasked at a time. 1 = Disable DREQ for the selected channel. DMA Channel Select—WO. These bits select the DMA Channel Mode Register to program. 00 = Channel 0 (4) 1:0 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7)
Ch. #0–3 = 0Ah; Ch. #4–7 = D4h 0000 01xx No
Attribute: Size: Power Well:
Description
WO 8-bit Core
9.2.7
DMACH_MODE—DMA Channel Mode Register
I/O Address: Default Value: Lockable:
Bit
Ch. #0–3 = 0Bh; Ch. #4–7 = D6h 0000 00xx No
Attribute: Size: Power Well:
Description
WO 8-bit Core
7:6
DMA Transfer Mode—WO. Each DMA channel can be programmed in one of four different modes: 00 = Demand mode 01 = Single mode 10 = Reserved 11 = Cascade mode Address Increment/Decrement Select—WO. This bit controls address increment/decrement during DMA transfers. 0 = Address increment. (default after part reset or Master Clear) 1 = Address decrement. Autoinitialize Enable—WO. 0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset or Master Clear disables autoinitialization. 1 = DMA restores the Base Address and Count registers to the current registers following a terminal count (TC). DMA Transfer Type—WO. These bits represent the direction of the DMA transfer. When the channel is programmed for cascade mode, (bits[7:6] = “11”) the transfer type is irrelevant.
5
4
3:2
00 = Verify - No I/O or memory strobes generated 01 = Write - Data transferred from the I/O devices to memory 10 = Read - Data transferred from memory to the I/O device 11 = Illegal DMA Channel Select—WO. These bits select the DMA Channel Mode Register that will be written by bits [7:2].
1:0
00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7)
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LPC Interface Bridge Registers (D31:F0)
9.2.8
DMA Clear Byte Pointer Register
I/O Address: Default Value: Lockable:
Bit
Ch. #0–3 = 0Ch; Ch. #4–7 = D8h xxxx xxxx No
Attribute: Size: Power Well:
Description
WO 8-bit Core
7:0
Clear Byte Pointer—WO. No specific pattern. Command enabled with a write to the I/O port address. Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is also cleared by part reset and by the Master Clear command. This command precedes the first access to a 16-bit DMA controller register. The first access to a 16 bit register will then access the significant byte, and the second access automatically accesses the most significant byte.
9.2.9
DMA Master Clear Register
I/O Address: Default Value:
Bit 7:0
Ch. #0–3 = 0Dh; Ch. #4–7 = DAh xxxx xxxx
Attribute: Size:
Description
WO 8-bit
Master Clear—WO. No specific pattern. Enabled with a write to the port. This has the same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are cleared and the Mask Register is set.
9.2.10
DMA_CLMSK—DMA Clear Mask Register
I/O Address: Default Value: Lockable:
Bit 7:0
Ch. #0–3 = 0Eh; Ch. #4–7 = DCh xxxx xxxx No
Attribute: Size: Power Well:
Description
WO 8-bit Core
Clear Mask Register—WO. No specific pattern. Command enabled with a write to the port.
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LPC Interface Bridge Registers (D31:F0)
9.2.11
DMA_WRMSK—DMA Write All Mask Register
I/O Address: Default Value: Lockable:
Bit 7:4 Reserved. Must be 0. Channel Mask Bits—R/W. This register permits all four channels to be simultaneously enabled/ disabled instead of enabling/disabling each channel individually, as is the case with the Mask Register - Write Single Mask Bit. In addition, this register has a read path to allow the status of the channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/ Word Count Register reaches terminal count (unless the channel is in auto-initialization mode). Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status. Bit 0 = Channel 0 (4) Bit 1 = Channel 1 (5) Bit 2 = Channel 2 (6) Bit 3 = Channel 3 (7) 1 = Masked, 0 = Not Masked 1 = Masked, 0 = Not Masked 1 = Masked, 0 = Not Masked 1 = Masked, 0 = Not Masked
Ch. #0–3 = 0Fh; Ch. #4–7 = DEh 0000 1111 No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
3:0
Note: Disabling channel 4 also disables channels 0–3 due to the cascade of channels 0–3 through channel 4.
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LPC Interface Bridge Registers (D31:F0)
9.3
Timer I/O Registers
Port 40h Aliases 50h Counter 0 Counter Access Port Register Counter 1 Interval Time Status Byte Format 41h 51h Counter 1 Counter Access Port Register Counter 2 Interval Time Status Byte Format 42h 52h Counter 2 Counter Access Port Register Timer Control Word Register 43h 53h Timer Control Word Register Read Back Counter Latch Command Undefined Undefined XXXXXXX0b X0h R/W WO WO WO Undefined 0XXXXXXXb R/W RO Undefined 0XXXXXXXb R/W RO Register Name/Function Counter 0 Interval Time Status Byte Format Default Value 0XXXXXXXb Type RO
9.3.1
TCW—Timer Control Word Register
I/O Address: Default Value: 43h All bits undefined Attribute: Size: WO 8 bits
This register is programmed prior to any counter being accessed to specify counter modes. Following part reset, the control words for each register are undefined and each counter output is 0. Each timer must be programmed to bring it into a known state.
Bit Description Counter Select—WO. The Counter Selection bits select the counter the control word acts upon as shown below. The Read Back Command is selected when bits[7:6] are both 1. 00 = Counter 0 select 7:6 01 = Counter 1 select 10 = Counter 2 select 11 = Read Back Command Read/Write Select—WO. These bits are the read/write control bits. The actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = Counter Latch Command 5:4 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB Counter Mode Selection—WO. These bits select one of six possible modes of operation for the selected counter. 000 = Mode 0 001 = Mode 1 3:1 x10 = Mode 2 x11 = Mode 3 100 = Mode 4 101 = Mode 5 0 Out signal on end of count (=0) Hardware retriggerable one-shot Rate generator (divide by n counter) Square wave output Software triggered strobe Hardware triggered strobe
Binary/BCD Countdown Select—WO. 0 = Binary countdown is used. The largest possible binary count is 216 1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104
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LPC Interface Bridge Registers (D31:F0)
There are two special commands that can be issued to the counters through this register, the Read Back Command and the Counter Latch Command. When these commands are chosen, several bits within this register are redefined. These register formats are described below.
9.3.1.1
RDBK_CMD—Read Back Command
The Read Back Command is used to determine the count value, programmed mode, and current states of the OUT pin and Null count flag of the selected counter or counters. Status and/or count may be latched in any or all of the counters by selecting the counter during the register write. The count and status remain latched until read, and further latch commands are ignored until the count is read. Both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. If both are latched, the first read operation from that counter returns the latched status. The next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. Subsequent reads return an unlatched count.
Bit 7:6 5 Description Read Back Command. This field must be “11” to select the Read Back Command. Latch Count of Selected Counters. 0 = Current count value of the selected counters will be latched 1 = Current count will not be latched Latch Status of Selected Counters. 4 0 = Status of the selected counters will be latched 1 = Status will not be latched Counter 2 Select. 1 = Counter 2 count and/or status will be latched Counter 1 Select. 1 = Counter 1 count and/or status will be latched Counter 0 Select. 1 = Counter 0 count and/or status will be latched. Reserved. Must be 0.
3 2 1 0
9.3.1.2
LTCH_CMD—Counter Latch Command
The Counter Latch Command latches the current count value. This command is used to insure that the count read from the counter is accurate. The count value is then read from each counter's count register through the Counter Ports Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read according to the programmed format (i.e., if the counter is programmed for two byte counts, two bytes must be read). The two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). If a counter is latched once and then latched again before the count is read, the second Counter Latch Command is ignored.
Bit Description Counter Selection. These bits select the counter for latching. If “11” is written, then the write is interpreted as a read back command. 00 = Counter 0 01 = Counter 1 10 = Counter 2 Counter Latch Command. 00 = Selects the Counter Latch Command. Reserved. Must be 0.
7:6
5:4 3:0
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LPC Interface Bridge Registers (D31:F0)
9.3.2
SBYTE_FMT—Interval Timer Status Byte Format Register
I/O Address: Default Value: Counter 0 = 40h, Counter 1 = 41h, Counter 2 = 42h Bits[6:0] undefined, Bit 7=0 Attribute: Size: RO 8 bits per counter
Each counter's status byte can be read following a Read Back Command. If latch status is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. The status byte returns the following:
Bit Counter OUT Pin State—RO. 7 0 = OUT pin of the counter is also a 0. 1 = OUT pin of the counter is also a 1. Count Register Status—RO. This bit indicates when the last count written to the Count Register (CR) has been loaded into the counting element (CE). The exact time this happens depends on the counter mode, but until the count is loaded into the counting element (CE), the count value will be incorrect. 0 = Count has been transferred from CR to CE and is available for reading. 1 = Null Count. Count has not been transferred from CR to CE and is not yet available for reading. Read/Write Selection Status—RO. These reflect the read/write selection made through bits[5:4] of the control register. The binary codes returned during the status read match the codes used to program the counter read/write selection. 5:4 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB Mode Selection Status—RO. These bits return the counter mode programming. The binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 = Mode 0 001 = Mode 1 3:1 x10 = Mode 2 x11 = Mode 3 100 = Mode 4 101 = Mode 5 0 Out signal on end of count (=0) Hardware retriggerable one-shot Rate generator (divide by n counter) Square wave output Software triggered strobe Hardware triggered strobe Description
6
Countdown Type Status—RO. This bit reflects the current countdown type. 0 = Binary countdown 1 = Binary Coded Decimal (BCD) countdown.
9.3.3
Counter Access Ports Register
I/O Address: Default Value:
Bit
Counter 0 –40h, Counter 1 –41h, Counter 2–42h All bits undefined
Attribute: Size:
Description
R/W 8 bit
7:0
Counter Port—R/W. Each counter port address is used to program the 16-bit Count Register. The order of programming (either LSB only, MSB only, or LSB then MSB) is defined with the Interval Counter Control Register at port 43h. The counter port is also used to read the current count from the Count Register, and return the status of the counter programming following a Read Back Command.
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LPC Interface Bridge Registers (D31:F0)
9.4
9.4.1
8259 Interrupt Controller (PIC) Registers
Interrupt Controller I/O MAP
The interrupt controller registers are located at 20h and 21h for the master controller (IRQ[0:7]), and at A0h and A1h for the slave controller (IRQ[8:13]). These registers have multiple functions depending on the data written to them. Table 9-3 lists the different register possibilities for each address.
Table 9-3. PIC Registers
Port Aliases 24h, 28h, 20h 2Ch, 30h, 34h, 38h, 3Ch Register Name/Function Master PIC ICW1 Init. Cmd Word 1 Register Master PIC OCW2 Op Ctrl Word 2 Register Master PIC OCW3 Op Ctrl Word 3 Register Master PIC ICW2 Init. Cmd Word 2 Register 25h, 29h, 21h 2Dh, 31h, 35h, 39h, 3Dh Master PIC ICW4 Init. Cmd Word 4 Register Master PIC OCW1 Op Ctrl Word 1 Register A4h, A8h, A0h ACh, B0h, B4h, B8h, BCh Slave PIC ICW1 Init. Cmd Word 1 Register Slave PIC OCW2 Op Ctrl Word 2 Register Slave PIC OCW3 Op Ctrl Word 3 Register Slave PIC ICW2 Init. Cmd Word 2 Register A5h, A9h, A1h ADh, B1h, B5h, B9h, BDh 4D0h 4D1h – – Slave PIC ICW4 Init. Cmd Word 4 Register Slave PIC OCW1 Op Ctrl Word 1 Register Master PIC Edge/Level Triggered Register Slave PIC Edge/Level Triggered Register 01h 00h 00h 00h WO R/W R/W R/W Slave PIC ICW3 Init. Cmd Word 3 Register 01h 00h Undefined 001XXXXXb X01XXX10b Undefined Undefined WO R/W WO WO R/W WO WO Master PIC ICW3 Init. Cmd Word 3 Register Default Value Undefined 001XXXXXb X01XXX10b Undefined Undefined Type WO WO R/W WO WO
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LPC Interface Bridge Registers (D31:F0)
9.4.2
ICW1—Initialization Command Word 1 Register
Offset Address: Default Value: Master Controller–020h Slave Controller–0A0h All bits undefined Attribute: Size: WO 8 bit /controller
A write to Initialization Command Word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. The Interrupt Mask register is cleared. 2. IRQ7 input is assigned priority 7. 3. The slave mode address is set to 7. 4. Special Mask Mode is cleared and Status Read is set to IRR. Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the initialization sequence.
Bit 7:5 4 3 2 1 0 Description ICW/OCW select—WO. These bits are MCS-85 specific, and not needed. 000 = Should be programmed to “000” ICW/OCW select—WO. 1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence. Edge/Level Bank Select (LTIM)—WO. Disabled. Replaced by the edge/level triggered control registers (ELCR). ADI—WO. 0 = Ignored for the ICH2. Should be programmed to 0. Single or Cascade (SNGL)—WO. 0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode. ICW4 Write Required (IC4)—WO. 1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed.
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LPC Interface Bridge Registers (D31:F0)
9.4.3
ICW2—Initialization Command Word 2 Register
Offset Address: Default Value: Master Controller–021h Slave Controller–0A1h All bits undefined Attribute: Size: WO 8 bit /controller
ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. The value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the master controller and 70h for the slave controller.
Bit 7:3 Description Interrupt Vector Base Address—WO. Bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. Interrupt Request Level—WO. When writing ICW2, these bits should all be 0. During an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second INTA# cycle. The code is a three bit binary code: Code 000 2:0 001 010 011 100 101 110 111 Master Interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Slave Interrupt IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
9.4.4
ICW3—Master Controller Initialization Command Word 3 Register
Offset Address: Default Value:
Bit 7:3
21h All bits undefined
Attribute: Size:
Description
WO 8 bits
0 = These bits must be programmed to zero. Cascaded Interrupt Controller IRQ Connection—WO. This bit indicates that the slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through the slave controller’s priority resolver. The slave controller’s INTR output onto IRQ2. IRQ2 then goes through the master controller’s priority solver. If it wins, the INTR signal is asserted to the processor, and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1 = This bit must always be programmed to a 1. 0 = These bits must be programmed to zero.
2
1:0
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LPC Interface Bridge Registers (D31:F0)
9.4.5
ICW3—Slave Controller Initialization Command Word 3 Register
Offset Address: Default Value:
Bit 7:3
A1h All bits undefined
Attribute: Size:
Description
WO 8 bits
0 = These bits must be programmed to zero. Slave Identification Code—WO. These bits are compared against the slave identification code broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits must be programmed to 02h to match the code broadcast by the master controller. When 02h is broadcast by the master controller during the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector.
2:0
9.4.6
ICW4—Initialization Command Word 4 Register
Offset Address: Master Controller–021h Slave Controller–0A1h Attribute: Size:
Description 0 = These bits must be programmed to zero. Special Fully Nested Mode (SFNM)—WO. 4 0 = Should normally be disabled by writing a 0 to this bit. 1 = Special fully nested mode is programmed. Buffered Mode (BUF)—WO. 0 = Must be programmed to 0 for the ICH2. This is non-buffered mode. Master/Slave in Buffered Mode—WO. Not used. 0 = Should always be programmed to 0. Automatic End of Interrupt (AEOI)—WO. 1 0 = This bit should normally be programmed to 0. This is the normal end of interrupt. 1 = Automatic End of Interrupt (AEOI) mode is programmed. AEOI is discussed in Section 5.7.4. Microprocessor Mode—WO. 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecturebased system.
WO 8 bits
Bit 7:5
3 2
0
9.4.7
OCW1—Operational Control Word 1 (Interrupt Mask) Register
Offset Address: Default Value:
Bit
Master Controller–021h Slave Controller–0A1h 00h
Attribute: Size:
R/W 8 bits
Description Interrupt Request Mask—R/W. When a 1 is written to any bit in this register, the corresponding IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is cleared and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master controller will also mask the interrupt requests from the slave controller.
7:0
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LPC Interface Bridge Registers (D31:F0)
9.4.8
OCW2—Operational Control Word 2 Register
Offset Address: Default Value: Master Controller–020h Attribute: Slave Controller–0A0h Size: Bit[4:0]=undefined, Bit[7:5]=001 WO 8 bits
Following a part reset or ICW initialization, the controller enters the fully nested mode of operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI mode are disabled following initialization.
Bit Description Rotate and EOI Codes (R, SL, EOI)—WO. These three bits control the Rotate and End of Interrupt modes and combinations of the two. 000 = Rotate in Auto EOI Mode (Clear) 001 = Non-specific EOI command 010 = No Operation 7:5 011 = Specific EOI Command 100 = Rotate in Auto EOI Mode (Set) 101 = Rotate on Non-Specific EOI Command 110 = *Set Priority Command 111 = *Rotate on Specific EOI Command *L0–L2 Are Used 4:3 OCW2 Select—WO. When selecting OCW2, bits 4:3 = “00” Interrupt Level Select (L2, L1, L0)—WO. L2, L1, and L0 determine the interrupt level acted upon when the SL bit is active. A simple binary code, outlined below, selects the channel for the command to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case. 2:0 Bits 000 001 010 011 Interrupt Level IRQ0/8 IRQ1/9 IRQ2/10 IRQ3/11 Bits 100 101 110 111 Interrupt Level IRQ4/12 IRQ5/13 IRQ6/14 IRQ7/15
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LPC Interface Bridge Registers (D31:F0)
9.4.9
OCW3—Operational Control Word 3 Register
Offset Address: Default Value: Master Controller–020h Attribute: Slave Controller–0A0h Size: Bit[6,0]=0, Bit[7,4:2]=undefined, Bit[5,1]=1
Description Reserved. Must be 0. Special Mask Mode (SMM)—WO. 1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning. Enable Special Mask Mode (ESMM)—WO. 5 4:3 0 = Disable. The SMM bit becomes a "don't care". 1 = Enable the SMM bit to set or reset the Special Mask Mode. OCW3 Select—WO. When selecting OCW3, bits 4:3 = “01” Poll Mode Command—WO. 2 0 = Disable. Poll Command is not issued. 1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt acknowledge cycle. An encoded byte is driven onto the data bus, representing the highest priority level requesting service. Register Read Command—WO. These bits provide control for reading the In-Service Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3 port address read will be "read IRR". To retain the current selection (read ISR or read IRR), always write a 0 to bit 1 when programming this register. The selected register can be read repeatedly without reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior to attempting the read. 00 = No Action 01 = No Action 10 = Read IRQ Register 11 = Read IS Register
WO 8 bits
Bit 7
6
1:0
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LPC Interface Bridge Registers (D31:F0)
9.4.10
ELCR1—Master Controller Edge/Level Triggered Register
Offset Address: Default Value: 4D0h 00h Attribute: Size: R/W 8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode.
Bit IRQ7 ECL—R/W. 7 0 = Edge. 1 = Level. IRQ6 ECL—R/W. 6 0 = Edge. 1 = Level. IRQ5 ECL—R/W. 5 0 = Edge. 1 = Level. IRQ4 ECL—R/W. 4 0 = Edge. 1 = Level. IRQ3 ECL—R/W. 3 2:0 0 = Edge. 1 = Level. Reserved. Must be 0. Description
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LPC Interface Bridge Registers (D31:F0)
9.4.11
ELCR2—Slave Controller Edge/Level Triggered Register
Offset Address: Default Value: 4D1h 00h Attribute: Size: R/W 8 bits
In edge mode (bit[x] = 0) the interrupt is recognized by a low-to-high transition. In level mode (bit[x] = 1) the interrupt is recognized by a high level. The real time clock interrupt (IRQ8#) and the floating point error interrupt (IRQ13) cannot be programmed for level mode.
Bit IRQ15 ECL—R/W. 7 0 = Edge. 1 = Level. IRQ14 ECL—R/W. 6 5 4 0 = Edge. 1 = Level. Reserved. Must be 0. IRQ12 ECL—R/W. 0 = Edge. 1 = Level. IRQ11 ECL—R/W. 3 0 = Edge. 1 = Level. IRQ10 ECL—R/W. 2 0 = Edge. 1 = Level. IRQ9 ECL—R/W. 1 0 0 = Edge. 1 = Level. Reserved. Must be 0. Description
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LPC Interface Bridge Registers (D31:F0)
9.5
9.5.1
Advanced Interrupt Controller (APIC)
APIC Register Map
The APIC is accessed via an indirect addressing scheme. Two registers are visible by software for manipulation of most of the APIC registers. These registers are mapped into memory space. The registers are shown in Table 9-4.
Table 9-4. APIC Direct Registers
Address FEC0_0000h FEC0_0010h FECO_0020h FECO_0040h Index Register Data Register IRQ Pin Assertion Register EOI Register Register Size 8 bits 32 bits 8 bits 8 bits Type R/W R/W WO WO
Table 9-5 lists the registers which can be accessed within the APIC via the Index Register. When accessing these registers, accesses must be done a DWord at a time. For example, software should never access byte 2 from the Data register before accessing bytes 0 and 1. The hardware will not attempt to recover from a bad programming model in this case. Table 9-5. APIC Indirect Registers
Index 00h 01h 02h 03h 03h–0Fh 10h –11h 12h–13h ... 3Eh–3Fh 40h–FFh ID Version Arbitration ID Boot Configuration Reserved Redirection Table 0 Redirection Table 1 ... Redirection Table 23 Reserved 64 bits 64 bits ... 64 bits Register Size 32 bits 32 bits 32 bits 32 bits Type R/W RO RO R/W RO R/W R/W ... R/W RO
9.5.2
IND—Index Register
Memory Address Default Value: FEC0_0000h 00h Attribute: Size: R/W 8 bits
The Index Register will select which APIC indirect register to be manipulated by software. The selector values for the indirect registers are listed in Table 9-5. Software programs this register to select the desired APIC internal register
.
Bit 7:0
Description APIC Index—R/W. This is an 8 bit pointer into the I/O APIC register table.
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LPC Interface Bridge Registers (D31:F0)
9.5.3
DAT—Data Register
Memory Address Default Value: FEC0_0010h 00000000h Attribute: Size: R/W 32 bits
This is a 32 bit register specifying the data to be read or written to the register pointed to by the Index register. This register can only be accessed in DWord quantities.
Bit 7:0 Description APIC Data—R/W. This is a 32 bit register for the data to be read or written to the APIC indirect register pointed to by the Index register.
9.5.4
IRQPA—IRQ Pin Assertion Register
Memory Address Default Value: FEC0_0020h N/A Attribute: Size: WO 32 bits
The IRQ Pin Assertion Register is present to provide a mechanism to scale the number of interrupt inputs into the I/O APIC without increasing the number of dedicated input pins. When a device that supports this interrupt assertion protocol requires interrupt service, that device will issue a write to this register. Bits 4:0 written to this register contain the IRQ number for this interrupt. The only valid values are 0–23. Bits 31:5 are ignored. To provide for future expansion, peripherals should always write a value of 0 for Bits 31:5. See Section 5.8.4 for more details on how PCI devices will use this field. Note: Writes to this register are only allowed by the processor and by masters on the ICH2’s PCI bus. Writes by devices on PCI buses above the ICH2 (e.g., a PCI segment on a P64H) are not supported.
Bit 31:5 4:0 Reserved. Bits 31:5 are ignored. IRQ Number—WO. Bits 4:0 written to this register contain the IRQ number for this interrupt. The only valid values are 0–23. Description
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LPC Interface Bridge Registers (D31:F0)
9.5.5
EOIR—EOI Register
Memory Address Default Value: FEC0_0040h N/A Attribute: Size: WO 32 bits
The EOI register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared. Note: This is similar to what already occurs when the APIC sees the EIO message on the serial bus. Note that if multiple I/O Redirection entries, for any reason, assign the same vector for more than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt which was prematurely reset will not be lost because if its input remained active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the ICH2. To provide for future expansion, the processor should always write a value of 0 to Bits 31:8.
Bit 31:8 Description Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. Redirection Entry Clear—WO. When a write is issued to this register, the I/O APIC will check this field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.
Note:
7:0
9.5.6
ID—Identification Register
Index Offset: Default Value: 00h 00000000h Attribute: Size: R/W 32 bits
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is derived from its I/O APIC ID. This register is reset to zero on power up reset.
Bit 31:28 27:24 23:0 Reserved. APIC ID—R/W. Software must program this value before using the APIC. Reserved. Description
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LPC Interface Bridge Registers (D31:F0)
9.5.7
VER—Version Register
Index Offset: Default Value: 01h 00170002h Attribute: Size: RO 32 bits
Each I/O APIC contains a hardwired Version Register that identifies different implementation of APIC and their versions. The maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this APIC.
Bit 31:24 23:16 Reserved. Maximum Redirection Entries—RO. This is the entry number (0 being the lowest entry) of the highest entry in the redirection table. It is equal to the number of interrupt input pins minus one and is in the range 0 through 239. In the ICH2 this field is hardwired to 17h to indicate 24 interrupts. PRQ—RO. This bit is set to 1 to indicate that this version of the I/O APIC implements the IRQ Assertion register and allows PCI devices to write to it to cause interrupts. Reserved. Version—RO. This is a version number that identifies the implementation version. Description
15 14 :8 7:0
9.5.8
ARBID—Arbitration ID Register
Index Offset: Default Value: 02h 00000000h Attribute: Size: RO 32 bits
This register contains the bus arbitration priority for the APIC. This register is loaded whenever the APIC ID register is loaded. A rotating priority scheme is used for APIC bus arbitration. The winner of the arbitration becomes the lowest priority agent and assumes an arbitration ID of 0.
a
Bit 31:28 27:24 23:0 Reserved.
Description
I/O APIC Identification—RO. This 4 bit field contains the I/O APIC Arbitration ID. Reserved.
9.5.9
BOOT_CONFIG—Boot Configuration Register
Index Offset: Default Value: 03h 00000000h Attribute: Size: R/W 32 bits
This register is used to control the interrupt delivery mechanism for the APIC.
a
Bit 31:1 0 Reserved. Delivery Type (DT)—R/W.
Description
0 = Interrupt delivery mechanism is via the APIC serial bus (default). 1 = Interrupt delivery mechanism is a front-side bus message.
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LPC Interface Bridge Registers (D31:F0)
9.5.10
Redirection Table
Index Offset: Default Value: 10h–11h (vector 0) through 3E–3Fh (vector 23) Bit 16–1, Bits[15:12]=0. All other bits undefined Attribute: Size: R/W 64 bits each, (accessed as two 32 bit quantities)
The Redirection Table has a dedicated entry for each interrupt input pin. The information in the Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin into an APIC message. The APIC will respond to an edge-triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the I/O APIC is set. The state machine will step ahead and wait for an acknowledgment from the APIC bus unit that the interrupt message was sent over the APIC bus. Only then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new edge will only result in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt was not already pending at the destination.)
Bit 63:56 55:17 Description Destination—R/W. If bit 11 of this entry is 0 [Physical], then bits [59:56] specifies an APIC ID. If bit 11 of this entry is 1 [Logical], then bits [63:56] specify the logical destination address of a set of processors. Reserved. Mask—R/W. 0 = Not masked: An edge or level on this interrupt pin results in the delivery of the interrupt to the destination. 1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the device withdrawing the interrupt before it is posted to the processor. It is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. Trigger Mode—R/W. This field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = Edge triggered. 1 = Level triggered. Remote IRR—R/W. This bit is used for level triggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = Reset when an EOI message is received from a local APIC. 1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC. Interrupt Input Pin Polarity—R/W. This bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = Active high. 1 = Active low. Delivery Status—RO. This field contains the current status of the delivery of this interrupt. Writes to this bit have no effect. 12 0 = Idle. No activity for this interrupt. 1 = Pending. Interrupt has been injected, but delivery is held up due to the APIC bus being busy or the inability of the receiving APIC unit to accept the interrupt at this time. Destination Mode—R/W. This field determines the interpretation of the Destination field. 11 0 = Physical. Destination APIC ID is identified by bits [59:56]. 1 = Logical. Destinations are identified by matching bit [63:56] with the Logical Destination in the Destination Format Register and Logical Destination Register in each Local APIC.
16
15
14
13
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LPC Interface Bridge Registers (D31:F0)
Bit
Description Delivery Mode—R/W. This field specifies how the APICs listed in the destination field should act upon reception of this signal. Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode. These encodings are: 000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination. Trigger Mode can be edge or level. 001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. Trigger Mode can be edge or level. 010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge triggered. The vector information is ignored but must be programmed to all zeroes for future compatibility. 011 = Reserved 100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination. Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. Once the interrupt is detected, it will be sent over the APIC bus. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the NMI pin is reached again, the interrupt will be sent over the APIC bus again. 101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated as an edge triggered interrupt even if programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The INIT delivery mode does not set the RIRR bit. Once the interrupt is detected, it will be sent over the APIC bus. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the INIT pin is reached again, the interrupt will be sent over the APIC bus again 110 = Reserved 111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259A compatible interrupt controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the external controller that is expected to supply the vector. Requires the interrupt to be programmed as edge triggered.
10:8
7:0
Vector—R/W. This field contains the interrupt vector for this interrupt. Values range between 10h and FEh.
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LPC Interface Bridge Registers (D31:F0)
9.6
9.6.1
Real Time Clock Registers
I/O Register Address Map
The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the standard and extended banks. The first 14 bytes of the standard bank contain the RTC time and date information along with four registers, A–D, that are used for configuration of the RTC. The extended bank contains a full 128 bytes of battery backed SRAM and will be accessible even when the RTC module is disabled (via the RTC configuration register). Registers A–D do not physically exist in the RAM. All data movement between the host processor and the real-time clock is done through registers mapped to the standard I/O space. The register map appears in Table 9-6.
Table 9-6. RTC I/O Registers
I/O Locations 70h and 74h 71h and 75h 72h and 76h 73h and 77h NOTES: 1. I/O locations 70h and 71h are the standard ISA location for the real-time clock. The map for this bank is shown in Table 9-7. Locations 72h and 73h are for accessing the extended RAM. The extended RAM bank is also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address 73h is used as the data register. Index addresses above 127h are not valid. If the extended RAM is not needed, it may be disabled. 2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to these addresses, software must first read the value, and then write the same value for bit 7 during the sequential address write. If U128E bit = 0 Also alias to 72h and 76h Also alias to 73h and 77h Function Real-Time Clock (Standard RAM) Index Register Real-Time Clock (Standard RAM) Target Register Extended RAM Index Register (if enabled) Extended RAM Target Register (if enabled)
9.6.2
Indexed Registers
The RTC contains two sets of indexed registers that are accessed using the two separate Index and Target registers (70h/71h or 72h/73h), as shown in Table 9-7.
Table 9-7. RTC (Standard) RAM Bank
Index 00h 01h 02h 03h 04h 05h 06h 07h Seconds Seconds Alarm. Minutes Minutes Alarm Hours Hours Alarm Day of Week Day of Month Name Index 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh–7Fh Month Year Register A Register B Register C Register D 114 Bytes of User RAM Name
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LPC Interface Bridge Registers (D31:F0)
9.6.2.1
RTC_REGA—Register A
RTC Index: Default Value: Lockable: 0A Undefined No Attribute: Size: Power Well: R/W 8-bit RTC
This register is used for general configuration of the RTC functions. None of the bits are affected by RSMRST# or any other ICH2 reset signal.
Bit Description Update In Progress (UIP)—R/W. This bit may be monitored as a status flag. 7 0 = The update cycle will not start for at least 492us. The time, calendar, and alarm information in RAM is always available when the UIP bit is 0. 1 = The update is soon to occur or is in progress. Division Chain Select (DV[2:0])—R/W. These three bits control the divider chain for the oscillator, and are not affected by RSMRST# or any other reset signal. DV[2] corresponds to bit 6. 010 = Normal Operation 11X = Divider Reset 6:4 101 = Bypass 15 stages (test mode only) 100 = Bypass 10 stages (test mode only) 011 = Bypass 5 stages (test mode only) 001 = Invalid 000 = Invalid RS[3:0] Rate Select—R/W. Selects one of 13 taps of the 15 stage divider chain. The selected tap can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to zero. RS3 corresponds to bit 3. 0000 = Interrupt never toggles 0001 = 3.90625 ms 3:0 0010 = 7.8125 ms 0011 = 122.070 us 0100 = 244.141 us 0101 = 488.281 us 0110 = 976.5625 us 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms
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LPC Interface Bridge Registers (D31:F0)
9.6.2.2
RTC_REGB—Register B (General Configuration)
RTC Index: Default Value: Lockable:
Bit
0Bh U0U00UUU (U: Undefined) No
Attribute: Size: Power Well:
Description
R/W 8-bit RTC
Update Cycle Inhibit (SET)—R/W. Enables/Inhibits the update cycles. This bit is not affected by RSMRST# nor any other reset signal. 7 0 = Update cycle occurs normally once each second. 1 = A current update cycle will abort and subsequent update cycles will not occur until SET is returned to zero. When set is one, the BIOS may initialize time and calendar bytes safely. Periodic Interrupt Enable (PIE)—R/W. This bit is cleared by RSMRST#, but not on any other reset. 6 0 = Disable. 1 = Allows an interrupt to occur with a time base set with the RS bits of register A. Alarm Interrupt Enable (AIE)—R/W. This bit is cleared by RSMRST#, but not on any other reset. 5 0 = Disable. 1 = Allows an interrupt to occur when the AF is set by an alarm match from the update cycle. An alarm can occur once a second, one an hour, once a day, or one a month. Update-ended Interrupt Enable (UIE)—R/W. This bit is cleared by RSMRST#, but not on any other reset. 0 = Disable. 1 = Allows an interrupt to occur when the update cycle ends. Square Wave Enable (SQWE)—R/W. This bit serves no function in the ICH2. It is left in this register bank to provide compatibility with the Motorola* 146818B. The ICH2 has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset. Data Mode (DM)—R/W. Specifies either binary or BCD data representation. This bit is not affected by RSMRST# nor any other reset signal. 0 = BCD 1 = Binary Hour Format (HOURFORM)—R/W. Indicates the hour byte format. This bit is not affected by RSMRST# nor any other reset signal. 0 = Twelve-hour mode. In twelve hour mode, the seventh bit represents AM as zero and PM as one. 1 = Twenty-four hour mode. Daylight Savings Enable (DSE)—R/W. Triggers two special hour updates per year. The days for the hour adjustment are those specified in United States federal law as of 1987, which is different than previous years. This bit is not affected by RSMRST# nor any other reset signal. 0 0 = Daylight Savings Time updates do not occur. 1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to 3:00:00 AM. b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it is changed to 1:00:00 AM. The time must increment normally for at least two update cycles (seconds) previous to these conditions for the time change to occur properly.
4
3
2
1
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9.6.2.3
RTC_REGC—Register C (Flag Register)
RTC Index: Default Value: Lockable: 0Ch 00U00000 (U: Undefined) No Attribute: Size: Power Well: RO 8-bit RTC
Writes to Register C have no effect.
Bit 7 Description Interrupt Request Flag (IRQF)—RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This also causes the CH_IRQ_B signal to be asserted. This bit is cleared upon RSMRST# or a read of Register C. Periodic Interrupt Flag (PF)—RO. This bit is cleared upon RSMRST# or a read of Register C. 6 0 = If no taps are specified via the RS bits in Register A, this flag will not be set. 1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is 1. Alarm Flag (AF)—RO. 5 0 = This bit is cleared upon RTCRST# or a read of Register C. 1 = Alarm Flag will be set after all Alarm values match the current time. Update-ended Flag (UF)—RO. 4 3:0 0 = The bit is cleared upon RSMRST# or a read of Register C. 1 = Set immediately following an update cycle for each second. Reserved. Will always report 0.
9.6.2.4
RTC_REGD—Register D (Flag Register)
RTC Index: Default Value: Lockable:
Bit Valid RAM and Time Bit (VRT)—R/W. 7 0 = This bit should always be written as a 0 for write cycle; however, it will return a 1 for read cycles. 1 = The Valid Ram and Time bit is set to 1 when the PWRGD (power good) signal provided is high. This feature is not typically used. Reserved. This bit always returns a 0 and should be set to 0 for write cycles. Date Alarm—R/W. These bits store the date of month alarm value. If set to 000000b, then a don’t care state is assumed. The host must configure the date alarm for these bits to do anything, yet they can be written at any time. If the date alarm is not enabled, these bits will return zeros to mimic the functionality of the Motorola* 146818B. These bits are not affected by RESET.
0Dh 10UUUUUU (U: Undefined) No
Attribute: Size: Power Well:
Description
R/W 8-bit RTC
6
5:0
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LPC Interface Bridge Registers (D31:F0)
9.7
9.7.1
Processor Interface Registers
NMI_SC—NMI Status and Control Register
I/O Address: Default Value: Lockable:
Bit
61h 00h No
Attribute: Size: Power Well:
Description
R/W (some bits RO) 8-bit Core
7
SERR# NMI Source Status (SERR#_NMI_STS)—RO. 1 = PCI agent detected a system error and pulses the PCI SERR# line. This interrupt source is enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port 61h, this bit must be 0. IOCHK# NMI Source Status (IOCHK_NMI_STS)—RO. 1 = An ISA agent (via SERIRQ) asserted IOCHK# on the ISA bus. This interrupt source is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to 0 and then set it to 1. When writing to port 61h, this bit must be a 0. Timer Counter 2 OUT Status (TMR2_OUT_STS)—RO. This bit reflects the current state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a determinate value. When writing to port 61h, this bit must be a 0. Refresh Cycle Toggle (REF_TOGGLE)—RO. This signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be a 0. IOCHK# NMI Enable (IOCHK_NMI_EN)—R/W. 0 = Enabled. 1 = Disabled and cleared. PCI SERR# Enable (PCI_SERR_EN)—R/W. 0 = SERR# NMIs are enabled. 1 = SERR# NMIs are disabled and cleared. Speaker Data Enable (SPKR_DAT_EN)—R/W. 0 = SPKR output is a 0. 1 = SPKR output is equivalent to the Counter 2 OUT signal value. Timer Counter 2 Enable (TIM_CNT2_EN)—R/W. 0 = Disable. 1 = Enable
6
5
4
3
2
1
0
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LPC Interface Bridge Registers (D31:F0)
9.7.2
NMI_EN—NMI Enable (and Real Time Clock Index)
I/O Address: Default Value: Lockable: 70h 80h No Attribute: Size: Power Well: R/W (Special) 8-bit Core
Note:
The RTC Index field is write-only for normal operation. This field can only be read in Alt-Access Mode. Note, however, that this register is aliased to Port 74h (documented in Table 19-2), and all bits are readable at that address.
Bits NMI Enable (NMI_EN)—R/W. 7 0 = Enable NMI sources. 1 = Disable All NMI sources. Real Time Clock Index Address (RTC_INDX)—R/W. This data goes to the RTC to select which register or CMOS RAM address is being accessed. Description
6:0
9.7.3
PORT92—Fast A20 and Init Register
I/O Address: Default Value: Lockable:
Bit 7:2 Reserved. Alternate A20 Gate (ALT_A20_GATE)—R/W. This bit is ORed with the A20GATE input signal to generate A20M# to the processor. 0 = A20M# signal can potentially go active. 1 = This bit is set when INIT# goes active. Interrupt Now (INIT_NOW)—R/W. When this bit transitions from a 0 to a 1, the ICH2 will force INIT# active for 16 PCI clocks.
92h 00h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
1
0
9.7.4
COPROC_ERR—Coprocessor Error Register
I/O Address: Default Value: Lockable:
Bits 7:0
F0h 00h No
Attribute: Size: Power Well:
Description
WO 8-bits Core
Coprocessor Error (COPROC_ERR)—WO. Any value written to this register will cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13, the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, Bit 13) must be 1.
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LPC Interface Bridge Registers (D31:F0)
9.7.5
RST_CNT—Reset Control Register
I/O Address: Default Value: Lockable:
Bit 7:4 Reserved. Full Reset (FULL_RST)—R/W. This bit is used to determine the states of SLP_S3# and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going low (with RSMRST# high), or after two TCO time-outs. 1 = ICH2 will drive SLP_S3# and SLP_S5# low for 3–5 seconds. 0 = ICH2 will keep SLP_S3# and SLP_S5# high. 2 Reset Processor (RST_CPU)—R/W. When this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register). System Reset (SYS_RST)—R/W. This bit is used to determine a hard or soft reset to the processor. 1 1 = When RST_CPU bit goes from 0 to 1, the ICH2 performs a hard reset by activating PCIRST# for 1 millisecond. It also resets the resume well bits (except for those noted throughout the
CF9h 00h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
3
datasheet).
0 = When RST_CPU bit goes from 0 to 1, the ICH2 performs a soft reset by activating INIT# for 16 PCI clocks. 0 Reserved.
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LPC Interface Bridge Registers (D31:F0)
9.8
Power Management Registers (D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in the main (core) power well. Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved bit, the value should always be 0. Software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0.
9.8.1
Power Management PCI Configuration Registers (D31:F0)
Table 9-8 shows a small part of the configuration space for PCI Device 31: Function 0. It includes only those registers dedicated for power management. Some of the registers are only used for Legacy Power management schemes.
Table 9-8. PCI Configuration Map (PM—D31:F0)
Offset 40h–43h 44h A0h A2h A4h B8–BBh C0 C4–CAh CCh Mnemonic ACPI_BASE ACPI_CNTL GEN_PMCON_1 GEN_PMCON_2 GEN_PMCON_3 GPI_ROUT TRP_FWD_EN MON[n]_TRP_RNG MON_TRP_MSK Register Name/Function ACPI Base Address ACPI Control General Power Management Configuration 1 General Power Management Configuration 2 General Power Management Configuration 3 GPI Route Control I/O Monitor Trap Forwarding Enable I/O Monitor[4:7] Trap Range I/O Monitor Trap Range Mask 0000h 0000h R/W R/W Default 00000001h 00h 0000h 0000h 00h 00000000h Type R/W R/W R/W R/W R/W R/W
9.8.1.1
GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0)
Offset Address: Default Value: Lockable: A0h 00h No Attribute: Size: Usage: Power Well:
Description ICH2 (82801BA): Reserved ICH2-M (82801BAM): 15:12 Global Standby Timer Timeout Count (GST_TIMEOUT) — R/W. For the ICH2-M, this field sets the number of clock ticks that the Global Standby Timer counts before generating a wake event. The GST starts counting when the ICH2-M enters the S1 state. If a value of 0h is entered in this field, the GST does not count and no wake event is generated. The GST_TICK bit sets the tick rate. ICH2 (82801BA): Reserved 11 ICH2-M (82801BAM): Global Standby Timer Tick Rate (GST_TICK) — R/W. 0 = 1 minute resolution. This yields a GST timeout range of 1 to 15 minutes. 1 = 32 minute resolution, This yields a GST timeout range of 32 minutes to 8 hours.
R/W 16-bit ACPI, Legacy Core
Bit
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LPC Interface Bridge Registers (D31:F0)
Bit
Description Software SMI Rate Select (SWSMI_RATE_SEL)—R/W. 0 = SWSMI Timer will time out in 64 ms ± 4 ms (default). 1 = SWSMI Timer will time out in 1.5 ms ± 0.5 ms. PWRBTN# Level (PWRBTN_LVL)—RO. This read-only bit indicates the current state of the PWRBTN# signal. 0 = Low. 1 = High. Reserved. iiA64 Processor Mode Enable (A64_EN)—R/W. Set by software to indicate the presence of an iA64 processor. 0 = iA32 processor mode. 1 = iA64 processor mode. CPU SLP# Enable (CPUSLP_EN)—R/W. 0 = Disable.. ICH2 (82801BA): 1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the processor power.
10
9
8:7
6
5
Note that CPUSLP# will go active on entry to S3, S4 and S5 even if this bit is not set. ICH2-M (82801BAM): 1 = Enables the CPUSLP# signal to go active in the C3 state. This reduces the processor power. Note that CPUSLP# goes active during SpeedStep™ transitions and on entry to S1, S3, S4 and S5 even if this bit is not set.
4
Reserved. ICH2 (82801BA): Reserved ICH2-M (82801BAM):
3
Intel® SpeedStep™ Enable (SS_EN)— R/W. 0 = Intel® SpeedStep™ logic is disabled and the SS_CNT register will not be visible (reads to SS_CNT return 00h and writes have no effect). 1 = Intel® SpeedStep™ logic is enabled. ICH2 (82801BA): Reserved ICH2-M (82801BAM): PCI CLKRUN# Enable (CLKRUN_EN)— R/W.
2
0 = Disable. ICH2-M drives the CLKRUN# signal low. 1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and STP_PCI# signals. Note that when the SLP_EN# bit is set, the ICH2-M drives the CLKRUN# signal low, regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and LPC clocks continue running during a transition to a sleep state. Periodic SMI# rate Select (PER_SMI_SEL)—R/W. Set by software to control the rate at which periodic SMI# is generated. 00 = 1 minute
1:0
01 = 32 seconds 10 = 16 seconds 11 = 8 seconds
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LPC Interface Bridge Registers (D31:F0)
9.8.1.2
GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0)
Offset Address: Default Value: Lockable: A2h 00h No Attribute: Size: Usage: Power Well:
Description Reserved. CPU Power Failure (CPUPWR_FLR)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position.. ICH2 (82801BA): 1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low. ICH2-M (82801BAM): 1 = Indicates that the VGATE signal from the processor’s VRM went low. This bit will not be set if VGATE went low due to a Intel® SpeedStep™ transition. PWROK Failure (PWROK_FLR)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position, or when the system goes into a G3 state. 1 = This bit will be set any time PWROK goes low, when the system was in S0 or S1 state. The bit will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state. 0 Note: Traditional designs have a reset button logically ANDed with the PWROK signal from the power supply and the processor’s voltage regulator module. If this is done with the ICH2, the PWROK_FLR bit will be set. The ICH2 treats this internally as if the RSMRST# signal had gone active. However, it is not treated as a full power failure. If PWROK goes inactive and then active (but RSMRST# stays high), then the ICH2 will reboot (regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low before PWROK goes high, then this is a full power failure and the reboot policy is controlled by the AFTERG3 bit.
R/WC 16-bit ACPI, Legacy Resume
Bit 7:2
1
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LPC Interface Bridge Registers (D31:F0)
9.8.1.3
GEN_PMCON_3—General PM Configuration 3 Register (PM—D31:F0)
Offset Address: Default Value: Lockable: A4h 00h No Attribute: Size: Usage: Power Well:
Description Reserved. RTC Power Status (RTC_PWR_STS)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Indicates that the RTC battery was removed or failed. This bit is set when RTCRST# signal is low. Note: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Power Failure (PWR_FLR)—R/WC. This bit is in the RTC well and is not cleared by any type of reset except RTCRST#. 1 0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software clears this bit by writing a 1 to the bit position. 1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed. Note: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. After G3 State Select (AFTERG3_EN)—R/W. Determines what state to go to when power is reapplied after a power failure (G3 state). This bit is in the RTC well and is not cleared by any type of reset except writes to CF9h or RTCRST#. 0 0 = System will return to S0 state (boot) after power is re-applied. 1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the S5 state, the only enabled wake event is the Power Button or any enabled wake event that was preserved through the power failure.
R/W 8-bit ACPI, Legacy RTC
Bit 7:3
2
9.8.1.4
GPI_ROUT—GPI Routing Control Register (PM—D31:F0)
Offset Address: Default Value: Lockable:
Bit 31:30
B8h–BBh 0000h No
Attribute: Size: Power Well:
Description
R/W 32-bit Resume
GPI[15] Route—R/W. See bits 1:0 for description. Same pattern for GPI[14] through GPI[3]
5:4 3:2
GPI[2] Route—R/W. See bits 1:0 for description. GPI[1] Route—R/W. See bits 1:0 for description. GPI[0] Route—R/W. GPIO[13:11,8:6,4:3,1:0] can be routed to cause an SMI or SCI when the GPI[n]_STS bit is set. If the GPIO is not set to an input, this field has no effect. If the system is in an S1–S5 state and if the GPE1_EN bit is also set, then the GPI can cause a Wake event, even if the GPI is NOT routed to cause an SMI# or SCI.
1:0
00 = No effect. 01 = SMI# (if corresponding GPE1_EN bit is also set) 10 = SCI (if corresponding GPE1_EN bit is also set) 11 = Reserved
Note:
GPIOs that are not implemented will not have the corresponding bits implemented in this register.
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LPC Interface Bridge Registers (D31:F0)
9.8.1.5
TRP_FWD_EN—IO Monitor Trap Forwarding Enable Register (PM—D31:F0)
Offset Address: Default Value: Lockable: Power Well: C0h 00h No Core Attribute: Size: Usage: R/W (Special) 8 bits Legacy Only
The ICH2 uses this register to enable the monitors to forward cycles to LPC, independent of the POS_DEC_EN bit and the bits that enable the monitor to generate an SMI#. The only criteria is that the address passes the decoding logic as determined by the MON[n]_TRP_RNG and MON_TRP_MSK register settings.
Bit Description Monitor 7 Forward Enable (MON7_FWD_EN)—R/W. 7 0 = Disable. Cycles trapped by I/O Monitor 7 will not be forwarded to LPC. 1 = Enable. Cycles trapped by I/O Monitor 7 will be forwarded to LPC. Monitor 6 Forward Enable (MON6_FWD_EN)—R/W. 6 0 = Disable. Cycles trapped by I/O Monitor 6 will not be forwarded to LPC. 1 = Enable. Cycles trapped by I/O Monitor 6 will be forwarded to LPC. Monitor 5 Forward Enable (MON5_FWD_EN)—R/W. 5 0 = Disable. Cycles trapped by I/O Monitor 5 will not be forwarded to LPC. 1 = Enable. Cycles trapped by I/O Monitor 5 will be forwarded to LPC. Monitor 4 Forward Enable (MON4_FWD_EN)—R/W. 4 3:0 0 = Disable. Cycles trapped by I/O Monitor 4 will not be forwarded to LPC. 1 = Enable. Cycles trapped by I/O Monitor 4 will be forwarded to LPC. Reserved.
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LPC Interface Bridge Registers (D31:F0)
9.8.1.6
MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range Register for Devices 4–7 (PM—D31:F0)
Offset Address: Default Value: Lockable: Power Well: C4h, C6h, C8h, CAh 00h No Core Attribute: Size: Usage: R/W 16 bits Legacy Only
These registers set the ranges that Device Monitors 4–7 should trap. Offset 4Ch corresponds to Monitor 4. Offset C6h corresponds to Monitor 5, etc. If the trap is enabled in the MON_SMI register and the address is in the trap range (and passes the mask set in the MON_TRP_MSK register) the ICH2 generates an SMI#. This SMI# occurs if the address is positively decoded by another device on PCI or by the ICH2 (because it would be forwarded to LPC or some other ICH2 internal registers). The trap ranges should not point to registers in the ICH2’s internal IDE, USB, AC’97 or LAN I/O space. If the cycle is to be claimed by the ICH2 and targets one of the permitted ICH2 internal registers (interrupt controller, RTC, etc.), the cycle will complete to the intended target and an SMI# will be generated (this is the same functionality as the ICH component). If the cycle is to be claimed by the ICH2 and the intended target is on LPC, an SMI# will be generated but the cycle will only be forwarded to the intended target if forwarding to LPC is enabled via the TRP_FWD_EN register settings.
Bit Description Monitor Trap Base Address (MON[n]_TRAP_BASE)—R/W. Base I/O locations that MON[n] traps (where n = 4, 5, 6 or 7). The range can be mapped anywhere in the processor I/O space (0–64 KB). Any access to the range will generate an SMI# if enabled by the associated DEV[n]_TRAP_EN bit in the MON_SMI register (PMBASE +40h).
15:0
9.8.1.7
MON_TRP_MSK—I/O Monitor Trap Range Mask Register for Devices 4–7 (PM—D31:F0)
Offset Address: Default Value: Lockable: Power Well:
Bit 15:12 11:8 7:4
CCh 00h No Core
Attribute: Size: Usage:
R/W 16 bits Legacy Only
Description Monitor 7 Forward Mask (MON7_MASK)—R/W. Selects low 4-bit mask for the I/O locations that MON7 will trap. Similar to MON4_MASK. Monitor 6 Forward Mask (MON6_MASK)—R/W. Selects low 4-bit mask for the I/O locations that MON6 will trap. Similar to MON4_MASK. Monitor 5 Forward Mask (MON5_MASK)—R/W. Selects low 4-bit mask for the I/O locations that MON5 will trap. Similar to MON4_MASK. Monitor 4 Forward Mask (MON4_MASK)—R/W. Selects low 4-bit mask for the I/O locations that MON7 will trap. When a mask bit is set to a 1, the corresponding bit in the base I/O selection will not be decoded. For example, if MON4_TRAP_BASE = 1230h, and MON4_MSK = 0011b, the ICH2 will decode 1230h, 1231h, 1232h, and 1233h for Monitor 4.
3:0
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LPC Interface Bridge Registers (D31:F0)
9.8.2
APM I/O Decode
Table 9-9 shows the I/O registers associated with APM support. This register space is enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location).
Table 9-9. APM Register Map
Address B2h B3h Mnemonic APM_CNT APM_STS Register Name/Function Advanced Power Management Control Port Advanced Power Management Status Port Default 00h 00h Type R/W R/W
9.8.2.1
APM_CNT—Advanced Power Management Control Port Register
I/O Address: Default Value: Lockable: Power Well:
Bit 7:0
B2h 00h No Core
Attribute: Size: Usage:
R/W 8-bit Legacy Only
Description Used to pass an APM command between the OS and the SMI handler. Writes to this port not only store data in the APMC register but also generate an SMI# when the APMC_EN bit is set.
9.8.2.2
APM_STS—Advanced Power Management Status Port Register
I/O Address: Default Value: Lockable: Power Well:
Bit 7:0
B3h 00h No Core
Attribute: Size: Usage:
R/W 8-bit Legacy Only
Description Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and is not effected by any other register or function (other than a PCI reset).
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LPC Interface Bridge Registers (D31:F0)
9.8.3
Power Management I/O Registers
Table 9-10 shows the registers associated with ACPI and Legacy power management support. These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers are defined to be compliant with the ACPI 1.0 specification, and use the same bit names. Note: All reserved bits and registers will always return 0 when read, and will have no effect when written.
Table 9-10. ACPI and Legacy I/O Register Map
PMBASE+ Offset 00–01h 02–03h 04–07h 08–0Bh 0Ch 10h–13h 14h Register Name PM1 Status PM1 Enable PM1 Control PM1 Timer Reserved Processor Control Level 2 ICH2 (82801BA): 15h Reserved ICH2-M (82801BAM): Level 3 16–19h Reserved ICH2 (82801BA): 20h Reserved ICH2-M (82801BAM): PM2 Control 28–29h 2A–2Bh 2C–2D 2E–2F 30–31h 34–35h 36–3Fh 40h 42h 44h 48h 4Ch–4Dh 4Eh General Purpose Event 0 Status General Purpose Event 0 Enables General Purpose Event 1 Status General Purpose Event 1 Enables SMI# Control and Enable SMI Status Register Reserved Monitor SMI Status Reserved Device Trap Status Trap Enable register Bus Address Tracker Bus Cycle Tracker ICH2 (82801BA): 50h Reserved ICH2-M (82801BAM): SpeedStep™ Control 51–5Fh 60h–7Fh Reserved Reserved for TCO Registers — — — 00h — — WO — — — — — PM2a_CNT_BLK GPE0_BLK GPE0_BLK+2 GPE1_BLK GPE1_BLK+2 — — — — — — — — — 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h — 0000h 0000h Last Cycle Last Cycle R/W R/W R/W R/W R/W R/W R/W RO R/W — R/W R/W RO RO — — — P_BLK+5 — 0000h — RO — — — — ACPI Pointer PM1a_EVT_BLK PM1a_EVT_BLK+2 PM1a_CNT_BLK PMTMR_BLK — P_BLK P_BLK+4 Default 0000h 0000h 00000000h 00000000h — 00000000h 00h Attributes R/W R/W R/W RO — R/W RO
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LPC Interface Bridge Registers (D31:F0)
9.8.3.1
PM1_STS—Power Management 1 Status Register
I/O Address: Default Value: Lockable: Power Well: PMBASE + 00h (ACPI PM1a_EVT_BLK) 0000h No Bits 0–7: Core, Bits 8–15: Resume, except Bit 11 in RTC Attribute: Size: Usage: R/WC 16-bit ACPI or Legacy
If bit 10 or 8 in this register is 1 and the corresponding _EN bit is set in the PM1_EN register, ICH2 generates a Wake Event. Once back in an S0 state (or if already in S0 state when the event occurs), ICH2 also generates an SCI if the SCI_EN bit is set or an SMI# if the SCI_EN bit is not set. Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an SMI# or SCI.
Bit Description Wake Status (WAK_STS)—R/WC. This bit is not affected by hard resets caused by a CF9 write but is reset by RSMRST#. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN bit) and an enabled wake event occurs. Upon setting this bit, the ICH2 will transition the system to the ON state. 15 If the AFTERG3_EN bit is not set and a power failure occurs without the SLP_EN bit set, the system will return to an S0 state when power returns, and the WAK_STS bit will not be set. For the 82801BAM ICH2-M, power failure could result from removing the batteries. If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set, the system will go into an S5 state when power returns and a subsequent wake event will cause the WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by either a Power Button press or an enabled wake event that was preserved through the power failure (enable bit in the RTC well). 14:12 Reserved Power Button Override Status (PRBTNOR_STS)—R/WC. This bit is not affected by hard resets caused by a CF9 write and is not reset by RSMRST#. Thus, this bit will be preserved through a power failure. 11 0 = The BIOS or SCI handler can clear this bit by writing a 1 to it. 1 = Set by hardware anytime a Power Button Override Event occurs which occurs when the power button is pressed for at least 4 consecutive seconds. The power button override causes an unconditional transition to the S5 state and sets the AFTERG3 bit. This bit can also be set by the SMBus Slave logic. RTC Status (RTC_STS)—R/WC. This bit is not affected by hard resets caused by a CF9 write but is reset by RSMRST#. 10 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal). Additionally if the RTC_EN bit is set, the setting of the RTC_STS bit will generate a wake event. Reserved Power Button Status (PWRBTN_STS)—R/WC. This bit is not affected by hard resets caused by a CF9 write. 1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any other enable bit. In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if SCI_EN is not set) will be generated. In any sleeping state S1–S5, while PWRBTN_EN and PWRBTN_STS are both set, a wake event is generated. 0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state with only PWRBTN# enabled as a wake event. This bit can be cleared by software by writing a one to the bit position.
9
8
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LPC Interface Bridge Registers (D31:F0)
Bit 7:6 Reserved
Description
5
Global Status (GBL _STS)—R/WC. 1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit. 0 = The SCI handler should then clear this bit by writing a 1 to the bit location. ICH2 (82801BA): Reserved ICH2-M (82801BAM): Bus Master Status (BM_STS)— R/WC. 1 = Set by the ICH2-M when a bus master requests a break from the C3 state (the bus master break events are generated by PIRQ[x]# assertion or bus master activity by any of ICH2-M’s internal bus masters). Bus master activity is detected by any of the PCI requests being active, any internal bus master request being active, the AGPBUSY# signal being active, or activity on either of the ICH2-M’s USB Controllers. A USB Controller is considered active if all three of the following conditions are true 1. The controller is not in Global Suspend 2. At least one of the controller’s ports is not suspended 3. The USB RUN bit is set Bus Master IDE Controller activity also causes BM_STS to be set. The ICH2-M’s BMIDE Controller is considered active when the Controller’s Start bit is set. 0 = Software clears this bit by writing a 1 to the bit position. Reserved Timer Overflow Status (TMROF_STS)—R/WC. 1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit is set, then the setting of the TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN). 0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
4
3:1
0
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LPC Interface Bridge Registers (D31:F0)
9.8.3.2
PM1_EN—Power Management 1 Enable Register
I/O Address: Default Value: Lockable: Power Well: PMBASE + 02h (ACPI PM1a_EVT_BLK + 2) 0000h No Bits 0–7: Core, Bits 8–15: Resume Attribute: Size: Usage: R/W 16-bit ACPI or Legacy
Bit 15:11 Reserved.
Description
10
RTC Event Enable (RTC_EN)—R/W. This bit is in the RTC well to allow an RTC event to wake after a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override event. 1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes active. 0 = No SCI (or SMI#) or wake event is generated then RTC_STS goes active. Power Button Enable (PWRBTN_EN)—R/W. This bit is used to enable the setting of the PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no effect on the PWRBTN_STS bit being set by the assertion of the power button. The Power Button is always enabled as a Wake event. 0 = Disable. 1 = Enable. Global Enable (GBL_EN)—R/W. When both the GBL_EN and the GBL_STS are set, an SCI is raised. 0 = Disable. 1 = Enable SCI on GBL_STS going active. Timer Overflow Interrupt Enable (TMROF_EN)—R/W. Works in conjunction with the SCI_EN bit as described below:
8
5
0
TMROF_EN 0 1 1
SCI_EN x 0 1
Effect when TMROF_STS is set No SMI# or SCI SMI# SCI
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LPC Interface Bridge Registers (D31:F0)
9.8.3.3
PM1_CNT—Power Management 1 Control Register
I/O Address: Default Value: Lockable: Power Well: PMBASE + 04h (ACPI PM1a_CNT_BLK) 0000h No Bits 0–7: Core, Bits 8–15: Resume Attribute: Size: Usage: R/W 32-bit ACPI or Legacy
Bit 13
Description Sleep Enable (SLP_EN)—WO. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. Sleep Type (SLP_TYP)—R/W. This 3-bit field defines the type of Sleep the system should enter when the SLP_EN bit is set to 1. 000 = ON: Typically maps to S0 state.. 001 = ICH2 (82801BA): Assert STPCLK#. Puts processor in Stop-Grant state. Optional to assert CPUSLP# to put processor in sleep state: Typically, maps to S1 state. ICH2-M (82801BAM): Reserved.
12:10
010 = ICH2 (82801BA): Reserved ICH2-M (82801BAM): Assert SLP_S1#: Typically, maps to S1 state. 011 = Reserved 100 = Reserved 101 = Suspend-To-RAM. Assert SLP_S1# and SLP_S3#; typically, maps to S3 state. 110 = Suspend-To-Disk. Assert SLP_S1#, SLP_S3#, and SLP_S5# SLP_S3# and, SLP_S5#; typically, maps to S4 state. 111 = Soft Off. Assert SLP_S1#, SLP_S3#, and SLP_S5# SLP_S3#, and SLP_S5#; typically, maps to S5 state. Global Release (GBL_RLS)—WO. 1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has corresponding enable and status bits to control its ability to receive ACPI events. 0 = This bit always reads as 0. ICH2 (82801BA): Reserved ICH2-M (82801BAM):
2
1
Bus Master Reload (BM_RLD)— R/W. This bit is reset to 0 by PCIRST# 0 = Bus master requests do not cause a break from the C3 state. 1 = Enable Bus Master requests (internal, external or AGPBUSY#) to cause a break from the C3 state. SCI Enable (SCI_EN)—R/W. Selects the SCI interrupt or the SMI# interrupt for various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS. 0 = These events will generate an SMI#. 1 = These events will generate an SCI.
0
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LPC Interface Bridge Registers (D31:F0)
9.8.3.4
PM1_TMR—Power Management 1 Timer Register
I/O Address: Default Value: Lockable: Power Well:
Bit 31:24 Reserved Timer Value (TMR_VAL)—RO. Returns the running count of the PM timer. This counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to zero during a PCI reset and then continues counting as long as the system is in the S0 state. Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit is set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit is set, an SCI interrupt is also generated.
PMBASE + 08h (ACPI PMTMR_BLK) xx000000h No Core Attribute: Size: Usage: RO 32-bit ACPI
Description
23:0
9.8.3.5
PROC_CNT—Processor Control Register
I/O Address: Default Value: Lockable: Power Well:
Bit 31:18 Reserved. Throttle Status (THTL_STS)—RO. 17 0 = No clock throttling is occurring (maximum processor performance). 1 = Indicates that the clock state machine is in some type of low power state (where the processor is not running at its maximum performance): thermal throttling or hardware throttling. Reserved Force Thermal Throttling (FORCE_THTL)—R/W. Software can set this bit to force the thermal throttling function. This has the same effect as the THRM# signal being active for 2 seconds. 8 0 = No forced throttling. 1 = Throttling at the duty cycle specified in THRM_DTY starts immediately (no 2 second delay), and no SMI# is generated. Thermal Duty Cycle (THRM_DTY). This write-once 3-bit field determines the duty cycle of the throttling when the thermal override condition occurs. The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs. Note that the throttling only occurs if the system is in the C0 state. If in the C2 state, no throttling occurs. There is no enable bit for thermal throttling, because it should not be disabled. Once the THRM_DTY field is written, any subsequent writes will have no effect until PCIRST# goes active. 7:5 THRM_DTY 000 001 010 011 100 101 110 111 Throttle Mode RESERVED (Default) (Will be 50%) 87.5% 75.0% 62.5% 50% 37.5% 25% 12.5% PCI Clocks 512 896 768 640 512 384 256 128
PMBASE + 10h (ACPI P_BLK) 00000000h No (bits 7:5 are write once) Core
Attribute: Size: Usage:
R/W 32-bit ACPI or Legacy
Description
16:9
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LPC Interface Bridge Registers (D31:F0)
Bit
Description Throttling Enable (THTL_EN). When this bit is set and the system is in a C0 state, processorcontrolled STPCLK# throttling is enabled. The duty cycle is selected in the THTL_DTY field. 0 = Disable 1 = Enable Throttling Duty Cycle (THTL_DTY). This 3-bit field determines the duty cycle of the throttling when the THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs. THTL_DTY 000 Throttle Mode RESERVED (Default) (Will be 50%) 87.5% 75.0% 62.5% 50% 37.5% 25% 12.5% PCI Clocks 512 896 768 640 512 384 256 128
4
3:1
001 010 011 100 101 110 111 Reserved
0
9.8.3.6
LV2—Level 2 Register
I/O Address: Default Value: Lockable: Power Well:
Bit
PMBASE + 14h (ACPI P_BLK+4) 00h No Core
Attribute: Size: Usage:
RO 8-bit ACPI or Legacy
Description Reads to this register return all zeros; writes have no effect. Reads to this register generate a “enter a level 2 power state” (C2) to the clock control logic. This causes the STPCLK# signal to go active, and stay active until a break event occurs. Throttling (due either to THTL_EN or THRM# override) will be ignored.
7:0
9.8.3.7
LV3—Level 3 Register (82801BAM ICH2-M)
I/O Address: Default Value: Lockable: PMBASE + 15h (ACPI P_BLK + 5) Attribute: 00h Size: No Usage: Power Well:
Description Reads to this register return all zeros, writes to this register have no effect. Reads to this register generate an “enter a C3 power state” to the clock control logic. The C3 state persists until a break event occurs.
RO 8-bit ACPI or Legacy Core
Bit 7:0
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LPC Interface Bridge Registers (D31:F0)
9.8.3.8
PM2_CNT—Power Management 2 Control (82801BAM ICH2-M)
I/O Address: Default Value: Lockable: Power Well:
Bit 7:1 Reserved. Arbiter Disable (ARB_DIS)— R/W. 0 = Enable system arbiter. The arbiter can grant the bus to bus masters (internal devices or external PCI devices), other than the processor. 0 1 = Disable system arbiter (default). Processor has ownership of the system bus and memory. No bus masters (internal or external) are granted the bus. Note that after the arbiter is disabled, the processor must not initiate any down-bound reads to PCI devices that may have up-bound posted data, as this will result in system deadlock.
PMBASE + 20h (ACPI PM2_BLK) 00h No Core
Attribute: Size: Usage:
R/W 8-bit ACPI
Description
9.8.3.9
GPE0_STS—General Purpose Event 0 Status Register
I/O Address: Default Value: Lockable: Power Well: PMBASE + 28h (ACPI GPE0_BLK) 0000h No Resume Attribute: Size: Usage: R/WC 16-bit ACPI
Note:
This register is symmetrical to the General Purpose Event 0 Enable Register. If the corresponding seen bit is set, then when the _STS bit get set, ICH2 generates a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), ICH2 also generates an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set. There will be no SCI/SMI# or wake event on THRMOR_STS since there is no corresponding x_EN bit. None of these bits are reset by CF9h write. All are reset by RSMRST#.
Bit 15:12 Reserved. PME Status (PME_STS)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set, and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1–S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event, and an SCI will be generated. If the system is in an S5 state due to power button override or a power failure, then PME_STS will not cause a wake event or SCI. ICH2 (82801BA): Reserved 10 ICH2-M (82801BAM): BATLOW_STS — R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when the BATLOW# signal is asserted. Description
11
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LPC Interface Bridge Registers (D31:F0)
Bit ICH2 (82801BA): Reserved ICH2-M (82801BAM): 9
Description
Global Standby Timer Status (GST_STS)— R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware to indicate that the wake event was due to GST timeout. This bit will only be set when the system was in the S1 state. RI_STS—R/WC.
8
0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when the RI# input signal goes active. SMBus Wake Status (SMB_WAK_STS)—R/WC. SMBus Wake Status—R/WC. The SMBus controller can independently cause an SMI# or SCI; thus, this bit does not need to do so (unlike the other bits in this register).
7
0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware to indicate that the wake event was caused by the ICH2’s SMBus logic. This bit is set by the WAKE/SMI# command type, even if the system is already awake. The SMI handler should then clear this bit. TCO SCI Status (TCOSCI_STS)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when the TCO logic causes an SCI. AC97 Status (AC97_STS)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit gets set only from the following two cases: 1. ACSDIN[1] or ACSDIN[0] is high and BITCLK is not oscillating, or 2. The GSCI bit is set (section 13.2.9, NAMBAR +30h, bit 0) USB Controller 2 Status (USB2_STS)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when USB Controller 2 needs to cause a wake. Wake event will be generated if the corresponding USB2_EN bit is set. USB Controller 1 Status (USB1_STS)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware when USB Controller 1 needs to cause a wake. Wake event will be generated if the corresponding USB1_EN bit is set. Reserved. Thermal Interrupt Override Status (THRMOR_STS)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = This bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling the processor’s clock at the THRM_DTY ratio. This will not cause an SMI#, SCI, or wake event. Thermal Interrupt Status (THRM_STS)—R/WC. 0 = Software clears this bit by writing a 1 to the bit position. 1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL bit. Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also generate a power management event (SCI or SMI#).
6
5
4
3
2
1
0
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LPC Interface Bridge Registers (D31:F0)
9.8.3.10
GPE0_EN—General Purpose Event 0 Enables Register
I/O Address: Default Value: Lockable: Power Well: PMBASE + 2Ah (ACPI GPE0_BLK + 2) 0000h No Bits 0–7 Resume, Bits 8–15 RTC Attribute: Size: Usage: R/W 16-bit ACPI
Note:
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this register should be cleared to 0 based on a Power Button Override. The resume well bits are all cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#.
Bit 15:12 Reserved. PME# Enable (PME_EN)—R/W. 11 0 = Disable. 1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be a wake event from the S1–S4 state or from S5 (if entered via SLP_EN, but not power button override). ICH2 (82801BA): Reserved ICH2-M (82801BAM): 10 BATLOW_EN — R/W. 0 = Disable. 1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN bit) when it goes low. This bit does not prevent the BATLOW# signal from inhibiting the wake event. 9 Reserved RI_EN—R/W. The value of this bit will be maintained through a G3 state and is not affected by a hard reset caused by RSMRST# or a CF9h write. Assertion of RTCRST# resets this bit. 0 = Disable. 1 = Enables the setting of the RI_STS to generate a wake event. Reserved TCO SCI Enable (TCOSCI_EN)—R/W. 6 0 = Disable. 1 = Enables the setting of the TCOSCI_STS to generate an SCI. AC97 Enable (AC97_EN)—R/W. 5 0 = Disable. 1 = Enables the setting of the AC97_STS to generate a wake event. USB Controller 2 Enable (USB2_EN)—R/W. 4 0 = Disable. 1 = Enables the setting of the USB2_STS to generate a wake event. USB Controller 1 Enable (USB1_EN)—R/W. 3 0 = Disable. 1 = Enables the setting of the USB1_STS to generate a wake event. Thermal Pin Polarity (THRM#_POL)—R/W. This bit controls the polarity of the THRM# pin needed to set the THRM_STS bit. 0 = Low value on the THRM# signal will set the THRM_STS bit. 1 = HIGH value on the THRM# signal will set the THRM_STS bit. Reserved. Thermal Signal Reporting Enable (THRM_EN)—R/W. 0 0 = Disable. 1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the THRM_STS bit and generate a power management event (SCI or SMI). Description
8
7
2
1
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LPC Interface Bridge Registers (D31:F0)
9.8.3.11
GPE1_STS—General Purpose Event 1 Status Register
I/O Address: Default Value: Lockable: Power Well: PMBASE + 2Ch (ACPI GPE1_BLK) 0000h No Resume Attribute: Size: Usage: R/WC 16-bit ACPI
Note:
This register is symmetrical to the General Purpose Event 1 Enable Register. GPIOs that are not implemented will not have the corresponding bits implemented in this register. Bits 5 and 2 are not implemented since GPIO5 and GPIO2 are not implemented.
Bit Description GPI[15:6] Status (GPI[15:6]_STS)—R/WC. 0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal is not active. (The status bit cannot be cleared while the corresponding signal is still active). 1 = These bits are set any time the corresponding GPIO is set up as an input and the corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set). 15:6 If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is set, then: - If the system is in an S1_S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will be generated, depending on the GPI_ROUT bits for the corresponding GPI. 5 Reserved GPI[4:3] Status (GPI[4:3]_STS)—R/WC. 0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal is not active. (The status bit cannot be cleared while the corresponding signal is still active). 1 = These bits are set any time the corresponding GPIO is set up as an input and the corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set). 4:3 If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is set, then: - If the system is in an S1_S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will be generated, depending on the GPI_ROUT bits for the corresponding GPI. 2 Reserved GPI[1:0] Status (GPI[1:0]_STS)—R/WC. 0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal is not active. (The status bit cannot be cleared while the corresponding signal is still active). 1 = These bits are set any time the corresponding GPIO is set up as an input and the corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set). 1:0 If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is set, then: - If the system is in an S1_S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will be generated, depending on the GPI_ROUT bits for the corresponding GPI.
Note:
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LPC Interface Bridge Registers (D31:F0)
9.8.3.12
GPE1_EN—General Purpose Event 1 Enable Register
I/O Address: Default Value: Lockable: Power Well: PMBASE + 2Eh (ACPI GPE1_BLK + 2) 0000h No Resume Attribute: Size: Usage: R/W 16-bit ACPI
Note:
This register is symmetrical to the General Purpose Event 1 Status Register. GPIOs that are not implemented will not have the corresponding bits implemented in this register. All of the bits in this register will be cleared by RSMRST#. Bits 5 and 2 are not implemented since GPIO5 and GPIO2 are not implemented.
Bit Description GPI[15:6] Enable (GPI[15:6]_EN)—R/W. 1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event. 0 = Disable. 5 4:3 2 1:0 Reserved GPI[4:3] Enable (GPI[4:3]_EN)—R/W. 1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event. 0 = Disable. Reserved GPI[1:0] Enable (GPI[1:0]_EN)—R/W. 1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event. 0 = Disable.
Note:
15:6
9.8.3.13
SMI_EN—SMI Control and Enable Register
I/O Address: Default Value: Lockable: Power Well:
Bit 31:15 Reserved Periodic SMI# Enable (PERIODIC_EN)—R/W. 14 0 = Disable. 1 = Enables the ICH2 to generate an SMI# when the PERIODIC_STS bit is set in the SMI_STS register. TCO Enable (TCO_EN)—R/W. 13 0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs. 1 = Enables the TCO logic to generate SMI#. Reserved Microcontroller SMI# Enable (MCSMI_EN)—R/W. 11 0 = Disable. 1 = Enables ICH2 to trap accesses to the microcontroller range (62h or 66h) and generate an SMI#. Note that ’trapped’ cycles will be claimed by the ICH2 on PCI, but not forwarded to LPC. Reserved
PMBASE + 30h 0000h No Core
Attribute: Size: Usage:
R/W 32 bit ACPI or Legacy
Description
12
10:8
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LPC Interface Bridge Registers (D31:F0)
Bit BIOS Release (BIOS_RLS)—WO. 7
Description
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect. 1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit position by BIOS software. Software SMI# Timer Enable (SWSMI_TMR_EN)—R/W. 0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the SMI# will not be generated. 1 = Starts Software SMI# Timer. When the SWSMI timer expires (the time-out period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated. SWSMI_TMR_EN stays set until cleared by software. APMC Enable (APMC_EN)—R/W. 0 = Disable. Writes to the APM_CNT register will not cause an SMI#. 1 = Enables writes to the APM_CNT register to cause an SMI#. SLP SMI Enable (SLP_SMI_EN)—R/W. 0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit. 1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the system will not transition to the sleep state based on that write to the SLP_EN bit. Legacy USB Enable (LEGACY_USB_EN)—R/W. 0 = Disable. 1 = Enables legacy USB circuit to cause SMI#. BIOS Enable (BIOS_EN)—R/W. 0 = Disable. 1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit. End of SMI (EOS)—R/W (special). This bit controls the arbitration of the SMI signal to the processor. This bit must be set for the ICH2 to assert SMI# low to the processor. 1 = When this bit is set, SMI# signal will be deasserted for 4 PCI clocks before its assertion. In the SMI handler, the processor should clear all pending SMIs (by servicing them and then clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to reassert SMI upon detection of an SMI event and the setting of a SMI status bit. 0 = Once the ICH2 asserts SMI# low, the EOS bit is automatically cleared. Global SMI Enable (GBL_SMI_EN)—R/W.
6
5
4
3
2
1
0
0 = No SMI# will be generated by ICH2. This bit is reset by a PCI reset event. 1 = Enables the generation of SMI# in the system upon any enabled SMI event.
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LPC Interface Bridge Registers (D31:F0)
9.8.3.14
SMI_STS—SMI Status Register
I/O Address: Default Value: Lockable: Power Well: PMBASE + 34h 0000h No Core Attribute: Size: Usage: R/W 32-bit ACPI or Legacy
Note:
If the corresponding _EN bit is set when the _STS bit is set, the ICH2 will cause an SMI# (except bits 8:10 and 12, which do not need enable bits since they are logic ORs of other registers that have enable bits).
Bit 31:17 Reserved SMBus SMI Status (SMBUS_SMI_STS)—R/WC. 1 = Indicates that the SMI# was caused by either the SMBus Slave receiving a message, or the SMBALERT# signal going active. This bit will be set on SMBALERT# assertion only if the SMBus Host Controller is programmed to generate SMIs (not interrupts). 0 = This bit is cleared by writing a 1 to its bit position. 15 SERR IRQ SMI Status (SERIRQ_SMI_STS)—RO. 1 = Indicates that the SMI# was caused by the SERIRQ decoder. 0 = SMI# was not caused by SERIRQ decoder. This is not a sticky bit. Periodic Status (PERIODIC_STS)—R/WC. 1 = This bit will be set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit is also set, the ICH2 will generate an SMI#. 0 = This bit is cleared by writing a 1 to its bit position. TCO Status (TCO_STS)—RO. 13 0 = SMI# not caused by TCO logic. 1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event. Device Monitor Status (DEVMON_STS)—RO. 1 = Set under any of the following conditions: - Any of the DEV[7:4]_TRAP_STS bits are set and the corresponding DEV[7:4]_TRAP_EN bits are also set. - Any of the DEVTRAP_STS bits are set and the corresponding DEVTRAP_EN bits are also set. 0 = SMI# not caused by Device Monitor. Microcontroller SMI# Status (MCSMI_STS)—R/WC. 11 0 = Indicates that there has been no access to the power management microcontroller range (62h or 66h). This bit is cleared by software writing a 1 to the bit position. 1 = Set if there has been an access to the power management microcontroller range (62h or 66h). If this bit is set, and the MCSMI_EN bit is also set, the ICH2 will generate an SMI#. GPE1 Status (GPE1_STS)—RO. This bit is a logical OR of the bits in the GPE1_STS register that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the corresponding bit set in the GPE1_EN register. Bits that are not routed to cause an SMI# will have no effect on the GPE1_STS bit. 0 = SMI# was not generated by a GPI assertion. 1 = SMI# was generated by a GPI assertion. GPE0 Status (GPE0_STS)—RO. This bit is a logical OR of the bits in the GPE0_STS register that also have the corresponding bit set in the GPE0_EN register. 0 = SMI# was not generated by a GPE0 event. 1 = SMI# was generated by a GPE0 event. PM1 Status Register (PM1_STS_REG)—RO. This is an OR of the bits in the ACPI PM1 Status Register (offset PMBASE+00h) that can cause an SMI#. 0 = SMI# was not generated by a PM1_STS event. 1 = SMI# was generated by a PM1_STS event. Reserved. Description
16
14
12
10
9
8
7
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LPC Interface Bridge Registers (D31:F0)
Bit
Description Software SMI Timer Status (SWSMI_TMR_STS)—R/WC. 1 = Set by the hardware when the Software SMI# Timer expires. 0 = Software clears this bit by writing a 1 to the bit location. APM Status (APM_STS)—R/WC. 1 = SMI# was generated by a write access to the APM control register with the APMC_EN bit set. 0 = Software clears this bit by writing a 1 to the bit location. SLP SMI Status (SLP_SMI_STS)—R/WC. 1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set. 0 = Software clears this bit by writing a 1 to the bit location. Legacy USB Status (LEGACY_USB_STS)—RO. This bit is a logical OR of each of the SMI status bits in the USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. 0 = SMI# was not generated by USB Legacy event. 1 = SMI# was generated by USB Legacy event. BIOS Status (BIOS_STS)—R/WC. 1 = SMI# was generated due to ACPI software requesting attention (writing a 1 to the GBL_RLS bit with the BIOS_EN bit set). 0 = This bit cleared by software writing a 1 to its bit position. Reserved.
6
5
4
3
2
1:0
9.8.3.15
MON_SMI—Device Monitor SMI Status and Enable Register
I/O Address: Default Value: Lockable: Power Well:
Bit
PMBASE +40h 0000h No Core
Attribute: Size: Usage:
R/W, R/WC 16-bit Legacy Only
Description Device 7:4 Trap Status (DEV[7:4]_TRAP_STS)—R/WC. Bit 12 corresponds to Monitor 4, bit 13 corresponds to Monitor 5 etc. 1 = SMI# was caused by an access to the corresponding device monitor’s I/O range. 0 = SMI# was not caused by the associated device monitor. Device 7:4 Trap Enable (DEV[7:4]_TRAP_EN)—R/W. Bit 8 corresponds to Monitor 4, bit 9 corresponds to Monitor 5 etc. 1 = Enables SMI# due to an access to the corresponding device monitor’s I/O range. 0 = Disable. Reserved
15:12
11:8
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LPC Interface Bridge Registers (D31:F0)
9.8.3.16
DEVACT_STS—Device Activity Status Register
I/O Address: Default Value: Lockable: Power Well: PMBASE +44h 0000h No Core Attribute: Size: Usage: R/WC 16-bit Legacy Only
This register is used in conjunction with the Periodic SMI# timer to detect any system activity for legacy power management.
Bit 15:14 13 Reserved ADLIB Activity Status (ADLIB_ACT_STS)—R/WC. 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. Keyboard Controller Activity Status (KBC_ACT_STS)—R/WC. KBC (60/64h). 12 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. MIDI Activity Status (MIDI_ACT_STS)—R/WC. 11 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. Audio Activity Status (AUDIO_ACT_STS)—R/WC. Audio (Sound Blaster “ORed” with MSS). 10 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. PIRQ[D or H] Activity Status (PIRQDH_ACT_STS)—R/WC. 9 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQ[C or G] Activity Status (PIRQCG_ACT_STS)—R/WC. 8 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQ[B or F] Activity Status (PIRQBF_ACT_STS)—R/WC. 7 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQ[A or E] Activity Status (PIRQAE_ACT_STS)—R/WC. 6 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. Legacy Activity Status (LEG_ACT_STS)—R/WC. Parallel Port, Serial Port 1, Serial Port 2, Floppy Disk Controller. 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. Reserved. IDE Secondary Drive 1 Activity Status (IDES1_ACT_STS)—R/WC. 3 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. IDE Secondary Drive 0 Activity Status (IDES0_ACT_STS)—R/WC. 2 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. Description
5
4
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LPC Interface Bridge Registers (D31:F0)
Bit
Description IDE Primary Drive 1 Activity Status (IDEP1_ACT_STS)—R/WC.
1
0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. IDE Primary Drive 0 Activity Status (IDEP0_ACT_STS)—R/WC. 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.
0
9.8.3.17
DEVTRAP_EN—Device Trap Enable Register
I/O Address: Default Value Lockable: Power Well: PMBASE +48h 0000h No Core Attribute: Size: Usage: R/W 16-bit Legacy Only
This register enables the individual trap ranges to generate an SMI# when the corresponding status bit in the DEVACT_STS register is set. When a range is enabled, I/O cycles associated with that range will not be forwarded to LPC or IDE.
Bit 15:14 13 Reserved ADLIB Trap Enable (ADLIB_TRP_EN)—R/W. 0 = Disable. 1 = Enable. KBC Trap Enable (KBC_TRP_EN)—R/W. KBC (60/64h). 12 0 = Disable. 1 = Enable. MIDI Trap Enable (MIDI_TRP_EN)—R/W. 11 0 = Disable. 1 = Enable. Audio Trap Enable (AUDIO_TRP_EN)—R/W. Audio (Sound Blaster “ORed” with MSS). 10 9:6 5 4 3 0 = Disable. 1 = Enable. Reserved LEG_IO_TRP_EN—R/W. Parallel Port, Serial Port 1, Serial Port 2, Floppy Disk Controller. 0 = Disable. 1 = Enable. Reserved. IDE Secondary Drive 1 Trap Enable (IDES1_TRP_EN)—R/W. 0 = Disable. 1 = Enable. IDE Secondary Drive 0 Trap Enable (IDES0_TRP_EN)—R/W. 2 0 = Disable. 1 = Enable. IDE Primary Drive 1 Trap Enable (IDEP1_TRP_EN)—R/W. 1 0 = Disable. 1 = Enable. IDE Primary Drive 0 Trap Enable (IDEP0_TRP_EN)—R/W. 0 0 = Disable. 1 = Enable. Description
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LPC Interface Bridge Registers (D31:F0)
9.8.3.18
BUS_ADDR_TRACK—Bus Address Tracker Register
I/O Address: Lockable: Power Well: PMBASE +4Ch No Core Attribute: Size: Usage: RO 16-bit Legacy Only
This register could be used by the SMI# handler to assist in determining what was the last cycle from the processor.
Bit 15:0 Description Corresponds to the low 16 bits of the last I/O cycle, as would be defined by the PCI AD[15:0] signals on the PCI bus (even though it may not be a real PCI cycle). The value is latched based on SMI# active. This functionality is useful for figuring out which I/O was last being accessed.
9.8.3.19
BUS_CYC_TRACK—Bus Cycle Tracker Register
I/O Address: Lockable: Power Well: PMBASE +4Eh No Core Attribute: Size: Usage: RO 8-bit Legacy Only
This register could be used by the SMM handler to assist in determining what was the last cycle from the processor.
Bit 7:4 3:0 Description Corresponds to the byte enables, as would be defined by the PCI C/BE# signals on the PCI bus (even though it may not be a real PCI cycle). The value is latched based on SMI# going active. Corresponds to the cycle type, as would be defined by the PCI C/BE# signals on the PCI bus (even though it may not be a real PCI cycle). The value is latched based on SMI# going active.
9.8.3.20
SS_CNT— SpeedStep™ Control Register (82801BAM ICH2-M)
I/O Address: Default Value Lockable: Power Well: PMBASE +50h 01h No Core Attribute: Size: Usage: R/W (special) 8-bit ACPI/Legacy
Writes to this register initiates an Intel® SpeedStep™ transition, which involves a temporary transition to a C3-like state in which the STPCLK# signal will go active. An Intel® SpeedStep™ transition always occur on writes to the SS_CNT register, even if the value written to SS_STATE is the same as the previous value (after this “transition” the system would still be in the same Intel® SpeedStep™ state).
Bit 7:1 Reserved SpeedStepTM State (SS_STATE)— R/W (Special). When this bit is read, it will return the current SpeedStep™ state. Writes to this register will cause a change to the SpeedStepTM state indicated by the value written to this bit. 0 = High-power state. 1 = Low-power state. Description
0
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LPC Interface Bridge Registers (D31:F0)
9.9
System Management TCO Registers (D31:F0)
The TCO logic is accessed via registers mapped to the PCI configuration space (Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers, see LPC Device 31:Function 0 PCI Configuration registers.
9.9.1
TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which is, ACPIBASE + 60h in the PCI configuration space. The following table shows the mapping of the registers within that 32-byte range. Each register is described in the sections below.
Table 9-11. TCO I/O Register Map
Offset 00h 01h 02h 03h 04h–05h 06h–07h 08h–09h 0Ah–0Bh 0Ch–0Dh 0Eh 0Fh 10h 11h–1Fh SW_IRQ_GEN Mnemonic TCO_RLD TCO_TMR TCO_DAT_IN TCO_DAT_OUT TCO1_STS TCO2_STS TCO1_CNT TCO2_CNT TCO_MESSAGE1, TCO_MESSAGE2 TCO_WDSTATUS Register Name: Function TCO Timer Reload and Current Value TCO Timer Initial Value TCO Data In TCO Data Out TCO Status TCO Status TCO Control TCO Control Used by BIOS to indicate POST/Boot progress Watchdog Status Register Reserved Software IRQ Generation Register Reserved Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W RO
9.9.2
TCO1_RLD—TCO Timer Reload and Current Value Register
I/O Address: Default Value: Lockable:
Bit 7:0
TCOBASE +00h 0000h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
TCO Timer Value. Reading this register will return the current count of the TCO timer. Writing any value to this register will reload the timer to prevent the time-out. Bits 7:6 will always be 0.
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9.9.3
TCO1_TMR—TCO Timer Initial Value Register
I/O Address: Default Value: Lockable:
Bit 7:6 5:0 Reserved TCO Timer Initial Value. Value that is loaded into the timer each time the TCO_RLD register is written. Values of 0h–3h will be ignored and should not be attempted. The timer is clocked at approximately 0.6 seconds, and this allows time-outs ranging from 2.4 seconds to 38 seconds.
TCOBASE +01h 0004h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
9.9.4
TCO1_DAT_IN—TCO Data In Register
I/O Address: Default Value: Lockable:
Bit 7:0
TCOBASE +02h 0000h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
TCO Data In Value. Data Register for passing commands from the OS to the SMI handler. Writes to this register will cause an SMI and set the OS_TCO_SMI bit in the TCO_STS register.
9.9.5
TCO1_DAT_OUT—TCO Data Out Register
I/O Address: Default Value: Lockable:
Bit 7:0
TCOBASE +03h 0000h No
Attribute: Size: Power Well:
Description
R/W 8-bit Core
TCO Data Out Value. Data Register for passing commands from the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL bits.
9.9.6
TCO1_STS—TCO1 Status Register
I/O Address: Default Value: Lockable: TCOBASE +04h 0000h No Attribute: Size: Power Well: R/WC RO 16-bit Core (Except bit 7, in RTC)
Bit 15:13 Reserved
Description
12
Hub Interface SERR Status (HUBSERR_STS)—R/WC. 1 = ICH2 received an SERR# message via the hub interface. The software must read the memory controller hub (or its equivalent) to determine the reason for the SERR#. 0 = Software clears this bit by writing a 1 to the bit position. Hub Interface NMI Status (HUBNMI_STS)—R/WC. 1 = ICH2 received an NMI message via the hub interface. The software must read the memory controller hub (or its equivalent) to determine the reason for the NMI. 0 = Software clears this bit by writing a 1 to the bit position.
11
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Bit
Description Hub Interface SMI Status (HUBSMI_STS)—R/WC. 1 = ICH2 received an SMI message via the hub interface. The software must read the memory controller hub (or its equivalent) to determine the reason for the SMI#. 0 = Software clears this bit by writing a 1 to the bit position. Hub Interface SCI Status (HUBSCI_STS)—R/WC. 1 = ICH2 received an SCI message via the hub interface. The software must read the memory controller hub (or its equivalent) to determine the reason for the SCI. 0 = Software clears this bit by writing a 1 to the bit position. BIOS Write Status (BIOSWR_STS)—R/WC. 1 = ICH2 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS. This occurs when either: a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or b) any write is attempted to the BIOS and the BIOSWP bit is also set. 0 = Software clears this bit by writing a 1 to the bit position. Note:On write cycles attempted to the 4 MB lower alias to the BIOS space, the BIOSWR_STS will not be set. New Century Status (NEWCENTURY_STS)—R/WC. This bit is in the RTC well. 1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00. Setting this bit will cause an SMI# (but not a wake event). 0 = Cleared by writing a 1 to the bit position or by RTCRST# going active. Note that the NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when RTC power has not been maintained). Software can determine if RTC power has not been maintained by checking the RTC_PWR_STS bit or by other means (e.g., a checksum on RTC RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a legal value and then clear the NEWCENTURY_STS bit. The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a “1” is written to the bit to clear it. After writing a “1” to this bit, software should not exit the SMI handler until verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered.
10
9
8
7
6:4 3
Reserved Time Out Status (TIMEOUT)—R/WC. 1 = Set by ICH2 to indicate that the SMI was caused by the TCO timer reaching 0. 0 = Software clears this bit by writing a 1 to the bit position. TCO Interrupt Status (TCO_INT_STS)—R/WC. 1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register. 0 = Software clears this bit by writing a 1 to the bit position. Software TCO SMI Status (SW_TCO_SMI)—R/WC. 1 = Software caused an SMI# by writing to the TCO_DAT_IN register. 0 = Software clears this bit by writing a 1 to the bit position. NMI to SMI Status (NMI2SMI_STS)—RO. 1 = Set by the ICH2 when an SMI# occurs because an event occurred that would otherwise have caused an NMI (because NMI2SMI_EN is set). 0 = Cleared by clearing the associated NMI status bit.
2
1
0
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9.9.7
TCO2_STS—TCO2 Status Register
I/O Address: Default Value: Lockable: TCOBASE +06h 0000h No Attribute: Size: Power Well: R/WC, RO 16-bit Resume (Except Bit 0, in RTC)
Bit 15:3 Reserved
Description
Boot Status (BOOT_STS): 1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the first instruction. 2 0 = Cleared by ICH2 based on RSMRST# or by software writing a 1 to this bit. Note that software should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit. If rebooting due to a second TCO timer time-out and if the BOOT_STS bit is set, the ICH2 will reboot using the ‘safe’ multiplier (1111). This allows the system to recover from a processor frequency multiplier that is too high, and allows the BIOS to check the BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the BIOS knows that the processor has been programmed to an illegal multiplier. Second TCO Time-out Status (SECOND_TO_STS)—R/WC. 1 = The ICH2 sets this bit to a 1 to indicate that the TCO timer timed out a second time (probably due to system lock). If this bit is set the ICH2 will reboot the system after the second time-out. The reboot is done by asserting PCIRST#. 0 = This bit is cleared by writing a 1 to the bit position or by a RSMRST#. Intruder Detect (INTRD_DET)—R/WC. 1 = Set by ICH2 to indicate that an intrusion was detected. This bit is set even if the system is in G3 state. 0 = This bit is only cleared by writing a 1 to the bit position, or by RTCRST# assertion.
1
0
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9.9.8
TCO1_CNT—TCO1 Control Register
I/O Address: Default Value: Lockable:
Bit 15:12 Reserved TCO Timer Halt (TCO_TMR_HLT)—R/W. 11 0 = The TCO Timer is enabled to count. 1 = The TCO Timer will halt. It will not count and, thus, cannot reach a value that will cause an SMI# or set the SECOND_TO_STS bit. When set, this bit prevents rebooting and prevents Alert On LAN event messages from being transmitted on the SMLINK (but not Alert On LAN heartbeat messages). Send Now (SENDNOW)—R/W (special). 1 = Writing a 1 to this bit will cause the ICH to send an Alert On LAN Event message over the SMLINK interface, with the Software Event bit set. 10 0 = The ICH will clear this bit when it has completed sending the message. Software must not set this bit to 1 again until the ICH has set it back to 0. Setting the SENDNOW bit causes the ICH2 integrated LAN Controller to reset, which can have unpredictable side-effects. Unless software protects against these side effects, software should not attempt to set this bit. NMI to SMI Enable (NMI2SMI_EN)—R/W. 0 = Normal NMI functionality. 1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table: 9 NMI_EN 0 0 1 1 GBL_SMI_EN 0 1 0 1 Description No SMI# at all because GBL_SMI_EN = 0 SMI# will be caused due to NMI events No SMI# at all because GBL_SMI_EN = 0 No SMI# due to NMI because NMI_EN = 1
TCOBASE +08h 0000h No
Attribute: Size: Power Well:
Description
R/W, R/WC 16-bit Core
8
NMI Now (NMI_NOW)—R/WC. 1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to the NMI handler. 0 = This bit is cleared by writing a 1 to the bit position. The NMI handler is expected to clear this bit. Another NMI will not be generated until the bit is cleared.
7:0
Reserved
9.9.9
TCO2_CNT—TCO2 Control Register
I/O Address: Default Value: Lockable:
Bit 15:3 Reserved. INTRUDER# Signal Select (INTRD_SEL)—R/W. Selects the action to take if the INTRUDER# signal goes active. 00 = No interrupt or SMI# 2:1 01 = Interrupt (as selected by TCO_INT_SEL). 10 = SMI 11 = Reserved 0 Reserved.
TCOBASE +0Ah 0000h No
Attribute: Size: Power Well:
Description
R/W 16-bit Resume
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9.9.10
TCO_MESSAGE1 and TCO_MESSAGE2 Registers
I/O Address: Default Value: Lockable:
Bit 7:0
TCOBASE +0Ch (Message 1) Attribute: TCOBASE +0Dh (Message 2) 00h Size: No Power Well:
Description
R/W 8-bit Resume
TCO Message (TCO_MESSAGE[n])—R/W.The value written into this register will be sent out via the SMLINK interface in the MESSAGE field of the Alert On LAN message. BIOS can write to this register to indicate its boot progress which can be monitored externally.
9.9.11
TCO_WDSTATUS—TCO2 Control Register
Offset Address: Default Value: Power Well:
Bit
TCOBASE + 0Eh 00h Resume
Attribute: Size:
R/W 8 bits
Description Watchdog Status (WDSTATUS)—R/W. The value written to this register will be sent in the Alert On LAN message on the SMLINK interface. It can be used by the BIOS or system management software to indicate more details on the boot progress. This register will be reset to the default of 00h based on RSMRST# (but not PCI reset).
7:0
9.9.12
SW_IRQ_GEN—Software IRQ Generation Register
Offset Address: Default Value: Power Well:
Bit 7:2 1 Reserved. IRQ12 Cause (IRQ12_CAUSE)—R/W. The state of this bit is logically ANDed with the IRQ12 signal as received by the ICH2’s SERIRQ logic. This bit must be a “1” (default) if the ICH2 is expected to receive IRQ12 assertions from a SERIRQ device. IRQ1 Cause (IRQ1_CAUSE)—R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by the ICH2’s SERIRQ logic. This bit must be a “1” (default) if the ICH2 is expected to receive IRQ1 assertions from a SERIRQ device.
TCOBASE + 10h 03h Resume
Attribute: Size:
R/W 8 bits
Description
0
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9.10
General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte I/O space. The base offset for this space is selected by the GPIO_BAR register. Table 9-12 summarizes the ICH2 GPIO implementation.
Table 9-12. Summary of GPIO Implementation
GPIO Type Alternate Function (Note 1) REQ[A]# Power Well Notes GPIO_USE_SEL bit 0 enables REQ/GNT[A]# pair. Input active status read from GPE1_STS register bit 0. Input active high/low set through GPI_INV register bit 0. GPIO_USE_SEL bit 1 enables REQ/GNT[B]# pair (See note 4). Input active status read from GPE1_STS register bit 1. Input active high/low set through GPI_INV register bit 1. Not implemented GPIO_USE_SEL bits [3:4] enable PIRQ[F:G]#. Input active status read from GPE1_STS reg. bits [3:4]. Input active high/low set through GPI_INV reg. bit [3:4]. Not implemented ICH2 (82801BA): GPIO[6] Input Only Unmuxed Core Input active status read from GPE1_STS register bit 6. Input active high/low set through GPI_INV register bit 6. ICH2-M (82801BAM): Not implemented. GPIO[7] GPIO[8] GPIO[9:10] GPIO[11] Input Only Input Only N/A Input Only Input Only Input Only N/A Output Only Output Only Unmuxed Unmuxed N/A SMBALERT# Core Resume N/A Resume Input active status read from GPE1_STS register bit 7. Input active high/low set through GPI_INV register bit 7 Input active status read from GPE1_STS register bit 8. Input active high/low set through GPI_INV register bit 8. Not implemented GPIO_USE_SEL bit 11 enables SMBALERT# Input active status read from GPE1_STS register bit 11. Input active high/low set through GPI_INV register bit 11. Input active status read from GPE1_STS register bit 12. Input active high/low set through GPI_INV register bit 12. Input active status read from GPE1_STS register bit 13. Input active high/low set through GPI_INV register bit 13. Not Implemented Output controlled via GP_LVL register bit 16. TTL driver output Output controlled via GP_LVL register bit 17. TTL driver output ICH2 (82801BA): GPIO[18:19] Output Only Unmuxed Core Output controlled via GP_LVL register bits [18:19]. TTL driver output ICH2-M (82801BAM): Not implemented.
GPIO[0]
Input Only
Core
GPIO[1]
Input Only N/A Input Only N/A
REQ[B]# or REQ[5]# N/A PIRQ[E:H]# N/A
Core
GPIO[2] GPIO[3:4] GPIO[5]
N/A Core N/A
GPIO[12] GPIO[13] GPIO[14:15] GPIO[16] GPIO[17]
Unmuxed Unmuxed N/A GNT[A]# GNT[B]# or GNT[5]#
Resume Resume N/A Core Core
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Table 9-12. Summary of GPIO Implementation (Continued)
GPIO Type Alternate Function (Note 1) Power Well ICH2 (82801BA): GPIO[20] Output Only Unmuxed Core Output controlled via GP_LVL register bit 20. TTL driver output ICH2-M (82801BAM): Not implemented. ICH2 (82801BA): Output Only Unmuxed for ICH2 82801BA CS_STAT# for ICH2-M 82801BAM This GPO defaults high. Output controlled via GP_LVL register bit 21. TTL driver output ICH2-M (82801BAM): Output controlled via GP_LVL register bit 21. TTL driver output ICH2 (82801BA): GPIO[22] Output Only Unmuxed Core Output controlled via GP_LVL register bit [22]. Open-drain output ICH2-M (82801BAM): Not implemented. ICH2 (82801BA): GPIO[23] Output Only Unmuxed Core Output controlled via GP_LVL register bit [23]. TTL driver output ICH2-M (82801BAM): Not implemented. ICH2 (82801BA): GPIO[24] Input / Output Unmuxed Resume Input active status read from GP_LVL register bit 24. Output controlled via GP_LVL register bit 24. TTL driver output ICH2-M (82801BAM): Not implemented. Input / Output N/A Input / Output N/A Blink enabled via GPO_BLINK register bit 25. Input active status read from GP_LVL register bit 25 Output controlled via GP_LVL register bit 25. TTL driver output Not implemented Input active status read from GP_LVL register bits [27:28] Output controlled via GP_LVL register bits [27:28] TTL driver output Not implemented Notes
GPIO[21]
Core
GPIO[25]
Unmuxed
Resume
GPIO[26] GPIO[27:28] GPIO[29:31]
N/A Unmuxed N/A
N/A Resume N/A
NOTES: 1. All GPIOs default to their alternate function 2. All inputs are sticky. The status bit will remain set as long as the input was asserted for 2 clocks. GPIs are sampled on PCI clocks in S0/S1... 3. GPIs are sampled on RTC clocks in S3/S4/S5 for the 82801BA ICH2 and in S1/S3/S4/S5 for the 82801BAM ICH2-M. 4. GPIO[7:6,4:3,1:0] (GPIO[7,4:3,1:0] for the ICH2-M) are 5V tolerant, and all GPIs can be routed to cause an SCI or SMI# 5. If GPIO_USE_SEL bit 1 is set to 1 and GEN_CNT bit 25 is also set to 1 then REQ/GNT[5]# is enabled. See Section 9.1.22.
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9.10.1
GPIO Register I/O Address Map
Table 9-13. Registers to Control GPIO
Offset Mnemonic Register Name General Registers 00–03h 04–07h 08–0Bh 0C–0Fh 10–13h GPIO_USE_SEL GP_IO_SEL — GP_LVL — GPIO Use Select GPIO Input/Output Select Reserved GPIO Level for Input or Output Reserved Output Control Registers 14–17h 18–1Bh 1C–1Fh GPO_TTL GPO_BLINK — GPIO TTL Select GPIO Blink Enable Reserved Input Control Registers 20–2Bh 2C–2Fh — GPI_INV Reserved GPIO Signal Invert 00000000h 00000000h RO R/W 06630000h 00000000h 0 RO R/W RO 1A00 3180h 0000 FFFFh 00h 1F1F 0000h 00h R/W R/W RO R/W RO Default Access
9.10.2
GPIO_USE_SEL—GPIO Use Select Register
Offset Address: Default Value: Lockable:
Bit
GPIOBASE + 00h 1A003180h Yes
Attribute: Size: Power Well:
Description
R/W 32-bit Resume
GPIO Use Select (GPIO_USE_SEL)—R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. 21,11, 5:0 Note: ICH2 82801BA: Bits 31:29, 26, 15:14, 10:9 and 7 are not implemented because there is no corresponding GPIO. ICH2-M 82801BAM: Bits 31:29, 26, 24:22, 20:18, 15:14, 10:9, and 7:6 are not implemented because there is no corresponding GPIO. Note: ICH2 82801BA: Bits 28:27, 25:22, 20:18,13:12, 8 and 6 are not implemented because the corresponding GPIOs are not multiplexed. ICH2-M 82801BAM: Bits 28:27, 25, 13:12 and 8 are not implemented because the corresponding GPIOs are not mutiplexed.
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9.10.3
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address: Default Value: Lockable:
Bit 31:29, 26 15:14, 10:9, 5, 2 28:27,25:24 (ICH2) 28:27,25 (ICH2-M) 24:22, 20:18, 6 (ICH2-M) 23:16 (ICH2) 21:16 (ICH2-M) 13:11, 8:6, 4:3, 1:0 (ICH2) 13:11, 8:7, 4:3, 1:0 (ICH2-M) Reserved. GPIO[n] Select (GPIO[n]_SEL)—R/W. 0 = Output. The corresponding GPIO signal is an output. 1 = Input. The corresponding GPIO signal is an input. Reserved Always 0. The GPIOs are fixed as outputs.
GPIOBASE +04h 0000FFFFh No
Attribute: Size: Power Well:
Description
R/W 32-bit Resume
Always 1. These GPIOs are fixed as inputs.
NOTES: 1. There will be some delay on GPIO[24:28] going to their default state based on the rising edge of
RSMRST#. This is the case since these signals are in the resume well and resume well outputs are not valid until after RSMRST# goes high. ICH2 only guarantees that these GPIOs will be stable prior to SLP_S3# going active.
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9.10.4
GP_LVL—GPIO Level for Input or Output Register
Offset Address: Default Value: Lockable:
Bit 31:29, 26, 15:14, 10:9, 5, 2 (ICH2) 31:29, 26, 24:22, 20:18, 15:14, 10:9 6, 5, 2 (ICH2-M) Reserved.
GPIOBASE +0Ch 1B3F 0000h No
Attribute: Size: Power Well:
Description
R/W, RO 32-bit See bit descriptions
28:27, 25:24 (ICH2) 28:27, 25 (ICH2-M)
GPIO Level (GP_LVL[n])—R/W. If GPIO[n] is programmed to be an output (via the corresponding bit in the GP_IO_SEL register), then the bit can be updated by software to drive a high or low value on the output pin. If GPIO[n] is programmed as an input, then software can read the bit to determine the level on the corresponding input pin. These bits correspond to GPIO that are in the Resume well, and will be reset to their default values by RSMRST# but not by PCIRST#. 0 = Low 1 = High
23:16 (ICH2) 21, 17:16 (ICH2-M)
GPIO Level (GP_LVL[n])—R/W. These bits can be updated by software to drive a high or low value on the output pin. These bits correspond to GPIO that are in the Core well, and will be reset to their default values by PCIRST#. 0 = Low 1 = High ICH2 82801BA: For GPI[13:11] and [8:6,4:3,1:0], the active status of a GPI is read from the corresponding bit in GPE1_STS register. ICH2-M 82801BAM: For GPI[13:11] and [8:7,4:3,1:0], the active status of a GPI is read from the corresponding bit in GPE1_STS register.
13:11, 8:6, 4:3, 1:0 (ICH2) 13:11, 8:7, 4:3, 1:0 (ICH2-M)
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9.10.5
GPO_BLINK—GPO Blink Enable Register
Offset Address: Default Value: Lockable:
Bit 31:29, 26, 24:20, 17:0 (ICH2) 31:29, 26, 24:20, 18:0 (ICH2-M)
GPIOBASE +18h 0004 0000h No
Attribute: Size: Power Well:
Description
R/W 32-bit See bit description
Reserved
28:27, 25
GPIO Blink (GP_BLINK[n])—R/W. The setting of these bits will have no effect if the corresponding GPIO is programmed as an input. These bits correspond to GPIO that are in the Resume well and will be reset to their default values by RSMRST# but not by PCIRST#. 0 = The corresponding GPIO will function normally. 1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate of approximately once per second. The high and low times have approximately 50% duty cycle. The GP_LVL bit is not altered when this bit is set. GPIO Blink (GP_BLINK[n])—R/W. The setting of these bits will have no effect if the corresponding GPIO is programmed as an input. These bits correspond to GPIO that are in the Core well, and will be reset to their default values by PCIRST#. 0 = The corresponding GPIO will function normally. 1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate of approximately once per second. The high and low times have approximately 50% duty cycle. The GP_LVL bit is not altered when this bit is set.
19:18 (ICH2) 19 (ICH2-M)
NOTES:. 1. ICH2 82801BA: GPIO[18]
blinks, by default, immediately after reset. This signal could be connected to an LED to indicate a failed boot (by programming BIOS to clear GP_BLINK[18] after successful POST).
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9.10.6
GPI_INV—GPIO Signal Invert Register
Offset Address: Default Value: Lockable:
Bit 31:14, 10:9, 5, 2 (ICH2) 31:14, 10:9, 6, 5, 2 (ICH2-M)
GPIOBASE +2Ch 00000000h No
Attribute: Size: Power Well:
Description
R/W 32-bit See bit description
Reserved
13:11, 8
GPIO Signal High/Low Select (GP_INV[n])—R/W. These bits are used to allow both activelow and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least 2 PCI clocks to ensure detection by the ICH2. In the S3, S4 or S5 states the input signal must be active for at least 2 RTC clocks to ensure detection. The setting of these bits will have no effect if the corresponding GPIO is programmed as an output. These bits correspond to GPIO that are in the Resume well, and will be reset to their default values by RSMRST# but not by PCIRST#. 0 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input pin to be high. 1 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input pin to be low. GPIO Signal High/Low Select (GP_INV[n])—R/W. These bits are used to allow both activelow and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least 2 PCI clocks to ensure detection by the ICH2. The setting of these bits will have no effect if the corresponding GPIO is programmed as an output. These bits correspond to GPIO that are in the Core well, and will be reset to their default values by PCIRST#. 0 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input pin to be high. 1 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input pin to be low.
7:6, 4:3, 1:0 (ICH2) 7, 4:3, 1:0 (ICH2-M)
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IDE Controller Registers (D31:F1)
IDE Controller Registers (D31:F1)
10.1
Note:
10
PCI Configuration Registers (IDE—D31:F1)
Registers that are not shown should be treated as Reserved (See Section 6.2 for details). All of the IDE registers are in the Core well. None can be locked.
Table 10-1. PCI Configuration Map (IDE—D31:F1)
Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 0Dh 0Eh 20h–23h 2C–2Dh 2E–2Fh 40h–41h 42–43h 44h 48h 4Ah–4Bh 54h Mnemonic VID DID CMD STS RID PI SCC BCC MLT HTYPE BAR SVID SID IDE_TIMP ID_TIMS SIDETIM SDMAC SDMATIM IDE_CONFIG Register Name/Function Vendor ID Device ID Command Register Device Status Revision ID Programming Interface Sub Class Code Base Class Code Master Latency Timer Header Type Base Address Register Subsystem Vendor ID Subsystem ID Primary IDE Timing Secondary IDE Timing Slave IDE Timing Synchronous DMA Control Register Synchronous DMA Timing Register IDE I/O Configuration Register Default 8086h 244Bh (ICH2) 244Ah (ICH2-M) 00h 0280h See Note 1 80h 01h 01h 00 00h 00000001h 00 00 0000h 0000h 00h 00h 0000h 00h Type RO RO R/W R/W RO RO RO RO RO RO R/W R/WriteOnce R/WriteOnce R/W R/W R/W R/W R/W R/W
NOTES: 1. Refer to the Specification Update for the value of the Revision ID Register 2. The ICH2 IDE controller is not arbitrated as a PCI device; therefore, it doe s not need a master latency timer.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-1
IDE Controller Registers (D31:F1)
10.1.1
VID—Vendor ID Register (IDE—D31:F1)
Offset Address: Default Value: Lockable:
Bit 15:0
00–01h 8086h No
Attribute: Size: Power Well:
Description
RO 16-bit Core
Vendor ID Value. This is a 16 bit value assigned to Intel. Intel VID = 8086h
10.1.2
DID—Device ID Register (IDE—D31:F1)
Offset Address: Lockable: Default Value: 02–03h No 244Bh (82801BA ICH2) 244Ah (82801BAM ICH2-M) Attribute: Size: Power Well: RO 16-bit Core
Bit 15:0
Description Device ID Value. This is a 16 bit value assigned to the ICH2 IDE controller.
10.1.3
CMD—Command Register (IDE—D31:F1)
Address Offset: Default Value:
Bit 15:10 9 8 7 6 5 4 3 2 1 Reserved. Fast Back to Back Enable (FBE)—RO. Reserved as 0. SERR# Enable—RO. Reserved as 0. Wait Cycle Control—RO. Reserved as 0. Parity Error Response—RO. Reserved as 0. VGA Palette Snoop—RO. Reserved as 0. Postable Memory Write Enable (PMWE)—RO. Reserved as 0. Special Cycle Enable (SCE)—RO. Reserved as 0. Bus Master Enable (BME)—R/W. Controls the ICH2’s ability to act as a PCI master for IDE Bus Master transfers. Memory Space Enable (MSE)—RO. Reserved as 0. I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers. 0 = Disables access to the Legacy IDE ports (both Primary and Secondary) as well as the Bus Master IO registers. 1 = Enable. Note that the Base Address register for the Bus Master registers should be programmed before this bit is set. Note: Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently disable the Primary or Secondary I/O spaces.
04h–05h 00h
Attribute: Size:
Description
RO, R/W 16 bits
0
10-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
IDE Controller Registers (D31:F1)
10.1.4
STS—Device Status Register (IDE—D31:F1)
Address Offset: Default Value:
Bit 15 14 13 12
06–07h 0280h
Attribute: Size:
Description
R/WC, RO 16 bits
Detected Parity Error (DPE)—RO. Reserved as 0. Signaled System Error (SSE)—RO. Reserved as 0. Received Master-Abort Status (RMA)—R/WC. 1 = Bus Master IDE interface function, as a master, generated a master abort. 0 = Cleared by writing a 1 to it. Reserved as 0—RO. Signaled Target-Abort Status (STA)—R/WC. 1 = ICH2 IDE interface function is targeted with a transaction that the ICH2 terminates with a target abort. 0 = Cleared by writing a 1 to it. DEVSEL# Timing Status (DEVT)—RO.
11
10:9 8 7 6 5 4:0
01 = Hardwired; however, the ICH2 does not have a real DEVSEL# signal associated with the IDE unit, so these bits have no effect. Data Parity Error Detected—RO. Reserved as 0. Fast Back-to-Back Capable—RO. Reserved as 1. User Definable Features (UDF)—RO. Reserved as 0. 66 MHz Capable—RO. Reserved as 0. Reserved
10.1.5
RID—Revision ID Register (HUB-PCI—D30:F0)
Offset Address: Default Value:
Bit 7:0
08h See bit description
Attribute: Size:
Description
RO 8 bits
Revision Identification Number—RO. This 8-bit value indicates the revision number for the ICH2 IDE controller. Refer to the Specification Update for the value of the Revision ID Register.
10.1.6
PI—Programming Interface (IDE—D31:F1)
Address Offset: Default Value:
Bit 7:0 Programming Interface Value—RO. 80h = The 1b in bit 7 indicates that this IDE controller is capable of bus master operation.
09h 80h
Attribute: Size:
Description
RO 8 bits
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-3
IDE Controller Registers (D31:F1)
10.1.7
SCC—Sub Class Code (IDE—D31:F1)
Address Offset: Default Value:
Bit 7:0 Sub Class Code—RO. 01h = IDE device, in the context of a mass storage device.
0Ah 01h
Attribute: Size:
Description
RO 8 bits
10.1.8
BCC—Base Class Code (IDE—D31:F1)
Address Offset: Default Value:
Bit 7:0 Base Class Code—RO. 01 = Mass storage device
0Bh 01h
Attribute: Size:
Description
RO 8 bits
10.1.9
MLT—Master Latency Timer (IDE—D31:F1)
Address Offset: Default Value:
Bit
0Dh 00h
Attribute: Size:
Description
RO 8 bits
7:0
Bus Master Latency—RO. The IDE controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. Hardwired to 00h.
10.1.10
BM_BASE—Bus Master Base Address Register (IDE—D31:F1)
Address Offset: Default Value: 20h–23h 00000001h Attribute: Size: R/W 32 bits
The Bus Master IDE interface function uses Base Address register 5 to request a 16 byte IO space to provide a software interface to the Bus Master functions. Only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address.
Bit 31:16 15:4 3:1 0 Reserved. Base Address—R/W. Base address of the I/O space (16 consecutive I/O locations). Reserved. Resource Type Indicator (RTE)—RO. Hardwired to 1, indicating a request for IO space. Description
10-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
IDE Controller Registers (D31:F1)
10.1.11
IDE_SVID—Subsystem Vendor ID (IDE—D31:F1)
Address Offset: Default Value: Lockable:
Bit
2Ch–2Dh 00h No
Attribute: Size: Power Well:
Description
R/Write-Once 16 bits Core
15:0
Subsystem Vendor ID (SVID)—R/Write-Once. The SVID register, in combination with the Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS) sets the value in this register. After that, the value can be read, but subsequent writes to this register have no effect. The value written to this register will also be readable via the corresponding SVID registers for the USB#1, USB#2 and SMBus functions.
10.1.12
IDE_SID—Subsystem ID (IDE—D31:F1)
Address Offset: Default Value: Lockable:
Bit
2Eh–2Fh 00h No
Attribute: Size: Power Well:
Description
R/Write-Once 16 bits Core
15:0
Subsystem ID (SID)—R/Write-Once. The SID register, in combination with the SVID register, enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS) sets the value in this register. After that, the value can be read, but subsequent writes to this register have no effect. The value written to this register will also be readable via the corresponding SID registers for the USB#1, USB#2 and SMBus functions.
10.1.13
IDE_TIM—IDE Timing Register (IDE—D31:F1)
Address Offset: Default Value: Primary: 40–41h Secondary: 42–43h 0000h Attribute: Size: R/W 16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It also controls operation of the buffer for PIO transfers.
Bit Description IDE Decode Enable (IDE)—R/W. Individually enable/disable the Primary or Secondary decode. The IDE I/O Space Enable bit in the Command register must be set in order for this bit to have any effect. Additionally, separate configuration bits are provided (in the IDE I/O Configuration register) to individually disable the primary or secondary IDE interface signals, even if the IDE Decode Enable bit is set. 0 = Disable. 1 = Enables the ICH2 to decode the associated Command Blocks (1F0h–1F7h for primary, 170h–177h for secondary) and Control Block (3F6h for primary and 376h for secondary). Drive 1 Timing Register Enable (SITRE)—R/W. 14 0 = Use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1 IORDY Sample Point (ISP). The setting of these bits determine the number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point. 00 = 5 clocks 13:12 01 = 4 clocks 10 = 3 clocks 11 = Reserved
15
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-5
IDE Controller Registers (D31:F1)
Bit 11:10 Reserved.
Description
Recovery Time (RCT)—R/W. The setting of these bits determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle. 00 = 4 clocks 9:8 01 = 3 clocks 10 = 2 clocks 11 = 1 clock Drive 1 DMA Timing Enable (DTE1)—R/W. 7 0 = Disable. 1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 1 Prefetch/Posting Enable (PPE1)—R/W. 6 0 = Disable. 1 = Enable Prefetch and posting to the IDE data port for this drive. Drive 1 IORDY Sample Point Enable (IE1)—R/W. 5 0 = Disable IORDY sampling for this drive. 1 = Enable IORDY sampling for this drive. Drive 1 Fast Timing Bank (TIME1)—R/W. 4 0 = Accesses to the data port will use compatible timings for this drive. 1 = When this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time. When this bit = 1 and bit 14 = 1, accesses to the data port will use the IORDY sample point and recover time specified in the slave IDE timing register. Drive 0 DMA Timing Enable (DTE0)—R/W. 3 0 = Disable. 1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 0 Prefetch/Posting Enable (PPE0)—R/W. 2 0 = Disable prefetch and posting to the IDE data port for this drive. 1 = Enable prefetch and posting to the IDE data port for this drive. Drive 0 IORDY Sample Point Enable (IE0)—R/W. 1 0 = Disable IORDY sampling is disabled for this drive. 1 = Enable IORDY sampling for this drive. Drive 0 Fast Timing Bank (TIME0)—R/W. 0 0 = Accesses to the data port will use compatible timings for this drive. 1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time
10-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
IDE Controller Registers (D31:F1)
10.1.14
SLV_IDETIM—Slave (Drive 1) IDE Timing Register (IDE—D31:F1)
Address Offset: Default Value:
Bit
44h 00h
Attribute: Size:
Description
R/W 8 bits
Secondary Drive 1 IORDY Sample Point (SISP1)—R/W. Determines the number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port and bit 14 of the IDE timing register for secondary is set. 7:6 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved Secondary Drive 1 Recovery Time (SRCT1)—R/W. Determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE timing register for secondary is set. 5:4 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks Primary Drive 1 IORDY Sample Point (PISP1)—R/W. Determines the number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 3:2 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved Primary Drive 1 Recovery Time (PRCT1)—R/W. Determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 1:0 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-7
IDE Controller Registers (D31:F1)
10.1.15
SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1)
Address Offset: Default Value:
Bit 7:4 3 Reserved. Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1)—R/W. 0 = Disable (default). 1 = Enable Synchronous DMA mode for secondary channel drive 1 Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0)—R/W. 2 0 = Disable (default). 1 = Enable Synchronous DMA mode for secondary drive 0. Primary Drive 1 Synchronous DMA Mode Enable (PSDE1)—R/W. 1 0 = Disable (default). 1 = Enable Synchronous DMA mode for primary channel drive 1 Primary Drive 0 Synchronous DMA Mode Enable (PSDE0)—R/W. 0 0 = Disable (default). 1 = Enable Synchronous DMA mode for primary channel drive 0
48h 00h
Attribute: Size:
Description
R/W 8 bits
10.1.16
SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1)
Address Offset: Default Value:
Bit 15:14 Reserved. Secondary Drive 1 Cycle Time (SCT1)—R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. SCB1 = 0 (33 MHz clk) 13:12 00 = CT 4 clocks, RP 6 clocks 01 = CT 3 clocks, RP 5 clocks 10 = CT 2 clocks, RP 4 clocks 11 = Reserved 11:10 Reserved. Secondary Drive 0 Cycle Time (SCT0)—R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. SCB1 = 0 (33 MHz clk) 9:8 00 = CT 4 clocks, RP 6 clocks 01 = CT 3 clocks, RP 5 clocks 10 = CT 2 clocks, RP 4 clocks 11 = Reserved 7:6 Reserved. SCB1 = 1 (66 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_SCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clks, RP 16 clks 10 = Reserved 11 = Reserved SCB1 = 1 (66 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_SCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clks, RP 16 clks 10 = Reserved 11 = Reserved
4A–4Bh 0000h
Attribute: Size:
Description
R/W 16 bits
10-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
IDE Controller Registers (D31:F1)
Bit
Description Primary Drive 1 Cycle Time (PCT1)—R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clks, RP 16 clks 10 = Reserved 11 = Reserved
5:4
00 = CT 4 clocks, RP 6 clocks 00 = Reserved 01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved 11 = Reserved
3:2
Reserved. Primary Drive 0 Cycle Time (PCT0)—R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clks, RP 16 clks 10 = Reserved 11 = Reserved
1:0
00 = CT 4 clocks, RP 6 clocks 00 = Reserved 01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved 11 = Reserved
10.1.17
IDE_CONFIG—IDE I/O Configuration Register
Address Offset: Default Value:
Bit 31:20 Reserved. Secondary IDE Signal Mode (SEC_SIG_MODE)—R/W. 00 = Normal (Enabled). 01 = Tri-state (Disabled). 10 = Drive low (Disabled). 11 = Reserved. 19:18 ICH2 (82801BA): These bits are used to control mode of the Secondary IDE signal pins. These bits should always be set to 00b for desktop implementations. ICH2-M (82801BAM): These bits are used to control mode of the Secondary IDE signal pins for mobile swap bay support. Primary IDE Signal Mode (PRIM_SIG_MODE)—R/W. 00 = Normal (Enabled). 01 = Tri-state (Disabled). 10 = Drive low (Disabled). 11 = Reserved. 17:16 ICH2 (82801BA): These bits are used to control mode of the Primary IDE signal pins. These bits should always be set to 00b for desktop implementations. ICH2-M (82801BAM): These bits are used to control mode of the Secondary IDE signal pins for mobile swap bay support. Fast Secondary Drive 1 Base Clock (FAST_SCB1)—R/W. This bit is used in conjuction with the SCT1 bits to enable/disable Ultra ATA/100 timings for the Secondary Slave drive. 0 = Disable Ultra ATA/100 timing for the Secondary Slave drive. 1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this register).
54h 00h
Attribute: Size:
Description
R/W 32 bits
15
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-9
IDE Controller Registers (D31:F1)
Bit
Description Fast Secondary Drive 0 Base Clock (FAST_SCB0)—R/W. This bit is used in conjuction with the SCT0 bits to enable/disable Ultra ATA/100 timings for the Secondary Master drive. 0 = Disable Ultra ATA/100 timing for the Secondary Master drive. 1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this register). Fast Primary Drive 1 Base Clock (FAST_PCB1)—R/W. This bit is used in conjuction with the PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary Slave drive. 0 = Disable Ultra ATA/100 timing for the Primary Slave drive. 1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register). Fast Primary Drive 0 Base Clock (FAST_PCB0)—R/W. This bit is used in conjuction with the PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary Master drive. 0 = Disable Ultra ATA/100 timing for the Primary Master drive. 1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register). Reserved. Write Buffer PingPong Enable (WR_PingPong_EN)—R/W. 0 = Disabled. The buffer will behave similar to PIIX4. 1 = Enables the write buffer to be used in a split (ping/pong) manner. Reserved. Secondary Slave Channel Cable Reporting—R/W. BIOS should program this bit to tell the IDE driver which cable is plugged into the channel. 0 = 40 conductor cable is present. 1 = 80 conductor cable is present. Secondary Master Channel Cable Reporting—R/W. Same description as bit 7 Primary Slave Channel Cable Reporting—R/W. Same description as bit 7 Primary Master Channel Cable Reporting—R/W. Same description as bit 7 Secondary Drive 1 Base Clock (SCB1)—R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Secondary Drive 0 Base Clock (SCBO)—R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Primary Drive 1 Base Clock (PCB1)—R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Primary Drive 0 Base Clock (PCB0)—R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings
14
13
12
11 10 9:8
7
6 5 4 3
2
1
0
10-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
IDE Controller Registers (D31:F1)
10.2
Bus Master IDE I/O Registers (D31:F1)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located in Device 31:Function 1 Configuration space (offset 20h). All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value; writes to reserved bits have no affect (but should not be attempted). The description of the I/O registers is shown in Table 10-2.
Table 10-2. Bus Master IDE I/O Registers
Offset 00h 01h 02h 03h 04h–07h 08h 09h 0Ah 0Bh 0Ch–0Fh BMIDS BMISS BMIDP BMICS BMISP Mnemonic BMICP Register Command Register Primary Reserved Status Register Primary Reserved Descriptor Table Pointer Primary Command Register Secondary Reserved Status Register Secondary Reserved Descriptor Table Pointer Secondary Default 00h 00h 00h 00h xxxxxxxxh 00h 00h 00h 00h xxxxxxxxh Type R/W RO R/WC RO R/W R/W RO R/WC RO R/W
10.2.1
BMIC[P,S]—Bus Master IDE Command Register
Address Offset: Default Value:
Bit 7:4 Reserved. Returns 0s. Read / Write Control (RWC)—R/W. This bit sets the direction of the bus master transfer: This bit must NOT be changed when the bus master function is active. 0 = Memory reads. 1 = Memory writes Reserved. Returns 0s. Start/Stop Bus Master (START)—R/W. 1 = Enables bus master operation of the controller. Bus master operation begins when this bit is detected changing from a zero to a one. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a '0' to this bit. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master IDE Active bit of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. This bit is intended to be reset after the data transfer is completed, as indicated by either the Bus Master IDE Active bit or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both.
Primary: 00h Secondary: 08h 00h
Attribute: Size:
Description
R/W 8 bits
3
2:1
0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-11
IDE Controller Registers (D31:F1)
10.2.2
BMIS[P,S]—Bus Master IDE Status Register
Address Offset: Default Value:
Bit 7 Reserved. Returns 0. Drive 1 DMA Capable—R/W. 6 0 = Not Capable. 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The ICH2 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Drive 0 DMA Capable—R/W. 5 0 = Not Capable. 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this channel is capable of DMA transfers and that the controller has been initialized for optimum performance. The ICH2 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Reserved. Returns 0s. Interrupt—R/WC. Software can use this bit to determine if an IDE device has asserted its interrupt line (IRQ14 for the Primary channel and IRQ15 for Secondary). 1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal I/O APIC. When this bit is read as a one, all data transferred from the drive is visible in system memory. 0 = This bit is cleared by software writing a '1' to the bit position. If this bit is cleared while the interrupt is still active, this bit will remain clear until another assertion edge is detected on the interrupt line. Error—R/WC. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. 0 = This bit is cleared by software writing a '1' to the bit position. Bus Master IDE Active (ACT)—RO. 1 = Set by the ICH2 when the Start bit is written to the Command register. 0 0 = This bit is cleared by the ICH2 when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared by the ICH2 when the Start bit is cleared in the Command register. When this bit is read as a zero, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted.
Primary: 02h Secondary: 0Ah 00h
Attribute: Size:
Description
R/WC 8 bits
4:3
2
1
10.2.3
BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register
Address Offset: Default Value:
Bit 31:2 1:0
Primary: 04h Secondary: 0Ch All bits undefined
Attribute: Size:
Description
R/W 32 bits
Base address of Descriptor table (BADDR)—R/W. Corresponds to A[31:2]. The Descriptor Table must be DWord aligned. The Descriptor Table must not cross a 64 KB boundary in memory. Reserved.
10-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet
USB Controller Registers
USB Controller Registers
11.1
Note:
11
PCI Configuration Registers (D31:F2/F4)
Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
Table 11-1. PCI Configuration Map (USB—D31:F2/F4)
Offset 00–01h 02–03h 04–05h 06–07h 08h 09h 0Ah 0Bh 0Eh 20–23h 2C–2Dh 2E–2Fh 3Ch 3Dh 60h C0–C1h C4h Mnemonic VID DID CMD STA RID PI SCC BCC HTYPE Base SVID SID INTR_LN INTR_PN SB_RELNUM USB_LEGKEY USB_RES Register Name/Function Vendor ID Device ID Command Register Device Status Revision ID Programming Interface Sub Class Code Base Class Code Header Type Base Address Register Subsystem Vendor ID Subsystem ID Interrupt Line Interrupt Pin Serial Bus Release Number USB Legacy Keyboard/ Mouse Control USB Resume Enable Function 2 Default 8086h 2442h 0000h 0280h See Note 00h 03h 0Ch 00h 00000001h 00 00 00h 03h 10h 2000h 00h Function 4 Default 8086h 2444h 0000h 0280h See Note 00h 03h 0Ch 00h 00000001h 00 00 00h 03h 10h 2000h 00h Type RO RO R/W R/W RO RO RO RO RO R/W RO RO R/W RO RO R/W R/W
NOTE: Refer to the Specification Update for the value of the Revision ID Register.
11.1.1
VID—Vendor Identification Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 15:0
00–01h 8086h
Attribute: Size:
Description
RO 16 bits
Vendor ID Value—RO. This is a 16-bit value assigned to Intel.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
11-1
USB Controller Registers
11.1.2
DID—Device Identification Register (USB—D31:F2/F4)
Address Offset: Default Value: 02–03h Function 2: 2442h Function 4: 2444h Attribute: Size: RO 16 bits
Bit 15:0
Description Device ID Value—RO. This is a 16-bit value assigned to the ICH2 USB Host Controllers
11.1.3
CMD—Command Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 15:10 9 8 7 6 5 4 3 2 1 Reserved. Fast Back to Back Enable (FBE)—RO. Reserved as 0. SERR# Enable—RO. Reserved as 0. Wait Cycle Control—RO. Reserved as 0. Parity Error Response—RO. Reserved as 0. VGA Palette Snoop—RO. Reserved as 0. Postable Memory Write Enable (PMWE)—RO. Reserved as 0. Special Cycle Enable (SCE)—RO. Reserved as 0. Bus Master Enable (BME)—R/W. When set, the ICH2 can act as a master on the PCI bus for USB transfers. Memory Space Enable (MSE)—RO. Reserved as 0. I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers. 1 = Enable accesses to the USB I/O registers. The Base Address register for USB should be programmed before this bit is set. 0 = Disable
04–05h 0000h
Attribute: Size:
Description
R/W 16 bits
0
11-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
USB Controller Registers
11.1.4
STA—Device Status Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 15:14 13 12 11 Reserved as ‘00b’. Read Only. Received Master-Abort Status (RMA)—R/WC. 1 = USB, as a master, generated a master-abort. 0 = Software clears this bit by writing a 1 to the bit location. Reserved. Always read as 0. Signaled Target-Abort Status (STA)—R/WC. 1 = USB function is targeted with a transaction that the ICH2 terminates with a target abort. 0 = Software clears this bit by writing a 1 to the bit location. 10:9 8 7 6 5 4:0 DEVSEL# Timing Status (DEVT)—RO. This 2-bit field defines the timing for DEVSEL# assertion. These read only bits indicate the ICH2's DEVSEL# timing when performing a positive decode. ICH2 generates DEVSEL# with medium timing for USB. Data Parity Error Detected: Reserved as 0. Read Only. Fast Back-to-Back Capable: Reserved as 1. Read Only. User Definable Features (UDF): Reserved as 0. Read Only. 66 MHz Capable: Reserved as 0. Read Only. Reserved.
06–07h 0280h
Attribute: Size:
Description
R/WC 16 bits
11.1.5
RID—Revision Identification Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 7:0
08h See bit description
Attribute: Size:
Description
RO 8 bits
Revision Identification. These bits contain device stepping information and are hardwired to the default value. Refer to the Specification Update for the value of the Revision ID Register.
11.1.6
PI—Programming Interface (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 7:0 Programming Interface—RO. 00h = No specific register level programming interface defined.
09h 00h
Attribute: Size:
Description
RO 8 bits
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USB Controller Registers
11.1.7
SCC—Sub Class Code Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 7:0 Sub Class Code—RO. 03h = Universal Serial Bus Host Controller.
0Ah 03h
Attribute: Size:
Description
RO 8 bits
11.1.8
BCC—Base Class Code Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 7:0 Base Class Code—RO. 0Ch = Serial Bus controller.
0Bh 0Ch
Attribute: Size:
Description
RO 8 bits
11.1.9
BASE—Base Address Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 31:16 15:5 4:1 0 Reserved. Base Address—R/W. Bits [15:5] correspond to I/O address signals AD [15:5], respectively. This gives 32 bytes of relocatable I/O space. Reserved. Resource Type Indicator (RTE)—RO. This bit is hardwired to 1 indicating that the base address field in this register maps to I/O space
20–23h 00000001h
Attribute: Size:
Description
R/W 32 bits
11.1.10
SVID—Subsystem Vendor ID (USB—D31:F2/F4)
Address Offset: Default Value: Lockable:
Bit
2Ch–2Dh 00h No
Attribute: Size: Power Well:
Description
RO 16 bits Core
15:0
Subsystem Vendor ID (SVID)—RO. The SVID register, in combination with the Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE_SVID register.
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USB Controller Registers
11.1.11
SID—Subsystem ID (USB—D31:F2/F4)
Address Offset: Default Value: Lockable:
Bit 15:0
2Eh–2Fh 00h No
Attribute: Size: Power Well:
Description
RO 16 bits Core
Subsystem ID (SID)—R/Write-Once. The SID register, in combination with the SVID register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE_SID register.
11.1.12
INTR_LN—Interrupt Line Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 7:0
3Ch 00h
Attribute: Size:
Description
R/W 8 bits
Interrupt Line—R/W. This data is not used by the ICH2. It is to communicate to software the interrupt line that the interrupt pin is connected to.
11.1.13
INTR_PN—Interrupt Pin Register (USB—D31:F2/F4)
Address Offset: Default Value: Default Value: Attribute: Size: Function 2: 03h(82801BA ICH2) 04h (82801B AM ICH2-M) Function 4: 03h (both ICH2 and ICH2-M)
Description Reserved. Interrupt Pin—RO. The value of 03h in Function 2 indicates that the ICH2 will drive PIRQD# as its interrupt line for USB Controller 0 (ports 0 and 1). 2:0 The value of 03h in Function 4 indicates that the ICH2 will drive PIRQC# as its interrupt line for USB Controller 1 (ports 2 and 3). However, in the ICH2 implementation, when the USB Controller 1 interrupt is generated PIRQ[H]# will go active, not PIRQ[C]#.
3Dh
RO 8 bits
Bit 7:3
11.1.14
SB_RELNUM—Serial Bus Release Number Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 7:0 Serial Bus Release Number—RO. 10h = Indicates that the USB controller is compliant with the USB specification release 1.0.
60h 10h
Attribute: Size:
Description
RO 8 bits
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USB Controller Registers
11.1.15
USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit
C0–C1 2000h
Attribute: Size:
Description
R/W, R/WC, RO 16 bits
15
SMI Caused by End of Pass-through (SMIBYENDPS)—R/WC. Indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 0, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 1 = Event Occurred 0 = Software clears this bit by writing a 1 to the bit location. Reserved. PCI Interrupt Enable (USBPIRQEN)—R/W. Used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note that it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 1 = Enable 0 = Disable SMI Caused by USB Interrupt (SMIBYUSB)—RO. Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 4, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 1 = Event Occurred 0 = Software should clear the IRQ via the USB controller. Writing a 1 to this bit will have no effect. SMI Caused by Port 64 Write (TRAPBY64W)—R/WC. Indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 3, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 1 = Event Occurred 0 = Software clears this bit by writing a 1 to the bit location. SMI Caused by Port 64 Read (TRAPBY64R)—R/WC. Indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 1 = Event Occurred 0 = Software clears this bit by writing a 1 to the bit location. SMI Caused by Port 60 Write (TRAPBY60W)—R/WC. Indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 1, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 1 = Event Occurred 0 = Software clears this bit by writing a 1 to the bit location. SMI Caused by Port 60 Read (TRAPBY60R)—R/WC. Indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 0, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 1 = Event Occurred 0 = Software clears this bit by writing a 1 to the bit location. SMI at End of Pass-through Enable (SMIATENDPS)—R/W. May need to cause SMI at the end of a pass-through. Can occur if an SMI is generated in the middle of a pass through, and needs to be serviced later. 1 = Enable 0 = Disable Pass Through State (PSTATE)—RO. 1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence. 0 = If software needs to reset this bit, it should set bit 5 to 0. A20Gate Pass-Through Enable (A20PASSEN)—R/W. 1 = Allows A20GATE sequence Pass-Through function. SMI# will not be generated, even if the various enable bits are set. 0 = Disable
14
13
12
11
10
9
8
7
6
5
11-6
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USB Controller Registers
Bit
Description SMI on USB IRQ Enable (USBSMIEN)—R/W. 1 = USB interrupt will cause an SMI event. 0 = Disable SMI on Port 64 Writes Enable (64WEN)—R/W. 1 = A write to port 64h will cause an SMI event. 0 = Disable SMI on Port 64 Reads Enable (64REN)—R/W. 1 = A read to port 64h will cause an SMI event. 0 = Disable SMI on Port 60 Writes Enable (60WEN)—R/W. 1 = A write to port 60h will cause an SMI event. 0 = Disable SMI on Port 60 Reads Enable (60REN)—R/W. 1 = A read to port 60h will cause an SMI event. 0 = Disable
4
3
2
1
0
11.1.16
USB_RES—USB Resume Enable Register (USB—D31:F2/F4)
Address Offset: Default Value:
Bit 7:2 Reserved. PORT1EN—R/W. Enable the USB controller to respond to wakeup events on this port. For Function 2 this applies to port 1; for Function 4, this applies to port 3. 1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events. 0 = The USB controller will not look at this port for a wakeup event. PORT0EN—R/W. Enable the USB controller to respond to wakeup events on this port. For Function 2 this applies to port 0; for Function 4, this applies to port 2. 1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events. 0 = The USB controller will not look at this port for a wakeup event.
C4h 00h
Attribute: Size:
Description
R/W 8 bits
1
0
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USB Controller Registers
11.2
USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub ports function such that on read back they reflect the current state of the port, and not necessarily the state of the last write to the register. This allows the software to poll the state of the port and wait until it is in the proper state before proceeding. A Host Controller Reset, Global Reset, or Port Reset will immediately terminate a transfer on the affected ports and disable the port. This affects the USBCMD register, bit [4] and the PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.
Table 11-2. USB I/O Registers
Offset 00–01h 02–03h 04–05h 06–07h 08–0Bh 0Ch 0D–0Fh 10–11h 12–13h 14–17h 18h Mnemonic USBCMD USBSTS USBINTR FRNUM FRBASEADD SOFMOD — PORTSC0 PORTSC1 — LOOPDATA Register USB Command Register USB Status Register USB Interrupt Enable USB Frame Number USB Frame List Base Address USB Start of Frame Modify Reserved Port 0 Status/Control Port 1 Status/Control Reserved Loop Back Test Data Default 0000h 0020h 0000h 0000h Undefined 40h 0 0080h 0080h 0 00h Type R/W* R/WC R/W R/W (see Note 1) R/W R/W RO R/WC (see Note 1) R/WC (see Note 1) RO RO
NOTES: 1. These registers are Word writable only. Byte writes to these registers have unpredictable effects.
11.2.1
USBCMD—USB Command Register
I/O Offset: Default Value: Base + (00–01h) 0000h Attribute: Size: R/W 16 bits
The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. The table following the bit description provides additional information on the operation of the Run/Stop and Debug bits.
Bit 15:7 Reserved. Loop Back Test Mode—R/W. 1 = ICH2 is in loop back test mode. When both ports are connected together, a write to one port will be seen on the other port and the data will be stored in I/O offset 18h. 0 = Disable loop back test mode. Max Packet (MAXP)—R/W. This bit selects the maximum packet size that can be used for full speed bandwidth reclamation at the end of a frame. This value is used by the Host Controller to determine whether it should initiate another transaction based on the time remaining in the SOF counter. Use of reclamation packets larger than the programmed size will cause a Babble error if executed during the critical window at frame end. The Babble error results in the offending endpoint being stalled. Software is responsible for ensuring that any packet which could be executed under bandwidth reclamation be within this size limit. 1 = 64 bytes 0 = 32 bytes Description
8
7
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
USB Controller Registers
Bit
Description Configure Flag (CF)—R/W. This bit has no effect on the hardware. It is provided only as a semaphore service for software. 1 = HCD software sets this bit as the last action in its process of configuring the Host Controller. 0 = Indicates that software has not completed host controller configuration. Software Debug (SWDBG)—R/W. The SWDBG bit must only be manipulated when the controller is in the stopped state. This can be determined by checking the HCHalted bit in the USBSTS register. 1 = Debug mode. In SW Debug mode, the Host Controller clears the Run/Stop bit after the completion of each USB transaction. The next transaction is executed when software sets the Run/Stop bit back to 1. 0 = Normal Mode. Force Global Resume (FGR)—R/W. 1 = Host Controller sends the Global Resume signal on the USB, and sets this bit to 1 when a resume event (connect, disconnect, or K-state) is detected while in global suspend mode. 0 = Software resets this bit to 0 after 20 ms has elapsed to stop sending the Global Resume signal. At that time all USB devices should be ready for bus activity. The 1 to 0 transition causes the port to send a low speed EOP signal. This bit will remain a 1 until the EOP has completed. Enter Global Suspend Mode (EGSM)—R/W. 1 = Host Controller enters the Global Suspend mode. No USB transactions occur during this time. The Host Controller is able to receive resume signals from USB and interrupt the system. Software must ensure that the Run/Stop bit (bit 0) is cleared prior to setting this bit. 0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or after writing bit 4 to 0. Global Reset (GRESET)—R/W. 1 = Global Reset. The Host Controller sends the global reset signal on the USB and then resets all its logic, including the internal hub registers. The hub registers are reset to their power on state. Chip Hardware Reset has the same effect as Global Reset (bit 2), except that the Host Controller does not send the Global Reset on USB. 0 = This bit is reset by the software after a minimum of 10 ms has elapsed as specified in Chapter 7 of the USB Specification. Host Controller Reset (HCRESET)—R/W. The effects of HCRESET on Hub registers are slightly different from Chip Hardware Reset and Global USB Reset. The HCRESET affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of each port. HCRESET resets the state machines of the Host Controller including the Connect/Disconnect state machine (one for each port). When the Connect/Disconnect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. This virtual disconnect causes the port to be disabled. This disconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the PORTSC to get set. The disconnect also causes bit 8 of PORTSC to reset. About 64 bit times after HCRESET goes to 0, the connect and low-speed detect will take place, and bits 0 and 8 of the PORTSC will change accordingly. 1 = Reset. When this bit is set, the Host Controller module resets its internal timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. 0 = Reset by the Host Controller when the reset process is complete. Run/Stop (RS)—R/W. When set to 1, the ICH2 proceeds with execution of the schedule. The ICH2 continues execution as long as this bit is set. When this bit is cleared, the ICH2 completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. The Host Controller clears this bit when the following fatal errors occur: consistency check failure, PCI Bus errors. 1 = Run 0 = Stop
6
5
4
3
2
1
0
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USB Controller Registers
Table 11-3. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation
SWDBG (Bit 5) Run/Stop (Bit 0) Description If executing a command, the Host Controller completes the command and then stops. The 1.0 ms frame counter is reset and command list execution resumes from start of frame using the frame list pointer selected by the current value in the FRNUM register. (While Run/Stop=0, the FRNUM register can be reprogrammed). Execution of the command list resumes from Start Of Frame using the frame list pointer selected by the current value in the FRNUM register. The Host Controller remains running until the Run/Stop bit is cleared (by software or hardware). If executing a command, the Host Controller completes the command and then stops and the 1.0 ms frame counter is frozen at its current value. All status are preserved. The Host Controller begins execution of the command list from where it left off when the Run/Stop bit is set. Execution of the command list resumes from where the previous execution stopped. The Run/Stop bit is set to 0 by the Host Controller when a TD is being fetched. This causes the Host Controller to stop again after the execution of the TD (single step). When the Host Controller has completed execution, the HC Halted bit in the Status Register is set.
0
0
0
1
1
0
1
1
When the USB Host Controller is in Software Debug Mode (USBCMD Register bit 5=1), the single stepping software debug operation is as follows: To Enter Software Debug Mode: 1. HCD puts Host Controller in Stop state by setting the Run/Stop bit to 0. 2. HCD puts Host Controller in Debug Mode by setting the SWDBG bit to 1. 3. HCD sets up the correct command list and Start Of Frame value for starting point in the Frame List Single Step Loop. 4. HCD sets Run/Stop bit to 1. 5. Host Controller executes next active TD, sets Run/Stop bit to 0, and stops. 6. HCD reads the USBCMD register to check if the single step execution is completed (HCHalted=1). 7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to end Software Debug mode. 8. HCD ends Software Debug mode by setting SWDBG bit to 0. 9. HCD sets up normal command list and Frame List table. 10. HCD sets Run/Stop bit to 1 to resume normal schedule execution. In Software Debug mode, when the Run/Stop bit is set, the Host Controller starts. When a valid TD is found, the Run/Stop bit is reset. When the TD is finished, the HCHalted bit in the USBSTS register (bit 5) is set. The SW Debug mode skips over inactive TDs and only halts after an active TD has been executed. When the last active TD in a frame has been executed, the Host Controller waits until the next SOF is sent and then fetches the first TD of the next frame before halting. This HCHalted bit can also be used outside of Software Debug mode to indicate when the Host Controller has detected the Run/Stop bit and has completed the current transaction. Outside of the Software Debug mode, setting the Run/Stop bit to 0 always resets the SOF counter so that when the Run/Stop bit is set the Host Controller starts over again from the frame list location pointed to by the Frame List Index (see FRNUM Register description) rather than continuing where it stopped.
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USB Controller Registers
11.2.2
USBSTA—USB Status Register
I/O Offset: Default Value: Base + (02–03h) 0020h Attribute: Size: R/WC 16 bits
This register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1 to it.
Bit 15:6 Reserved. HCHalted—R/WC. 1 = The Host Controller has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (debug mode or an internal error). Default. 0 = Software resets this bit to 0 by writing a 1 to the bit position. Host Controller Process Error—R/WC. 1 = The Host Controller has detected a fatal error. This indicates that the Host Controller suffered a consistency check failure while processing a Transfer Descriptor. An example of a consistency check failure would be finding an illegal PID field while processing the packet header portion of the TD. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further schedule execution. A hardware interrupt is generated to the system. 0 = Software resets this bit to 0 by writing a 1 to the bit position. Host System Error—R/WC. 1 = A serious error occurred during a host system access involving the Host Controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. A hardware interrupt is generated to the system. 0 = Software resets this bit to 0 by writing a 1 to the bit position. Resume Detect (RSM_DET)—R/WC. 1 = The Host Controller received a “RESUME” signal from a USB device. This is only valid if the Host Controller is in a global suspend state (bit 3 of Command register = 1). 0 = Software resets this bit to 0 by writing a 1 to the bit position. USB Error Interrupt—R/WC. 1 = Completion of a USB transaction resulted in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0 are set. 0 = Software resets this bit to 0 by writing a 1 to the bit position. USB Interrupt (USBINT)—R/WC. 1 = The Host Controller sets this bit when the cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set. Also set when a short packet is detected (actual length field in TD is less than maximum length field in TD), and short packet detection is enabled in that TD. 0 = Software resets this bit to 0 by writing a 1 to the bit position. Description
5
4
3
2
1
0
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USB Controller Registers
11.2.3
USBINTR—Interrupt Enable Register
I/O Offset: Default Value: Base + (04–05h) 0000h Attribute: Size: R/W 16 bits
This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Fatal errors (Host Controller Processor Error-bit 4, USBSTS Register) cannot be disabled by the host controller. Interrupt sources that are disabled in this register still appear in the Status Register to allow the software to poll for events.
Bit 15:4 3 Reserved. Short Packet Interrupt Enable—R/W. 1 = Enabled. 0 = Disabled. 2 Interrupt On Complete (IOC) Enable—R/W. 1 = Enabled. 0 = Disabled. 1 Resume Interrupt Enable—R/W. 1 = Enabled. 0 = Disabled. 0 Time-out/CRC Interrupt Enable—R/W. 1 = Enabled. 0 = Disabled. Description
11.2.4
FRNUM—Frame Number Register
I/O Offset: Default Value: Base + (06–07h) 0000h Attribute: Size: R/W (Writes must be Word Writes) 16 bits
Bits [10:0] of this register contain the current frame number which is included in the frame SOF packet. This register reflects the count value of the internal frame number counter. Bits [9:0] are used to select a particular entry in the Frame List during scheduled execution. This register is updated at the end of each frame time. This register must be written as a word. Byte writes are not supported. This register cannot be written unless the Host Controller is in the STOPPED state as indicated by the HCHalted bit (USBSTS register). A write to this register while the Run/Stop bit is set (USBCMD register) is ignored.
Bit 15:11 Reserved. Frame List Current Index/Frame Number—R/W. Provides the frame number in the SOF Frame. The value in this register increments at the end of each time frame (approximately every 1 ms). In addition, bits [9:0] are used for the Frame List current index and correspond to memory address signals [11:2]. Description
10:0
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82801BA ICH2 and 82801BAM ICH2-M Datasheet
USB Controller Registers
11.2.5
FRBASEADD—Frame List Base Address
I/O Offset: Default Value: Base + (08–0Bh) Undefined Attribute: Size: R/W 32 bits
This 32-bit register contains the beginning address of the Frame List in the system memory. HCD loads this register prior to starting the schedule execution by the Host Controller. When written, only the upper 20 bits are used. The lower 12 bits are written as zero (4-KB alignment). The contents of this register are combined with the frame number counter to enable the Host Controller to step through the Frame List in sequence. The two least significant bits are always 00. This requires DWord alignment for all list entries. This configuration supports 1024 Frame List entries.
Bit 31:12 11:0 Description Base Address—R/W. These bits correspond to memory address signals [31:12], respectively. Reserved.
11.2.6
SOFMOD—Start of Frame Modify Register
I/O Offset: Default Value: Base + (0Ch) 40h Attribute: Size: R/W 8 bits
This 1-byte register is used to modify the value used in the generation of SOF timing on the USB. Only the 7 least significant bits are used. When a new value is written into these 7 bits, the SOF timing of the next frame will be adjusted. This feature can be used to adjust out any offset from the clock source that generates the clock that drives the SOF counter. This register can also be used to maintain real time synchronization with the rest of the system so that all devices have the same sense of real time. Using this register, the frame length can be adjusted across the full range required by the USB specification. Its initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. It may be reprogrammed by USB system software at any time. Its value will take effect from the beginning of the next frame. This register is reset upon a Host Controller Reset or Global Reset. Software must maintain a copy of its value for reprogramming if necessary.
Bit 7 Reserved. SOF Timing Value—R/W. Guidelines for the modification of frame time are contained in Chapter 7 of the USB Specification. The SOF cycle time (number of SOF counter clock periods to generate a SOF frame length) is equal to 11936 + value in this field. The default value is decimal 64 which gives a SOF cycle time of 12000. For a 12 MHz SOF counter clock input, this produces a 1 ms Frame period. The following table indicates what SOF Timing Value to program into this field for a certain frame period. Frame Length (# 12 MHz Clocks) (decimal) 6:0 11936 11937 . . 11999 12000 12001 . . 12062 12063 SOF Reg. Value (decimal) 0 1 . . 63 64 65 . . 126 127 Description
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USB Controller Registers
11.2.7
PORTSC[0,1]—Port Status and Control Register
I/O Offset: Default Value: Port 0/2: Base + (10–11h) Port 1/3: Base + (12–13h) 0080h Attribute: Size: R/W (Word writes only) 16 bits
Note:
For Function 2, this applies to ICH2 USB ports 0 and 1. For Function 4, this applies to ICH2 USB ports 2 and 3. After a Power-up reset, Global reset, or Host Controller reset, the initial conditions of a port are: no device connected, Port disabled, and the bus line status is 00 (single-ended zero).
Bit 15:13 Reserved—RO. Suspend—R/W. This bit should not be written to a 1 if global suspend is active (bit 3=1 in the USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows: Bits [12,2] X0 01 11 Hub State Disable Enable Suspend Description
12
When in suspend state, downstream propagation of data is blocked on this port, except for singleended 0 resets (global reset and port reset). The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. 1 = Port in suspend state. 0 = Port not in suspend state. Note: Normally, if a transaction is in progress when this bit is set, the port will be suspended when the current transaction completes. However, in the case of a specific error condition (out transaction with babble), the ICH2 may issue a start-of-frame, and then suspend the port.
11
Overcurrent Indicator—R/WC. Set by hardware 1 = Overcurrent pin has gone from inactive to active on this port. 0 = Software clears this bit by writing a 1 to the bit position. Overcurrent Active—RO. This bit is set and cleared by hardware. 1 = Indicates that the overcurrent pin is active (low). 0 = Indicates that the overcurrent pin is inactive (high). Port Reset—RO. 1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling. 0 = Port is not in Reset. Low Speed Device Attached (LS)—RO. Writes have no effect. 1 = Low speed device is attached to this port. 0 = Full speed device is attached. Reserved—RO. Always read as 1. Resume Detect (RSM_DET)—R/W. Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected for at least 32 microseconds while the port is in the Suspend state. The ICH2 then reflects the K-state back onto the bus as long as the bit remains a 1 and the port is still in the suspend state (bit 12,2 are 11). Writing a 0 (from 1) causes the port to send a low speed EOP. This bit will remain a 1 until the EOP has completed. 1 = Resume detected/driven on port. 0 = No resume (K-state) detected/driven on port. Line Status—RO. These bits reflect the D+ (bit 4) and D- (bit 5) signals lines’ logical levels. These bits are used for fault detect and recovery as well as for USB diagnostics. This field is updated at EOF2 time (See Chapter 11 of the USB Specification).
10
9
8 7
6
5:4
11-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet
USB Controller Registers
Bit
Description Port Enable/Disable Change—R/WC. For the root hub, this bit gets set only when a port is disabled due to disconnect on that port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). 1 = Port enabled/disabled status has changed. 0 = No change. Software clears this bit by writing a 1 to the bit location. Port Enabled/Disabled (PORT_EN)—R/W. Ports can be enabled by host software only. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction currently in progress on the USB. 1 = Enable. 0 = Disable. Connect Status Change—R/WC. Indicates that a change has occurred in the port’s Current Connect Status (see bit 0). The hub device sets this bit for any changes to the port device connect status, even if system software has not cleared a connect status change. If, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting” an already-set bit (i.e., the bit will remain set). However, the hub transfers the change bit only once when the Host Controller requests a data transfer to the Status Change endpoint. System software is responsible for determining state change history in such a case. 1 = Change in Current Connect Status. 0 = No change. Software clears this bit by writing a 1 to the bit location. Current Connect Status—RO. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 1 = Device is present on port. 0 = No device is present.
3
2
1
0
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USB Controller Registers
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SMBus Controller Registers (D31:F3)
SMBus Controller Registers (D31:F3) 12
12.1 PCI Configuration Registers (SMBUS—D31:F3)
Table 12-1. PCI Configuration Registers (SMBUS—D31:F3)
Offset 00–01h 02–03h 04–05h 06–07h 08h 09h 0Ah 0Bh 20–23h 2C–2Dh 2E–2Fh 3Ch 3Dh 40h Mnemonic VID DID CMD STA RID PI SCC BCC SMB_BASE SVID SID INTR_LN INTR_PN HOSTC Vendor ID Device ID Command Register Device Status Revision ID Programming Interface Sub Class Code Base Class Code SMBus Base Address Register Subsystem Vendor ID Subsystem ID Interrupt Line Interrupt Pin Host Configuration Register Name/Function Attribute RO RO RO, R/W RO, R/WC RO RO RO RO R/W RO RO R/W RO R/W
Note:
Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
12.1.1
VID—Vendor Identification Register (SMBUS—D31:F3)
Address: Default Value:
Bit 15:0
00–01h 8086h
Attributes: Size:
Description
RO 16 bits
Vendor ID Value—RO. This is a 16 bit value assigned to Intel
12.1.2
DID—Device Identification Register (SMBUS—D31:F3)
Address: Default Value:
Bit 15:0 Device ID value—RO.
02–03h 2443h
Attributes: Size:
Description
RO 16 bits
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12-1
SMBus Controller Registers (D31:F3)
12.1.3
CMD—Command Register (SMBUS—D31:F3)
Address: Default Value:
Bit 15:10 9 8 7 6 5 4 3 2 1 0 Reserved. Fast Back to Back Enable (FBE)—RO. Reserved as 0. SERR# Enable (SERREN)—RO. Reserved as 0. Wait Cycle Control (WCC)—RO. Reserved as 0. Parity Error Response (PER)—RO. Reserved as 0. VGA Palette Snoop (VPS)—RO. Reserved as 0. Postable Memory Write Enable (PMWE)—RO. Reserved as 0. Special Cycle Enable (SCE)—RO. Reserved as 0. Bus Master Enable (BME)—RO. Reserved as 0. Memory Space Enable (MSE)—RO. Reserved as 0. I/O Space Enable (IOSE)—R/W. 0 = Disable. 1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register.
04–05h 0000h
Attributes: Size:
Description
RO, R/W 16 bits
12.1.4
STA—Device Status Register (SMBUS—D31:F3)
Address: Default Value:
Bit 15 14 13 12 11
06–07h 0280h
Attributes: Size:
Description
RO, R/WC 16 bits
Detected Parity Error (DPE)—RO. Reserved as 0. Signaled System Error (SSE)—RO. Reserved as 0. Received Master Abort (RMA)—RO. Reserved as 0. Received Target Abort (RTA)—RO. Reserved as 0. Signaled Target-Abort Status (STA)—R/WC. 1 = Function is targeted with a transaction that the ICH2 terminates with a target abort. 0 = Software resets STA to 0 by writing a 1 to this bit location. DEVSEL# Timing Status (DEVT)—RO. This 2-bit field defines the timing for DEVSEL# assertion for positive decode. 01 = Medium timing. Data Parity Error Detected—RO. Reserved as 0. Fast Back-to-Back Capable—RO. Reserved as 1. User Definable Features (UDF)—RO. Reserved as 0. 66 MHz Capable—RO. Reserved as 0. Reserved.
10:9 8 7 6 5 4:0
12-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
SMBus Controller Registers (D31:F3)
12.1.5
RID—Revision ID Register (SMBUS—D31:F3)
Offset Address: Default Value:
Bit 7:0
08h See bit description
Attribute: Size:
Description
RO 8 bits
Revision Identification Number. 8-bit value that indicates the revision number for the SMBus Controller. Refer to the Specification Update for the value of the Revision ID Register
12.1.6
PI—Programming Interface (SMBUS—D31:F3)
Address Offset: Default Value:
Bit 7:0 Programming Interface Value—RO. 80h = The 1b in bit 7 indicates that this IDE controller is capable of bus master operation.
09h 80h
Attribute: Size:
Description
RO 8 bits
12.1.7
SCC—Sub Class Code Register (SMBUS—D31:F3)
Address Offset: Default Value:
Bit 7:0 Sub Class Code—RO. 05h = SM Bus serial controller
0Ah 05h
Attributes: Size:
Description
RO 8 bits
12.1.8
BCC—Base Class Code Register (SMBUS—D31:F3)
Address Offset: Default Value:
Bit 7:0 Base Class Code—RO. 0Ch = Serial controller.
0Bh 0Ch
Attributes: Size:
Description
RO 8 bits
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SMBus Controller Registers (D31:F3)
12.1.9
SMB_BASE—SMBus Base Address Register (SMBUS—D31:F3)
Address Offset: Default Value:
Bit 31:16 15:4 3:1 0 Reserved. Base Address—R/W. Provides the 16-bit system I/O base address for the ICH2 SMB logic. Reserved. IO Space Indicator—RO. This read-only bit is always 1, indicating that the SMB logic is I/O mapped.
20–23h 00000001h
Attribute: Size:
Description
R/W 32-bits
12.1.10
SVID—Subsystem Vendor ID (SMBUS—D31:F2/F4)
Address Offset: Default Value: Lockable:
Bit
2Ch–2Dh 00h No
Attribute: Size: Power Well:
Description
RO 16 bits Core
15:0
Subsystem Vendor ID (SVID)—RO. The SVID register, in combination with the Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE_SVID register.
12.1.11
SID—Subsystem ID (SMBUS—D31:F2/F4)
Address Offset: Default Value: Lockable:
Bit 15:0
2Eh–2Fh 00h No
Attribute: Size: Power Well:
Description
RO 16 bits Core
Subsystem ID (SID)—R/Write-Once. The SID register, in combination with the SVID register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE_SID register.
12.1.12
INTR_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset: Default Value:
Bit 7:0
3Ch 00h
Attributes: Size:
Description
R/W 8 bits
Interrupt line—R/W. This data is not used by the ICH2. It is to communicate to software the interrupt line that the interrupt pin is connected to PIRQB#.
12-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
SMBus Controller Registers (D31:F3)
12.1.13
INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset: Default Value:
Bit 7:0 Interrupt PIN—RO. 02h = Indicates that the ICH2 SMBus Controller will drive PIRQB# as its interrupt line.
3Dh 02h
Attributes: Size:
Description
RO 8 bits
12.1.14
HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset: Default Value:
Bit 7:3 Reserved. I2C Enable (I2C_EN)—R/W. 2 0 = SMBus behavior. 1 = The ICH2 is enabled to communicate with I2C devices. This will change the formatting of some commands. SMBus to SMI Enable (SMB_SMI_EN)—R/W. 1 0 = SMBus interrupts will not generate an SMI#. 1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. This bit will only take effect if the INTREN bit is set in I/O space.This bit needs to be set for SMBALERT# to be enabled. SMBus Host Enable (HST_EN)—R/W. 0 0 = Disable the SMBus Host Controller. 1 = Enable. The SMB Host Controller interface is enabled to execute commands. The INTREN bit needs to be enabled for the SMB Host Controller to interrupt or SMI#. Note that the SMB Host Controller will not respond to any new requests until all interrupt requests have been serviced.
40h 00h
Attribute: Size:
Description
R/W 8 bits
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12-5
SMBus Controller Registers (D31:F3)
12.2
SMBus I/O Registers
Table 12-2. SMB I/O Registers
Offset 00h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh–0Dh 0Eh Mnemonic HST_STS HST_CNT HST_CMD XMIT_SLVA HST_D0 HST_D1 BLOCK_DB — RCV_SLVA SLV_DATA — SMLINK_PIN_CTL Register Name/Function Host Status Host Control Host Command Transmit Slave Address Host Data 0 Host Data 1 Block Data Byte Reserved Receive Slave Address Slave Data Reserved SMLINK Pin Control Default 00h 00h 00h 00h 00h 00h 00h 00h 44h 0000h 00h See Register Description See Register Description Access R/W R/W R/W R/W R/W R/W R/W RO R/W R/W RO R/W
0Fh
SMBUS_PIN_CTL
SMbus Pin Control
R/W
12-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
SMBus Controller Registers (D31:F3)
12.2.1
HST_STS—Host Status Register
Register Offset: Default Value: 00h 00h Attribute: Size: R/WC 8-bits
All status bits are set by hardware and cleared by the software writing a one to the particular bit position. Writing a zero to any bit position has no effect.
Bit Description Byte Done Status (BYTE_DONE_STA)—R/WC. 1 = The ICH2 has received a byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write commands). This bit will be set even on the last byte of the transfer. It will not be set when transmission is due to the Alert On LAN* heartbeat. 0 = Cleared by writing a 1 to the bit position. In Use Status (INUSE_STA)—R/WC (special). This bit is used as semaphore among various independent software threads that may need to use the ICH2’s SMBus logic and has no other effect on Hardware. 6 0 = After a full PCI reset, a read to this bit returns a 0. 1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0, and will then own the usage of the host controller. SMBus Alert Status (SMBALERT_STA)—R/WC. 5 0 = Interrupt or SMI# was not generated by SMBALERT#. 1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by software writing a 1 to the bit position or by RSMRST# going low. If the signal is programmed as a GPIO, then this bit will never be set. Interrupt/SMI# was Failed Bus Transaction (FAILED)—R/WC. 1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to the KILL bit being set to terminate the host transaction. 0 = Cleared by writing a 1 to the bit position. 3 Bus Error (BUS_ERR)—R/WC. 1 = The source of the interrupt of SMI# was a transaction collision. 0 = Cleared by writing a 1 to the bit position. Device Error (DEV_ERR)—R/WC. 1 = The source of the interrupt or SMI# was due to one of the following: • Illegal Command Field, 2 • Unclaimed Cycle (host initiated), • Host Device Time-out Error.] 0 = Software resets this bit by writing a 1 to this location. The ICH2 will then deassert the interrupt or SMI#. Interrupt/SMI# was Successful Completion (INTR)—R/WC (special). This bit can only be set by termination of a command. INTR is not dependent on the INTREN bit of the Host Controller Register (offset 02h); it is only dependent on the termination of the command. If the INTREN bit is not set, the INTR bit will be set, although the interrupt will not be generated. Software can poll the INTR bit in this non-interrupt case. 1 = The source of the interrupt or SMI# was the successful completion of its last command. 0 = Software resets this bit by writing 1 to this location. The ICH2 then deasserts the interrupt or SMI#. Host Busy (HOST_BUSY)—RO. 1 = Indicates that the ICH2 is running a command from the host interface. No SMB registers should be accessed while this bit is set, except the Block Data Byte Register. The Block Data Byte register can be accessed when this bit is set only when the SMB_CMD bits in the Host Control register are programmed for Block command or I2C Read command. This is necessary in order to check the BYTE_DONE_STS bit. 0 = Cleared by the ICH2 when the current transaction is completed.
7
4
1
0
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12-7
SMBus Controller Registers (D31:F3)
12.2.2
HST_CNT—Host Control Register
Register Offset: Default Value:
Bit 7 Reserved. START—WO. 1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers should be setup prior to writing a 1 to this bit position. 0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset 00h) can be used to identify when the ICH2 has finished the command. 5 LAST BYTE—WO. This bit is used for Block Read commands. 1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the block. This causes the ICH2 to send a NACK (instead of an ACK) after receiving the last byte. SMBus Command (SMB_CMD)—R/W. The bit encoding below indicates which command the ICH2 is to perform. If enabled, the ICH2 generates an interrupt or SMI# when the command has completed. If the value is for a non-supported or reserved command, the ICH2 sets the device error (DEV_ERR) status bit and generates an interrupt when the START bit is set. The ICH2 performs no command and does not operate until DEV_ERR is cleared. 000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = Byte: This command uses the transmit slave address and command registers. Bit 0 of the slave address register determines if this is a read or write command. 010 = Byte Data: This command uses the transmit slave address, command, and DATA0 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, the DATA0 register will contain the read data. 011 = Word Data: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, after the command completes, the DATA0 and DATA1 registers will contain the read data. 100 = Process Call: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. After the command completes, the DATA0 and DATA1 registers will contain the read data. 101 = Block: This command uses the transmit slave address, command, DATA0 registers, and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block reads, the count is received and stored in the DATA0 register. Bit 0 of the slave address register selects if this is a read or write command. For writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. 110 = I2C Read: This command uses the transmit slave address, command, DATA0, DATA1 registers, and the Block Data Byte register. The read data is stored in the Block Data Byte register. The ICH2 will continue reading data until the NAK is received. 111 = Reserved KILL—R/W. 1 = When set, kills the current host transaction taking place, sets the FAILED status bit, and asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to allow the SMBus Host Controller to function normally. 0 = Normal SMBus Host Controller functionality. 0 INTREN—R/W. 1 = Enable the generation of an interrupt or SMI# upon the completion of the command. 0 = Disable.
02h 00h
Attribute: Size:
Description
R/W 8-bits
6
4:2
1
12-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
SMBus Controller Registers (D31:F3)
12.2.3
HST_CMD—Host Command Register
Register Offset: Default Value:
Bit 7:0
03h 00h
Attribute: Size:
Description
R/W 8 bits
Host Command—R/W. This eight bit field is transmitted by the host controller in the command field of the SMBus protocol during the execution of any command.
12.2.4
XMIT_SLVA—Transmit Slave Address Register
Register Offset: Default Value: 04h 00h Attribute: Size: R/W 8 bits
This register is transmitted by the host controller in the slave address field of the SMBus protocol.
Bit 7:1 0 Description ADDRESS—R/W. 7-bit address of the targeted slave. Read/Write Select—R/W. Direction of the host transfer. 0 = Write 1 = Read
12.2.5
HST_D0—Data 0 Register
Register Offset: Default Value:
Bit
05h 00h
Attribute: Size:
Description
R/W 8 bits
7:0
DATA0/COUNT—R/W. This field contains the eight bit data sent in the DATA0 field of the SMBus protocol. For block write commands, this register reflects the number of bytes to transfer. This register should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host controller does not check or log illegal block counts.
12.2.6
HST_D1—Data 1 Register
Register Offset: Default Value:
Bit 7:0
06h 00h
Attribute: Size:
Description
R/W 8 bits
DATA1—R/W. This eight bit register is transmitted in the DATA1 field of the SMBus protocol during the execution of any command.
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SMBus Controller Registers (D31:F3)
12.2.7
BLOCK_DB—Block Data Byte Register
Register Offset: Default Value:
Bit
07h 00h
Attribute: Size:
Description
R/W 8 bits
7:0
Block Data Byte—R/W. For Block Writes, software writes the first byte to this register as part of the setup for this command. After the ICH2 has sent the Address, Command, and Byte Count fields, it will send the byte in the Block Data Byte register. After the byte has been sent, the ICH2 sets the BYTE_DONE_STS bit in the Host Status register. If there are more bytes to send, the software then writes in the next byte to the Block Data Byte register and software also clears the BYTE_DONE_STS bit. The ICH2 then sends the next byte. During the time from when a byte has been transmitted to when the next byte has been loaded, the ICH2 inserts wait-states on the SMBus/I2C. A similar process will be used for Block Reads. After receiving the byte count (which goes in the DATA 0 register), the first “data byte” goes in the Block Data Byte register and the ICH2 generates an SMI# or interrupt (depending on configuration). The interrupt or SMI# handler then reads the byte and clears the BYTE_DONE_STS bit. This frees room for the next byte. During the time from when a byte is read to when the BYTE_DONE_STS bit is cleared, the ICH2 inserts wait-states on the SMBus/I2C.
12.2.8
RCV_SLVA—Receive Slave Address Register
Register Offset: Default Value: Lockable:
Bit 7 6:0 Reserved SLAVE_ADDR—R/W. This field is the slave address that the ICH2 decodes for read and write cycles. The default is not 0 so the SMBus Slave Interface can respond even before the processor comes up (or if the processor is dead). This register is cleared by RSMRST#, but not by PCIRST#.
09h 44h No
Attribute: Size: Power Well:
Description
R/W 8 bits Resume
12.2.9
SLV_DATA—Receive Slave Data Register
Register Offset: Default Value: Lockable: 0Ah 00h No Attribute: Size: Power Well: RO 16 bits Resume
This register contains the 16-bit data value written by the external SMBus master. The CPU can then read the value from this register. This register is reset by RSMRST#, but not PCIRST#.
Bit 15:8 7:0 Description DATA_MSG1: Data Message Byte 1—RO. See Section 5.17.5 for a discussion of this field. DATA_MSG0: Data Message Byte 0—RO. See Section 5.17.5 for a discussion of this field.
12-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
SMBus Controller Registers (D31:F3)
12.2.10
SMLINK_PIN_CTL—SMLINK Pin Control Register
Register Offset: Default Value: 0Eh See Below Attribute: Size: Read/Write 8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit 7:3 Reserved SMLINK Clock Pin Control (SMLINK_CLK_CTL)—R/W. 2 1 = No functional impact on the SMLINK[0] pin. (default) 0 = ICH2 will drive the SMLINK[0] pin low, independent of the what the other SMLINK logic would otherwise indicate for the SMLINK[0] pin. SMLINK[1] Pin Current Status (SMLINK[1]_CUR_STA)—RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMLINK[1] pin. This allows software to read the current state of the pin. 1 = SMLINK[1] pin is high 0 = SMLINK[1] pin is low SMLINK[0] Pin Current Status (SMLINK[0]_CUR_STA)—RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMLINK[0] pin. This allows software to read the current state of the pin. 1 = SMLINK[0] pin is high 0 = SMLINK[0] pin is low Description
1
0
12.2.11
SMBUS_PIN_CTL—SMBus Pin Control Register
Register Offset: Default Value: 0Fh See Below Attribute: Size: Read/Write 8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit 7:3 Reserved SMBCLK Pin Control (SMBCLK_CTL)—R/W. 2 1 = No functional impact on the SMBCLK pin. (default) 0 = ICH2 drives the SMBCLK pin low, independent of the what the other SMB logic would otherwise indicate for the SMBCLK pin. SMBDATA Pin Current Status (SMBDATA_CUR_STA)—RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMBDATA pin. This allows software to read the current state of the pin. 1 = SMBDATA pin is high 0 = SMBDATA pin is low SMBCLK Pin Current Status (SMBCLK_CUR_STA)—RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMBCLK pin. This allows software to read the current state of the pin. 1 = SMBCLK pin is high 0 = SMBCLK pin is low Description
1
0
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SMBus Controller Registers (D31:F3)
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AC’97 Audio Controller Registers (D31:F5)
AC’97 Audio Controller Registers (D31:F5)
13.1
Note:
13
AC’97 Audio PCI Configuration Space (D31:F5)
Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
Table 13-1. PCI Configuration Map (Audio—D31:F5)
Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 0Eh 10h–13h 14h–17h 18h–2Bh 2Ch–2Dh 2Eh–2Fh 30h–3Bh 3Ch 3Dh 3Eh–FFh Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC HEDT NAMBAR NABMBAR — SVID SID — INTR_LN INTR_PN — Register Vendor Identification Device Identification PCI Command PCI Device Status Revision Identification Programming Interface Sub Class Code Base Class Code Header Type Native Audio Mixer Base Address Native Audio Bus Mastering Base Address Reserved Subsystem Vendor ID Subsystem ID Reserved Interrupt Line Interrupt Pin Reserved Default 8086h 2445h 0000 0280h See Note 00 01h 04h 00 00000001h 00000001h 00h 0000h 0000h — 00h 02h — Access RO RO R/W R/WC RO RO RO RO RO R/W R/W RO Write-Once Write-Once — R/W RO —
NOTE: Refer to the Specification Update for the value of the Revision ID Register
13.1.1
VID—Vendor Identification Register (Audio—D31:F5)
Offset: Default Value: Lockable:
Bit 15:0
01h-00h 8086h No
Attribute: Size: Power Well:
Description
RO 16 Bits Core
Vendor ID Value. This is a 16 bit value assigned to Intel
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-1
AC’97 Audio Controller Registers (D31:F5)
13.1.2
DID—Device Identification Register (Audio—D31:F5)
Offset: Default Value: Lockable:
Bit 15:0 Device ID Value.
03h–02h 2445h No
Attribute: Size: Power Well:
Description
RO 16 Bits Core
13.1.3
PCICMD—PCI Command Register (Audio—D31:F5)
Address Offset: Default Value: Lockable: 05h–04h 0000h No Attribute: Size: Power Well: R/W 16 bits Core
PCICMD is a 16-bit control register. Refer to the PCI 2.1 specification for complete details on each bit.
Bit 15:10 9 8 7 6 5 4 3 2 1 Reserved. Read as 0s. Fast Back to Back Enable (FBE). Not implemented. Hardwired to 0. SERR# Enable (SEN). Not implemented. Hardwired to 0. Wait Cycle Control (WCC). Not implemented. Hardwired to 0. Parity Error Response (PER). Not implemented. Hardwired to 0. VGA Palette Snoop (VPS). Not implemented. Hardwired to 0. Memory Write and Invalidate Enable (MWI). Not implemented. Hardwired to 0. Special Cycle Enable (SCE). Not implemented. Hardwired to 0. Bus Master Enable (BME)—R/W. Controls standard PCI bus mastering capabilities. 0 = Disable. 1 = Enable Memory Space (MS). Hardwired to 0, AC '97 does not respond to memory accesses IOS (I/O Space)—R/W. This bit controls access to the AC’97 Audio Controller I/O space registers. 0 0 = Disable (Default). 1 = Enable access to I/O space. The Native PCI Mode Base Address register should be programmed prior to setting this bit. Description
13-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Audio Controller Registers (D31:F5)
13.1.4
PCISTS—PCI Device Status Register (Audio—D31:F5)
Offset: Default Value Lockable: 07h–06h 0280h No Attribute: Size: Power Well: R/WC 16 bits Core
PCISTA is a 16-bit status register. Refer to the PCI 2.1 specification for complete details on each bit.
Bit 15 14 13 12 11 10:9 8 7 6 5 4:0 Description Detected Parity Error (DPE). Not implemented. Hardwired to 0. SERR# Status (SERRS). Not implemented. Hardwired to 0. Master-Abort Status (MAS)—R/WC. 1 = Bus Master AC '97 2.1 interface function, as a master, generates a master abort. 0 = Software clears this bit by writing a 1 to the bit position. Reserved. Will always read as 0. Signaled Target-Abort Status (STA). Not implemented. Hardwired to 0. DEVSEL# Timing Status (DEVT)—RO. This 2-bit field reflects the ICH2's DEVSEL# timing when performing a positive decode. 01b = Medium timing. Data Parity Detected (DPD). Not implemented. Hardwired to 0. Fast Back to back Capable (FBC). Hardwired to 1. This bit indicates that the ICH2 as a target is capable of fast back-to-back transactions. UDF Supported. Not implemented. Hardwired to 0. 66 MHz Capable. Hardwired to 0. Reserved. Read as 0's.
13.1.5
RID—Revision Identification Register (Audio—D31:F5)
Offset: Default Value: Lockable:
Bit 7:0
08h See bit description No
Attribute: Size: Power Well:
Description
RO 8 Bits Core
Revision ID Value—RO. Refer to the ICH2 / ICH2-M Specification Update for the value of the Revision ID Register
13.1.6
PI—Programming Interface Register (Audio—D31:F5)
Offset: Default Value: Lockable:
Bit 7:0 Programming Interface—RO.
09h 00h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-3
AC’97 Audio Controller Registers (D31:F5)
13.1.7
SCC—Sub Class Code Register (Audio—D31:F5)
Address Offset: Default Value: Lockable:
Bit 7:0 Sub Class Code—RO. 01h = Audio Device
0Ah 01h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
13.1.8
BCC—Base Class Code Register (Audio—D31:F5)
Address Offset: Default Value: Lockable:
Bit 7:0 Base Class Code—RO. 04h = Multimedia device
0Bh 04h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
13.1.9
HEDT—Header Type Register (Audio—D31:F5)
Address Offset: Default Value: Lockable:
Bit 7:0 Header Type Value. Hardwired to 00h.
0Eh 00h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
13-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Audio Controller Registers (D31:F5)
13.1.10
NAMBAR—Native Audio Mixer Base Address Register (Audio—D31:F5)
Address Offset: Default Value: Lockable: 10h–13h 00000001h No Attribute: Size: Power Well: R/W 32 bits Core
The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the Native Audio Mixer software interface. The mixer requires 256 bytes of I/O space. Native Audio Mixer and Modem codec I/O registers are located from 00h to 7Fh and reside in the codec. Access to these registers will be decoded by the AC '97 controller and forwarded over the AC-link to the codec. The codec will then respond with the register value. In the case of the split codec implementation, accesses to the different codecs are differentiated by the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh for the secondary codec. For a description of these I/O registers, refer to the AC‘97 specification.
Bit 31:16 Hardwired to 0s Base Address—R/W. These bits are used in the I/O space decode of the Native Audio Mixer interface registers. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For the AC ‘97 mixer, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. This configuration yields a maximum I/O block size of 256 bytes for this base address. Note: This address must align to a 256-byte boundary. 7:1 0 Reserved. Read as 0s. Resource Type Indicator (RTE)—RO. Hardwired to 1 indicating a request for I/O space. Description
15:8
13.1.11
NABMBAR—Native Audio Bus Mastering Base Address Register (Audio—D31:F5)
Address Offset: Default Value: Lockable: 14h–17h 00000001h No Attribute: Size: Power Well: R/W 32 bits Core
The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the Native Mode Audio software interface.
Bit 31:16 Hardwired to 0s Base Address—R/W. These bits are used in the I/O space decode of the Native Audio Bus Mastering interface registers. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For AC '97 bus mastering, the upper 16 bits are hardwired to 0, while bits 15:6 are programmable. This configuration yields a maximum I/O block size of 64 bytes for this base address. Note: This address must align to a 64-byte boundary. 5:1 0 Reserved. Read as 0s. Resource Type Indicator (RTE)—RO. This bit is set to 1 indicating a request for I/O space. Description
15:6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-5
AC’97 Audio Controller Registers (D31:F5)
13.1.12
SVID—Subsystem Vendor ID Register (Audio—D31:F5)
Address Offset: Default Value: Lockable: 2Dh–2Ch 0000h No Attribute: Size: Power Well: Read/Write-Once 16 bits Core
The SVID register, in combination with the Subsystem ID register, enable the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect.
Bit 15:0 Description Subsystem Vendor ID Value—R/Write-Once.
13.1.13
SID—Subsystem ID Register (Audio—D31:F5)
Address Offset: Default Value: Lockable: 2Fh–2Eh 0000h No Attribute: Size: Power Well: Read/Write-Once 16 bits Core
The SID register, in combination with the Subsystem Vendor ID register make it possible for the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect.
Bit 15:0 Subsystem ID Value—R/Write-Once. Description
13.1.14
INTR_LN—Interrupt Line Register (Audio—D31:F5)
Address Offset: Default Value: Lockable: 3Ch 00h No Attribute: Size: Power Well: R/W 8 bits Core
This register indicates which PCI interrupt line is used for the AC’97 module interrupt.
Bit 7:0 Description Interrupt Line—R/W. This data is not used by the ICH2. It is used to communicate to software the interrupt line that the interrupt pin is connected to.
13-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Audio Controller Registers (D31:F5)
13.1.15
INTR_PN—Interrupt Pin Register (Audio—D31:F5)
Address Offset: Default Value: Lockable: 3Dh 02h No Attribute: Size: Power Well: RO 8 bits Core
This register indicates which PCI interrupt pin is used for the AC '97 module interrupt. The AC '97 interrupt is internally OR’ed to the interrupt controller with the PIRQB# signal.
Bit 7:3 2:0 Reserved. AC '97 Interrupt Routing—RO. Hardwired to 010b to select PIRQB#. Description
13.2
AC’97 Audio I/O Space (D31:F5)
The AC’97 I/O space includes Native Audio Bus Master Registers and Native Mixer Registers. Table 13-2 shows the register addresses for the audio mixer registers.
Table 13-2. ICH2 Audio Mixer Register Configuration
Primary offset 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah Secondary Offset 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh A0h A2h A4h A6h A8h AAh NAMBAR Exposed Registers (D31:F5) Reset Master Volume Mute Headphone Volume Mute Master Volume Mono Mute Master Tone (R & L) PC_BEEP Volume Mute Phone Volume Mute Mic Volume Mute Line In Volume Mute CD Volume Mute Video Volume Mute Aux Volume Mute PCM Out Volume Mute Record Select Record Gain Mute Record Gain Mic Mute General Purpose 3D Control AC’97 RESERVED Powerdown Ctrl/Stat Extended Audio Extended Audio Ctrl/Stat
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-7
AC’97 Audio Controller Registers (D31:F5)
Table 13-2. ICH2 Audio Mixer Register Configuration (Continued)
Primary offset 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah:56h 58h1 7Ah1 7Ch1 7Eh1 Secondary Offset ACh AEh B0h B2h B4h B6h B8h BAh–F6h NAMBAR Exposed Registers (D31:F5) PCM Front DAC Rate PCM Surround DAC Rate PCM LFE DAC Rate PCM LR ADC Rate MIC ADC Rate 6Ch Vol: C, LFE Mute 6Ch Vol: L, R Surround Mute Intel RESERVED Vendor Reserved Vendor Reserved Vendor ID1 Vendor ID2
NOTE: 1. Registers in bold are multiplexed between audio and modem functions 2. Software should not try to access reserved registers
The Bus Master registers are located from offset + 00h to offset + 51h and reside in the AC ‘97 controller. Accesses to these registers do NOT cause the cycle to be forwarded over the AC-link to the codec. In the case of the split codec implementation accesses to the different codecs are differentiated by the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh for the secondary codec. The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the same global registers in the audio and modem I/O space. Therefore a read/write to these registers in either audio or modem I/O space affects the same physical register. Bus Mastering registers exist in I/O space and reside in the AC ‘97 controller. The three channels (PCM in, PCM out, and Mic in) each have their own set of Bus Mastering registers. The following register descriptions apply to all three channels. The register definition section titles use a generic “x_” in front of the register to indicate that the register applies to all three channels. The naming prefix convention used in Table 13-3 and in the register description I/O address is as follows:
• PI = PCM in channel • PO = PCM out channel • MC = Mic in channel.
13-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Audio Controller Registers (D31:F5)
Table 13-3. Native Audio Bus Master Control Registers
Offset 00h 04h 05h 06h 08h 0Ah 0Bh 10h 14h 15h 16h 18h 1Ah 1Bh 20h 24h 25h 26h 28h 2Ah 2Bh 2Ch 30h 34h Mnemonic PI_BDBAR PI_CIV PI_LVI PI_SR PI_PICB PI_PIV PI_CR PO_BDBAR PO_CIV PO_LVI PO_SR PO_PICB PO_PIV PO_CR MC_BDBAR PM_CIV MC_LVI MC_SR MC_PICB MC_PIV MC_CR GLOB_CNT GLOB_STA ACC_SEMA Name PCM In Buffer Descriptor list Base Address Register PCM In Current Index Value PCM In Last Valid Index PCM In Status Register PCM In Position In Current Buffer PCM In Prefetched Index Value PCM In Control Register PCM Out Buffer Descriptor list Base Address Register PCM Out Current Index Value PCM Out Last Valid Index PCM Out Status Register PCM Out Position In Current Buffer PCM Out Prefetched Index Value PCM Out Control Register Mic. In Buffer Descriptor list Base Address Register Mic. In Current Index Value Mic. In Last Valid Index Mic. In Status Register Mic In Position In Current Buffer Mic. In Prefetched Index Value Mic. In Control Register Global Control Global Status Codec Write Semaphore Register Default 00000000h 00h 00h 0001h 0000h 00h 00h 00000000h 00h 00h 0001h 0000h 00h 00h 00000000h 00h 00h 0001h 0000h 00h 00h 00000000h 00000000h 00h Access R/W RO R/W R/W RO RO R/W R/W RO R/W R/W RO RO R/W R/W RO R/W R/W RO RO R/W R/W RO R/W
13.2.1
x_BDBAR—Buffer Descriptor Base Address Register
I/O Address: Default Value: Lockable: NABMBAR + 00h (PIBDBAR), Attribute: NABMBAR + 10h (POBDBAR), NABMBAR + 20h (MCBDBAR) 00000000h Size: No Power Well: R/W (DWord access only) 32 bits Core
This register can be accessed only as a DWord (32 bits). Bit 31:3 2:0 Description Buffer Descriptor Base Address[31:3]—R/W. These bits represent address bits 31:3. The data should be aligned on 8 byte boundaries. Each buffer descriptor is 8 bytes long and the list can contain a maximum of 32 entries. Hardwired to 0.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-9
AC’97 Audio Controller Registers (D31:F5)
13.2.2
x_CIV—Current Index Value Register
I/O Address: Default Value: Lockable: NABMBAR + 04h (PICIV), NABMBAR + 14h (POCIV), NABMBAR + 24h (MCCIV) 00h No Attribute: Size: Power Well: RO 8 bits Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single 32 bit read from address offset 04h. Software can also read this register individually by doing a single 8 bit read to offset 04h.
Bit 7:5 4:0 Hardwired to 0 Current Index Value[4:0]—RO. These bits represent which buffer descriptor within the list of 32 descriptors is currently being processed. As each descriptor is processed, this value is incremented. The value rolls over after it reaches 31. Description
13.2.3
x_LVI—Last Valid Index Register
I/O Address: Default Value: Lockable: NABMBAR + 05h (PILVI), NABMBAR + 15h (POLVI), NABMBAR + 25h (MCLVI) 00h No Attribute: Size: Power Well: R/W 8 bits Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single 32 bit read from address offset 04h. Software can also read this register individually by doing a single 8 bit read to offset 05h.
Bit 7:5 4:0 Hardwired to 0. Last Valid Index[4:0]—R/W. This value represents the last valid descriptor in the list. This value is updated by the software each time it prepares a new buffer and adds it to the list. Description
13-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Audio Controller Registers (D31:F5)
13.2.4
x_SR—Status Register
I/O Address: Default Value: Lockable: NABMBAR + 06h (PISR), NABMBAR + 16h (POSR), NABMBAR + 26h (MCSR) 0001h No Attribute: Size: Power Well: R/WC, RO (Word Access only) 16 bits Core
This register can be accessed only as a Word (16 bits).
Bit 15:5 Reserved. FIFO error (FIFOE)—R/WC. 1 = FIFO error occurs.
Description
0 = Cleared by writing a 1 to this bit position. 4 PISR Register: FIFO error indicates a FIFO overrun. The FIFO pointers do not increment, the incoming data is not written into the FIFO, thus is lost. POSR Register: FIFO error indicates a FIFO underrun. The sample transmitted in this case should be the last valid sample. The ICH2 will set the FIFOE bit if the under-run or overrun occurs when there are more valid buffers to process. Buffer Completion Interrupt Status (BCIS)—R/WC. 1 = Set by the hardware after the last sample of a buffer has been processed, AND if the Interrupt on Completion (IOC) bit is set in the command byte of the buffer descriptor. It remains active until cleared by software. 0 = Cleared by writing a 1 to this bit position. Last Valid Buffer Completion Interrupt (LVBCI)—R/WC. 1 = Last valid buffer has been processed. It remains active until cleared by software. This bit indicates the occurrence of the event signified by the last valid buffer being processed. Thus, this is an event status bit that can be cleared by software once this event has been recognized. This event will cause an interrupt if the enable bit in the Control Register is set. The interrupt is cleared when the software clears this bit. In the case of Transmits (PCM out, Modem out) this bit is set, after the last valid buffer has been fetched (not after transmitting it). While in the case of Receives, this bit is set after the data for the last buffer has been written to memory. 0 = Cleared by writing a 1 to this bit position. Current Equals Last Valid (CELV)—RO. 1 = Current Index is equal to the value in the Last Valid Index Register, and the buffer pointed to by the CIV has been processed (i.e., after the last valid buffer has been processed). This bit is very similar to bit 2, except this bit reflects the state rather than the event. This bit reflects the state of the controller, and remains set until the controller exits this state. 0 = Cleared by hardware when controller exists state (i.e., until a new value is written to the LVI register.) 0 DMA Controller Halted (DCH)—RO. 1 = Halted. This could happen because of the Start/Stop bit being cleared, or it could happen once the controller has processed the last valid buffer (in which case it will set bit 1 and halt).
3
2
1
Software can read the above 3 registers simultaneously by scheduling a single 32 bit read from address offset 04h. Software can also read this individual register by performing a 16 bit read from 06h.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-11
AC’97 Audio Controller Registers (D31:F5)
13.2.5
x_PICB—Position In Current Buffer Register
I/O Address: Default Value: Lockable: NABMBAR + 08h (PIPICB), NABMBAR + 18h (POPICB), NABMBAR + 28h (MCPICB) 0000h No Attribute: Size: Power Well: RO (Word access only) 16 bits Core
This register can be accessed only as a Word (16 bits).
Bit
Description Position In Current Buffer[15:0]—RO. These bits represent the number of DWords remaining to be processed in the current buffer; the number of samples not yet read from memory (in the case of reads from memory) or not yet written to memory (in the case of writes to memory), irrespective of the number of samples that have been transmitted/received across AC-link.
15:0
13.2.6
x_PIV—Prefetched Index Value Register
I/O Address: Default Value: Lockable:
Bit 7:5 4:0 Hardwired to 0. Prefetched Index Value[4:0]—RO. These bits represent which buffer descriptor in the list has been prefetched. The bits in this register are also modulo 32 and roll over after they reach 31.
NABMBAR + 0Ah (PIPIV), NABMBAR + 1Ah (POPIV), NABMBAR + 2Ah (MCPIV) 00h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
13-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Audio Controller Registers (D31:F5)
13.2.7
x_CR—Control Register
I/O Address: Default Value: Lockable:
Bit 7:5 Reserved. Interrupt On Completion Enable (IOCE)—R/W. This bit controls whether or not an interrupt occurs when a buffer completes with the IOC bit set in its descriptor. 0 = Disable. Interrupt will not occur. 1 = Enable. FIFO Error Interrupt Enable (FEIE)—R/W. This bit controls whether the occurrence of a FIFO error will cause an interrupt or not. 0 = Disable. Bit 4 in the Status Register will be set; however, the interrupt will not occur. 1 = Enable. Interrupt will occur. Last Valid Buffer Interrupt Enable (LVBIE)—R/W. This bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = Disable. Bit 2 in the Status register will still be set; however, the interrupt will not occur. 1 = Enable. Reset Registers (RR)—R/W (special). 1 = Contents of all Bus master related registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). Software needs to set this bit but need not clear it since the bit is self clearing. This bit must be set only when the Run/Pause bit is cleared. Setting it when the Run bit is set will cause undefined consequences. 0 = Removes reset condition. Run/Pause Bus master (RPBM)—R/W. 0 0 = Pause bus master operation. This results in all state information being retained (i.e., master mode operation can be stopped and then resumed). 1 = Run. Bus master operation starts.
NABMBAR + 0Bh (PICR), NABMBAR + 1Bh (POCR), NABMBAR + 2Bh (MCCR) 00h No
Attribute: Size: Power Well:
Description
R/W 8 bits Core
4
3
2
1
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-13
AC’97 Audio Controller Registers (D31:F5)
13.2.8
GLOB_CNT—Global Control Register
I/O Address: Default Value: Lockable: NABMBAR + 2Ch 00000000h No Attribute: Size: Power Well: R/W (DWord access only) 32 bits Core
This register can be accessed only as a DWord (32 bits).
Bit 31:22 Reserved.
Description
PCM 4/6 Enable—R/W. Configures PCM Output for 2, 4 or 6 channel mode. 21:20 00 = 2-channel mode (default) 01 = 4-channel mode 10 = 6-channel mode 11 = Reserved Reserved. Secondary Resume Interrupt Enable—R/W. 5 0 = Disable. 1 = Enable an interrupt to occur when the secondary codec causes a resume event on the AC-link. Primary Resume Interrupt Enable—R/W. 4 0 = Disable. 1 = Enable an interrupt to occur when the primary codec causes a resume event on the AC-link. ACLINK Shut Off—R/W. 3 0 = Normal operation. 1 = Drive all AC’97 outputs low and turn off all AC’97 input buffer enables AC’97 Warm Reset—R/W (special). 0 = Normal operation. 1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken a suspended codec without clearing its internal registers. If software attempts to perform a warm reset while bit_clk is running, the write will be ignored and the bit will not change. This bit is self-clearing (it remains set until the reset completes and bit_clk is seen on the ACLink, after which it clears itself). AC ‘97 Cold Reset#—R/W. 0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry. All data in the controller and the codec will be lost. Software needs to clear this bit no sooner than the minimum number of ms have elapsed. 1 = This bit defaults to 0; thus, after reset, the driver needs to set this bit to a 1. The value of this bit is retained after suspends; thus, if this bit is set to a 1 prior to suspending, a cold reset is not generated automatically upon resuming. Note: This bit is in the Resume well, not in the Core well. GPI Interrupt Enable (GIE)—R/W. This bit controls whether the change in status of any GPI causes an interrupt. 0 = Bit 0 of the Global Status Register is set, but no interrupt is generated. 1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register.
19:6
2
1
0
13-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Audio Controller Registers (D31:F5)
13.2.9
GLOB_STA—Global Status Register
I/O Address: Default Value: Lockable: NABMBAR + 30h 00300000h No Attribute: RO, R/W, R/WC (DWord access only) Size: 32 bits Power Well: Core
This register can be accessed only as a DWord (32 bits).
Bit 31:22 21 Reserved.
Description
6 Channel Capability (6CH_CAP)—RO. Hardwired to 1. 0 = The AC ‘97 Controller does not support 6-channel PCM Audio output. 1 = The AC ‘97 Controller supports 6-channel PCM Audio output. 4 Channel Capability (4CH_CAP)—RO. Hardwired to 1. 20 19:18 17 0 = The AC ‘97 Controller does not support 4-channel PCM Audio output. 1 = The AC ‘97 Controller supports 4-channel PCM Audio output. Reserved. MD3—R/W. Power down semaphore for Modem. This bit exists in the suspend well and maintains context across power states (except G3). The bit has no hardware function. It is used by software in conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state. AD3—R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains context across power states (except G3). The bit has no hardware function. It is used by software in conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state. Read Completion Status (RCS)—R/WC. This bit indicates the status of codec read completions. 15 0 = A codec read completes normally. 1 = A codec read results in a time-out. The bit remains set until being cleared by software writing a 1 to the bit location. Bit 3 of slot 12—RO. Display bit 3 of the most recent slot 12. Bit 2 of slot 12—RO. Display bit 2 of the most recent slot 12. Bit 1 of slot 12—RO. Display bit 1 of the most recent slot 12. Secondary Resume Interrupt (SRI)—R/WC. This bit indicates that a resume event occurred on AC_SDIN[1]. 1 = Resume event occurred 0 = Cleared by writing a 1 to this bit position. Primary Resume Interrupt (PRI)—R/WC. This bit indicates that a resume event occurred on AC_SDIN[0]. 1 = Resume event occurred 0 = Cleared by writing a 1 to this bit position. Secondary Codec Ready (SCR)—RO. Reflects the state of the codec ready bit in AC_SDIN[1]. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously. 0 = Not Ready. 1 = Ready. Primary Codec Ready (PCR)—RO. Reflects the state of the codec ready bit in AC_SDIN [0]. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously. 0 = Not Ready. 1 = Ready. 7 Mic In Interrupt (MINT)—RO. This bit indicates that one of the Mic in channel interrupts occurred. 1 = Interrupt occurred. 0 = When the specific interrupt is cleared, this bit will be cleared.
16
14 13 12
11
10
9
8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-15
AC’97 Audio Controller Registers (D31:F5)
Bit
Description PCM Out Interrupt (POINT)—RO. This bit indicates that one of the PCM out channel interrupts occurred. 1 = Interrupt occurred. 0 = When the specific interrupt is cleared, this bit will be cleared. PCM In Interrupt (PIINT)—RO. This bit indicates that one of the PCM in channel interrupts occurred. 1 = Interrupt occurred. 0 = 0 = When the specific interrupt is cleared, this bit will be cleared. Reserved Modem Out Interrupt (MOINT)—RO. This bit indicates that one of the modem out channel interrupts occurred. 1 = Interrupt occurred. 0 = When the specific interrupt is cleared, this bit will be cleared. Modem In Interrupt (MIINT)—RO. This bit indicates that one of the modem in channel interrupts occurred. 1 = Interrupt occurred. 0 = When the specific interrupt is cleared, this bit will be cleared. GPI Status Change Interrupt (GSCI)—RWC. This bit reflects the state of bit 0 in slot 12, and is set whenever bit 0 of slot 12 is set. This happens when the value of any of the GPIOs currently defined as inputs changes. 1 = Input changed. 0 = Cleared by writing a 1 to this bit position.
6
5
4:3
2
1
0
13.2.10
CAS—Codec Access Semaphore Register
I/O Address: Default Value: Lockable:
Bit 7:1 Reserved. Codec Access Semaphore (CAS)—R/W (special). This bit is read by software to check whether a codec access is currently in progress. 0 0 = No access in progress. 1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform an I/O access. Once the access is completed, hardware automatically clears this bit.
NABMBAR + 34h 00h No
Attribute: Size: Power Well:
Description
R/W 8 bits Core
13-16
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Modem Controller Registers (D31:F6)
AC’97 Modem Controller Registers (D31:F6)
14.1
Note:
14
AC’97 Modem PCI Configuration Space (D31:F6)
Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
Table 14-1. PCI Configuration Map (Modem—D31:F6)
Offset 00h–01h 02h–03h 04h–05h 06h–07h 08h 09h 0Ah 0Bh 0Eh 0Fh 10h–13h 14h–17h 18h–1Bh 1Ch–2Bh 2Ch–2Dh 2Eh–2Fh 30h–3Bh 3Ch 3Dh 3Eh–FFh Mnemonic VID DID PCICMD PCISTA RID PI SCC BCC HEDT — MMBAR MBAR — — SVID SID — INTR_LN INT_PN — Register Vendor Identification Device Identification PCI Command PCI Device Status Revision Identification Programming Interface Sub Class Code Base Class Code Header Type Reserved Modem Mixer Base Address Modem Base Address Reserved Reserved Subsystem Vendor ID Subsystem ID Reserved Interrupt Line Interrupt Pin Reserved Default 8086 2446h 0000 0280h See Note 00 03h 07h 00 — 00000001h 00000001h 00000001h — 0000h 0000h — 00h 02h — Access RO RO R/W R/WC RO RO RO RO RO — R/W R/W — — Write-Once Write-Once — RO RO —
NOTE: Refer to the Specification Update for the value of the Revision ID Register
14.1.1
VID—Vendor Identification Register (Modem—D31:F6)
Address Offset: Default Value: Lockable:
Bit 15:0 Vendor ID Value.
01h–00h 8086 No
Attribute: Size: Power Well:
Description
RO 16 Bits Core
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-1
AC’97 Modem Controller Registers (D31:F6)
14.1.2
DID—Device Identification Register (Modem—D31:F6)
Address Offset: Default Value: Lockable:
Bit 15:0 Device ID Value.
03h–02h 2446h No
Attribute: Size: Power Well:
Description
RO 16 Bits Core
14.1.3
PCICMD—PCI Command Register (Modem—D31:F6)
Address Offset: Default Value: Lockable: 05h–04h 0000h No Attribute: Size: Power Well: R/W 16 bits Core
PCICMD is a 16-bit control register. Refer to the PCI 2.1 specification for complete details on each bit.
Bit 15:10 9 8 7 6 5 4 3 2 1 Reserved. Read 0. Fast Back to Back Enable (FBE). Not implemented. Hardwired to 0. SERR# Enable (SEN). Not implemented. Hardwired to 0. Wait Cycle Control (WCC). Not implemented. Hardwired to 0. Parity Error Response (PER). Not implemented. Hardwired to 0. VGA Palette Snoop (VPS). Not implemented. Hardwired to 0. Memory Write and Invalidate Enable (MWI). Not implemented. Hardwired to 0. Special Cycle Enable (SCE). Not implemented. Hardwired to 0. Bus Master Enable (BME)—R/W. Controls standard PCI bus mastering capabilities. 0 = Disable. 1 = Enable Memory Space (MS). Hardwired to 0, AC ‘97 does not respond to memory accesses. I/O Space (IOS)—R/W. This bit controls access to the I/O space registers. 0 0 = Disable access. (default = 0). 1 = Enable access to I/O space. The Native PCI Mode Base Address register should be programmed prior to setting this bit. Description
14-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Modem Controller Registers (D31:F6)
14.1.4
PCISTA—Device Status Register (Modem—D31:F6)
Address Offset: Default Value: Lockable: 07h–06h 0280h No Attribute: Size: Power Well: R/WC 16 bits Core
PCISTA is a 16-bit status register. Refer to the PCI 2.1 specification for complete details on each bit.
Bit 15 14 13 12 11 10:9 8 7 6 5 4:0 Description Detected Parity Error (DPE)—RO. Not implemented. Hardwired to 0. SERR# Status (SERRS)—RO. Not implemented. Hardwired to 0. Master-Abort Status (MAS)—R/WC. 1 = Bus Master AC ‘97 interface function, as a master, generates a master abort. 0 = Software clears this bit by writing a 1 to the bit position. Reserved. Read as “0”. Signaled Target-Abort Status (STA)—RO. Not implemented. Hardwired to 0. DEVSEL# Timing Status (DEVT)—RO. This 2-bit field reflects the ICH2's DEVSEL# timing parameter. These read only bits indicate the ICH2's DEVSEL# timing when performing a positive decode. Data Parity Detected (DPD)—RO. Not implemented. Hardwired to 0. Fast Back to back Capable (FBC)—RO. Hardwired to 1. This bit indicates that the ICH2 as a target is capable of fast back-to-back transactions. UDF Supported—RO. Not implemented. Hardwired to 0. 66 MHz Capable—RO. Hardwired to 0. Reserved. Read as 0s.
14.1.5
RID—Revision Identification Register (Modem—D31:F6)
Address Offset: Default Value: Lockable:
Bit 7:0
08h See bit description No
Attribute: Size: Power Well:
Description
RO 8 Bits Core
Revision ID Value—RO. Refer to the Specification Update for the value of the Revision ID Register
14.1.6
PI—Programming Interface Register (Modem—D31:F6)
Address Offset: Default Value: Lockable:
Bit 7:0 Programming Interface Value—RO.
09h 00h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-3
AC’97 Modem Controller Registers (D31:F6)
14.1.7
SCC—Sub Class Code Register (Modem—D31:F6)
Address Offset: Default Value: Lockable:
Bit 7:0 Sub Class Code Value—RO. 03h = Generic Modem.
0Ah 03h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
14.1.8
BCC—Base Class Code Register (Modem—D31:F6)
Address Offset: Default Value: Lockable:
Bit 7:0 Base Class Code Value—RO. 07h = Simple Communications Controller.
0Bh 07h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
14.1.9
HEDT—Header Type Register (Modem—D31:F6)
Address Offset: Default Value: Lockable:
Bit 7:0 Header Value—RO.
0Eh 00h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
14.1.10
MMBAR—Modem Mixer Base Address Register (Modem—D31:F6)
Address Offset: Default Value: 10h–13h 00000001h Attribute: Size: R/W 32 bits
The Native PCI Mode Modem uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the Modem Mixer software interface. The mixer requires 256 bytes of I/O space. All accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. In the case of the split codec implementation accesses to the different codecs are differentiated by the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh for the secondary codec.
14-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Modem Controller Registers (D31:F6)
Bit 31:16 Hardwired to 0s
Description
15:8
Base Address—R/W. These bits are used in the I/O space decode of the Modem interface registers. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For the AC ‘97 Modem, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. This configuration yields a maximum I/O block size of 256 bytes for this base address. Note: This address must align to a 256-byte boundary. Reserved. Read as 0 Resource Type Indicator (RTE)—RO. This bit is set to one, indicating a request for I/O space.
7:1 0
14.1.11
MBAR—Modem Base Address Register (Modem—D31:F6)
Address Offset: Default Value: 14h–17h 00000001h Attribute: Size: R/W 32 bits
The Modem function uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the Modem software interface. The Modem Bus Mastering register space requires 128 bytes of I/O space. All Modem registers reside in the controller, therefore cycles are NOT forwarded over the AC-link to the codec.
Bit 31:16 Hardwired to 0s Base Address—R/W. These bits are used in the I/O space decode of the Modem interface registers. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For the AC ‘97 Modem, the upper 16 bits are hardwired to 0, while bits 15:7 are programmable. This configuration yields a maximum I/O block size of 128 bytes for this base address. Note: This address must align to a 128-byte boundary. 6:1 0 Reserved. Read as 0 Resource Type Indicator (RTE)—RO. This bit is set to one, indicating a request for I/O space. Description
15:7
14.1.12
SVID—Subsystem Vendor ID (Modem—D31:F6)
Address Offset: Default Value: Lockable: 2Dh–2Ch 0000h No Attribute: Size: Power Well: Write-Once 16 bits Core
The SVID register, in combination with the Subsystem ID register, enable the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to the register, the value can be read back. Any subsequent writes will have no effect.
Bit 15:0 Description Subsystem Vendor ID Value—Read/Write-Once.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-5
AC’97 Modem Controller Registers (D31:F6)
14.1.13
SID—Subsystem ID (Modem—D31:F6)
Address Offset: Default Value: Lockable: 2Fh–2Eh 0000h No Attribute: Size: Power Well: Write-Once 16 bits Core
The SID register, in combination with the Subsystem Vendor ID register, makes it possible for the operating environment to distinguish one audio subsystem from another. This register is implemented as a write-once register. Once a value is written to the register, the value can be read back. Any subsequent writes will have no effect.
Bit 15:0 Subsystem ID Value—Read/Write-Once. Description
14.1.14
INTR_LN—Interrupt Line Register (Modem—D31:F6)
Address Offset: Default Value: Lockable: 3Ch 00h No Attribute: Size: Power Well: R/W 8 bits Core
This register indicates which PCI interrupt line is used for the AC’97 module interrupt.
Bit 7:0 Description Interrupt Line—R/W. This data is not used by the ICH2. It is used to communicate to software the interrupt line that the interrupt pin is connected to.
14.1.15
INT_PIN—Interrupt Pin (Modem—D31:F6)
Address Offset: Default Value: Lockable: 3Dh 02h No Attribute: Size: Power Well: RO 8 bits Core
This register indicates which PCI interrupt pin is used for the AC ‘97 modem interrupt. The AC ‘97 interrupt is internally ORed to the interrupt controller with the PIRQB# signal.
Bit 7:3 2:0 Reserved. AC ‘97 Interrupt Routing—RO. Hardwired to 010b to select PIRQB#. Description
14-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Modem Controller Registers (D31:F6)
14.2
AC’97 Modem I/O Space (D31:F6)
In the case of the split codec implementation accesses to the modem mixer registers in different codecs are differentiated by the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh for the secondary codec. Table 14-2 shows the register addresses for the modem mixer registers.
Table 14-2. ICH2 Modem Mixer Register Configuration
Register Primary 00h:38h 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h1 7Ah
1 1
MMBAR Exposed Registers (D31:F6) Name Intel RESERVED Extended Modem ID Extended Modem Status/Control Line 1 DAC/ADC Rate Line 2 DAC/ADC Rate2 Handset DAC/ADC Rate2 Line 1 DAC/ADC Level Mute Line 2 DAC/ADC Level Mute2 Handset DAC/ADC Level Mute2 GPIO Pin Configuration GPIO Polarity/Type GPIO Pin Sticky GPIO Pin Wake Up GPIO Pin Status Misc. Modem AFE Stat/Ctrl Vendor Reserved Vendor Reserved Vendor ID1 Vendor ID2
Secondary 80h:B8h BCh BEh C0h C2h C4h C6h C8h CAh CCh CEh D0h D2h D4h D6h D8h FAh FCh FEh
7Ch 7Eh
1
NOTE: 1. Registers in bold are multiplexed between audio and modem functions 2. Registers in italics are for functions not supported by the ICH2 3. Software should not try to access reserved registers 4. The ICH2 supports a modem codec as either primary or secondary, but does not support two modem codecs.
The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the same global registers in the audio and modem I/O space. Therefore a read/write to these registers in either audio or modem I/O space affects the same physical register. These registers exist in I/O space and reside in the AC ‘97 controller. The two channels, Modem in and Modem out, each have their own set of Bus Mastering registers. The following register descriptions apply to both channels. The naming prefix convention used is as follows:
• MI = Modem in channel • MO = Modem out channel
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-7
AC’97 Modem Controller Registers (D31:F6)
Table 14-3. Modem Registers
Offset 00h 04h 05h 06h 08h 0Ah 0Bh 10h 14h 15h 16h 18h 1Ah 1Bh 3Ch 40h 44h Mnemonic MI_BDBAR MI_CIV MI_LVI MI_SR MI_PICB MI_PIV MI_CR MO_BDBAR MO_CIV MO_LVI MO_SR MI_PICB MO_PIV MO_CR GLOB_CNT GLOB_STA ACC_SEMA Name Modem In Buffer Descriptor List Base Address Register Modem In Current Index Value Register Modem In Last Valid Index Register Modem In Status Register Modem In Position In Current Buffer Register Modem In Prefetch Index Value Register Modem In Control Register Modem Out Buffer Descriptor List Base Address Register Modem Out Current Index Value Register Modem Out Last Valid Register Modem Out Status Register Modem In Position In Current Buffer Register Modem Out Prefetched Index Register Modem Out Control Register Global Control Global Status Codec Write Semaphore Register Default 00000000h 00h 00h 0001h 00h 00h 00h 00000000h 00h 00h 0001h 00h 00h 00h 00000000h 00000000h 00h Access R/W R R/W R/W R RO R/W R/W RO R/W R/W RO RO R/W R/W RO R/W
NOTE: 1. MI = Modem in channel; MO = Modem out channel
14.2.1
x_BDBAR—Buffer Descriptor List Base Address Register
I/O Address: Default Value: Lockable: MBAR + 00h (MIBDBAR), MBAR + 10h (MOBDBAR) 00000000h No Attribute: Size: Power Well: R/W (DWord access only) 32bits Core
This register can be accessed only as a DWord (32 bits).
Bit 31:3 2:0
Description Buffer Descriptor List Base Address[31:3]—R/W. These bits represent address bits 31:3. The entries should be aligned on 8 byte boundaries. Hardwired to 0.
14-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Modem Controller Registers (D31:F6)
14.2.2
x_CIV—Current Index Value Register
I/O Address: Default Value: Lockable:
Bit 7:5 4:0 Hardwired to 0. Current Index Value [4:0]—RO. These bits represent which buffer descriptor within the list of 16 descriptors is being processed currently. As each descriptor is processed, this value is incremented.
MBAR + 04h (MICIV), MBAR + 14h (MOCIV), 00h No
Attribute: Size: Power Well:
Description
RO 8bits Core
14.2.3
x_LVI—Last Valid Index Register
I/O Address: Default Value:
Bit 7:5 4:0 Hardwired to 0 Last Valid Index [4:0]—R/W. These bits indicate the last valid descriptor in the list. This value is updated by software as it prepares new buffers and adds to the list.
MBAR + 05h (MILVI), MBAR + 15h (MOLVI) 00h
Attribute: Power Well:
Description
R/W Core
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-9
AC’97 Modem Controller Registers (D31:F6)
14.2.4
x_SR—Status Register
I/O Address: Default Value: Lockable: MBAR + 06h (MISR), MBAR + 16h (MOSR) 0001h No Attribute: Size: Power Well: R/WC (Word access only) 16 bits Core
This register can be accessed only as a Word (16 bits).
Bit 15:5 Reserved. FIFO error (FIFOE)—R/WC. 1 = FIFO error occurs. 0 = Cleared by writing a 1 to this bit position. 4 Modem in: FIFO error indicates a FIFO overrun. The FIFO pointers do not increment, the incoming data is not written into the FIFO, thereby being lost. Modem out: FIFO error indicates a FIFO underrun. The sample transmitted in this case should be the last valid sample. The ICH2 sets the FIFOE bit if the under-run or overrun occurs when there are more valid buffers to process. Buffer Completion Interrupt Status (BCIS)—R/WC. 1 = Set by the hardware after the last sample of a buffer has been processed, AND if the Interrupt on Completion (IOC) bit is set in the command byte of the buffer descriptor. Remains active until software clears bit. 0 = Cleared by writing a 1 to this bit position. Last Valid Buffer Completion Interrupt (LVBCI)—R/WC. 1 = Set by hardware when last valid buffer has been processed. It remains active until cleared by software. This bit indicates the occurrence of the event signified by the last valid buffer being processed. Thus, this is an event status bit that can be cleared by software once this event has been recognized. This event will cause an interrupt if the enable bit in the Control Register is set. The interrupt is cleared when the software clears this bit. In the case of transmits (PCM out, Modem out) this bit is set, after the last valid buffer has been fetched (not after transmitting it) While in the case of Receives, this bit is set after the data for the last buffer has been written to memory. 0 = Cleared by writing a 1 to this bit position Current Equals Last Valid (CELV)—RO. 1 = Current Index is equal to the value in the Last Valid Index Register, AND the buffer pointed to by the CIV has been processed (i.e., after the last valid buffer has been processed). This bit is very similar to bit 2, except, this bit reflects the state rather than the event. This bit reflects the state of the controller, and remains set until the controller exits this state. 0 = Hardware clears when controller exists state (i.e., until a new value is written to the LVI register). DMA Controller Halted (DCH)—RO. 1 = DMA controller is halted. This could happen because of the Start/Stop bit being cleared, or it could happen once the controller has processed the last valid buffer (in which case it will set bit 1 and halt). Description
3
2
1
0
14-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Modem Controller Registers (D31:F6)
14.2.5
x_PICB—Position In Current Buffer Register
I/O Address: Default Value: Lockable: MBAR + 08h (MIPICB), MBAR + 18h (MOPICB), 0000h No Attribute: Size: Power Well: RO (Word access only) 16 bits Core
This register can be accessed only as a Word (16 bits).
Bit 15:0 Description Position In Current Buffer[15:0]—RO. These bits represent the number of DWords left to be processed in the current buffer.
14.2.6
x_PIV—Prefetch Index Value Register
I/O Address: Default Value: Lockable:
Bit 7:5 4:0 Hardwired to 0 Prefetched Index value [4:0]—RO. These bits represent which buffer descriptor in the list has been prefetched.
MBAR + 0Ah (MIPIV), MBAR + 1Ah (MOPIV) 00h No
Attribute: Size: Power Well:
Description
RO 8 bits Core
14.2.7
x_CR—Control Register
I/O Address: Default Value: Lockable:
Bit 7:5 Reserved. Interrupt On Completion Enable (IOCE)—R/W. This bit controls whether or not an interrupt occurs when a buffer completes with the IOC bit set in its descriptor. 0 = Disable. 1 = Enable. FIFO Error Interrupt Enable (FEIE)—R/W. This bit controls whether the occurrence of a FIFO error will cause an interrupt or not. 0 = Disable. Bit 4 in the Status Register will be set, but the interrupt will not occur. 1 = Enable. Interrupt will occur Last Valid Buffer Interrupt Enable (LVBIE)—R/W. This bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur. 1 = Enable. Reset Registers (RR)—R/W (special). 1 = Contents of all registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). Software needs to set this bit. It must be set only when the Run/Pause bit is cleared. Setting it when the Run bit is set will cause undefined consequences. This bit is self-clearing (software does not need to clear it). 0 = Removes reset condition.
MBAR + 0Bh (MICR), MBAR + 1Bh (MOCR) 00h No
Attribute: Size: Power Well:
Description
R/W 8 bits Core
4
3
2
1
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-11
AC’97 Modem Controller Registers (D31:F6)
Bit Run/Pause Bus master (RPBM)—R/W. 0
Description
0 = Pause bus master operation. This results in all state information being retained (i.e., master mode operation can be stopped and then resumed). 1 = Run. Bus master operation starts.
14.2.8
GLOB_CNT—Global Control Register
I/O Address: Default Value: Lockable: MBAR + 3Ch 00000000h No Attribute: Size: Power Well: R/W (DWord access only) 32 bits Core
This register can be accessed only as a DWord (32 bits).
Bit 31:6 Reserved. Secondary Resume Interrupt Enable—R/W. 5 0 = Disable. 1 = Enable an interrupt to occur when the secondary codec causes a resume event on the AC-link. Primary Resume Interrupt Enable—R/W. 4 0 = Disable. 1 = Enable an interrupt to occur when the primary codec causes a resume event on the AC-link. ACLINK Shut Off—R/W. 3 0 = Normal operation. 1 = Disable the AC-link signals (drive all AC’97 outputs low and turn off all AC’97 input buffer enables) AC’97 Warm Reset—R/W (special). 1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken a suspended codec without clearing its internal registers. If software attempts to perform a warm reset while BIT_CLK is running, the write will be ignored and the bit will not be changed. A warm reset can only occur in the absence of BIT_CLK. 0 = This bit is self-clearing (it clears itself after the reset has occurred and BIT_CLK has started). AC‘97 Cold Reset#—R/W (special). 1 0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC‘97 circuitry. All data in the codec will be lost. Software needs to clear this bit no sooner than after 1usec has elapsed. This bit reflects the state of the AC_RST# pin. The ICH2 clears this bit to “0” upon entering S3/S4/S5 sleep states and PCIRST#. GPI Interrupt Enable (GIE)—R/W. This bit controls whether the change in status of any GPI causes an interrupt. 0 = Bit 0 of the Global Status Register is set, but an interrupt is not generated. 1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register. Description
2
0
14-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet
AC’97 Modem Controller Registers (D31:F6)
14.2.9
GLOB_STA—Global Status Register
I/O Address: Default Value: Lockable: MBAR + 40h 00300000h No Attribute: Size: Power Well: RO, R/W, R/WC (DWord access only) 32 bits Core
This register can be accessed only as a DWord (32 bits).
Bit 31:22 21 Reserved. 6 Channel Capability (6CH_CAP)—RO. Hardwired to 1. 0 = The AC ‘97 Controller does not support 6-channel PCM Audio output. 1 = The AC ‘97 Controller supports 6-channel PCM Audio output. 4 Channel Capability (4CH_CAP)—RO. Hardwired to 1. 20 19:18 17 0 = The AC ‘97 Controller does not support 4-channel PCM Audio output. 1 = The AC ‘97 Controller supports 4-channel PCM Audio output. Reserved. MD3—R/W. Power down semaphore for modem. This bit exists in the suspend well and maintains context across power states (except G3). The bit has no hardware function. It is used by software in conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state. AD3—R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains context across power states (except G3). The bit has no hardware function. It is used by software in conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state. Read Completion Status (RCS)—R/W. This bit indicates the status of codec read completions. 15 14 13 12 0 = A codec read completes normally. 1 = A codec read results in a time-out. The bit remains set until being cleared by software. Bit 3 of slot 12—RO. Display bit 3 of the most recent slot 12 Bit 2 of slot 12—RO. Display bit 2 of the most recent slot 12 Bit 1 of slot 12—RO. Display bit 1 of the most recent slot 12 Secondary Resume Interrupt (SRI)—R/WC. This bit indicates that a resume event occurred on AC_SDIN[1]. 1 = Resume event occurred 0 = Cleared by writing a 1 to this bit position. Primary Resume Interrupt (PRI)—R/WC. This bit indicates that a resume event occurred on AC_SDIN[0]. 1 = Resume event occurred 0 = Cleared by writing a 1 to this bit position. Secondary Codec Ready (SCR)—RO. Reflects the state of the codec ready bit in AC_SDIN[1]. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously. 0 = Not Ready. 1 = Ready. Primary Codec Ready (PCR)—RO. Reflects the state of the codec ready bit in AC_SDIN [0]. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously. 0 = Not Ready. 1 = Ready. 7 Mic In Interrupt (MINT)—RO. This bit indicates that one of the Mic in channel interrupts occurred. 1 = Interrupt occurred. 0 = When the specific interrupt is cleared, this bit will be cleared. Description
16
11
10
9
8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-13
AC’97 Modem Controller Registers (D31:F6)
Bit
Description PCM Out Interrupt (POINT)—RO. This bit indicates that one of the PCM out channel interrupts occurred. 1 = Interrupt occurred. 0 = When the specific interrupt is cleared, this bit will be cleared. PCM In Interrupt (PIINT)—RO. This bit indicates that one of the PCM in channel interrupts occurred. 1 = Interrupt occurred. 0 = 0 = When the specific interrupt is cleared, this bit will be cleared. Reserved Modem Out Interrupt (MOINT)—RO. This bit indicates that one of the modem out channel interrupts occurred. 1 = Interrupt occurred. 0 = When the specific interrupt is cleared, this bit will be cleared. Modem In Interrupt (MIINT)—RO. This bit indicates that one of the modem in channel interrupts occurred. 1 = Interrupt occurred. 0 = When the specific interrupt is cleared, this bit will be cleared. GPI Status Change Interrupt (GSCI)—RWC. This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. This happens when the value of any of the GPIOs currently defined as inputs changes. 1 = Input changed. 0 = Cleared by writing a 1 to this bit position.
6
5
4:3
2
1
0
Note:
On reads from a codec, the controller will give the codec a maximum of 4 frames to respond, after which if no response is received, it will return a dummy read completion to the processor (with all pHs on the data) and also set the Read Completion Status bit in the Global Status Register.
14.2.10
CAS—Codec Access Semaphore Register
I/O Address: Default Value: Lockable:
Bit 7:1 Reserved. Codec Access Semaphore (CAS)—R/W (special). This bit is read by software to check whether a codec access is currently in progress. 0 0 = No access in progress. 1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform an I/O access. Once the access is completed, hardware automatically clears this bit.
NABMBAR + 44h 00h No
Attribute: Size: Power Well:
Description
R/W 8 bits Core
14-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Pinout and Package Information
Pinout and Package Information
15.1 Pinout
15
This section contains the ICH2 82801BA and ICH2-M 82801BAM ballout information. Figure 15-1 and Figure 15-2 provide a graphical illustration of how the ballout maps to the 360 EBGA package for both the ICH2 82801BA and 82801BAM ICH2-M. Table 15-1 provides the ballout for the ICH2 82801BA, listed alphabetically by signal name. Table 15-2 provides the ballout for the ICH2-M 82801BAM, listed alphabetically by signal name.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
15-1
Pinout and Package Information
Figure 15-1. ICH2 82801BA and ICH2-M 82801BAM Ballout (Top view — Left side)
1 2 3 4 5 6 7 8 9 10 11
A
VSS
VSS
HLCOMP
HL0
HL2
HL_STB
HL_STB#
HL5
HL7
VSS
IGNNE#
B
VSS
VSS
VSS
HUBREF
HL1
HL3
HL4
HL6
VSS
VSS
NMI
C
#N/A
VSS
VSS
VSS
HL11
HL9
HL10
HL8
VSS
STPCLK#
INTR
D
#N/A
VCC1_8
VSS
CLK66
VSS
VSS
VSS
VSS
VSS
VCC1_8
A20M#
E
#N/A
#N/A
#N/A
#N/A
VCC1_8
VSS
VSS
VSS
VSS
VCCSUS3_3 (ICH2) F LAN_TXD2 LAN_TXD1 LAN_TXD0 #N/A VCCLAN3_3 (ICH2-M)
VCCSUS3_3 (ICH2) G LAN_RXD1 LAN_RXD0 LAN_CLK #N/A VCCLAN3_3 (ICH2-M)
VCCSUS1_8 (ICH2) H LAN_RXD2 LAN_RSTSYNC #N/A #N/A VCCLAN1_8 (ICH2-M)
VCCSUS1_8 (ICH2) J #N/A #N/A EE_SHCLK EE_DOUT VCCLAN1_8 (ICH2-M) VSS VSS VSS
K
VSS
V5REF1
EE_DIN
EE_CS
VSS
VSS
VSS
GPIO21 (ICH2) L C3_STAT# / GPIO21 (ICH2-M) GNTA# /GPIO16 REQB# / REQ5# / GPIO1 GNTB# / GNT5# / GPIO17 VSS VSS VSS
M
GNT1#
GNT0#
REQA# / GPIO0
PIRQH#
VSS
VSS
VSS
N
PIRQG# / GPIO4
PIRQF#/ GPIO3
PIRQE#
PIRQD#
VSS
VSS
VSS
P
PIRQA#
PIRQB#
PIRQC#
REQ4#
VCC1_8
VSS
VSS
VSS
R
GNT4#
REQ0#
REQ1#
GNT2#
VCC3_3
T
REQ2#
GNT3#
AD30
AD28
VCC3_3
U
AD26
AD24
AD22
AD20
VCC3_3
V
AD18
AD16
FRAME#
TRDY#
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC1_8
W
STOP#
PAR
AD11
AD4
AD3
AD10
SERR#
IRDY#
AD21
AD27
PCICLK
GPIO6 (ICH2) Y AD15 AD13 AD9 AD2 AD5 AD12 PERR# C/BE2# AD23 AD29 AGPBUSY# (ICH2-M)
AA
VSS
VSS
C/BE0#
AD0
AD7
AD14
PLOCK#
AD17
C/BE3#
AD31
GPIO7
AB
VSS
VSS
AD6
AD1
AD8
C/BE1#
DEVSEL#
AD19
AD25
REQ3#
LFRAME# / FWH4
1
2
3
4
5
6
7
8
9
10
11
15-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Pinout and Package Information
Figure 15-2. ICH2 82801BA and ICH2-M 82801BAM Ballout (Top view — Right side)
12 13 14 GPIO23 (ICH2) GMUXSEL# (ICH2-M) 15 GPIO18 (ICH2) STP_PCI# (ICH2-M) VRMPWRGD (ICH2) VGATE / VRMPWRGD (ICH2-M) 16 17 18 19 20 21 22
CPUSLP#
CPUPWRGD
SDA0
SIORDY
SDD15
SDD13
SDD3
VSS
VSS
A
SMI#
RCIN# GPIO22 (ICH2) CPUPERF# (ICH2-M)
SDA2
SDDACK#
SDDREQ
SDD1
SDD11
VSS
VSS
B
INIT#
A20GATE
GPIO20 (ICH2) STP_CPU# (ICH2-M) GPIO19 (ICH2) SLP_S1# (ICH2-M)
SDCS1#
IRQ15
SDIOW#
SDD14
SDD12
SDD4
SDD5
SDD9
C
V_CPU_IO
V_CPU_IO
SDCS3#
SDA1
SDIOR#
SDD0
SDD2
SDD10
SDD8
SDD6
D
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
PDCS3#
SDD7
PDCS1#
PDA2
E
VCC3_3
PDA1
PDA0
IRQ14
PDDACK#
F
VCC3_3
PDIOR#
PIORDY
PDIOW#
PDDREQ
G
VCC3_3
PDD0
PDD15
PDD14
PDD1
H
VSS
VSS
VSS
VCC3_3
PDD2
PDD13
PDD12
PDD3
J
VSS
VSS
VSS
VCC1_8
PDD11
PDD4
PDD10
K
VSS
VSS
VSS
VCC1_8
PDD5
PDD9
PDD8
L
VSS
VSS
VSS
CLK14
V5REF2
PDD6
PDD7
M
VSS
VSS
VSS
APICD1
APICCLK
SERIRQ
SPKR
N
VSS
VSS
VSS
VCC3_3
AC_SYNC
CLK48
AC_SDOUT
APICD0
P
VCC3_3
AC_BITCLK
PWROK
RSMRST#
FERR#
R
VCCSUS3_3
INTRUDER#
RTCRST# TP0(ICH2) BATLOW# (ICH2-M)
VBIAS
RTCX2
T
VCCSUS3_3
SMLINK0
VCCRTC
RTCX1
U
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
VCCSUS3_3
VCCSUS3_3
V5REF_SUS
SMLINK1
GPIO24 (ICH2) CLKRUN# (ICH2-M)
AC_RST#
V
LAD1 / FWH1
LDRQ1#
GPIO12
GPIO25
SLP_S3# RSM_PWROK (ICH2) LAN_PWROK# (ICH2-M)
USBP0P
USBP2P
OC0#
OC3#
PWRBTN#
AC_SDIN1
W
LAD0 / FWH0
LDRQ0#
GPIO8
PME#
SUSSTAT#
USBP0N
USBP2N
OC1#
OC2#
AC_SDIN0
Y
FS0
THRM#
GPIO28
PCIRST#
SMBDATA
RI#
SUSCLK
USBP1N
USBP3N
VSS
VSS
AA
LAD3 / FWH3
LAD2 / FWH2
GPIO27
GPIO13
SMBCLK
SMBALERT# / GPIO11
SLP_S5#
USBP1P
USBP3P
VSS
VSS
AB
12
13
14
15
16
17
18
19
20
21
22
82801BA ICH2 and 82801BAM ICH2-M Datasheet
15-3
Pinout and Package Information
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name SDD03 A20GATE A20M# AC_BITCLK AC_RST# AC_SDIN0 AC_SDIN1 AC_SDOUT AC_SYNC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 Ball Number A20 C13 D11 R19 V22 Y22 W22 P21 P19 AA4 AB4 Y4 W5 W4 Y5 AB3 AA5 AB5 Y3 W6 W3 Y6 Y2 AA6 Y1 V2 AA8 V1 AB8 U4 W9 U3 Y9 U2 AB9 U1 W10
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name AD28 AD29 AD30 AD31 APICCLK APICD0 APICD1 C/BE0# C/BE1# C/BE2# C/BE3# CLK14 CLK48 CLK66 CPUPWRGD CPUSLP# DEVSEL# EE_CS EE_DIN EE_DOUT EE_SHCLK FERR# FRAME# FS0 GNT0# GNT1# GNT2# GNT3# GNT4# GNTA# / GPIO16 GNTB# / GNT5# / GPIO17 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO18 GPIO19 Ball Number T4 Y10 T3 AA10 N20 P22 N19 AA3 AB6 Y8 AA9 M19 P20 D4 A13 A12 AB7 K4 K3 J4 J3 R22 V3 AA12 M2 M1 R4 T2 R1 L2 L4 Y11 AA11 Y14 W14 AB15 A15 D14
15-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Pinout and Package Information
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO27 GPIO28 HL_STB HL_STB# HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HL11 HLCOMP HUBREF IGNNE# INIT# INTR INTRUDER# IRDY# IRQ14 IRQ15 LAD0 / FWH0 LAD1 / FWH1 LAD2 / FWH2 LAD3 / FWH3 LAN_CLK LAN_RSTSYNC LAN_RXD0 Ball Number C14 L1 B14 A14 V21 W15 AB14 AA14 A6 A7 A4 B5 A5 B6 B7 A8 B8 A9 C8 C6 C7 C5 A3 B4 A11 C12 C11 T19 W8 F21 C16 Y12 W12 AB13 AB12 G3 H2 G2
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LDRQ0# LDRQ1# LFRAME# / FWH4 NMI OC0# OC1# OC2# OC3# PAR PCICLK PCIRST# PDA0 PDA1 PDA2 PDCS1# PDCS3# PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDDACK# Ball Number G1 H1 F3 F2 F1 Y13 W13 AB11 B11 W19 Y20 Y21 W20 W2 W11 AA15 F20 F19 E22 E21 E19 H19 H22 J19 J22 K21 L20 M21 M22 L22 L21 K22 K20 J21 J20 H21 H20 F22
82801BA ICH2 and 82801BAM ICH2-M Datasheet
15-5
Pinout and Package Information
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name PDDREQ PDIOR# PDIOW# PERR# PIORDY PIRQA# PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# PLOCK# PME# PWRBTN# PWROK RCIN# REQ0# REQ1# REQ2# REQ3# REQ4# REQA# / GPIO0 REQB# / REQ5#/ GPIO1 RI# RSM_PWROK RSMRST# RTCRST# RTCX1 RTCX2 SDA0 SDA1 SDA2 SDCS1# SDCS3# SDD0 SDD1 Ball Number G22 G19 G21 Y7 G20 P1 P2 P3 N4 N3 N2 N1 M4 AA7 Y15 W21 R20 B13 R2 R3 T1 AB10 P4 M3 L3 AA17 Y16 R21 T20 U22 T22 A16 D16 B16 C15 D15 D18 B19
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name SDD2 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDDACK# SDDREQ SDIOR# SDIOW# SERIRQ SERR# SIORDY SLP_S3# SLP_S5# SMBALERT# / GPIO11 SMBCLK SMBDATA SMI# SMLINK0 SMLINK1 SPKR STOP# STPCLK# SUSCLK SUSSTAT# THRM# TP0 TRDY# USBP0N USBP0P Ball Number D19 C20 C21 D22 E20 D21 C22 D20 B20 C19 A19 C18 A18 B17 B18 D17 C17 N21 W7 A17 W16 AB18 AB17 AB16 AA16 B12 U19 V20 N22 W1 C10 AA18 Y17 AA13 U20 V4 Y18 W17
15-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Pinout and Package Information
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P V_CPU_IO V_CPU_IO V5REF_SUS V5REF1 V5REF2 VBIAS VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCCRTC Ball Number AA19 AB19 Y19 W18 AA20 AB20 D12 D13 V19 K2 M20 T21 D10 D2 K19 L19 P5 V9 E5 E14 E15 E16 E17 E18 F18 G18 H18 J18 P18 R18 R5 T5 U5 V5 V6 V7 V8 U21
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VRMPWRGD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball Number H5 J5 V14 V15 V16 F5 G5 T18 U18 V17 V18 B15 D7 D8 D9 E6 E7 E8 E9 J10 J11 J12 J13 J14 J9 K1 K10 K11 K12 K13 K14 K9 L10 L11 A1 A10 A2 A21
82801BA ICH2 and 82801BAM ICH2-M Datasheet
15-7
Pinout and Package Information
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball Number A22 AA1 AA2 AA21 AA22 AB1 AB2 AB21 AB22 B1 B10 B2 B21 B22 B3 B9 C2 C3 C4 C9 D3 D5 D6
Table 15-1. ICH2 82801BA Alphabetical Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball Number L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9
15-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Pinout and Package Information
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name A20GATE A20M# AC_BITCLK AC_RST# AC_SDIN0 AC_SDIN1 AC_SDOUT AC_SYNC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 Ball Number C13 D11 R19 V22 Y22 W22 P21 P19 AA4 AB4 Y4 W5 W4 Y5 AB3 AA5 AB5 Y3 W6 W3 Y6 Y2 AA6 Y1 V2 AA8 V1 AB8 U4 W9 U3 Y9 U2 AB9 U1 W10 T4
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name AD29 AD30 AD31 AGPBUSY# APICCLK APICD0 APICD1 BATLOW# C/BE0# C/BE1# C/BE2# C/BE3# C3_STAT# / GPIO21 CLK14 CLK48 CLK66 CLKRUN# CPUPERF# CPUPWRGD CPUSLP# DEVSEL# EE_CS EE_DIN EE_DOUT EE_SHCLK FERR# FRAME# FS0 GMUXSEL# GNT0# GNT1# GNT2# GNT3# GNT4# GNTA# / GPIO16 GNTB# / GNT5# / GPIO17 GPIO7 Ball Number Y10 T3 AA10 Y11 N20 P22 N19 U20 AA3 AB6 Y8 AA9 L1 M19 P20 D4 V21 B14 A13 A12 AB7 K4 K3 J4 J3 R22 V3 AA12 A14 M2 M1 R4 T2 R1 L2 L4 AA11
82801BA ICH2 and 82801BAM ICH2-M Datasheet
15-9
Pinout and Package Information
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name GPIO8 GPIO12 GPIO13 GPIO25 GPIO27 GPIO28 HL_STB HL_STB# HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HL11 HLCOMP HUBREF IGNNE# INIT# INTR INTRUDER# IRDY# IRQ14 IRQ15 LAD0 / FWH0 LAD1 / FWH1 LAD2 / FWH2 LAD3 / FWH3 LAN_CLK LAN_PWROK LAN_RSTSYNC LAN_RXD0 Ball Number Y14 W14 AB15 W15 AB14 AA14 A6 A7 A4 B5 A5 B6 B7 A8 B8 A9 C8 C6 C7 C5 A3 B4 A11 C12 C11 T19 W8 F21 C16 Y12 W12 AB13 AB12 G3 Y16 H2 G2
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LDRQ0# LDRQ1# LFRAME# / FWH4 NMI OC0# OC1# OC2# OC3# PAR PCICLK PCIRST# PDA0 PDA1 PDA2 PDCS1# PDCS3# PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 Ball Number G1 H1 F3 F2 F1 Y13 W13 AB11 B11 W19 Y20 Y21 W20 W2 W11 AA15 F20 F19 E22 E21 E19 H19 H22 J19 J22 K21 L20 M21 M22 L22 L21 K22 K20 J21 J20 H21 H20
15-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Pinout and Package Information
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name PDDACK# PDDREQ PDIOR# PDIOW# PERR# PIORDY PIRQA# PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# PLOCK# PME# PWRBTN# PWROK RCIN# REQ0# REQ1# REQ2# REQ3# REQ4# REQA# / GPIO0 REQB# / REQ5#/ GPIO1 RI# RSMRST# RTCRST# RTCX1 RTCX2 SDA0 SDA1 SDA2 SDCS1# SDCS3# SDD0 Ball Number F22 G22 G19 G21 Y7 G20 P1 P2 P3 N4 N3 N2 N1 M4 AA7 Y15 W21 R20 B13 R2 R3 T1 AB10 P4 M3 L3 AA17 R21 T20 U22 T22 A16 D16 B16 C15 D15 D18
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDDACK# SDDREQ SDIOR# SDIOW# SERIRQ SERR# SIORDY SLP_S1# SLP_S3# SLP_S5# SMBALERT# / GPIO11 SMBCLK SMBDATA SMI# SMLINK0 SMLINK1 SPKR STOP# STP_CPU# STP_PCI# STPCLK# SUSCLK Ball Number B19 D19 A20 C20 C21 D22 E20 D21 C22 D20 B20 C19 A19 C18 A18 B17 B18 D17 C17 N21 W7 A17 D14 W16 AB18 AB17 AB16 AA16 B12 U19 V20 N22 W1 C14 A15 C10 AA18
82801BA ICH2 and 82801BAM ICH2-M Datasheet
15-11
Pinout and Package Information
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name SUSSTAT# THRM# TRDY# USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P V_CPU_IO V_CPU_IO V5REF_SUS V5REF1 V5REF2 VBIAS VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 Ball Number Y17 AA13 V4 Y18 W17 AA19 AB19 Y19 W18 AA20 AB20 D12 D13 V19 K2 M20 T21 D10 D2 K19 L19 P5 V9 E5 E14 E15 E16 E17 E18 F18 G18 H18 J18 P18 R18 R5 T5
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCCLAN1_8 VCCLAN1_8 VCCLAN3_3 VCCLAN3_3 VCCRTC VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VGATE / VRMPWRGD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball Number U5 V5 V6 V7 V8 H5 J5 F5 G5 U21 V14 V15 V16 T18 U18 V17 V18 B15 D7 D8 D9 E6 E7 E8 E9 J10 J11 J12 J13 J14 J9 K1 K10 K11 K12 K13 K14
15-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Pinout and Package Information
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball Number K9 L10 L11 A1 A10 A2 A21 A22 AA1 AA2 AA21 AA22 AB1 AB2 AB21 AB22 B1 B10 B2 B21 B22 B3 B9 C2 C3 C4
Table 15-2. ICH2-M 82801BAM Alphabetical Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball Number C9 D3 D5 D6 L12 L13 L14 L9 M10 M11 M12 M13 M14 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9
82801BA ICH2 and 82801BAM ICH2-M Datasheet
15-13
Pinout and Package Information
15.2
Package Information
Figure 15-3 and Figure 15-4 illustrate the ICH2 and ICH2-M 360 EBGA package.
Figure 15-3. ICH2 / ICH2-M Package (Top and Side Views)
Top View
0.127 A 23.00 ±0.10 Pin 1 corner 19.50 ±0.20 -BPin 1 I.D. -A-
Detail A
23.00 ±0.10 14.70 REF 19.50 ±0.20
45° Chamfer (4 places)
0.127
A
14.70 REF
Detail A (Not to scale)
Pin #1 Corner No Radius Au Gate
90°
Pin #1 SHINY 1.0 Dia x 0.15 Depth 6.75 ±0.50 x 6.75 ±0.50 From Center Line
Side View
2.23 ±0.19 1.17 ±0.05 30°
0.15 C 0.15 0.56 ±0.04 0.50 ±0.10 Seating Plane (see Note 3) Notes: 1. All dimensions are in millimeters. 2. All dimensions and tolerances conform to ANSI Y14.5M - 1982. 3. Primary Datum (-C-) and seating plane are defined by the sperical crowns of the solder balls. -C-
15-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Pinout and Package Information
Figure 15-4. ICH2 / ICH2-M Package (Bottom View)
B o tto m V iew
22 N ote 3
ϕ
P in A 1 corner 8 6 4 2
21
20
19
18
17
16
15
14
13
12
11
10
9
7
5
3
1
0 .70 0 .50 BS A B C D E F G H J 1.00 K L M N P R T U V W Y AA AB 1.00 R E F 1.00
ϕ 0 .30 S
C
AS
1.00 R E F
ϕ 1 .0
3 places
N otes : 1. A ll dim ensions are in m illim eters. 2. A ll dim ensions and toleranc es conform to A N S I Y 14.5M - 1982. 3. D im ension is m easured at the m axim um s older ball diam eter. P arallel to D atum (-C -) on S ide V iew illustration.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
15-15
Pinout and Package Information
This page is intentionally left blank.
15-16
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Electrical Characteristics
Note:
16
The data provided in this chapter regarding the Electrical Characteristics of the ICH2 component are preliminary and subject to change.
16.1
Absolute Maximum Ratings
Case Temperature under Bias ..................................................................................... 0°C to +109°C Storage Temperature ............................................................................................... -55°C to +150°C Voltage on Any 3.3V Pin with Respect to Ground ...............................................-0.5 to Vcc + 0.3 V Voltage on Any 5V Tolerant Pin with Respect to Ground (VREF=5V)...............-0.5 to VREF + 0.3 V 1.8V Supply Voltage with Respect to Vss ..................................................................... -0.5 to +2.7V 3.3V Supply Voltage with Respect to Vss .................................................................... -0.5 to +4.6 V 5.0V Supply Voltage (Vref) with Respect to Vss ......................................................... -0.5 to +5.5 V Maximum Power Dissipation ....................................................................................................2.0 W
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. See Section 16.2 for the Functional Operating Range of the ICH2.
16.2
Functional Operating Range
All of the AC and DC Characteristics specified in this document assume that the ICH2 component is operating within the Functional Operating Range given in this section. Operation outside of the Functional Operating Range is not recommended, and extended exposure outside of the Functional Operating Range may affect component reliability. Case Temperature under Bias .................................................................................... 0°C to +109°C 1.8V Supply Voltage (VCC1_8) with respect to Vss......................................................1.7V to 1.9V 1.8V Supply Voltage (VccSus1_8) with respect to Vss..................................................1.6V to 1.9V ICH2-M: 1.8V Supply Voltage (VCCLAN1_8) with respect to Vss...........................1.6V to 1.9V 3.3V Supply Voltage (VCC3_3, VccSus3_3) with respect to Vss .........................3.102V to 3.498V ICH2-M: 3.3V Supply Voltage (VCCLAN3_3) with respect to Vss...................3.102V to 3.498V 5V Supply Voltage (V5REF, V5REF_Sus) with respect to Vss ................................ 4.75V to 5.25V V_CPU_IO Voltage with respect to Vss......................................................................................TBD
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-1
Electrical Characteristics
16.3
D.C. Characteristics
Table 16-1. ICH2-M Power Consumption Measurements
Power Plane S0 1.8V Core 3.3V I/O 1.8V LAN 3.3V LAN (LAN + LAN Connect Component) 186 mA 180 mA 2 mA (ICH2) 1.8 mA (ICH2-M) 1.4 mA 300 mA 410 mA 30 mA Maximum Sustain Supply Current Icc(max) S1 100 mA 5 mA 23 mA S3 0 0 6 mA S4 0 0 6 mA S5 0 0 6 mA G3 (ICH2-M)
180 mA; 50 mA when LAN Connect Componenplaced in reduced power mode (50 MHz clk!5 MHz)
1.8V Sus
5 mA
1.8 mA
1.8 mA
1.8 mA
3.3V Sus VccRTC
15 mA
1.4 mA
1.4 mA
1.4 mA 4 uA
NOTES: 1. 1.8V and 3.3V LAN Icc(max) in S0 was measured running Full Duplex LAN test. 2. 1.8V SUS Icc(max) in S0 state was measured while running a test that continuously accessed PM registers. 3. 3.3V SUS Icc(max) in S0 state was measured running a concurrency test, in which all 4 USB ports were exercised. 4. 1.8V Core and 3.3V I/O Icc(max) in S0 state was measured running a test that generated a constant stream of CPU->PCI writes, with an inverting pattern, causing data lines to switch on every clock.
Table 16-2. DC Characteristic Input Signal Association
Symbol Associated Signals PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, TRDY#, STOP#, PAR, PERR#, PLOCK#, SERR#, REQ[4:0]# PC/PCI Signals: REQ[A]#/GPIO[0], REQB[#]/REQ[5]#/GPIO[1] IDE Signals: PDD[15:0], SDD[15:0], PDDREQ, PIORDY, SDDREQ, SIORDY Interrupt Signals: IRQ[15:14], SERIRQ, PIRQ[D:A]#, PIRQ[H]#, PIRQ[G:F]#/GPIO[4:3], PIRQ[E]# VIH1/VIL1 (5V Tolerant) Legacy Signals: RCIN#, A20GATE USB Signals: OC[3:0]#. ICH2 (82801BA): GPIO Signals: GPIO[7,6,4,3,1,0] ICH2-M (82801BAM): GPIO Signals: GPIO[7,4,3,1,0] Power Management Signals: AGPBUSY# VIH2/VIL2 Clock Signals: CLK66, CLK48, CLK14, LAN_CLK, PCICLK
16-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Table 16-2. DC Characteristic Input Signal Association (Continued)
Symbol Associated Signals LPC/FWH Signals: LDRQ[1:0]#, LAD[3:0]/FWH[3:0]. System Management Signals: SMBALERT#/GPIO[11] EEPROM Signals: EE_DIN AC’97 Signals: AC_BITCLK, AC_SDIN[1:0], AC_SYNC ICH2 (82801BA): VIH3/VIL3 Power Management Signals: PME#, PWRBTN#, RI#, RSM_PWROK, RTCRST#, THRM#, VRMPWRGD GPIO Signals: GPIO[25:24, 13:12, 8] ICH2-M (82801BAM): Power Management Signals: BATLOW#, CLKRUN#, PME#, PWRBTN#, RI#, LAN_PWROK, RTCRST#, THRM#, VRMPWRGD/VGATE GPIO Signals: GPIO[25, 13:12, 8] VIH4/VIL4 Clock Signals: APICCLK SMBus Signals: SMBCLK, SMBDATA System Management Signals: INTRUDER#, SMLINK[1:0] VIH5/VIL5 Power Management Signals: RSMRST#, PWROK, GPIO Signals: GPIO[28:27] VIL6/VIH6 VIL7/VIH7 VIL8/VIH8 VDI / VCM / VSE VIL9/VIH9 LAN Signals: LAN_RXD[2:0] Processor Signals: FERR#, APICD[1:0] Hub Interface Signals: HL[11:0], HL_STB#, HL_STB USB Signals: USBP[1:0][P,N] RTCX1
Table 16-3. DC Input Characteristics
Symbol VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VIL4 VIH4 VIL5 VIH5 VIL6 VIH6 VIL7 VIH7 VIL8 Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Min. -0.5 2.0 -0.5 2.0 -0.5 0.5Vcc3_3 -0.5 1.7 -0.5 2.1 -0.5 0.6Vcc3_3 -0.5 1.2 -0.5 HUBREF - 0.20 Max 0.8 V5REF + 0.5 0.8 Vcc3_3 + 0.5 0.3Vcc3_3 Vcc3_3 + 0.5 0.7 2.625 0.6 VccSus3_3 + 0.5 0.3Vcc3_3 Vcc3_3 + 0.5 0.6 Vcc3_3 + 0.5 HUBREF - 0.15 V Enhanced Mode Unit V V V V V V V V V V V V V V Normal Mode Notes
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-3
Electrical Characteristics
Table 16-3. DC Input Characteristics
Symbol VIH8 VDI VCM VSE VIL9 VIH10 Parameter Input High Voltage HUBREF + 0.20 Differential Input Sensitivity Differential Common Mode Range Single-Ended Receiver Threshold Input Low Voltage Input High Voltage 0.2 0.8 0.8 -0.5 0.40 2.5 2.0 0.10 2.0 V V V V V Min. HUBREF + 0.15 Vcc1_8 + 0.5 V Enhanced Mode Note 1 Note 2 Max Unit Notes Normal Mode
NOTES: 1. VDI = | USBPx[P] - USBPx[N] | 2. Includes VDI range.
Table 16-4. DC Characteristic Output Signal Association
Symbol Associated Signals IDE Signals: PDD[15:0], SDD[15:0], PDIOW#/PDSTOP, SDIOW#/SDSTOP, PDIOR#/ PDWSTB/PRDMARDY, SDIOR#/STWSTB/SRDMARDY, PDDACK#, SDDACK#, PDA[2:0], SDA[2:0], PDCS[3,1]#, SDCS[3,1]# Processor Signals: A20M#, CPUPWRGD, CPUSLP#, IGNNE#, INIT#, INTR, NMI, SMI#, STPCLK# PCI Signals: AD[31:0], C/BE[3:0]#, PCIRST#, GNT[4:0]#, PAR, DEVSEL#, PERR#, PLOCK#, STOP#, TRDY#, IRDY#, FRAME#, SERR# Interrupt Signals: SERIRQ, PIRQ[D:A]#, PIRQ[H]#, PIRQ[G:F]#/GPIO[4:3], PIRQ[E]# PCI Signals: GNT5#/GNTB#/GPIO17, GNTA#/GPIO16 LPC/FWH Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4] AC’97 Signals: AC_RST#, AC_SDOUT, AC_SYNC VOH4/VOL4 LAN Signals: LAN_RSTSYNC, LAN_TXD[2:0] ICH2 (82801BA): Power Management Signals: PME# GPIO Signals: GPIO[21] ICH2-M (82801BAM): Power Management Signals: PME#, C3_STAT# SMBus Signals: SMBCLK, SMBDATA VOL5/VOH5 System Management Signals: SMLINK[1:0] Interrupt Signals: APICD[1:0] EEPROM Signals: EE_CS, EE_DOUT, EE_SHCLK Other Signals: SPKR] ICH2 (82801BA): VOL6/VOH6 Power Management Signals: SLP_S3#, SLP_S5#, SUS_STAT#, SUSCLK GPIO Signals: GPIO[25:22, 20:18] ICH2-M (82801BAM): GPIO Signals: GPIO[25] VOL7/VOH7 VOL8/VOH8 USB Signals: USBPO[P:N], USBP1[P:N] Hub Signals: HL[11:0], HL_STB#, HL_STB
VOH1/VOL1 VOH2/VOL2
VOH3/VOL3
16-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Table 16-5. DC Output Characteristics
Symbol VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 VOL4 VOH4 VOL5 VOH5 VOL6 VOH6 VOL7 VOH7 VOL8 Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage 0.8 0.9(Vcc1_8) VOH8 Output High Voltage 1.6 V V V Vcc - 0.5 0.1(Vcc1_8) Vcc3_3 - 0.5 0.4 N/A 0.4 0.9Vcc 0.4 2.4 0.1Vcc V_CPU_IO - 0.13V 0.55 2.4 0.4 Min. Max 0.5 Unit V V V V V V V V V V V V V V V 4.0 mA -2.0 mA 5 mA -2 mA 1 mA 20 mA -1 mA -1.5 mA Normal Mode Enhanced Mode Normal Mode Enhanced Mode Note 1 IOL / IOH 4 mA -0.4 mA 4.0 mA -0.5 mA 6 mA -2 mA 1.5 mA -0.5 mA 3.0 mA Note 1 Note 1 Note 1 Note 1 Notes
NOTES: 1. The CPUPWRGD, SERR#, PIRQ[A:H], PME#, GPIO22/CPUPERF, APIC[1:0], SMBDATA, SMBCLK and SMLINK[1:0] signals have an open drain driver, and the VOH specification does not apply. These signals must have external pull-up resistors.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-5
Electrical Characteristics
Table 16-6. Other DC Characteristics
Symbol VBIAS V5REF VCC3_3 VCC1_8 HUBREF V5REF_Sus VccSus3_3 VccSus1_8 VccLAN3_3 (ICH2-M) VccLAN1_8 (ICH2-M) Vcc(RTC) VIT+ VITVDI VCM VCRS VSE ILI1 ILI2 ILI3 CIN COUT CI/O CL Parameter Voltage BIAS ICH2 Core Well Reference Voltage I/O Buffer Voltage Internal Logic Voltage Hub Interface Reference Voltage 0.64(Vcc1.8) Suspend Well Reference Voltage Suspend Well I/O Buffer Voltage Suspend Well Logic Voltage LAN Controller I/O Buffer Voltage LAN Controller Logic Voltage Battery Voltage Hysteresis Input Rising Threshold Hysteresis Input Falling Threshold Differential Input Sensitivity Differential Common Mode Range Output Signal Crossover Voltage Single Ended Rcvr Threshold Input Leakage Current Hi-Z State Data Line Leakage Input Leakage Current - Clock signals Input Capacitance - Hub interface Input Capacitance - All Other Output Capacitance I/O Capacitance Crystal Load Capacitance 7.5 0.2 0.8 1.3 0.8 -1.0 -10 -100 2.5 2.0 2.0 +1.0 +10 +100 8 12 12 12 15 4.75 3.102 1.6 3.102 1.7 2.0 1.9 1.3 0.70(Vcc1.8) 5.25 3.498 1.9 3.498 1.9 3.6 V V V V V V V V V V V V V uA uA uA pF pF pF pF (0 V< VIN< 3.3V) See Note FC = 1 MHz FC = 1 MHz FC = 1 MHz Applied to USBP[3:0][P:N] Applied to USBP[3:0]P:N] |(USBPx+,USBPx-)| Includes VDI Enhanced Mode Min. 0.32 4.75 3.102 1.7 0.48(Vcc1.8) Max 0.44 5.25 3.498 1.9 0.52(Vcc1.8) Unit V V V V V Normal Mode Notes
NOTE: Includes APICCLK, CLK14, CLK48, CLK66, LAN_CLK and PCICLK
16-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
16.4
A.C. Characteristics
Table 16-7. Clock Timings
Sym Parameter PCI Clock (PCICLK) t1 t2 t3 t4 t5 Period High Time Low Time Rise Time Fall Time Oscillator Clock (OSC) t6 t7 t8 Period High Time Low time USB Clock (USBCLK) fclk48 t9 t10 t11 t12 t13 Operating Frequency Frequency Tolerance High Time Low time Rise Time Fall Time Suspend Clock (SUSCLK) fsusclk t14 t15 Operating Frequency High time Low Time SMBus Clock (SMBCLK) fsmb t18 t19 t20 t21 Operating Frequency High time Low time Rise time Fall time I/O APIC Clock (APICCLK) fioap t22 t23 t24 t25 Operating Frequency High time Low time Rise time Fall time 14.32 12 12 1.0 1.0 33.33 36 36 5.0 5.0 MHz ns ns ns ns 16-2 16-2 16-2 16-2 10 4.0 4.7 1000 300 16 50 KHz us us ns ns 2 16-17 16-17 16-17 16-17 10 10 32 KHz us us 5 5 5 16-2 16-2 7 7 1.2 1.2 48 2500 MHz ppm ns ns ns ns 1 16-2 16-2 16-2 16-2 67 20 20 ns 70 ns 16-2 16-2 16-2 30 12 12 3 3 33.3 ns ns ns ns ns 16-2 16-2 16-2 16-2 16-2 Min Max Unit Notes Figure
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-7
Electrical Characteristics
Table 16-7. Clock Timings (Continued)
Sym Parameter AC’97 Clock (BITCLK) fac97 t26 t27 t28 t29 t30 Operating Frequency Output Jitter High time Low time Rise time Fall time Hub Interface Clock fhl t31 t32 t33 t34 t35 Operating Frequency High time Low time Rise time Fall time CLK66 leads PCICLK 6.0 6.0 0.25 0.25 1.0 1.2 1.2 4.5 66 ns ns ns ns 3 16-2 16-2 16-2 16-2 32.56 32.56 2.0 2.0 12.288 750 48.84 48.84 6.0 6.0 ns ns ns ns 4 4 16-2 16-2 16-2 16-2 Min Max Unit Notes Figure
NOTES: 1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. 2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle conditions. 3. This specification includes pin-to-pin skew from the clock generator as well as board skew. 4. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD. 5. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
16-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Table 16-8. PCI Interface Timing
Sym t40 t41 t42 t43 Parameter AD[31:0] Valid Delay AD[31:0] Setup Time to PCICLK Rising AD[31:0] Hold Time from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, DEVSEL# Valid Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output Enable Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, Setup Time to PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold Time from PCLKIN Rising PCIRST# Low Pulse Width GNT[A:B}#, GNT[5:0]# Valid Delay from PCICLK Rising REQ[A:B]#, REQ[5:0]# Setup Timer to PCICLK Rising Min 2 7 0 2 11 Max 11 Units ns ns ns ns Min: 0pF Max: 50pF Notes Min: 0pF Max: 50pF Figure 16-3 16-4 16-4 16-3
t44
2
ns
16-7
t45
2
28
ns
16-5
t46
7
ns
16-4
t47 t48 t49 t50
0 1 2 12 12
ns ms ns ns
16-4 16-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-9
Electrical Characteristics
Table 16-9. IDE PIO & Multiword DMA Mode Timing
Sym t60 t61 t62 t63 t64 t65 t66 t67 t68 t69 t70 t71 t72 t73 t74 t75 t76 Parameter PDIOR#/PDIOW#/SDIOR#/SDIOW# Active From CLK66 Rising PDIOR#/PDIOW#/SDIOR#/SDIOW# Inactive From CLK66 Rising PDA[2:0]/SDA[2:0] Valid Delay From CLK66 Rising PDCS1#/SDCS1#, PDCS3#/SDCS3# Active From CLK66 Rising PDCS1#/SDCS1#, PDCS3#/SDCS3# Inactive From CLK66 Rising PDDACK#/SDDACK# Active From CLK66 Rising PDDACK#/SDDACK# Inactive From CLK66 Rising PDDREQ/SDDREQ Setup Time to CLK66 Rising PDDREQ/SDDREQ Hold From CLK66 Rising PDD[15:0]/SDD[15:0] Valid Delay From CLK66 Rising PDD[15:0]/SDD[15:0] Setup Time to CLK66 Rising PDD[15:0]/SDD[15:0] Hold From CLK66 Rising PIORDY/SIORDY Setup Time to CLK66 Rising PIORDY/SIORDY Hold From CLK66 Rising PIORDY/SIORDY Inactive Pulse Width PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width Low PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width High Min 2 2 2 2 2 2 2 7 7 2 10 7 7 7 48 30 Max 20 20 30 30 30 20 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2,3 3,4 1 1 16-9 16-9 16-8, 16-9 16-8, 16-9 16-8, 16-9 16-8 16-8 16-8 16-8, 16-9 16-8, 16-9 Notes Figure 16-8, 16-9 16-8, 16-9 16-8 16-8 16-8 16-9
NOTES: 1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock. 2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register 3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE timing register. 4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or greater. Refer to the RCT field in the IDE Timing Register.
16-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Table 16-10. Ultra ATA Timing (Mode 0, Mode 1, Mode 2)
Sym t80 t81 t82 t83 t84 t85 t86 t87 t88 t89 t90 t91 Parameter (1) Sustained Cycle Time (T2cyctyp) Cycle Time (Tcyc) Two Cycle Time (T2cyc) Data Setup Time (Tds) Data Hold Time (Tdh) Data Valid Setup Time (Tdvs) Data Valid Hold Time (Tdvh) Limited Interlock Time (Tli) Interlock Time w/ Minimum (Tmli) Envelope Time (Tenv) Ready to Pause Time (Trp) DMACK setup/hold Time (Tack) 112 230 15 5 70 6 0 20 20 160 20 70 150 Mode 0 (ns) Min Max 240 73 154 10 5 48 6 0 20 20 125 20 70 150 Mode 1 (ns) Min 160 54 115 7 5 30 6 0 20 20 100 20 70 150 Max Mode 2 (ns) Figure Min 120 16-11 16-11 16-11 16-11 16-11 16-11 16-13 16-13 16-10 16-12 16-10, 16-13 Max
NOTE: 1. The specification symbols in parentheses correspond to the Ultra ATA specification name.
Table 16-11. Ultra ATA Timing (Mode 3, Mode 4, Mode 5)
Sym t80 t81 t82 t83 t84 t85 t86 t87 t88 t89 t90 t91 Parameter (1) Sustained Cycle Time (T2cyctyp) Cycle Time (Tcyc) (2) Two Cycle Time (T2cyc) Data Setup Time (Tds) Data Hold Time (Tdh) Data Valid Setup Time (Tdvs) Data Valid Hold Time (Tdvh) Limited Interlock Time (Tli) Interlock Time w/ Minimum (Tmli) Envelope Time (Tenv) Ready to Pause Time (Trp) DMACK setup/hold Time (Tack) 39 86 7 5 20 6 0 20 20 100 20 55 100 Mode 3 (ns) Min 90 25 57 5 5 6 6 0 20 20 100 20 55 20 85 20 100 Max Mode 4 (ns) Min 60 16.8 38 4.0 4.6 3.3 3.3 0 75 20 50 Max Mode 5 (ns) Figure Min 40 16-11 16-11 16-11 16-11 16-11 16-11 16-13 16-13 16-10 16-12 16-10, 16-13 Max
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-11
Electrical Characteristics
Table 16-12. Universal Serial Bus Timing
Sym Parameter Min Max Units Notes Fig
Full Speed Source (Note 7) t100 t101 t102 t103 t104 t105 USBPx+, USBPx- Driver Rise Time USBPx+, USBPx- Driver Fall Time Source Differential Driver Jitter To Next Transition For Paired Transitions Source EOP Width Differential to SE0 Transition Skew Receiver Data Jitter Tolerance To Next Transition For Paired Transitions t106 t107 EOP Width: Must reject as EOP EOP Width: Must accept as EOP Differential to SE0 Transition Skew -20 -10 40 85 -2 5 20 10 ns ns ns ns ns 3 16-15 -2 -1 160 -2 2 1 175 5 ns ns ns ns 2, 3 4 5 16-15 16-16 4 4 20 20 ns ns 1, CL = 50 pF 1, CL = 50 pF 16-14 16-14
4 5
16-16
Low Speed Source (Note 8) t108 USBPx+, USBPx- Driver Rise Time 75 300 ns ns ns ns 1, 6 CL = 50 pF CL = 350 pF 1,6 CL = 50 pF CL = 350 pF 2, 3 4 5 3 16-15 16-14
t109
USBPx+, USBPx- Driver Fall Time Source Differential Driver Jitter
75
300
16-14
t110 t111 t112 t113
To Next Transition For Paired Transitions Source EOP Width Differential to SE0 Transition Skew Receiver Data Jitter Tolerance To Next Transition For Paired Transitions EOP Width: Must reject as EOP EOP Width: Must accept as EOP Differential to SE0 Transition Skew
-2 -1 160 -2 -20 -10 40 85 -2
2 1 175 5 20 10
ns ns ns ns ns ns ns ns
16-15 16-16
t114 t115
4 5
16-16
5
ns
NOTES: 1. Driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at maximum 2. Timing difference between the differential data signals 3. Measured at crossover point of differential data signals 4. Measured at 50% swing point of data signals 5. Measured from last crossover point to 50% swing point of data line at leading edge of EOP 6. Measured from 10% to 90% of the data signal 7. Full Speed Data Rate has minimum of 11.97 Mbps and maximum of 12.03 Mbps 8. Low Speed Data Rate has a minimum of 1.48 Mbps and a maximum of 1.52 Mbps
16-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Table 16-13. IOAPIC Bus Timing
Sym t120 t121 t122 Parameter APICCD[1:0]# Valid Delay from APICCLK Rising APICCD[1:0]# Setup Time to APICCLK Rising APICCD[1:0]# Hold Time from APICCLK Rising Min 3.0 8.5 3.0 Max 12.0 Units ns ns ns Notes Fig 16-3 16-4 16-4
Table 16-14. SMBus Timing
Sym t130 t131 t132 t133 t134 t135 t136 t137 t138 Parameter Bus Tree Time Between Stop and Start Condition Hold Time after (repeated) Start Condition. After this period, the first clock is generated. Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Device Time Out Cumulative Clock Low Extend Time (slave device) Cumulative Clock Low Extend Time (master device) Min 4.7 4.0 4.7 4.0 300 250 25 35 25 10 Max Units us us us us ns ns ms ms ms 1 2 3 16-18 16-18 Notes Fig 16-17 16-17 16-17 16-17 16-17 16-17
NOTES: 1. A device will time out when any clock low exceeds this value. 2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop.
Table 16-15. AC’97 Timing
Sym t140 t141 t142 Parameter ACSDIN[0:1] Setup to Falling Edge of BITCLK ACSDIN[0:1] Hold from Falling Edge of BITCLK ACSYNC, ACSDOUT valid delay from rising edge of BITCLK Min 15 5 15 Max Units ns ns ns 16-3 Notes Fig
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-13
Electrical Characteristics
Table 16-16. LPC Timing
Sym t150 t151 t152 t153 t154 t155 t156 t157 Parameter LAD[3:0] Valid Delay from PCICLK Rising LAD[3:0] Output Enable Delay from PCICLK Rising LAD[3:0] Float Delay from PCICLK Rising LAD[3:0] Setup Time to PCICLK Rising LAD[3:0] Hold Time from PCICLK Rising LDRQ[1:0]# Setup Time to PCICLK Rising LDRQ[1:0]# Hold Time from PCICLK Rising LFRAME# Valid Delay from PCICLK Rising 7 0 12 0 2 12 Min 2 2 28 Max 11 Units ns ns ns ns ns ns ns ns Notes Fig 16-3 16-7 16-5 16-4 16-4 16-4 16-4 16-3
Table 16-17. Miscellaneous Timings
Sym t160 t161 t162 t163 t164 t165 Parameter SERIRQ Setup Time to PCICLK Rising SERIRQ Hold Time from PCICLK Rising RI#, EXTSMI#, GPI, USB Resume Pulse Width SPKR Valid Delay from OSC Rising SERR# Active to NMI Active IGNNE# Inactive from FERR# Inactive Min 7 0 2 200 200 230 Max Units ns ns RTCCLK ns ns ns Notes Fig 16-4 16-4 16-6 16-3
Table 16-18. Power Sequencing and Reset Signal Timings
Sym t170 t171 t172 t173 (ICH2) t173 (ICH2-M) t174 t175 (ICH2) t175a (ICH2-M) t175b (ICH2-M) t175c (ICH2-M) Parameter VccRTC active to RTCRST# inactive V5RefSus active to VccSus3_3, VccSus1_8 active VccRTC supply active to VccSus supplies active VccSus supplies active to RSM_PWROK active, RSMRST# inactive VccSus supplies active to RSMRST# inactive V5Ref active to Vcc3_3, Vcc1_8 active VccSus supplies active to Vcc supplies active VccSus supplies active to VccLAN supplies active VccLAN supplies active to LAN_PWROK active VccLAN supplies active to Vcc supplies active Min 5 0 0 10 5 0 0 0 10 0 Max Units ms ms ms ms ms ms ms ms ms ms 1, 2 3 3 1, 2 3 Notes Fig 16-18, 16-19 16-18, 16-19 16-18, 16-19 16-18, 16-21 16-19 16-22 16-18, 16-19 16-18 16-19 16-19 16-20 16-19
16-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Table 16-18. Power Sequencing and Reset Signal Timings (Continued)
Sym t176 (ICH2) t176 (ICH2-M) Parameter Vcc supplies active to PWROK, VRMPWRGD active Min 10 Max Units ms Notes Fig 16-18, 16-21, 16-25 16-19 16-20 16-22 16-18, 16-21 16-25 16-18 16-20 16-22 16-18, 16-19 16-21, 16-22 16-25, 16-26
Vcc supplies active to PWROK, VGATE active
10
-
ms
t177
PWROK, VRMPWRGD active to SUS_STAT# inactive PWROK, VGATE active to SUS_STAT# inactive
32
34
RTCCLK
t177
32
34
RTCCLK
t178
SUS_STAT# inactive to PCIRST# inactive
1
3
RTCCLK
t179 t180
AC_RST# active low pulse width AC_RST# inactive to BIT_CLK startup delay
1 162.8
us ns
NOTES: 1. The V5Ref supply must power up before or simultaneous with its associated 3.3V supply, and must power down simultaneous with or after the 3.3V supply. See Section 2.20.4 for details. 2. The associated 3.3V and 1.8V supplies are assumed to power up or down together. The difference between the levels of the 3.3V and 1.8V supplies must never be greater than 2.0V. 3. 82801BA ICH2: The VccSus supplies must never be active while the VccRTC supply is inactive. Likewise, the Vcc supplies must never be active while the VccSus supplies are inactive. 4. 82801BAM ICH2-M: The VccSus supplies must never be active while the VccRTC supply is inactive. Likewise, the Vcc or VccLAN supplies must never be active while the VccSus supplies are inactive, and the Vcc supplies must never be active while the VccLAN supplies are inactive.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-15
Electrical Characteristics
Table 16-19. Power Management Timings
Sym t181 t182 t183 t184 (ICH2) t184 (ICH2-M) Parameter VccSus active to SLP_S3#, SLP_S5#, SUS_STAT# and PCIRST# active RSMRST# inactive to SUSCLK running, SLP_S3#, SLP_S5# inactive Vcc active to STPCLK#, CPUSLP#, inactive, and processor Frequency Strap signals high Vcc active to STPCLK#, CPUSLP#, STP_CPU#, STP_PCI#, SLP_S1, C3_STAT# inactive, and CPU Frequency Strap signals high PWROK and VRMPWRGD active to SUS_STAT# inactive and processor Frequency Straps latched to Strap Values Processor Reset Complete to Frequency Strap signals unlatched from Strap Values 32 Min Max 50 110 50 Units ns ms ns 7 Notes Fig 16-21, 16-22 16-21, 16-22 16-21, 16-25 16-20 16-22 16-21, 16-22 16-21, 16-22 16-23, 16-24 16-25, 16-26 16-25, 16-25 4 16-23, 16-26, 16-28 16-23, 16-26, 16-28 4 16-23 16-23, 16-25 1 16-25 16-23, 16-26, 16-28 16-23, 16-26, 16-25 1 1 16-23, 16-26, 16-23, 16-26, 16-23, 16-26, 16-25, 16-26
50
ns
t185
34
RTCCLK
1
t186
7
9
CLK66
2
t187
STPCLK# active to Stop Grant cycle
N/A
N/A
3
t188 (ICH2) t188a (ICH2-M) t188b (ICH2-M) t189 (ICH2) t190 t192 (ICH2) t192a (ICH2-M) t192b (ICH2-M) t193 (ICH2) t193a (ICH2-M) t193b (ICH2-M) t193c (ICH2-M) t194
Stop Grant cycle to CPUSLP# active
60
63
PCICLK
4
Stop Grant cycle to C3_STAT# active
0
6
PCICLK
C3_STAT# active to CPUSLP# active
2.8
us
S1 Wake Event to CPUSLP# inactive CPUSLP# inactive to STPCLK# inactive CPUSLP# active to SUS_STAT# active
1 204 2
25 237 4
PCICLK us RTCCLK
CPUSLP# active to STP_CPU# active
16
PCICLK
4
STP_CPU# active to SUS_STAT# active SUS_STAT# active to PCIRST# active SUS_STAT# active to STP_PCI# active STP_PCI# active to SLP_S1# active SLP_S1# active to PCIRST# active, STP_PCI# inactive, SLP_S1# inactive, and STP_CPU# inactive PCIRST# active to SLP_S3# active
2 9 2 2
4 15 4 4
RTCCLK RTCCLK RTCCLK RTCCLK 1
1
5
7
RTCCLK
1
1
2
RTCCLK
1
16-16
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Table 16-19. Power Management Timings
Sym t195 t196 t196a t197 t198 t198a (ICH2-M) t199 (ICH2-M) t200 (ICH2-M) t201 (ICH2-M) t203 (ICH2-M) t204 t205 t206 t207 (ICH2-M) t208 (ICH2-M) Parameter SLP_S3# active to SLP_S5# active SLP_S3# active to VRMPWRGD (VRMPWRGD / VGATE for ICh2-M) inactive SLP_S3# active to PWROK PWROK, VRMPWRGD inactive to Vcc supplies inactive Wake Event to SLP_S3#, SLP_S5# inactive Wake Event to SLP_S1# inactive SLP_S1# inactive to STP_CPU#, STP_PCI# inactive STP_CPU#, STP_PCI# inactive to SUS_STAT# inactive SUS_STAT# inactive to CPU_SLP# inactive STPCLK# inactive to C3_STAT# inactive Processor I/F signals latched prior to STPCLK# active Break Event to STPCLK# inactive STPCLK# inactive to processor I/F signals unlatched Break Event to STP_CPU# inactive STP_CPU# inactive to CPU_SLP# inactive Min 1 0 100 20 1 1 3 7 2 0 0 30 240 0 30 20 20 6 10 4 15 4 3120 1880 8 45 Max 2 Units RTCCLK ms us ns RTCCLK RTCCLK ms ms PCICLK ns CLK66 ns ns PCICLK us 4 2 4 1 1 Notes 1, 6 5 Fig 16-25, 16-26 16-25, 16-26 16-25, 16-26 16-25, 16-26 16-25, 16-26 16-23, 16-23, 16-23, 16-23, 16-23, 16-28 16-27 16-27 16-27 16-28 16-28
NOTES: 1. These transitions are clocked off the internal RTC. One RTC clock is approximately 32 us. 2. This transition is clocked off the 66 MHz CLK66. One CLK66 is approximately 15 ns. 3. The ICH2 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing for this cycle getting to the ICH2 is dependant on the processor and the memory controller. 4. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns. 5. The ICH2 has no maximum timing requirement for this transition. It is up to the system designer to determine if the SLP_S3# and SLP_S5# signals are used to control the power planes. 6. If the transition to S5 is due to Power Button Override, SLP_S3# and SLP_S5# are asserted together following timing t194 (PCIRST# active to SLP_S3# and SLP_S5# active). 7. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-17
Electrical Characteristics
16.5
Timing Diagrams
Figure 16-1. Clock Timing
Period High Time 2.0V 0.8V Low Time Fall Time Rise Time
Figure 16-2. Valid Delay From Rising Clock Edge
Clock
1.5V
Valid Delay
Output
VT
Figure 16-3. Setup And Hold Times
Clock
1.5V
Setup Time
Hold Time
Input
VT
VT
Figure 16-4. Float Delay
Input
VT
Float Delay Output
16-18
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Figure 16-5. Pulse Width
Pulse Width
VT
VT
Figure 16-6. Output Enable Delay
Clock
1.5V
Output Enable Delay
Output
VT
Figure 16-7. IDE PIO Mode
CLK66 t61
t60 t75 DIOx#
t76
t69 DD[15:0] Write write data t71 t70 DD[15:0] Read read data
t69
t73 t72 IORDY sample point
t74
t62,t63 DA[2:0], CS1#, CS3#
t64
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-19
Electrical Characteristics
Figure 16-8. IDE Multiword DMA
CLK66 t67 DDREQ[1:0] t65 DDACK[1:0] t60 t75 DIOx# t61 t76 t68
t70 DD[15:0] Read
t71 Read Data
Read Data
t69 DD[15:0] Write
t69 Write Data Write Data
id d d
Figure 16-9. Ultra ATA Mode (Drive Initiating a Burst Read)
DMARQ (drive) t91
DMACK# (host) t89 STOP (host) t89 DMARDY# (host)
STROBE (drive)
DD[15:0]
DA[2:0], CS[1:0]
16-20
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Figure 16-10. Ultra ATA Mode (Sustained Burst)
t82 t81 t85 STROBE @ sender t86 t86 t86 t81 t85
Data @ sender
t83 STROBE @ receiver t84 t84
t83
t84
Data @ receiver
Figure 16-11. Ultra ATA Mode (Pausing a DMA Burst)
t90 STOP (host)
DMARDY#
STROBE
DATA
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-21
Electrical Characteristics
Figure 16-12. Ultra ATA Mode (Terminating a DMA Burst)
DMARQ (drive)
t88 DMACK# (host)
t91
STOP (host)
DMARDY# (drive) t87 Strobe (host)
DATA (host)
CRC
Figure 16-13. USB Rise and Fall Times
Rise Time CL Differential Data Lines 10% CL tR tF 10% 90% Fall Time 90%
Full Speed: 4 to 20 ns at C 0 pF =5 L
C Low Speed: 75 ns at= 50 pF, 300 ns at = 350 pF LC L
Figure 16-14. USB Jitter
Tperiod Crossover Points
Differential Data Lines
Consecutive Transitions Paired Transitions
16-22
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Figure 16-15. USB EOP Width
Tperiod Data Crossover Level
Differential Data Lines
EOP Width
Figure 16-16. SMBus Transaction
t19 t20 t21 SMBCLK t131 t134 t135 t132 t18 t133
SMBDATA
t130
Figure 16-17. SMBus Time-out
Start t137 CLK ack t138 SMBCLK t138 CLK ack Stop
SMBDATA
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-23
Electrical Characteristics
Figure 16-18. Power Sequencing and Reset Signal Timings (82801BA ICH2 only)
PWROK, VRMPWRGD Vcc3_3, Vcc1_8, V_CPU_IO V5Ref RSMRST#, RSM_PWROK VccSus3_3, VccSus1_8 T173 T172 T171 V5RefSus RTCRST# T170 VccRTC
ich2_powerup_reset_DT.vsd
T176 T175 T174
Figure 16-19. Power Sequencing and Reset Signal Timings (82801BAM ICH2-M only)
PWROK, VGATE Vcc3_3, Vcc1_8, V_CPU_IO V5Ref T175b LAN_PWROK VccLAN3_3, VccLAN1_8 RSMRST# VccSus3_3, VccSus1_8 T173 T172 T171 V5RefSus RTCRST# T170 VccRTC
ICH2_Powerup_Reset_MO.vst
T175c
T176 T174
T175a
16-24
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Figure 16-20. 1.8V/3.3V Power Sequencing
V 3.3
1.8 Voltage
V V < 2.0V
Time
S
t
2
Figure 16-21. G3 (Mechanical Off) to S0 Timings (82801BA ICH2 only)
System State
Hub interface "CPU Reset Complete" message STPCLK#, CPUSLP#
G3
G3
S5
S5
S0
S0 state
T186 T184
Frequency Straps T185 PCIRST# T181 SUS_STAT# PWROK, VRMPWRGD T176 T177 T178
Strap Values
Normal Operation
Vcc
SLP_S3# SLP_S5# T181 SUSCLK RSMRST#, RSM_PWROK T173 VccSus
ICH2_G3_S0_timing_DT1.vst
T183
Running
T182
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-25
Electrical Characteristics
Figure 16-22. G3 (Mechanical Off) to S0 Timings (82801BAM ICH2-M only)
System State
Hub interface "CPU Reset Complete" message
STPCLK#, CPUSLP#, STP_CPU#, STP_PCI#, SLP_S1#, C3_STAT#
Main Battery Removed (G3)
G3
S5
S5
S0
S0 state
T186 T184
Frequency Straps T185 PCIRST# T181 SUS_STAT# PWROK, VGATE, LAN_PWROK Vcc, VccLAN SLP_S3# SLP_S5# T181 SUSCLK T182 RSMRST# T173 VccSus T183
T175b / T176
Strap Values
Normal Operation
T178
T177
Running
ICH2 G3 S0 timing MO vsd
Figure 16-23. S0 to S1 to S0 Timings (82801BA ICH2 only)
STATE
S0
S0
S1
S1
S1
S0
S0
STPCLK# PCI Stop Grant Cycle T187 CPUSLP# T188 Wake Event
ich2_S0_S1D_timing.vsd
T190
T189
16-26
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Figure 16-24. S0 to S1 to S0 Timings (82801BAM ICH2-M only)
STATE S0 S0 S1 S1 S1 S0 S0
STPCLK# PCI Stop Grant Cycle
T187
T190 T203
T188a
C3_STAT#
CPUSLP#
T188b
T201
STP_CPU#
T192a
T199 SUS_STAT#
T192b
T200
STP_PCI#
T193a
SLP_S1#
T193b
T198a
Wake Event
Figure 16-25. S0 to S5 to S0 Timings (82801BA ICH2 only)
S0 S0 S3 S3 S4/S5 S3/S4/S5 S0
S0
STPCLK# Stop Grant C ycle T 187 C PU SLP# T 188 SUS_ST AT # T 192 T 177 PCIR ST # T 193 SLP_S3#
T194
T 184
T 178
T 198 SLP_S5# T 195 W ake Event
V RM PW R G D T 196 T 176 PW R OK T 196a T 176 Vcc T 197
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-27
Electrical Characteristics
Figure 16-26. S0 to S5 to S0 Timings (82801BAM ICH2-M only)
S0 S0 S3 S3 S4/S5 S3/S4/S5 S0
S0
STPC LK# Stop G rant C ycle C 3_ST AT# T 187
T1 88 a
T 184
C PU SLP#
T1 88 b
STP_C PU #
T1 92 a
T 177
T1 92 b
SUS_STAT #
SLP_S1#
T1 93 a
STP_PCI#
T1 93 b
T 178
PCIR ST #
T1 93 c
SLP_S3#
T1 94
T 198 T 195
SLP_S5# W ake Event
VG AT E T 196 T 176 PW R O K T 196a T 176 Vcc T 197
Figure 16-27. C0 to C2 to C0 Timings
CPU I/F Signals STPCLK# Break Event
T204 T205 T206
ICH2 C0 C2 Ti i d
Unlatched
Latched
Unlatched
16-28
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Electrical Characteristics
Figure 16-28. C0 to C3 to C0 Timings (82801BAM ICH2-M only)
CPU I/F Unlatched Signals STPCLK# PCI Stop Grant Cycle C3_STAT#
T188a T203 T204 T190 T206
Latched
Unlatched
CPU_SLP#
T188b T208
STP_CPU# Break Event
T192a T207
ICH2_C0_C3_Timing.vsd
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-29
Electrical Characteristics
This page is intentionally left blank.
16-30
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Testability
Testability
17.1 Test Mode Description
17
The ICH2 supports two types of test modes, a tri-state test mode and a XOR Chain test mode. Driving RTCRST# low for a specific number of PCI clocks while PWROK is high activates a particular test mode as described in Table 17-1. Note:
.
RTCRST# can be driven low any time after PCIRST# is inactive.
Table 17-1. Test Mode Selection
Number of PCI Clocks RTCRST# driven low after PWROK active 24 Test Mode No Test Mode Selected XOR Chain 1 XOR Chain 2 XOR Chain 3 XOR Chain 4 All “Z” Reserved. DO NOT ATTEMPT No Test Mode Selected
Figure 17-1 illustrates the entry into a test mode. A particular test mode is entered upon the rising edge of the RTCRST# after being asserted for a specific number of PCI clocks while PWROK is active. To change test modes, the same sequence should be followed again. To restore the ICH2 to normal operation, execute the sequence with RTCRST# being asserted so that no test mode is selected as specified in Table 17-1. Figure 17-1. Test Mode Entry (XOR Chain Example)
RSMRST#
PWROK RTCRST# Other Signal Outputs N Number of PCI Clocks Test Mode Entered
All Output Signals Tri-Stated
XOR Chain Output Enabled
82801BA ICH2 and 82801BAM ICH2-M Datasheet
17-1
Testability
17.2
Tri-state Mode
When in the tri-state mode, all outputs and bi-directional pin are tri-stated, including the XOR Chain outputs.
17.3
XOR Chain Mode
In the ICH2, provisions for Automated Test Equipment (ATE) board level testing are implemented with XOR Chains. The ICH2 signals are grouped into four independent XOR chains which are enabled individually. When an XOR chain is enabled, all output and bi-directional buffers within that chain are tri-stated, except for the XOR chain output. Every signal in the enabled XOR chain (except for the XOR chain’s output) functions as an input. All output and bi-directional buffers for pins not in the selected XOR chain are tri-stated. Figure 17-2 is a schematic example of XOR chain circuitry. Table 17-3 - Table 17-6 list each XOR chain pin ordering, with the first value being the first input and the last value being the XOR chain output. Table 17-7 lists the signal pins not included in any XOR chain.
Figure 17-2. Example XOR Chain Circuitry
Vcc
XOR Chain Output Input Pin 1 Input Pin 2 Input Pin 3 Input Pin 4 Input Pin 5 Input Pin 6
17.3.1
XOR Chain Testability Algorithm Example
XOR chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 17-2.
Table 17-2. XOR Test Pattern Example
Vector 1 2 3 4 5 6 7 Input Pin 1 0 1 1 1 1 1 1 Input Pin 2 0 0 1 1 1 1 1 Input Pin 3 0 0 0 1 1 1 1 Input Pin 4 0 0 0 0 1 1 1 Input Pin 5 0 0 0 0 0 1 1 Input Pin 6 0 0 0 0 0 0 1 XOR Output 1 0 1 0 1 0 1
17-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Testability
In this example, Vector 1 applies all "0s" to the chain inputs. The outputs being non-inverting, will consistently produce a "1" at the XOR output on a good board. One short to Vcc (or open floating to Vcc) will result in a "0" at the chain output, signaling a defect. Likewise, applying Vector 7 (all "1s") to the chain inputs (given that there are an even number of input signals in the chain), will consistently produce a "1" at the XOR chain output on a good board. One short to Vss (or open floating to Vss) will result in a "0" at the chain output, signaling a defect. It is important to note that the number of inputs pulled to "1" will affect the expected chain output value. If the number of chain inputs pulled to "1" is even, then expect "1" at the output. If the number of chain inputs pulled to "1" is odd, expect "0" at the output. Continuing with the example in Table 17-2, as the input pins are driven to "1" across the chain in sequence, the XOR Output will toggle between "0" and "1." Any break in the toggling sequence (e.g., "1011") will identify the location of the short or open.
17.3.1.1
Test Pattern Consideration for XOR Chain 4
When the ICH2 is operated with the Hub Interface in "Normal" mode (See Section 2.20.1), the HL_STB and HL_STB# signals must always be driven to complementary logic levels. For example, if a "1" is driven on HL_STB, then a "0" must be driven on HL_STB# and vice versa. This will need to be considered in applying test patterns to this chain. When the ICH2 is operated with the Hub Interface in "Enhanced" mode there are no restrictions on the values that may be driven onto the HL_STB and HL_STB# signals.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
17-3
Testability
Table 17-3. XOR Chain #1 (RTCRST# Asserted for 4 PCI Clocks while PWROK Active)
Pin Name LAN_TXD0 LAN_TXD1 LAN_TXD2 LAN_RXD0 LAN_RXD1 LAN_RXD2 EE_DOUT EE_SHCLK EE_CS EE_DIN GPIO21 (ICH2) C3_STAT#/ GPIO21 (ICH2-M) GPIO16 / GNTA# GPIO1 / REQB# / REQ5# GPIO17 / GNTB# / GNT5# GNT1# GNT0# GPIO0 / REQA# PIRQH# GPIO4 / PIRQG# GPIO3 / PIRQF# PIRQE# PIRQD# PIRQA# PIRQB# PIRQC# REQ4# GNT4# REQ0# REQ1# L1 PAR W2 Ball # F3 F2 F1 G2 G1 H1 J4 J3 K4 K3 Notes Top of XOR Chain 2nd signal in XOR Pin Name REQ2# GNT2# GNT3# AD26 AD30 AD28 AD18 AD22 AD16 STOP# Ball # T1 R4 T2 U1 T3 T4 V1 U3 V2 W1 Notes
L2 L3 L4 M1 M2 M3 M4 N1 N2 N3 N4 P1 P2 P3 P4 R1 R2 R3
FRAME# AD20 AD15 TRDY# AD11 AD13 AD4 AD9 C/BE0# AD2 AD6 AD3 AD0 AD5 AD10 AD7
V3 U4 Y1 V4 W3 Y2 W4 Y3 AA3 Y4 AB3 W5 AA4 Y5 W6 AA5 Last in XOR Chain XOR Chain #1
AC_SDIN1
W22
OUTPUT
17-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Testability
Table 17-4. XOR Chain #2 (RTCRST# Asserted for 5 PCI clocks while PWROK Active)
Pin Name AD1 AD12 AD8 SERR# AD14 PERR# C/BE1# DEVSEL# PLOCK# C/BE2# IRDY# AD17 AD19 AD23 AD21 C/BE3# AD25 AD27 AD29 AD31 REQ3# GPIO6 (ICH2) AGPBUSY# (ICH2-M) GPIO7 LFRAME# / FWH4 LAD3 / FWH3 FS0 LAD0 / FWH0 LAD1 / FWH1 LAD2 / FWH2 THRM# LDRQ0# Y11 AA11 AB11 AB12 AA12 Y12 W12 AB13 AA13 TP0 (ICH2) Y13 BATLOW# (ICH2-M) U20 OUTPUT USBP2P USBP2N USBP3P USBP3N OC0# OC1# OC2# OC3# W18 Y19 AB20 AA20 W19 Y20 Y21 W20 XOR Chain #2 Ball # AB4 Y6 AB5 W7 AA6 Y7 AB6 AB7 AA7 Y8 W8 AA8 AB8 Y9 W9 AA9 AB9 W10 Y10 AA10 AB10 Notes Top of XOR Chain 2nd signal in XOR Pin Name LDRQ1# GPIO27 GPIO28 GPIO8 GPIO12 GPIO13 PCIRST# PME# GPIO25 SMBCLK SMBDATA SMBALERT# / GPIO11 RI# SLP_S5# SUSSTAT# SLP_S3# SUSCLK USBP0P USBP0N USBP1P USBP1N Ball # W13 AB14 AA14 Y14 W14 AB15 AA15 Y15 W15 AB16 AA16 AB17 AA17 AB18 Y17 W16 AA18 W17 Y18 AB19 AA19 Notes
82801BA ICH2 and 82801BAM ICH2-M Datasheet
17-5
Testability
Table 17-5. XOR Chain #3 (RTCRST# Asserted for 6 PCI Clocks while PWROK Active)
Pin Name AC_SDIN0 PWRBTN# SMLINK0 SMLINK1 AC_SDIN1 TP0 (ICH2) BATLOW# (ICH2-M) AC_RST# GPIO24 (ICH2) CLKRUN# (ICH2-M) AC_SDOUT AC_SYNC FERR# APICD0 APICD1 SERIRQ SPKR PDD6 PDD7 PDD8 PDD9 PDD5 PDD10 PDD4 PDD11 PDD13 PDD3 PDD12 PDD1 PDD2 V21 P21 P19 R22 P22 N19 N21 N22 M21 M22 L22 L21 L20 K22 K21 K20 J20 J22 J21 H22 J19 RI# AA17 IRQ14 SDD6 PIORDY PDCS1# PDIOR# PDA0 SDD8 SDD9 PDA1 SDD7 SDD5 SDD10 SDD4 PDCS3# SDD11 SDD2 SDD12 SDD3 F21 D22 G20 E21 G19 F20 D21 C22 F19 E20 C21 D20 C20 E19 B20 D19 C19 A20 Last in XOR Chain XOR Chain #3 OUTPUT U20 V22 PDDACK# PDA2 F22 E22 Ball # Y22 W21 U19 V20 W22 Notes Top of XOR Chain 2nd signal in XOR Pin name PDD14 PDD0 PDDREQ PDIOW# PDD15 Ball # H21 H19 G22 G21 H20 Notes
17-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Testability
Table 17-6. XOR Chain #4 (RTCRST# Asserted for 7 PCI Clocks while PWROK Active)
Pin Name SDD13 SDD1 SDD14 SDD0 SDIOR# SDDREQ SDIOW# SDD15 SDA1 SDDACK# IRQ15 SIORDY SDA2 SDCS3# SDA0 SDCS1# VRMPWRGD (ICH2) VRMPWRGD / VGATE (ICH2-M) GPIO18 (ICH2) STP_PCI# (ICH2-M) GPIO19 (ICH2) SLP_S1# (ICH2-M) GPIO20 (ICH2) STP_CPU# (ICH2-M) GPIO22 (ICH2) CPUPERF# (ICH2-M) GPIO23 (ICH2) SSMUXSEL# (ICH2-M) A20GATE RCIN# CPUPWRGD A14 C13 B13 A13 OC0# W19 HLCOMP A3 Last in XOR Chain XOR Chain #4 OUTPUT B14 HL11 C5 C14 HL0 A4 D14 HL1 B5 A15 HL2 A5 Ball # A19 B19 C18 D18 D17 B18 C17 A18 D16 B17 C16 A17 B16 D15 A16 C15 Notes Top of XOR Chain 2nd signal in XOR Pin Name INIT# SMI# CPUSLP# IGNNE# NMI INTR A20M# STPCLK# HL7 HL5 HL6 HL4 HL8 HL10 HL_STB# HL_STB Ball # C12 B12 A12 A11 B11 C11 D11 C10 A9 A8 B8 B7 C8 C7 A7 A6 See Section 17.3.1.1 See Section 17.3.1.1 Notes
B15
HL9
C6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
17-7
Testability
Table 17-7. Signals Not in XOR Chain
Pin Name RSMRST# PWROK RTCX1 RTCX2 VBIAS RTCRST# Ball # R21 R20 U22 T22 T21 T20 Notes Pin Name CLK14 CLK48 CLK66 APICCLK PCICLK INTRUDER# RSM_PWROK (ICH2) LAN_PWROK (ICH2-M) Ball # M19 P20 D4 N20 W11 T19 Notes
LAN_CLK
G3
Y16
AC_BITCLK
R19
17-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
I/O Register Index
I/O Register Index
Table A-1. ICH2 Fixed I/O Registers
Register Name Channel 0 DMA Base & Current Address Register Channel 0 DMA Base & Current Count Register Channel 1 DMA Base & Current Address Register Channel 1 DMA Base & Current Count Register Channel 2 DMA Base & Current Address Register Channel 2 DMA Base & Current Count Register Channel 3 DMA Base & Current Address Register Channel 3 DMA Base & Current Count Register Channel 0–3 DMA Command Register Channel 0–3 DMA Status Register Channel 0–3 DMA Write Single Mask Register Channel 0–3 DMA Channel Mode Register Channel 0–3 DMA Clear Byte Pointer Register Channel 0–3 DMA Master Clear Register Channel 0–3 DMA Clear Mask Register Channel 0–3 DMA Write All Mask Register Aliased at 00h–0Fh Master PIC ICW1 Init. Cmd Word 1 Register Master PIC OCW2 Op Ctrl Word 2 Register Master PIC OCW3 Op Ctrl Word 3 Register 20h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h–1Fh Port 00h 01h 02h 03h 04h 05h 06h 07h EDS Section and Location
A
Section 9.2.1, “DMABASE_CA—DMA Base and Current Address Registers” on page 9-24 Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers” on page 9-25 Section 9.2.1, “DMABASE_CA—DMA Base and Current Address Registers” on page 9-24 Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers” on page 9-25 Section 9.2.1, “DMABASE_CA—DMA Base and Current Address Registers” on page 9-24 Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers” on page 9-25 Section 9.2.1, “DMABASE_CA—DMA Base and Current Address Registers” on page 9-24 Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers” on page 9-25 Section 9.2.4, “DMACMD—DMA Command Register” on page 9-26 Section 9.2.5, “DMASTS—DMA Status Register” on page 9-26 Section 9.2.6, “DMA_WRSMSK—DMA Write Single Mask Register” on page 9-27 Section 9.2.7, “DMACH_MODE—DMA Channel Mode Register” on page 9-27 Section 9.2.8, “DMA Clear Byte Pointer Register” on page 9-28 Section 9.2.9, “DMA Master Clear Register” on page 9-28 Section 9.2.10, “DMA_CLMSK—DMA Clear Mask Register” on page 9-28 Section 9.2.11, “DMA_WRMSK—DMA Write All Mask Register” on page 9-29
08h
Section 9.4.2, “ICW1—Initialization Command Word 1 Register” on page 9-34 Section 9.4.8, “OCW2—Operational Control Word 2 Register” on page 9-37 Section 9.4.9, “OCW3—Operational Control Word 3 Register” on page 9-38
82801BA ICH2 and 82801BAM ICH2-M Datasheet
A-1
I/O Register Index
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name Master PIC ICW2 Init. Cmd Word 2 Register Master PIC ICW3 Init. Cmd Word 3 Register Master PIC ICW4 Init. Cmd Word 4 Register Master PIC OCW1 Op Ctrl Word 1 Register Aliased at 20h–21h Aliased at 20h–21h Aliased at 20h–21h Aliased at 20h–21h Aliased at 20h–21h Aliased at 20h–21h Aliased at 20h–21h Aliased at 20h–21h Counter 0 Interval Time Status Byte Format Counter 0 Counter Access Port Register Counter 1 Interval Time Status Byte Format Counter 1 Counter Access Port Register Counter 2 Interval Time Status Byte Format Counter 2 Counter Access Port Register Timer Control Word Register Timer Control Word Register Read Back Counter Latch Command Aliased at 40h–43h NMI Status and Control Register NMI Enable Register Real-Time Clock (Standard RAM) Index Register Real-Time Clock (Standard RAM) Target Register Extended RAM Index Register Extended RAM Target Register 50h–53h 61h 70h Section 9.7.1, “NMI_SC—NMI Status and Control Register” on page 9-51 Section 9.7.2, “NMI_EN—NMI Enable (and Real Time Clock Index)” on page 9-52 Table 9-7 “RTC (Standard) RAM Bank” on page 9-47 70h Section 9.7.2, “NMI_EN—NMI Enable (and Real Time Clock Index)” on page 9-52 Table 9-7 “RTC (Standard) RAM Bank” on page 9-47 43h 24h–25h 28h–29h 24h–25h 2Ch–2Dh 30h–31h 34h–35h 38h–39h 3Ch–3Dh Section 9.3.2, “SBYTE_FMT—Interval Timer Status Byte Format Register” on page 9-32 Section 9.3.3, “Counter Access Ports Register” on page 9-32 Section 9.3.2, “SBYTE_FMT—Interval Timer Status Byte Format Register” on page 9-32 Section 9.3.3, “Counter Access Ports Register” on page 9-32 Section 9.3.2, “SBYTE_FMT—Interval Timer Status Byte Format Register” on page 9-32 Section 9.3.3, “Counter Access Ports Register” on page 9-32 Section 9.3.1, “TCW—Timer Control Word Register” on page 9-30 Section 9.3.1.1, “RDBK_CMD—Read Back Command” on page 9-31 Section 9.3.1.2, “LTCH_CMD—Counter Latch Command” on page 9-31 21h Port EDS Section and Location Section 9.4.3, “ICW2—Initialization Command Word 2 Register” on page 9-35 Section 9.4.4, “ICW3—Master Controller Initialization Command Word 3 Register” on page 9-35 Section 9.4.6, “ICW4—Initialization Command Word 4 Register” on page 9-36 Section 9.4.7, “OCW1—Operational Control Word 1 (Interrupt Mask) Register” on page 9-36
40h
41h
42h
71h 72h 73h
A-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
I/O Register Index
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name Port EDS Section and Location Aliased if U128E bit in RTC Configuration Register is enabled Section 9.1.24, “RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)” on page 9-14 Aliased to 70h–71h if U128E bit in RTC Configuration Register is enabled Section 9.1.24, “RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)” on page 9-14 Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on page 9-25 Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on page 9-25 Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on page 9-25
Aliased at 70h–71h
74h–75h
Aliased at 72h–73h or 70h–71h
76h–77h
Channel 2 DMA Memory Low Page Register Channel 3 DMA Memory Low Page Register Channel 1 DMA Memory Low Page Register Reserved Page Registers Channel 0 DMA Memory Low Page Register Reserved Page Register Channel 6 DMA Memory Low Page Register Channel 7 DMA Memory Low Page Register Channel 5 DMA Memory Low Page Register Reserved Page Registers Refresh Low Page Register Aliased at 81h–8Fh Fast A20 and INIT Register Slave PIC ICW1 Init. Cmd Word 1 Register Slave PIC OCW2 Op Ctrl Word 2 Register Slave PIC OCW3 Op Ctrl Word 3 Register Slave PIC ICW2 Init. Cmd Word 2 Register Slave PIC ICW3 Init. Cmd Word 3 Register Slave PIC ICW4 Init. Cmd Word 4 Register Slave PIC OCW1 Op Ctrl Word 1 Register Aliased at A0h–A1h Aliased at A0h–A1h Aliased at A0h–A1h Aliased at A0h–A1h
81h 82h 83h 84h–86h 87h 88h 89h 8Ah 8Bh 8Ch–8Eh 8Fh 91h–9Fh (except 92h) 92h
Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on page 9-25
Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on page 9-25 Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on page 9-25 Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on page 9-25
Section 9.7.3, “PORT92—Fast A20 and Init Register” on page 9-52 Section 9.4.2, “ICW1—Initialization Command Word 1 Register” on page 9-34
A0h
Section 9.4.8, “OCW2—Operational Control Word 2 Register” on page 9-37 Section 9.4.9, “OCW3—Operational Control Word 3 Register” on page 9-38 Section 9.4.3, “ICW2—Initialization Command Word 2 Register” on page 9-35
A1
Section 9.4.4, “ICW3—Master Controller Initialization Command Word 3 Register” on page 9-35 Section 9.4.6, “ICW4—Initialization Command Word 4 Register” on page 9-36 Section 9.4.7, “OCW1—Operational Control Word 1 (Interrupt Mask) Register” on page 9-36
A4h–A5h A8h–A9h ACh–ADh B0h–B1h
82801BA ICH2 and 82801BAM ICH2-M Datasheet
A-3
I/O Register Index
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name Advanced Power Management Control Port Register Advanced Power Management Status Port Register Aliased at A0h–A1h Aliased at A0h–A1h Aliased at A0h–A1h Channel 4 DMA Base & Current Address Register Aliased at C0h Channel 4 DMA Base & Current Count Register Aliased at C2h Channel 5 DMA Base & Current Address Register Aliased at C4h Channel 5 DMA Base & Current Count Register Aliased at C6h Channel 6 DMA Base & Current Address Register Aliased at C8h Channel 6 DMA Base & Current Count Register Aliased at CAh Channel 7 DMA Base & Current Address Register Aliased at CCh Channel 7 DMA Base & Current Count Register Aliased at CEh Channel 4–7 DMA Command Register Channel 4–7 DMA Status Register Aliased at D0h Channel 4–7 DMA Write Single Mask Register Aliased at D4h Channel 4–7 DMA Channel Mode Register Aliased at D6h Channel 4–7 DMA Clear Byte Pointer Register Aliased at D8h D1h D4h D5h D6h D7h D8h D9h Section 9.2.8, “DMA Clear Byte Pointer Register” on page 9-28 Section 9.2.7, “DMACH_MODE—DMA Channel Mode Register” on page 9-27 Section 9.2.6, “DMA_WRSMSK—DMA Write Single Mask Register” on page 9-27 Port B2h B3h B4h–B5h B8h–B9h BCh–BDh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh Section 9.2.4, “DMACMD—DMA Command Register” on page 9-26 Section 9.2.5, “DMASTS—DMA Status Register” on page 9-26 Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers” on page 9-25 Section 9.2.1, “DMABASE_CA—DMA Base and Current Address Registers” on page 9-24 Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers” on page 9-25 Section 9.2.1, “DMABASE_CA—DMA Base and Current Address Registers” on page 9-24 Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers” on page 9-25 Section 9.2.1, “DMABASE_CA—DMA Base and Current Address Registers” on page 9-24 Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers” on page 9-25 Section 9.2.1, “DMABASE_CA—DMA Base and Current Address Registers” on page 9-24 EDS Section and Location Section 9.8.2.1, “APM_CNT—Advanced Power Management Control Port Register” on page 9-60 Section 9.8.2.2, “APM_STS—Advanced Power Management Status Port Register” on page 9-60
D0h
A-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
I/O Register Index
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name Channel 4–7 DMA Master Clear Register Aliased at DAh Channel 4–7 DMA Clear Mask Register Aliased at DCh Channel 4–7 DMA Write All Mask Register Aliased at DEh Coprocessor Error Reigster PIO Mode Command Block Offset for Secondary Drive PIO Mode Command Block Offset for Primary Drive PIO Mode Control Block Offset for Secondary Drive PIO Mode Control Block Offset for Primary Drive Master PIC Edge/Level Triggered Register Slave PIC Edge/Level Triggered Register Reset Control Register Port DAh DBh DCh DEh DEh DFh F0h 170h–177h 1F0h–1F7h 376h 3F6h 4D0h 4D1h CF9h Section 9.7.4, “COPROC_ERR—Coprocessor Error Register” on page 9-52 See ATA Specification for detailed register description See ATA Specification for detailed register description See ATA Specification for detailed register description See ATA Specification for detailed register description Section 9.4.10, “ELCR1—Master Controller Edge/Level Triggered Register” on page 9-39 Section 9.4.11, “ELCR2—Slave Controller Edge/Level Triggered Register” on page 9-40 Section 9.7.5, “RST_CNT—Reset Control Register” on page 9-53 Section 9.2.11, “DMA_WRMSK—DMA Write All Mask Register” on page 9-29 Section 9.2.10, “DMA_CLMSK—DMA Clear Mask Register” on page 9-28 EDS Section and Location Section 9.2.9, “DMA Master Clear Register” on page 9-28
NOTE: When the POS_DEC_EN bit is set, additional I/O ports get positively decoded by the ICH2. Refer to through for a listing of these ranges.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
A-5
I/O Register Index
Table A-2. ICH2 Variable I/O Registers
Register Name Offset EDS Section and Location
LAN Control/Status Registers (CSR) may be mapped to either I/O space or memory space. LAN CSR at CSR_IO_BASE + Offset or CSR_MEM_BASE + Offset. CSR_MEM_BASE set in Section 7.1.11, “CSR_MEM_BASE CSR—Memory-Mapped Base Address Register (LAN Controller— B1:D8:F0)” on page 7-5 CSR_IO_BASE set in Section 7.1.12, “CSR_IO_BASE—CSR I/O-Mapped Base Address Register (LAN Controller—B1:D8:F0)” on page 7-5 SCB Status Word SCB Command Word SCB General Pointer PORT EEPROM Control Register MDI Control Register Receive DMA Byte Count Early Receive Interrupt Flow Control Register PMDR General Control General Status 01h–00h 03h–02h 07h–04h OBh–08h 0Fh–0Eh 13h–10h 17h–14h 18h 1Ah–19h 1Bh 1Ch 1Dh Section 7.2.1, “System Control Block Status Word Register” on page 7-11 Section 7.2.2, “System Control Block Command Word Register” on page 7-12 Section 7.2.3, “System Control Block General Pointer Register” on page 7-14 Section 7.2.4, “PORT Register” on page 7-14 Section 7.2.5, “EEPROM Control Register” on page 7-15 Section 7.2.6, “Management Data Interface (MDI) Control Register” on page 7-16 Section 7.2.7, “Receive DMA Byte Count Register” on page 7-16 Section 7.2.8, “Early Receive Interrupt Register” on page 7-17 Section 7.2.9, “Flow Control Register” on page 7-18 Section 7.2.10, “Power Management Driver (PMDR) Register” on page 7-19 Section 7.2.11, “General Control Register” on page 7-19 Section 7.2.12, “General Status Register” on page 7-20
Power Management I/O Registers at PMBASE+Offset PMBASE set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-6 PM1 Status PM1 Enable PM1 Control PM1 Timer Processor Control Level 2 Register General Purpose Event 0 Status General Purpose Event 0 Enables General Purpose Event 1 Status General Purpose Event 1 Enables 00–01h 02–03h 04–07h 08–0Bh 10h–13h 14h 28–29h 2A–2Bh 2C–2D 2E–2F Section 9.8.3.1, “PM1_STS—Power Management 1 Status Register” on page 9-62 Section 9.8.3.2, “PM1_EN—Power Management 1 Enable Register” on page 9-64 Section 9.8.3.3, “PM1_CNT—Power Management 1 Control Register” on page 9-65 Section 9.8.3.4, “PM1_TMR—Power Management 1 Timer Register” on page 9-66 Section 9.8.3.5, “PROC_CNT—Processor Control Register” on page 9-66 Section 9.8.3.6, “LV2—Level 2 Register” on page 9-67 Section 9.8.3.9, “GPE0_STS—General Purpose Event 0 Status Register” on page 9-68 Section 9.8.3.10, “GPE0_EN—General Purpose Event 0 Enables Register” on page 9-70 Section 9.8.3.11, “GPE1_STS—General Purpose Event 1 Status Register” on page 9-71 Section 9.8.3.12, “GPE1_EN—General Purpose Event 1 Enable Register” on page 9-72
A-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
I/O Register Index
Table A-2. ICH2 Variable I/O Registers (Continued)
Register Name SMI# Control and Enable SMI Status Register Monitor SMI Status Device Activity Status Device Trap Enable Bus Address Tracker Bus Cycle Tracker Offset 30–31h 34–35h 40h 44h 48h 4Ch 4Eh EDS Section and Location Section 9.8.3.13, “SMI_EN—SMI Control and Enable Register” on page 9-72 Section 9.8.3.14, “SMI_STS—SMI Status Register” on page 9-74 Section 9.8.3.15, “MON_SMI—Device Monitor SMI Status and Enable Register” on page 9-75 Section 9.8.3.16, “DEVACT_STS—Device Activity Status Register” on page 9-76 Section 9.8.3.17, “DEVTRAP_EN—Device Trap Enable Register” on page 9-77 Section 9.8.3.18, “BUS_ADDR_TRACK—Bus Address Tracker Register” on page 9-78 Section 9.8.3.19, “BUS_CYC_TRACK—Bus Cycle Tracker Register” on page 9-78
TCO I/O Registers at TCOBASE + Offset TCOBASE = PMBASE + 40h PMBASE is set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-6 TCO_RLD: TCO Timer Reload and Current Value TCO_TMR: TCO Timer Initial Value TCO_DAT_IN: TCO Data In TCO_DAT_OUT: TCO Data Out TCO1_STS: TCO Status TCO2_STS: TCO Status TCO1_CNT: TCO Control TCO2_CNT: TCO Control 00h 01h 02h 03h 04h–05h 06h–07h 08h–09h 0Ah–0Bh Section 9.9.2, “TCO1_RLD—TCO Timer Reload and Current Value Register” on page 9-79 Section 9.9.3, “TCO1_TMR—TCO Timer Initial Value Register” on page 9-80 Section 9.9.4, “TCO1_DAT_IN—TCO Data In Register” on page 9-80 Section 9.9.5, “TCO1_DAT_OUT—TCO Data Out Register” on page 9-80 Section 9.9.6, “TCO1_STS—TCO1 Status Register” on page 9-80 Section 9.9.7, “TCO2_STS—TCO2 Status Register” on page 9-82 Section 9.9.8, “TCO1_CNT—TCO1 Control Register” on page 9-83 Section 9.9.9, “TCO2_CNT—TCO2 Control Register” on page 9-83
GPIO I/O Registers at GPIOBASE + Offset GPIOBASE is set in Section 9.1.14, “GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)” on page 9-8 GPIO Use Select GPIO Input/Output Select GPIO Level for Input or Output GPIO Blink Enable GPIO Signal Invert 00–03h 04–07h 0C–0Fh 18–1Bh 2C–2Fh Section 9.10.2, “GPIO_USE_SEL—GPIO Use Select Register” on page 9-87 Section 9.10.3, “GP_IO_SEL—GPIO Input/Output Select Register” on page 9-88 Section 9.10.4, “GP_LVL—GPIO Level for Input or Output Register” on page 9-89 Section 9.10.5, “GPO_BLINK—GPO Blink Enable Register” on page 9-90 Section 9.10.6, “GPI_INV—GPIO Signal Invert Register” on page 9-91
82801BA ICH2 and 82801BAM ICH2-M Datasheet
A-7
I/O Register Index
Table A-2. ICH2 Variable I/O Registers (Continued)
Register Name Offset EDS Section and Location
BMIDE I/O Registers at BM_BASE + Offset BM_BASE is set at Section 10.1.10, “BM_BASE—Bus Master Base Address Register (IDE—D31:F1)” on page 10-4 Command Register Primary Status Register Primary Descriptor Table Pointer Primary Command Register Secondary Status Register Secondary Descriptor Table Pointer Secondary 00h 02h 04h–07h 08h 0Ah 0Ch–0Fh Section 10.2.1, “BMIC[P,S]—Bus Master IDE Command Register” on page 10-11 Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status Register” on page 10-12 Section 10.2.3, “BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register” on page 10-12 Section 10.2.1, “BMIC[P,S]—Bus Master IDE Command Register” on page 10-11 Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status Register” on page 10-12 Section 10.2.3, “BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register” on page 10-12
USB I/O Registers at Base Address + Offset USB Base Address is set at Section 11.1.9, “BASE—Base Address Register (USB—D31:F2/F4)” on page 11-4 USB Command Register USB Status Register USB Interrupt Enable USB Frame Number USB Frame List Base Address USB Start of Frame Modify Port 0, 2 Status/Control Port 1, 3 Status/Control Loop Back Test Data 00h–01h 02h–03h 04h–05h 06h–07h 08h–0Bh 0Ch 10h–11h 12h–13h 18h Section 11.2.1, “USBCMD—USB Command Register” on page 11-8 Section 11.2.2, “USBSTA—USB Status Register” on page 11-11 Section 11.2.3, “USBINTR—Interrupt Enable Register” on page 11-12 Section 11.2.4, “FRNUM—Frame Number Register” on page 11-12 Section 11.2.5, “FRBASEADD—Frame List Base Address” on page 11-13 Section 11.2.6, “SOFMOD—Start of Frame Modify Register” on page 11-13 Section 11.2.7, “PORTSC[0,1]—Port Status and Control Register” on page 11-14 Section 11.2.7, “PORTSC[0,1]—Port Status and Control Register” on page 11-14
SMBus I/O Registers at SMB_BASE + Offset SMB_BASE is set at Section 12.1.9, “SMB_BASE—SMBus Base Address Register (SMBUS—D31:F3)” on page 12-4 Host Status Host Control Host Command Transmit Slave Address Host Data 0 Host Data 1 00h 02h 03h 04h 05h 06h Section 12.2.1, “HST_STS—Host Status Register” on page 12-7 Section 12.2.2, “HST_CNT—Host Control Register” on page 12-8 Section 12.2.3, “HST_CMD—Host Command Register” on page 12-9 Section 12.2.4, “XMIT_SLVA—Transmit Slave Address Register” on page 12-9 Section 12.2.5, “HST_D0—Data 0 Register” on page 12-9 Section 12.2.6, “HST_D1—Data 1 Register” on page 12-9
A-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
I/O Register Index
Table A-2. ICH2 Variable I/O Registers (Continued)
Register Name Block Data Byte Receive Slave Address Receive Slave Data Offset 07h 09h 0Ah EDS Section and Location Section 12.2.7, “BLOCK_DB—Block Data Byte Register” on page 12-10 Section 12.2.8, “RCV_SLVA—Receive Slave Address Register” on page 12-10 Section 12.2.9, “SLV_DATA—Receive Slave Data Register” on page 12-10
AC’97 Audio I/O Registers at NAMBAR + Offset NAMBAR is set at Section 13.1.11, “NABMBAR—Native Audio Bus Mastering Base Address Register (Audio—D31:F5)” on page 13-5 PCM In Buffer Descriptor list Base Address Register PCM In Current Index Value PCM In Last Valid Index PCM In Status Register PCM In Position In Current Buffer PCM In Prefetched Index Value PCM In Control Register PCM Out Buffer Descriptor list Base Address Register PCM Out Current Index Value PCM Out Last Valid Index PCM Out Status Register PCM Out Position In Current Buffer PCM Out Prefetched Index Value PCM Out Control Register Mic. In Buffer Descriptor list Base Address Register Mic. In Current Index Value Mic. In Last Valid Index Mic. In Status Register Mic In Position In Current Buffer Mic. In Prefetched Index Value Mic. In Control Register 00h 04h 05h 06h 08h 0Ah 0Bh 10h 14h 15h 16h 18h 1Ah 1Bh 20h 24h 25h 26h 28h 2Ah 2Bh Section 13.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on page 13-9 Section 13.2.2, “x_CIV—Current Index Value Register” on page 13-10 Section 13.2.3, “x_LVI—Last Valid Index Register” on page 13-10 Section 13.2.4, “x_SR—Status Register” on page 13-11 Section 13.2.5, “x_PICB—Position In Current Buffer Register” on page 13-12 Section 13.2.6, “x_PIV—Prefetched Index Value Register” on page 13-12 Section 13.2.7, “x_CR—Control Register” on page 13-13 Section 13.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on page 13-9 Section 13.2.2, “x_CIV—Current Index Value Register” on page 13-10 Section 13.2.3, “x_LVI—Last Valid Index Register” on page 13-10 Section 13.2.4, “x_SR—Status Register” on page 13-11 Section 13.2.5, “x_PICB—Position In Current Buffer Register” on page 13-12 Section 13.2.6, “x_PIV—Prefetched Index Value Register” on page 13-12 Section 13.2.7, “x_CR—Control Register” on page 13-13 Section 13.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on page 13-9 Section 13.2.2, “x_CIV—Current Index Value Register” on page 13-10 Section 13.2.3, “x_LVI—Last Valid Index Register” on page 13-10 Section 13.2.4, “x_SR—Status Register” on page 13-11 Section 13.2.5, “x_PICB—Position In Current Buffer Register” on page 13-12 Section 13.2.6, “x_PIV—Prefetched Index Value Register” on page 13-12 Section 13.2.7, “x_CR—Control Register” on page 13-13
82801BA ICH2 and 82801BAM ICH2-M Datasheet
A-9
I/O Register Index
Table A-2. ICH2 Variable I/O Registers (Continued)
Register Name Global Control Global Status Codec Access Semaphore Register Offset 2Ch 30h 34h EDS Section and Location Section 13.2.8, “GLOB_CNT—Global Control Register” on page 13-14 Section 13.2.9, “GLOB_STA—Global Status Register” on page 13-15 Section 13.2.10, “CAS—Codec Access Semaphore Register” on page 13-16
AC’97 Modem I/O Registers at MBAR + Offset MBAR is set in Section 14.1.11, “MBAR—Modem Base Address Register (Modem—D31:F6)” on page 14-5 Modem In Buffer Descriptor List Base Address Register Modem In Current Index Value Register Modem In Last Valid Index Register Modem In Status Register Modem In Position In Current Buffer Register Modem In Prefetch Index Value Register Modem In Control Register Modem Out Buffer Descriptor List Base Address Register Modem Out Current Index Value Register Modem Out Last Valid Register Modem Out Status Register Modem In Position In Current Buffer Register Modem Out Prefetched Index Register Modem Out Control Register Global Control Global Status Codec Access Semaphore Register 00h 04h 05h 06h 08h 0Ah 0Bh 10h 14h 15h 16h 18h 1Ah 1Bh 3Ch 40h 44h Section 14.2.1, “x_BDBAR—Buffer Descriptor List Base Address Register” on page 14-8 Section 14.2.2, “x_CIV—Current Index Value Register” on page 14-9 Section 14.2.3, “x_LVI—Last Valid Index Register” on page 14-9 Section 14.2.4, “x_SR—Status Register” on page 14-10 Section 14.2.5, “x_PICB—Position In Current Buffer Register” on page 14-11 Section 14.2.6, “x_PIV—Prefetch Index Value Register” on page 14-11 Section 14.2.7, “x_CR—Control Register” on page 14-11 Section 14.2.1, “x_BDBAR—Buffer Descriptor List Base Address Register” on page 14-8 Section 14.2.2, “x_CIV—Current Index Value Register” on page 14-9 Section 14.2.3, “x_LVI—Last Valid Index Register” on page 14-9 Section 14.2.4, “x_SR—Status Register” on page 14-10 Section 14.2.5, “x_PICB—Position In Current Buffer Register” on page 14-11 Section 14.2.6, “x_PIV—Prefetch Index Value Register” on page 14-11 Section 14.2.7, “x_CR—Control Register” on page 14-11 Section 14.2.8, “GLOB_CNT—Global Control Register” on page 14-12 Section 14.2.9, “GLOB_STA—Global Status Register” on page 14-13 Section 14.2.10, “CAS—Codec Access Semaphore Register” on page 14-14
A-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Register Bit Index
Numerics 4 Channel Capability 13-15, 14-13 6 Channel Capability 13-15, 14-13 A A20Gate Pass-Through Enable (A20PASSEN) 11-6 AC ‘97 Cold Reset# 13-14 AC ‘97 Interrupt Routing 14-6 AC ’97 Interrupt Routing 13-7 AC‘97 Cold Reset# 14-12 AC’97 Warm Reset 13-14, 14-12 AC97_EN 9-66 AC97_STS 9-65 ACLINK Shut Off 13-14, 14-12 ACPI_EN 9-6 AD3 13-15, 14-13 ADDRESS 12-8 Address Increment/Decrement Select 9-27 ADLIB_ACT_STS 9-72 ADLIB_LPC_EN 9-18 ADLIB_TRP_EN 9-73 AF Alarm Flag 9-50 AFTERG3_EN 9-55 AIE Alarm Interrupt Enable 9-49 ALT_A20_GATE 9-52 ALTACC_EN Alternate Access Mode Enable 9-12 APIC Data 9-42 APIC ID 9-43 APIC Index 9-41 APIC_EN 9-12 APM_STS 9-71 APMC_EN 9-69 AUDIO_ACT_STS 9-72 AUDIO_TRP_EN 9-73 Autoinitialize Enable 9-27 Automatic End of Interrupt (AEOI) 9-36 Auxiliary Current 7-8
B
B Base Address 7-5, 9-6, 9-8, 10-4, 11-4, 11-13, 12-3, 13-5, 14-5 Base address of Descriptor table (BADDR) 10-12 Base and Current Address 9-24 Base and Current Count 9-25 Base Class Code 7-4, 8-5, 9-5, 10-4, 11-4, 12-3, 13-4 Base Class Code Value 14-4 Binary/BCD Countdown Select 9-30 BIOS_EN 9-69 BIOS_RLS BIOS Release 9-69 BIOS_STS 9-71 BIOSWE BIOS Write Enable 9-7 BIOSWR_STS 9-77 Bit 1 of slot 12 13-15, 14-13 Bit 2 of slot 12 13-15, 14-13 Bit 3 of slot 12 13-15, 14-13 BLE BIOS Lock Enable 9-7 Block Data Byte 12-9 BOOT_STS 9-78 Buffer Completion Interrupt Status (BCIS) 13-11, 14-10 Buffer Descriptor Base Address 13-9 Buffer Descriptor List Base Address 14-8 Buffered Mode (BUF) 9-36 Bus Master Enable (BME) 7-2, 8-3, 10-2, 11-2, 13-2, 14-2 Bus Master IDE Active (ACT) 10-12 BUS_ERR 12-6 BYTE_DONE_STS 12-6 C CAP_ID Capability ID 7-8 CAP_LIST Capabilities List 7-3 CAP_PTR Capabilities Pointer 7-6 Cascaded Interrupt Controller IRQ Connection 9-35 Channel 0 Select 9-11
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Index-1
Register Bit Index
Channel 1 Select 9-11 Channel 2 Select. 9-11 Channel 3 Select 9-11 Channel 5 Select 9-11 Channel 6 Select 9-11 Channel 7 Select 9-11 Channel Mask Bits 9-29 Channel Mask Select 9-27 Channel Request Status 9-26 Channel Terminal Count Status 9-26 Clear Byte Pointer 9-28 Clear Mask Register 9-28 CLS Cache Line Size 7-4 CNA CU Not Active 7-11 CNA Mask 7-12 CNF1_LPC_EN 9-17 CNF2_LPC_EN 9-17 Codec Write In Progress (CWIP) 13-16 COMA Decode Range 9-14 COMA_LPC_EN 9-18 COMB Decode Range 9-14 COMB_LPC_EN 9-18 Configure Flag (CF) 11-9 Connect Status Change 11-15 COPR_ERR_EN Coprocessor Error Enable 9-11 COPROC_ERR 9-52 Count Register Status 9-32 Countdown Type Status 9-32 Counter 0 Select 9-31 Counter 1 Select 9-31 Counter 2 Select 9-31 Counter Latch Command 9-31 Counter Mode Selection 9-30 Counter OUT Pin State 9-32 Counter Port 9-32 Counter Select 9-30 Counter Selection 9-31 CPU_BIST_EN 9-13 CPUPWR_FLR CPU Power Failure 9-55 CPUSLP_EN 9-54 CUC Command Unit Command 7-13 Current Connect Status 11-15
Current Equals Last Valid (CELV) 13-11, 14-10 Current Index Value 13-10, 14-9 CUS Command Unit Status 7-11 CX Command Unit (CU) Executed 7-11 CX Mask 7-12 D D1 Support 7-8 D2 Support 7-8 Data 7-16 Data Parity Error Detected (DPD) 7-3, 8-4, 8-8 Data Scale 7-9 Data Select 7-9 DATA_MSG0 Data Message Byte 0 12-9 DATA_MSG1 Data Message Byte 1 12-9 DATA0/COUNT 12-8 DATA1 12-8 Date Alarm 9-50 DCB_EN DMA Collection Buffer Enable 9-12 Deep Power-Down on Link Down Enable 7-19 Delivery Mode 9-46 Delivery Status 9-45 Destination 9-45 Destination Mode 9-45 Detected Parity Error (DPE) 7-3, 8-4, 8-8 DEV_ERR 12-6 DEV_STS DEVSEL# Timing Status 9-4 DEV_TRAP_EN 9-71 DEV_TRAP_STS 9-71 Device ID Value 9-2, 11-2, 13-2, 14-2 Device ID value 12-1 Device Identification Number 7-2, 8-2 Device Specific Initialization (DSI) 7-8 DEVMON_STS Device Monitor Status 9-70 DEVSEL# Timing Status (DEVT) 10-3, 11-3, 12-2, 13-3 DM Data Mode 9-49 DMA Channel Group Enable 9-26 DMA Channel Select 9-27 DMA Controller Halted (DCH) 13-11, 14-10 DMA Group Arbitration Priority 9-26 DMA Low Page 9-25
Index-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Register Bit Index
DMA Transfer Mode 9-27 DMA Transfer Type 9-27 DPE Detected Parity Error 9-4 DPED Data Parity Error Detected 9-4 Drive 0 DMA Capable 10-12 Drive 0 DMA Timing Enable (DTE0) 10-6 Drive 0 Fast Timing Bank (TIME0) 10-7 Drive 0 IORDY Sample Point Enable (IE0) 10-7 Drive 0 Prefetch/Posting Enable (PPE0) 10-7 Drive 1 DMA Capable 10-12 Drive 1 DMA Timing Enable (DTE1) 10-6 Drive 1 Fast Timing Bank (TIME1) 10-6 Drive 1 IORDY Sample Point Enable (IE1) 10-6 Drive 1 Prefetch/Posting Enable (PPE1) 10-6 Drive 1 Timing Register Enable (SITRE) 10-6 DSE Daylight Savings Enable 9-49 DT Delivery Type 9-44 DTE Delayed Transaction Enable 9-12 Duplex Mode 7-20 DV Division Chain Select 9-48 Dynamic Data 7-9 E Early Receive Count 7-17 Edge/Level Bank Select (LTIM) 9-34 EECS EEPROM Chip Select 7-15 EEDI EEPROM Serial Data In 7-15 EEDO EEPROM Serial Data Out 7-15 EESK EEPROM Serial Clock 7-15 Enable Special Mask Mode (ESMM) 9-38 Enter Global Suspend Mode (EGSM) 11-9 EOS End of SMI 9-69 ER Early Receive 7-11 ER Mask 7-12 Error 10-12 F F1_Disable 9-22 F2_Disable 9-22 F3_Disable 9-22 F4_Disable 9-22 F5_Disable 9-22 F6_Disable 9-22 FAILED 12-6
FAST_PCB0 Fast Primary Drive 0 Base Clock 10-10 FAST_PCB1 Fast Primary Drive 1 Base Clock 10-9 FAST_SCB0 Fast Secondary Drive 0 Base Clock 10-9 FAST_SCB1 Fast Secondary Drive 1 Base Clock 10-9 FC Full 7-18 FC Paused 7-18 FC Paused Low 7-18 FCP Flow control Pause 7-11 FCP Mask 7-12 FDD Decode Range 9-15 FDD_LPC_EN 9-18 FIFO error (FIFOE) 13-11, 14-10 FIFO Error Interrupt Enable (FEIE) 13-13, 14-11 Flow Control Threshold 7-18 Force Global Resume (FGR) 11-9 FORCE_THTL 9-63 FR Frame Received 7-11 FR Mask 7-12 Frame List Current Index/Frame Number 11-12 FREQ_STRAP 9-13 FULL_RST 9-53 FWH_C0_EN 9-16, 9-21 FWH_C0_IDSEL 9-19 FWH_C8_EN 9-16, 9-21 FWH_C8_IDSEL 9-19 FWH_D0_EN 9-16, 9-21 FWH_D0_IDSEL 9-19 FWH_D8_EN 9-16, 9-21 FWH_D8_IDSEL 9-19, 9-20 FWH_E0_EN 9-16 FWH_E0_IDSEL 9-19, 9-20 FWH_E8_EN 9-16 FWH_E8_IDSEL 9-19, 9-20 FWH_F0_EN 9-16 FWH_F0_IDSEL 9-19, 9-20 FWH_F8_EN 9-16 FWH_F8_IDSEL 9-19
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Index-3
Register Bit Index
G GAMEH_LPC_EN 9-17 GAMEL_LPC_EN 9-17 GBL _STS 9-61 GBL_EN 9-61 GBL_RLS Global Release 9-62 GBL_SMI_EN 9-69 GEN1_BASE Generic I/O Decode Range 1 Base 9-17 GEN1_EN Generic Decode Range 1 Enable 9-17 GEN2_BASE Generic I/O Decode Range 2 Base 9-20 GEN2_EN Generic I/O Decode Range 2 Enable 9-20 Global Reset (GRESET) 11-9 GPE0_STS 9-70 GPE1_STS 9-70 GPI Interrupt Enable (GIE) 13-14, 14-12 GPI Route 9-56 GPI Status Change Interrupt (GSCI) 13-16, 14-14 GPI_EN 9-68 GPI_STS 9-67 GPIO_EN 9-8 GPIO_SEL 9-84 GPIO_USE_SEL 9-83 H HCHalted 11-11 Header Type 7-5, 9-5 Header Type Value 13-4 Header Value 14-4 HIDE_ISA Hide ISA Bridge 9-11 Hole Enable (15MB-16MB). 8-12 Host Controller Process Error 11-11 Host Controller Reset (HCRESET) 11-9 Host System Error 11-11 HOST_BUSY 12-6 HOURFORM Hour Format 9-49 HP_PCI_EN 8-12 HST_EN SMBus Host Enable 12-4 HUBNMI_STS 9-76 HUBSCI_STS 9-77 HUBSERR_STS 9-76
HUBSMI_STS 9-77 I I/O Address Base bits 8-7 I/O Address Limit bits 8-7 I/O Addressing Capability 8-7 I/O APIC Identification 9-44 I/O Space (IOS) 14-2 I/O Space Enable (IOE) 7-2, 8-3 I/O Space Enable (IOSE) 11-2, 12-2 I2C_EN 12-4 iA64_EN iA64 Processor Mode Enable 9-54 ICW/OCW select 9-34 ICW4 Write Required (IC4) 9-34 IDE Decode Enable (IDE) 10-6 IDEP0_ACT_STS 9-73 IDEP0_TRP_EN 9-73 IDEP1_ACT_STS 9-73 IDEP1_TRP_EN 9-73 IDES0_ACT_STS 9-72 IDES0_TRP_EN 9-73 IDES1_ACT_STS 9-72 IDES1_TRP_EN 9-73 INIT_NOW 9-52 INT_LN Interrupt Line 7-7 INT_PN Interrupt Pin 7-7 Interesting Packet 7-19 Internal LAN Master Request Status (LAN_MREQ_STS) 8-13 Internal PCI Master Request Status (INT_MREQ_STS) 8-13 Interrupt 10-12 Interrupt Enable 7-16 Interrupt Input Pin Polarity 9-45 Interrupt Level Select (L2, L1, L0) 9-37 Interrupt Line 11-5, 13-6, 14-6 Interrupt line 12-4 Interrupt On Complete (IOC) Enable 11-12 Interrupt On Completion Enable (IOCE) 13-13, 14-11 Interrupt PIN 12-4 Interrupt pin 11-5 Interrupt Request Level 9-35 Interrupt Request Mask 9-36
Index-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Register Bit Index
Interrupt Vector Base Address 9-35 INTR 12-6 INTRD_DET Intruder Detect 9-78 INTRD_SEL 9-80 INTREN 12-7 INUSE_STS 12-6 IO Space Indicator 12-3 IOCHK_NMI_EN 9-51 IOCHK_NMI_STS IOCHK# NMI Source Status 9-51 IORDY Sample Point (ISP) 10-6 IOS (I/O Space) 13-2 IOSE I/O Space Enable (IOSE) 10-2 IRQ Number 9-42 IRQ Routing 9-8, 9-9 IRQ10 ECL 9-40 IRQ11 ECL 9-40 IRQ12 ECL 9-40 IRQ12LEN Mouse IRQ12 Latch Enable 9-12 IRQ14 ECL 9-40 IRQ15 ECL 9-40 IRQ1LEN Keyboard IRQ1 Latch Enable 9-11 IRQ3 ECL 9-39 IRQ4 ECL 9-39 IRQ5 ECL 9-39 IRQ6 ECL 9-39 IRQ7 ECL 9-39 IRQ9 ECL 9-40 IRQEN Interrupt Routing Enable 9-8, 9-9 IRQF Interrupt Request Flag 9-50 ISA Enable 8-11 K KBC_ACT_STS 9-72 KBC_LPC_EN 9-17 KBC_TRP_EN 9-73 KILL 12-7 L L128LOCK Lower 128-byte Lock 9-14 LAN Connect Address 7-16 LAN Connect Register Address 7-16 LAN Connect Software Reset 7-19 Last Valid Buffer Completion Interrupt (LVBCI) 13-11, 14-10
Last Valid Buffer Interrupt Enable (LVBIE) 13-13, 14-11 Last Valid Index 13-10, 14-9 Latch Count of Selected Counters 9-31 Latch Status of Selected Counters 9-31 LEG_ACT_STS 9-72 LEG_IO_TRP_EN 9-73 LEGACY_USB_EN 9-69 LEGACY_USB_STS 9-71 Line Status 11-14 Link Status Change Indication 7-19 Link Status Indication 7-20 Loop Back Test Mode 11-8 Low Speed Device Attached (LS) 11-14 LPT Decode Range 9-15 LPT_LPC_EN 9-18 M M Interrupt Mask 7-12 Magic Packet 7-19 MAS (Master-Abort Status) 14-3 Mask 9-45 Master Abort Mode 8-11 Master Clear 9-28 Master Latency Count 8-6 Master/Slave in Buffered Mode 9-36 Master-Abort Status (MAS) 13-3 Max Packet (MAXP) 11-9 Maximum Redirection Entries 9-44 MC_LPC_EN 9-17 MCSMI_EN Microcontroller SMI Enable 9-68 MCSMI_STS Microcontroller SMI# Status 9-70 MD3 13-15, 14-13 MDI Management Data Interrupt 7-11 Memory Address Base 8-9 Memory Address Limit 8-9 Memory Space Enable (MSE) 7-2, 8-3 Mic In Interrupt (MINT) 13-15, 14-13 Microprocessor Mode 9-36 MIDI Decode Range 9-15 MIDI_ACT_STS 9-72 MIDI_LPC_EN 9-18 MIDI_TRP_EN 9-73
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Index-5
Register Bit Index
MLTC Master Latency Timer Count 7-4 Mode Selection Status 9-32 Modem In Interrupt (MIINT) 13-16, 14-14 Modem Out Interrupt (MOINT) 13-16, 14-14 MON_TRAP_BASE 9-57 MON4_FWD_EN 9-56 MON4_MASK 9-57 MON5_FWD_EN 9-56 MON5_MASK 9-57 MON6_FWD_EN 9-56 MON6_MASK 9-57 MON7_FWD_EN 9-56 MON7_MASK 9-57 MSS Decode Range 9-15 MSS_LPC_EN 9-18 Multi-function Device 9-5 Multi-function Device. 7-5 Multi-Transaction Timer Count Value 8-12 MWIE Memory Write and Invalidate Enable 7-2 N NEWCENTURY_STS 9-77 NMI_EN 9-52 NMI_NOW 9-79 NMI2SMI_EN 9-77, 9-79 NO_REBOOT 9-13 NXT_PTR Next Item Pointer 7-8 O OCW2 Select 9-37 OCW3 Select 9-38 Opcode 7-16 Overcurrent Active 11-14 Overcurrent Indicator 11-14 P Parity Error Response 8-3 Parity Error Response Enable 8-11 Pass Through State (PSTATE) 11-6 PCB0 10-10 PCB1 10-10 PCI Interrupt Enable (USBPIRQEN) 11-6 PCI Master Request Status (PCI_MREQ_STS) 8-13 PCI_DAC_EN 8-11 PCI_SERR_EN 9-51
PCM 4/6 Enable 13-14 PCM In Interrupt (PIINT) 13-16, 14-14 PCM Out Interrupt (POINT) 13-16, 14-13 PER Parity Error Response 7-2, 9-3 PER_SMI_SEL 9-54 PERIODIC_EN 9-68 PERIODIC_STS 9-70 PF Periodic Interrupt Flag 9-50 PIE Periodic Interrupt Enable 9-49 PIRQAE_ACT_STS 9-72 PIRQBF_ACT_STS 9-72 PIRQCG_ACT_STS 9-72 PIRQDH_ACT_STS 9-72 PM1_STS_REG 9-70 PME Clock 7-8 PME Enable 7-9 PME Status 7-9, 7-19 PME Support 7-8 PME_EN 9-66 PME_STS 9-64 Pointer Field 7-14 Poll Mode Command 9-38 Port Enable/Disable Change 11-15 Port Enabled/Disabled (PORT_EN) 11-15 PORT Function Selection 7-14 Port Reset 11-14 PORT0EN 11-7 PORT1EN 11-7 POS_DEC_EN Positive Decode Enable 9-12 Position In Current Buffer 13-12, 14-11 Power State 7-9 PRBTNOR_STS Power Button Override Status 9-60 Prefetchable Memory Address Base 8-9 Prefetchable Memory Address Limit 8-10 Prefetched Index Value 13-12 Prefetched Index value 14-11 PRIM_SIG_MODE 10-9 Primany Resume Interrupt Enable 13-14, 14-12 Primary Bus Number 8-6 Primary Codec Ready (PCR) 13-15, 14-13 Primary Drive 0 Cycle Time (PCT0) 10-9
Index-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Register Bit Index
Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) 10-8 Primary Drive 1 Cycle Time (PCT1) 10-9 Primary Drive 1 IORDY Sample Point (PISP1) 10-7 Primary Drive 1 Recovery Time (PRCT1) 10-7 Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) 10-8 Primary Master Channel Cable Reporting 10-10 Primary Resume Interrupt 13-15, 14-13 Primary Slave Channel Cable Reporting 10-10 Programming Interface Value 10-3, 14-3 PRQ 9-44 PWR_FLR Power Failure 9-55 PWRBTN__STS 9-60 PWRBTN_EN 9-61 PWRBTN_LVL 9-54 PWROK_FLR PWROK Failure 9-55 R Read / Write Control (RWC) 10-11 Read Back Command 9-31 Read Completion Status 13-15 Read/Write Select 9-30 Read/Write Selection Status 9-32 Ready 7-16 Receive DMA Byte Count 7-16 Received Master Abort (RMA) 8-4, 8-8 Received Master-Abort Status (RMA) 10-3, 11-3 Received System Error (SSE) 8-4, 8-8 Received Target Abort (RTA) 7-3, 8-4, 8-8 Recovery Time (RCT) 10-6 Redirection Entry Clear 9-43 REF_TOGGLE Refresh Cycle Toggle 9-51 Register Read Command 9-38 Remote IRR 9-45 Reset Registers(RR) 14-11 Reset Registers(RR). 13-13 Resource Indicator 9-6, 9-8 Resource Type Indicator (RTE) 10-4, 11-4, 13-5, 14-5 Resume Detect (RSM_DET) 11-11, 11-14
Resume Interrupt Enable 11-12 Revision ID Value 13-3, 14-3 Revision Identification Number 8-4, 9-4 Revision Identification Number. 7-3 RI_EN 9-66 RI_STS 9-64 RMA Master Abort Status 7-3, 9-4 RNR Mask 7-12 RNR Receive Not Ready 7-11 Rotate and EOI Codes (R, SL, EOI) 9-37 RS Rate Select 9-48 RST_CPU 9-53 RTA Received Target Abort 9-4 RTC_EN RTC Event Enable 9-61 RTC_INDX Real Time Clock Index Address 9-52 RTC_PWR_STS 9-55 RTC_STS 9-60 RUC Receive Unit Command 7-13 Run/Pause Bus master (RPBM) 13-13, 14-11 Run/Stop (RS) 11-10 RUS Receive Unit Status 7-11 RW 12-8 S SAFE_MODE 9-13 SB16 Decode Range 9-15 SB16_LPC_EN 9-18 SCB General Pointer 7-14 SCB1 10-10 SCBO 10-10 SCI_EN 9-62 SCI_IRQ_SEL 9-6 SEC_SIG_MODE 10-9 SECOND_TO_STS 9-78 Secondary Bus Number 8-6 Secondary Codec Ready (SCR) 13-15, 14-13 Secondary Drive 0 Cycle Time (SCT0) 10-8 Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0) 10-8 Secondary Drive 1 Cycle Time (SCT1) 10-8 Secondary Drive 1 IORDY Sample Point (SISP1) 10-7 Secondary Drive 1 Recovery Time (SRCT1) 10-7
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Index-7
Register Bit Index
Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1) 10-8 Secondary Master Channel Cable Reporting 10-10 Secondary Resume Interrupt 13-15, 14-13 Secondary Resume Interrupt Enable 13-14, 14-12 Secondary Slave Channel Cable Reporting 10-10 SENDNOW 9-79 Serial Bus Release Number 11-5 SERIRQ_SMI_STS 9-70 SERR# Due to Delayed Transaction Timeout (SERR_DTT). 8-14 SERR# Due to Received Target Abort (SERR_RTA). 8-14 SERR# Enable 8-11 SERR# Enable (SERR_EN) 7-2, 8-3 SERR# enable on Delayed Transaction Timeout (SERR_DTT_EN) 8-13 SERR# enable on receiving target abort (SERR_RTA_EN) 8-13 SERR#_NMI_STS SERR# NMI Source Status 9-51 SERR_DTT SERR# Due to Delayed Transaction Timeout 9-10 SERR_DTT_EN SERR# on Delayed Transaction Timeout Enable 9-10 SERR_EN 9-3 SERR_RTA SERR# Due to Received Target Abort 9-10 SERR_RTA_EN SERR# on Received Target Abort Enable 9-10 SET Update Cycle Inhibit 9-49 SFPW Start Frame Pulse Width 9-9 Short Packet Interrupt Enable 11-12 SI Software Generated Interrupt 7-12 Signaled System Error (SSE) 7-3 Signaled Target Abort (STA) 8-4 Signaled Target-Abort Status 12-2 Signaled Target-Abort Status (STA) 10-3, 11-3 Single or Cascade (SNGL) 9-34 SIRQEN Serial IRQ Enable 9-9
SIRQMD Serial IRQ Mode Select 9-9 SIRQSZ Serial IRQ Frame Size 9-9 Slave Identification Code 9-36 SLAVE_ADDR 12-9 SLP_EN 9-62 SLP_SMI_EN 9-69 SLP_SMI_STS 9-71 SLP_TYP 9-62 SMB_CMD 12-7 SMB_FOR_BIOS 9-22 SMB_SMI_EN 12-4 SMB_WAK_STS SMBus Wake Status 9-64 SMBALERT_STS 12-6 SMBUS_SMI_STS 9-70 SMI at End of Pass-through Enable (SMIATENDPS) 11-6 SMI Caused by End of Pass-through (SMIBYENDPS) 11-6 SMI Caused by Port 60 Read (TRAPBY60R) 11-6 SMI Caused by Port 60 Write (TRAPBY60W) 11-6 SMI Caused by Port 64 Read (TRAPBY64R) 11-6 SMI Caused by Port 64 Write (TRAPBY64W) 11-6 SMI Caused by USB Interrupt (SMIBYUSB) 11-6 SMI on Port 60 Reads Enable (60REN) 11-7 SMI on Port 60 Writes Enable (60WEN) 11-7 SMI on Port 64 Reads Enable (64REN) 11-7 SMI on Port 64 Writes Enable (64WEN) 11-7 SMI on USB IRQ (USBSMIEN) 11-7 SOF Timing Value 11-13 Software Debug (SWDBG) 11-9 Special Fully Nested Mode (SFNM) 9-36 Special Mask Mode (SMM) 9-38 Speed 7-20 SPKR_DAT_EN 9-51 SQWE Square Wave Enable 9-49 SSE Signaled System Error 9-4 STA Signaled Target Abort 9-4 START 12-7 Start/Stop Bus Master (START) 10-11
Index-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Register Bit Index
Sub Class Code 10-3, 11-4, 12-3, 13-4 Sub Class Code Value 14-4 Sub-Class Code 7-4, 8-5, 9-5 Subordinate Bus Number 8-6 Subsystem ID Value 13-6, 14-6 Subsystem Vendor ID Value 13-6, 14-5 Suspend 11-14 SW_TCO_SMI 9-77 SWI Software Interrupt 7-11 SWSMI_RATE_SEL 9-54 SWSMI_TMR_EN Software SMI# Timer Enable 9-69 SWSMI_TMR_STS 9-71 SYS_RST 9-53 T TCO_EN 9-68 TCO_INT_EN TCO Interrupt Enable 9-7 TCO_INT_SEL TCO Interrupt Select 9-7 TCO_INT_STS 9-77 TCO_MESSAGE 9-80 TCO_STS 9-70 TCO_TMR_HLT TCO Timer Halt 9-79 TCOSCI_EN 9-66 TCOSCI_STS 9-64 THRM#_POL 9-66 THRM_DTY 9-63 THRM_EN 9-66 THRM_STS Thermal Interrupt Status 9-65 THRMOR_STS Thermal Interrupt Override Status 9-65 THT_EN 9-63 THTL_DTY 9-63 THTL_STS Throttle Status 9-63 TIM_CNT2_EN Timer Counter 2 Enable 9-51 TIMEOUT 9-77
Timeout/CRC Interrupt Enable 11-12 TMR_VAL 9-62 TMR2_OUT_STS Timer Counter 2 OUT Status 9-51 TMROF_EN Timer Overflow Interrupt Enable 9-61 TMROF_STS Timer Overflow Status 9-61 TOP_SWAP 9-13 Trigger Mode 9-45 U U128E Upper 128-byte Enable 9-14 U128LOCK Upper 128-byte Lock 9-14 UF Update-ended Flag 9-50 UIE Update-ended Interrupt Enable 9-49 UIP Update In Progress 9-48 USB Error Interrupt 11-11 USB Interrupt (USBINT) 11-11 USB1_EN 9-66 USB1_STS 9-65 USB2_EN 9-66 USB2_STS 9-65 V Vendor ID Value 9-2, 11-1, 12-1, 13-1, 14-1 Vendor Identification Number 8-2 Version 7-8 VGA Enable 8-11 VRT Valid RAM and Time Bit 9-50 W WAK_STS 9-60 WDSTATUS Watchdog Status 9-80 WR_PingPong_EN 10-10 X Xoff 7-18 Xon 7-18
82801BA ICH2 and 82801BAM ICH2-M Datasheet
Index-9
Intel around the world
United States and Canada Intel Corporation Robert Noyce Building 2200 Mission College Boulevard P.O. Box 58119 Santa Clara, CA 95052-8119 USA Phone: (800) 628-8686 Europe Intel Corporation (UK) Ltd. Pipers Way Swindon Wiltshire SN3 1RJ UK Phone: England Germany France Italy Israel Netherlands Sweden (44) 1793 403 000 (49) 89 99143 0 (33) 1 4571 7171 (39) 2 575 441 (972) 2 589 7111 (31) 10 286 6111 (46) 8 705 5600
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