82P35

Intel® 3 Series Express Chipset Family Datasheet - For the Intel® 82Q35, 82Q33, 82G33 Graphics and Memory Controller Hub (GMCH) and Intel® 82P35 Memory Controller Hub (MCH) August 2007 Document Number: 316966-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 82Q35 GMCH, 82Q33 GMCH, 82G33 GMCH, and 82P35 MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Pentium, Intel Core, Intel Inside, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Intel Corporation. All rights reserved. 2 Datasheet Contents 1 Introduction ................................................................................................... 19 1.1 1.2 1.3 Terminology ........................................................................................ 24 Reference Documents ........................................................................... 26 (G)MCH Overview................................................................................. 27 1.3.1 Host Interface......................................................................... 27 1.3.2 System Memory Interface......................................................... 28 1.3.3 Direct Media Interface (DMI)..................................................... 29 1.3.4 PCI Express* Interface............................................................. 29 1.3.5 Graphics Features (Intel® 82Q35, 82Q33, 82G33 GMCH Only) ....... 30 1.3.6 SDVO and Analog Display Features (Intel® 82Q35, 82Q33, 82G33 GMCH Only) ................................................................. 30 1.3.7 (G)MCH Clocking ..................................................................... 31 1.3.8 Thermal Sensor ...................................................................... 31 1.3.9 Power Management ................................................................. 32 1.3.10 Intel® Active Management Technology (Intel® AMT)/ Controller Link (Intel® 82Q35 GMCH Only) ................................................ 32 1.3.11 Intel® Trusted Execution Technology (Intel® 82Q35 GMCH Only) .... 33 1.3.12 Intel® Virtualization Technology for Directed I/O (Intel® VT-d) (Intel® 82Q35 GMCH Only) ....................................................... 33 Host Interface Signals ........................................................................... 36 System Memory (DDR2/DDR3) Channel A Interface Signals........................ 40 System Memory (DDR2/DDR3) Channel B Interface Signals........................ 41 System Memory DDR2/DDR3 Miscellaneous Signals .................................. 42 PCI Express* Interface Signals ............................................................... 43 Controller Link Interface Signals ............................................................. 43 Analog Display Signals (Intel® 82Q33, GMCH, 82Q33 GMCH, and 82G33 GMCH Only) ........................................................................................ 44 Clocks, Reset, and Miscellaneous ............................................................ 45 Direct Media Interface........................................................................... 46 Serial DVO Interface (Intel® 82Q35, 82Q33, 82G33 GMCH Only) ................. 47 Power and Grounds .............................................................................. 50 2 Signal Description ........................................................................................... 35 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3 System Address Map ....................................................................................... 51 3.1 Legacy Address Range .......................................................................... 55 3.1.1 DOS Range (0h – 9_FFFFh)....................................................... 56 3.1.2 Legacy Video Area (A_0000h – B_FFFFh) .................................... 56 3.1.3 Expansion Area (C_0000h – D_FFFFh)........................................ 57 3.1.4 Extended System BIOS Area (E_0000h-E_FFFFh)......................... 57 3.1.5 System BIOS Area (F_0000h-F_FFFFh)....................................... 58 3.1.6 PAM Memory Area Details......................................................... 58 Main Memory Address Range (1MB – TOLUD) ........................................... 59 3.2.1 ISA Hole (15 MB-16 MB) .......................................................... 60 3.2.2 TSEG..................................................................................... 60 3.2.3 Pre-allocated Memory .............................................................. 60 3 3.2 Datasheet 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 4 PCI Memory Address Range (TOLUD – 4GB) ............................................. 61 3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) .................. 63 3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh)............................................. 63 3.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................. 63 3.3.4 High BIOS Area....................................................................... 63 Main Memory Address Space (4 GB to TOUUD) ......................................... 64 3.4.1 Memory Re-claim Background ................................................... 65 3.4.2 Memory Reclaiming ................................................................. 65 PCI Express* Configuration Address Space............................................... 65 PCI Express* Graphics Attach (PEG)........................................................ 66 Graphics Memory Address Ranges (Intel® 82Q35, 82Q33, and 82G33 (G)MCH Only) ...................................................................................... 67 System Management Mode (SMM) .......................................................... 67 3.8.1 SMM Space Definition .............................................................. 68 3.8.2 SMM Space Restrictions............................................................ 68 3.8.3 SMM Space Combinations ......................................................... 69 3.8.4 SMM Control Combinations ....................................................... 69 3.8.5 SMM Space Decode and Transaction Handling.............................. 69 3.8.6 Processor WB Transaction to an Enabled SMM Address Space ........ 69 3.8.7 SMM Access through GTT TLB (Intel® 82Q35, 82Q33, 82G33 GMCH Only) ........................................................................... 70 Memory Shadowing .............................................................................. 70 I/O Address Space................................................................................ 70 3.10.1 PCI Express* I/O Address Mapping ............................................ 71 (G)MCH Decode Rules and Cross-Bridge Address Mapping .......................... 72 3.11.1 Legacy VGA and I/O Range Decode Rules ................................... 72 Register Terminology ............................................................................ 74 Configuration Process and Registers ........................................................ 76 4.2.1 Platform Configuration Structure ............................................... 76 Configuration Mechanisms ..................................................................... 77 4.3.1 Standard PCI Configuration Mechanism ...................................... 77 4.3.2 PCI Express* Enhanced Configuration Mechanism ........................ 77 Routing Configuration Accesses .............................................................. 79 4.4.1 Internal Device Configuration Accesses....................................... 80 4.4.2 Bridge Related Configuration Accesses........................................ 80 4.4.2.1 PCI Express* Configuration Accesses ........................... 80 4.4.2.2 DMI Configuration Accesses ....................................... 81 I/O Mapped Registers ........................................................................... 81 4.5.1 CONFIG_ADDRESS—Configuration Address Register ..................... 81 4.5.2 CONFIG_DATA—Configuration Data Register ............................... 83 DRAM Controller (D0:F0)....................................................................... 85 5.1.1 VID—Vendor Identification........................................................ 87 5.1.2 DID—Device Identification ........................................................ 87 5.1.3 PCICMD—PCI Command ........................................................... 88 5.1.4 PCISTS—PCI Status ................................................................. 89 5.1.5 RID—Revision Identification ...................................................... 90 5.1.6 CC—Class Code....................................................................... 91 5.1.7 MLT—Master Latency Timer ...................................................... 91 5.1.8 HDR—Header Type .................................................................. 92 Datasheet (G)MCH Register Description ............................................................................ 73 4.1 4.2 4.3 4.4 4.5 5 DRAM Controller Registers (D0:F0).................................................................... 85 5.1 4 5.2 SVID—Subsystem Vendor Identification...................................... 92 SID—Subsystem Identification .................................................. 92 CAPPTR—Capabilities Pointer .................................................... 93 PXPEPBAR—PCI Express* Egress Port Base Address ..................... 93 MCHBAR—(G)MCH Memory Mapped Register Range Base .............. 94 GGC—GMCH Graphics Control Register (Intel® 82Q35, 82Q33, 82G33 GMCH Only) ................................................................. 95 5.1.15 DEVEN—Device Enable............................................................. 97 5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ................ 99 5.1.17 DMIBAR—Root Complex Register Range Base Address ................ 101 5.1.18 PAM0—Programmable Attribute Map 0...................................... 102 5.1.19 PAM1—Programmable Attribute Map 1...................................... 104 5.1.20 PAM2—Programmable Attribute Map 2...................................... 105 5.1.21 PAM3—Programmable Attribute Map 3...................................... 106 5.1.22 PAM4—Programmable Attribute Map 4...................................... 107 5.1.23 PAM5—Programmable Attribute Map 5...................................... 108 5.1.24 PAM6—Programmable Attribute Map 6...................................... 109 5.1.25 LAC—Legacy Access Control.................................................... 110 5.1.26 REMAPBASE—Remap Base Address Register.............................. 111 5.1.27 REMAPLIMIT—Remap Limit Address Register ............................. 111 5.1.28 SMRAM—System Management RAM Control .............................. 112 5.1.29 ESMRAMC—Extended System Management RAM Control ............. 113 5.1.30 TOM—Top of Memory............................................................. 114 5.1.31 TOUUD—Top of Upper Usable Dram ......................................... 115 5.1.32 GBSM—Graphics Base of Stolen Memory................................... 116 5.1.33 BGSM—Base of GTT stolen Memory.......................................... 117 5.1.34 TSEGMB—TSEG Memory Base ................................................. 117 5.1.35 TOLUD—Top of Low Usable DRAM ............................................ 118 5.1.36 ERRSTS—Error Status ............................................................ 119 5.1.37 ERRCMD—Error Command ...................................................... 121 5.1.38 SMICMD—SMI Command........................................................ 122 5.1.39 SKPD—Scratchpad Data ......................................................... 122 5.1.40 CAPID0—Capability Identifier .................................................. 123 MCHBAR ........................................................................................... 127 5.2.1 CHDECMISC—Channel Decode Miscellaneous............................. 130 5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ................. 131 5.2.3 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ................. 132 5.2.4 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ................. 133 5.2.5 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ................. 133 5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ......................... 134 5.2.7 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ......................... 135 5.2.8 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG............................... 135 5.2.9 C0CYCTRKACT—Channel 0 CYCTRK ACT ................................... 136 5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR ..................................... 137 5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ................................... 138 5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR ................................ 138 5.2.13 C0CKECTRL—Channel 0 CKE Control ........................................ 139 5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control......................... 140 5.2.15 C0ODTCTRL—Channel 0 ODT Control ....................................... 142 5.2.16 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ................. 143 5.2.17 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ................. 143 5.2.18 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ................. 144 5.2.19 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ................. 144 5.2.20 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes ........................ 145 5.2.21 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes ........................ 145 5.1.9 5.1.10 5.1.11 5.1.12 5.1.13 5.1.14 Datasheet 5 5.3 5.2.22 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG............................... 146 5.2.23 C1CYCTRKACT—Channel 1 CYCTRK ACT ................................... 147 5.2.24 C1CYCTRKWR—Channel 1 CYCTRK WR ..................................... 148 5.2.25 C1CYCTRKRD—Channel 1 CYCTRK READ................................... 149 5.2.26 C1CKECTRL—Channel 1 CKE Control ........................................ 150 5.2.27 C1REFRCTRL—Channel 1 DRAM Refresh Control......................... 151 5.2.28 C1ODTCTRL—Channel 1 ODT Control ....................................... 153 5.2.29 EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0........ 154 5.2.30 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1 ......... 154 5.2.31 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2 ......... 154 5.2.32 EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3 ......... 155 5.2.33 EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute.................. 155 5.2.34 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute.................. 156 5.2.35 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE............................. 156 5.2.36 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT ............................ 157 5.2.37 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR .............................. 158 5.2.38 EPDCYCTRKWRTRD—EPD CYCTRK WRT READ............................ 159 5.2.39 EPDCKECONFIGREG—EPD CKE Related Configuration Register ..... 160 5.2.40 MEMEMSPACE—ME Memory Space Configuration ....................... 162 5.2.41 EPDREFCONFIG—EP DRAM Refresh Configuration....................... 163 5.2.42 TSC1—Thermal Sensor Control 1 ............................................. 165 5.2.43 TSC2—Thermal Sensor Control 2 ............................................. 166 5.2.44 TSS—Thermal Sensor Status................................................... 168 5.2.45 TSTTP—Thermal Sensor Temperature Trip Point......................... 169 5.2.46 TCO—Thermal Calibration Offset.............................................. 170 5.2.47 THERM1—Hardware Throttle Control ........................................ 171 5.2.48 TIS—Thermal Interrupt Status ................................................ 172 5.2.49 TSMICMD—Thermal SMI Command.......................................... 174 5.2.50 PMSTS—Power Management Status ......................................... 175 EPBAR .............................................................................................. 176 5.3.1 EPESD—EP Element Self Description ........................................ 176 5.3.2 EPLE1D—EP Link Entry 1 Description........................................ 177 5.3.3 EPLE1A—EP Link Entry 1 Address ............................................ 177 5.3.4 EPLE2D—EP Link Entry 2 Description........................................ 178 5.3.5 EPLE2A—EP Link Entry 2 Address ............................................ 179 PCI Express* Configuration Register Details (D1:F0) ............................... 183 6.1.1 VID1—Vendor Identification .................................................... 183 6.1.2 DID1—Device Identification .................................................... 183 6.1.3 PCICMD1—PCI Command ....................................................... 184 6.1.4 PCISTS1—PCI Status ............................................................. 186 6.1.5 RID1—Revision Identification .................................................. 187 6.1.6 CC1—Class Code ................................................................... 187 6.1.7 CL1—Cache Line Size............................................................. 188 6.1.8 HDR1—Header Type .............................................................. 188 6.1.9 PBUSN1—Primary Bus Number ................................................ 188 6.1.10 SBUSN1—Secondary Bus Number ............................................ 189 6.1.11 SUBUSN1—Subordinate Bus Number........................................ 189 6.1.12 IOBASE1—I/O Base Address ................................................... 190 6.1.13 IOLIMIT1—I/O Limit Address................................................... 190 6.1.14 SSTS1—Secondary Status ...................................................... 191 6.1.15 MBASE1—Memory Base Address.............................................. 192 6.1.16 MLIMIT1—Memory Limit Address ............................................. 193 6.1.17 PMBASE1—Prefetchable Memory Base Address .......................... 194 Datasheet 6 PCI Express* Registers (D1:F0) ...................................................................... 180 6.1 6 6.1.18 6.1.19 6.1.20 6.1.21 6.1.22 6.1.23 6.1.24 6.1.25 6.1.26 6.1.27 6.1.28 6.1.29 6.1.30 6.1.31 6.1.32 6.1.33 6.1.34 6.1.35 6.1.36 6.1.37 6.1.38 6.1.39 6.1.40 6.1.41 6.1.42 6.1.43 6.1.44 6.1.45 6.1.46 6.1.47 6.1.48 6.1.49 6.1.50 6.1.51 6.1.52 6.1.53 6.1.54 6.1.55 6.1.56 6.1.57 6.1.58 7 7.1 PMLIMIT1—Prefetchable Memory Limit Address.......................... 195 PMBASEU1—Prefetchable Memory Base Address ........................ 196 PMLIMITU1—Prefetchable Memory Limit Address........................ 197 CAPPTR1—Capabilities Pointer................................................. 198 INTRLINE1—Interrupt Line...................................................... 198 INTRPIN1—Interrupt Pin......................................................... 198 BCTRL1—Bridge Control ......................................................... 199 PM_CAPID1—Power Management Capabilities............................ 201 PM_CS1—Power Management Control/Status ............................ 202 SS_CAPID—Subsystem ID and Vendor ID Capabilities ................ 203 SS—Subsystem ID and Subsystem Vendor ID ........................... 203 MSI_CAPID—Message Signaled Interrupts Capability ID .............. 204 MC—Message Control............................................................. 204 MA—Message Address............................................................ 205 MD—Message Data ................................................................ 205 PEG_CAPL—PCI Express*-G Capability List................................ 206 PEG_CAP—PCI Express*-G Capabilities..................................... 206 DCAP—Device Capabilities ...................................................... 207 DCTL—Device Control ............................................................ 208 DSTS—Device Status ............................................................. 209 LCAP—Link Capabilities .......................................................... 210 LCTL—Link Control ................................................................ 212 LSTS—Link Status ................................................................. 214 SLOTCAP—Slot Capabilities..................................................... 215 SLOTCTL—Slot Control ........................................................... 216 SLOTSTS—Slot Status............................................................ 219 RCTL—Root Control ............................................................... 220 RSTS—Root Status ................................................................ 221 PEGLC—PCI Express*-G Legacy Control .................................... 222 VCECH—Virtual Channel Enhanced Capability Header ................. 223 PVCCAP1—Port VC Capability Register 1 ................................... 223 PVCCAP2—Port VC Capability Register 2 ................................... 224 PVCCTL—Port VC Control........................................................ 224 VC0RCAP—VC0 Resource Capability ......................................... 225 VC0RCTL—VC0 Resource Control ............................................. 226 VC0RSTS—VC0 Resource Status .............................................. 227 RCLDECH—Root Complex Link Declaration Enhanced .................. 228 ESD—Element Self Description ................................................ 228 LE1D—Link Entry 1 Description ............................................... 229 LE1A—Link Entry 1 Address .................................................... 229 PEGSSTS—PCI Express*-G Sequence Status ............................. 230 Direct Memory Interface (DMI) Registers.......................................................... 232 Direct Memory Interface (DMI) Configuration Register Details ................... 233 7.1.1 DMIVCECH—DMI Virtual Channel Enhanced Capability ................ 233 7.1.2 DMIPVCCAP1—DMI Port VC Capability Register 1 ....................... 234 7.1.3 DMIPVCCAP2—DMI Port VC Capability Register 2 ....................... 234 7.1.4 DMIPVCCTL—DMI Port VC Control............................................ 235 7.1.5 DMIVC0RCAP—DMI VC0 Resource Capability ............................. 235 7.1.6 DMIVC0RCTL0—DMI VC0 Resource Control ............................... 236 7.1.7 DMIVC0RSTS—DMI VC0 Resource Status .................................. 237 7.1.8 DMIVC1RCAP—DMI VC1 Resource Capability ............................. 237 7.1.9 DMIVC1RCTL1—DMI VC1 Resource Control ............................... 238 7.1.10 DMIVC1RSTS—DMI VC1 Resource Status .................................. 239 7.1.11 DMILCAP—DMI Link Capabilities .............................................. 239 Datasheet 7 7.1.12 7.1.13 8 DMILCTL—DMI Link Control .................................................... 240 DMILSTS—DMI Link Status ..................................................... 241 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) ....................................................................................... 242 8.1 Integrated Graphics Register Details (D2:F0).......................................... 242 8.1.1 VID2—Vendor Identification .................................................... 243 8.1.2 DID—Device Identification ...................................................... 244 8.1.3 PCICMD2—PCI Command ....................................................... 244 8.1.4 PCISTS2—PCI Status ............................................................. 246 8.1.5 RID2—Revision Identification .................................................. 247 8.1.6 CC—Class Code..................................................................... 247 8.1.7 CLS—Cache Line Size............................................................. 248 8.1.8 MLT2—Master Latency Timer................................................... 248 8.1.9 HDR2—Header Type .............................................................. 249 8.1.10 GMADR—Graphics Memory Range Address ................................ 249 8.1.11 IOBAR—I/O Base Address....................................................... 250 8.1.12 SVID2—Subsystem Vendor Identification .................................. 250 8.1.13 SID2—Subsystem Identification .............................................. 251 8.1.14 ROMADR—Video BIOS ROM Base Address ................................. 251 8.1.15 CAPPOINT—Capabilities Pointer ............................................... 252 8.1.16 INTRLINE—Interrupt Line ....................................................... 252 8.1.17 INTRPIN—Interrupt Pin .......................................................... 252 8.1.18 MINGNT—Minimum Grant ....................................................... 253 8.1.19 MAXLAT—Maximum Latency ................................................... 253 8.1.20 CAPID0—Capability Identifier .................................................. 254 8.1.21 MGGC—GMCH Graphics Control Register................................... 255 8.1.22 DEVEN—Device Enable........................................................... 257 8.1.23 SSRW—Software Scratch Read Write........................................ 259 8.1.24 BSM—Base of Stolen Memory.................................................. 259 8.1.25 HSRW—Hardware Scratch Read Write ...................................... 259 8.1.26 MC—Message Control............................................................. 260 8.1.27 MA—Message Address............................................................ 261 8.1.28 MD—Message Data ................................................................ 261 8.1.29 GDRST—Graphics Debug Reset ............................................... 262 8.1.30 PMCAPID—Power Management Capabilities ID ........................... 263 8.1.31 PMCAP—Power Management Capabilities .................................. 263 8.1.32 PMCS—Power Management Control/Status ................................ 264 8.1.33 SWSMI—Software SMI ........................................................... 265 IGD Configuration Register Details (D2:F1) ............................................ 266 8.2.1 VID2—Vendor Identification .................................................... 268 8.2.2 DID2—Device Identification .................................................... 268 8.2.3 PCICMD2—PCI Command ....................................................... 269 8.2.4 PCISTS2—PCI Status ............................................................. 270 8.2.5 RID2—Revision Identification .................................................. 271 8.2.6 CC—Class Code Register ........................................................ 271 8.2.7 CLS—Cache Line Size............................................................. 272 8.2.8 MLT2—Master Latency Timer................................................... 272 8.2.9 HDR2—Header Type .............................................................. 273 8.2.10 MMADR—Memory Mapped Range Address ................................. 273 8.2.11 SVID2—Subsystem Vendor Identification .................................. 274 8.2.12 SID2—Subsystem Identification .............................................. 274 8.2.13 ROMADR—Video BIOS ROM Base Address ................................. 275 8.2.14 CAPPOINT—Capabilities Pointer ............................................... 275 8.2.15 MINGNT—Minimum Grant ....................................................... 276 Datasheet 8.2 8 8.2.16 8.2.17 8.2.18 8.2.19 8.2.20 8.2.21 8.2.22 8.2.23 8.2.24 8.2.25 8.2.26 8.2.27 9 9.1 MAXLAT—Maximum Latency ................................................... 276 CAPID0—Mirror of Dev0 Capability Identifier ............................. 276 MGGC—Mirror of Dev 0 GMCH Graphics Control Register ............. 277 DEVEN—Device Enable........................................................... 279 SSRW—Mirror of Fun 0 Software Scratch Read Write .................. 281 BSM—Mirror of Func0 Base of Stolen Memory............................ 281 HSRW—Mirror of Dev2 Func0 Hardware Scratch Read Write ........ 282 GDRST—Mirror of Dev2 Func0 Graphics Reset ........................... 282 PMCAPID—Mirror of Fun 0 Power Management Capabilities ID...... 283 PMCAP—Mirror of Fun 0 Power Management Capabilities ............. 284 PMCS—Power Management Control/Status ................................ 285 SWSMI—Mirror of Func0 Software SMI ..................................... 286 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) ............... 288 Host Embedded Controller Interface (HECI1) Configuration Register Details (D3:F0) .................................................................................. 288 9.1.1 ID— Identifiers ..................................................................... 289 9.1.2 CMD— Command .................................................................. 290 9.1.3 STS— Device Status .............................................................. 291 9.1.4 RID— Revision ID.................................................................. 292 9.1.5 CC— Class Code.................................................................... 292 9.1.6 CLS— Cache Line Size............................................................ 292 9.1.7 MLT— Master Latency Timer ................................................... 293 9.1.8 HTYPE— Header Type ............................................................ 293 9.1.9 HECI_MBAR— HECI MMIO Base Address ................................... 294 9.1.10 SS— Sub System Identifiers ................................................... 294 9.1.11 CAP— Capabilities Pointer....................................................... 295 9.1.12 INTR— Interrupt Information .................................................. 295 9.1.13 MGNT— Minimum Grant ......................................................... 295 9.1.14 MLAT— Maximum Latency ...................................................... 296 9.1.15 HFS— Host Firmware Status ................................................... 296 9.1.16 PID— PCI Power Management Capability ID .............................. 296 9.1.17 PC— PCI Power Management Capabilities.................................. 297 9.1.18 PMCS— PCI Power Management Control And Status ................... 298 9.1.19 MID— Message Signaled Interrupt Identifiers ............................ 299 9.1.20 MC— Message Signaled Interrupt Message Control ..................... 299 9.1.21 MA— Message Signaled Interrupt Message Address .................... 300 9.1.22 MUA— Message Signaled Interrupt Upper Address (Optional)....... 300 9.1.23 MD— Message Signaled Interrupt Message Data ........................ 301 9.1.24 HIDM—HECI Interrupt Delivery Mode ....................................... 301 HECI2 Configuration Register Details (D3:F1) (Intel® 82Q35 and 82Q33 GMCH only) ............................................................................. 302 9.2.1 ID— Identifiers ..................................................................... 303 9.2.2 CMD— Command .................................................................. 303 9.2.3 STS— Device Status .............................................................. 305 9.2.4 RID— Revision ID.................................................................. 306 9.2.5 CC— Class Code.................................................................... 306 9.2.6 CLS— Cache Line Size............................................................ 306 9.2.7 MLT— Master Latency Timer ................................................... 307 9.2.8 HTYPE— Header Type ............................................................ 307 9.2.9 HECI_MBAR— HECI MMIO Base Address ................................... 308 9.2.10 SS— Sub System Identifiers ................................................... 308 9.2.11 CAP— Capabilities Pointer....................................................... 309 9.2.12 INTR— Interrupt Information .................................................. 309 9.2.13 MGNT— Minimum Grant ......................................................... 309 9 9.2 Datasheet 9.3 9.4 9.2.14 MLAT— Maximum Latency ...................................................... 310 9.2.15 HFS— Host Firmware Status ................................................... 310 9.2.16 PID— PCI Power Management Capability ID .............................. 310 9.2.17 PC— PCI Power Management Capabilities.................................. 311 9.2.18 PMCS— PCI Power Management Control And Status ................... 312 9.2.19 MID— Message Signaled Interrupt Identifiers ............................ 313 9.2.20 MC— Message Signaled Interrupt Message Control ..................... 313 9.2.21 MA— Message Signaled Interrupt Message Address .................... 314 9.2.22 MUA— Message Signaled Interrupt Upper Address (Optional)....... 314 9.2.23 MD— Message Signaled Interrupt Message Data ........................ 315 9.2.24 HIDM—HECI Interrupt Delivery Mode ....................................... 315 IDE Function for Remote Boot and Installations PT IDER Register Details (D3:F2) (Intel® 82Q35 and 82Q33 GMCH Only) ............................ 316 9.3.1 ID—Identification .................................................................. 317 9.3.2 CMD—Command Register ....................................................... 317 9.3.3 STS—Device Status ............................................................... 319 9.3.4 RID—Revision ID................................................................... 320 9.3.5 CC—Class Codes ................................................................... 320 9.3.6 CLS—Cache Line Size............................................................. 320 9.3.7 MLT—Master Latency Timer .................................................... 321 9.3.8 HTYPE—Header Type ............................................................. 321 9.3.9 PCMDBA—Primary Command Block IO Bar ................................ 322 9.3.10 PCTLBA—Primary Control Block Base Address............................ 322 9.3.11 SCMDBA—Secondary Command Block Base Address................... 323 9.3.12 SCTLBA—Secondary Control Block base Address ........................ 323 9.3.13 LBAR—Legacy Bus Master Base Address ................................... 324 9.3.14 SS—Sub System Identifiers .................................................... 325 9.3.15 EROM—Expansion ROM Base Address....................................... 325 9.3.16 CAP—Capabilities Pointer........................................................ 326 9.3.17 INTR—Interrupt Information ................................................... 326 9.3.18 MGNT—Minimum Grant .......................................................... 327 9.3.19 MLAT—Maximum Latency ....................................................... 327 9.3.20 PID—PCI Power Management Capability ID ............................... 327 9.3.21 PC—PCI Power Management Capabilities................................... 328 9.3.22 PMCS—PCI Power Management Control and Status .................... 328 9.3.23 MID—Message Signaled Interrupt Capability ID ......................... 330 9.3.24 MC—Message Signaled Interrupt Message Control ...................... 330 9.3.25 MA—Message Signaled Interrupt Message Address ..................... 331 9.3.26 MAU—Message Signaled Interrupt Message Upper Address .......... 331 9.3.27 MD—Message Signaled Interrupt Message Data ......................... 332 Serial Port for Remote Keyboard and Text KT Redirection Register Details (D3:F3) (Intel® 82Q35 and 82Q33 GMCH Only) ............................ 333 9.4.1 ID—Identification .................................................................. 334 9.4.2 CMD—Command Register ....................................................... 334 9.4.3 STS—Device Status ............................................................... 336 9.4.4 RID—Revision ID................................................................... 337 9.4.5 CC—Class Codes ................................................................... 337 9.4.6 CLS—Cache Line Size............................................................. 337 9.4.7 MLT—Master Latency Timer .................................................... 338 9.4.8 HTYPE—Header Type ............................................................. 338 9.4.9 KTIBA—KT IO Block Base Address............................................ 339 9.4.10 KTMBA—KT Memory Block Base Address................................... 339 9.4.11 SS—Sub System Identifiers .................................................... 340 9.4.12 EROM—Expansion ROM Base Address....................................... 341 9.4.13 CAP—Capabilities Pointer........................................................ 341 Datasheet 10 9.4.14 9.4.15 9.4.16 9.4.17 9.4.18 9.4.19 9.4.20 9.4.21 9.4.22 9.4.23 9.4.24 10 10.1 INTR—Interrupt Information ................................................... 342 MGNT—Minimum Grant .......................................................... 342 MLAT—Maximum Latency ....................................................... 343 PID—PCI Power Management Capability ID ............................... 343 PC—PCI Power Management Capabilities................................... 344 PMCS—PCI Power Management Control and Status .................... 345 MID—Message Signaled Interrupt Capability ID ......................... 346 MC—Message Signaled Interrupt Message Control ...................... 347 MA—Message Signaled Interrupt Message Address ..................... 348 MAU—Message Signaled Interrupt Message Upper Address .......... 348 MD—Message Signaled Interrupt Message Data ......................... 349 Functional Description ................................................................................... 350 Host Interface.................................................................................... 350 10.1.1 FSB IOQ Depth ..................................................................... 350 10.1.2 FSB OOQ Depth .................................................................... 350 10.1.3 FSB GTL+ Termination ........................................................... 350 10.1.4 FSB Dynamic Bus Inversion .................................................... 350 10.1.4.1 APIC Cluster Mode Support ...................................... 351 System Memory Controller................................................................... 352 10.2.1 System Memory Organization Modes ........................................ 352 10.2.2 Single Channel Mode ............................................................. 352 10.2.3 Dual Channel Symmetric Mode ................................................ 352 10.2.4 Dual Channel Asymmetric Mode with Intel® Flex Memory Mode Enabled ............................................................................... 353 10.2.5 System Memory Technology Supported .................................... 354 PCI Express* ..................................................................................... 355 10.3.1 PCI Express* Architecture....................................................... 355 10.3.2 Transaction Layer.................................................................. 355 10.3.3 Data Link Layer..................................................................... 355 10.3.4 Physical Layer....................................................................... 355 Intel® Serial Digital Video Output (SDVO) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) ............................................................................ 356 10.4.1 Intel® SDVO Capabilities......................................................... 356 10.4.2 Intel® SDVO Modes................................................................ 357 10.4.3 PCI Express* and Internal Graphics Simultaneous Operation ....... 358 10.4.3.1 Standard PCI Express* Cards and Internal Graphics..... 358 10.4.3.2 Media Expansion Cards (Concurrent SDVO and PCI Express*) .............................................................. 358 Integrated Graphics Controller (Intel® 82Q35, 82Q33, 82G33 GMCH Only) . 360 10.5.1 3D Graphics Pipeline .............................................................. 360 10.5.2 3D Engine ............................................................................ 361 10.5.3 Texture Engine ..................................................................... 362 10.5.4 Raster Engine ....................................................................... 362 Display Interfaces (Intel® 82Q35, 82Q33, 82G33 Only GMCH) .................. 362 10.6.1 Analog Display Port Characteristics .......................................... 363 10.6.1.1 Integrated RAMDAC ................................................ 363 10.6.1.2 Sync Signals .......................................................... 363 10.6.1.3 VESA/VGA Mode ..................................................... 363 10.6.1.4 DDC (Display Data Channel)..................................... 364 10.6.2 Digital Display Interface ......................................................... 364 10.6.2.1 Multiplexed Digital Display Channels – Intel® SDVOB and Intel® SDVOC ........................................ 364 11 10.2 10.3 10.4 10.5 10.6 Datasheet 10.7 10.8 10.9 10.6.2.2 ADD2/Media Expansion Card (MEC) ........................... 364 10.6.2.3 TMDS Capabilities ................................................... 364 10.6.2.4 HDMI Capabilities ................................................... 365 10.6.2.5 LVDS Capabilities.................................................... 365 10.6.2.6 TV-IN Capabilities ................................................... 365 10.6.2.7 TV-Out Capabilities ................................................. 365 10.6.2.8 Control Bus............................................................ 366 10.6.3 Multiple Display Configurations................................................ 366 Power Management ............................................................................ 367 10.7.1 ACPI.................................................................................... 367 10.7.2 PCI Express Active State Power Management ............................ 367 Thermal Sensor.................................................................................. 368 10.8.1 PCI Device 0 Function 0 ......................................................... 368 10.8.2 MCHBAR Thermal Sensor Registers .......................................... 368 10.8.3 Programming Sequence ......................................................... 369 10.8.4 Trip Point Temperature Programming ....................................... 370 Clocking............................................................................................ 371 10.9.1 Overview ............................................................................. 371 10.9.2 Platform Clocks ..................................................................... 372 Absolute Minimum and Maximum Ratings .............................................. 374 Current Consumption .......................................................................... 375 Signal Groups .................................................................................... 378 DC Characteristics .............................................................................. 381 11.4.1 I/O Buffer Supply Voltages ..................................................... 381 11.4.2 General DC Characteristics ..................................................... 382 11.4.3 R, G, B / CRT DAC Display DC Characteristics (Intel® 82Q35, 82Q33, 82G33 Only).............................................................. 387 Ballout.............................................................................................. 388 11 Electrical Characteristics ................................................................................ 374 11.1 11.2 11.3 11.4 12 Ballout and Package Information ..................................................................... 388 12.1 13 14 Package Specifications................................................................................... 424 Testability.................................................................................................... 426 14.1 14.2 14.3 XOR Test Mode Initialization ................................................................ 426 XOR Chain Definition .......................................................................... 428 XOR Chains ....................................................................................... 429 12 Datasheet Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1-1. Intel® Q35/Q33 Express Chipsets System Block Diagram Example.......... 21 1-2. Intel® G33 Express Chipset System Block Diagram Example .................. 22 1-3. Intel® P35 Express Chipset System Block Diagram Example .................. 23 3-1. System Address Ranges................................................................... 54 3-2. DOS Legacy Address Range.............................................................. 55 3-3. Main Memory Address Range ............................................................ 59 3-4. PCI Memory Address Range.............................................................. 62 4-1. Memory Map to PCI Express* Device Configuration Space..................... 78 4-2. GMCH Configuration Cycle Flow Chart ................................................ 79 10-1. sDVO Conceptual Block Diagram ................................................... 357 10-2. Concurrent savon / PCI Express* Non-Reversed Configurations ......... 359 10-3. Concurrent SDVO / PCI Express* Reversed Configurations ................ 359 10-4. Integrated 3D Graphics Pipeline .................................................... 361 10-5. Intel® 3 Series Express Chipset Clocking Diagram ............................ 372 12-1. (G)MCH Ballout Diagram (Top View Left – Columns 43–30) ............... 389 12-2. (G)MCH Ballout Diagram (Top View Middle– Columns 29–15) ............ 390 12-3. (G)MCH Ballout Diagram (Top View Right – Columns 14–1)............... 391 13-1. (G)MCH Package Drawing............................................................. 425 14-1. XOR Test Mode Initialization Cycles ............................................... 426 Datasheet 13 Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2-1. 3-1. 3-2. 3-3. 3-4. SDVO/PCI Express* Signal Mapping.................................................... 49 Expansion Area Memory Segments ..................................................... 57 Extended System BIOS Area Memory Segments ................................... 57 System BIOS Area Memory Segments................................................. 58 Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB GTT stolen and 1 MB TSEG ............................................................... 60 3-5. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB TSEG..................................................................................... 68 3-6. SMM Space ..................................................................................... 69 5-1. DRAM Controller Register Address Map (D0:F0).................................... 85 5-2. MCHBAR Register Address Map ........................................................ 127 5-3. DRAM Rank Attribute Register Programming ...................................... 134 5-4. EPBAR Register Address Map ........................................................... 176 6-1. PCI Express* Register Address Map (D1:F0) ...................................... 180 7-1. DMI Register Address Map............................................................... 232 8-1. Integrated Graphics Device Register Address Map (D2:F0) ................... 242 8-2. Integrated Graphics Device Register Address Map (D2:F1) ................... 266 9-1. HECI Function in ME Subsystem Register Address Map ........................ 288 9-2. Second HECI Function in ME Subsystem Register Address Map ............. 302 9-3. IDE Function for Remote Boot and Installations PT IDER Register Address Map.................................................................................. 316 9-4. Serial Port for Remote Keyboard and Text KT Redirection Register Address Map................................................................................. 333 10-1. Sample System Memory Dual Channel Symmetric Organization Mode with Intel® Flex Memory Mode Enabled .................................... 353 10-2. Sample System Memory Dual Channel Asymmetric Organization Mode with Intel® Flex Memory Mode Disabled ................................... 353 10-3 Supported DIMM Module Configurations............................................ 354 10-4. Concurrent SDVO / PCI Express* Configuration Strap Controls............ 358 10-5. Intel® G33 and P35 Express Chipset (G)MCH Voltage Rails ................. 367 10-6. Intel® Q35 and Q33 Express Chipset GMCH Voltage Rails ................... 367 11-1. Absolute Minimum and Maximum Ratings ........................................ 374 11-2. Intel® Q35/Q33 Express Chipset – GMCH Current Consumption in S0 .. 376 11-3. Current Consumption in S3, S4, S5 with Intel® Active Management Technology Operation (82Q35 GMCH Only) ...................................... 377 11-4. Signal Groups .............................................................................. 378 11-5. I/O Buffer Supply Voltage............................................................. 381 11-6. DC Characteristics ....................................................................... 382 11-7. R, G, B / CRT DAC Display DC Characteristics: Functional Operating Range (VCCA_DAC = 3.3 V ± 5%) ................................................. 387 12-1. Ballout – Sorted by Ball................................................................. 392 12-2. Ballout – Sorted by Signal ............................................................. 411 14-1. XOR Chain 14 functionality ............................................................ 427 14-2. XOR Chain Outputs....................................................................... 428 14-3. XOR Chain 0................................................................................ 429 14-4. XOR Chain 1................................................................................ 430 14-5. XOR Chain 2................................................................................ 430 14-6. XOR Chain 3................................................................................ 431 14 Datasheet Table Table Table Table Table Table Table Table Table Table Table 14-7. XOR Chain 4................................................................................ 431 14-8. XOR Chain 5................................................................................ 432 14-9. XOR Chain 6................................................................................ 432 14-10. XOR Chain 7 .............................................................................. 433 14-11. XOR Chain 8 .............................................................................. 433 14-12. XOR Chain 9 .............................................................................. 434 14-13. XOR Chain 10 ............................................................................ 434 14-14. XOR Chain 11 ............................................................................ 435 14-15. XOR Chain 12 ............................................................................ 436 14-16. XOR Chain 13 ............................................................................ 436 14-17. XOR Chain 14 ............................................................................ 436 Datasheet 15 Revision History Revision Number -001 -002 Description • Initial release. • Added Intel 82Q35 GMCH and Intel 82Q33 GMCH specifications Revision Date June 2007 August 2007 § 16 Datasheet Intel® 3 Series Chipset (G)MCH Features • Processor/Host Interface (FSB) ⎯ Supports Intel® Core™2 Duo desktop processor ⎯ Supports Intel® Core™2 Quad desktop processor ⎯ 800/1067/1333 MT/s (200/266/333 MHz) FSB ⎯ Hyper-Threading Technology (HT Technology) ⎯ FSB Dynamic Bus Inversion (DBI) ⎯ 36-bit host bus addressing ⎯ 12-deep In-Order Queue ⎯ 1-deep Defer Queue ⎯ GTL+ bus driver with integrated GTL termination resistors ⎯ Supports cache Line Size of 64 bytes • System Memory Interface ⎯ One or two channels (each channel consisting of 64 data lines) ⎯ Single or Dual Channel memory organization ⎯ DDR2-800/667 frequencies ⎯ DDR3-1066/800 frequencies (82G33 GMCH and 82P35 MCH only) ⎯ Unbuffered, non-ECC DIMMs only ⎯ Supports 1-Gb, 512-Mb DDR2 or DDR3 technologies for x8 and x16 devices ⎯ 8 GB maximum memory • Direct Media Interface (DMI) ⎯ Chip-to-chip connection interface to Intel ICH9 ⎯ 2 GB/s point-to-point DMI to ICH9 (1 GB/s each direction) ⎯ 100 MHz reference clock (shared with PCI Express graphics attach) ⎯ 32-bit downstream addressing ⎯ Messaging and Error Handling • PCI Express* Interface ⎯ One x16 PCI Express port ⎯ Compatible with the PCI Express Base Specification, Revision 1.1 ⎯ Raw bit rate on data pins of 2.5 Gb/s resulting in a real bandwidth per pair of 250 MB/s • Integrated Graphics Device (82Q35, 82Q33, 82G33 GMCH only) ⎯ Core frequency of 400 MHz ⎯ 1.6 GP/s pixel rate ⎯ High-Quality 3D Setup and Render Engine ⎯ High-Quality Texture Engine ⎯ 3D Graphics Rendering Enhancements ⎯ 2D Graphics ⎯ Video Overlay ⎯ Multiple Overlay Functionality • Analog Display (82Q35, 82Q33, 82G33 GMCH only) ⎯ 350 MHz Integrated 24-bit RAMDAC ⎯ Up to 2048x1536 @ 75 Hz refresh ⎯ Hardware Color Cursor Support ⎯ DDC2B Compliant Interface • Digital Display (82Q35, 82Q33, 82G33 GMCH only) ⎯ SDVO ports in single mode supported ⎯ 225 MHz dot clock on each 12-bit interface ⎯ Flat panels up to 2048x1536 @ 60 Hz or digital CRT/HDTV at 1400x1050 @ 85Hz ⎯ Dual independent display options with digital display ⎯ Multiplexed digital display channels (supported with ADD2 Card). ⎯ Supports TMDS transmitters or TV-Out encoders ⎯ ADD2/MEC card uses PCI Express graphics x16 connector ⎯ Two channels multiplexed with PCI Express* Graphics port ⎯ Supports Hot-Plug and Display • Thermal Sensor ⎯ Catastrophic Trip Point support ⎯ Hot Trip Point support for SMI generation • Power Management ⎯ PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3) ⎯ ACPI Revision 2.0 compatible power management ⎯ Supports processor states: C0, C1, C2 ⎯ Supports System states: S0, S1, S3, and S5 ⎯ Supports processor Thermal Management 2 • Package ⎯ FC-BGA. 34 mm × 34 mm. The 1226 balls are located in a non-grid pattern § Datasheet 17 18 Datasheet Introduction 1 Introduction The Intel® 3 Series Chipsets are designed for use with the Intel® Core™2 Duo desktop processor and Intel® Core™2 Quad processor based platforms. Each chipset contains two components: GMCH (or MCH) for the host bridge and I/O Controller Hub 9 (ICH9) for the I/O subsystem. The 82Q33 GMCH is part of the Intel® Q35 Express chipset. The 82Q33 GMCH is part of the Intel® Q33 Express chipset. The 82G33 GMCH is part of the Intel® G33 Express chipset. The 82P35 MCH is part of the Intel® P35 Express chipset. The ICH9 is the ninth generation I/O Controller Hub and provides a multitude of I/O related functions. The following figures show example system block diagrams for the Intel® Q35, Q33, G33 and P35 Express chipsets. This document is the datasheet for the Intel® 82Q35, 82Q33, and 82G33 Graphics and Memory Controller Hub (GMCH) and Intel® 82P35 Memory Controller Hub (MCH). Topics covered include; signal description, system memory map, PCI register description, a description of the (G)MCH interfaces and major functional units, electrical characteristics, ballout definitions, and package characteristics. The primary difference between the Intel® 82Q35, 82Q33, 82G33 GMCH and 82P35 MCH is that the 82Q35 GMCH, 82Q33 GMCH, and 82G33 GMCH have an integrated graphics device (IGD) plus the associated display interfaces. The 82P35 does not contain an IGD and the associated interfaces. Note: Unless otherwise specified, the information in this document applies to the Intel® 82Q35, 82Q33, 82G33 Graphics and Memory Controller Hub (GMCH) and Intel® 82P35 Memory Controller Hub (MCH). Note: The term (G)MCH refers to the 82Q35 GMCH, 82Q33 GMCH, 82G33 GMCH and 82P35 MCH. Note: Unless otherwise specified, ICH9 refers to the Intel® 82801IB ICH9, Intel® 82801IR ICH9R, and Intel® 82801IH ICH9DH I/O Controller Hub 9 components. Note: The term ICH9 refers to the ICH9, ICH9R, and ICH9DH components. Datasheet 19 Introduction The following table provides a high-level component feature summary. Capability Memory Speed 82Q35 GMCH DDR2-800/667 82Q33 GMCH DDR2-800/667 82G33 GMCH DDR2-800/667 DDR3-1067/800 Integrated Graphics Device Discrete Graphics PCI Express Interface SDVO Expansion Dual Independent Display Intel® Active Management Technology (AMT)1,2 Alerting Standard Format (ASF) NOTE: 1. 2. 3. Yes PCI Express x16 Yes (1) x16 ADD2/MEC Yes Yes1 Yes PCI Express x16 Yes (1) x16 ADD2/MEC Yes No Yes PCI Express x16 Yes (1) x16 ADD2/MEC Yes No 82P35 MCH DDR2-800/667 DDR3-1067/800 No PCI Express x16 Yes (1) x16 — — No Yes1 Yes Yes (DDR2 only)3 Yes (DDR2 only)3 For the 82Q35 GMCH, only one manageability solution can be supported, AMT or ASF. Intel® Active Management Technology requires the platform to have an Intel® AMTenabled chipset, network hardware and software, connection with a power source and an active LAN port. ASF is available on 82G33 GMCH and 82P35 MCH with DDR2 system memory only. ASF on 82G33 GMCH and 82P35 MCH with DDR3 system memory is not a validated configuration. 20 Datasheet Introduction Figure 1-1. Intel® Q35/Q33 Express Chipsets System Block Diagram Example Processor 800/1067/1333 MHz FSB Intel® Q35/Q33 Express Chipset Analog Display System Memory Channel A Display MEC GMCH VGA DDR2 SDVO Channel B Display Graphics Card OR PCI Express* x16 Graphics DMI Interface USB 2.0 (Supports 12 USB ports Dual EHCI Controller) SATA (6 ports) Intel® High Definition Audio Codec(s) Controller Link DDR2 Power Management Clock Generators Intel ® System Management (TCO) SMBus 2.0/I2C Intel® ICH9 PCI Express* x1 Intel® Gigabit Ethernet Phy GLCI LCI SPI BIOS Flash PCI Bus GPIO LPC I/F Other ASICs (optional) TPM (optional) Super I/O S L O T ... S L O T Firmware Hub Sys_Blk_Q35-Q33 Datasheet 21 Introduction Figure 1-2. Intel® G33 Express Chipset System Block Diagram Example Processor 800/1067/1333 MHz FSB Intel® G33 Express Chipset VGA Analog Display Channel A GMCH System Memory DDR2/DDR3 Display MEC Channel B SDVO Graphics Card OR PCI Express* x16 Graphics DMI Interface USB 2.0 (Supports 12 USB ports Dual EHCI Controller) SATA (6 ports) Intel High Definition Audio Codec(s) ® DDR2/DDR3 Display Controller Link Power Management Clock Generators Intel ® System Management (TCO) SMBus 2.0/I2C Intel® ICH9 PCI Express* x1 Intel® Gigabit Ethernet Phy GLCI LCI SPI BIOS Flash PCI Bus GPIO LPC I/F Other ASICs (optional) TPM (optional) Super I/O S L O T ... S L O T Firmware Hub Sys_Blk_Q35-G33 22 Datasheet Introduction Figure 1-3. Intel® P35 Express Chipset System Block Diagram Example Processor 800/1067/1333 MHz FSB Intel® P35 Express Chipset System Memory PCI Express* x16 Graphics MCH Channel A DDR2/DDR3 Display Graphics Card Channel B DDR2/DDR3 DMI Interface USB 2.0 (Supports 12 USB ports Dual EHCI Controller) SATA (6 ports) Controller Link Power Management Clock Generators Intel Intel® High Definition Audio Codec(s) ® System Management (TCO) SMBus 2.0/I2C Intel® ICH9 PCI Express* x1 Intel Gigabit Ethernet Phy ® GLCI LCI SPI BIOS Flash PCI Bus GPIO LPC I/F Other ASICs (optional) TPM (optional) Super I/O S L O T ... S L O T Firmware Hub Sys_Blk_P35 Datasheet 23 Introduction 1.1 Terminology Term ADD Card Description Advanced Digital Display Card. Provides digital display options for an Intel Graphics Controller that supports ADD cards (have DVOs multiplexed with AGP interface). Keyed like an AGP 4x card and plugs into an AGP connector. Will not work with an Intel Graphics Controller that implements Intel® SDVO. Advanced Digital Display Card – 2nd Generation. Provides digital display options for an Intel graphics controller that supports ADD2 cards. Plugs into an x16 PCI Express* connector but utilizes the multiplexed SDVO interface. Will not work with an Intel Graphics Controller that supports Intel® DVO and ADD cards. Used in this specification to refer to one or more hardware components that connects processor complexes to the I/O and memory subsystems. The chipset may include a variety of integrated devices. GMCH-ICH9 Control Link The internal base logic in the (G)MCH Cathode Ray Tube Dynamic Bus Inversion A second generation Double Data Rate SDRAM memory technology A third generation Double Data Rate SDRAM memory technology Translating the address in a DMA request (DVA) to a host physical address (HPA) (G)MCH-Intel® ICH9 Direct Media Interface A collection of physical, logical or virtual resources that are allocated to work together. Domain is used as a generic term for virtual machines, partitions, etc. Digital Video Interface. Specification that defines the connector and interface for digital displays. Dynamic Video Memory Technology Front Side Bus, synonymous with Host or processor bus Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN# and PWROK are asserted. Guest Address Width. GAW refers to the DMA virtual addressability limit. Graphics and Memory Controller Hub. GMCH is a component that contains the processor interface, DRAM controller, and x16 PCI Express port (typically the external graphics interface). It communicates with the I/O controller hub (Intel® ICH9) over the DMI interconnect. The GMCH contains an embedded graphics controller. Memory Controller Hub. See MCH. GPA Guest Physical Address is the view of physical memory from software running in a partition. GPA is also used in this document as an example usage for DMA virtual addresses (DVA) ADD2 Card Chipset / Root – Complex CLink Core CRT DBI DDR2 DDR3 DMA Remapping DMI Domain DVI DVMT FSB Full Reset GAW GMCH 24 Datasheet Introduction Term Media Expansion Card (MEC) Description Media Expansion Card. MEC provides digital display options for an Intel Graphics Controller that supports MEC cards. Plugs into an x16 PCI Express connector but uses the multiplexed SDVO interface. Adds Video In capabilities to platform. Will not work with an Intel Graphics Controller that supports DVO and ADD cards. MEC Will function as an ADD2 card in an ADD2 supported system, but Video In capabilities will not work. Memory Controller Hub. MCH is a component that contains the processor interface, DRAM controller, and x16 PCI Express port (typically the external graphics interface). It communicates with the I/O controller hub (Intel® ICH9) over the DMI interconnect. The MCH does not contain an embedded graphics controller. Maximum Guest Address Width. MGAW refers to the maximum DMA virtual addressability supported by a DMA-remapping hardware implementation. Host Address Width. This refers to the maximum host physical address that can be accessed by a given processor / root-complex implementation. The host BIOS typically reports the host system address map. This term is used synonymously with processor Host Physical Address Internal Graphics Device An interrupt request signal where X stands for interrupts A, B, C and D Ninth generation I/O Controller Hub component that contains the primary PCI interface, LPC interface, USB2.0, SATA, and other I/O functions. For this GMCH, the term Intel® ICH refers to Intel® ICH9. Intel® Management Engine that provides core functionality for Intel® AMT. I/O Translation Look aside Buffer. IOTLB refers to an address translation cache in a DMA-remapping hardware unit that caches effective translations from DVA (GPA) to HPA. In Order Queue A VMM offering that can be measured for security properties Message Signaled Interrupt. A transaction conveying interrupt information to the receiving agent through the same path that normally carries read and write commands. Out of Order Queuing PDE (non-leaf) cache refers to address translation caches in a DMAremapping hardware unit that caches page directory entries at the various page-directory levels. These are also referred to as non-leaf caches in this document. A high-speed serial interface whose configuration is software compatible with the legacy PCI specifications. The physical PCI bus that is driven directly by the Intel® ICH9 component. Communication between Primary PCI and the (G)MCH occurs over DMI. Note that the Primary PCI bus is not PCI Bus 0 from a configuration standpoint. System Error. An indication that an unrecoverable error has occurred on an I/O bus. A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four x16 SDRAM devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DIMM. System Control Interrupt. Used in ACPI protocol. MCH MGAW HAW Host HPA IGD INTx Intel® ICH9 Intel® ME IOTLB IOQ MVMM MSI OOQ PDE Cache/ Non-leaf Cache PCI Express* Primary PCI SERR Rank SCI Datasheet 25 Introduction Term SDVO Description Serial Digital Video Out (SDVO). Digital display channel that serially transmits digital display data to an external SDVO device. The SDVO device accepts this serialized format and then translates the data into the appropriate display format (i.e. TMDS, LVDS, and TV-Out). This interface is not electrically compatible with the previous digital display channel - DVO. Third party codec that uses SDVO as an input. May have a variety of output formats, including DVI, LVDS, HDMI, TV-out, etc. System Management Interrupt. Used to indicate any of several system conditions such as thermal sensor events, throttling activated, access to System Management RAM, chassis open, or other system state related activity. Transition Minimized Differential Signaling. Signaling interface from Silicon Image that is used in DVI and HDMI. Intel® Trusted Execution Technology defines platform level enhancements that provide the building blocks for creating trusted platforms. Unified Memory Architecture used for system memory. Typically used by IGD or ME functionality. Voltage Controlled Oscillator Virtual Machine Monitor. A software layer that controls virtualization SDVO Device SMI TMDS Intel® TXT UMA VCO VMM 1.2 Reference Documents Document Name Intel 3 Series Chipset Family Specification Update Intel® Q35/Q33/G33/P35 Express Chipset Family Thermal and Mechanical Design Guide. Intel® Core™2 Duo Processor and Intel® Pentium® Dual Core Thermal and Mechanical Design Guide Intel® I/O Controller Hub 9 (ICH9) Family Thermal Mechanical Design Guide. Intel® I/O Controller Hub 9 (ICH9) Family Datasheet Designing for Energy Efficiency White Paper Intel® Q35/Q33/P35/G33 Express Chipset Memory Technology and Configuration Guide White Paper Advanced Configuration and Power Interface Specification, Version 2.0 Advanced Configuration and Power Interface Specification, Version 1.0b The PCI Local Bus Specification, Version 2.3 PCI Express* Specification, Version 1.1 ® Location www.intel.com/design/chipsets/ specupdt/316967.htm www.intel.com/design/chipsets/ designex/316968,htm www.intel.com/design/processor /designex/317804.htm www.intel.com/design/chipsets/ designex/316974.htm www.intel.com/design/chipsets/ datashts/316972.htm www.intel.com/design/chipsets/ applnots/316970.htm www.intel.com/design/chipsets/ applnots/316971.htm http://www.acpi.info/ http://www.acpi.info/ http://www.pcisig.com/specifica tions http://www.pcisig.com/specifica tions 26 Datasheet Introduction 1.3 (G)MCH Overview The (G)MCH designed for use with the Intel® Core™2 Duo desktop processors and Intel® Core™2 Quad desktop processors in desktop platforms. The role of a (G)MCH in a system is to manage the flow of information between its four interfaces: the processor interface, the System Memory interface, the External Graphics interface, and the I/O Controller through DMI interface. This includes arbitrating between the four interfaces when each initiates transactions. The 82G33 and 82P35 (G)MCHs support one or two channels of DDR2 or DDR3 SDRAM. The 82Q35 and 82Q33 GMCHs support one or two channels of DDR2 SDRAM. The (G)MCH also supports the PCI Express based external graphics attach. The Q35/Q33/G33/P35 Express chipset platforms support the ninth generation I/O Controller Hub (Intel® ICH9) to provide a multitude of I/O related features. 1.3.1 Host Interface The (G)MCH can use a single LGA775 socket processor. The (G)MCH supports FSB frequencies of 200/266/333 MHz. Host-initiated I/O cycles are decoded to PCI Express, DMI, or the (G)MCH configuration space. Host-initiated memory cycles are decoded to PCI Express, DMI, or system memory. PCI Express device accesses to noncacheable system memory are not snooped on the host bus. Memory accesses initiated from PCI Express using PCI semantics and from DMI to system SDRAM will be snooped on the host bus. Capabilities of the Host Interface include: • Supports Intel® CoreTM2 Duo processors and Intel® CoreTM2 Quad processors • Supports Front Side Bus (FSB) at 800/1066/1333 MT/s (200/266/333 MHz) • Supports FSB Dynamic Bus Inversion (DBI) • Supports 36-bit host bus addressing, allowing the processor to access the entire 64 GB of the host address space • Has a 12-deep In-Order Queue to support up to twelve outstanding pipelined address requests on the host bus • Has a 1-deep Defer Queue • Uses GTL+ bus driver with integrated GTL termination resistors • Supports a Cache Line Size of 64 bytes Datasheet 27 Introduction 1.3.2 System Memory Interface The (G)MCH integrates a system memory DDR2 and DDR3 (82G33 GMCH and 82P35 MCH only) controller with two, 64-bit wide interfaces. The buffers support both SSTL_1.8 (Stub Series Terminated Logic for 1.8 V) and SSTL_1.5 (Stub Series Terminated Logic for 1.5 V) signal interfaces. The memory controller interface is fully configurable through a set of control registers. Capabilities of the system memory interface include: • Directly supports one or two channels of DDR2 or DDR3 (82G33 GMCH and 82P35 MCH only) memory with a maximum of two DIMMs per channel. • Supports single and dual channel memory organization modes. • Supports a data burst length of eight for all memory organization modes. • Supports memory data transfer rates of 667 MHz and 800 MHz for DDR2, and 800 MHz and 1066 MHz for DDR3. • I/O Voltage of 1.8 V for DDR2 and 1.5 V for DDR3. • Supports only un-buffered non-ECC DDR2 or DDR3 DIMMs • Supports maximum memory bandwidth of 6.4 GB/s in single-channel or dualchannel asymmetric mode, or 12.8 GB/s in dual-channel symmetric mode assuming DDR2 800 MHz. • Supports maximum memory bandwidth of 8.5 GB/s in single-channel or dualchannel asymmetric mode, or 17 GB/s in dual-channel interleaved mode assuming DDR3 1066 MHz. • Supports 512 Mb and 1 Gb DDR2 or DDR3 (82G33 GMCH and 82P35 MCH only) DRAM technologies for x8 and x16 devices. • Using 512 Mb device technologies, the smallest memory capacity possible is 256 MB, assuming Single Channel Mode with a single x16 single sided un-buffered non-ECC DIMM memory configuration. • Using 1 Gb device technologies, the largest memory capacity possible is 8 GB, assuming Dual Channel Mode with four x8 double sided un-buffered non-ECC DIMM memory configuration. • Supports up to 32 simultaneous open pages per channel (assuming 4 ranks of 8 bank devices). • Supports opportunistic refresh scheme. The (G)MCH has an arbitration scheme to refresh memory when the DRAM is idle. • Supports Partial Writes to memory using Data Mask (DM) signals. • Supports a memory thermal management scheme to selectively manage reads and/or writes. Memory thermal management can be triggered either by on-die thermal sensor, or by preset limits. Management limits are determined by weighted sum of various commands that are scheduled on the memory interface. 28 Datasheet Introduction 1.3.3 Direct Media Interface (DMI) Direct Media Interface (DMI) is the chip-to-chip connection between the (G)MCH and ICH9. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally. To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions, the ICH9 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both ends of the DMI link (i.e., the ICH9 and (G)MCH). • A chip-to-chip connection interface to Intel ICH9 • 2 GB/s point-to-point DMI to ICH9 (1 GB/s each direction) • 100 MHz reference clock (shared with PCI Express Graphics Attach) • 32-bit downstream addressing • APIC and MSI interrupt messaging support. Will send Intel-defined “End Of Interrupt” broadcast message when initiated by the processor. • Message Signaled Interrupt (MSI) messages • SMI, SCI, and SERR error indication 1.3.4 PCI Express* Interface The (G)MCH contains one 16-lane (x16) PCI Express port intended for an external PCI Express graphics card. The PCI Express port is compliant to the PCI Express* Base Specification revision 1.1. The x16 port operates at a frequency of 2.5 Gb/s on each lane while employing 8b/10b encoding, and supports a maximum theoretical bandwidth of 40 Gb/s in each direction. The 82Q35/82Q33/82G33 GMCHs multiplex the PCI Express interface with the Intel® SDVO ports. • One, 16-lane PCI Express port intended for Graphics Attach, compatible to the PCI Express* Base Specification revision 1.1. • PCI Express frequency of 1.25 GHz resulting in 2.5 Gb/s each direction per lane. • Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of 250 MB/s given the 8b/10b encoding used to transmit data across this interface • Maximum theoretical realized bandwidth on the interface of 4 GB/s in each direction simultaneously, for an aggregate of 8 GB/s when x16. • PCI Express* Graphics Extended Configuration Space. The first 256 bytes of configuration space alias directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4 KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. • PCI Express Enhanced Addressing Mechanism. Accessing the device configuration space in a flat memory mapped fashion. Datasheet 29 Introduction • Automatic discovery, negotiation, and training of link out of reset • Supports traditional PCI style traffic (asynchronous snooped, PCI ordering) • Supports traditional AGP style traffic (asynchronous non-snooped, PCI Expressrelaxed ordering) • Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e., normal PCI 2.3 Configuration space as a PCI-to-PCI bridge) • Supports “static” lane numbering reversal. This method of lane reversal is controlled by a Hardware Reset strap, and reverses both the receivers and transmitters for all lanes (e.g., TX[15]->TX[0], RX[15]->RX[0]). This method is transparent to all external devices and is different than lane reversal as defined in the PCI Express Specification. In particular, link initialization is not affected by static lane reversal. 1.3.5 Graphics Features (Intel® 82Q35, 82Q33, 82G33 GMCH Only) The GMCH provides an integrated graphics device (IGD) delivering cost competitive 3D, 2D and video capabilities. The GMCH contains an extensive set of instructions for 3D operations, 2D operations, motion compensation, overlay, and display control. The GMCH’s video engines support video conferencing and other video applications. The GMCH uses a UMA configuration with DVMT for graphics memory. The GMCH also has the capability to support external graphics accelerators via the PCI Express Graphics (PEG) port but cannot work concurrently with the integrated graphics device. High bandwidth access to data is provided through the system memory port. 1.3.6 SDVO and Analog Display Features (Intel® 82Q35, 82Q33, 82G33 GMCH Only) The GMCH provides interfaces to a progressive scan analog monitor and two SDVO ports. For the GMCH, the SDVO ports are multiplexed with PCI Express x16 graphics port signals. The GMCH supports two multiplexed SDVO ports that each drive pixel clocks up to 225 MHz. The SDVO ports can each support a single-channel SDVO device. If both ports are active in single-channel mode, they can have different display timing and data. The digital display channels are capable of driving a variety of SDVO devices (e.g., TMDS, TV-Out). Note that SDVO only works with the Integrated Graphics Device (IGD). The GMCH is capable of driving an Advanced Digital Display (ADD2) card or Media Expansion Card. The Media Expansion Card adds video-in capabilities. The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant external device and connector, the GMCH has a high-speed interface to a digital display (e.g., flat panel or digital CRT). The GMCH is compliant with HDMI specification 1.1. When combined with a HDMI compliant external device and connector, the external HDMI device can support standard, enhanced, or high-definition video, plus multi-channel digital audio on a single cable. 30 Datasheet Introduction Capabilities of the SDVO and Analog Display interfaces include: • SDVO Support ⎯ SDVO ports in either single modes supported ⎯ 3x3 Built In full panel scalar ⎯ 180 degree Hardware screen rotation ⎯ Multiplexed Digital Display Channels (Supported with ADD2/MEC) ⎯ Two channels multiplexed with PCI Express* Graphics port ⎯ 225 MHz dot clock on each 12-bit interface ⎯ Supports flat panels up to 1920 x 1200 @ 60 Hz or digital CRT/HDTV at 1400 x1050 @ 85 Hz ⎯ Supports Hot-Plug and Display ⎯ Supports TMDS transmitters or TV-out encoders ⎯ ADD2/Media Expansion card utilizes PCI Express Graphics x16 connector • Analog Display Support ⎯ 350 MHz Integrated 24-bit RAMDAC ⎯ Up to 2048x1536 @ 75 Hz refresh ⎯ Hardware Color Cursor Support ⎯ DDC2B Compliant Interface • Dual Independent Display options with digital display 1.3.7 (G)MCH Clocking • Differential Host clock of 200/266/333 MHz (HCLKP/HCLKN). Supports transfer rates of 800/1066/1333 MT/s. • Internal and External Memory clocks of 333 MHz, 400 MHz, and 533 MHz generated from one of two (G)MCH PLLs that use the Host clock as a reference. • The PCI Express* PLL of 100 MHz Serial Reference Clock (GCLKP/GCLKN) generates the PCI Express core clock of 250 MHz • Display timings are generated from display PLLs that use a 96 MHz differential non-spread spectrum clock as a reference. Display PLLs can also use the SDVO_TVCLKIN[+/-] from an SDVO device as a reference. • All of the above clocks are capable of tolerating Spread Spectrum clocking. • Host, Memory, and PCI Express Graphics PLLs and all associated internal clocks are disabled until PWROK is asserted. 1.3.8 Thermal Sensor (G)MCH Thermal Sensor support includes: • Catastrophic Trip Point support for emergency clock gating for the (G)MCH at 115 °C. • Hot Trip Point support for SMI generation between 85 °C and 105 °C. • The minimal temperature reported by (G)MCH is 66 °C Datasheet 31 Introduction 1.3.9 Power Management (G)MCH Power Management support includes: • • • PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3) SMRAM space remapping to A0000h (128 KB) Supports extended SMRAM space above 256 MB, additional 1 MB TSEG from the Base of graphics stolen memory (BSM) when enabled, and cacheable (cacheability controlled by processor) ACPI Rev 2.0 compatible power management Supports processor states: C0, C1, and C2 Supports System states: S0, S1, S3 and S5 Supports processor Thermal Management 2 (TM2) Supports Manageability states M0, M1-S3, M1-S5, Moff-S3, Moff-S5 • • • • • 1.3.10 Intel® Active Management Technology (Intel® AMT)/ Controller Link (Intel® 82Q35 GMCH Only) The GMCH supports Intel® Active Management Technology that combines hardware and software solutions to provide: • Asset Management • OOB diagnostics • Agent Present and Health Detect • Network Protection with System Defense Intel® AMT integrates advanced manageability features into hardware and firmware. Intel® AMT extends the capabilities of existing management solutions by enabling system and software asset information, remote diagnostics, and recovery plus network protection through the OOB (Out-Of-Band) channel (i.e., always available even when the system is in a low-power “off” state or the OS is hung). Controller link is the Intel® Management Engine link between the GMCH and the ICH9. 32 Datasheet Introduction 1.3.11 Intel® Trusted Execution Technology (Intel® 82Q35 GMCH Only) Intel® Trusted Execution Technology (Intel® TXT) is a security initiative that involves the processor, chipset and platform. Intel® Trusted Execution Technology requires the following support in the chipset: • FSB encodings for LTMW and LTMR cycles • Measured launch of a VMM, using a TPM • Protected path from the processor to the TPM, which is enabled by the processor • Ranges of memory protected from DMA accesses. ® Intel® TXT is only supported by the Intel Q35 Express chipset. 1.3.12 Intel® Virtualization Technology for Directed I/O (Intel® VT-d) (Intel® 82Q35 GMCH Only) Intel® Virtualization Technology for Directed I/O comprises technology components to support virtualization of platforms based on Intel architecture microprocessors. This document describes the chipset hardware components supporting I/O virtualization ® that are in the (G)MCH. Intel® VT-d is only supported by the Intel Q35 Express chipset. § Datasheet 33 Introduction 34 Datasheet Signal Description 2 Signal Description This chapter provides a detailed description of (G)MCH signals. The signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type: Signal Type PCI Express* Description PCI Express interface signals. These signals are compatible with PCI Express 1.1 Signaling Environment AC Specifications and are AC coupled. The buffers are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2 Vmax. Single-ended maximum = 1.25 V. Single-ended minimum = 0 V. Direct Media Interface signals. These signals are compatible with PCI Express 1.1 Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2 Vmax. Single-ended maximum = 1.25 V. Single-ended minimum = 0 V. CMOS buffers. 1.5 V tolerant. CMOS Open Drain buffers. 3.3 V tolerant. Host Clock Signal Level buffers. Current mode differential pair. Differential typical swing = (|D+ – D-|) * 2 = 1.4 V. Single ended input tolerant from -0.35 V to 1.2 V. Typical crossing voltage 0.35 V. DMI CMOS COD HCSL HVCMOS HVIN SSTL_1.8 SSTL_1.5 A High Voltage CMOS buffers. 3.3 V tolerant. High Voltage CMOS input-only buffers. 3.3 V tolerant. Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V tolerant. Stub Series Termination Logic. These are 1.5 V output capable buffers. 1.5 V tolerant Analog reference or output. May be used as a threshold voltage or for buffer compensation. Gunning Transceiver Logic signaling technology. Implements a voltage level as defined by VTT of 1.2 V. GTL+ Datasheet 35 Signal Description 2.1 Host Interface Signals Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination voltage of the Host Bus (VTT). Signal Name FSB_ADSB Type I/O GTL+ Description Address Strobe: The processor bus owner asserts FSB_ADSB to indicate the first of two cycles of a request phase. The (G)MCH can assert this signal for snoop cycles and interrupt messages. Block Next Request: Used to block the current request bus owner from issuing new requests. This signal is used to dynamically control the processor bus pipeline depth. Priority Agent Bus Request: The (G)MCH is the only Priority Agent on the processor bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the FSB_LOCKB signal was asserted. Bus Request 0: The (G)MCH pulls the processor bus’ FSB_BREQ0B signal low during FSB_CPURSTB. The processors sample this signal on the active-to-inactive transition of FSB_CPURSTB. The minimum setup time for this signal is 4 HCLKs. The minimum hold time is 2 HCLKs and the maximum hold time is 20 HCLKs. FSB_BREQ0B should be tri-stated after the hold time requirement has been satisfied. CPU Reset: The FSB_CPURSTB signal is an output from the (G)MCH. The (G)MCH asserts FSB_CPURSTB while PWROK (PCIRST# from the ICH) is asserted and for approximately 1 ms after RSTINB is de-asserted. The FSB_CPURSTB allows the processors to begin execution in a known state. Data Bus Busy: This signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: This signal indicates that the (G)MCH will terminate the transaction currently being snooped with either a deferred response or with a retry response. FSB_BNRB I/O GTL+ FSB_BPRIB O GTL+ FSB_BREQ0B O GTL+ FSB_CPURSTB O GTL+ FSB_DBSYB I/O GTL+ FSB_DEFERB O GTL+ 36 Datasheet Signal Description Signal Name FSB_DINVB_3:0 Type I/O GTL+ 4x Description Dynamic Bus Inversion: These signals are driven along with the FSB_DB_63:0 signals. They indicate if the associated signals are inverted. FSB_DINVB_3:0 are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16 bit group never exceeds 8. FSB_DINVB_x FSB_DINVB_3 FSB_DINVB_2 FSB_DINVB_1 FSB_DINVB_0 Data Bits FSB_DB_63:48 FSB_DB_47:32 FSB_DB_31:16 FSB_DB_15:0 FSB_DRDYB I/O GTL+ Data Ready: This signal is asserted for each cycle that data is transferred. Host Address Bus: FSB_AB_35:3 connect to the processor address bus. During processor cycles, FSB_AB_35:3 are inputs. The (G)MCH drives FSB_AB_35:3 during snoop cycles on behalf of DMI and PCI-Express-G initiators. FSB_AB_35:3 are transferred at 2x rate. Note that the address is inverted on the processor bus. The values stored in the POC register are driven in these signals by the (G)MCH between PWROK assertion and FSB_CPURSTB de-assertion to allow processor configuration. Host Address Strobe: The source synchronous strobes are used to transfer FSB_AB_31:3 and FSB_REQB_4:0 at the 2x transfer rate. Strobe FSB_ADSTBB_0 FSB_ADSTBB_1 Address Bits FSB_AB_16:3, FSB_REQB_4:0 FSB_AB_31:17 FSB_AB_35:3 I/O GTL+ 2x FSB_ADSTBB_1:0 I/O GTL+ 2x FSB_DB_63:0 I/O GTL+ 4x Host Data: These signals are connected to the processor data bus. Data on FSB_DB_63:0 is transferred at a 4x rate. Note that the data signals may be inverted on the processor bus, depending on the FSB_DINVB_3:0 signals. Datasheet 37 Signal Description Signal Name FSB_DSTBPB_3:0 FSB_DSTBNB_3:0 Type I/O GTL+ 4x Description Differential Host Data Strobes: The differential source synchronous strobes used to transfer FSB_DB_63:0 and FSB_DINVB_3:0 at the 4x transfer rate. These signals are named this way because they are not level sensitive. Data is captured on the falling edge of both strobes. Hence, they are pseudo-differential, and not true differential. Strobe FSB_DSTBPB_2, FSB_DSTBNB_2 FSB_DSTBPB_2, FSB_DSTBNB_2 FSB_DSTBPB_1, FSB_DSTBNB_1 FSB_DSTBPB_0, FSB_DSTBNB_0 Data Bits FSB_DB_63:48, HDINVB_3 FSB_DB_47:32, HDINVB_2 FSB_DB_31:16, HDINVB_1 FSB_DB_15:0, HDINVB_0 FSB_HITB I/O GTL+ Hit: This signal indicates that a caching agent holds an unmodified version of the requested line. Also, driven in conjunction with FSB_HITMB by the target to extend the snoop window. Hit Modified: This signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. Also, driven in conjunction with FSB_HITB to extend the snoop window. Host Lock: All processor bus cycles sampled with the assertion of FSB_LOCKB and FSB_ADSB, until the negation of FSB_LOCKB must be atomic (i.e., no DMI or PCI-Express access to DRAM are allowed when FSB_LOCKB is asserted by the processor). Host Request Command: These signals define the attributes of the request. FSB_REQB_4:0 are transferred at 2x rate. Asserted by the requesting agent during both halves of Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the (G)MCH Host Bridge are defined in the Host Interface section of this document. FSB_HITMB I/O GTL+ FSB_LOCKB I GTL+ FSB_REQB_4:0 I/O GTL+ 2x FSB_TRDYB O GTL+ Host Target Ready: This signal indicates that the target of the processor transaction is able to enter the data transfer phase. 38 Datasheet Signal Description Signal Name FSB_RSB_2:0 Type O GTL+ Description Response Signals: These signals indicate type of response according as shown below: 000 = Idle state 001 = Retry response 010 = Deferred response 011 = Reserved (not driven by (G)MCH) 100 = Hard Failure (not driven by (G)MCH) 101 = No data response 110 = Implicit Writeback 111 = Normal data response FSB_RCOMP I/O A Host RCOMP: This signal is used to calibrate the Host GTL+ I/O buffers. This signal is powered by the Host Interface termination rail (VTT). Connects to FSB_XRCOMP1IN in the package. Slew Rate Compensation: This signal provides compensation for the Host Interface for Rising edges Slew Rate Compensation: This signal provides compensation for the Host Interface for falling edges Host Voltage Swing: These signals provide reference voltages used by the FSB RCOMP circuits. FSB_SWING is used for the signals handled by FSB_RCOMP. Host Reference Voltage: Reference voltage input for the Data signals of the Host GTL interface. Host Reference Voltage: Reference voltage input for the Address, signals of the Host GTL interface. FSB_SCOMP I/O A FSB_SCOMPB I/O A FSB_SWING I/O A FSB_DVREF I/O A FSB_ACCVREF I/O A Datasheet 39 Signal Description 2.2 System Memory (DDR2/DDR3) Channel A Interface Signals Note: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components. Signal Name DDR_A_CK_5:0 Type O SSTL-1.8/1.5 Description SDRAM Differential Clocks • • DDR_A_CKB_5:0 O SSTL-1.8/1.5 • • DDR_A_CSB_3:0 O SSTL-1.8/1.5 O SSTL-1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8 O SSTL-1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8 O SSTL-1.5 I/O SSTL-1.8/1.5 O SSTL-1.8/1.5 I/O SSTL-1.8/1.5 I/O SSTL-1.8/1.5 DDR2: Three per DIMM (5:0) DDR3: Two per DIMM (3:0) DDR2: Three per DIMM (5:0) DDR3: Two per DIMM (3:0) SDRAM Inverted Differential Clocks DDR2/DDR3 Device Rank 3, 2, and 0 chip selects DDR2 Device Rank 1 chip select DDR3 Device Rank 1 Chip Select DDR2/DDR3 Clock Enable (1 per Device Rank) DDR2/DDR3 On Die Termination (1 per Device Rank) DDR2/DDR3 Address Signals 14:1 DDR2 Address Signals 0 DDR3 Address Signal 0 DDR2/DDR3 Bank Select DDR2/DDR3 RAS signal DDR2/DDR3 CAS signal DDR2 Write Enable signal DDR3 Write Enable signal DDR2/DDR3 Data Lines DDR2/DDR3 Data Mask DDR2/DDR3 Data Strobes DDR2/DDR3 Data Strobe Complements DDR3_A_CSB_1 DDR_A_CKE_3:0 DDR_A_ODT_3:0 DDR_A_MA_14:1 DDR_A_MA_0 DDR3_A_MA_0 DDR_A_BS_2:0 DDR_A_RASB DDR_A_CASB DDR_A_WEB DDR3_A_WEB DDR_A_DQ_63:0 DDR_A_DM_7:0 DDR_A_DQS_7:0 DDR_A_DQSB_7:0 40 Datasheet Signal Description 2.3 System Memory (DDR2/DDR3) Channel B Interface Signals Note: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components. Signal Name DDR_B_CK_5:0 Type O SSTL-1.8/1.5 Description SDRAM Differential Clocks • • DDR2: Three per DIMM (5:0) DDR3: Two per DIMM (3:0) DDR_B_CKB_5:0 O SSTL-1.8/1.5 SDRAM Inverted Differential Clocks • • DDR2: Three per DIMM (5:0) DDR3: Two per DIMM (3:0) DDR_B_CSB_3:0 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8 O SSTL-1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 O SSTL-1.8/1.5 I/O SSTL-1.8/1.5 O SSTL-1.8/1.5 I/O SSTL-1.8/1.5 I/O SSTL-1.8/1.5 DDR2/DDR3 Chip Select (1 per Device Rank) DDR2/DDR3 Clock Enable (1 per Device Rank) DDR2/DDR3 Device Rank 2, 1, and 0 On Die Termination DDR2 Device Rank 3 On Die Termination DDR3 Device Rank 3 On Die Termination DDR2/DDR3 Address Signals 14:0 DDR2/DDR3 Bank Select DDR2/DDR3 RAS signal DDR2/DDR3 CAS signal DDR2/DDR3 Write Enable DDR2/DDR3 Data Lines DDR2/DDR3 Data Mask DDR2/DDR3 Data Strobes DDR2/DDR3 Data Strobe Complements DDR_B_CKE_3:0 DDR_B_ODT_2:0 DDR_B_ODT_3 DDR3_B_ODT_3 DDR_B_MA_14:0 DDR_B_BS_2:0 DDR_B_RASB DDR_B_CASB DDR_B_WEB DDR_B_DQ_63:0 DDR_B_DM_7:0 DDR_B_DQS_7:0 DDR_B_DQSB_7:0 Datasheet 41 Signal Description 2.4 System Memory DDR2/DDR3 Miscellaneous Signals Note: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components. Signal Name DDR_RCOMPXPD DDR_RCOMPXPU DDR_RCOMPYPD DDR_RCOMPYPU DDR_VREF DDR3_DRAM_PWROK DDR3_DRAMRSTB Type I/O A I/O A I/O A I/O A I A I O SSTL-1.5 Description DDR2/DDR3 Pull-down RCOMP DDR2/DDR3 Pull-up RCOMP DDR2/DDR3 Pull-down RCOMP DDR2/DDR3 Pull-up RCOMP DDR2/DDR3 Reference Voltage DDR3 VCC_DDR Power OK DDR3 Reset 42 Datasheet Signal Description 2.5 PCI Express* Interface Signals Signal Name PEG_RXN_15:0 PEG_RXP_15:0 PEG_TXN_15:0 PEG_TXP_15:0 EXP_COMPO EXP_COMPI Type I PCI Express* O PCI Express* O A I A Description PCI Express Receive Differential Pair PCI Express Transmit Differential Pair PCI Express Output Current Compensation PCI Express Input Current Compensation 2.6 Controller Link Interface Signals Signal Name CL_DATA Type I/O CMOS CL_CLK I/O CMOS CL_VREF I CMOS CL_RSTB I/O CMOS Controller Link reset Active low (bi-direct) Controller Link External reference voltage Controller Link Bi Directional Clock Description Controller Link Bi Directional Data Datasheet 43 Signal Description 2.7 Analog Display Signals (Intel® 82Q33, GMCH, 82Q33 GMCH, and 82G33 GMCH Only) Signal Name CRT_RED Type O A Description RED Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5 ohm routing impedance, but the terminating resistor to ground will be 75 ohms (e.g., 75 ohm resistor on the board, in parallel with a 75 ohm CRT load). RED# Analog Output: This signal is an analog video output from the internal color palette DAC. It should be shorted to the ground plane. GREEN Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5 ohm routing impedance, but the terminating resistor to ground will be 75 ohms (e.g., 75 ohm resistor on the board, in parallel with a 75 ohm CRT load). GREEN# Analog Output: This signal is an analog video output from the internal color palette DAC. It should be shorted to the ground plane. BLUE Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5 ohm routing impedance, but the terminating resistor to ground will be 75 ohms (e.g., 75 ohm resistor on the board, in parallel with a 75 ohm CRT load). BLUE# Analog Output: This signal is an analog video output from the internal color palette DAC. It should be shorted to the ground plane. Resistor Set: Set point resistor for the internal color palette DAC. CRT Horizontal Synchronization: This signal is used as the horizontal sync (polarity is programmable) or “sync interval”, 3.3 V output CRT Vertical Synchronization: This signal is used as the vertical sync (polarity is programmable) 3.3 V output. Monitor Control Clock: This signal may be used as the DDC_CLK for a secondary multiplexed digital display connector. Monitor Control Data: This signal may be used as the DDC_Data for a secondary multiplexed digital display connector. CRT_REDB O A CRT_GREEN O A CRT_GREENB O A CRT_BLUE O A CRT_BLUEB O A CRT_IREF I/O A CRT_HSYNC O HVCMOS CRT_VSYNC O HVCMOS CRT_DDC_CLK I/O COD CRT_DDC_DATA I/O COD 44 Datasheet Signal Description 2.8 Clocks, Reset, and Miscellaneous Signal Name HPL_CLKINP HPL_CLKINN Type I HCSL Description Differential Host Clock In: These pins receive a differential host clock from the external clock synthesizer. This clock is used by all of the (G)MCH logic that is in the Host clock domain. Differential PCI-Express Clock In: These pins receive a differential 100 MHZ Serial Reference clock from the external clock synthesizer. This clock is used to generate the clocks necessary for the support of PCI-Express and DMI. Display PLL Differential Clock In EXP_CLKINP EXP_CLKINN I HCSL DPL_REFCLKINN DPL_REFCLKINP RSTINB I HCSL I HVIN Reset In: When asserted, this signal will asynchronously reset the (G)MCH logic. This signal is connected to the PCIRST# output of the ICH9. All PCI-Express Graphics Attach output signals and DMI output signals will also tri-state compliant to PCI Express Rev 1.0 specification. This input should have a Schmitt trigger to avoid spurious resets. This signal is required to be 3.3 V tolerant. CL_PWROK I/O CMOS CL Power OK: When asserted, CL_PWROK is an indication to the (G)MCH that 1.25 V VCC_CL power supply (Manageability well) has been stable for at least 10 us. PCI Express* Static Lane Reversal/Form Factor Selection: (G)MCH’s PCI Express lane numbers are reversed to differentiate BTX and ATX form factors. 0 = (G)MCH PCI Express lane numbers are reversed (BTX) 1 = Normal operation (ATX) EXP_SLR I CMOS TCEN I CMOS TLS Confidentiality Enable. Enable/disable TLS Confidentiality. This signal has an internal pull-up. 0 = TLS Confidentiality is disabled. 1 = TLS Confidentiality is enabled. BSEL2 BSEL1 BSEL0 MTYPE I CMOS Bus Speed Select: At the assertion of PWROK, the value sampled on these pins determines the expected frequency of the bus. Theses pins must also be routed to probe points or to the XDP connector when applicable. Memory Type: This signal determines DDR2 or DDR3 board 0 = DDR3 (82G33 and 82P35 (G)MCH Only) 1 = DDR2 I CMOS Datasheet 45 Signal Description Signal Name EXP_EN Type I CMOS Description Concurrent PCI Express Port Enable: This signal selects Concurrent SDVO and PCI Express 0 = Only SDVO or PCI Express is operational. 1 = Both SDVO and PCI Express are operating simultaneously via the PCI Express port. NOTES: For the 82P35 MCH, this signal should be pulled low. PWROK I/O HVIN Power OK: When asserted, PWROK is an indication to the (G)MCH that core power has been stable for at least 10 us. ICH Sync: Maintains synchronization between (G)MCH and ICH9. This signal is connected to the MCH_SYNC# signal on the ICH. All Z Test: ALLZTEST is used for chipset Bed of Nails testing to execute All Z Test. XOR Chain Test: XORTEST is used for Chipset Bed of Nails testing to execute XOR Chain Test. XORTEST (Ball F20) 0 0 ALLZTEST (Ball K20) 0 1 Description Reserved XORTEST. Used for chipset Bed of Nails Testing to execute XOR Chain Test. All pins tri-stated. Used for chipset testing. Normal ICH_SYNCB O HVCMOS ALLZTEST/ XORTEST I/O CMOS 1 1 TEST[2:0] I/O A 0 1 In Circuit Test: These pins should be connected to test points on the motherboard. They are internally shorted to the package ground and can be used to determine if the corner balls on the (G)MCH are correctly soldered down to the motherboard. These pins should NOT connect to ground on the motherboard. If TEST[2:0] are not going to be used, they should be left as no connects. 2.9 Direct Media Interface Signal Name DMI_RXP_3:0 DMI_RXN_3:0 DMI_TXP_3:0 DMI_TXN_3:0 Type I DMI O DMI Description Direct Media Interface: Receive differential pair (RX). These signals are the (G)MCH-ICH9 serial interface input. Direct Media Interface: Transmit differential pair (TX). These signals are the (G)MCH-ICH9 serial interface output. 46 Datasheet Signal Description 2.10 Serial DVO Interface (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Most of these signals are multiplexed with PCI Express signals. SDVO_CTTCLK and SDVO_CTRLDATA are the only unmultiplexed signals on the SDVO interface. SDVO is mapped to lanes 0-7 or lanes 15-8 of the PEG port depending on the PCI Express Static Lane Reversal and SDVO/PCI Express Coexistence straps. The lower 8 lanes are used when both straps are either asserted or not asserted. Otherwise, the upper 8 lanes are used. Signal Name SDVOB_CLK- Type O PCI Express* Description Serial Digital Video Channel B Clock Complement SDVOB_CLK+ O PCI Express* Serial Digital Video Channel B Clock SDVOB_RED- O PCI Express* Serial Digital Video Channel C Red Complement SDVOB_RED+ O PCI Express* Serial Digital Video Channel C Red SDVOB_GREEN- O PCI Express* Serial Digital Video Channel B Green Complement SDVOBGREEN+ O PCI Express* Serial Digital Video Channel B Green SDVOB_BLUE- O PCI Express* Serial Digital Video Channel B Blue Complement SDVOB_BLUE+ O PCI Express* Serial Digital Video Channel B Blue SDVOC_RED- O PCI Express* Serial Digital Video Channel C Red Complement SDVOC_RED+ O PCI Express* Serial Digital Video Channel C Red Channel B Alpha Serial Digital Video Channel C Green Complement SDVOC_GREEN- O PCI Express* SDVOC_GREEN+ O PCI Express* Serial Digital Video Channel C Green SDVOC_BLUE- O PCI Express* Serial Digital Video Channel C Blue Complement Datasheet 47 Signal Description Signal Name SDVOC_BLUE+ Type O PCI Express* Description Serial Digital Video Channel C Blue SDVOC_CLK- O PCI Express* Serial Digital Video Channel C Clock Complement SDVOC_CLK+ O PCI Express* Serial Digital Video Channel C Clock SDVO_TVCLKIN- I PCI Express* Serial Digital Video TVOUT Synchronization Clock Complement Serial Digital Video TVOUT Synchronization Clock SDVO_TVCLKIN+ I PCI Express* SDVOB_INT- I PCI Express* Serial Digital Video Input Interrupt Complement SDVOB_INT+ I PCI Express* Serial Digital Video Input Interrupt SDVOC_INT- I PCI Express* Serial Digital Video Input Interrupt Complement SDVOC_INT+ I PCI Express* Serial Digital Video Input Interrupt SDVO_STALL- I PCI Express* Serial Digital Video Field Stall Complement SDVO_STALL+ I PCI Express* Serial Digital Video Field Stall SDVO_CTRLCLK I/O COD Serial Digital Video Device Control Clock SDVO_CTRLDATA I/O COD Serial Digital Video Device Control Data NOTE: Table 2-1 shows the mapping of SDVO signals to the PCI Express* lanes in the various possible configurations as determined by the strapping configuration. Note that slotreversed configurations do not apply to the Integrated-graphics only variants. 48 Datasheet Signal Description Table 2-1. SDVO/PCI Express* Signal Mapping Configuration-wise Mapping SDVO Signal SDVO Only – Normal SDVO Only – Reversed Concurrent SDVO and PCI Express* – Normal PEG_TXN15 PEG_TXP15 PEG_TXN14 PEG_TXP14 PEG_TXN13 PEG_TXP13 PEG_TXN12 PEG_TXP12 PEG_TXN11 PEG_TXP11 PEG_TXN10 PEG_TXP10 PEG_TXN9 PEG_TXP9 PEG_TXN8 PEG_TXP8 PEG_RXN15 PEG_RXP15 PEG_RXN14 PEG_RXP14 PEG_RXN10 PEG_RXP10 PEG_RXN13 PEG_RXP13 Concurrent SDVO and PCI Express* – Reversed PEG_TXN0 PEG_TXP0 PEG_TXN1 PEG_TXP1 PEG_TXN2 PEG_TXP2 PEG_TXN3 PEG_TXP3 PEG_TXN4 PEG_TXP4 PEG_TXN5 PEG_TXP5 PEG_TXN6 PEG_TXP6 PEG_TXN7 PEG_TXP7 PEG_RXN0 PEG_RXP0 PEG_RXN1 PEG_RXP1 PEG_RXN5 PEG_RXP5 PEG_RXN2 PEG_RXP2 SDVOB_RED# SDVOB_RED SDVOB_GREEN# SDVOB_GREEN SDVOB_BLUE# SDVOB_BLUE SDVOB_CLKN SDVOB_CLKP SDVOC_RED# SDVOC_RED SDVOC_GREEN# SDVOC_GREEN SDVOC_BLUE# SDVOC_BLUE SDVOC_CLKN SDVOC_CLKP SDVO_TVCLKIN# SDVO_TVCLKIN SDVOB_INT# SDVOB_INT SDVOC_INT# SDVOC_INT SDVO_FLDSTALL# SDVO_FLDSTALL PEG_TXN0 PEG_TXP0 PEG_TXN1 PEG_TXP1 PEG_TXN2 PEG_TXP2 PEG_TXN3 PEG_TXP3 PEG_TXN4 PEG_TXP4 PEG_TXN5 PEG_TXP5 PEG_TXN6 PEG_TXP6 PEG_TXN7 PEG_TXP7 PEG_RXN0 PEG_RXP0 PEG_RXN1 PEG_RXP1 PEG_RXN5 PEG_RXP5 PEG_RXN2 PEG_RXP2 PEG_TXN15 PEG_TXP15 PEG_TXN14 PEG_TXP14 PEG_TXN13 PEG_TXP13 PEG_TXN12 PEG_TXP12 PEG_TXN11 PEG_TXP11 PEG_TXN10 PEG_TXP10 PEG_TXN9 PEG_TXP9 PEG_TXN8 PEG_TXP8 PEG_RXN15 PEG_RXP15 PEG_RXN14 PEG_RXP14 PEG_RXN10 PEG_RXP10 PEG_RXN13 PEG_RXP13 Datasheet 49 Signal Description 2.11 Power and Grounds Name VCC VTT VCC_EXP VCC_DDR VCC_CKDDR VCC3_3 VCCAPLL_EXP VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPL VCCA_DAC VCCD_CRT VCCDQ_CRT VCC_CL VSS Voltage 1.25 V 1.05V/1.2 V 1.25 V 1.8V/1.5V 1.8V/1.5V 3.3 V 1.25 V 1.25 V 1.25 V 1.25 V 1.25 V 3.3 V 1.5/1.8 V 1.5/1.8V 1.25 V 0V Core Power Processor System Bus Power PCI Express* and DMI Power DDR2/DDR3 System Memory Power DDR2/DDR3 System Clock Memory Power 3.3 V CMOS Power PCI Express PLL Analog Power Display PLL A Analog Power. Display PLL B Analog Power. Host PLL Analog Power System Memory PLL Analog Power Display DAC Analog Power Display Digital Supply Power CRTDAC Power Controller Link Aux Power Ground Description § 50 Datasheet System Address Map 3 System Address Map The (G)MCH supports 64 GB (36 bit) of host address space and 64 KB+3 of addressable I/O space. There is a programmable memory address space under the 1 MB region that is divided into regions which can be individually controlled with programmable attributes such as Disable, Read/Write, Write Only, or Read Only. Attribute programming is described in the Register Description section. This section focuses on how the memory space is partitioned and what the separate memory regions are used for. I/O address space has a simpler mapping and is explained in Section 3.10. Note: Address mapping information for the Integrated Graphics Device applies to the 82Q35, 82Q33, and 82G33 GMCH only. The 82P35 MCH does not have an IGD. The (G)MCH supports PEG port upper pre-fetchable base/limit registers. This allows the PEG unit to claim IO accesses above 36 bit, complying with the PCI Express Specification. Addressing of greater than 8 GB is allowed on either the DMI Interface or PCI Express interface. The (G)MCH supports a maximum of 8 GB of DRAM. No DRAM memory will be accessible above 8 GB. When running in internal graphics mode (82Q35/82Q33/82G33 GMCH only), writes to GMADR range linear range are supported. Write accesses to linear regions are supported from DMI only. Write accesses to tileX and tileY regions are not supported from DMI or the PEG port. GMADR read accesses are not supported from either DMI or PEG. In the following sections, it is assumed that all of the compatibility memory ranges reside on the DMI Interface. The exception to this rule is VGA ranges, which may be mapped to PCI-Express, DMI, or to the internal graphics device (IGD). In the absence of more specific references, cycle descriptions referencing PCI should be interpreted as the DMI Interface/PCI, while cycle descriptions referencing PCI Express or IGD are related to the PCI Express bus or the internal graphics device respectively. The (G)MCH does not remap APIC or any other memory spaces above TOLUD (Top of Low Usable DRAM). The TOLUD register is set to the appropriate value by BIOS. The reclaim base/reclaim limit registers remap logical accesses bound for addresses above 4 GB onto physical addresses that fall within DRAM. Datasheet 51 System Address Map The Address Map includes a number of programmable ranges: • Device 0 ⎯ PXPEPBAR – Express port registers. Necessary for setting up VC1 as an isochronous channel using time based weighted round robin arbitration. (4 KB window) ⎯ MCHBAR – Memory mapped range for internal (G)MCH registers. For example, memory buffer register controls. (16 KB window) ⎯ PCIEXBAR – Flat memory-mapped address spaced to access device configuration registers. This mechanism can be used to access PCI configuration space (0-FFh) and Extended configuration space (100h–FFFh) for PCI Express devices. This enhanced configuration access mechanism is defined in the PCI Express specification. (64 MB, 128 MB, or 256 MB window). ⎯ DMIBAR –This window is used to access registers associated with the Direct Media Interface (DMI) register memory range. (4 KB window) ⎯ GGCGMS (82Q35/82Q33/82G33 GMCH only) – GMCH graphics control register, Graphics Mode Select. GGCGMS is used to select the amount of main memory that is pre-allocated to support the internal graphics device in VGA (non-linear) and Native (linear) modes. (0–256 MB options). ⎯ GGCGGMS (82Q35/82Q33/82G33 GMCH only) – GMCH graphics control register, GTT Graphics Memory Size. GGCGGMS is used to select the amount of main memory that is pre-allocated to support the Internal Graphics Translation Table. (0–2 MB options). • Device 1 ⎯ MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window. ⎯ PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window. ⎯ PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access window ⎯ IOBASE1/IOLIMIT1 – PCI Express port IO access window. • Device 2, Function 0 (82Q35/82Q33/82G33 GMCH only) ⎯ MMADR – IGD registers and internal graphics instruction port. (512 KB window) ⎯ IOBAR – IO access window for internal graphics. Though this window address/data register pair, using I/O semantics, the IGD and internal graphics instruction port registers can be accessed. Note, this allows accessing the same registers as MMADR. In addition, the IOBAR can be used to issue writes to the GTTADR table. ⎯ GMADR – Internal graphics translation window. (128 MB, 256 MB or 512 MB window). ⎯ GTTADR – Internal graphics translation table location. (1 MB window). Note that the Base of GTT stolen Memory register (Device 0 A8) indicates the physical address base which is 1 MB aligned. • Device 2, Function 1 (82Q35/82Q33/82G33 GMCH only) ⎯ MMADR – Function 1 IGD registers and internal graphics instruction port. (512 KB window) • Device 3, Function 0 ⎯ EPHECIBAR – Function 0 HECI memory-mapped registers. (16 B window) 52 Datasheet System Address Map • MCHBAR ⎯ GFXVTBAR – Memory-mapped window to Graphics VT remap engine registers. (4 KB window) ⎯ DMIVC1BAR – Memory-mapped window to DMI VC1 VT remap engine registers. (4 KB window) ⎯ VTMEBAR – Memory-mapped window to ME VT remap engine registers (4 KB window) ⎯ VTDPVC0BAR – Memory-mapped window to PEG/DMI VC0 VT remap engine registers. (4 KB window) The rules for the above programmable ranges are: 1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or system designers' responsibility to limit memory population so that adequate PCI, PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memory space can be allocated. In the case of overlapping ranges with memory, the memory decode will be given priority. This is an Intel® TXT requirement. It is necessary to get Intel® TXT protection checks, avoiding potential attacks. There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges. Accesses to overlapped ranges may produce indeterminate results. The only peer-to-peer cycles allowed below the top of Low Usable memory (register TOLUD) are DMI Interface to PCI Express VGA range writes. Note that peer-to-peer cycles to the Internal Graphics VGA range are not supported. 2. 3. 4. 5. Datasheet 53 System Address Map Figure 3-1 represents system memory address map in a simplified form. Figure 3-1. System Address Ranges Host/System View 64 GB PCI Memory Address Range (subtractively decoded to DMI Reclaim Limit = Reclaim Base +X (64 MB Aligned) Reclaim Base (64 MB Aligned) Main Memory Address Range 4 GB PCI Memory Address Range (subtractively decoded to DMI) TSEG X Physical Memory (DRAM Controller View) Device 3 Device 1 Bars Device 0 Bars TOM Main Memory Reclaim Address Range EP Stolen Base EP-UMA (1 – 64 MB) 0 – 63 MB Unusable 64 MB Aligned 1 MB Aligned 64 MB Aligned Independently Programmable Non-Overlapping Windows TOUUD Base OS Visible > 4 GB M HBA Device 3 Device 2 Device 1 Bars Device 0 GGC (GFX Stolen Mem) Device 0 Bars TOLUD Base (64 MB Aligned) OS Invisible Reclaim GFX Stolen (1 – 64 MB) TSEG (0 – 8 MB) 64 MB Aligned for Reclaim 1 MB Aligned 1 MB Aligned Independently Programmable Non-Overlapping Windows Main Memory Address Range OS Visible < 4 GB 1 MB Legacy Address Range Memap_Sys_Addr_Ranges 0 NOTE: 1. References to Internal Graphics Device address ranges are for the 82Q35/82Q33/82G33 GMCH only. 54 Datasheet System Address Map 3.1 Legacy Address Range This area is divided into the following address regions: • 0 – 640 KB – DOS Area • 640 – 768 KB – Legacy Video Buffer Area • 768 – 896 KB in 16 KB sections (total of 8 sections) – Expansion Area • 896 – 960 KB in 16 KB sections (total of 4 sections) – Extended System BIOS Area • 960 KB – 1 MB Memory – System BIOS Area Figure 3-2. DOS Legacy Address Range 000F_FFFFh System BIOS (Upper) 64 KB 000F_0000h 000E_FFFFh 000E_0000h 000D_FFFFh Extended System BIOS (Lower) 64 KB (16 KB x 4) 1 MB 960 KB 896 KB Expansion Area 128 KB (16 KB x 8) 000C_0000h 000B_FFFFh Legacy Video Area (SMM Memory) 128 KB 000A_0000h 0009_FFFFh 640 KB 768 KB DOS Area 0000_0000h MemMap_Legacy Datasheet 55 System Address Map 3.1.1 DOS Range (0h – 9_FFFFh) The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main memory controlled by the (G)MCH. 3.1.2 Legacy Video Area (A_0000h – B_FFFFh) The legacy 128 KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh) can be mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMI Interface. The appropriate mapping depends on which devices are enabled and the programming of the VGA steering bits. Based on the VGA steering bits, priority for VGA mapping is constant. The (G)MCH always decodes internally mapped devices first. Internal to the GMCH, decode precedence is always given to IGD. The (G)MCH always positively decodes internally mapped devices, namely the IGD and PCIExpress. Subsequent decoding of regions mapped to PCI Express or the DMI Interface depends on the Legacy VGA configuration bits (VGA Enable and MDAP). This region is also the default for SMM space. Compatible SMRAM Address Range (A_0000h – B_FFFFh) When compatible SMM space is enabled, SMM-mode processor accesses to this range are routed to physical system DRAM at 000A 0000h – 000B FFFFh. Non-SMM-mode processor accesses to this range are considered to be to the Video Buffer Area as described above. PCI Express and DMI originated cycles to enabled SMM space are not allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the VGA device. PCI Express and DMI initiated cycles are attempted as Peer cycles, and will master abort on PCI if no external VGA device claims them. Monochrome Adapter (MDA) Range (B_0000h – B_7FFFh) Legacy support requires the ability to have a second graphics controller (monochrome) in the system. Accesses in the standard VGA range are forwarded to IGD, PCI Express, or the DMI Interface (depending on configuration bits). Since the monochrome adapter may be mapped to anyone of these devices, the (G)MCH must decode cycles in the MDA range (000B_0000h – 000B_7FFFh) and forward either to IGD, PCI Express, or the DMI Interface. This capability is controlled by a VGA steering bits and the legacy configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the (G)MCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to the either IGD, PCI-Express, and/or the DMI Interface. PEG 16-bit VGA Decode The PCI to PCI Bridge Architecture Specification Revision 1.2 requires that 16-bit VGA decode be a feature. 56 Datasheet System Address Map 3.1.3 Expansion Area (C_0000h – D_FFFFh) This 128 KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight 16 KB segments. Each segment can be assigned one of four Read/Write states: readonly, write-only, read/write, or disabled. Typically, these blocks are mapped through (G)MCH and are subtractive decoded to ISA space. Memory that is disabled is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. Table 3-1. Expansion Area Memory Segments Memory Segments 0C0000h – 0C3FFFh 0C4000h – 0C7FFFh 0C8000h – 0CBFFFh 0CC000h – 0CFFFFh 0D0000hH – 0D3FFFh 0D4000h – 0D7FFFh 0D8000h – 0DBFFFh 0DC000h – 0DFFFFh Attributes WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE Comments Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS 3.1.4 Extended System BIOS Area (E_0000h-E_FFFFh) This 64 KB area (000E_0000h – 000E_FFFFh) is divided into four 16 KB segments. Each segment can be assigned independent read and write attributes so it can be mapped either to main DRAM or to DMI Interface. Typically, this area is used for RAM or ROM. Memory segments that are disabled are not remapped elsewhere. Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. Table 3-2. Extended System BIOS Area Memory Segments Memory Segments 0E0000h – 0E3FFFh 0E4000h – 0E7FFFh 0E8000h – 0EBFFFh 0EC000h – 0EFFFFh Attributes WE RE WE RE WE RE WE RE Comments BIOS Extension BIOS Extension BIOS Extension BIOS Extension Datasheet 57 System Address Map 3.1.5 System BIOS Area (F_0000h-F_FFFFh) This area is a single 64 KB segment (000F_0000h – 000F_FFFFh). This segment can be assigned read and write attributes. It is by default (after reset) read/write disabled and cycles are forwarded to DMI Interface. By manipulating the read/write attributes, the (G)MCH can “shadow” BIOS into the main DRAM. When disabled, this segment is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. Table 3-3. System BIOS Area Memory Segments Memory Segments 0F0000h – 0FFFFFh Attributes WE RE Comments BIOS Area 3.1.6 PAM Memory Area Details The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM memory area. The (G)MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all memory residing on DMI should be set as non-cacheable, there will normally not be IWB cycles targeting DMI. However, DMI becomes the default target for processor and DMI originated accesses to disabled segments of the PAM region. If the MTRRs covering the PAM regions are set to WB or RD it is possible to get IWB cycles targeting DMI. This may occur for processor originated cycles and for DMI originated cycles to disabled PAM regions. For example, say that a particular PAM region is set for “Read Disabled” and the MTRR associated with this region is set to WB. A DMI master generates a memory read targeting the PAM region. A snoop is generated on the FSB and the result is an IWB. Since the PAM region is “Read Disabled” the default target for the Memory Read becomes DMI. The IWB associated with this cycle will cause the (G)MCH to hang. Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. 58 Datasheet System Address Map 3.2 Main Memory Address Range (1MB – TOLUD) This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the (G)MCH (as programmed in the TOLUD register). All accesses to addresses within this range will be forwarded by the (G)MCH to the DRAM unless it falls into the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory. Figure 3-3. Main Memory Address Range 8 GB Main Memory FFFF_FFFFh . . . . . FLASH APIC LT PCI Memory Range TSEG (1MB/2MB/8MB, optional) 4 GB Main Memory 0100_0000h ISA Hole (optional) 00F0_0000h Main Memory 0010_0000h DOS Compatibility Memory 0h Datasheet 59 System Address Map 3.2.1 ISA Hole (15 MB-16 MB) A hole can be created at 15 MB – 16 MB as controlled by the fixed hole enable in Device 0 space. Accesses within this hole are forwarded to the DMI Interface. The range of physical DRAM memory disabled by opening the hole is not remapped to the top of the memory – that physical DRAM space is not accessible. This 15 MB – 16 MB hole is an optionally enabled ISA hole. Video accelerators originally used this hole. It is also used by validation and customer SV teams for some of their test cards. That is why it is being supported. There is no inherent BIOS request for the 15 MB – 16 MB window. 3.2.2 TSEG TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory, which is at the top of Low Usable physical memory (TOLUD). SMM-mode processor accesses to enabled TSEG access the physical DRAM at the same address. Nonprocessor originated accesses are not allowed to SMM space. PCI Express, DMI, and Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for writes. When the extended SMRAM space is enabled, processor accesses to the TSEG range without SMM attribute or without WB attribute are also forwarded to memory as invalid accesses (see table 8). Non-SMM-mode Write Back cycles that target TSEG space are completed to DRAM for cache coherency. When SMM is enabled the maximum amount of memory available to the system is equal to the amount of physical DRAM minus the value in the TSEG register which is fixed at 1 MB, 2 MB, or 8 MB. 3.2.3 Pre-allocated Memory Voids of physical addresses that are not accessible as general system memory and reside within system memory address range (< TOLUD) are created for SMM-mode, legacy VGA graphics compatibility, and GFX GTT stolen memory. It is the responsibility of BIOS to properly initialize these regions. The following table details the location and attributes of the regions. Enabling/Disabling these ranges are described in the (G)MCH Control Register Device 0 (GCC). Table 3-4. Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB GTT stolen and 1 MB TSEG Memory Segments 0000_0000h – 03CF_FFFFh 03D0_0000h – 03DF_FFFFh 03E0_0000h – 03EF_FFFFh Attributes R/W SMM Mode Only processor Reads R/W Comments Available System Memory 61 MB TSEG Address Range & Pre-allocated Memory Pre-allocated Graphics VGA memory. 1 MB (or 4/8/16/32/64/128/256 MB) when IGD is enabled on the 82Q35/82Q33/82G33 GMCH. R/W Pre-allocated Graphics GTT stolen memory. 1 MB (or 2 MB) when IGD is enabled on the 82Q35/82Q33/82G33 GMCH. 03F0_0000h – 03FF_FFFFh 60 Datasheet System Address Map 3.3 PCI Memory Address Range (TOLUD – 4GB) This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally mapped to the DMI Interface. Device 0 exceptions are: • Addresses decoded to the Express port registers (PXPEPBAR) • Addresses decoded to the memory mapped range for internal (G)MCH registers (MCHBAR) • Addresses decoded to the flat memory-mapped address spaced to access device configuration registers (PCIEXBAR) • Addresses decoded to the registers associated with the Direct Media Interface (DMI) register memory range. (DMIBAR) With PCI Express port, there are two exceptions to this rule. • Addresses decoded to the PCI Express Memory Window defined by the MBASE1 and MLIMIT1 registers are mapped to PCI Express. • Addresses decoded to the PCI Express prefetchable Memory Window defined by the PMBASE1 and PMLIMIT1 registers are mapped to PCI Express. In integrated graphics configurations, there are exceptions to this rule: • Addresses decoded to the IGD registers and internal graphics instruction port (Function 0 MMADR, Function 1 MMADR) • Addresses decode to the internal graphics translation window (GMADR) • Addresses decode to the Internal graphics translation table (GTTADR) In an Intel ME configuration, there are exceptions to this rule: • Addresses decoded to the ME Keyboard and Text MMIO range (EPKTBAR) • Addresses decoded to the ME HECI MMIO range (EPHECIBAR) • Addresses decoded to the ME HECI2 MMIO range (EPHECI2BAR) In a VT enable configuration, there are exceptions to this rule: • Addresses decoded to the memory mapped window to Graphics VT remap engine registers (GFXVTBAR) • Addresses decoded to the memory mapped window to DMI VC1 VT remap engine registers (DMIVC1BAR) • Addresses decoded to the memory mapped window to ME VT remap engine registers (VTMEBAR) Addresses decoded to the memory-mapped window to PEG/DMI VC0 VT remap engine registers (VTDPVC0BAR) Some of the MMIO Bars may be mapped to this range or to the range above TOUUD. Datasheet 61 System Address Map There are sub-ranges within the PCI Memory address range defined as APIC Configuration Space, FSB Interrupt Space, and High BIOS Address Range. The exceptions listed above for internal graphics and the PCI Express ports MUST NOT overlap with these ranges. Figure 3-4. PCI Memory Address Range FFFF_FFFFh FFE0_0000h DMI Interface (subtractive decode) FEF0_0000h FSB Interrupts FEE0_0000h FED0_0000h FEC8_0000h I/O APIC FEC0_0000h DMI Interface (subtractive decode) F000_0000h 4 GB – 256 MB PCI Express Configuration Space E000_0000h 4 GB – 512 MB BARs, Internal Graphics ranges, PCI Express Port, CHAPADR could be here. TOLUD MemMap_PCI 4 GB High BIOS 4 GB – 2 MB 4 GB – 17 MB 4 GB – 18 MB 4 GB – 19 MB DMI Interface (subtractive decode) Local (Processor) APIC Optional HSEG FEDA_0000h to FEDB_FFFFh 4 GB – 20 MB Possible address range/size (not ensured) DMI Interface (subtractive decode) 62 Datasheet System Address Map 3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the ICH9 portion of the chipset, but may also exist as stand-alone components like PXH. The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated in the system. Since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh) are always forwarded to DMI. The (G)MCH optionally supports additional I/O APICs behind the PCI Express “Graphics” port. When enabled via the PCI Express Configuration register (Device 1 Offset 200h), the PCI Express port will positively decode a subset of the APIC configuration space – specifically FEC8_0000h thru FECF_FFFFh. Memory request to this range would then be forwarded to the PCI Express port. This mode is intended for the entry Workstation/Server SKU of the (G)MCH, and would be disabled in typical Desktop systems. When disabled, any access within entire APIC Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI. 3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window to SMM Memory. It is sometimes called the High SMM memory space. SMMmode processor accesses to the optionally enabled HSEG are remapped to 000A_0000h – 000B_FFFFh. Non-SMM-mode processor accesses to enabled HSEG are considered invalid and are terminated immediately on the FSB. The exceptions to this rule are Non-SMM-mode Write Back cycles which are remapped to SMM space to maintain cache coherency. PCI Express and DMI originated cycles to enabled SMM space are not allowed. Physical DRAM behind the HSEG transaction address is not remapped and is not accessible. All cacheline writes with WB attribute or Implicit write backs to the HSEG range are completed to DRAM like an SMM cycle. 3.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any device on PCI Express or DMI may issue a Memory Write to 0FEEx_xxxxh. The (G)MCH will forward this Memory Write along with the data to the FSB as an Interrupt Message Transaction. The (G)MCH terminates the FSB transaction by providing the response and asserting HTRDYB. This memory write cycle does not go to DRAM. 3.3.4 High BIOS Area The top 2 MB (FFE0_0000h – FFFF_FFFFh) of the PCI Memory Address Range is reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system BIOS. The processor begins execution from the High BIOS after reset. This region is mapped to DMI Interface so that the upper subset of this region aliases to 16 MB – 256 KB range. The actual address space required for the BIOS is Datasheet 63 System Address Map less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be considered. 3.4 Main Memory Address Space (4 GB to TOUUD) The (G)MCH supports 36 bit addressing. The maximum main memory size supported is 8 GB total DRAM memory. A hole between TOLUD and 4 G occurs when main memory size approaches 4 GB or larger. As a result, TOM, and TOUUD registers and RECLAIMBASE/RECLAIMLIMIT registers become relevant. The new reclaim configuration registers exist to reclaim lost main memory space. The greater than 32 bit reclaim handling will be handled similar to other (G)MCHs. Upstream read and write accesses above 36-bit addressing will be treated as invalid cycles by PEG and DMI. Top of Memory The “Top of Memory” (TOM) register reflects the total amount of populated physical memory. This is NOT necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory-mapped I/O above TOM). TOM is used to allocate the Intel Management Engine's stolen memory. The Intel ME stolen size register reflects the total amount of physical memory stolen by the Intel ME. The ME stolen memory is located at the top of physical memory. The ME stolen memory base is calculated by subtracting the amount of memory stolen by the Intel ME from TOM. The Top of Upper Usable DRAM (TOUUD) register reflects the total amount of addressable DRAM. If reclaim is disabled, TOUUD will reflect TOM minus Intel ME stolen size. If reclaim is enabled, then it will reflect the reclaim limit. Also, the reclaim base will be the same as TOM minus ME stolen memory size to the nearest 64 MB alignment. TOLUD register is restricted to 4 GB memory (A[31:20]), but the (G)MCH can support up to 16 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD register helps identify the address range in between the 4 GB boundary and the top of physical memory. This identifies memory that can be directly accessed (including reclaim address calculation) which is useful for memory access indication, early path indication, and trusted read indication. When reclaim is enabled, TOLUD must be 64 MB aligned, but when reclaim is disabled, TOLUD can be 1 MB aligned. C1DRB3 cannot be used directly to determine the effective size of memory as the values programmed in the DRBs depend on the memory mode (stacked, interleaved). The Reclaim Base/Limit registers also can not be used because reclaim can be disabled. The C0DRB3 register is used for memory channel identification (channel 0 vs. channel 1) in the case of stacked memory. 64 Datasheet System Address Map 3.4.1 Memory Re-claim Background The following are examples of Memory Mapped IO devices are typically located below 4 GB: • • • • • • • • • High BIOS HSEG TSEG Graphics stolen XAPIC Local APIC FSB Interrupts Mbase/Mlimit Memory-mapped I/O space that supports only 32 B addressing The (G)MCH provides the capability to re-claim the physical memory overlapped by the Memory Mapped IO logical address space. The (G)MCH re-maps physical memory from the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an equivalent sized logical address range located just below the Intel ME's stolen memory. 3.4.2 Memory Reclaiming An incoming address (referred to as a logical address) is checked to see if it falls in the memory re-map window. The bottom of the re-map window is defined by the value in the RECLAIMBASE register. The top of the re-map window is defined by the value in the RECLAIMLIMIT register. An address that falls within this window is reclaimed to the physical memory starting at the address defined by the TOLUD register. The TOLUD register must be 64 MB aligned when RECLAIM is enabled, but can be 1 MB aligned when reclaim is disabled. 3.5 PCI Express* Configuration Address Space There is a device 0 register, PCIEXBAR, that defines the base address for the configuration space associated with all devices and functions that are potentially a part of the PCI Express root complex hierarchy. The size of this range is programmable for the (G)MCH. BIOS must assign this address range such that it will not conflict with any other address ranges. See Chapter 6 for more details. Datasheet 65 System Address Map 3.6 PCI Express* Graphics Attach (PEG) The (G)MCH can be programmed to direct memory accesses to the PCI Express interface when addresses are within either of two ranges specified via registers in (G)MCH’s Device 1 configuration space. • The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers. • The second range is controlled via the Pre-fetchable Memory Base (PMBASE) and Pre-fetchable Memory Limit (PMLIMIT) registers. Conceptually, address decoding for each range follows the same basic concept. The top 12 bits of the respective Memory Base and Memory Limit registers correspond to address bits A[31:20] of a memory address . For the purpose of address decoding, the (G)MCH assumes that address bits A[19:0] of the memory base are zero and that address bits A[19:0] of the memory limit address are FFFFFh. This forces each memory address range to be aligned to 1MB boundary and to have a size granularity of 1 MB. The (G)MCH positively decodes memory accesses to PCI Express memory address space as defined by the following equations: Memory_Base_Address ≤ Address ≤ Memory_Limit_Address Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address The window size is programmed by the plug-and-play configuration software. The window size depends on the size of memory claimed by the PCI Express device. Normally these ranges will reside above the Top-of-Low Usable-DRAM and below High BIOS and APIC address ranges. They MUST reside above the top of low memory (TOLUD) if they reside below 4 GB and MUST reside above top of upper memory (TOUUD) if they reside above 4 GB or they will steal physical DRAM memory space. It is essential to support a separate Pre-fetchable range in order to apply USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining. Note that the (G)MCH Device 1 memory range registers described above are used to allocate memory address space for any PCI Express devices sitting on PCI Express that require such a window. The PCICMD1 register can override the routing of memory accesses to PCI Express. In other words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the memory base/limit and pre-fetchable base/limit windows. The upper PMUBASE1/PMULIMIT1 registers have been implemented for PCI Express Specification compliance. The (G)MCH locates MMIO space above 4 GB using these registers. 66 Datasheet System Address Map 3.7 Graphics Memory Address Ranges (Intel® 82Q35, 82Q33, and 82G33 (G)MCH Only) The (G)MCH can be programmed to direct memory accesses to IGD when addresses are within any of five ranges specified via registers in (G)MCH’s Device 2 configuration space. • The Memory Map Base Register (MMADR) is used to access graphics control registers. • The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory allocated via the graphics translation table. • The Graphics Translation Table Base Register (GTTADR) is used to access the translation table. These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC address ranges. They MUST reside above the top of memory (TOLUD) and below 4 GB so they do not steal any physical DRAM memory space. GMADR is a Prefetchable range in order to apply USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining. 3.8 System Management Mode (SMM) System Management Mode uses main memory for System Management RAM (SMM RAM). The (G)MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management RAM space provides a memory area that is available for the SMI handlers and code and data storage. This memory resource is normally hidden from the system OS so that the processor has immediate access to this memory space upon entry to SMM. The (G)MCH provides three SMRAM options: • Below 1 MB option that supports compatible SMI handlers. • Above 1 MB option that allows new SMI handlers to execute with write-back cacheable SMRAM. • Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. For the 82Q35/82Q33/82G33, the TSEG area lies below IGD stolen memory. The above 1 MB solutions require changes to compatible SMRAM handlers code to properly execute above 1 MB. Note: DMI Interface and PCI Express masters are not allowed to access the SMM space. Datasheet 67 System Address Map 3.8.1 SMM Space Definition SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed SMM space is defined as the range of bus addresses used by the processor to access SMM space. DRAM SMM space is defined as the range of physical DRAM memory locations containing the SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible, High and TSEG. The Compatible and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space is the same address range. Since the High SMM space is remapped the addressed and DRAM SMM space is a different address range. Note that the High DRAM space is the same as the Compatible Transaction Address space. Table 3-5 describes three unique address ranges. Table 3-5. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB TSEG SMM Space Enabled Compatible High TSEG Transaction Address Space 000A_0000h to 000B_FFFFh FEDA_0000h to FEDB_FFFFh (TOLUD-STOLEN-TSEG) to TOLUD-STOLEN DRAM Space (DRAM) 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh (TOLUD-STOLEN-TSEG) to TOLUD-STOLEN NOTES: 1. STOLEN memory is only for the 82Q35/82Q33/82G33 GMCH. 3.8.2 SMM Space Restrictions If any of the following conditions are violated the results of SMM accesses are unpredictable and may cause the system to hang: 1. 2. The Compatible SMM space must not be set-up as cacheable. High or TSEG SMM transaction address space must not overlap address space assigned to system DRAM, or to any “PCI” devices (including DMI Interface, PCIExpress, and graphics devices). This is a BIOS responsibility. Both D_OPEN and D_CLOSE must not be set to 1 at the same time. When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available DRAM. This is a BIOS responsibility. Any address translated through the GMADR TLB must not target DRAM from A_0000–F_FFFFh. 3. 4. 5. 68 Datasheet System Address Map 3.8.3 SMM Space Combinations When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible SMM space is effectively disabled. Processor-originated accesses to the Compatible SMM space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP); otherwise, they are forwarded to the DMI Interface. PCI Express and DMI Interface originated accesses are never allowed to access SMM space. Table 3-6. SMM Space Global Enable G_SMRAME 0 1 1 1 1 High Enable H_SMRAM_EN X 0 0 1 1 TSEG Enable TSEG_EN X 0 1 0 1 Compatible (C) Range Disable Enable Enable Disabled Disabled High (H) Range Disable Disable Disable Enable Enable TSEG (T) Range Disable Disable Enable Disable Enable 3.8.4 SMM Control Combinations The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM mode accesses. The D_CLS bit causes SMM (both CSEG and TSEG) data accesses to be forwarded to the DMI Interface or PCI Express. The SMM software can use this bit to write to video memory while running SMM code out of DRAM. 3.8.5 SMM Space Decode and Transaction Handling Only the processor is allowed to access SMM space. PCI Express and DMI Interface originated transactions are not allowed to SMM space. 3.8.6 Processor WB Transaction to an Enabled SMM Address Space Processor Writeback transactions (REQa[1]# = 0) to enabled SMM Address Space must be written to the associated SMM DRAM even though D_OPEN=0 and the transaction is not performed in SMM mode. This ensures SMM space cache coherency when cacheable extended SMM space is used. Datasheet 69 System Address Map 3.8.7 SMM Access through GTT TLB (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Accesses through GTT TLB address translation to enabled SMM DRAM space are not allowed. Writes will be routed to memory address 000C_0000h with byte enables deasserted and reads will be routed to memory address 000C_0000h. If a GTT TLB translated address hits enabled SMM DRAM space, an error is recorded. PCI Express and DMI Interface originated accesses are never allowed to access SMM space directly or through the GTT TLB address translation. If a GTT TLB translated address hits enabled SMM DRAM space, an error is recorded. PCI Express and DMI Interface write accesses through GMADR range will be snooped. Assesses to GMADR linear range (defined via fence registers) are supported. PCI Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when translated, the resulting physical address is to enabled SMM DRAM space, the request will be remapped to address 000C_0000h with de-asserted byte enables. PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will have no address translation concerns. PCI Express and DMI Interface reads to GMADR will be remapped to address 000C_0000h. The read will complete with UR (unsupported request) completion status. GTT fetches are always decoded (at fetch time) to ensure not in SMM (actually, anything above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to address 000C_0000h, but that is not specific to PCI Express or DMI; it applies to processor or internal graphics engines. Also, since the GMADR snoop would not be directly to the SMM space, there would not be a writeback to SMM. In fact, the writeback would also be invalid (because it uses the same translation) and go to address 000C_0000h. 3.9 Memory Shadowing Any block of memory that can be designated as read-only or write-only can be “shadowed” into (G)MCH DRAM memory. Typically this is done to allow ROM code to execute more rapidly out of main DRAM. ROM is used as a read-only during the copy process while DRAM at the same time is designated write-only. After copying, the DRAM is designated read-only so that ROM is shadowed. Processor bus transactions are routed accordingly. 3.10 I/O Address Space The (G)MCH does not support the existence of any other I/O devices beside itself on the processor bus. The (G)MCH generates either DMI Interface or PCI Express bus cycles for all processor I/O accesses that it does not claim. Within the host bridge, the (G)MCH contains two internal registers in the processor I/O space: Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). These locations are used to implement configuration space access mechanism. 70 Datasheet System Address Map The processor allows 64 K+3 bytes to be addressed within the I/O space. The (G)MCH propagates the processor I/O address without any translation on to the destination bus and therefore provides addressability for 64K+3 byte locations. Note that the upper 3 locations can be accessed only during I/O address wrap-around when processor bus HAB_16 address signal is asserted. HAB_16 is asserted on the processor bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HAB_16 is also asserted when an I/O access is made to 2 bytes from address 0FFFFh. A set of I/O accesses (other than ones used for configuration space access) are consumed by the internal graphics device if it is enabled. The mechanisms for internal graphics I/O decode and the associated control is explained later. The I/O accesses (other than ones used for configuration space access) are forwarded normally to the DMI Interface bus unless they fall within the PCI Express I/O address range as defined by the mechanisms explained below. I/O writes are NOT posted. Memory writes to ICH9 or PCI Express are posted. The PCICMD1 register can disable the routing of I/O cycles to the PCI Express. The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with an UR status. Upstream I/O cycles and configuration cycles should never occur. If one does occur, the request will route as a read to memory address 000C_0000h so a completion is naturally generated (whether the original request was a read or write). The transaction will complete with an UR completion status. For Pentium® 4 processors, I/O reads that lie within 8-byte boundaries but cross 4byte boundaries are issued from the processor as 1 transaction. The (G)MCH breaks this into 2 separate transactions. I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed to be split into 2 transactions by the processor. 3.10.1 PCI Express* I/O Address Mapping The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus interface when processor initiated I/O cycle addresses are within the PCI Express I/O address range. This range is controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in (G)MCH Device 1 configuration space. Address decoding for this range is based on the following concept. The top 4 bits of the respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address. For the purpose of address decoding, the (G)MCH assumes that lower 12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces the I/O address range alignment to 4 KB boundary and produces a size granularity of 4 KB. The (G)MCH positively decodes I/O accesses to PCI Express I/O address space as defined by the following equation: I/O_Base_Address ≤ Processor I/O Cycle Address ≤ I/O_Limit_Address The effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of I/O space claimed by the PCI Express device. The (G)MCH also forwards accesses to the Legacy VGA I/O ranges according to the settings in the Device 1 configuration registers BCTRL (VGA Enable) and PCICMD1 Datasheet 71 System Address Map (IOAE1), unless a second adapter (monochrome) is present on the DMI Interface/PCI (or ISA). The presence of a second graphics adapter is determined by the MDAP configuration bit. When MDAP is set, the (G)MCH will decode legacy monochrome I/O ranges and forward them to the DMI Interface. The IO ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh. Note that the (G)MCH Device 1 I/O address range registers defined above are used for all I/O space allocation for any devices requiring such a window on PCI Express. The PCICMD1 register can disable the routing of I/O cycles to PCI Express. 3.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping VGAA = 000A_0000 – 000A_FFFF MDA = 000B_0000 – 000B_7FFF VGAB = 000B_8000 – 000B_FFFF MAINMEM = 0100_0000 to TOLUD HIGHMEM = 4 GB to TOM RECLAIMMEM = RECLAIMBASE to RECLAIMLIMIT 3.11.1 Legacy VGA and I/O Range Decode Rules The legacy 128 KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMI Interface depending on the programming of the VGA steering bits. Priority for VGA mapping is constant in that the (G)MCH always decodes internally mapped devices first. Internal to the GMCH, decode precedence is always given to IGD. The GMCH always positively decodes internally mapped devices, namely the IGD and PCI-Express. Subsequent decoding of regions mapped to PCI Express or the DMI Interface depends on the Legacy VGA configurations bits (VGA Enable and MDAP). § 72 Datasheet (G)MCH Register Description 4 (G)MCH Register Description The (G)MCH contains two sets of software accessible registers, accessed via the Host processor I/O address space: Control registers and internal configuration registers. • Control registers are I/O mapped into the processor I/O space, which control access to PCI and PCI Express configuration space (see section entitled I/O Mapped Registers). • Internal configuration registers residing within the (G)MCH are partitioned into three logical device register sets (“logical” since they reside within a single physical device). The first register set is dedicated to Host Bridge functionality (i.e. DRAM configuration, other chip-set operating parameters and optional features). The second register block is dedicated to Host-PCI Express Bridge functions (controls PCI Express interface configurations and operating parameters). For the 82Q35/82Q33/82G33 GMCH, there is a third register block for the internal graphics functions. The (G)MCH internal registers (I/O Mapped, Configuration and PCI Express Extended Configuration registers) are accessible by the Host processor. The registers that reside within the lower 256 bytes of each device can be accessed as Byte, Word (16 bit), or DWord (32 bit) quantities, with the exception of CONFIG_ADDRESS, which can only be accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field). Registers which reside in bytes 256 through 4095 of each device may only be accessed using memory mapped transactions in DWord (32 bit) quantities. Some of the (G)MCH registers described in this section contain reserved bits. These bits are labeled "Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, and write operation for the Configuration Address Register. In addition to reserved bits within a register, the (G)MCH contains address locations in the configuration space of the Host Bridge entity that are marked either "Reserved" or “Intel Reserved”. The (G)MCH responds to accesses to “Reserved” address locations by completing the host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8-, 16-, or 32 bits in size). Writes to “Reserved” registers have no effect on the (G)MCH. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads from “Intel Reserved” registers may return a non-zero value. Upon a Full Reset, the (G)MCH sets its entire set of internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bringing up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the (G)MCH registers accordingly. Datasheet 73 (G)MCH Register Description 4.1 Register Terminology The following table shows the register-related terminology that is used. Item RO RO/S Definition Read Only bit(s). Writes to these bits have no effect. This may be a status bit or a static value. Read Only / Sticky bit(s). Writes to these bits have no effect. These are status bits only. Bits are not returned to their default values by "warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a cold reset is “Power Good Reset” as defined in the PCI Express spec). Read Set / Write Clear bit(s). The first time the bit is read with an enabled byte, it returns the value 0, but a side-effect of the read is that the value changes to 1. Any subsequent reads with enabled bytes return a 1 until a 1 is written to the bit. When the bit is read, but the byte is not enabled, the state of the bit does not change, and the value returned is irrelevant, but will match the state of the bit. When a 0 is written to the bit, there is no effect. When a 1 is written to the bit, its value becomes 0, until the next byte-enabled read. When the bit is written, but the byte is not enabled, there is no effect. RW RWC Read / Write bit(s). These bits can be read and written by software. Hardware may only change the state of this bit by reset. Read / Write Clear bit(s). These bits can be read. Internal events may set this bit. A software write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect. Read / Write Clear / Lockable bit(s). These bits can be read. Internal events may set this bit. A software write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect. Additionally there is a Key bit (which is marked R/W/K or R/W/L/K) that, when set, prohibits this bit field from being writeable (bit field becomes Read Only). Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may set this bit. A software write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect. Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a cold reset is “Power Good Reset” as defined in the PCI Express spec). Read / Write / Blind bit(s). These bits can be read and written by software. Additionally there is a selector bit which, when set, changes what may be read from these bits. The value written is always stored in a hidden register. When the selector bit indicates that the written value should not be read, some other status is read from this bit. When the selector bit indicates that the written value should be read, the value in the hidden register is read from this bit. Read / Write / Blind / Lockable bit(s). These bits can be read and written by software. Additionally there is a selector bit which, when set, changes what may be read from these bits. The value written is always stored in a hidden register. When the selector bit indicates that the written value should not be read, some other status is read from this bit. When the selector bit indicates that the written value should be read, the value in the hidden register is read from this bit. Additionally there is a Key bit (which is marked R/W/K or R/W/L/K) that, when set, prohibits this bit field from being writeable (bit field becomes Read Only). RS/WC RWC/L RWC/S RW/B RW/B/L 74 Datasheet (G)MCH Register Description Item RW/K Definition Read / Write / Key bit(s). These bits can be read and written by software. Additionally this bit, when set, prohibits some other bit field(s) from being writeable (bit fields become Read Only). Read / Write / Lockable bit(s). These bits can be read and written by software. Additionally there is a Key bit (which is marked R/W/K or R/W/L/K) that, when set, prohibits this bit field from being writeable (bit field becomes Read Only). Read / Write / Lockable / Key bit(s). These bits can be read and written by software. Additionally this bit is a Key bit that, when set, prohibits this bit field and/or some other specified bit fields from being writeable (bit fields become Read Only). Read / Write / Sticky bit(s). These bits can be read and written by software. Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a cold reset is “Power Good Reset” as defined in the PCI Express spec). Read / Write / Sticky / Blind bit(s). These bits can be read and written by software. Additionally there is a selector bit which, when set, changes what may be read from these bits. The value written is always stored in a hidden register. When the selector bit indicates that the written value should not be read, some other status is read from this bit. When the selector bit indicates that the written value should be read, the value in the hidden register is read from this bit. Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a cold reset is “Power Good Reset” as defined in the PCI Express spec). Read / Write / Self Clear bit(s). These bits can be read and written by software. When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly sooner than any subsequent software read could retrieve a ‘1’. Read / Write / Self Clear / Lockable bit(s). These bits can be read and written by software. When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly sooner than any subsequent software read could retrieve a ‘1’. Additionally there is a bit (which is marked R/W/K or R/W/L/K) that, when set, prohibits this bit field from being writeable (bit field becomes Read Only). Write Once bit(s). Once written by software, bits with this attribute become Read Only. These bits can only be cleared by a Reset. If there are multiple R/WO fields within a DWORD, they should be written all at once (atomically) to avoid capturing an incorrect value. Write Only. These bits may be written by software, but will always return zeros when read. They are used for write side-effects. Any data written to these registers cannot be retrieved. RW/L RW/L/K RW/S RW/S/B RW/SC RW/SC/L RWO WO Datasheet 75 (G)MCH Register Description 4.2 4.2.1 Configuration Process and Registers Platform Configuration Structure The DMI physically connects the (G)MCH and the Intel ICH9; so, from a configuration standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the (G)MCH and the Intel ICH9 appear to be on PCI bus 0. Note: The ICH9 internal LAN controller does not appear on bus 0 – it appears on the external PCI bus (whose number is configurable). The system’s primary PCI expansion bus is physically attached to the Intel ICH9 and, from a configuration perspective, appears to be a hierarchical PCI bus behind a PCIto-PCI bridge and therefore has a programmable PCI Bus number. The PCI Express Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI bus 0. Note: A physical PCI bus 0 does not exist and that DMI and the internal devices in the (G)MCH and Intel ICH9 logically constitute PCI Bus 0 to configuration software. The (G)MCH contains four PCI devices within a single physical component. The configuration registers for the four devices are mapped as devices residing on PCI bus 0. • Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device residing on PCI bus #0. Device 0 contains the standard PCI header registers, PCI Express base address register, DRAM control (including thermal/throttling control), configuration for the DMI, and other (G)MCH specific registers. • Device 1: Host-PCI Express Bridge. Logically this appears as a “virtual” PCI-toPCI bridge residing on PCI bus #0 and is compliant with PCI Express Specification rev 1.0. Device 1 contains the standard PCI-to-PCI bridge registers and the standard PCI Express/PCI configuration registers (including the PCI Express memory address mapping). It also contains Isochronous and Virtual Channel controls in the PCI Express extended configuration space. • Device 2: Internal Graphics Control (82Q35, 82Q33 ,82G33 GMCH only). Logically, this appears as a PCI device residing on PCI bus #0. Physically, device 2 contains the configuration registers for 3D, 2D, and display functions. • Device 3: Manageability Engine Device. ME Control. 76 Datasheet (G)MCH Register Description 4.3 Configuration Mechanisms The processor is the originator of configuration cycles so the FSB is the only interface in the platform where these mechanisms are used. Internal to the (G)MCH transactions received through both configuration mechanisms are translated to the same format. 4.3.1 Standard PCI Configuration Mechanism The following is the mechanism for translating processor I/O bus cycles to configuration cycles. The PCI specification defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the (G)MCH. The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though 0CFFh). To reference a configuration register a DWord I/O write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device and a specific configuration register of the device function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the (G)MCH translating the CONFIG_ADDRESS into the appropriate configuration cycle. The (G)MCH is responsible for translating and routing the processor’s I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal (G)MCH configuration registers, DMI or PCI Express. 4.3.2 PCI Express* Enhanced Configuration Mechanism PCI Express extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express configuration space is divided into a PCI 2.3 compatible region, which consists of the first 256B of a logical device’s configuration space and a PCI Express extended region which consists of the remaining configuration space. The PCI compatible region can be accessed using either the Standard PCI Configuration Mechanism or using the PCI Express Enhanced Configuration Mechanism described in this section. The extended configuration registers may only be accessed using the PCI Express Enhanced Configuration Mechanism. To maintain compatibility with PCI configuration addressing mechanisms, system software must access the extended configuration space using 32-bit operations (32-bit aligned) only. These 32bit operations include byte enables allowing only appropriate bytes within the DWord to be accessed. Locked transactions to the PCI Express memory mapped configuration address space are not supported. All changes made using either access mechanism are equivalent. Datasheet 77 (G)MCH Register Description The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped address space to access device configuration registers. This address space is reported by the system firmware to the operating system. There is a register, PCIEXBAR, that defines the base address for the block of addresses below 4GB for the configuration space associated with busses, devices and functions that are potentially a part of the PCI Express root complex hierarchy. In the PCIEXBAR register there exists controls to limit the size of this reserved memory mapped space. 256MB is the amount of address space required to reserve space for every bus, device, and function that could possibly exist. Options for 128MB and 64MB exist in order to free up those addresses for other uses. In these cases the number of busses and all of their associated devices and functions are limited to 128 or 64 busses respectively. The PCI Express Configuration Transaction Header includes an additional 4 bits (ExtendedRegisterAddress[3:0]) between the Function Number and Register Address fields to provide indexing into the 4 KB of configuration space allocated to each potential device. For PCI Compatible Configuration Requests, the Extended Register Address field must be all zeros. Figure 4-1. Memory Map to PCI Express* Device Configuration Space FFFFFFFh Bus 255 FFFFFh Device 31 7FFFh Function 7 PCI Express* Extended Configuration Space FFFh 1FFFFFh Bus 1 FFFFFh Bus 0 0h FFFFh Device 1 7FFFh Device 0 1FFFh Function 1 FFFh Function 0 FFh PCI Compatible Config Space PCI Compatible Config Header 3Fh Located By PCI Express* Base Address MemMap_PCIExpress Just the same as with PCI devices, each device is selected based on decoded address information that is provided as a part of the address portion of Configuration Request packets. A PCI Express device will decode all address information fields (bus, device, function and extended address numbers) to provide access to the correct register. To access this space (steps 1, 2, 3 are done only once by BIOS), 1. use the PCI compatible configuration mechanism to enable the PCI Express enhanced configuration mechanism by writing 1 to bit 0 of the PCIEXBAR register. use the PCI compatible configuration mechanism to write an appropriate PCI Express base address into the PCIEXBAR register calculate the host address of the register you wish to set using (PCI Express base + (bus number * 1 MB) + (device number * 32KB) + (function number * 4 KB) + (1 B * offset within the function) = host address) use a memory write or memory read cycle to the calculated host address to write or read that register. 2. 3. 4. 78 Datasheet (G)MCH Register Description 4.4 Routing Configuration Accesses The (G)MCH supports two PCI related interfaces: DMI and PCI Express. The (G)MCH is responsible for routing PCI and PCI Express configuration cycles to the appropriate device that is an integrated part of the (G)MCH or to one of these two interfaces. Configuration cycles to the ICH9 internal devices and Primary PCI (including downstream devices) are routed to the ICH9 via DMI. Configuration cycles to both the PCI Express Graphics PCI compatibility configuration space and the PCI Express Graphics extended configuration space are routed to the PCI Express Graphics port device or associated link. Figure 4-2. GMCH Configuration Cycle Flow Chart Datasheet 79 (G)MCH Register Description 4.4.1 Internal Device Configuration Accesses The (G)MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration cycle is targeting a PCI Bus #0 device. If the targeted PCI Bus #0 device exists in the (G)MCH and is not disabled, the configuration cycle is claimed by the appropriate device. 4.4.2 Bridge Related Configuration Accesses Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs. • Bus Number [7:0] is Header Byte 8 [7:0] • Device Number [4:0] is Header Byte 9 [7:3] • Function Number [2:0] is Header Byte 9 [2:0] And special fields for this type of TLP: • Extended Register Number [3:0] is Header Byte 10 [3:0] • Register Number [5:0] is Header Byte 11 [7:2] See the PCI Express specification for more information on both the PCI 2.3 compatible and PCI Express Enhanced Configuration Mechanism and transaction rules. 4.4.2.1 PCI Express* Configuration Accesses When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express Enhanced Configuration access matches the Device #1 Secondary Bus Number a PCI Express Type 0 Configuration TLP is generated on the PCI Express link targeting the device directly on the opposite side of the link. This should be Device #0 on the bus number assigned to the PCI Express link (likely Bus #1). The device on other side of link must be Device #0. The (G)MCH will Master Abort any Type 0 Configuration access to a non-zero Device number. If there is to be more than one device on that side of the link there must be a bridge implemented in the downstream device. When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express Enhanced Configuration access is within the claimed range (between the upper bound of the bridge device’s Subordinate Bus Number register and the lower bound of the bridge device’s Secondary Bus Number register) but doesn't match the Device #1 Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the secondary side of the PCI Express link. PCI Express Configuration Writes: • Internally the host interface unit will translate writes to PCI Express extended configuration space to configuration writes on the backbone. • Writes to extended space are posted on the FSB, but non-posted on the PCI Express or DMI (i.e., translated to configuration writes) 80 Datasheet (G)MCH Register Description 4.4.2.2 DMI Configuration Accesses Accesses to disabled (G)MCH internal devices, bus numbers not claimed by the HostPCI Express bridge, or PCI Bus #0 devices not part of the (G)MCH will subtractively decode to the ICH9 and consequently be forwarded over the DMI via a PCI Express configuration TLP. If the Bus Number is zero, the (G)MCH will generate a Type 0 Configuration Cycle TLP on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the Host-PCI Express bridge, the (G)MCH will generate a Type 1 Configuration Cycle TLP on DMI. The ICH9 routes configurations accesses in a manner similar to the (G)MCH. The ICH9 decodes the configuration TLP and generates a corresponding configuration access. Accesses targeting a device on PCI Bus #0 may be claimed by an internal device. The ICH7 compares the non-zero Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its P2P bridges to determine if the configuration access is meant for Primary PCI, or some other downstream PCI bus or PCI Express link. Configuration accesses that are forwarded to the ICH9, but remain unclaimed by any device or bridge will result in a master abort. 4.5 I/O Mapped Registers The (G)MCH contains two registers that reside in the processor I/O address space − the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window. 4.5.1 CONFIG_ADDRESS—Configuration Address Register I/O Address: Default Value: Access: Size: 0CF8h Accessed as a DW 00000000h RW 32 bits CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or Word reference will "pass through" the Configuration Address Register and DMI onto the Primary PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended. Datasheet 81 (G)MCH Register Description Bit 31 Access & Default RW 0b Description Configuration Enable (CFGE). 0 = Disable 1 = Enable Reserved Bus Number. If the Bus Number is programmed to 00h the target of the Configuration Cycle is a PCI Bus 0 agent. If this is the case and the (G)MCH is not the target (i.e., the device number is ≥ 2), then a DMI Type 0 Configuration Cycle is generated. If the Bus Number is non-zero, and does not fall within the ranges enumerated by device 1’s Secondary Bus Number or Subordinate Bus Number Register, then a DMI Type 1 Configuration Cycle is generated. If the Bus Number is non-zero and matches the value programmed into the Secondary Bus Number Register of device 1, a Type 0 PCI configuration cycle will be generated on PCI Express-G. If the Bus Number is non-zero, greater than the value in the Secondary Bus Number register of device 1 and less than or equal to the value programmed into the Subordinate Bus Number Register of device 1 a Type 1 PCI configuration cycle will be generated on PCI Express-G. This field is mapped to byte 8 [7:0] of the request header format during PCI Express Configuration cycles and A[23:16] during the DMI Type 1 configuration cycles. 30:24 23:16 RW 00h 15:11 RW 00h Device Number. This field selects one agent on the PCI bus selected by the Bus Number. When the Bus Number field is “00” the (G)MCH decodes the Device Number field. The (G)MCH is always Device Number 0 for the Host bridge entity, Device Number 1 for the HostPCI Express entity. Therefore, when the Bus Number =0 and the Device Number equals 0, 1, or 2 the internal (G)MCH devices are selected. This field is mapped to byte 6 [7:3] of the request header format during PCI Express Configuration cycles and A [15:11] during the DMI configuration cycles. 10:8 RW 000b Function Number. This field allows the configuration registers of a particular function in a multi-function device to be accessed. The (G)MCH ignores configuration cycles to its internal devices if the function number is not equal to 0 or 1. This field is mapped to byte 6 [2:0] of the request header format during PCI Express Configuration cycles and A[10:8] during the DMI configuration cycles. 7:2 RW 00h Register Number. This field selects one register within a particular Bus, Device, and Function as specified by the other fields in the Configuration Address Register. This field is mapped to byte 7 [7:2] of the request header format during PCI Express Configuration cycles and A[7:2] during the DMI Configuration cycles. 1:0 Reserved 82 Datasheet (G)MCH Register Description 4.5.2 CONFIG_DATA—Configuration Data Register I/O Address: Default Value: Access: Size: 0CFCh 00000000h RW 32 bits CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Bit 31:0 Access & Default RW 0000 0000h Description Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, any I/O access to the CONFIG_DATA register will produce a configuration transaction using the contents of CONFIG_ADDRESS to determine the bus, device, function, and offset of the register to be accessed. § Datasheet 83 (G)MCH Register Description 84 Datasheet DRAM Controller Registers (D0:F0) 5 DRAM Controller Registers (D0:F0) DRAM Controller (D0:F0) The DRAM Controller registers are in Device 0 (D0), Function 0 (F0). Warning: Address locations that are not listed are considered Intel Reserved registers locations. Reads to Reserved registers may return non-zero values. Writes to reserved locations may cause system failures. All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in this component are simply not included in this document. The reserved/unimplemented space in the PCI configuration header space is not documented as such in this summary. 5.1 Table 5-1. DRAM Controller Register Address Map (D0:F0) Address Offset 00–01h 02–03h 04–05h 06–07h 08h 09–0Bh 0Dh 0Eh 2C–2Dh 2E–2Fh 34h 40–47h 48–4Fh 52–53h 54–57h Register Symbol VID DID PCICMD PCISTS RID CC MLT HDR SVID SID CAPPTR PXPEPBAR MCHBAR GGC DEVEN Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Master Latency Timer Header Type Subsystem Vendor Identification Subsystem Identification Capabilities Pointer PCI Express Port Base Address (G)MCH Memory Mapped Register Range Base GMCH Graphics Control Register Device Enable Default Value 8086h 29C0h 0006h 0090h 00h 060000h 00h 00h 0000h 0000h E0h 0000000000 000000h 0000000000 000000h 0030h 000003DBh Access RO RO RO, RW RWC, RO RO RO RO RO RWO RWO RO RW/L, RO RW/L, RO RO, RW/L RO, RW/L Datasheet 85 DRAM Controller Registers (D0:F0) Address Offset 60–67h 68–6Fh 90h 91h 92h 93h 94h 95h 96h 97h 98–99h 9A–9Bh 9Dh Register Symbol PCIEXBAR DMIBAR PAM0 PAM1 PAM2 PAM3 PAM4 PAM5 PAM6 LAC REMAPBASE REMAPLIMIT SMRAM Register Name PCI Express Register Range Base Address Root Complex Register Range Base Address Programmable Attribute Map 0 Programmable Attribute Map 1 Programmable Attribute Map 2 Programmable Attribute Map 3 Programmable Attribute Map 4 Programmable Attribute Map 5 Programmable Attribute Map 6 Legacy Access Control Remap Base Address Register Remap Limit Address Register System Management RAM Control Default Value 00000000E0 000000h 0000000000 000000h 00h 00h 00h 00h 00h 00h 00h 00h 03FFh 0000h 02h Access RO, RW/L, RW/L/K RO, RW/L RO, RW/L RO, RW/L RO, RW/L RO, RW/L RO, RW/L RO, RW/L RO, RW/L RW/L, RO, RW RO, RW/L RO, RW/L RO, RW/L, RW, RW/L/K RW/L, RWC, RO RO, RW/L RW/L RW/L ,RO RW/L ,RO RW/L, RO RW/L RO RO, RWC/S RO, RW RO, RW RW RO 9Eh A0–A1h A2–A3h A4–A7h A8–ABh AC–AFh B0–B1h C8–C9h CA–CBh CC–CDh DC–DFh E0–EAh ESMRAMC TOM TOUUD GBSM BGSM TSEGMB TOLUD ERRSTS ERRCMD SMICMD SKPD CAPID0 Extended System Management RAM Control Top of Memory Top of Upper Usable Dram Graphics Base of Stolen Memory Base of GTT stolen Memory TSEG Memory Base Top of Low Usable DRAM Error Status Error Command SMI Command Scratchpad Data Capability Identifier 38h 0001h 0000h 00000000h 00000000h 00000000h 0010h 0000h 0000h 0000h 00000000h 0000010000 0000010B0 009h 86 Datasheet DRAM Controller Registers (D0:F0) 5.1.1 VID—Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 0–1h 8086h RO 16 bits This register combined with the Device Identification register uniquely identifies any PCI device. Bit 15:0 Access & Default RO 8086h Description Vendor Identification Number (VID): PCI standard identification for Intel. 5.1.2 DID—Device Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 02–03h See table below RO 16 bits This register combined with the Vendor Identification register uniquely identifies any PCI device. Bit 15:0 Access & Default RO 29B0h 29C0h 29D0h Description Device Identification Number (DID): 29B0h = Intel® 82Q35 GMCH 29C0h = Intel® 82G33/82P35 (G)MCH 29D0h = Intel® 82Q33 GMCH Datasheet 87 DRAM Controller Registers (D0:F0) 5.1.3 PCICMD—PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 4–5h 0006h RO, RW 16 bits Since (G)MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented. Bit 15:10 9 Access & Default RO 00h RO 0b RW 0b Reserved Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back write. Since device 0 is strictly a target, this bit is not implemented and is hardwired to 0. SERR Enable (SERRE): This bit is a global enable bit for Device 0 SERR messaging. The (G)MCH does not have an SERR signal. The (G)MCH communicates the SERR condition by sending an SERR message over DMI to the ICH. 1= The (G)MCH is enabled to generate SERR messages over DMI for specific Device 0 error conditions that are individually enabled in the ERRCMD and DMIUEMSK registers. The error status is reported in the ERRSTS, PCISTS, and DMIUEST registers. 0 = The SERR message is not generated by the (G)MCH for Device 0. Note that this bit only controls SERR messaging for the Device 0. Device 1 has its own SERRE bits to control error reporting for error conditions occurring in that device. The control bits are used in a logical OR manner to enable the SERR DMI message mechanism. 7 6 RO 0b RW 0b Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the (G)MCH, and this bit is hardwired to 0. Parity Error Enable (PERRE): This bit controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set. 0= Master Data Parity Error bit in PCI Status register can NOT be set. 1 = Master Data Parity Error bit in PCI Status register CAN be set. 5 4 RO 0b RO 0b RO 0b RO 1b RO 1b RO 0b VGA Palette Snoop Enable (VGASNOOP): The (G)MCH does not implement this bit and it is hardwired to a 0. Memory Write and Invalidate Enable (MWIE): The (G)MCH will never issue memory write and invalidate commands. This bit is therefore hardwired to 0. Special Cycle Enable (SCE): The (G)MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Bus Master Enable (BME): The (G)MCH is always enabled as a master on the backbone. This bit is hardwired to a 1. Memory Access Enable (MAE): The (G)MCH always allows access to main memory. This bit is not implemented and is hardwired to 1. I/O Access Enable (IOAE): This bit is not implemented in the (G)MCH and is hardwired to a 0. Description 8 3 2 1 0 88 Datasheet DRAM Controller Registers (D0:F0) 5.1.4 PCISTS—PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 6–7h 0090h RWC, RO 16 bits This status register reports the occurrence of error events on Device 0's PCI interface. Since the (G)MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented. Bit 15 Access & Default RWC 0b RWC 0b Description Detected Parity Error (DPE): 1= Device received a Poisoned TLP. Signaled System Error (SSE): Software clears this bit by writing a 1 to it. 1= The (G)MCH Device 0 generated a SERR message over DMI for any enabled Device 0 error condition. Device 0 error conditions are enabled in the PCICMD, ERRCMD, and DMIUEMSK registers. Device 0 error flags are read/reset from the PCISTS, ERRSTS, or DMIUEST registers. 14 13 RWC 0b Received Master Abort Status (RMAS): Software clears this bit by writing a 1 to it. 1 = (G)MCH generated a DMI request that receives an Unsupported Request completion packet. 12 RWC 0b Received Target Abort Status (RTAS): Software clears this bit by writing a 1 to it. 1 = (G)MCH generated a DMI request that receives a Completer Abort completion packet. 11 RO 0b RO 00b Signaled Target Abort Status (STAS): The (G)MCH will not generate a Target Abort DMI completion packet or Special Cycle. This bit is not implemented in the (G)MCH and is hardwired to a 0. DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions have no affect. Device 0 does not physically connect to PCI_A. These bits are set to "00" (fast decode) so that optimum DEVSEL timing for PCI_A is not limited by the (G)MCH. Master Data Parity Error Detected (DPD): 1 = This bit is set when DMI received a Poisoned completion from the ICH. NOTE: This bit can only be set when the Parity Error Enable bit in the PCI Command register is set. 10:9 8 RWC 0b 7 RO 1b Fast Back-to-Back (FB2B): This bit is hardwired to 1. Device 0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for PCI_A is not limited by the (G)MCH. Datasheet 89 DRAM Controller Registers (D0:F0) Bit 6 5 4 Access & Default RO 0b RO 0b RO 1b Reserved Description 66 MHz Capable: Does not apply to PCI Express. Hardwired to 0. Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the Capability Identification register resides. Reserved 3:0 RO 0h 5.1.5 RID—Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 8h 00h RO 8 bits This register contains the revision number of the (G)MCH Device #0. These bits are read only and writes to this register have no effect. Bit 7:0 Access & Default RO 00h Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the (G)MCH Device 0. Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 90 Datasheet DRAM Controller Registers (D0:F0) 5.1.6 CC—Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 09–0Bh 060000h RO 24 bits This register identifies the basic function of the device, a more specific sub-class, and a register-specific programming interface. Bit 23:16 Access & Default RO 06h Description Base Class Code (BCC): This is an 8-bit value that indicates the base class code for the (G)MCH. 06h = Bridge device. 15:8 RO 00h Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of Bridge into which the (G)MCH falls. 00h = Host Bridge. 7:0 RO 00h Programming Interface (PI): This is an 8-bit value that indicates the programming interface of this device. This value does not specify a particular register set layout and provides no practical use for this device. 5.1.7 MLT—Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 0Dh 00h RO 8 bits Device 0 in the (G)MCH is not a PCI master. Therefore this register is not implemented. Bit 7:0 Access & Default RO 00h Reserved Description Datasheet 91 DRAM Controller Registers (D0:F0) 5.1.8 HDR—Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI Eh 00h RO 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 Access & Default RO 00h Description PCI Header (HDR): This field always returns 0 to indicate that the (G)MCH is a single function device with standard header layout. Reads and writes to this location have no effect. 5.1.9 SVID—Subsystem Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 2C–2Dh 0000h RWO 16 bits This value is used to identify the vendor of the subsystem. Bit 15:0 Access & Default RWO 0000h Description Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes read only. 5.1.10 SID—Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 2E–2Fh 0000h RWO 16 bits This value is used to identify a particular subsystem. Bit 15:0 Access & Default RWO 0000h Description Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has been written once, it becomes read only. 92 Datasheet DRAM Controller Registers (D0:F0) 5.1.11 CAPPTR—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 34h E0h RO 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit 7:0 Access & Default RO E0h Description Capabilities Pointer (CAPPTR): Pointer to the offset of the first capability ID register block. In this case the first capability is the product-specific Capability Identifier (CAPID0). 5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 40–47h 0000000000000000h RW/L, RO 64 bits This is the base address for the PCI Express Egress Port MMIO Configuration space. There is no physical memory within this 4KB window that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Egress port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0] All the bits in this register are locked in Intel® TXT mode. Bit 63:36 35:12 Access & Default RO 0000000h RW/L 000000h Reserved PCI Express Egress Port MMIO Base Address (PXPEPBAR): This field corresponds to bits 35:12 of the base address PCI Express Egress Port MMIO configuration space. BIOS will program this register resulting in a base address for a 4 KB block of contiguous memory address space. This register ensures that a naturally aligned 4 KB space is allocated within the first 64 GB of addressable memory space. System Software uses this base address to program the (G)MCH MMIO register set. All the bits in this register are locked in Intel® TXT mode. Reserved PXPEPBAR Enable (PXPEPBAREN): 0 = PXPEPBAR is disabled and does not claim any memory 1 = PXPEPBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel® TXT. Description 11:1 0 RO 000h RW/L 0b Datasheet 93 DRAM Controller Registers (D0:F0) 5.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 48–4Fh 0000000000000000h RW/L, RO 64 bits This is the base address for the (G)MCH Memory Mapped Configuration space. There is no physical memory within this 16 KB window that can be addressed. The 16 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the (G)MCH MMIO Memory Mapped Configuration space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0] All the bits in this register are locked in Intel® Execution Technology mode. The register space contains memory control, initialization, timing, and buffer strength registers; clocking registers; and power and thermal management registers. The 16 KB space reserved by the MCHBAR register is not accessible during Intel® Execution Technology mode of operation or if the ME security lock is asserted (MESMLCK.ME_SM_lock at PCI device 0, function 0, offset F4h) except for the following offset ranges. 02B8h to 02BFh: Channel 0 Throttle Counter Status Registers 06B8h to 06BFh: Channel 1 Throttle Counter Status Registers 0CD0h to 0CFFh: Thermal Sensor Control Registers 3000h to 3FFFh: Unlocked registers for future expansion Bit 63:36 35:14 Access & Default RO 0000000h RW/L 000000h Reserved Description GMCH Memory Mapped Base Address (MCHBAR): This field corresponds to bits 35:14 of the base address (G)MCH Memory Mapped configuration space. BIOS will program this register resulting in a base address for a 16 KB block of contiguous memory address space. This register ensures that a naturally aligned 16 KB space is allocated. System Software uses this base address to program the (G)MCH Memory Mapped register set. All the bits in this register are locked in Intel® TXT mode. Reserved MCHBAR Enable (MCHBAREN): 0= MCHBAR is disabled and does not claim any memory 1 = MCHBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel® TXT. 13:1 0 RO 0000h RW/L 0b 94 Datasheet DRAM Controller Registers (D0:F0) 5.1.14 GGC—GMCH Graphics Control Register (Intel® 82Q35, 82Q33, 82G33 GMCH Only) B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 52–53h 0030h RO, RW/L 16 bits All the bits in this register are Intel® TXT lockable. Bit 15:10 9:8 Access & Default RO 00h RW/L 0h Reserved GTT Graphics Memory Size (GGMS): This field is used to select the amount of main memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is preallocated only when Internal graphics is enabled. 00 = No memory pre-allocated. GTT cycles (Memory and I/O) are not claimed. 01 = No VT mode, 1 MB of memory pre-allocated for GTT. 10 = VT mode, 2 MB of memory pre-allocated for GTT. 11 = Reserved Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. Description Datasheet 95 DRAM Controller Registers (D0:F0) Bit 7:4 Access & Default RW/L 0011b Description Graphics Mode Select (GMS): This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled. 0000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and the Sub-Class Code field within Device 2 function 0 Class Code register is 80h. 0001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame buffer. 0010 = DVMT (UMA) mode, 4 MB of memory pre-allocated for frame buffer. 0011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame buffer. 0100 = DVMT (UMA) mode, 16 MB of memory pre-allocated for frame buffer. 0101 = DVMT (UMA) mode, 32 MB of memory pre-allocated for frame buffer. 0110 = DVMT (UMA) mode, 48 MB of memory pre-allocated for frame buffer. 0111 = DVMT (UMA) mode, 64 MB of memory pre-allocated for frame buffer. 1000 = DVMT (UMA) mode, 128 MB of memory pre-allocated for frame buffer. 1001 = DVMT (UMA) mode, 256 MB of memory pre-allocated for frame buffer. Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. BIOS Requirement: BIOS must not set this field to 000 if IVD (bit 1 of this register) is 0. 3:2 1 RO 00b RW/L 0b Reserved IGD VGA Disable (IVD): 0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the Sub-Class Code within Device 2 Class Code register is 00h. 1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and the Sub-Class Code field within Device 2 function 0 Class Code register is 80h. BIOS Requirement: BIOS must not set this bit to 0 if the GMS field (bits 6:4 of this register) pre-allocates no memory. This bit MUST be set to 1 if Device 2 is disabled either via a fuse or fuse override (CAPID0[46] = 1) or via a register (DEVEN[3] = 0). This register is locked by Intel® TXT or ME stolen Memory lock. 0 RO 0b Reserved 96 Datasheet DRAM Controller Registers (D0:F0) 5.1.15 DEVEN—Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 54–57h 000003DBh RO, RW/L 32 bits This register allows for enabling/disabling of PCI devices and functions that are within the (G)MCH. All the bits in this register are Intel® TXT Lockable. Bit 31:10 9 Access & Default RO 00000h RW/L 1b Reserved EP Function 3 (D3F3EN): 0 = Bus 0 Device 3 Function 3 is disabled and hidden 1 = Bus 0 Device 3 Function 3 is enabled and visible If Device 3, Function 0 is disabled and hidden, then Device 3, Function 3 is also disabled and hidden independent of the state of this bit. If this (G)MCH does not have ME capability (CAPID0[57] = 1 or CAPID0[56] = 1), then Device 3, Function 3 is disabled and hidden independent of the state of this bit. 8 RW/L 1b EP Function 2 (D3F2EN): 0 = Bus 0 Device 3 Function 2 is disabled and hidden 1 = Bus 0 Device 3 Function 2 is enabled and visible If Device 3, Function 0 is disabled and hidden, then Device 3, Function 2 is also disabled and hidden independent of the state of this bit. If this (G)MCH does not have ME capability (CAPID0[57] = 1 or CAPID0[56] = 1), then Device 3, Function 2 is disabled and hidden independent of the state of this bit. 7 RW/L 1b EP Function 1 (D3F1EN): 0 = Bus 0, Device 3, Function 1 is disabled and hidden 1 = Bus 0, Device 3, Function 1 is enabled and visible. If Device 3, Function 0 is disabled and hidden, then Device 3, Function 1 is also disabled and hidden independent of the state of this bit. If this (G)MCH does not have ME capability (CAPID0[57] = 1), then Device 3, Function 1 is disabled and hidden independent of the state of this bit. 6 RW/L 1b EP Function 0 (D3F0EN): 0 = Bus 0, Device 3, Function 0 is disabled and hidden 1 = Bus 0, Device 3, Function 0 is enabled and visible. If this (G)MCH does not have ME capability (CAPID0[57] = 1), then Device 3, Function 0 is disabled and hidden independent of the state of this bit. Description Datasheet 97 DRAM Controller Registers (D0:F0) Bit 5 4 Access & Default RO 0b RW/L 1b Reserved Description 82Q35, 82Q33, 82G33 GMCH Internal Graphics Engine Function 1 (D2F1EN): 0 = Bus 0, Device 2, Function 1 is disabled and hidden 1 = Bus 0, Device 2, Function 1 is enabled and visible If Device 2, Function 0 is disabled and hidden, then Device 2, Function 1 is also disabled and hidden independent of the state of this bit. If this component is not capable of Dual Independent Display (CAPID0[78] = 1), then this bit is hardwired to 0b to hide Device 2, Function 1. 82P35 MCH Reserved 3 RW/L 1b 82Q35, 82Q33, 82G33 GMCH Internal Graphics Engine Function 0 (D2F0EN): 0 = Bus 0, Device 2, Function 0 is disabled and hidden 1 = Bus 0, Device 2, Function 0 is enabled and visible If this GMCH does not have internal graphics capability (CAPID0[46] = 1), then Device 2, Function 0 is disabled and hidden independent of the state of this bit. 82P35 MCH Reserved 2 1 RO 0b RW/L 1b Reserved PCI Express Port (D1EN): 0 = Bus 0, Device 1, Function 0 is disabled and hidden. 1 = Bus 0, Device 1, Function 0 is enabled and visible. Default value is determined by the device capabilities (see CAPID0 [44]), SDVO Presence hardware strap and the SDVO/PCI Express Concurrent hardware strap. Device 1 is Disabled on Reset if the SDVO Presence strap was sampled high, and the SDVO/PCI Express Concurrent strap was sampled low at the last assertion of PWROK, and is enabled by default otherwise. 0 RO 1b Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be disabled and is therefore hardwired to 1. 98 Datasheet DRAM Controller Registers (D0:F0) 5.1.16 PCIEXBAR—PCI Express* Register Range Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 60–67h 00000000E0000000h RO, RW/L, RW/L/K 64 bits This is the base address for the PCI Express configuration space. This window of addresses contains the 4 KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the (G)MCH. There is not actual physical memory within this window of up to 256 MB that can be addressed. The actual length is determined by a field in this register. Each PCI Express Hierarchy requires a PCI Express BASE register. The (G)MCH supports one PCI Express hierarchy. The region reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. For example, MCHBAR reserves a 16 KB space and PXPEPBAR reserves a 4 KB space both outside of PCIEXBAR space. They cannot be overlayed on the space reserved by PCIEXBAR for devices 0. On reset, this register is disabled and must be enabled by writing a 1 to the enable field in this register. This base address shall be assigned on a boundary consistent with the number of buses (defined by the Length field in this register), above TOLUD and still within 64 bit addressable memory space. All other bits not decoded are read only 0. The PCI Express Base Address cannot be less than the maximum address written to the Top of physical memory register (TOLUD). Software must ensure that these ranges do not overlap with known ranges located above TOLUD. Software must ensure that the sum of Length of enhanced configuration region + TOLUD + (other known ranges reserved above TOLUD) is not greater than the 36-bit addressable limit of 64 GB. In general system implementation and number of PCI/PCI Express/PCI-X buses supported in the hierarchy will dictate the length of the region. All the Bits in this register are locked in Intel® TXT mode. Bit 63:36 Access & Default RO 0000000h Reserved Description Datasheet 99 DRAM Controller Registers (D0:F0) Bit 35:28 Access & Default RW/L 0Eh Description PCI Express Base Address (PCIEXBAR): This field corresponds to bits 35:28 of the base address for PCI Express enhanced configuration space. BIOS will program this register resulting in a base address for a contiguous memory address space; size is defined by bits 2:1 of this register. This Base address shall be assigned on a boundary consistent with the number of buses (defined by the Length field in this register) above TOLUD and still within 64-bit addressable memory space. The address bits decoded depend on the length of the region defined by this register. This register is locked by Intel® TXT. The address used to access the PCI Express configuration space for a specific device can be determined as follows: PCI Express Base Address + Bus Number * 1 MB + Device Number * 32 KB + Function Number * 4 KB The address used to access the PCI Express configuration space for Device 1 in this component would be PCI Express Base Address + 0 * 1 MB + 1 * 32 KB + 0 * 4 KB = PCI Express Base Address + 32 KB. Remember that this address is the beginning of the 4KB space that contains both the PCI compatible configuration space and the PCI Express extended configuration space. All the Bits in this register are locked in Intel® TXT mode. 27 RW/L 0b RW/L 0b RO 000000h RW/L/K 00b 128 MB Base Address Mask (128ADMSK): This bit is either part of the PCI Express Base Address (R/W) or part of the Address Mask (RO, read 0b), depending on the value of bits 2:1 in this register. 64 MB Base Address Mask (64ADMSK): This bit is either part of the PCI Express Base Address (R/W) or part of the Address Mask (RO, read 0b), depending on the value of bits 2:1 in this register. Reserved Length (LENGTH): This Field describes the length of this region. Enhanced Configuration Space Region/Buses Decoded 00 = 256 MB (buses 0–255). Bits 31:28 are decoded in the PCI Express Base Address Field 01 = 128 MB (Buses 0–127). Bits 31:27 are decoded in the PCI Express Base Address Field. 10 = 64 MB (Buses 0–63). Bits 31:26 are decoded in the PCI Express Base Address Field. 11 = Reserved This register is locked by Intel® TXT. 26 25:3 2:1 100 Datasheet DRAM Controller Registers (D0:F0) Bit 0 Access & Default RW/L 0b Description PCIEXBAR Enable (PCIEXBAREN): 0 = The PCIEXBAR register is disabled. Memory read and write transactions proceed as if there were no PCIEXBAR register. PCIEXBAR bits 35:26 are R/W with no functionality behind them. 1 = The PCIEXBAR register is enabled. Memory read and write transactions whose address bits 35:26 match PCIEXBAR will be translated to configuration reads and writes within the (G)MCH. These Translated cycles are routed as shown in the table above. This register is locked by Intel® TXT. 5.1.17 DMIBAR—Root Complex Register Range Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 68–6Fh 0000000000000000h RO, RW/L 64 bits This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the (G)MCH. There is no physical memory within this 4 KB window that can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Root Complex configuration space is disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0] All the Bits in this register are locked in Intel® TXT mode. Bit 63:36 35:12 Access RO 0000000h RW/L 000000h Reserved DMI Base Address (DMIBAR): This field corresponds to bits 35:12 of the base address DMI configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4 KB space is allocated within the first 64 GB of addressable memory space. System Software uses this base address to program the DMI register set. Reserved DMIBAR Enable (DMIBAREN): Description 11:1 0 RO 000h RW/L 0b 0 = DMIBAR is disabled and does not claim any memory 1 = DMIBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel® TXT. Datasheet 101 DRAM Controller Registers (D0:F0) 5.1.18 PAM0—Programmable Attribute Map 0 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 90h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h–0FFFFFh. The (G)MCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the P6 processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to both host accesses and PCI initiator accesses to the PAM areas. These attributes are: RE – Read Enable. When RE = 1, the processor read accesses to the corresponding memory segment are claimed by the (G)MCH and directed to main memory. Conversely, when RE = 0, the host read accesses are directed to PCI_A. When WE = 1, the host write accesses to the corresponding memory segment are claimed by the (G)MCH and directed to main memory. Conversely, when WE = 0, the host write accesses are directed to PCI_A. WE – Write Enable. The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in size. Note that the (G)MCH may hang if a PCI Express Graphics Attach or DMI originated access to Read Disabled or Write Disabled PAM segments occur (due to a possible IWB to non-DRAM). For these reasons the following critical restriction is placed on the programming of the PAM regions: At the time that a DMI or PCI Express Graphics Attach accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writeable. 102 Datasheet DRAM Controller Registers (D0:F0) Bit 7:6 5:4 Access & Default RO 00b RW/L 00b Reserved Description 0F0000h–0FFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0F0000h to 0FFFFFh. 00 = DRAM Disabled: All accesses are directed to DMI. 01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. 3:0 RO 0h Reserved Datasheet 103 DRAM Controller Registers (D0:F0) 5.1.19 PAM1—Programmable Attribute Map 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 91h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h–0C7FFFh. Bit 7:6 5:4 Access & Default RO 00b RW/L 00b Reserved 0C4000h–0C7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C4000 to 0C7FFF. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. 3:2 1:0 RO 00b RW/L 00b Reserved 0C0000h–0C3FFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C0000h to 0C3FFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. Description 104 Datasheet DRAM Controller Registers (D0:F0) 5.1.20 PAM2—Programmable Attribute Map 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 92h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h–0CFFFFh. Bit 7:6 5:4 Access & Default RO 00b RW/L 00b Reserved 0CC000h–0CFFFFh Attribute (HIENABLE): 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. 3:2 1:0 RO 00b RW/L 00b Reserved 0C8000h–0CBFFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C8000h to 0CBFFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. Description Datasheet 105 DRAM Controller Registers (D0:F0) 5.1.21 PAM3—Programmable Attribute Map 3 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 93h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h–0D7FFFh. Bit 7:6 5:4 Access & Default RO 00b RW/L 00b Reserved 0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. 3:2 1:0 RO 00b RW/L 00b Reserved 0D0000–0D3FFF Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. Description 106 Datasheet DRAM Controller Registers (D0:F0) 5.1.22 PAM4—Programmable Attribute Map 4 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 94h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h–0DFFFFh. Bit 7:6 5:4 Access & Default RO 00b RW/L 00b Reserved 0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0DC000h to 0DFFFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. 3:2 1:0 RO 00b RW/L 00b Reserved 0D8000h–0DBFFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0D8000h to 0DBFFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. Description Datasheet 107 DRAM Controller Registers (D0:F0) 5.1.23 PAM5—Programmable Attribute Map 5 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 95h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h–0E7FFFh. Bit 7:6 5:4 Access & Default RO 00b RW/L 00b Reserved 0E4000h–0E7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. 3:2 1:0 RO 00b RW/L 00b Reserved 0E0000h–0E3FFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. Description 108 Datasheet DRAM Controller Registers (D0:F0) 5.1.24 PAM6—Programmable Attribute Map 6 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 96h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h–0EFFFFh. Bit 7:6 5:4 Access & Default RO 00b RW/L 00b Reserved 0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. 3:2 1:0 RO 00b RW/L 00b Reserved 0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh. 00 = DRAM Disabled: Accesses are directed to DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. This register is locked by Intel® TXT. Description Datasheet 109 DRAM Controller Registers (D0:F0) 5.1.25 LAC—Legacy Access Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 97h 00h RW/L, RO, RW 8 bits This 8-bit register controls a fixed DRAM hole from 15–16 MB. Bit 7 Access & Default RW/L 0b Description Hole Enable (HEN): This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No memory hole. 1 = Memory hole from 15 MB to 16 MB. This bit is Intel® TXT lockable. 6:1 0 RO 00000b RW 0b Reserved MDA Present (MDAP): This bit works with the VGA Enable bits in the BCTRL register of Device 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if device 1's VGA Enable bit is not set. If device 1's VGA enable bit is not set, then accesses to IO address range x3BCh–x3BFh are forwarded to DMI. If the VGA enable bit is set and MDA is not present, then accesses to IO address range x3BCh–x3BFh are forwarded to PCI Express if the address is within the corresponding IOBASE and IOLIMIT, otherwise they are forwarded to DMI. MDA resources are defined as the following: Memory: I/O: 0B0000h – 0B7FFFh 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode) Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to the DMI even if the reference includes I/O locations not listed above. The following table shows the behavior for all combinations of MDA and VGA: VGAEN 0 0 1 1 MDAP 0 1 0 1 Description All References to MDA and VGA space are routed to DMI Invalid combination All VGA and MDA references are routed to PCI Express Graphics Attach. All VGA references are routed to PCI Express Graphics Attach. MDA references are routed to DMI. VGA and MDA memory cycles can only be routed across the PEG when MAE (PCICMD1[1]) is set. VGA and MDA I/O cycles can only be routed across the PEG if IOAE (PCICMD1[0]) is set. 110 Datasheet DRAM Controller Registers (D0:F0) 5.1.26 REMAPBASE—Remap Base Address Register B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 98–99h 03FFh RO, RW/L 16 bits Bit 15:10 9:0 Access & Default RO 000000b RW/L 3FFh Reserved Description Remap Base Address [35:26] (REMAPBASE): The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[25:0] of the Remap Base Address are assumed to be 0s. Thus, the bottom of the defined memory range will be aligned to a 64 MB boundary. When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled. These bits are Intel® TXT lockable or ME stolen Memory lockable. 5.1.27 REMAPLIMIT—Remap Limit Address Register B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 9A–9Bh 0000h RO, RW/L 16 bits Bit 15:10 9:0 Access & Default RO 000000b RW/L 000h Reserved Description Remap Limit Address [35:26] (REMAPLMT): The value in this register defines the upper boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[25:0] of the remap limit address are assumed to be Fhs. Thus the top of the defined range will be one less than a 64 MB boundary. When the value in this register is less than the value programmed into the Remap Base register, the Remap window is disabled. These Bits are Intel® TXT lockable or ME stolen Memory lockable. Datasheet 111 DRAM Controller Registers (D0:F0) 5.1.28 SMRAM—System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 9Dh 02h RO, RW/L, RW, RW/L/K 8 bits The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set. Bit 7 6 Access & Default RO 0b RW/L 0b Reserved SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space DRAM. This will allow SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible SMRAM functions are enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADSB with SMM decode). To enable Extended SMRAM function this bit has be set to 1. Refer to the section on SMM for more details. Once D_LCK is set, this bit becomes read only. Compatible SMM Space Base Segment (C_BASE_SEG): This field indicates the location of SMM space. SMM DRAM is not remapped. It is simply made visible if the conditions are right to access SMM space, otherwise the access is forwarded to DMI. Since the (G)MCH supports only the SMM space between A0000 and BFFFF, this field is hardwired to 010. Description 5 RW 0b 4 RW/L/K 0b 3 RW/L 0b 2:0 RO 0b 112 Datasheet DRAM Controller Registers (D0:F0) 5.1.29 ESMRAMC—Extended System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 9Eh 38h RW/L, RWC, RO 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB. Bit 7 Access & Default RW/L 0b Description Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space location (i.e., above 1 MB or below 1 MB) When G_SMRAME is 1 and H_SMRAME is set to 1, the high SMRAM memory space is enabled. SMRAM accesses within the range 0FEDA0000h to 0FEDBFFFFh are remapped to DRAM addresses within the range 000A0000h to 000BFFFFh. Once D_LCK has been set, this bit becomes read only. Invalid SMRAM Access (E_SMERR): This bit is set when processor has accessed the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. It is software's responsibility to clear this bit. The software must write a 1 to this bit to clear it. SMRAM Cacheable (SM_CACHE): This bit is forced to 1 by the (G)MCH. L1 Cache Enable for SMRAM (SM_L1): This bit is forced to 1 by the (G)MCH. L2 Cache Enable for SMRAM (SM_L2): This bit is forced to 1 by the (G)MCH. TSEG Size (TSEG_SZ): Selects the size of the TSEG memory block if enabled. Memory from the top of DRAM space is partitioned away so that it may only be accessed by the processor interface and only then when the SMM bit is set in the request packet. Non-SMM accesses to this memory region are sent to DMI when the TSEG memory block is enabled. 00 = 1 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics Stolen Memory Size – 1 MB) to (TOLUD – GTT Graphics Memory Size – Graphics Stolen Memory Size). 01 = 2 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics Stolen Memory Size – 2 MB) to (TOLUD – GTT Graphics Memory Size – Graphics Stolen Memory Size). 10 = 8 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics Stolen Memory Size – 8 MB) to (TOLUD – GTT Graphics Memory Size – Graphics Stolen Memory Size). 11 = Reserved. Once D_LCK has been set, these bits becomes read only. 6 RWC 0b 5 4 3 2:1 RO 1b RO 1b RO 1b RW/L 00b Datasheet 113 DRAM Controller Registers (D0:F0) Bit 0 Access & Default RW/L 0b Description TSEG Enable (T_EN): Enabling of SMRAM memory for Extended SMRAM space only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only. 5.1.30 TOM—Top of Memory B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI A0–A1h 0001h RO, RW/L 16 bits This Register contains the size of physical memory. BIOS determines the memory size reported to the OS using this Register. Bit 15:10 9:0 Access & Default RO 00h RW/L 001h Reserved Top of Memory (TOM): This register reflects the total amount of populated physical memory. This is NOT necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory mapped I/O). These bits correspond to address bits 35:26 (64 MB granularity). Bits 25:0 are assumed to be 0. All the bits in this register are locked in Intel® TXT mode. Description 114 Datasheet DRAM Controller Registers (D0:F0) 5.1.31 TOUUD—Top of Upper Usable Dram B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI A2–A3h 0000h RW/L 16 bits This 16 bit register defines the Top of Upper Usable DRAM. Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to (reclaim limit + 1 byte) 64 MB aligned since reclaim limit is 64 MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than or equal to 4 GB. These bits are Intel® TXT lockable. Bit 15:0 Access & Default RW/L 0000h Description TOUUD (TOUUD): This register contains bits 35 to 20 of an address one byte above the maximum DRAM memory above 4 G that is usable by the operating system. Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to (reclaim limit + 1 byte) 64 MB aligned since reclaim limit is 64 MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4 GB. All the Bits in this register are locked in Intel® TXT mode. Datasheet 115 DRAM Controller Registers (D0:F0) 5.1.32 GBSM—Graphics Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI A4–A7h 00000000h RW/L, RO 32 bits This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0, offset B0h, bits 15:4). Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. Bit 31:20 Access & Default RW/L 000h Description Graphics Base of Stolen Memory (GBSM): This register contains bits 31:20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0, offset 52h, bits 6:4) from TOLUD (PCI Device 0, offset B0h, bits 15:04). Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. 19:0 RO 00000h Reserved 116 Datasheet DRAM Controller Registers (D0:F0) 5.1.33 BGSM—Base of GTT stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI A8–ABh 00000000h RW/L, RO 32 bits This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the graphics stolen memory base (PCI Device 0, offset A4h, bits 31:20). Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. Bit 31:20 Access & Default RW/L 000h Description Graphics Base of Stolen Memory (GBSM): This register contains bits 31:20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0, offset 52h, bits 9:8) from the graphics stolen memory base (PCI Device 0, offset A4h, bits 31:20). Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. 19:0 RO 00000h Reserved 5.1.34 TSEGMB—TSEG Memory Base B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI AC–AFh 00000000h RW/L, RO 32 bits This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory by subtracting the TSEG size (PCI Device 0, offset 9Eh, bits 2:1) from graphics GTT stolen base (PCI Device 0, offset A8h, bits 31:20). Once D_LCK has been set, these bits becomes read only. Bit 31:20 Access & Default RW/L 000h Description TESG Memory base (TSEGMB): This register contains bits 31:20 of the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory by subtracting the TSEG size (PCI Device 0, offset 9Eh, bits 2:1) from graphics GTT stolen base (PCI Device 0, offset A8h, bits 31:20). Once D_LCK has been set, these bits becomes read only. 19:0 RO 00000h Reserved Datasheet 117 DRAM Controller Registers (D0:F0) 5.1.35 TOLUD—Top of Low Usable DRAM B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI B0–B1h 0010h RW/L, RO 16 bits This 16 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics Memory and Graphics Stolen Memory are within the DRAM space defined. From the top, (G)MCH optionally claims 1 to 64 MB of DRAM for internal graphics if enabled 1, 2 MB of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for TSEG, if enabled. Programming Example : C1DRB3 is set to 4 GB TSEG is enabled and TSEG size is set to 1 MB Internal Graphics is enabled and Graphics Mode Select set to 32 MB GTT Graphics Stolen Memory Size set to 2 MB BIOS knows the OS requires 1 GB of PCI space. BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the system. This 20MB range at the very top of addressable memory space is lost to APIC and Intel® TXT. According to the above equation, TOLUD is originally calculated to: 4 GB = 1_0000_0000h The system memory requirements are: 4GB (max addressable space) – 1 GB (PCI space) – 35 MB (lost memory) = 3 GB – 35 MB (minimum granularity) = ECB0_0000h Since ECB0_0000h (PCI and other system requirements) is less than 1_0000_0000h, TOLUD should be programmed to ECBh. These bits are Intel® TXT lockable. 118 Datasheet DRAM Controller Registers (D0:F0) Bit 15:4 Access & Default RW/L 001h Description Top of Low Usable DRAM (TOLUD): This register contains bits 31:20 of an address one byte above the maximum DRAM memory below 4 GB that is usable by the operating system. Address bits 31:20 programmed to 01h implies a minimum memory size of 1 MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register. Note that the Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and TSEG. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by TSEG size to determine base of TSEG. All the Bits in this register are locked in Intel® TXT mode. This register must be 64 MB aligned when reclaim is enabled. 3:0 RO 0000b Reserved 5.1.36 ERRSTS—Error Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI C8–C9h 0000h RO, RWC/S 16 bits This register is used to report various error conditions via the SERR DMI messaging mechanism. An SERR DMI message is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated. After the error processing is complete, the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it. Bit 15 14 Access & Default RO 0b RWC/S 0b Reserved Isochronous TBWRR Run Behind FIFO full (ITCV): If set, this bit indicates a VC1 TBWRR is running behind, resulting in the slot timer to stop until the request is able to complete. If this bit is already set, then an interrupt message will not be sent on a new error event. Description Datasheet 119 DRAM Controller Registers (D0:F0) Bit 13 Access & Default RWC/S 0b Description Isochronous TBWRR Run behind FIFO put (ITSTV): If set, this bit indicates a VC1 TBWRR request was put into the run behind. This will likely result in a resulting in a contract violation due to the (G)MCH Express port taking too long to service the isochronous request. If this bit is already set, then an interrupt message will not be sent on a new error event. 12 RWC/S 0b RWC/S 0b (G)MCH Software Generated Event for SMI (GSGESMI): This indicates the source of the SMI was a Device 2 Software Event. (G)MCH Thermal Sensor Event for SMI/SCI/SERR (GTSE): This bit indicates that a (G)MCH Thermal Sensor trip has occurred and an SMI, SCI or SERR has been generated. The status bit is set only if a message is sent based on Thermal event enables in Error command, SMI command and SCI command registers. A trip point can generate one of SMI, SCI, or SERR interrupts (two or more per event is invalid). Multiple trip points can generate the same interrupt, if software chooses this mode, subsequent trips may be lost. If this bit is already set, then an interrupt message will not be sent on a new thermal sensor event. Reserved LOCK to non-DRAM Memory Flag (LCKF): 1 = (G)MCH has detected a lock operation to memory space that did not map into DRAM. Reserved DRAM Throttle Flag (DTF): 1 = DRAM Throttling condition occurred. 0 = Software has cleared this flag since the most recent throttling event. 11 10 9 RO 0b RWC/S 0b 8 7 RO 0b RWC/S 0b 6:0 RO 0s Reserved 120 Datasheet DRAM Controller Registers (D0:F0) 5.1.37 ERRCMD—Error Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI CA–CBh 0000h RO, RW 16 bits This register controls the (G)MCH responses to various system errors. Since the (G)MCH does not have an SERR# signal, SERR messages are passed from the (G)MCH to the ICH over DMI. When a bit in this register is set, a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register. Bit 15:12 11 Access & Default RO 0h RW 0b Reserved SERR on (G)MCH Thermal Sensor Event (TSESERR): 1 = The (G)MCH generates a DMI SERR special cycle when bit 11 of the ERRSTS is set. The SERR must not be enabled at the same time as the SMI for the same thermal sensor event. 0 = Reporting of this condition via SERR messaging is disabled. 10 9 RO 0b RW 0b Reserved SERR on LOCK to non-DRAM Memory (LCKERR): 1 = The (G)MCH will generate a DMI SERR special cycle whenever a processor lock cycle is detected that does not hit DRAM. 0 = Reporting of this condition via SERR messaging is disabled. 8:7 6:0 RW 00b RO 0s Reserved Reserved Description Datasheet 121 DRAM Controller Registers (D0:F0) 5.1.38 SMICMD—SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI CC–CDh 0000h RO, RW 16 bits This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers, respectively. Note that one and only one message type can be enabled. Bit 15:12 11 Access & Default RO 0h RW 0b Reserved SMI on (G)MCH Thermal Sensor Trip (TSTSMI): 1 = A SMI DMI special cycle is generated by (G)MCH when the thermal sensor trip requires an SMI. A thermal sensor trip point cannot generate more than one special cycle. 0 = Reporting of this condition via SMI messaging is disabled. 10:0 RO 0s Reserved Description 5.1.39 SKPD—Scratchpad Data B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI DC–DFh 00000000h RW 32 bits This register holds 32 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. Bit 31:0 Access & Default RW 00000000h Description Scratchpad Data (SKPD): 1 DWord of data storage. 122 Datasheet DRAM Controller Registers (D0:F0) 5.1.40 CAPID0—Capability Identifier B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI E0–EAh 00000100000000010B0009h RO 88 bits Control of bits in this register are only required for customer visible SKU differentiation. Bit 87:79 78 Access & Default RO 0s RO 0b Reserved 82Q35, 82Q33, 82G33 GMCH Dual Independent Display Disable (DIDD): This bit determines whether the component is capable of Dual Independent Display functionality. This functionality requires both functions (0 and 1) to be visible in the Internal Graphics Device 2. This capability is only meaningful if the component is capable of Internal Graphics. Definitions: • Clone mode – Same Image. Different display timing on each pipe. • Twin mode – Same Image. Same exact display timings. Extended Desktop mode – Unique images. Different display timings on each pipe. When Device 2 Function 1 is hidden, the second controller and its associated frame buffer are no longer visible to the Operating System. The OS thinks our device has only one display controller and stops supporting Extended Desktop mode. 0 = Capable of Dual Independent Display (independent frame buffers), Extended Desktop mode is supported. 1 = Not capable of Dual Independent Display. Hardwires bit 4 of the Device Enable (DEVEN) register (Device 0 Offset 54h) to '0'. Clone mode and twin mode are still supported (single frame buffer). 82P35 MCH Reserved 77 RO 0b Dual Channel Disable (DCD): 0 = Dual channel operation allowed 1 = Only single channel operation allowed Description Datasheet 123 DRAM Controller Registers (D0:F0) Bit 76 Access & Default RO 0b Description 2 DIMMS per Channel Disable (2DPCD): 0 = 2 DIMMs per channel Enabled 1 = 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the rank population field for each channel to zero. (MCHBAR offset 260h, bits 22–23 for channel 0 and MCHBAR offset 660h, bits 22–23 for channel 1) 75:73 72 RO 00b RO 0b Reserved Agent Presence Disable (APD): 0 = Disable 1 = Enable 71 RO 0b System Defense Disable (CBD): 0 = Disable 1 = Enable 70 RO 0b Multiprocessor Disable (MD): 0 = (G)MCH capable of Multiple Processors 1 = (G)MCH capable of uni-processor only. 69 RO 0b FAN Speed Control Disable (FSCD): 0 = Disable 1 = Enable 68 RO 0b EastFork Disable (EFD): 0 = Disable 1 = Enable 67:58 57 RO 0s RO 0b Reserved ME Disable (MED): 0 = ME feature is enabled 1 = ME feature is disabled 56:48 47 RO 0s RO 0b Reserved 82Q35, 82Q33, 82G33 GMCH 3D Integrated graphics Disable (3DIGD): 0 = 3D Internal Graphics are enabled 1 = 3D Internal Graphics are disabled. VGA still supported 82P35 MCH Reserved 124 Datasheet DRAM Controller Registers (D0:F0) Bit 46 Access & Default RO 0b Description 82Q35, 82Q33, 82G33 GMCH Internal Graphics Disable (IGD): 0 = There is a graphics engine within this GMCH. Internal Graphics Device (Device #2) is enabled and all of its memory and I/O spaces are accessible. Configuration cycles to Device 2 will be completed within the GMCH. All non-SMM memory and IO accesses to VGA will be handled based on Memory and IO enables of Device 2 and IO registers within Device 2 and VGA Enable of the PCI to PCI bridge control register in Device 1 (If PCI Express GFX attach is supported). A selected amount of Graphics Memory space is preallocated from the main memory based on Graphics Mode Select (GMS in the GMCH Control Register). Graphics Memory is preallocated above TSEG Memory. 1 = There is no graphics engine within this GMCH. Internal Graphics Device (Device #2) and all of its memory and I/O functions are disabled. Configuration cycle targeted to Device 2 will be passed on to DMI. In addition, all clocks to internal graphics logic are turned off. All non-SMM memory and IO accesses to VGA will be handled based on VGA Enable of the PCI to PCI bridge control register in Device 1. DEVEN [4:3] (Device 0, offset 54h) have no meaning. Device 2 Functions 0 and 1 are disabled and hidden. 82P35 MCH Reserved 45 RO 0b PEG Port x16 Disable (PEGX16D): 0 = Capable of x16 PEG Port. 1 = Not Capable of x16 PEG port, instead PEG limited to x8 and below. Causes PEG port to enable and train logical lanes 7:0 only. Logical lanes 15:8 are powered down, and the Max Link Width field of the Link Capability register reports x8 instead of x16. (in the case of lane reversal, lanes 15:8 are active and lanes 7:0 are powered down) 44 RO 0b PCI Express Port Disable (PEGPD): 0 = There is a PCI Express Port on this GMCH. Device 1 and associated memory spaces are accessible. All non-SIMM memory and IO accesses to VGA will be handled based on VGA Enable of the PCI to PCI bridge control register in Device 1 and VGA settings controlling internal graphics VGA if internal graphics is enabled. 1 = There is no PCI Express Port on this GMCH. Device 1 and associated memory and IO spaces are disabled by hardwiring the D1EN field bit 1 of the Device Enable register (DEVEN Dev 0 Offset 54h). In addition, Next_Pointer = 00h, VGA memory and IO cannot decode to the PCI Express interface. From a Physical Layer perspective, all 16 lanes are powered down and the link does not attempt to train. 43:39 RO 00000b Reserved Datasheet 125 DRAM Controller Registers (D0:F0) Bit 38 Access & Default RO 0b DDR3 Disable (DDR3D): Description 0 = Capable of supporting DDR3 SDRAM (82G33 GMCH and 82P35 MCH only) 1 = Not Capable of supporting DDR3 SDRAM 37:34 33:31 RO 0000b RO 000b Reserved DDR Frequency Capability (DDRFC): This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h). Any attempt to write an unsupported value will be ignored. 000 = (G)MCH capable of "All" memory frequencies 001 = Reserved 010 = Reserved 011 = (G)MCH capable of up to DDR2/DDR3 1333 100 = (G)MCH capable of up to DDR2/DDR3 1067 101 = (G)MCH capable of up to DDR2/DDR3 800 110 = (G)MCH capable of up to DDR2/DDR3 667 NOTE: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components. 30:28 RO 000b FSB Frequency Capability (FSBFC): This field controls which values are allowed in the PSB Frequency Select Field 2:0 of the Clocking Configuration Register. These values are determined by the BSEL[2:0] frequency straps. Any unsupported strap values will render the (G)MCH System Memory Interface inoperable. 000 = (G)MCH capable of "All" Memory Frequencies 001 = Reserved 010 = Reserved 011 = (G)MCH capable of up to PSB 1333 100 = (G)MCH capable of up to PSB 1067 101 = (G)MCH capable of up to PSB 800 110 = (G)MCH capable of up to PSB 667 27:24 23:16 15:8 7:0 RO 1h RO 0bh RO 00h RO 09h CAPID Version (CAPIDV): This field has the value 0001b to identify the first revision of the CAPID register definition. CAPID Length (CAPIDL): This field has the value 0bh to indicate the structure length (11 bytes). Next Capability Pointer (NCP): This field is hardwired to 00h indicating the end of the capabilities linked list. Capability Identifier (CAP_ID): This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. 126 Datasheet DRAM Controller Registers (D0:F0) 5.2 MCHBAR The MCHBAR registers are offset from the MCHBAR base address. Table 5-2 provides an address map of the registers listed by address offset in ascending order. Detailed register bit descriptions follow the table. Table 5-2. MCHBAR Register Address Map Address Offset 111h 200–01h 202–203h 204–205h 206–207h 208–209h 20A–20Bh 250–251h 252–255h 256–257h 258–25Ah 25B–25Ch 260–263h 269–26Eh 29C–29Fh 600–601h 602–603h 604–605h 606–607h Register Symbol CHDECMISC C0DRB0 C0DRB1 C0DRB2 C0DRB3 C0DRA01 C0DRA23 C0CYCTRKPCHG C0CYCTRKACT C0CYCTRKWR C0CYCTRKRD C0CYCTRKREFR C0CKECTRL C0REFRCTRL C0ODTCTRL C1DRB0 C1DRB1 C1DRB2 C1DRB3 Register Name Channel Decode Miscellaneous Channel 0 DRAM Rank Boundary Address 0 Channel 0 DRAM Rank Boundary Address 1 Channel 0 DRAM Rank Boundary Address 2 Channel 0 DRAM Rank Boundary Address 3 Channel 0 DRAM Rank 0,1 Attribute Channel 0 DRAM Rank 2,3 Attribute Channel 0 CYCTRK PCHG Channel 0 CYCTRK ACT Channel 0 CYCTRK WR Channel 0 CYCTRK READ Channel 0 CYCTRK REFR Channel 0 CKE Control Channel 0 DRAM Refresh Control Channel 0 ODT Control Channel 1 DRAM Rank Boundary Address 0 Channel 1 DRAM Rank Boundary Address 1 Channel 1 DRAM Rank Boundary Address 2 Channel 1 DRAM Rank Boundary Address 3 Default Value 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 00000000h 0000h 000000h 0000h 00000800h 021830000 C30h 00000000h 0000h 0000h 0000h 0000h Access RW/L RO, RW/L RW/L, RO RW/L, RO RW/L, RO RW/L RW/L RW, RO RW, RO RW RW, RO RO, RW RO, RW, RW/L RW, RO RO, RW RW/L, RO RW/L, RO RW/L, RO RW/L, RO Datasheet 127 DRAM Controller Registers (D0:F0) Address Offset 608–609h 60A–60Bh 650–651h 652–655h 656–657h 658–65Ah 660–663h 669–66Eh 69C–69Fh A00– A01h A02– A03h A04– A05h A06– A07h A08– A09h A0A– A0Bh A19– A1Ah A1C– A1Fh A20– A21h A22– A23h A24– A26h A28– A33h A2Eh A30–A33h CD8h Register Symbol C1DRA01 C1DRA23 C1CYCTRKPCHG C1CYCTRKACT C1CYCTRKWR C1CYCTRKRD C1CKECTRL C1REFRCTRL C1ODTCTRL EPC0DRB0 EPC0DRB1 EPC0DRB2 EPC0DRB3 EPC0DRA01 EPC0DRA23 EPDCYCTRKWRTPRE EPDCYCTRKWRTACT EPDCYCTRKWRTWR EPDCYCTRKWRTREF EPDCYCTRKWRTRD EPDCKECONFIGREG MEMEMSPACE EPDREFCONFIG TSC1 Register Name Channel 1 DRAM Rank 0,1 Attributes Channel 1 DRAM Rank 2,3 Attributes Channel 1 CYCTRK PCHG Channel 1 CYCTRK ACT Channel 1 CYCTRK WR Channel 1 CYCTRK READ Channel 1 CKE Control Channel 1 DRAM Refresh Control Channel 1 ODT Control EP Channel 0 DRAM Rank Boundary Address 0 EP Channel 0 DRAM Rank Boundary Address 1 EP Channel 0 DRAM Rank Boundary Address 2 EP Channel 0 DRAM Rank Boundary Address 3 EP Channel 0 DRAM Rank 0,1 Attribute EP Channel 0 DRAM Rank 2,3 Attribute EPD CYCTRK WRT PRE EPD CYCTRK WRT ACT EPD CYCTRK WRT WR EPD CYCTRK WRT REF EPD CYCTRK WRT READ EPD CKE related configuration registers ME Memory Space Configuration EP DRAM Refresh Configuration Thermal Sensor Control 1 Default Value 0000h 0000h 0000h 00000000h 0000h 000000h 00000800h 021830000 C30h 00000000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 00000000h 0000h 0000h 000000h 00E0000000 h 00h 40000C30h 00h Access RW/L, RW/L RO, RW RO, RW RW, RO, RW RW/L, RW, RO RW, RO RO, RW RW, RO RO, RW RO, RW RW, RO RW RW RW, RO RO, RW RW, RO RO, RW RW RW RW, RO RO, RW RW/L, RW, RS/WC 128 Datasheet DRAM Controller Registers (D0:F0) Address Offset CD9h CDAh CDC–CDFh CE2h CE4h Register Symbol TSC2 TSS TSTTP TCO THERM1 Register Name Thermal Sensor Control 2 Thermal Sensor Status Thermal Sensor Temperature Trip Point Thermal Calibration Offset Hardware Throttle Control Default Value 00h 00h 00000000h 00h 00h Access RW/L, RO RO RO, RW, RW/L RW/L/K, RW/L RW/L, RO, RW/L/K RO, RWC RO, RW RWC/S, RO CEA–CEBh CF1h F14–F17h TIS TSMICMD PMSTS Thermal Interrupt Status Thermal SMI Command Power Management Status 0000h 00h 00000000h Datasheet 129 DRAM Controller Registers (D0:F0) 5.2.1 CHDECMISC—Channel Decode Miscellaneous B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 111h 00h RW/L 8 bits This register has Miscellaneous CHDEC/MAGEN configuration bits. Bit 7 6:5 Access & Default RW/L 0b RW/L 00b Reserved Enhanced Mode Select (ENHMODESEL): 00 = Swap Enabled for Bank Selects and Rank Selects 01 = XOR Enabled for Bank Selects and Rank Selects 10 = Swap Enabled for Bank Selects only 11 = XOR Enabled for Bank Select only This register is locked by ME stolen Memory lock. 4 RW/L 0b Ch2 Enhanced Mode (CH2_ENHMODE): This bit enables Enhanced addressing mode of operation is enabled for Ch 2. 0 = Disable 1 = Enable 3 RW/L 0b Ch1 Enhanced Mode (CH1_ENHMODE): This bit enables Enhanced addressing mode of operation is enabled for Ch 1. 0 = Disable 1 = Enable 2 RW/L 0b Ch0 Enhanced Mode (CH0_ENHMODE): This bit enables Enhanced addressing mode of operation is enabled for Ch 0. 0 = Disable 1 = Enable 1 0 RW/L 0b RW/L 0b Reserved EP Present (EPPRSNT): This bit indicates whether EP UMA is present in the system or not. 0 = Not Present 1 = Present This register is locked by ME stolen Memory lock. Description 130 Datasheet DRAM Controller Registers (D0:F0) 5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 200–201h 0000h R/W, RO 16 bits The DRAM Rank Boundary Registers define the upper boundary address of each DRAM rank with a granularity of 64 MB. Each rank has its own single-word DRB register. These registers are used to determine which chip select will be active for a given address. Channel and rank map: Ch Ch Ch Ch Ch Ch Ch Ch 0, 0, 0, 0, 1, 1, 1, 1, Rank Rank Rank Rank Rank Rank Rank Rank 0 1 2 3 0 1 2 3 = = = = = = = = 200h 202h 204h 206h 600h 602h 604h 606h Programming Guide If Channel 0 is empty, all of the C0DRBs are programmed with 00h. C0DRB0 = Total memory in Ch 0, Rank 0 (in 64 MB increments) C0DRB1 = Total memory in Ch 0, Rank 0 + Ch 0, Rank 1 (in 64 MB increments) … If Channel 1 is empty, all of the C1DRBs are programmed with 00h C1DRB0= Total memory in Ch 1, Rank 0 (in 64 MB increments) C1DRB1= Total memory in Ch 1, Rank 0 + Ch 1, Rank 1 (in 64 MB increments) ... For Flex Memory Mode C1DRB0, C1DRB1, and C1DRB2: They are also programmed similar to non-Flex mode. Only exception is, the DRBs corresponding to the top most populated rank and higher ranks in Channel 1 must be programmed with the value of the total Channel 1 population plus the value of total Channel 0 population (C0DRB3). Example: If only Ranks 0 and 1 are populated in Ch1 in Flex mode, then: C1DRB0 = Total memory in Ch 1, Rank 0 (in 64MB increments) C1DRB1 = C0DRB3 + Total memory in Ch 1, Rank 0 + Ch 1, Rank 1 (in 64 MB increments) (Rank 1 is the topmost populated rank) C1DRB2 = C1DRB1 C1DRB3 = C1DRB1 C1DRB3: C1DRB3 = C0DRB3 + Total memory in Channel 1. Datasheet 131 DRAM Controller Registers (D0:F0) Bit 15:10 9:0 Access & Default RO 000000b R/W 000h Reserved Description Channel 0 Dram Rank Boundary Address 0 (C0DRBA0): This register defines the DRAM rank boundary for rank0 of Channel 0 (64 MB granularity) = R0 R0 = Total Rank 0 memory size is 64 MB R1 = Total Rank 1 memory size is 64 MB R2 = Total Rank 2 memory size is 64 MB R3 = Total Rank 3 memory size is 64 MB 5.2.3 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 202–203h 0000h R/W, RO 16 bits See C0DRB0 register for programming information. Bit 15:10 9:0 Access & Default RO 000000b R/W 000h Reserved Channel 0 Dram Rank Boundary Address 1 (C0DRBA1): This register defines the DRAM rank boundary for rank1 of Channel 0 (64 MB granularity) = (R1 + R0) R0 = Total Rank 0 memory size is 64 MB R1 = Total Rank 1 memory size is 64 MB R2 = Total Rank 2 memory size is 64 MB R3 = Total Rank 3 memory size is 64 MB Description 132 Datasheet DRAM Controller Registers (D0:F0) 5.2.4 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 204–205h 0000h RO, R/W 16 bits See C0DRB0 register for programming information. Bit 15:10 9:0 Access & Default RO 000000b R/W 000h Reserved Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2): This register defines the DRAM rank boundary for rank2 of Channel 0 (64 MB granularity) = (R2 + R1 + R0) R0 = Total Rank 0 memory size is 64 MB R1 = Total Rank 1 memory size is 64 MB R2 = Total Rank 2 memory size is 64 MB R3 = Total Rank 3 memory size is 64 MB Description 5.2.5 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 206–207h 0000h R/W, RO 16 bits See C0DRB0 register for programming information. Bit 15:10 9:0 Access & Default RO 000000b R/W 000h Reserved Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3): This register defines the DRAM rank boundary for rank3 of Channel 0 (64 MB granularity) = (R3 + R2 + R1 + R0) R0 = Total Rank 0 memory size is 64 MB R1 = Total Rank 1 memory size is 64 MB R2 = Total Rank 2 memory size is 64 MB R3 = Total Rank 3 memory size is 64 MB Description Datasheet 133 DRAM Controller Registers (D0:F0) 5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 208–209h 0000h R/W 16 bits The DRAM Rank Attribute Registers define the page sizes/number of banks to be used when accessing different ranks. These registers should be left with their default value (all zeros) for any rank that is unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in the CxDRA registers describes the page size of a pair of ranks. Channel and rank map: Ch Ch Ch Ch 0, 0, 1, 1, Rank Rank Rank Rank 0, 2, 0, 2, 1= 208h–209h 3 = 20Ah–20Bh 1= 608h–609h 3= 60Ah–60Bh DRA[7:0] = "00" means Cfg 0 , DRA[7:0] ="01" means Cfg 1 .... DRA[7:0] = "09" means Cfg 9 and so on. Table 5-3. DRAM Rank Attribute Register Programming Tech 512Mb 512Mb 512Mb 512Mb 1 Gb 1 Gb NOTE: DDRx 2 2 3 3 2,3 2,3 Depth 64M 32M 64M 32M 128M 64M Width 8 16 8 16 8 16 Row 14 13 13 12 14 13 Col 10 10 10 10 10 10 Bank 2 2 3 3 3 3 Row Size 512 MB 256 MB 512 MB 256 MB 1 GB 512 MB Page Size 8k 8k 8k 8k 8k 8k DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components. Bit 15:8 Access & Default R/W 00h R/W 00h Description Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines DRAM pagesize/number-of-banks for rank1 for given channel. See Table 5-3 for programming. Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines DRAM page size/number-of-banks for rank0 for given channel. See Table 5-3 for programming. 7:0 134 Datasheet DRAM Controller Registers (D0:F0) 5.2.7 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 20A–20Bh 0000h R/W 16 bits See C0DRA01 register for programming information. Bit 15:8 Access & Default R/W 00h R/W 00h Description Channel 0 DRAM Rank-3 Attributes (CODRA3): This register defines DRAM pagesize/number-of-banks for rank3 for given channel. See Table 5-3 for programming. Channel 0 DRAM Rank-2 Attributes (CODRA2): This register defines DRAM pagesize/number-of-banks for rank2 for given channel. See Table 5-3 for programming. 7:0 5.2.8 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 250–251h 0000h RW, RO 16 bits This register provides Channel 0 CYCTRK Precharge. Bit 15:11 10:6 Access & Default RO 00000b RW 00000b Reserved Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the same rank-bank. This field corresponds to tWR in the DDR Specification. READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the READ and PRE commands to the same rank-bank. PRE To PRE Delayed (C0sd_cr_pchg_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between two PRE commands to the same rank. Description 5:2 RW 0000b RW 00b 1:0 Datasheet 135 DRAM Controller Registers (D0:F0) 5.2.9 C0CYCTRKACT—Channel 0 CYCTRK ACT B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 252–255h 00000000h RW, RO 32 bits This register provides Channel 0 CYCTRK Activate. Bit 31:28 27:22 Access & Default RO 0h RW 000000b Reserved ACT Window Count (C0sd_cr_act_windowcnt): This field indicates the window duration (in DRAM clocks) during which the controller counts the # of activate commands which are launched to a particular rank. If the number of activate commands launched within this window is greater than 4, then a check is implemented to block launch of further activates to this rank for the rest of the duration of this window. Max ACT Check Disable (C0sd_cr_maxact_dischk): This field disenables the check which ensures that there are no more than four activates to a particular rank in a given window. ACT to ACT Delayed (C0sd_cr_act_act[): This field indicates the minimum allowed spacing (in DRAM clocks) between two ACT commands to the same rank. This field corresponds to tRRD in the DDR Specification. PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the minimum allowed spacing (in DRAM clocks) between the PRE and ACT commands to the same rank-bank. This field corresponds to tRP in the DDR Specification. ALLPRE to ACT Delay (C0sd0_cr_preall_act): From the launch of a prechargeall command wait for these many # of memory clocks before launching a activate command. This field corresponds to tPALL_RP. REF to ACT Delayed (C0sd_cr_rfsh_act): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between REF and ACT commands to the same rank. This field corresponds to tRFC in the DDR Specification. Description 21 RW 0b RW 0000b 20:17 16:13 RW 0000b 12:9 RW 0h RW 00000000 0b 8:0 136 Datasheet DRAM Controller Registers (D0:F0) 5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 256–257h 0000h RW 16 bits This register provides Channel 0 CYCTRK WR. Bit 15:12 Access & Default RW 0h Description ACT To Write Delay (C0sd_cr_act_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the same rank-bank. This field corresponds to tRCD_wr in the DDR Specification. Same Rank Write To Write Delay (C0sd_cr_wrsr_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between two WRITE commands to the same rank. Different Rank Write to Write Delay (C0sd_cr_wrdr_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between two WRITE commands to different ranks. This field corresponds to tWR_WR in the DDR Specification. READ To WRTE Delay (C0sd_cr_rd_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between the READ and WRITE commands. This field corresponds to tRD_WR. 11:8 RW 0h RW 0h 7:4 3:0 RW 0h Datasheet 137 DRAM Controller Registers (D0:F0) 5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 258–25Ah 000000h RW, RO 24 bits This register provides Channel 0 CYCTRK RD. Bit 23:21 20:17 Access & Default RO 000b RW 0h Reserved Min ACT To READ Delay (C0sd_cr_act_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and READ commands to the same rank-bank. This field corresponds to tRCD_rd in the DDR Specification. Same Rank Write To READ Delay (C0sd_cr_wrsr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and READ commands to the same rank. This field corresponds to tWTR in the DDR Specification. Different Ranks Write To READ Delay (C0sd_cr_wrdr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and READ commands to different ranks. This field corresponds to tWR_RD in the DDR Specification. Same Rank Read To Read Delay (C0sd_cr_rdsr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between two READ commands to the same rank. Different Ranks Read To Read Delay (C0sd_cr_rddr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between two READ commands to different ranks. This field corresponds to tRD_RD. Description 16:12 RW 00000b 11:8 RW 0000b 7:4 RW 0000b RW 0000b 3:0 5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 25B–25Ch 0000h RO, RW 16 bits This register provides Channel 0 CYCTRK Refresh. Bit 15:13 12:9 Access & Default RO 000b RW 0000b RW 000000000b Reserved Same Rank PALL to REF Delay (C0sd_cr_pchgall_rfsh): This field indicates the minimum allowed spacing (in DRAM clocks) between the PRE-ALL and REF commands to the same rank. Same Rank REF to REF Delay (C0sd_cr_rfsh_rfsh): This field indicates the minimum allowed spacing (in DRAM clocks) between two REF commands to same ranks. Description 8:0 138 Datasheet DRAM Controller Registers (D0:F0) 5.2.13 C0CKECTRL—Channel 0 CKE Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 260–263h 00000800h RO, RW, RW/L 32 bits This register provides CKE controls for Channel 0 Bit 31:28 27 26:24 Access & Default RO 0000b RW 0b RW 000b Reserved start the self-refresh exit sequence (sd0_cr_srcstart): This field indicates the request to start the self-refresh exit sequence. CKE pulse width requirement in high phase (sd0_cr_cke_pw_hl_safe): This field indicates CKE pulse width requirement in high phase. This field corresponds to tCKE ( high ) in the DDR Specification. Rank 3 Population (sd0_cr_rankpop3): 1 = Rank 3 populated 0 = Rank 3 not populated This register is locked by ME stolen Memory lock. 22 RW/L 0b Rank 2 Population (sd0_cr_rankpop2): 1 = Rank 2 populated 0 = Rank 2 not populated This register is locked by ME stolen Memory lock. 21 RW/L 0b Rank 1 Population (sd0_cr_rankpop1): 1 = Rank 1 populated 0 = Rank 1 not populated This register is locked by ME stolen Memory lock. 20 RW/L 0b Rank 0 Population (sd0_cr_rankpop0): 1 = Rank 0 populated 0 = Rank 0 not populated This register is locked by ME stolen Memory lock. 19:17 RW 000b CKE pulse width requirement in low phase (sd0_cr_cke_pw_lh_safe): This field indicates CKE pulse width requirement in low phase. This field corresponds to tCKE ( low ) in the DDR Specification. Enable CKE toggle for PDN entry/exit (sd0_cr_pdn_enable): This bit indicates that the toggling of CKEs (for PDN entry/exit) is enabled. Reserved Description 23 RW/L 0b 16 RW 0b RO 00b 15:14 Datasheet 139 DRAM Controller Registers (D0:F0) Bit 13:10 Access & Default RW 0010b Description Minimum Powerdown exit to Non-Read command spacing (sd0_cr_txp): This field indicates the minimum number of clocks to wait following assertion of CKE before issuing a non-read command. 0000–0001 = Reserved 0010–1001 = 2–9clocks 1010–1111 = Reserved 9:1 RW 00000000 0b RW 0b Self refresh exit count (sd0_cr_slfrfsh_exit_cnt): This field indicates the Self refresh exit count. (Program to 255). This field corresponds to tXSNR/tXSRD in the DDR Specification. Indicates only 1 DIMM populated (sd0_cr_singledimmpop): This bit, when set, indicates that only 1 DIMM is populated. 0 5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 269–26Eh 021830000C30h RW, RO 48 bits This register provides settings to configure the DRAM refresh controller. Bit 47:42 41:37 Access & Default RO 00h RW 10000b RW 11000b RW 00110b RW 0b Reserved Direct Rcomp Quiet Window (DIRQUIET): This field indicates the amount of refresh_tick events to wait before the service of rcomp request in non-default mode of independent rank refresh. Indirect Rcomp Quiet Window (INDIRQUIET): This field indicates the amount of refresh_tick events to wait before the service of rcomp request in non-default mode of independent rank refresh. Rcomp Wait (RCOMPWAIT): This field indicates the amount of refresh_tick events to wait before the service of rcomp request in nondefault mode of independent rank refresh. Reserved Description 36:32 31:27 26 140 Datasheet DRAM Controller Registers (D0:F0) Bit 25 Access & Default RW 0b Description Refresh Counter Enable (REFCNTEN): This bit is used to enable the refresh counter to count during times that DRAM is not in selfrefresh, but refreshes are not enabled. Such a condition may occur due to need to reprogram DIMMs following DRAM controller switch. This bit has no effect when Refresh is enabled (i.e., there is no mode where Refresh is enabled but the counter does not run). Thus, in conjunction with bit 23 REFEN, the modes are: REFEN:REFCNTEN 0:0 0:1 1:X Description Normal refresh disable Refresh disabled, but counter is accumulating refreshes. Normal refresh enable 24 RW 0b All Rank Refresh (ALLRKREF): This configuration bit enables (by default) that all the ranks are refreshed in a staggered/atomic fashion. If set, the ranks are refreshed in an independent fashion. Refresh Enable (REFEN): Refresh is enabled. 0 = Disabled 1 = Enabled 23 RW 0b 22 RW 0b DDR Initialization Done (INITDONE): Indicates that DDR initialization is complete. 0 = Not Done 1 = Done 21:20 19:18 RW 00b RW 00b Reserved DRAM Refresh Panic Watermark (REFPANICWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_panic flag is set. 00 01 10 11 = = = = 5 6 7 8 17:16 RW 00b DRAM Refresh High Watermark (REFHIGHWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 00 01 10 11 = = = = 3 4 5 6 Datasheet 141 DRAM Controller Registers (D0:F0) Bit 15:14 Access & Default RW 00b Description DRAM Refresh Low Watermark (REFLOWWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_low flag is set. 00 01 10 11 = = = = 1 2 3 4 13:0 RW 001100001 10000b Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a value that will provide 7.8 us at the memory clock frequency. At various memory clock frequencies this results in the following values: 667 MHz -> 1450 hex 5.2.15 C0ODTCTRL—Channel 0 ODT Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register provides ODT controls. Bit 31:12 11:8 7:4 3:0 Access & Default RO 00000h RW 0000b RW 0000b RW 0000b Reserved Reserved Reserved Reserved Description 0/0/0/MCHBAR 29C–29Fh 00000000h RO, RW 32 bits 142 Datasheet DRAM Controller Registers (D0:F0) 5.2.16 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 600–601h 0000h RW/L, RO 16 bits The operation of this register is detailed in the description for register C0DRB0. Bit 15:10 9:0 Access & Default RO 000000b RW/L 000h Reserved Channel 1 DRAM Rank Boundary Address 0 (C1DRBA0): See C0DRB0 register. In stacked mode, if this is the topmost populated rank in Channel 1, program this value to be cumulative of Ch0 DRB3. This register is locked by ME stolen Memory lock. Description 5.2.17 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 602–603h 0000h RW/L, RO 16 bits The operation of this register is detailed in the description for register C0DRB0. Bit 15:10 9:0 Access & Default RO 000000b RW/L 000h Reserved Channel 1 DRAM Rank Boundary Address 1 (C1DRBA1): See C0DRB1 register. In stacked mode, if this is the topmost populated rank in Channel 1, program this value to be cumulative of Ch0 DRB3. This register is locked by ME stolen Memory lock. Description Datasheet 143 DRAM Controller Registers (D0:F0) 5.2.18 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 604–605h 0000h RW/L, RO 16 bits The operation of this register is detailed in the description for register C0DRB0. Bit 15:10 9:0 Access & Default RO 000000b RW/L 000h Reserved Channel 1 DRAM Rank Boundary Address 2 (C1DRBA2): See C0DRB2 register. In stacked mode, if this is the topmost populated rank in Channel 1, program this value to be cumulative of Ch0 DRB3. This register is locked by ME stolen Memory lock. Description 5.2.19 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 606–607h 0000h RW/L, RO 16 bits The operation of this register is detailed in the description for register C0DRB0. Bit 15:10 9:0 Access & Default RO 000000b RW/L 000h Reserved Channel 1 DRAM Rank Boundary Address 3 (C1DRBA3): See C0DRB3 register. In stacked mode, this will be cumulative of Ch0 DRB3. This register is locked by ME stolen Memory lock. Description 144 Datasheet DRAM Controller Registers (D0:F0) 5.2.20 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 608–609h 0000h RW/L 16 bits The operation of this register is detailed in the description for register C0DRA01. Bit 15:8 Access & Default RW/L 00h RW/L 00h Description Channel 1 DRAM Rank-1 Attributes (C1DRA1): See C0DRA1 register. This register is locked by ME stolen Memory lock. 7:0 Channel 1 DRAM Rank-0 Attributes (C1DRA0): See C0DRA0 register. This register is locked by ME stolen Memory lock. 5.2.21 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 60A–60Bh 0000h RW/L 16 bits The operation of this register is detailed in the description for register C0DRA01. Bit 15:8 Access & Default RW/L 00h Description Channel 1 DRAM Rank-3 Attributes (C1DRA3): See C0DRA3 register. This register is locked by ME stolen Memory lock. 7:0 RW/L 00h Channel 1 DRAM Rank-2 Attributes (C1DRA2): See C0DRA2 register. This register is locked by ME stolen Memory lock. Datasheet 145 DRAM Controller Registers (D0:F0) 5.2.22 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 650–651h 0000h RO, RW 16 bits This register provides Channel 1 CYCTRK Precharge. Bit 15:11 10:6 Access & Default RO 00000b RW 00000b Reserved Write To PRE Delayed (C1sd_cr_wr_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the same rank-bank. This field corresponds to tWR in the DDR Specification. READ To PRE Delayed (C1sd_cr_rd_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the READ and PRE commands to the same rank-bank PRE To PRE Delayed (C1sd_cr_pchg_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between two PRE commands to the same rank. Description 5:2 RW 0000b RW 00b 1:0 146 Datasheet DRAM Controller Registers (D0:F0) 5.2.23 C1CYCTRKACT—Channel 1 CYCTRK ACT B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 652–655h 00000000h RO, RW 32 bits This register provides Channel 1 CYCTRK ACT. Bit 31:28 27:22 Access & Default RO 0h RW 000000b Reserved ACT Window Count (C1sd_cr_act_windowcnt): This field indicates the window duration (in DRAM clocks) during which the controller counts the # of activate commands which are launched to a particular rank. If the number of activate commands launched within this window is greater than 4, then a check is implemented to block launch of further activates to this rank for the rest of the duration of this window. Max ACT Check Disable (C1sd_cr_maxact_dischk): This field disenables the check which ensures that there are no more than four activates to a particular rank in a given window. ACT to ACT Delayed (C1sd_cr_act_act[): This field indicates the minimum allowed spacing (in DRAM clocks) between two ACT commands to the same rank. This field corresponds to tRRD in the DDR Specification. PRE to ACT Delayed (C1sd_cr_pre_act): This field indicates the minimum allowed spacing (in DRAM clocks) between the PRE and ACT commands to the same rank-bank:12:9R/W0000bPRE-ALL to ACT Delayed (C1sd_cr_preall_act): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between the PRE-ALL and ACT commands to the same rank. This field corresponds to tRP in the DDR Specification. ALLPRE to ACT Delay (C1sd_cr_preall_act): From the launch of a Prechargeall command wait for these many # of memory clocks before launching a activate command. This field corresponds to tPALL_RP. REF to ACT Delayed (C1sd_cr_rfsh_act): This field indicates the minimum allowed spacing (in DRAM clocks) between REF and ACT commands to the same rank. This field corresponds to tRFC in the DDR Specification. Description 21 RW 0b RW 0000b 20:17 16:13 RW 0000b 12:9 RW 0h RW 00000000 0b 8:0 Datasheet 147 DRAM Controller Registers (D0:F0) 5.2.24 C1CYCTRKWR—Channel 1 CYCTRK WR B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 656–657h 0000h RW 16 bits This register provides Channel 1 CYCTRK WR. Bit 15:12 Access & Default RW 0h Description ACT To Write Delay (C1sd_cr_act_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the same rank-bank. This field corresponds to tRCD_wr in the DDR Specification. Same Rank Write To Write Delayed (C1sd_cr_wrsr_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between two WRITE commands to the same rank. Different Rank Write to Write Delay (C1sd_cr_wrdr_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between two WRITE commands to different ranks. This field corresponds to tWR_WR in the DDR Specification. READ To WRTE Delay (C1sd_cr_rd_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between the READ and WRITE commands. This field corresponds to tRD_WR. 11:8 RW 0h RW 0h 7:4 3:0 RW 0h 148 Datasheet DRAM Controller Registers (D0:F0) 5.2.25 C1CYCTRKRD—Channel 1 CYCTRK READ B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 658–65Ah 000000h RO, RW 24 bits This is the Channel 1 CYCTRK READ register. Bit 23:21 20:17 Access & Default RO 0h RW 0h Reserved Min ACT To READ Delayed (C1sd_cr_act_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and READ commands to the same rank-bank. This field corresponds to tRCD_rd in the DDR Specification. Same Rank Write To READ Delayed (C1sd_cr_wrsr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and READ commands to the same rank. This field corresponds to tWTR in the DDR Specification. Different Ranks Write To READ Delayed (C1sd_cr_wrdr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and READ commands to different ranks. This field corresponds to tWR_RD in the DDR Specification. Same Rank Read To Read Delayed (C1sd_cr_rdsr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between two READ commands to the same rank. Different Ranks Read To Read Delayed (C1sd_cr_rddr_rd): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between two READ commands to different ranks. This field corresponds to tRD_RD. Description 16:12 RW 00000b 11:8 RW 0000b 7:4 RW 0000b RW 0000b 3:0 Datasheet 149 DRAM Controller Registers (D0:F0) 5.2.26 C1CKECTRL—Channel 1 CKE Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 660–663h 00000800h RW/L, RW, RO 32 bits This register provides Channel 1 CKE Controls. Bit 31:28 27 26:24 Access & Default RO 0h RW 0b RW 000b Reserved start the self-refresh exit sequence (sd1_cr_srcstart): This field indicates the request to start the self-refresh exit sequence. CKE pulse width requirement in high phase (sd1_cr_cke_pw_hl_safe): This field indicates CKE pulse width requirement in high phase. This field corresponds to tCKE (high) in the DDR Specification. Rank 3 Population (sd1_cr_rankpop3): 1 = Rank 3 populated 0 = Rank 3 not populated. This register is locked by ME stolen Memory lock. 22 RW/L 0b Rank 2 Population (sd1_cr_rankpop2): 1 = Rank 2 populated 0 = Rank 2 not populated This register is locked by ME stolen Memory lock. 21 RW/L 0b Rank 1 Population (sd1_cr_rankpop1): 1 = Rank 1 populated 0 = Rank 1 not populated. This register is locked by ME stolen Memory lock. 20 RW/L 0b Rank 0 Population (sd1_cr_rankpop0): 1 = Rank 0 populated 0 = Rank 0 not populated This register is locked by ME stolen Memory lock. 19:17 RW 000b CKE pulse width requirement in low phase (sd1_cr_cke_pw_lh_safe): This configuration register indicates CKE pulse width requirement in low phase. This field corresponds to tCKE (low) in the DDR Specification. Enable CKE toggle for PDN entry/exit (sd1_cr_pdn_enable): This configuration bit indicates that the toggling of CKEs (for PDN entry/exit) is enabled. Description 23 RW/L 0b 16 RW 0b 150 Datasheet DRAM Controller Registers (D0:F0) Bit 15:14 13:10 Access & Default RO 00b RW 0010b Reserved Description Minimum Powerdown Exit to Non-Read command spacing (sd1_cr_txp): This configuration register indicates the minimum number of clocks to wait following assertion of CKE before issuing a non-read command. 1010–1111 = Reserved. 0010–1001 = 2-9 clocks 0000–0001 = Reserved. 9:1 RW 000000000b Self refresh exit count (sd1_cr_slfrfsh_exit_cnt): This configuration register indicates the Self refresh exit count. (Program to 255). This field corresponds to tXSNR/tXSRD in the DDR Specification. indicates only 1 DIMM populated (sd1_cr_singledimmpop): This bit, when set, indicates that only 1 DIMM is populated. 0 RW 0b 5.2.27 C1REFRCTRL—Channel 1 DRAM Refresh Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 669–66Eh 021830000C30h RW, RO 48 bits This register provides settings to configure the DRAM refresh controller. Bit 47:42 41:37 Access & Default RO 00h RW 10000b Reserved Direct Rcomp Quiet Window (DIRQUIET): This configuration setting indicates the amount of refresh_tick events to wait before the service of rcomp request in non-default mode of independent rank refresh. Indirect Rcomp Quiet Window (INDIRQUIET): This configuration setting indicates the amount of refresh_tick events to wait before the service of rcomp request in non-default mode of independent rank refresh. Rcomp Wait (RCOMPWAIT): This configuration setting indicates the amount of refresh_tick events to wait before the service of rcomp request in non-default mode of independent rank refresh. ZQCAL Enable (ZQCALEN): This bit enables the DRAM controller to issue ZQCAL S command periodically. 0 = Disable 1 = Enable Description 36:32 RW 11000b 31:27 RW 00110b RW 0b 26 Datasheet 151 DRAM Controller Registers (D0:F0) Bit 25 Access & Default RW 0b Description Refresh Counter Enable (REFCNTEN): This bit is used to enable the refresh counter to count during times that DRAM is not in self-refresh, but refreshes are not enabled. Such a condition may occur due to need to reprogram DIMMs following DRAM controller switch. This bit has no effect when Refresh is enabled (i.e., there is no mode where Refresh is enabled but the counter does not run). Thus, in conjunction with bit 23 REFEN, the modes are: REFEN:REFCNTEN 0:0 0:1 1:X Description Normal refresh disable Refresh disabled, but counter is accumulating refreshes. Normal refresh enable 24 RW 0b RW 0b All Rank Refresh (ALLRKREF): This configuration bit enables (by default) that all the ranks are refreshed in a staggered/atomic fashion. If set, the ranks are refreshed in an independent fashion. Refresh Enable (REFEN): Refresh is enabled. 0 = Disabled 1 = Enabled 23 22 RW 0b DDR Initialization Done (INITDONE): Indicates that DDR initialization is complete. 0 = Not Done 1 = Done 21:20 RW 00b DRAM Refresh Hysterisis (REFHYSTERISIS): Hysterisis level Useful for dref_high watermark cases. The dref_high flag is set when the dref_high watermark level is exceeded, and is cleared when the refresh count is less than the hysterisis level. This field should be set to a value less than the high watermark level. 00 01 10 11 = = = = 3 4 5 6 19:18 RW 00b DRAM Refresh Panic Watermark (REFPANICWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_panic flag is set. 00 01 10 11 = = = = 5 6 7 8 17:16 RW 00b DRAM Refresh High Watermark (REFHIGHWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 00 01 10 11 = = = = 3 4 5 6 152 Datasheet DRAM Controller Registers (D0:F0) Bit 15:14 Access & Default RW 00b Description DRAM Refresh Low Watermark (REFLOWWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_low flag is set. 00 01 10 11 = = = = 1 2 3 4 13:0 RW 00110000 110000b Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a value that will provide 7.8 us at the memory clock frequency. At various memory clock frequencies this results in the following values: 266 MHz -> 820 hex 333 MHz -> A28 hex 400 MHz -> C30 hex 533 MHz -> 104B hex 666 MHz -> 1450 hex 5.2.28 C1ODTCTRL—Channel 1 ODT Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register provides ODT controls. Bit 31:12 11:8 Access & Default RO 00000h RW 0h Reserved DRAM ODT for Read Commands (sd1_cr_odt_duration_rd): Specifies the duration in MDCLKs to assert DRAM ODT for Read Commands. The Async value should be used when the Dynamic Powerdown bit is set. Else use the Sync value. DRAM ODT for Write Commands (sd1_cr_odt_duration_wr): Specifies the duration in MDCLKs to assert DRAM ODT for Write Commands. The Async value should be used when the Dynamic Powerdown bit is set. Else use the Sync value. MCH ODT for Read Commands (sd1_cr_mchodt_duration): Specifies the duration in MDCLKs to assert MCH ODT for Read Commands Description 0/0/0/MCHBAR 69C–69Fh 00000000h RO, RW 32 bits 7:4 RW 0h 3:0 RW 0h Datasheet 153 DRAM Controller Registers (D0:F0) 5.2.29 EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A00–A01h 0000h R/W, RO 16 bits Bit 15:10 9:0 Access & Default RO 000000b R/W 000h Reserved Description Channel 0 Dram Rank Boundary Address 0 (C0DRBA0): 5.2.30 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1 B/D/F/Type: Address Offset: Default Value: Access: Size: See C0DRB0 register. Bit 15:10 9:0 Access & Default RO 000000b RW 000h Reserved Channel 0 Dram Rank Boundary Address 1 (C0DRBA1): Description 0/0/0/MCHBAR A02–A03h 0000h RO, RW 16 bits 5.2.31 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2 B/D/F/Type: Address Offset: Default Value: Access: Size: See C0DRB0 register. Bit 15:10 9:0 Access & Default RO 000000b RW 000h Reserved Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2): Description 0/0/0/MCHBAR A04–A05h 0000h RO, RW 16 bits 154 Datasheet DRAM Controller Registers (D0:F0) 5.2.32 EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3 B/D/F/Type: Address Offset: Default Value: Access: Size: See C0DRB0 register. Bit 15:10 9:0 Access & Default RO 000000b RW 000h Reserved Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3): Description 0/0/0/MCHBAR A06–A07h 0000h RW, RO 16 bits 5.2.33 EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A08–A09h 0000h RW 16 bits The DRAM Rank Attribute Registers define the page sizes/number of banks to be used when accessing different ranks. These registers should be left with their default value (all zeros) for any rank that is unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in the CxDRA registers describes the page size of a pair of ranks. Channel and rank map: Ch0 Rank0, 1: Ch0 Rank2, 3: Ch1 Rank0, 1: Ch1 Rank2, 3: 108h – 109h 10Ah – 10Bh 188h – 189h 18Ah – 18Bh Bit 15:8 7:0 Access & Default RW 00h RW 00h Description Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines DRAM pagesize/number-of-banks for rank1 for given channel. Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines DRAM pagesize/number-of-banks for rank0 for given channel. Datasheet 155 DRAM Controller Registers (D0:F0) 5.2.34 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: See C0DRA01 register. Bit 15:8 7:0 Access & Default RW 00h RW 00h Description Channel 0 DRAM Rank-3 Attributes (C0DRA3): This field defines DRAM pagesize/number-of-banks for rank3 for given channel. Channel 0 DRAM Rank-2 Attributes (C0DRA2): This field defines DRAM pagesize/number-of-banks for rank2 for given channel. 0/0/0/MCHBAR A0A–A0Bh 0000h RW 16 bits 5.2.35 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A19–A1Ah 0000h RW, RO 16 bits This register provides EPD CYCTRK WRT PRE Status. Bit 15:11 Access & Default RW 00000b RW 00000b RW 0000b RO 00b Description ACTTo PRE Delayed (C0sd_cr_act_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and PRE commands to the same rank-bank Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the same rank-bank READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the READ and PRE commands to the same rank-bank Reserved 10:6 5:2 1:0 156 Datasheet DRAM Controller Registers (D0:F0) 5.2.36 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A1C–A1Fh 00000000h RO, RW 32 bits This register provides EPD CYCTRK WRT ACT Status. Bit 31:21 20:17 Access & Default RO 000h RW 0000b RW 0000b Reserved ACT to ACT Delayed (C0sd_cr_act_act[): This field indicates the minimum allowed spacing (in DRAM clocks) between two ACT commands to the same rank. PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the minimum allowed spacing (in DRAM clocks) between the PRE and ACT commands to the same rank-bank:12:9R/W0000bPRE-ALL to ACT Delayed (C0sd_cr_preall_act): This field indicates the minimum allowed spacing (in DRAM clocks) between the PRE-ALL and ACT commands to the same rank. 12:9 8:0 RO 0h RW 00000000 0b Reserved REF to ACT Delayed (C0sd_cr_rfsh_act): This field indicates the minimum allowed spacing (in DRAM clocks) between REF and ACT commands to the same rank. Description 16:13 Datasheet 157 DRAM Controller Registers (D0:F0) 5.2.37 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A20–A21h 0000h RW, RO 16 bits This register provides EPD CYCTRK WRT WR Status. Bit 15:12 Access & Default RW 0h RW 0h RO 0h RW 0h Description ACT To Write Delay (C0sd_cr_act_wr): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the same rank-bank. Same Rank Write To Write Delayed (C0sd_cr_wrsr_wr): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between two WRITE commands to the same rank. Reserved Same Rank WRITE to READ Delay (C0sd_cr_rd_wr): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and READ commands to the same rank 11:8 7:4 3:0 158 Datasheet DRAM Controller Registers (D0:F0) 5.2.38 EPDCYCTRKWRTRD—EPD CYCTRK WRT READ B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/0/0/MCHBAR A24–A26h 000000h RW 24 bits 000h This register provides EPD CYCTRK WRT RD Status. Bit 23:23 22:20 Access & Default RO 0h RW 000b RO 0h RW 0h RW 00000b RO 0h RW 000b RO 0h Reserved EPDunit DQS Slave DLL Enable to Read Safe (EPDSDLL2RD): This field provides the setting for Read command safe from the point of enabling the slave DLLs. Reserved Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and READ commands to the same rank-bank. Same Rank READ to WRITE Delayed (C0sd_cr_wrsr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the READ and WRITE commands. Reserved Same Rank Read To Read Delayed (C0sd_cr_rdsr_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between two READ commands to the same rank. Reserved Description 19:18 17:14 13:9 8:6 5:3 2:0 Datasheet 159 DRAM Controller Registers (D0:F0) 5.2.39 EPDCKECONFIGREG—EPD CKE Related Configuration Register B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/0/0/MCHBAR A28–A2Ch 00E0000000h RW 40 bits 0h This register provides CKE related configuration for EPD. Bit 39:35 Access & Default RW 00000b RW 000b Description EPDunit TXPDLL Count (EPDTXPDLL): This field specifies the delay from precharge power down exit to a command that requires the DRAM DLL to be operational. The commands are read/write. EPDunit TXP count (EPDCKETXP): This field specifies the timing requirement for Active power down exit or fast exit pre-charge power down exit to any command or slow exit pre-charge power down to Non-DLL (rd/wr/odt) command. Mode Select (sd0_cr_sms): This field indicates the mode in which the controller is operating in. 111 = Indicates normal mode of operation, else special mode of operation. 34:32 31:29 RW 111b 28:27 RW 00b EPDunit EMRS command select. (EPDEMRSSEL): EMRS mode to select BANK address. 01 = EMRS 10 = EMRS2 11 = EMRS3 26:24 RW 000b RW 0h RW 000b RO 0h RW 0b CKE pulse width requirement in high phase (sd0_cr_cke_pw_hl_safe): This field indicates CKE pulse width requirement in high phase. one-hot active rank population (ep_scr_actrank): This field indicates the active rank in a one hot manner CKE pulse width requirement in low phase (sd0_cr_cke_pw_lh_safe): This field indicates CKE pulse width requirement in low phase. Reserved EPDunit MPR mode (EPDMPR): MPR Read Mode 1 = MPR mode 0 = Normal mode In MPR mode, only read cycles must be issued by Firmware. Page Results are ignored by DCS and just issues the read chip select. 23:20 19:17 16:15 14 160 Datasheet DRAM Controller Registers (D0:F0) Bit 13 Access & Default RW 0b Description EPDunit Power Down enable for ODT Rank (EPDOAPDEN): Configuration to enable the ODT ranks to dynamically enter power down. 1 = Enable active power down. 0 = Disable active power down. 12 RW 0b EPDunit Power Down enable for Active Rank (EPDAAPDEN): Configuration to enable the active rank to dynamically enter power down. 1 = Enable active power down. 0 = Disable active power down. 11:10 9:1 RO 0h RW 00000000 0b RW 0b Reserved Self refresh exit count (sd0_cr_slfrfsh_exit_cnt): This field indicates the Self refresh exit count. (Program to 255) indicates only 1 rank enabled (sd0_cr_singledimmpop): This field indicates that only 1 rank is enabled. This bit needs to be set if there is one active rank and no odt ranks, or if there is one active rank and one odt rank and they are the same rank. 0 Datasheet 161 DRAM Controller Registers (D0:F0) 5.2.40 MEMEMSPACE—ME Memory Space Configuration B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A2Eh 00h R/W, RO 8 bits This register provides settings to enable the ME memory space and define the size of EP memory if enabled. Bit 7:5 4:0 Access & Default RO 000b R/W 00000b Reserved ME-UMA(Sx) Region Size (EXRS): These bits are written by firmware to indicate the desired size of ME-UMA(Sx) memory region. This is done prior to bring up core power and allowing BIOS to initialize memory. Within channel 0 DDR, the physical base address for MEUMA(Sx) will be determined by: ME-UMA(Sx)BASE = C0DRB3 - EXRS This forces the ME-UMA(Sx) region to always be positioned at the top of the memory populated in channel 0. The approved sizes for MEUMA(Sx) are values between 0000b (0MB, no ME-UMA(Sx) region) and 10000b (16MB ME-UMA(Sx) region) Description 162 Datasheet DRAM Controller Registers (D0:F0) 5.2.41 EPDREFCONFIG—EP DRAM Refresh Configuration B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A30–A33h 40000C30h RO, RW 32 bits This register provides settings to configure the EPD refresh controller. Bit 31 30:29 Access & Default RO 0b RW 10b Reserved EPDunit refresh count addition for self refresh exit. (EPDREF4SR): Configuration indicating the number of additional refreshes that needs to be added to the refresh request count after exiting self refresh. Typical value is to add 2 refreshes. 00 = Add 0 Refreshes 01 = Add 1 Refreshes 10 = Add 2 Refreshes 11 = Add 3 Refreshes Signal name used: ep_scr_refreq_aftersr[1:0] 28 RW 0b Refresh Counter Enable (REFCNTEN): This bit is used to enable the refresh counter to count during times that DRAM is not in selfrefresh, but refreshes are not enabled. Such a condition may occur due to need to reprogram DIMMs following DRAM controller switch. This bit has no effect when Refresh is enabled (i.e. there is no mode where Refresh is enabled but the counter does not run). Thus, in conjunction with bit 23 REFEN, the modes are: REFEN:REFCNTEN 0:0 0:1 1:X 27 RW 0b Description Normal refresh disable Refresh disabled, but counter is accumulating refreshes. Normal refresh enable Description Refresh Enable (REFEN): 0 = Disabled 1 = Enabled 26 RW 0b DDR Initialization Done (INITDONE): Indicates that DDR initialization is complete. 0 = Not Done 1 = Done Datasheet 163 DRAM Controller Registers (D0:F0) Bit 25:22 Access & Default RW 0000b Description DRAM Refresh Hysterisis (REFHYSTERISIS): Hysterisis level Useful for dref_high watermark cases. The dref_high flag is set when the dref_high watermark level is exceeded, and is cleared when the refresh count is less than the hysterisis level. This bit should be set to a value less than the high watermark level. 0000 = 0 0001 = 1 ....... 1000 = 8 21:18 RW 0000b DRAM Refresh High Watermark (REFHIGHWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 0000 = 0 0001 = 1 ....... 1000 = 8 17:14 RW 0000b DRAM Refresh Low Watermark (REFLOWWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_low flag is set. 0000 = 0 0001 = 1 ....... 1000 = 8 13:0 RW 001100001 10000b Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a value that will provide 7.8 us at the memory clock frequency. At various memory clock frequencies this results in the following values: 266 MHz -> 820 hex 333 MHz -> A28 hex 400 MHz -> C30 hex 533 MHz -> 104B hex 666 MHz -> 1450 hex 164 Datasheet DRAM Controller Registers (D0:F0) 5.2.42 TSC1—Thermal Sensor Control 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CD8h 00h RW/L, RW, RS/WC 8 bits This register controls the operation of the thermal sensor. Bits 7:1 of this register are reset to their defaults by CL_PWROK. Bit 0 is reset to its default by PLTRST#. Bit 7 Access & Default RW/L 0b Description Thermal Sensor Enable (TSE): This bit enables power to the thermal sensor. Lockable via TCO bit 7. 0 = Disabled 1 = Enabled 6 RW 0b Analog Hysteresis Control (AHC): This bit enables the analog hysteresis control to the thermal sensor. When enabled, about 1 degree of hysteresis is applied. This bit should normally be off in thermometer mode since the thermometer mode of the thermal sensor defeats the usefulness of analog hysteresis. 0 = hysteresis disabled 1= analog hysteresis enabled. 5:2 RW 0000b Digital Hysteresis Amount (DHA): This bit determines whether no offset, 1 LSB, 2... 15 is used for hysteresis for the trip points. 0000 = digital hysteresis disabled, no offset added to trip temperature 0001 = offset is 1 LSB added to each trip temperature when tripped ... 0110 = ~3.0 °C (Recommended setting) ... 1110 = added to each trip temperature when tripped 1111 = added to each trip temperature when tripped 1 RW/L 0b Thermal Sensor Comparator Select (TSCS): This bit multiplexes between the two analog comparator outputs. Normally Catastrophic is used. Lockable via TCO bit 7. 0 = Catastrophic 1 = Hot Datasheet 165 DRAM Controller Registers (D0:F0) Bit 0 Access & Default RS/WC 0b Description In Use (IU): Software semaphore bit. After a full MCH RESET, a read to this bit returns a 0. After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0, and will then own the usage of the thermal sensor. This bit has no other effect on the hardware, and is only used as a semaphore among various independent software threads that may need to use the thermal sensor. Software that reads this register but does not intend to claim exclusive access of the thermal sensor must write a one to this bit if it reads a 0, in order to allow other software threads to claim it. See also THERM3 bit 7 and IUB, which are independent additional semaphore bits. 5.2.43 TSC2—Thermal Sensor Control 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CD9h 00h RW/L, RO 8 bits This register controls the operation of the thermal sensor. All bits in this register are reset to their defaults by CL_PWROK. Bit 7:4 3:0 Access & Default RO 0h RW/L 0h Reserved Thermometer Mode Enable and Rate (TE): If analog thermal sensor mode is not enabled by setting these bits to 0000b, these bits enable the thermometer mode functions and set the Thermometer controller rate. When the Thermometer mode is disabled and TSC1[TSE] =enabled, the analog sensor mode should be fully functional. In the analog sensor mode, the Catastrophic trip is functional, and the Hot trip is functional at the offset below the catastrophic programmed into TSC2[CHO]. The other trip points are not functional in this mode. When Thermometer mode is enabled, all the trip points (Catastrophic, Hot, Aux0) will all operate using the programmed trip points and Thermometer mode rate. Note: When disabling the Thermometer mode while thermometer running, the Thermometer mode controller will finish the current cycle. Description 166 Datasheet DRAM Controller Registers (D0:F0) Bit Access & Default Description Note: During boot, all other thermometer mode registers (except lock bits) should be programmed appropriately before enabling the Thermometer Mode. Clock used is the memory command clock (i.e., ep_mcclk). Note: The same legacy thermal sensor design in prior (G)MCHs has been used in this design. However, the thermal sensor logic runs in a memory command clock domain that is ½ the frequency of the memory clock used in prior designs. Hence the period counted for the thermal sensor settling time has doubled for the same settings, compared to prior (G)MCHs. Thus the thermal sensor programming should be updated to maintain the same thermometer rate count as in prior (G)MCHs. Lockable via TCO bit 7. 0000 = Thermometer mode disabled (i.e., analog sensor mode) 0001 = enabled, 512 clock mode 0010 = enabled, 1024 clock mode (normal Thermometer mode operation, for DDR 667/800) provides ~6.14 us settling time @ 167 MHz ep_mcclk (DDR 667) provides ~5.12 us settling time @ 200 MHz ep_mcclk (DDR 800) provides ~3.84 us settling time @ 267 MHz ep_mcclk (DDR 1066) 0011 = enabled, 1536 clock mode (normal Thermometer mode operation, for DDR 1066) provides ~9.22 us settling time @ 167 MHz ep_mcclk (DDR provides ~7.68 us settling time @ 200 MHz ep_mcclk (DDR provides ~5.76 us settling time @ 267 MHz ep_mcclk (DDR provides ~4.61 us settling time @ 333 MHz ep_mcclk (DDR 0100 = enabled, 2048 clock mode (normal Thermometer mode operation, for DDR 1333) provides ~15.36 us settling time @ 133 MHz ep_mcclk (DDR 533) provides ~12.29 us settling time @ 167 MHz ep_mcclk (DDR 667) provides ~10.24 us settling time @ 200 MHz ep_mcclk (DDR 800) provides ~7.68 us settling time @ 267 MHz ep_mcclk (DDR 1066) 0101 = enabled, 3072 clock mode 0110 = enabled, 4096 clock mode 0111 = enabled, 6144 clock mode all other permutations are reserved 1111 = enabled, 4 clock mode (for testing digital logic) NOTE: The settling time for DAC and Thermal Diode is between 2 and 5 us. To meet this requirement the SE value must be programmed to be 5 us or more. Recommendation is to use: “0010” setting for DDR 667/800 and “0011” setting for DDR 1066. 667) 800) 1066) 1333) Datasheet 167 DRAM Controller Registers (D0:F0) 5.2.44 TSS—Thermal Sensor Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CDAh 00h RO 8 bits This read only register provides trip point and other status of the thermal sensor. All bits in this register are reset to their defaults by CL_PWROK. Bit 7 Access & Default RO 0b Description Catastrophic Trip Indicator (CTI): 1 = Internal thermal sensor temperature is above the catastrophic setting. Hot Trip Indicator (HTI): 1 = Internal thermal sensor temperature is above the Hot setting. Aux0 Trip Indicator (A0TI): 1 = Internal thermal sensor temperature is above the Aux0 setting. Thermometer Mode Output Valid (TOV): 1 = Thermometer mode is able to converge to a temperature and that the TR register is reporting a reasonable estimate of the thermal sensor temperature. 0 = Thermometer mode is off, or that temperature is out of range, or that the TR register is being looked at before a temperature conversion has had time to complete. 3:2 1 RO 00b RO 0b RO 0b Reserved Direct Catastrophic Comparator Read (DCCR): This bit reads the output of the Catastrophic comparator directly, without latching via the Thermometer mode circuit. Used for testing. Direct Hot Comparator Read (DHCR): This bit reads the output of the Hot comparator directly, without latching via the Thermometer mode circuit. Used for testing. 6 RO 0b RO 0b RO 0b 5 4 0 168 Datasheet DRAM Controller Registers (D0:F0) 5.2.45 TSTTP—Thermal Sensor Temperature Trip Point B/D/F/Type: Address Offset: Default Value: Access: Size: This register : • Sets the target values for the trip points in thermometer mode. See also TST[Direct DAC Connect Test Enable]. • Reports the relative thermal sensor temperature All bits in this register are reset to their defaults by CL_PWROK. Bit 31:24 Access & Default RO 00h Description Relative Temperature (RELT): In Thermometer mode, the RELT field of this register report the relative temperature of the thermal sensor. Provides a two's complement value of the thermal sensor relative to the Hot Trip Point. Temperature above the Hot Trip Point will be positive. TR and HTPS can both vary between 0 and 255. But RELT will be clipped between ±127 to keep it an 8 bit number. See also TSS[Thermometer mode Output Valid] In the Analog mode, the RELT field reports HTPS value. 23:16 15:8 RW 00h RW/L 00h Aux0 Trip point setting (A0TPS): Sets the target for the Aux0 trip point. Hot Trip Point Setting (HTPS): Sets the target value for the Hot trip point. Lockable via TCO bit 7. 7:0 RW/L 00h Catastrophic Trip Point Setting (CTPS): Sets the target for the Catastrophic trip point. See also TST[Direct DAC Connect Test Enable]. Lockable via TCO bit 7. 0/0/0/MCHBAR CDC–CDFh 00000000h RO, RW, RW/L 32 bits Datasheet 169 DRAM Controller Registers (D0:F0) 5.2.46 TCO—Thermal Calibration Offset B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CE2h 00h RW/L/K, RW/L 8 bits Bit 7: reset to its default by PLTRST#. Bits 6:0 reset to their defaults by CL_PWROK. Bit 7 Access & Default RW/L/K 0b Description Lock Bit for Catastrophic (LBC): This bit, when written to a 1, locks the Catastrophic programming interface, including bits 7:0 of this register and bits 15:0 of TSTTP, bits 1,7 of TSC 1, bits 3:0 of TSC 2, bits 4:0 of TSC 3, and bits 0,7 of TST. This bit may only be set to a 0 by a hardware reset (PLTRST#). Writing a 0 to this bit has no effect. Calibration Offset (CO): This field contains the current calibration offset for the Thermal Sensor DAC inputs. The calibration offset is a twos complement signed number which is added to the temperature counter value to help generate the final value going to the thermal sensor DAC. This field is Read/Write and can be modified by Software unless locked by setting bit 7 of this register. The fuses cannot be programmed via this register. Once this register has been overwritten by software, the values of the TCO fuses can be read using the Therm3 register. Note for TCO operation: While this is a seven-bit field, the 7th bit is sign extended to 9 bits for TCO operation. The range of 00h to 3Fh corresponds to 0 0000 0000 to 0 0011 1111. The range of 41h to 7Fh corresponds to 1 1100 001 (i.e., negative 3Fh) to 1 1111 1111 (i.e., negative 1), respectively. 6:0 RW/L 00h 170 Datasheet DRAM Controller Registers (D0:F0) 5.2.47 THERM1—Hardware Throttle Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CE4h 00h RW/L, RO, RW/L/K 8 bits All bits in this register are reset to their defaults by PLTRST#. Bit 7 Access & Default RW/L 00h Description Internal Thermal Hardware Throttling Enable (ITHTE): This bit is a master enable for internal thermal sensor-based hardware throttling. 0 = Disable. Hardware actions via the internal thermal sensor are disabled. 1 = Enable. Hardware actions via the internal thermal sensor are enabled. 6 RW/L 00h Internal Thermal Hardware Throttling Type (ITHTT): This policy bit determines what type of hardware throttling will be enacted by the internal thermal sensor when enabled by ITHTE. 0 = (G)MCH throttling 1 = DRAM throttling 5 4 RO 00h RW/L 00h Reserved Throttling Temperature Range Selection (TTRS): This bit determines what temperature ranges will enable throttling. Lockable by bit 0 of this register. See also the throttling registers in MCHBAR configuration space C0GTC and C1GTC [(G)MCH Thermal Sensor Trip Enable] and PEFC [Thermal Sensor Trip Enable] which are used to enable or disable throttling. 0 = Catastrophic only. The Catastrophic thermal temperature range will enable main memory thermal throttling. 1 = Hot and Catastrophic. 3 RW/L 00h Halt on Catastrophic (HOC): 0 = Continue to toggle clocks when the catastrophic sensor trips. 1 = All clocks are disabled when the catastrophic sensor trips. A system reset is required to bring the system out of a halt from the thermal sensor. 2:1 0 RO 00b RW/L/K 00h Reserved Hardware Throttling Lock Bit (HTL): This bit locks bits 7:0 of this register. 0 = The register bits are unlocked. 1 = The register bits are locked. It may only be set to a 0 by a hardware reset. Writing a 0 to this bit has no effect. Datasheet 171 DRAM Controller Registers (D0:F0) 5.2.48 TIS—Thermal Interrupt Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CEA–CEBh 0000h RO, RWC 16 bits This register is used to report which specific error condition resulted in the dev. 0 fn. 0 ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR Thermal Event. Software can examine the current state of the thermal zones by examining the TSS. Software can distinguish internal or external Trip Event by examining EXTTSCS. Software must write a 1 to clear the status bits in this register. Following scenario is possible. An interrupt is initiated on a rising temperature trip, the appropriate DMI cycles are generated, and eventually the software services the interrupt and sees a rising temperature trip as the cause in the status bits for the interrupts. Assume that the software then goes and clears the local interrupt status bit in the TIS register for that trip event. It is possible at this point that a falling temperature trip event occurs before the software has had the time to clear the global interrupts status bit. But since software has already looked at the status register before this event happened, software may not clear the local status flag for this event. Therefore, after the global interrupt is cleared by software, software must look at the instantaneous status in the TSS register. All bits in this register are reset to their defaults by PLTRST#. Bit 15:10 9 Access & Default RO 00h RWC 0b Reserved Description Was Catastrophic Thermal Sensor Interrupt Event (WCTSIE): 1 = Indicates that a Catastrophic Thermal Sensor trip based on a higher to lower temperature transition thru the trip point 0 = No trip for this event 8 RWC 0b Was Hot Thermal Sensor Interrupt Event (WHTSIE): 1 = Indicates that a Hot Thermal Sensor trip based on a higher to lower temperature transition thru the trip point 0 = No trip for this event 7 RWC 0b Was Aux0 Thermal Sensor Interrupt Event (WA0TSIE): 1 = Indicates that an Aux0 Thermal Sensor trip based on a higher to lower temperature transition thru the trip point 0 = No trip for this event Software must write a 1 to clear this status bit. 6:5 RO 00b Reserved 172 Datasheet DRAM Controller Registers (D0:F0) Bit 4 Access & Default RWC 0b Description Catastrophic Thermal Sensor Interrupt Event (CTSIE): 1 = Indicates that a Catastrophic Thermal Sensor trip event occurred based on a lower to higher temperature transition thru the trip point. 0 = No trip for this event Software must write a 1 to clear this status bit. 3 RWC 0b Hot Thermal Sensor Interrupt Event (HTSIE): 1 = Indicates that a Hot Thermal Sensor trip event occurred based on a lower to higher temperature transition thru the trip point. 0 = No trip for this event Software must write a 1 to clear this status bit. 2 RWC 0b Aux0 Thermal Sensor Interrupt Event (A0TSIE): 1 = Indicates that an Aux0 Thermal Sensor trip event occurred based on a lower to higher temperature transition thru the trip point. 0 = No trip for this event Software must write a 1 to clear this status bit. 1:0 RO 00b Reserved Datasheet 173 DRAM Controller Registers (D0:F0) 5.2.49 TSMICMD—Thermal SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CF1h 00h RO, RW 8 bits This register selects specific errors to generate a SMI DMI special cycle, as enabled by the Device 0 SMI Error Command Register [SMI on (G)MCH Thermal Sensor Trip]. The SMI must not be enabled at the same time as the SERR/SCI for the thermal sensor event. All bits in this register are reset to their defaults by PLTRST#. Bit 7:3 2 Access & Default RO 00h RW 0b Reserved SMI on (G)MCH Catastrophic Thermal Sensor Trip (SMGCTST): 1 = Does not mask the generation of an SMI DMI special cycle on a catastrophic thermal sensor trip. 0 = Disable reporting of this condition via SMI messaging. 1 RW 0b SMI on (G)MCH Hot Thermal Sensor Trip (SMGHTST): 1 = Does not mask the generation of an SMI DMI special cycle on a Hot thermal sensor trip. 0 = Disable reporting of this condition via SMI messaging. 0 RW 0b SMI on (G)MCH Aux Thermal Sensor Trip (SMGATST): 1 = Does not mask the generation of an SMI DMI special cycle on an Auxiliary thermal sensor trip. 0 = Disable reporting of this condition via SMI messaging. Description 174 Datasheet DRAM Controller Registers (D0:F0) 5.2.50 PMSTS—Power Management Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR F14–F17h 00000000h RWC/S, RO 32 bits This register is Reset by PWROK only. Bit 31:9 8 Access & Default RO 000000h RWC/S 0b Reserved Warm Reset Occurred (WRO): Set by the PMunit whenever a Warm Reset is received, and cleared by PWROK=0. 0 = No Warm Reset occurred. 1 = Warm Reset occurred. BIOS Requirement: BIOS can check and clear this bit whenever executing POST code. This way BIOS knows that if the bit is set, then the PMSTS bits [1:0] must also be set, and if not BIOS needs to power-cycle the platform. 7:2 1 RO 00h RWC/S 0b Reserved Channel 1 in Self-Refresh (C1SR): Set by power management hardware after Channel 1 is placed in self refresh as a result of a Power State or a Reset Warn sequence. Cleared by Power management hardware before starting Channel 1 self refresh exit sequence initiated by a power management exit. Cleared by the BIOS by writing a 1 in a warm reset (Reset# asserted while PWROK is asserted) exit sequence. 0 = Channel 1 not ensured to be in self refresh. 1 = Channel 1 in Self Refresh. 0 RWC/S 0b Channel 0 in Self-Refresh (C0SR): Set by power management hardware after Channel 0 is placed in self refresh as a result of a Power State or a Reset Warn sequence. Cleared by Power management hardware before starting Channel 0 self refresh exit sequence initiated by a power management exit. Cleared by the BIOS by writing a 1 in a warm reset (Reset# asserted while PWROK is asserted) exit sequence. 0 = Channel 0 not ensured to be in self refresh. 1 = Channel 0 in Self Refresh. Description Datasheet 175 DRAM Controller Registers (D0:F0) 5.3 EPBAR Table 5-4. EPBAR Register Address Map Address Offset 44–47h 50–53h 58–5Fh 60–63h 68–6Fh Symbol EPESD EPLE1D EPLE1A EPLE2D EPLE2A Register Name EP Element Self Description EP Link Entry 1 Description EP Link Entry 1 Address EP Link Entry 2 Description EP Link Entry 2 Address Default Value 00000201h 01000000h 0000000000 000000h 02000002h 0000000000 008000h Access RO, RWO RO, RWO RO, RWO RO, RWO RO 5.3.1 EPESD—EP Element Self Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 44–47h 00000201h RO, RWO 32 bits This register provides information about the root complex element containing this Link Declaration Capability. Bit 31:24 Access & Default RO 00h Description Port Number (PN): This field specifies the port number associated with this element with respect to the component that contains this element. A value of 00h indicates to configuration software that this is the default Express port. Component ID (CID): This field indicates identifies the physical component that contains this Root Complex Element. BIOS Requirement: Must be initialized according to guidelines in the PCI Express* Isochronous/Virtual Channel Support Hardware Programming Specification (HPS). 15:8 RO 0sh RO 0h RO 1h Number of Link Entries (NLE): This field indicates the number of link entries following the Element Self Description. This field reports 2 (one each for PEG and DMI). Reserved Element Type (ET): This field indicates the type of the Root Complex Element. Value of 1 h represents a port to system memory. 23:16 RWO 00h 7:4 3:0 176 Datasheet DRAM Controller Registers (D0:F0) 5.3.2 EPLE1D—EP Link Entry 1 Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 50–53h 01000000h RO, RWO 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element. Bit 31:24 Access & Default RO 01h Description Target Port Number (TPN): Specifies the port number associated with the element targeted by this link entry (DMI). The target port number is with respect to the component that contains this element as specified by the target component ID. Target Component ID (TCID): This field indicates the physical or logical component that is targeted by this link entry. BIOS Requirement: Must be initialized according to guidelines in the PCI Express* Isochronous/Virtual Channel Support Hardware Programming Specification (HPS). 15:2 1 RO 0000h RO 0b RWO 0b Reserved Link Type (LTYP): This field indicates that the link points to memorymapped space (for RCRB). The link address specifies the 64-bit base address of the target RCRB. Link Valid (LV): 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link. 23:16 RWO 00h 0 5.3.3 EPLE1A—EP Link Entry 1 Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 58–5Fh 0000000000000000h RO, RWO 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element. Bit 63:36 35:12 Access & Default RO 0s RWO 0s RO 0s Reserved Link Address (LA): This field contains the memory mapped base address of the RCRB that is the target element (DMI) for this link entry. Reserved Description 11:0 Datasheet 177 DRAM Controller Registers (D0:F0) 5.3.4 EPLE2D—EP Link Entry 2 Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 60–63h 02000002h RO, RWO 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element. Bit 31:24 Access & Default RO 02h Description Target Port Number (TPN): This field specifies the port number associated with the element targeted by this link entry (PEG). The target port number is with respect to the component that contains this element as specified by the target component ID. Target Component ID (TCID): This field indicates the physical or logical component that is targeted by this link entry. A value of 0 is reserved. Component IDs start at 1. This value is a mirror of the value in the Component ID field of all elements in this component. BIOS Requirement: Must be initialized according to guidelines in the PCI Express* Isochronous/Virtual Channel Support Hardware Programming Specification (HPS). 15:2 1 RO 0s RO 1b Reserved Link Type (LTYP): This field indicates that the link points to configuration space of the integrated device which controls the x16 root port. The link address specifies the configuration address (segment, bus, device, function) of the target root port. 0 RWO 0b Link Valid (LV): 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link. 23:16 RWO 00h 178 Datasheet DRAM Controller Registers (D0:F0) 5.3.5 EPLE2A—EP Link Entry 2 Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 68–6Fh 0000000000008000h RO 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element. Bit 63:28 27:20 19:15 14:12 11:0 Access & Default RO 0s RO 0s RO 00001b RO 000b RO 0s Description Reserved for Configuration Space Base Address (): Not required if root complex has only one configuration space. Bus Number (BUSN): Device Number (DEVN): Target for this link is PCI Express x16 port (Device 1). Function Number (FUNN): Reserved § Datasheet 179 PCI Express* Registers (D1:F0) 6 PCI Express* Registers (D1:F0) Device 1 (D1), Funciton 0 (F0) contains the controls associated with the PCI Express x16 root port that is the intended to attach as the point for external graphics. It also functions as the virtual PCI-to-PCI bridge. Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a valid value unless the register value is stable. The PCI Express* Specification defines two types of reserved bits. Reserved and Preserved: 1. 2. Reserved for future RW implementations; software must preserve value read for writes to bits. Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for writes to bits. Unless explicitly documented as Reserved and Zero, all bits marked as reserved are part of the Reserved and Preserved type, which have historically been the typical definition for Reserved. Note: Most (if not all) control bits in this device cannot be modified unless the link is down. Software is required to first Disable the link, then program the registers, and then reenable the link (which will cause a full-retrain with the new settings). Table 6-1. PCI Express* Register Address Map (D1:F0) Address Offset 00–01h 02–03h 04–05h 06–07h 08h 09–0Bh 0Ch 0Eh 18h 19h 1Ah 1Ch Register Symbol VID1 DID1 PCICMD1 PCISTS1 RID1 CC1 CL1 HDR1 PBUSN1 SBUSN1 SUBUSN1 IOBASE1 Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Cache Line Size Header Type Primary Bus Number Secondary Bus Number Subordinate Bus Number I/O Base Address Default Value 8086h 29C1h 0000h 0010h 00h 060400h 00h 01h 00h 00h 00h F0h Access RO RO RO, RW RO, RWC RO RO RW RO RO RW RW RW, RO 180 Datasheet PCI Express* Registers (D1:F0) Address Offset 1D 1E–1Fh 20–21h 22–23h 24–25h 26–27h 28–2Bh 2C–2Fh 34h 3Ch 3Dh 3E–3Fh 80–83h 84–87h Register Symbol IOLIMIT1 SSTS1 MBASE1 MLIMIT1 PMBASE1 PMLIMIT1 PMBASEU1 PMLIMITU1 CAPPTR1 INTRLINE1 INTRPIN1 BCTRL1 PM_CAPID1 PM_CS1 Register Name I/O Limit Address Secondary Status Memory Base Address Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Limit Address Capabilities Pointer Interrupt Line Interrupt Pin Bridge Control Power Management Capabilities Power Management Control/Status Default Value 00h 0000h FFF0h 0000h FFF1h 0001h 00000000h 00000000h 88h 00h 01h 0000h C8039001h 00000000h Access RW, RO RWC, RO RW, RO RW, RO RW, RO RW, RO RW, RW RO RW RO RO, RW RO RO, RW/S, RW RO RWO RO RW, RO RW, RO RW RO RO, RWO RO RO, RW RO, RWC RO, RWO RO, RW, RW/SC RO RWO, RO RO, RW 88–8Bh 8C–8Fh 90–91h 92–93h 94–97h 98–99h A0–A1h A2–A3h A4–A7h A8–A9h AA–ABh AC–AFh B0–B1h B2–B3h B4–B7h B8–B9h SS_CAPID SS MSI_CAPID MC MA MD PEG_CAPL PEG_CAP DCAP DCTL DSTS LCAP LCTL LSTS SLOTCAP SLOTCTL Subsystem ID and Vendor ID Capabilities Subsystem ID and Subsystem Vendor ID Message Signaled Interrupts Capability ID Message Control Message Address Message Data PCI Express-G Capability List PCI Express-G Capabilities Device Capabilities Device Control Device Status Link Capabilities Link Control Link Status Slot Capabilities Slot Control 0000800Dh 00008086h A005h 0000h 00000000h 0000h 0010h 0141h 00008000h 0000h 0000h 02014D01h 0000h 1001h 00040000h 01C0h Datasheet 181 PCI Express* Registers (D1:F0) Address Offset BA–BBh BC–BDh C0– C3h EC– EFh 100–103h 104–107h 108–10Bh 10C–10Dh 110–113h 114–117h 11A–11Bh 140–143h 144–147h 150–153h 158–15Fh 218–21Fh Register Symbol SLOTSTS RCTL RSTS PEGLC VCECH PVCCAP1 PVCCAP2 PVCCTL VC0RCAP VC0RCTL VC0RSTS RCLDECH ESD LE1D LE1A PEGSSTS Register Name Slot Status Root Control Root Status PCI Express-G Legacy Control Virtual Channel Enhanced Capability Header Port VC Capability Register 1 Port VC Capability Register 2 Port VC Control VC0 Resource Capability VC0 Resource Control VC0 Resource Status Root Complex Link Declaration Enhanced Element Self Description Link Entry 1 Description Link Entry 1 Address PCI Express-G Sequence Status Default Value 0000h 0000h 00000000h 00000000h 14010002h 00000000h 00000000h 0000h 00000000h 800000FFh 0002h 00010005h 02000100h 00000000h 0000000000 000000h 0000000000 000FFFh Access RO, RWC RO, RW RO, RWC RW, RO RO RO RO RO, RW RO RO, RW RO RO RO, RWO RO, RWO RO, RWO RO 182 Datasheet PCI Express* Registers (D1:F0) 6.1 PCI Express* Configuration Register Details (D1:F0) VID1—Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 00–01h 8086h RO 16 bits 6.1.1 This register combined with the Device Identification register uniquely identify any PCI device. Bit 15:0 Access & Default RO 8086h Description Vendor Identification (VID1): PCI standard identification for Intel. 6.1.2 DID1—Device Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 02–03h 29C1h RO 16 bits This register combined with the Vendor Identification register uniquely identifies any PCI device. Bit 15:8 Access & Default RO 29h RO 7h RO 1h Description Device Identification Number (DID1(UB)): Identifier assigned to the (G)MCH device 1 (virtual PCI-to-PCI bridge, PCI Express Graphics port). Device Identification Number (DID1(HW)): Identifier assigned to the (G)MCH device 1 (virtual PCI-to-PCI bridge, PCI Express Graphics port) Device Identification Number (DID1(LB)): Identifier assigned to the (G)MCH device 1 (virtual PCI-to-PCI bridge, PCI Express Graphics port). 7:4 3:0 Datasheet 183 PCI Express* Registers (D1:F0) 6.1.3 PCICMD1—PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 04–05h 0000h RO, RW 16 bits Bit 15:11 10 Access & Default RO 00h RW 0b Reserved Description INTA Assertion Disable (INTAAD): This bit 0nly affects interrupts generated by the device (PCI INTA from a PME or Hot Plug event) controlled by this command register. It does not affect upstream MSIs, upstream PCI INTA–INTD assert and de-assert messages. 0 = This device is permitted to generate INTA interrupt messages. 1 = This device is prevented from generating interrupt messages. Any INTA emulation interrupts already asserted must be de-asserted when this bit is set. 9 8 RO 0b RW 0b Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented. Hardwired to 0. SERR# Message Enable (SERRE1): Controls Device 1 SERR# messaging. The (G)MCH communicates the SERR# condition by sending an SERR message to the ICH. This bit, when set, enables reporting of non-fatal and fatal errors detected by the device to the Root Complex. Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control Register. 0 = The SERR message is generated by the (G)MCH for Device #1 only under conditions enabled individually through the Device Control Register. 1 = The (G)MCH is enabled to generate SERR messages which will be sent to the ICH for specific Device #1 error conditions generated/detected on the primary side of the virtual PCI to PCI bridge (not those received by the secondary side). The status of SERRs generated is reported in the PCISTS1 register. 7 6 RO 0b RW 0b Reserved: Not Applicable or Implemented. Hardwired to 0. Parity Error Response Enable (PERRE): This bit controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set. 0 = Master Data Parity Error bit in PCI Status register can NOT be set. 1 = Master Data Parity Error bit in PCI Status register CAN be set. 5 RO 0b VGA Palette Snoop (VGAPS): Not Applicable or Implemented. Hardwired to 0. 184 Datasheet PCI Express* Registers (D1:F0) Bit 4 3 2 Access & Default RO 0b RO 0b RW 0b Description Memory Write and Invalidate Enable (MWIE): Not Applicable or Implemented. Hardwired to 0. Special Cycle Enable (SCE): Not Applicable or Implemented. Hardwired to 0. Bus Master Enable (BME): This bit controls the ability of the PEG port to forward Memory and IO Read/Write Requests in the upstream direction. This bit does not affect forwarding of Completions from the primary interface to the secondary interface. 0 = This device is prevented from making memory or IO requests to its primary bus. Note that according to PCI Specification, as MSI interrupt messages are in-band memory writes, disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus. Upstream memory writes/reads, IO writes/reads, peer writes/reads, and MSIs will all be treated as invalid cycles. Writes are forwarded to memory address 000C_0000h with byte enables de-asserted. Reads will be forwarded to memory address 000C_0000h and will return Unsupported Request status (or Master abort) in its completion packet. 1 = This device is allowed to issue requests to its primary bus. Completions for previously issued memory read requests on the primary bus will be issued when the data is available. 1 RW 0b Memory Access Enable (MAE): 0 = All of device 1's memory space is disabled. 1 = Enable the Memory and Pre-fetchable memory address ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers. 0 RW 0b IO Access Enable (IOAE): 0 = All of device 1's I/O space is disabled. 1 = Enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers. Datasheet 185 PCI Express* Registers (D1:F0) 6.1.4 PCISTS1—PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 06–07h 0010h RO, RWC 16 bits This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the (G)MCH. Bit 15 Access & Default RO 0b RWC 0b Description Detected Parity Error (DPE): Not Applicable or Implemented. Hardwired to 0. Parity (generating poisoned TLPs) is not supported on the primary side of this device (we don't do error forwarding). Signaled System Error (SSE): This bit is set when this Device sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is 1. Both received (if enabled by BCTRL1[1]) and internally detected error messages affect this field. Received Master Abort Status (RMAS): Not Applicable or Implemented. Hardwired to 0. The concept of a master abort does not exist on primary side of this device. Received Target Abort Status (RTAS): Not Applicable or Implemented. Hardwired to 0. The concept of a target abort does not exist on primary side of this device. Signaled Target Abort Status (STAS): Not Applicable or Implemented. Hardwired to 0. The concept of a target abort does not exist on primary side of this device. DEVSELB Timing (DEVT): This device is not the subtractively decoded device on bus 0. This bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode. Master Data Parity Error (PMDPE): Because the primary side of the PEG's virtual PCI-to-PCI bridge is integrated with the (G)MCH functionality there is no scenario where this bit will get set. Because hardware will never set this bit, it is impossible for software to have an opportunity to clear this bit or otherwise test that it is implemented. The PCI specification defines it as a RWC, but for this implementation an RO definition behaves the same way and will meet all Microsoft testing requirements. This bit can only be set when the Parity Error Enable bit in the PCI Command register is set. 7 6 5 RO 0b RO 0b RO 0b Fast Back-to-Back (FB2B): Not Applicable or Implemented. Hardwired to 0. Reserved 66/60MHz capability (CAP66): Not Applicable or Implemented. Hardwired to 0. 14 13 RO 0b RO 0b RO 0b RO 12 11 10:9 8 RO 0b 186 Datasheet PCI Express* Registers (D1:F0) Bit 4 3 Access & Default RO 1b RO 0b Description Capabilities List (CAPL): Indicates that a capabilities list is present. Hardwired to 1. INTA Status (INTAS): Indicates that an interrupt message is pending internally to the device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit. Reserved 2:0 RO 000b 6.1.5 RID1—Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 08h 00h RO 8 bits This register contains the revision number of the (G)MCH device 1. These bits are read only and writes to this register have no effect. Bit 7:0 Access & Default RO 00h Description Revision Identification Number (RID1): This is an 8-bit value that indicates the revision identification number for the (G)MCH Device 0. Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 6.1.6 CC1—Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 09–0Bh 060400h RO 24 bits This register identifies the basic function of the device, a more specific sub-class, and a register- specific programming interface. Bit 23:16 15:8 7:0 Access & Default RO 06h RO 04h RO 00h Description Base Class Code (BCC): This field indicates the base class code for this device. This code has the value 06h, indicating a Bridge device. Sub-Class Code (SUBCC): This field indicates the sub-class code for this device. The code is 04h indicating a PCI to PCI Bridge. Programming Interface (PI): This field indicates the programming interface of this device. This value does not specify a particular register set layout and provides no practical use for this device. Datasheet 187 PCI Express* Registers (D1:F0) 6.1.7 CL1—Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 0Ch 00h RW 8 bits Bit 7:0 Access & Default RW 00h Description Cache Line Size (Scratch pad): Implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality. 6.1.8 HDR1—Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 0Eh 01h RO 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 Access & Default RO 01h Description Header Type Register (HDR): Returns 01 to indicate that this is a single function device with bridge header layout. 6.1.9 PBUSN1—Primary Bus Number B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 18h 00h RO 8 bits This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI bus #0. Bit 7:0 Access & Default RO 00h Description Primary Bus Number (BUSN): Configuration software typically programs this field with the number of the bus on the primary side of the bridge. Since device 1 is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0. 188 Datasheet PCI Express* Registers (D1:F0) 6.1.10 SBUSN1—Secondary Bus Number B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 19h 00h RW 8 bits This register identifies the bus number assigned to the second bus side of the "virtual" bridge (i.e., to PCI Express-G). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. Bit 7:0 Access & Default RW 00h Description Secondary Bus Number (BUSN): This field is programmed by configuration software with the bus number assigned to PCI Express. 6.1.11 SUBUSN1—Subordinate Bus Number B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 1Ah 00h RW 8 bits This register identifies the subordinate bus (if any) that resides at the level below PCI Express-G. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. Bit 7:0 Access & Default RW 00h Description Subordinate Bus Number (BUSN): This register is programmed by configuration software with the number of the highest subordinate bus that lies behind the device #1 bridge. When only a single PCI device resides on the PCI Express segment, this register will contain the same value as the SBUSN1 register. Datasheet 189 PCI Express* Registers (D1:F0) 6.1.12 IOBASE1—I/O Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 1Ch F0h RW, RO 8 bits This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4 KB boundary. Bit 7:4 3:0 Access & Default RW Fh RO 0h Description I/O Address Base (IOBASE): This field corresponds to A[15:12] of the I/O addresses passed by bridge 1 to PCI Express. Reserved 6.1.13 IOLIMIT1—I/O Limit Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 1Dh 00h RW, RO 8 bits This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4 KB aligned address block. Bit 7:4 Access & Default RW 0h Description I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of the I/O address limit of device 1. Devices between this upper limit and IOBASE1 will be passed to the PCI Express hierarchy associated with this device. Reserved 3:0 RO 0h 190 Datasheet PCI Express* Registers (D1:F0) 6.1.14 SSTS1—Secondary Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 1E–1Fh 0000h RWC, RO 16 bits SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., PCI Express side) of the "virtual" PCI-PCI bridge embedded within (G)MCH. Bit 15 Access & Default RWC 0b Description Detected Parity Error (DPE): This bit is set by the Secondary Side for a Type 1 Configuration Space header device whenever it receives a Poisoned TLP, regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register. Received System Error (RSE): This bit is set when the Secondary Side for a Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL. Received Master Abort (RMA): This bit is set when the Secondary Side for Type 1 Configuration Space Header Device (for requests initiated by the Type 1 Header Device itself) receives a Completion with Unsupported Request Completion Status. Received Target Abort (RTA): This bit is set when the Secondary Side for Type 1 Configuration Space Header Device (for requests initiated by the Type 1 Header Device itself) receives a Completion with Completer Abort Completion Status. Signaled Target Abort (STA): Not Applicable or Implemented. Hardwired to 0. The (G)MCH does not generate Target Aborts (the (G)MCH will never complete a request using the Completer Abort Completion status). DEVSELB Timing (DEVT): Not Applicable or Implemented. Hardwired to 0. Master Data Parity Error (SMDPE): When set, this bit indicates that the (G)MCH received across the link (upstream) a Read Data Completion Poisoned TLP (EP=1). This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set. Fast Back-to-Back (FB2B): Not Applicable or Implemented. Hardwired to 0. Reserved 66/60 MHz capability (CAP66): Not Applicable or Implemented. Hardwired to 0. Reserved 14 RWC 0b RWC 0b 13 12 RWC 0b 11 RO 0b 10:9 8 RO 00b RWC 0b 7 6 5 4:0 RO 0b RO 0b RO 0b RO 00h Datasheet 191 PCI Express* Registers (D1:F0) 6.1.15 MBASE1—Memory Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 20–21h FFF0h RW, RO 16 bits This register controls the processor-to-PCI Express non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB boundary. Bit 15:4 Access & Default RW FFFh RO 0h Description Memory Address Base (MBASE): This field corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express. Reserved 3:0 192 Datasheet PCI Express* Registers (D1:F0) 6.1.16 MLIMIT1—Memory Limit Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 22–23h 0000h RW, RO 16 bits This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1MB aligned memory block. NOTE: Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable PCI Express address ranges (typically where control/status memory-mapped I/O data structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges (typically graphics local memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved processor - PCI Express memory access performance. Note also that configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges i.e. prevent overlap with each other and/or with the ranges covered with the main memory. There is no provision in the (G)MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured. Bit 15:4 Access & Default RW 000h RO 0h Description Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the upper limit of the address range passed to PCI Express. Reserved 3:0 Datasheet 193 PCI Express* Registers (D1:F0) 6.1.17 PMBASE1—Prefetchable Memory Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 24–25h FFF1h RW, RO 16 bits This register in conjunction with the corresponding Upper Base Address register controls the processor-to-PCI Express prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are read/write and correspond to address bits A[39:32] of the 40-bit address. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB boundary. Bit 15:4 Access & Default RW FFFh RO 1h Description Prefetchable Memory Base Address (MBASE): This field corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express. 64-bit Address Support: This field indicates that the upper 32 bits of the prefetchable memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h. 3:0 194 Datasheet PCI Express* Registers (D1:F0) 6.1.18 PMLIMIT1—Prefetchable Memory Limit Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 26–27h 0001h RW, RO 16 bits This register in conjunction with the corresponding Upper Limit Address register controls the processor-to-PCI Express prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to address bits A[39:32] of the 40-bit address. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1MB aligned memory block. Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e. prefetchable) from the processor perspective. Bit 15:4 Access & Default RW 000h RO 1h Description Prefetchable Memory Address Limit (PMLIMIT): This field corresponds to A[31:20] of the upper limit of the address range passed to PCI Express. 64-bit Address Support: This field indicates that the upper 32 bits of the prefetchable memory region limit address are contained in the Prefetchable Memory Base Limit Address register at 2Ch 3:0 Datasheet 195 PCI Express* Registers (D1:F0) 6.1.19 PMBASEU1—Prefetchable Memory Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 28–2Bh 00000000h RW 32 bits The functionality associated with this register is present in the PEG design implementation. This register in conjunction with the corresponding Upper Base Address register controls the processor-to-PCI Express prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are read/write and correspond to address bits A[39:32] of the 40-bit address. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB boundary. Bit 31:0 Access & Default RW 00000000h Description Prefetchable Memory Base Address (MBASEU): This field corresponds to A[63:32] of the lower limit of the prefetchable memory range that will be passed to PCI Express. 196 Datasheet PCI Express* Registers (D1:F0) 6.1.20 PMLIMITU1—Prefetchable Memory Limit Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 2C–2Fh 00000000h RW 32 bits The functionality associated with this register is present in the PEG design implementation. This register in conjunction with the corresponding Upper Limit Address register controls the processor-to-PCI Express prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to address bits A[39:32] of the 40-bit address. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1MB aligned memory block. Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e. prefetchable) from the processor perspective. Bit 31:0 Access & Default RW 00000000h Description Prefetchable Memory Address Limit (MLIMITU): This field corresponds to A[63:32] of the upper limit of the prefetchable Memory range that will be passed to PCI Express. Datasheet 197 PCI Express* Registers (D1:F0) 6.1.21 CAPPTR1—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 34h 88h RO 8 bits The capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. Bit 7:0 Access & Default RO 88h Description First Capability (CAPPTR1): The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability. 6.1.22 INTRLINE1—Interrupt Line B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 3Ch 00h RW 8 bits This register contains interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information. Bit 7:0 Access & Default RW 00h Description Interrupt Connection (INTCON): Used to communicate interrupt line routing information. 6.1.23 INTRPIN1—Interrupt Pin B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 3Dh 01h RO 8 bits This register specifies which interrupt pin this device uses. Bit 7:0 Access & Default RO 01h Description Interrupt Pin (INTPIN): As a single function device, the PCI Express device specifies INTA as its interrupt pin. 01h=INTA. 198 Datasheet PCI Express* Registers (D1:F0) 6.1.24 BCTRL1—Bridge Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 3E–3Fh 0000h RO, RW 16 bits This register provides extensions to the PCICMD1 register that are specific to PCI-toPCI bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI Express) as well as some bits that affect the overall behavior of the "virtual" HostPCI Express bridge in the (G)MCH (e.g., VGA compatible address ranges mapping). Bit 15:12 11 10 9 8 7 6 Access & Default RO 0h RO 0b RO 0b RO 0b RO 0b RO 0b RW 0b Reserved Discard Timer SERR# Enable (DTSERRE): Not Applicable or Implemented. Hardwired to 0. Discard Timer Status (DTSTS): Not Applicable or Implemented. Hardwired to 0. Secondary Discard Timer (SDT): Not Applicable or Implemented. Hardwired to 0. Primary Discard Timer (PDT): Not Applicable or Implemented. Hardwired to 0. Fast Back-to-Back Enable (FB2BEN): Not Applicable or Implemented. Hardwired to 0. Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset on the corresponding PCI Express Port. This will force the LTSSM to transition to the Hot Reset state (via Recovery) from L0, L0s, or L1 states. Master Abort Mode (MAMODE): Does not apply to PCI Express. Hardwired to 0. VGA 16-bit Decode (VGA16D): Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O decoding and forwarding by the bridge. 0 = Execute 10-bit address decodes on VGA I/O accesses. 1 = Execute 16-bit address decodes on VGA I/O accesses. 3 RW 0b VGA Enable (VGAEN): This bit controls the routing of processor initiated transactions targeting VGA compatible I/O and memory address ranges. Description 5 4 RO 0b RW 0b Datasheet 199 PCI Express* Registers (D1:F0) Bit 2 Access & Default RW 0b Description ISA Enable (ISAEN): Needed to exclude legacy resource decode to route ISA resources to legacy decode path. This bit modifies the response by the (G)MCH to an I/O access issued by the processor that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers. 0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O transactions will be mapped to PCI Express. 1 = (G)MCH will not forward to PCI Express any I/O transactions addressing the last 768 bytes in each 1 KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. 1 RW 0b SERR Enable (SERREN): 0 = No forwarding of error messages from secondary side to primary side that could result in an SERR. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register. 0 RW 0b Parity Error Response Enable (PEREN): This bit controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the (G)MCH receives across the link (upstream) a Read Data Completion Poisoned TLP. 0 = Master Data Parity Error bit in Secondary Status register can NOT be set. 1 = Master Data Parity Error bit in Secondary Status register CAN be set. 200 Datasheet PCI Express* Registers (D1:F0) 6.1.25 PM_CAPID1—Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 80–83h C8039001h RO 32 bits Bit 31:27 Access & Default RO 19h Description PME Support (PMES): This field indicates the power states in which this device may indicate PME wake via PCI Express messaging. D0, D3hot & D3cold. This device is not required to do anything to support D3hot & D3cold, it simply must report that those states are supported. Refer to the PCI Power Management 1.1 specification for encoding explanation and other power management details. D2 Power State Support (D2PSS): Hardwired to 0 to indicate that the D2 power management state is NOT supported. D1 Power State Support (D1PSS): Hardwired to 0 to indicate that the D1 power management state is NOT supported. Auxiliary Current (AUXC): Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary current requirements. Device Specific Initialization (DSI): Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it. Auxiliary Power Source (APS): Hardwired to 0. PME Clock (PMECLK): Hardwired to 0 to indicate this device does NOT support PMEB generation. PCI PM CAP Version (PCIPMCV): A value of 011b indicates that this function complies with revision 1.2 of the PCI Power Management Interface Specification. Pointer to Next Capability (PNC): This contains a pointer to the next item in the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the capabilities list is the Message Signaled Interrupts (MSI) capability at 90h Capability ID (CID): Value of 01h identifies this linked list item (capability structure) as being for PCI Power Management registers. 26 25 24:22 21 RO 0b RO 0b RO 000b RO 0b RO 0b RO 0b RO 011b RO 90h 20 19 18:16 15:8 7:0 RO 01h Datasheet 201 PCI Express* Registers (D1:F0) 6.1.26 PM_CS1—Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 84–87h 00000000h RO, RW/S, RW 32 bits Bit 31:16 15 14:13 12:9 8 Access & Default RO 0000h RO 0b RO 00b RO 0h RW/S 0b Description Reserved: Not Applicable or Implemented. Hardwired to 0. PME Status (PMESTS): Indicates that this device does not support PME# generation from D3cold. Data Scale (DSCALE): Indicates that this device does not support the power management data register. Data Select (DSEL): Indicates that this device does not support the power management data register. PME Enable (PMEE): Indicates that this device does not generate PMEB assertion from any D-state. 0 = PMEB generation not possible from any D State 1 = PMEB generation enabled from any D State The setting of this bit has no effect on hardware. See PM_CAP[15:11] 7:2 1:0 RO 00h RW 00b Reserved Power State (PS): This field indicates the current power state of this device and can be used to set the device into a new power state. If software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. 00 01 10 11 = = = = D0 D1 (Not supported in this device. D2 (Not supported in this device.) D3 Support of D3cold does not require any special action. While in the D3hot state, this device can only act as the target of PCI configuration transactions (for power management control). This device also cannot generate interrupts or respond to MMR cycles in the D3 state. The device must return to the D0 state to be fully-functional. When the Power State is other than D0, the bridge will Master Abort (i.e., not claim) any downstream cycles (with exception of type 0 configuration cycles). Consequently, these unclaimed cycles will go down DMI and come back up as Unsupported Requests, which the (G)MCH logs as Master Aborts in Device 0 PCISTS[13] There is no additional hardware functionality required to support these Power States. 202 Datasheet PCI Express* Registers (D1:F0) 6.1.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 88–8Bh 0000800Dh RO 32 bits This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. However, it is necessary because Microsoft will test for its presence. Bit 31:16 15:8 Access & Default RO 0000h RO 80h RO 0Dh Reserved Pointer to Next Capability (PNC): This contains a pointer to the next item in the capabilities list which is the PCI Power Management capability. Capability ID (CID): Value of 0Dh identifies this linked list item (capability structure) as being for SSID/SSVID registers in a PCI-to-PCI Bridge. Description 7:0 6.1.28 SS—Subsystem ID and Subsystem Vendor ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 8C–8Fh 00008086h RWO 32 bits System BIOS can be used as the mechanism for loading the SSID/SVID values. These values must be preserved through power management transitions and a hardware reset. Bit 31:16 15:0 Access & Default RWO 0000h RWO 8086h Description Subsystem ID (SSID): Identifies the particular subsystem and is assigned by the vendor. Subsystem Vendor ID (SSVID): Identifies the manufacturer of the subsystem and is the same as the vendor ID which is assigned by the PCI Special Interest Group. Datasheet 203 PCI Express* Registers (D1:F0) 6.1.29 MSI_CAPID—Message Signaled Interrupts Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 90–91h A005h RO 16 bits When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. Bit 15:8 7:0 Access & Default RO A0h RO 05h Description Pointer to Next Capability (PNC): This contains a pointer to the next item in the capabilities list which is the PCI Express capability. Capability ID (CID): Value of 05h identifies this linked list item (capability structure) as being for MSI registers. 6.1.30 MC—Message Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 92–93h 0000h RW, RO 16 bits System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is ensured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one. Bit 15:8 7 Access & Default RO 00h RO 0b RW 000b Reserved 64-bit Address Capable (64AC): Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64-bit memory address. Multiple Message Enable (MME): System software programs this field to indicate the actual number of messages allocated to this device. This number will be equal to or less than the number actually requested. The encoding is the same as for the MMC field below. 3:1 RO 000b Multiple Message Capable (MMC): System software reads this field to determine the number of messages being requested by this device. 000 = 1 message requested All others are reserved. Description 6:4 204 Datasheet PCI Express* Registers (D1:F0) Bit 0 Access & Default RW 0b Description MSI Enable (MSIEN): Controls the ability of this device to generate MSIs. 0 = MSI will not be generated. 1 = MSI will be generated when we receive PME or HotPlug messages. INTA will not be generated and INTA Status (PCISTS1[3]) will not be set. 6.1.31 MA—Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 94–97h 00000000h RW, RO 32 bits Bit 31:2 Access & Default RW 00000000h RO 00b Description Message Address (MA): Used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address. Force DWord Align (FDWA): Hardwired to 0 so that addresses assigned by system software are always aligned on a DWord address boundary. 1:0 6.1.32 MD—Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: Bit 15:0 Access & Default RW 0000h 0/1/0/PCI 98–99h 0000h RW 16 bits Description Message Data (MD): Base message data pattern assigned by system software and used to handle an MSI from the device. When the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register. The upper 16 bits are always set to 0. The lower 16 bits are supplied by this register. Datasheet 205 PCI Express* Registers (D1:F0) 6.1.33 PEG_CAPL—PCI Express*-G Capability List B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI A0–A1h 0010h RO 16 bits This register enumerates the PCI Express capability structure. Bit 15:8 Access & Default RO 00h Description Pointer to Next Capability (PNC): This value terminates the capabilities list. The Virtual Channel capability and any other PCI Express specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space. Capability ID (CID): Identifies this linked list item (capability structure) as being for PCI Express registers. 7:0 RO 10h 6.1.34 PEG_CAP—PCI Express*-G Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI A2–A3h 0141h RO, RWO 16 bits This register indicates PCI Express device capabilities. Bit 15:14 13:9 8 Access & Default RO 00b RO 00h RWO 1b Reserved Interrupt Message Number (IMN): Not Applicable or Implemented. Hardwired to 0. Slot Implemented (SI): 0 = The PCI Express Link associated with this port is connected to an integrated component or is disabled. 1 = The PCI Express Link associated with this port is connected to a slot. 7:4 3:0 RO 4h RO 1h Device/Port Type (DPT): Hardwired to 4h to indicate root port of PCI Express Root Complex. PCI Express Capability Version (PCI EXPRESS*CV): Hardwired to 1 as it is the first version. Description 206 Datasheet PCI Express* Registers (D1:F0) 6.1.35 DCAP—Device Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI A4–A7h 00008000h RO 32 bits This register indicates PCI Express device capabilities. Bit 31:16 15 Access & Default RO 0000h RO 1b RO 000h RO 0b RO 00b RO 000b Description Reserved: Not Applicable or Implemented. Hardwired to 0. Role Based Error Reporting (RBER): This bit indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 specification. Reserved: Not Applicable or Implemented. Hardwired to 0. Extended Tag Field Supported (ETFS): Hardwired to indicate support for 5-bit Tags as a Requestor. Phantom Functions Supported (PFS): Not Applicable or Implemented. Hardwired to 0. Max Payload Size (MPS): Hardwired to indicate 128B max supported payload for Transaction Layer Packets (TLP). 14:6 5 4:3 2:0 Datasheet 207 PCI Express* Registers (D1:F0) 6.1.36 DCTL—Device Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI A8–A9h 0000h RO, RW 16 bits This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register. Bit 15:8 7:5 Access & Default RO 000h RW 000b Reserved Max Payload Size (MPS): 000 = 128B max supported payload for Transaction Layer Packets (TLP). As a receiver, the Device must handle TLPs as large as the set value; as transmitter, the Device must not generate TLPs exceeding the set value. All other encodings are reserved. Hardware will actually ignore this field. It is writeable only to support compliance testing. 4 3 RO 0b RW 0b Reserved: For Enable Relaxed Ordering Unsupported Request Reporting Enable (URRE): When set, allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_CORR to the Root Control register when detecting an unmasked Unsupported Request (UR). An ERR_CORR is signaled when an unmasked Advisory Non-Fatal UR is received. An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non-Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register. Fatal Error Reporting Enable (FERE): When set, enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. Non-Fatal Error Reporting Enable (NERE): When set, enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. Correctable Error Reporting Enable (CERE): When set, enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. Description 2 RW 0b 1 RW 0b 0 RW 0b 208 Datasheet PCI Express* Registers (D1:F0) 6.1.37 DSTS—Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI AA–ABh 0000h RO, RWC 16 bits This register reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link. Bit 15:6 5 Access & Default RO 000h RO 0b Description Reserved and Zero: For future R/WC/S implementations; software must use 0 for writes to bits. Transactions Pending (TP): 0 = All pending transactions (including completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1 = Device has transaction(s) pending (including completions for any outstanding non-posted requests for all used Traffic Classes). 4 3 RO 0b RWC 0b Reserved Unsupported Request Detected (URD): 0 = Unsupported request Not detected. 1 = Device received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register. Additionally, the Non-Fatal Error Detected bit or the Fatal Error Detected bit is set according to the setting of the Unsupported Request Error Severity bit. In production systems setting the Fatal Error Detected bit is not an option as support for AER will not be reported. 2 RWC 0b Fatal Error Detected (FED): 0 = Fatal error Not detected. 1 = Fatal error(s) were detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. When Advanced Error Handling is enabled, errors are logged in this register regardless of the settings of the uncorrectable error mask register. 1 RWC 0b Non-Fatal Error Detected (NFED): 0 = Non-Fatal error Not detected. 1 = Non-fatal error(s) were detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. When Advanced Error Handling is enabled, errors are logged in this register regardless of the settings of the uncorrectable error mask register. Datasheet 209 PCI Express* Registers (D1:F0) Bit 0 Access & Default RWC 0b Description Correctable Error Detected (CED): 0 = Correctable error Not detected. 1 = Correctable error(s) were detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. When Advanced Error Handling is enabled, errors are logged in this register regardless of the settings of the correctable error mask register. 6.1.38 LCAP—Link Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI AC–AFh 02014D01h RO, RWO 32 bits This register indicates PCI Express device specific capabilities. Bit 31:24 Access & Default RO 02h RO 000b RO 0b Description Port Number (PN): This field indicates the PCI Express port number for the given PCI Express link. Matches the value in Element Self Description[31:24]. Reserved Data Link Layer Link Active Reporting Capable (DLLLARC): For a Downstream Port, this bit must be set to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable field of the Slot Capabilities register), this bit must be set to 1b. For Upstream Ports and components that do not support this optional capability, this bit must be hardwired to 0b. 19 RO 0b Surprise Down Error Reporting Capable (SDERC): For a Downstream Port, this bit must be set to 1b if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and components that do not support this optional capability, this bit must be hardwired to 0b. 23:21 20 210 Datasheet PCI Express* Registers (D1:F0) Bit 18 Access & Default RO 0b Description Clock Power Management (CPM): A value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) when the link is in the L1 and L2/3 Ready link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these link states. This capability is applicable only in form factors that support “clock request” (CLKREQ#) capability. For a multi-function device, each function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1b in this bit. 17:15 RWO 010b L1 Exit Latency (L1ELAT): This field indicates the length of time this Port requires to complete the transition from L1 to L0. The value 010 b indicates the range of 2 us to less than 4 us. Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate (and undesired) value from ever existing. 14:12 RO 100b L0s Exit Latency (L0SELAT): Indicates the length of time this Port requires to complete the transition from L0s to L0. 000 001 010 011 100 101 110 111 = = = = = = = = Less than 64 ns 64ns to less than 128ns 128ns to less than 256 ns 256ns to less than 512 ns 512ns to less than 1 us 1 us to less than 2 us 2 us – 4 us More than 4 us The actual value of this field depends on the common Clock Configuration bit (LCTL[6]) and the Common and Non-Common clock L0s Exit Latency values in PEGL0SLAT (Offset 22Ch) 11:10 RWO 11b Active State Link PM Support (ASLPMS): 00 01 10 11 = = = = Reserved L0s is supported Reserved L1 and L0s are supported 9:4 3:0 RO 10h RO 1h Max Link Width (MLW): This field indicates the maximum number of lanes supported for this link. Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s. Datasheet 211 PCI Express* Registers (D1:F0) 6.1.39 LCTL—Link Control B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/1/0/PCI B0–B1h 0000h RO, RW, RW/SC 16 bits 0h This register allows control of PCI Express link. Bit 15:9 8 Access & Default RO 0000000b RO 0b Reserved Enable Clock Power Management (ECPM): Applicable only for form factors that support a “Clock Request” (CLKREQ#) mechanism, this enable functions as follows 0 = Disable. Clock power management is disabled and device must hold CLKREQ# signal low (Default) 1 = Enable. Device is permitted to use CLKREQ# signal to power manage link clock according to protocol defined in appropriate form factor specification. Components that do not support Clock Power Management (as indicated by a 0b value in the Clock Power Management bit of the Link Capabilities Register) must hardwire this bit to 0b. 7 RW 0b Extended Synch (ES): 0 = Standard Fast Training Sequence (FTS). 1 = Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state. This mode provides external devices (e.g., logic analyzers) monitoring the Link time to achieve bit and symbol lock before the link enters L0 and resumes communication. This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns. 6 RW 0b Common Clock Configuration (CCC): The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and the N_FTS value advertised during link training. See PEGL0SLAT at offset 22Ch. 0 = This component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1 = This component and the component at the opposite end of this Link are operating with a distributed common reference clock. 5 RW/SC 0b Retrain Link (RL): This bit always returns 0 when read. This bit is cleared automatically (no need to write a 0). 0 = Normal operation. 1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from L0, L0s, or L1 states to the Recovery state. Description 212 Datasheet PCI Express* Registers (D1:F0) Bit 4 Access & Default RW 0b Description Link Disable (LD): Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state. 0 = Normal operation 1 = Link is disabled. Forces the LTSSM to transition to the Disabled state (via Recovery) from L0, L0s, or L1 states. Link retraining happens automatically on 0 to 1 transition, just like when coming out of reset. 3 2 1:0 RO 0b RW 0b RW 00b Read Completion Boundary (RCB): Hardwired to 0 to indicate 64 byte. Far-End Digital Loopback (FEDLB): Active State PM (ASPM): This field controls the level of active state power management supported on the given link. 00 = Disabled 01 = L0s Entry Supported 10 = Reserved 11 = L0s and L1 Entry Supported Datasheet 213 PCI Express* Registers (D1:F0) 6.1.40 LSTS—Link Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI B2–B3h 1001h RO 16 bits This register indicates PCI Express link status. “ Bit 15:14 13 Access & Default RO 00b RO 0b Description Reserved and Zero: For future R/WC/S implementations; software must use 0 for writes to bits. Data Link Layer Link Active (Optional) (DLLLA): This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise. This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented. Otherwise, this bit must be hardwired to 0b. 12 RO 1b Slot Clock Configuration (SCC): 0 = The device uses an independent clock irrespective of the presence of a reference on the connector. 1 = The device uses the same physical reference clock that the platform provides on the connector. 11 RO 0b Link Training (LTRN): This bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state once Link training is complete. Undefined: The value read from this bit is undefined. In previous versions of this specification, this bit was used to indicate a Link Training Error. System software must ignore the value read from this bit. System software is permitted to write any value to this bit. Negotiated Width (NW): Indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). 00h 01h 02h 04h 08h 10h = = = = = = Reserved X1 Reserved Reserved Reserved X16 10 RO 0b 9:4 RO 00h All other encodings are reserved. 3:0 RO 1h Negotiated Speed (NS): Indicates negotiated link speed. 1h = 2.5 Gb/s All other encodings are reserved. 214 Datasheet PCI Express* Registers (D1:F0) 6.1.41 SLOTCAP—Slot Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI B4–B7h 00040000h RWO, RO 32 bits PCI Express Slot related registers allow for the support of Hot Plug. Bit 31:19 18 Access & Default RWO 0000h RWO 1b Description Physical Slot Number (PSN): Indicates the physical slot number attached to this Port. No Command Completed Support (NCCS): 1 = This slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set to 1b if the hotplug capable port is able to accept writes to all fields of the Slot Control register without delay between successive writes. Reserved for Electromechanical Interlock Present (EIP): Slot Power Limit Scale (SPLS): This field specifies the scale used for the Slot Power Limit Value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x If this field is written, the link sends a Set_Slot_Power_Limit message. 14:7 RWO 00h Slot Power Limit Value (SPLV): In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. If this field is written, the link sends a Set_Slot_Power_Limit message. 6 RO 0b Hot-plug Capable (HPC): 0 = Not Hot-plug capable 1 = Slot is capable of supporting hot-lug operations. 5 RO 0b Hot-plug Surprise (HPS): 0 = No Hot-plug surprise 1 = An adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the operating system to allow for such removal without impacting continued software operation. 17 16:15 RO 0b RWO 00b Datasheet 215 PCI Express* Registers (D1:F0) Bit 4 Access & Default RO 0b Description Power Indicator Present (PIP): 0 = No power indicator 1 = A Power Indicator is electrically controlled by the chassis for this slot. 3 RO 0b Attention Indicator Present (AIP): 0 = No Attention indicator 1 = An Attention Indicator is electrically controlled by the chassis. 2 RO 0b MRL Sensor Present (MSP): 0 = No MRL sensor 1 = MRL Sensor is implemented on the chassis for this slot. 1 RO 0b Power Controller Present (PCP): 0 = No power controller 1 = A software programmable Power Controller is implemented for this slot/adapter (depending on form factor). 0 RO 0b Attention Button Present (ABP): 0 = No attention button 1 = An Attention Button for this slot is electrically controlled by the chassis. 6.1.42 SLOTCTL—Slot Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI B8–B9h 01C0h RO, RW 16 bits PCI Express Slot related registers allow for the support of Hot Plug. Bit 15:13 12 Access & Default RO 000b RO 0b Reserved Data Link Layer State Changed Enable (DLLSCE): If the Data Link Layer Link Active capability is implemented, when set to 1b, this field enables software notification when Data Link Layer Link Active field is changed. Electromechanical Interlock Control (EIC): If an Electromechanical Interlock is implemented, a write of 1b to this field causes the state of the interlock to toggle. A write of 0b to this field has no effect. A read to this register always returns a 0. Description 11 RO 0b 216 Datasheet PCI Express* Registers (D1:F0) Bit 10 Access & Default RO 0b Description Power Controller Control (PCC): If a Power Controller is implemented, this field when written sets the power state of the slot per the defined encodings. Reads of this field must reflect the value from the latest write, even if the corresponding hotplug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. Depending on the form factor, the power is turned on/off either to the slot or within the adapter. Note that in some cases the power controller may autonomously remove slot power or not respond to a power-up request based on a detected fault condition, independent of the Power Controller Control setting. The defined encodings are: 0 = Power On 1 = Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to 0b, then writes to this field have no effect and the read value of this field is undefined. 9:8 RO 01b Power Indicator Control (PIC): If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 00 = Reserved 01 = On 10 = Blink 11 = Off 7:6 RO 11b Attention Indicator Control (AIC): If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. If the indicator is electrically controlled by chassis, the indicator is controlled directly by the downstream port through implementation specific mechanisms. 00 = Reserved 01 = On 10 = Blink 11 = Off Datasheet 217 PCI Express* Registers (D1:F0) Bit 5 Access & Default RO 0b Description Hot-plug Interrupt Enable (HPIE): 0 = Disable 1 = Enables generation of an interrupt on enabled hot-plug events Default value of this field is 0b. If the Hot Plug Capable field in the Slot Capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b. 4 RO 0b Command Completed Interrupt Enable (CCI): If Command Completed notification is supported (as indicated by No Command Completed Support field of Slot Capabilities Register), when set to 1b, this bit enables software notification when a hot-plug command is completed by the Hot-Plug Controller. If Command Completed notification is not supported, this bit must be hardwired to 0b. 3 RW 0b Presence Detect Changed Enable (PDCE): 0 = Disable 1 = Enables software notification on a presence detect changed event. 2 RO 0b MRL Sensor Changed Enable (MSCE): If the MRL Sensor Present field in the Slot Capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b. 0 = Disable (default) 1 = Enables software notification on a MRL sensor changed event. 1 RO 0b Power Fault Detected Enable (PFDE): If Power Fault detection is not supported, this bit is permitted to be read-only with a value of 0b. 0 = Disable (default) 1 = Enables software notification on a power fault event. 0 RO 0b Attention Button Pressed Enable (ABPE): 0 = Disable (default) 1 = Enables software notification on an attention button pressed event. 218 Datasheet PCI Express* Registers (D1:F0) 6.1.43 SLOTSTS—Slot Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI BA–BBh 0000h RO, RWC 16 bits PCI Express Slot related registers allow for the support of Hot Plug. Bit 15:7 6 Access & Default RO 0000000b RO 0b Description Reserved and Zero: For future R/WC/S implementations; software must use 0 for writes to bits. Presence Detect State (PDS): This bit indicates the presence of an adapter in the slot, reflected by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined for the slot's corresponding form factor. Note that the in-band presence detect mechanism requires that power be applied to an adapter for its presence to be detected. Consequently, form factors that require a power controller for hotplug must implement a physical pin presence detect mechanism. 0 = Slot Empty 1 = Card Present in slot This register must be implemented on all Downstream Ports that implement slots. For Downstream Ports not connected to slots (where the Slot Implemented bit of the PCI Express Capabilities Register is 0b), this bit must return 1b. 5 4 RO 0b RO 0b Reserved Command Completed (CC): If Command Completed notification is supported (as indicated by No Command Completed Support field of Slot Capabilities Register), this bit is set when a hot-plug command has completed and the Hot-Plug Controller is ready to accept a subsequent command. The Command Completed status bit is set as an indication to host software that the Hot-Plug Controller has processed the previous command and is ready to receive the next command; it provides no assurance that the action corresponding to the command is complete. If Command Completed notification is not supported, this bit must be hardwired to 0b. 3 2 RWC 0b RO 0b Detect Changed (PDC): This bit is set when the value reported in Presence Detect State is changed. MRL Sensor Changed (MSC): If an MRL sensor is implemented, this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be set. Datasheet 219 PCI Express* Registers (D1:F0) Bit 1 Access & Default RO 0b Description Power Fault Detected (PFD): If a Power Controller that supports power fault detection is implemented, this bit is set when the Power Controller detects a power fault at this slot. Note that, depending on hardware capability, it is possible that a power fault can be detected at any time, independent of the Power Controller Control setting or the occupancy of the slot. If power fault detection is not supported, this bit must not be set. Attention Button Pressed (ABP): If an Attention Button is implemented, this bit is set when the attention button is pressed. If an Attention Button is not supported, this bit must not be set. 0 RO 0b 6.1.44 RCTL—Root Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI BC–BDh 0000h RO, RW 16 bits This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link. Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register. Bit 15:4 3 Access & Default RO 000h RW 0b Reserved PME Interrupt Enable (PMEIE): 0 = No interrupts are generated as a result of receiving PME messages. 1 = Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register. A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state. 2 RW 0b System Error on Fatal Error Enable (SEFEE): This bit controls the Root Complex's response to fatal errors. 0 = No SERR generated on receipt of fatal error. 1 = SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. Description 220 Datasheet PCI Express* Registers (D1:F0) Bit 1 Access & Default RW 0b Description System Error on Non-Fatal Uncorrectable Error Enable (SENFUEE): This bit controls the Root Complex's response to nonfatal errors. 0 = No SERR generated on receipt of non-fatal error. 1 = SERR should be generated if a non-fatal error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. 0 RW 0b System Error on Correctable Error Enable (SECEE): This bit controls the Root Complex's response to correctable errors. 0 = No SERR generated on receipt of correctable error. 1 = SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. 6.1.45 RSTS—Root Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI C0–C3h 00000000h RO, RWC 32 bits This register provides information about PCI Express Root Complex specific parameters. Bit 31:18 17 Access & Default RO 0000h RO 0b Reserved PME Pending (PMEP): 1 = Another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately. The PME pending bit is cleared by hardware if no more PMEs are pending. PME Status (PMES): 1 = PME was asserted by the requestor ID indicated in the PME Requestor ID field. Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field. PME Requestor ID (PMERID): This field indicates the PCI requestor ID of the last PME requestor. Description 16 RWC 0b 15:0 RO 0000h Datasheet 221 PCI Express* Registers (D1:F0) 6.1.46 PEGLC—PCI Express*-G Legacy Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI EC–EFh 00000000h RW, RO 32 bits This register controls functionality that is needed by Legacy (non-PCI Express aware) operating systems during run time. Bit 31:3 2 Access & Default RO 00000000h RW 0b Reserved PME GPE Enable (PMEGPE): 0 = Do not generate GPE PME message when PME is received. 1 = Generate a GPE PME message when PME is received (Assert_PMEGPE and Deassert_PMEGPE messages on DMI). This enables the (G)MCH to support PMEs on the PEG port under legacy operating systems. 1 RW 0b Hot-Plug GPE Enable (HPGPE): 0 = Do not generate GPE Hot-Plug message when Hot-Plug event is received. 1 = Generate a GPE Hot-Plug message when Hot-Plug Event is received (Assert_HPGPE and Deassert_HPGPE messages on DMI). This enables the (G)MCH to support Hot-Plug on the PEG port under legacy operating systems. 0 RW 0b General Message GPE Enable (GENGPE): 0 = Do not forward received GPE assert/de-assert messages. 1 = Forward received GPE assert/de-assert messages. These general GPE message can be received via the PEG port from an external Intel device (i.e., PxH) and will be subsequently forwarded to the ICH (via Assert_GPE and Deassert_GPE messages on DMI). For example, PxH might send this message if a PCI Express device is hot plugged into a PxH downstream port. Description 222 Datasheet PCI Express* Registers (D1:F0) 6.1.47 VCECH—Virtual Channel Enhanced Capability Header B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 100–103h 14010002h RO 32 bits This register indicates PCI Express device Virtual Channel capabilities. Extended capability structures for PCI Express devices are located in PCI Express extended configuration space and have different field definitions than standard PCI capability structures. Bit 31:20 19:16 Access & Default RO 140h RO 1h RO 0002h Description Pointer to Next Capability (PNC): The Link Declaration Capability is the next in the PCI Express extended capabilities list. PCI Express Virtual Channel Capability Version (PCI EXPRESS*VCCV): Hardwired to 1 to indicate compliances with the 1.1 version of the PCI Express specification. Extended Capability ID (ECID): Value of 0002 h identifies this linked list item (capability structure) as being for PCI Express Virtual Channel registers. 15:0 6.1.48 PVCCAP1—Port VC Capability Register 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 104–107h 00000000h RO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit 31:7 6:4 Access & Default RO 0000000h RO 000b Reserved Low Priority Extended VC Count (LPEVCC): This field indicates the number of (extended) Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group that has the lowest priority with respect to other VC resources in a strict-priority VC Arbitration. The value of 0 in this field implies strict VC arbitration. 3 2:0 RO 0b RO 000b Reserved Extended VC Count (EVCC): This field indicates the number of (extended) Virtual Channels in addition to the default VC supported by the device. Description Datasheet 223 PCI Express* Registers (D1:F0) 6.1.49 PVCCAP2—Port VC Capability Register 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 108–10Bh 00000000h RO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit 31:24 Access & Default RO 00h Description VC Arbitration Table Offset (VCATO): This field indicates the location of the VC Arbitration Table. This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the base address of the Virtual Channel Capability Structure. A value of 0 indicates that the table is not present (due to fixed VC priority). Reserved Reserved 23:8 7:0 RO 0000h RO 00h 6.1.50 PVCCTL—Port VC Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 10C–10Dh 0000h RO, RW 16 bits Bit 15:4 3:1 Access & Default RO 000h RW 000b Reserved Description VC Arbitration Select (VCAS): This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. Since there is no other VC supported than the default, this field is reserved. Reserved 0 RO 0b 224 Datasheet PCI Express* Registers (D1:F0) 6.1.51 VC0RCAP—VC0 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 110–113h 00000000h RO 32 bits Bit 31:16 15 Access & Default RO 0000h RO 0b Reserved Description Reject Snoop Transactions (RSNPT): 0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1 = Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request. 14:0 RO 0000h Reserved Datasheet 225 PCI Express* Registers (D1:F0) 6.1.52 VC0RCTL—VC0 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 114–117h 800000FFh RO, RW 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit Access & Default RO 1b RO 0h RO 000b RO 0000h RW 7Fh Description 31 30:27 26:24 23:8 7:1 VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only as VC0 can never be disabled. Reserved VC0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0, this is hardwired to 0 and read only. Reserved TC/VC0 Map (TCVC0M): This field indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. TC0/VC0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0. 0 RO 1b 226 Datasheet PCI Express* Registers (D1:F0) 6.1.53 VC0RSTS—VC0 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 11A–11Bh 0002h RO 16 bits This register reports the Virtual Channel specific status. Bit 15:2 1 Access & Default RO 0000h RO 1b Reserved VC0 Negotiation Pending (VC0NP): 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization. It is set by default on Reset, as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state. It is cleared when the link successfully exits the FC_INIT2 state. Before using a Virtual Channel, software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link. 0 RO 0b Reserved Description Datasheet 227 PCI Express* Registers (D1:F0) 6.1.54 RCLDECH—Root Complex Link Declaration Enhanced B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 140–143h 00010005h RO 32 bits This capability declares links from this element (PEG) to other elements of the root complex component to which it belongs. See PCI Express specification for link/topology declaration requirements. Bit 31:20 19:16 Access & Default RO 000h RO 1h RO 0005h Description Pointer to Next Capability (PNC): This is the last capability in the PCI Express extended capabilities list Link Declaration Capability Version (LDCV): Hardwired to 1 to indicate compliances with the 1.1 version of the PCI Express specification. Extended Capability ID (ECID): Value of 0005h identifies this linked list item (capability structure) as being for PCI Express Link Declaration Capability. 15:0 6.1.55 ESD—Element Self Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 144–147h 02000100h RO, RWO 32 bits This register provides information about the root complex element containing this Link Declaration Capability. Bit 31:24 Access & Default RO 02h Description Port Number (PN): This field specifies the port number associated with this element with respect to the component that contains this element. This port number value is utilized by the Express port of the component to provide arbitration to this Root Complex Element. Component ID (CID): This field identifies the physical component that contains this Root Complex Element. Number of Link Entries (NLE): This field indicates the number of link entries following the Element Self Description. This field reports 1 (to Express port only as we don't report any peer-to-peer capabilities in our topology). Reserved Element Type (ET): This field indicates the type of the Root Complex Element. Value of 0h represents a root port. 23:16 15:8 RWO 00h RO 01h 7:4 3:0 RO 0h RO 0h 228 Datasheet PCI Express* Registers (D1:F0) 6.1.56 LE1D—Link Entry 1 Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 150–153h 00000000h RO, RWO 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element. Bit 31:24 Access & Default RO 00h Description Target Port Number (TPN): This field specifies the port number associated with the element targeted by this link entry (Express Port). The target port number is with respect to the component that contains this element as specified by the target component ID. Target Component ID (TCID): This field identifies the physical or logical component that is targeted by this link entry. Reserved Link Type (LTYP): This field indicates that the link points to memorymapped space (for RCRB). The link address specifies the 64-bit base address of the target RCRB. Link Valid (LV): 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link. 23:16 15:2 1 RWO 00h RO 0000h RO 0b RWO 0b 0 6.1.57 LE1A—Link Entry 1 Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 158–15Fh 0000000000000000h RO, RWO 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element. Bit 63:32 31:12 Access & Default RO 00000000h RWO 00000h RO 000h Reserved Link Address (LA): This field contains the memory-mapped base address of the RCRB that is the target element (Express Port) for this link entry. Reserved Description 11:0 Datasheet 229 PCI Express* Registers (D1:F0) 6.1.58 PEGSSTS—PCI Express*-G Sequence Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 218–21Fh 0000000000000FFFh RO 64 bits This register provides PCI Express status reporting that is required by the PCI Express specification. Bit 63:60 59:48 Access & Default RO 0h RO 000h Reserved Next Transmit Sequence Number (NTSN): This field indicates the value of the NXT_TRANS_SEQ counter. This counter represents the transmit Sequence number to be applied to the next TLP to be transmitted onto the Link for the first time. Reserved Next Packet Sequence Number (NPSN): This field indicates the packet sequence number to be applied to the next TLP to be transmitted or re-transmitted onto the Link. Reserved Next Receive Sequence Number (NRSN): This field is the sequence number associated with the TLP that is expected to be received next. Reserved Last Acknowledged Sequence Number (LASN): This field is the sequence number associated with the last acknowledged TLP. Description 47:44 43:32 RO 0h RO 000h RO 0h RO 000h RO 0h RO FFFh 31:28 27:16 15:12 11:0 § 230 Datasheet PCI Express* Registers (D1:F0) Datasheet 231 Direct Memory Interface (DMI) Registers 7 Direct Memory Interface (DMI) Registers This Root Complex Register Block (RCRB) controls the (G)MCH-ICH9 serial interconnect. The base address of this space is programmed in DMIBAR in D0:F0 configuration space. Table 7-1 provides an address map of the DMI registers listed by address offset in ascending order. Section 7.1 provides register bit descriptions. Table 7-1. DMI Register Address Map Address Offset 00–03h 04–07h 08–0Bh 0C–0Dh 10–13h 14–17h 1A–1Bh 1C–1Fh 20–23h 26–27h 84–87h 88–89h 8A–8Bh Register Symbol DMIVCECH DMIPVCCAP1 DMIPVCCAP2 DMIPVCCTL DMIVC0RCAP DMIVC0RCTL0 DMIVC0RSTS DMIVC1RCAP DMIVC1RCTL1 DMIVC1RSTS DMILCAP DMILCTL DMILSTS Register Name DMI Virtual Channel Enhanced Capability DMI Port VC Capability Register 1 DMI Port VC Capability Register 2 DMI Port VC Control DMI VC0 Resource Capability DMI VC0 Resource Control DMI VC0 Resource Status DMI VC1 Resource Capability DMI VC1 Resource Control DMI VC1 Resource Status DMI Link Capabilities DMI Link Control DMI Link Status Default Value 04010002h 00000001h 00000000h 0000h 00000001h 800000FFh 0002h 00008001h 01000000h 0002h 00012C41h 0000h 0001h Access RO RWO, RO RO RO, RW RO RO, RW RO RO RW, RO RO RO, RWO RW, RO RO 232 Datasheet Direct Memory Interface (DMI) Registers 7.1 Direct Memory Interface (DMI) Configuration Register Details DMIVCECH—DMI Virtual Channel Enhanced Capability B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 00–03h 04010002h RO 32 bits 7.1.1 This register indicates DMI Virtual Channel capabilities. Bit 31:20 Access & Default RO 040h RO 1h RO 0002h Description Pointer to Next Capability (PNC): This field contains the offset to the next PCI Express capability structure in the linked list of capabilities (Link Declaration Capability). PCI Express* Virtual Channel Capability Version (PCI EXPRESS*VCCV): Hardwired to 1 to indicate compliances with the 1.1 version of the PCI Express specification. Extended Capability ID (ECID): Value of 0002h identifies this linked list item (capability structure) as being for PCI Express Virtual Channel registers. 19:16 15:0 Datasheet 233 Direct Memory Interface (DMI) Registers 7.1.2 DMIPVCCAP1—DMI Port VC Capability Register 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 04–07h 00000001h RWO, RO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit 31:7 Access & Default RO 0000000h RO 000b Reserved Description 6:4 Low Priority Extended VC Count (LPEVCC): This field indicates the number of (extended) Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group that has the lowest priority with respect to other VC resources in a strict-priority VC Arbitration. The value of 0 in this field implies strict VC arbitration. 3 2:0 RO 0b RWO 001b Reserved Extended VC Count (EVCC): This field indicates the number of (extended) Virtual Channels in addition to the default VC supported by the device. The Private Virtual Channel is not included in this count. 7.1.3 DMIPVCCAP2—DMI Port VC Capability Register 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 08–0Bh 00000000h RO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit 31:0 Access & Default RO 00000000h Reserved Description 234 Datasheet Direct Memory Interface (DMI) Registers 7.1.4 DMIPVCCTL—DMI Port VC Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 0C–0Dh 0000h RO, RW 16 bits Bit 15:4 3:1 Access & Default RO 000h RW 000b Reserved Description VC Arbitration Select (VCAS): This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. See the PCI express specification for more details. 0 RO 0b Reserved 7.1.5 DMIVC0RCAP—DMI VC0 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 10–13h 00000001h RO 32 bits Bit 31:16 15 Access & Default RO 00000h RO 0b Reserved Description Reject Snoop Transactions (REJSNPT): 0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1 = Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request. 14:8 7:0 RO 00h RO 01h Reserved Port Arbitration Capability (PAC): Having only bit 0 set indicates that the only supported arbitration scheme for this VC is nonconfigurable hardware-fixed. Datasheet 235 Direct Memory Interface (DMI) Registers 7.1.6 DMIVC0RCTL0—DMI VC0 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 14–17h 800000FFh RO, RW 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit 31 30:27 26:24 23:20 19:17 Access & Default RO 1b RO 0h RO 000b RO 0h RW 000b Description Virtual Channel 0 Enable (VC0E): For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. Reserved Virtual Channel 0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read only. Reserved Port Arbitration Select (PAS): This field configures the VC resource to provide a particular Port Arbitration service. Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource. Because only bit 0 of that field is asserted. This field will always be programmed to '1'. 16:8 7:1 RO 000h RW 7Fh Reserved Traffic Class / Virtual Channel 0 Map (TCVC0M): This field indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. 0 RO 1b Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0. 236 Datasheet Direct Memory Interface (DMI) Registers 7.1.7 DMIVC0RSTS—DMI VC0 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 1A–1Bh 0002h RO 16 bits This register reports the Virtual Channel specific status. Bit 15:2 1 Access & Default RO 0000h RO 1b Reserved. Virtual Channel 0 Negotiation Pending (VC0NP): This bit indicates the status of the process of Flow Control initialization. It is set by default on Reset, as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state. It is cleared when the link successfully exits the FC_INIT2 state. 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). BIOS Requirement: Before using a Virtual Channel, software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link. 0 RO 0b Reserved Description 7.1.8 DMIVC1RCAP—DMI VC1 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: Size: Bit 31:16 15 Access & Default RO 00000h RO 1b Reserved Reject Snoop Transactions (REJSNPT): 0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1 = Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request. 14:8 7:0 RO 00h RO 01h Reserved Port Arbitration Capability (PAC): Having only bit 0 set indicates that the only supported arbitration scheme for this VC is nonconfigurable hardware-fixed. 0/0/0/DMIBAR 1C–1Fh 00008001h RO 32 bits Description Datasheet 237 Direct Memory Interface (DMI) Registers 7.1.9 DMIVC1RCTL1—DMI VC1 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 20–23h 01000000h RW, RO 32 bits This register controls the resources associated with PCI Express Virtual Channel 1. Bit 31 Access & Default RW 0b Description Virtual Channel 1 Enable (VC1E): 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. 30:27 26:24 RO 0h RW 001b RO 0h RW 000b Reserved Virtual Channel 1 ID (VC1ID): This field assigns a VC ID to the VC resource. Assigned value must be non-zero. This field can not be modified when the VC is already enabled. Reserved Port Arbitration Select (PAS): This field configures the VC resource to provide a particular Port Arbitration service. Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource. Reserved Traffic Class / Virtual Channel 1 Map (TCVC1M): This field indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. 0 RO 0b Traffic Class 0 / Virtual Channel 1 Map (TC0VC1M): Traffic Class 0 is always routed to VC0. 23:20 19:17 16:8 7:1 RO 000h RW 00h 238 Datasheet Direct Memory Interface (DMI) Registers 7.1.10 DMIVC1RSTS—DMI VC1 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 26–27h 0002h RO 16 bits This register reports the Virtual Channel specific status. Bit 15:2 1 Access & Default RO 0000h RO 1b Reserved Virtual Channel 1 Negotiation Pending (VC1NP): 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). 0 RO 0b Reserved Description 7.1.11 DMILCAP—DMI Link Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 84–87h 00012C41h RO, RWO 32 bits This register indicates DMI specific capabilities. Bit 31:18 17:15 Access & Default RO 0000h RWO 010b RWO 010b RO 11b RO 04h RO 1h Reserved L1 Exit Latency (L1SELAT): This field indicates the length of time this Port requires to complete the transition from L1 to L0. 010b = 2 us to less than 4 us. 14:12 L0s Exit Latency (L0SELAT): This field indicates the length of time this Port requires to complete the transition from L0s to L0. 010 = 128 ns to less than 256 ns 11:10 9:4 3:0 Active State Link PM Support (ASLPMS): L0s & L1 entry supported. Max Link Width (MLW): This field indicates the maximum number of lanes supported for this link. Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s. Description Datasheet 239 Direct Memory Interface (DMI) Registers 7.1.12 DMILCTL—DMI Link Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register allows control of DMI. Bit 15:8 7 Access & Default RO 00h RW 0b Reserved Extended Synch (EXTSYNC): 0 = Standard Fast Training Sequence (FTS). 1 = Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state. 6:3 2 1:0 RO 0h RW 0b RW 00b Reserved Far-End Digital Loopback (FEDLB): Active State Power Management Support (ASPMS): This field controls the level of active state power management supported on the given link. 00 = Disabled 01 = L0s Entry Supported 10 = Reserved 11 = L0s and L1 Entry Supported Description 0/0/0/DMIBAR 88–89h 0000h RW, RO 16 bits 240 Datasheet Direct Memory Interface (DMI) Registers 7.1.13 DMILSTS—DMI Link Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register indicates DMI status. Bit 15:10 9:4 Access & Default RO 00h RO 00h Description Reserved and Zero for future R/WC/S implementations. Software must use 0 for writes to these bits. Negotiated Width (NWID): This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). 04h = X4 All other encodings are reserved. 3:0 RO 1h Negotiated Speed (NSPD): This field indicates negotiated link speed. 1h = 2.5 Gb/s All other encodings are reserved. 0/0/0/DMIBAR 8A–8Bh 0001h RO 16 bits § Datasheet 241 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) The Integrated Graphics Device (IGD) registers are located in Device 2 (D0), Function 0 (F0) and Function 1 (F1). This chapter provides the descriptions for these registers. Section 8.1 provides the register descriptions for Device 2, Function 0. Section 8.2 provides the register descriptions for Device 2, Function 1. 8.1 Integrated Graphics Register Details (D2:F0) Device 2, Function 0 contains registers for the internal graphics functions. Table 8-1 lists the PCI configuration registers in order of ascending offset address. Function 0 can be VGA compatible or not, this is selected through bit 1 of GGC register (Device 0, offset 52h). Note: The following sections describe Device 2 PCI configuration registers only. Table 8-1. Integrated Graphics Device Register Address Map (D2:F0) Address Offset 00–01h 02–03h 04–05h 06–07h 08h 09–0Bh 0Ch 0Dh 0Eh 10–13h 2C–2Dh 2E–2Fh Register Symbol VID2 DID PCICMD2 PCISTS2 RID2 CC CLS MLT2 HDR2 MMADR SVID2 SID2 Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Cache Line Size Master Latency Timer Header Type Memory Mapped Range Address Subsystem Vendor Identification Subsystem Identification Default Value 8086h 29C2h 0000h 0090h 00h 030000h 00h 00h 80h 00000000h 0000h 0000h Access RO RO RO, RW RO RO RO RO RO RO RO, RW RWO RWO 242 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Address Offset 30–33h 34h 3Eh 3Fh 40–50h Register Symbol ROMADR CAPPOINT MINGNT MAXLAT CAPID0 Register Name Video BIOS ROM Base Address Capabilities Pointer Minimum Grant Maximum Latency Capability Identifier Default Value 00000000h 90h 00h 00h 000000000 000000001 000000000 10B0009h 0030h 000003DBh 00000000h 07800000h 0000h 00h 0001h 0022h 0000h 0000h 00000000h 00000000h Access RO RO RO RO RO 52–53h 54–57h 58–5Bh 5C–5Fh 60–61h C0h D0–D1h D2–D3h D4–D5h E0–E1h E4–E7h FC–FFh MGGC DEVEN SSRW BSM HSRW GDRST PMCAPID PMCAP PMCS SWSMI ASLE ASLS GMCH Graphics Control Register Device Enable Software Scratch Read Write Base of Stolen Memory Hardware Scratch Read Write Graphics Debug Reset Power Management Capabilities ID Power Management Capabilities Power Management Control/Status Software SMI System Display Event Register ASL Storage RO RO RW RO RW RO, RW/L RWO, RO RO RO, RW RW RW RW 8.1.1 VID2—Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 00–01h 8086h RO 16 bits This register combined with the Device Identification register uniquely identifies any PCI device. Bit 15:0 Access & Default RO 8086h Description Vendor Identification Number (VID): PCI standard identification for Intel. Datasheet 243 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.2 DID—Device Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 02–03h 29C2h RO 16 bits This register combined with the Vendor Identification register uniquely identifies any PCI device. Bit 15:0 Access & Default RO 29C2h Description Device Identification Number (DID): This is a 16 bit value assigned to the GMCH Graphic device. 8.1.3 PCICMD2—PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 04–05h 0000h RO, RW 16 bits This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory. Bit 15:11 10 Access & Default RO 00h RW 0b Reserved Interrupt Disable (INTDIS): This bit disables the device from asserting INTx#. 0 = Enable the assertion of this device's INTx# signal. 1 = Disable the assertion of this device's INTx# signal. DO_INTx messages will not be sent to DMI. 9 8 7 6 RO 0b RO 0b RO 0b RO 0b Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0. SERR Enable (SERRE): Not Implemented. Hardwired to 0. Address/Data Stepping Enable (ADSTEP): Not Implemented. Hardwired to 0. Parity Error Enable (PERRE): Not Implemented. Hardwired to 0. Since the IGD belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the IGD ignores any parity error that it detects and continues with normal operation. Description 244 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Bit 5 4 3 2 Access & Default RO 0b RO 0b RO 0b RW 0b Description Video Palette Snooping (VPS): This bit is hardwired to 0 to disable snooping. Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does not support memory write and invalidate commands. Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD ignores Special cycles. Bus Master Enable (BME): This bit controls the IGD's response to bus master accesses. 0 = Disable IGD bus mastering. 1 = Enable the IGD to function as a PCI compliant master. 1 RW 0b Memory Access Enable (MAE): This bit controls the IGD's response to memory space accesses. 0 = Disable. 1 = Enable. 0 RW 0b I/O Access Enable (IOAE): This bit controls the IGD's response to I/O space accesses. 0 = Disable. 1 = Enable. Datasheet 245 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.4 PCISTS2—PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 06–07h 0090h RO 16 bits PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD. Bit 15 14 13 12 11 10:9 8 Access & Default RO 0b RO 0b RO 0b RO 0b RO 0b RO 00b RO 0b RO 1b RO 0b RO 0b RO 1b Description Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always hardwired to 0. Signaled System Error (SSE): The IGD never asserts SERR#, therefore this bit is hardwired to 0. Received Master Abort Status (RMAS): The IGD never gets a Master Abort, therefore this bit is hardwired to 0. Received Target Abort Status (RTAS): The IGD never gets a Target Abort, therefore this bit is hardwired to 0. Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use target abort semantics. DEVSEL Timing (DEVT): N/A. These bits are hardwired to "00". Master Data Parity Error Detected (DPD): Since Parity Error Response is hardwired to disabled (and the IGD does not do any parity detection), this bit is hardwired to 0. Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back when the transactions are not to the same agent. User Defined Format (UDF): Hardwired to 0. 66 MHz PCI Capable (66C): N/A - Hardwired to 0. Capability List (CLIST): This bit is set to 1 to indicate that the register at 34h provides an offset into the function's PCI Configuration Space containing a pointer to the location of the first item in the list. Interrupt Status (INTSTS): This bit reflects the state of the interrupt in the device. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, will the devices INTx# signal be asserted. Reserved 7 6 5 4 3 RO 0b 2:0 RO 000b 246 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.5 RID2—Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 08h 00h RO 8 bits This register contains the revision number for Device #2 Functions 0 and 1. Bit 7:0 Access & Default RO 00h Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH Device 2. Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 8.1.6 CC—Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 09–0Bh 030000h RO 24 bits This register contains the device programming interface information related to the Sub-Class Code and Base Class Code definition for the IGD. This register also contains the Base Class Code and the function sub-class in relation to the Base Class Code. Bit 23:16 Access & Default RO 03h RO 00h Description Base Class Code (BCC): This is an 8-bit value that indicates the base class code for the GMCH. This code has the value 03h, indicating a Display Controller. Sub-Class Code (SUBCC): Value will be determined based on Device 0 GGC register, GMS and IVD fields. 00h = VGA compatible 80h = Non VGA (GMS = "0000" or IVD = "1") 7:0 RO 00h Programming Interface (PI): 00h = Hardwired as a Display controller. 15:8 Datasheet 247 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.7 CLS—Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 0Ch 00h RO 8 bits The IGD does not support this register as a PCI slave. Bit 7:0 Access & Default RO 00h Description Cache Line Size (CLS): This field is hardwired to 0s. The IGD as a PCI compliant master does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size. 8.1.8 MLT2—Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 0Dh 00h RO 8 bits The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit 7:0 Access & Default RO 00h Description Master Latency Timer Count Value (MLTCV): Hardwired to 0s. 248 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.9 HDR2—Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 0Eh 80h RO 8 bits This register contains the Header Type of the IGD. Bit 7 Access & Default RO 1b Description Multi Function Status (MFUNC): Indicates if the device is a MultiFunction Device. The Value of this register is determined by Device #0, offset 54h, DEVEN[4]. If Device 0 DEVEN[4] is set, the MFUNC bit is also set. Header Code (H): This is a 7-bit value that indicates the Header Code for the IGD. This code has the value 00h, indicating a type 0 configuration space format. 6:0 RO 00h 8.1.10 GMADR—Graphics Memory Range Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 18–1Bh 00000008h RW, RO, RW/L 32 bits IGD graphics memory base address is specified in this register. Bit 31:29 28 Access & Default RW 000b RW/L 0b Description Memory Base Address (MBA): Set by the OS, these bits correspond to address signals 31:29. 512MB Address Mask (512ADMSK): This Bit is either part of the Memory Base Address (R/W) or part of the Address Mask (RO), depending on the value of MSAC[1:0]. See MSAC (D2:F0, offset 62h) for details. 256 MB Address Mask (256ADMSK): This bit is either part of the Memory Base Address (R/W) or part of the Address Mask (RO), depending on the value of MSAC[1:0]. See MSAC (D2:F0, offset 62h) for details. Address Mask (ADM): Hardwired to 0s to indicate at least 128 MB address range. Prefetchable Memory (PREFMEM): Hardwired to 1 to enable prefetching. Memory Type (MEMTYP): Hardwired to 0 to indicate 32-bit address. Memory/IO Space (MIOS): Hardwired to 0 to indicate memory space. 27 RW/L 0b 26:4 3 2:1 0 RO 000000h RO 1b RO 00b RO 0b Datasheet 249 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.11 IOBAR—I/O Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 14–17h 00000001h RO, RW 32 bits This register provides the Base offset of the I/O registers within Device 2. Bits 15:3 are programmable allowing the I/O Base to be located anywhere in 16 bit I/O Address Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8 bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1–D3 or if I/O Enable is clear or if Device 2 is turned off or if Internal graphics is disabled thru the fuse or fuse override mechanisms. Note that access to this IO BAR is independent of VGA functionality within Device 2. Also note that this mechanism is available only through function 0 of Device 2 and is not duplicated in function 1. If accesses to this IO bar is allowed then the GMCH claims all 8, 16 or 32 bit I/O cycles from the processor that falls within the 8B claimed. Bit 31:16 15:3 2:1 0 Access & Default RO 0000h RW 0000h RO 00b RO 1b Reserved IO Base Address (IOBASE): Set by the OS, these bits correspond to address signals 15:3. Memory Type (MEMTYPE): Hardwired to 0s to indicate 32-bit address. Memory/IO Space (MIOS): Hardwired to 1 to indicate I/O space. Description 8.1.12 SVID2—Subsystem Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 2C–2Dh 0000h RWO 16 bits Bit 15:0 Access & Default RWO 0000h Description Subsystem Vendor ID (SUBVID): This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a Reset. 250 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.13 SID2—Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 2E–2Fh 0000h RWO 16 bits Bit 15:0 Access & Default RWO 0000h Description Subsystem Identification (SUBID): This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a Reset. 8.1.14 ROMADR—Video BIOS ROM Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 30–33h 00000000h RO 32 bits The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s. Bit 31:18 17:11 10:1 0 Access & Default RO 0000h RO 00h RO 000h RO 0b Description ROM Base Address (RBA): Hardwired to 0s. Address Mask (ADMSK): Hardwired to 0s to indicate 256 KB address range. Reserved. Hardwired to 0s. ROM BIOS Enable (RBE): 0 = ROM not accessible. Datasheet 251 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.15 CAPPOINT—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 34h 90h RO 8 bits Bit 7:0 Access & Default RO 90h Description Capabilities Pointer Value (CPV): This field contains an offset into the function's PCI Configuration Space for the first item in the New Capabilities Linked List, the MSI Capabilities ID registers at address 90h or the Power Management capability at D0h. This value is determined by the configuration in CAPL[0]. 8.1.16 INTRLINE—Interrupt Line B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 3Ch 00h RW 8 bits Bit 7:0 Access & Default RW 00h Description Interrupt Connection (INTCON): This field is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates to which input of the system interrupt controller the device's interrupt pin is connected. 8.1.17 INTRPIN—Interrupt Pin B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 3Dh 01h RO 8 bits Bit 7:0 Access & Default RO 01h Description Interrupt Pin (INTPIN): As a single function device, the IGD specifies INTA# as its interrupt pin. 01h = INTA#. 252 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.18 MINGNT—Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 3Eh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Minimum Grant Value (MGV): The IGD does not burst as a PCI compliant master. 8.1.19 MAXLAT—Maximum Latency B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 3Fh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Maximum Latency Value (MLV): The IGD has no specific requirements for how often it needs to access the PCI bus. Datasheet 253 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.20 CAPID0—Capability Identifier B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/2/0/PCI 40–50h 00000000000000000100000000010B0009h RO 136 bits 000000000000h This register control of bits in this register are only required for customer visible SKU differentiation. Bit 135:28 27:24 23:16 15:8 7:0 Access & Default RO 0s RO 1h RO 0bh RO 00h RO 09h Reserved CAPID Version (CAPIDV): This field has the value 0001b to identify the first revision of the CAPID register definition. CAPID Length (CAPIDL): This field has the value 0bh to indicate the structure length (11 bytes). Next Capability Pointer (NCP): This field is hardwired to 00h indicating the end of the capabilities linked list. Capability Identifier (CAP_ID): This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. Description 254 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.21 MGGC—GMCH Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 52–53h 0030h RO 16 bits All the Bits in this register are Intel® TXT lockable. Bit 15:10 9:8 Access & Default RO 00h RO 0h Reserved GTT Graphics Memory Size (GGMS): This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is preallocated only when Internal graphics is enabled. 00 = No memory pre-allocated. GTT cycles (Memory and I/O) are not claimed. 01 = No VT mode, 1 MB of memory pre-allocated for GTT. 10 = VT mode, 2 MB of memory pre-allocated for GTT. 11 = Reserved Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. Description Datasheet 255 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Bit 7:4 Access & Default RO 0011b Description Graphics Mode Select (GMS): This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled. 0000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and the Sub-Class Code field within Device 2 function 0 Class Code register is 80. 0001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame buffer. 0010 = DVMT (UMA) mode, 4 MB of memory pre-allocated for frame buffer. 0011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame buffer. 0100 = DVMT (UMA) mode, 16 MB of memory pre-allocated for frame buffer. 0101 = DVMT (UMA) mode, 32 MB of memory pre-allocated for frame buffer. 0110 = DVMT (UMA) mode, 48 MB of memory pre-allocated for frame buffer. 0111 = DVMT (UMA) mode, 64 MB of memory pre-allocated for frame buffer. 1000 = DVMT (UMA) mode, 128 MB of memory pre-allocated for frame buffer. 1001 = DVMT (UMA) mode, 256 MB of memory pre-allocated for frame buffer. Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. BIOS Requirement: BIOS must not set this field to 000 if IVD (bit 1 of this register) is 0. 3:0 RO 0000b Reserved 256 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.22 DEVEN—Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 54–57h 000003DBh RO 32 bits This register allows for enabling/disabling of PCI devices and functions that are within the GMCH. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel® TXT Lockable. Bit 31:15 14 Access & Default RO 00000h RO 0b Reserved Chap Enable (D7EN): 0 = Bus 0, Device 7 is disabled and not visible. 1 = Bus 0, Device 7 is enabled and visible. Non-production BIOS code should provide a setup option to enable Bus 0, Device 7. When enabled, Bus 0, Device 7 must be initialized in accordance to standard PCI device initialization procedures. 13:10 9 RO 0b RO 1b Reserved EP Function 3 (D3F3EN): 0 = Bus 0, Device 3, Function 3 is disabled and hidden 1 = Bus 0, Device 3, Function 3 is enabled and visible If Device 3, Function 0 is disabled and hidden, then Device 3, Function 3 is also disabled and hidden independent of the state of this bit. 8 RO 1b EP Function 2 (D3F2EN): 0 = Bus 0, Device 3, Function 2 is disabled and hidden 1 = Bus 0, Device 3, Function 2 is enabled and visible If Device 3, Function 0 is disabled and hidden, then Device 3, Function 2 is also disabled and hidden independent of the state of this bit. 7 RO 1b EP Function 1 (D3F1EN): 0 = Bus 0, Device 3, Function 1 is disabled and hidden 1 = Bus 0, Device 3, Function 1 is enabled and visible. If this GMCH does not have ME capability (CAPID0[??] = 1), then Device 3, Function 1 is disabled and hidden independent of the state of this bit. Description Datasheet 257 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Bit 6 Access & Default RO 1b EP Function 0 (D3F0EN): Description 0 = Bus 0, Device 3, Function 0 is disabled and hidden 1 = Bus 0, Device 3, Function 0 is enabled and visible. If this GMCH does not have ME capability (CAPID0[??] = 1), then Device 3, Function 0 is disabled and hidden independent of the state of this bit. 5 4 RO 0b RO 1b Reserved Internal Graphics Engine Function 1 (D2F1EN): 0 = Bus 0, Device 2, Function 1 is disabled and hidden 1 = Bus 0, Device 2, Function 1 is enabled and visible If Device 2, Function 0 is disabled and hidden, then Device 2, Function 1 is also disabled and hidden independent of the state of this bit. If this component is not capable of Dual Independent Display (CAPID0[78] = 1), then this bit is hardwired to 0b to hide Device 2, Function 1. 3 RO 1b Internal Graphics Engine Function 0 (D2F0EN): 0 = Bus 0, Device 2, Function 0 is disabled and hidden 1 = Bus 0, Device 2, Function 0 is enabled and visible If this GMCH does not have internal graphics capability (CAPID0[46] = 1), then Device 2, Function 0 is disabled and hidden independent of the state of this bit. 2 1 RO 0b RO 1b Reserved PCI Express Port (D1EN): 0 = Bus 0, Device 1, Function 0 is disabled and hidden. 1 = Bus 0, Device 1, Function 0 is enabled and visible. Default value is determined by the device capabilities (see CAPID0 [44]), SDVO Presence hardware strap and the SDVO/PCIe Concurrent hardware strap. Device 1 is Disabled on Reset if the SDVO Presence strap was sampled high, and the SDVO/PCIe Concurrent strap was sampled low at the last assertion of PWROK, and is enabled by default otherwise. 0 RO 1b Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be disabled and is therefore hardwired to 1. 258 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.23 SSRW—Software Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit 31:0 Access & Default RW 00000000h Reserved 0/2/0/PCI 58–5Bh 00000000h RW 32 bits Description 8.1.24 BSM—Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 5C–5Fh 07800000h RO 32 bits Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the top of low used DRAM, GMCH claims 1 to 64 MBs of DRAM for internal graphics if enabled. The base of stolen memory will always be below 4 GB. This is required to prevent aliasing between stolen range and the reclaim region. Bit 31:20 Access & Default RO 078h Description Base of Stolen Memory (BSM): This register contains bits 31:20 of the base address of stolen DRAM memory. The host interface determines the base of Graphics Stolen memory by subtracting the graphics stolen memory size from TOLUD. See Device 0 TOLUD for more explanation. Reserved 19:0 RO 00000h 8.1.25 HSRW—Hardware Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit 15:0 Access & Default RW 0000h Reserved 0/2/0/PCI 60–61h 0000h RW 16 bits Description Datasheet 259 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.26 MC—Message Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 92–93h 0000h RO, RW 16 bits System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is ensured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one. Bit 15:8 7 Access & Default RO 00h RO 0b Reserved 64 Bit Capable (64BCAP): Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message address register and is incapable of generating a 64-bit memory address. This may need to change in future implementations when addressable system memory exceeds the 32b / 4 GB limit. 6:4 RW 000b Multiple Message Enable (MME): System software programs this field to indicate the actual number of messages allocated to this device. This number will be equal to or less than the number actually requested. The encoding is the same as for the MMC field (Bits 3:1). 3:1 RO 000b Multiple Message Capable (MMC): System Software reads this field to determine the number of messages being requested by this device. 000 = 1 All of the following are reserved in this implementation 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = Reserved 111 = Reserved 0 RW 0b MSI Enable (MSIEN): This bit controls the ability of this device to generate MSIs. Description 260 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.27 MA—Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 94–97h 00000000h RW, RO 32 bits Bit 31:2 Access & Default RW 00000000h Description Message Address (MESSADD): Used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address. 1:0 RO 00b Force DWord Align (FDWORD): Hardwired to 0 so that addresses assigned by system software are always aligned on a DWord address boundary. 8.1.28 MD—Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI 98–99h 0000h RW 16 bits Bit 15:0 Access & Default RW 0000h Description Message Data (MESSDATA): Base message data pattern assigned by system software and used to handle an MSI from the device. When the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register. The upper 16 bits are always set to 0. The lower 16 bits are supplied by this register. Datasheet 261 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.29 GDRST—Graphics Debug Reset B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI C0h 00h RO, RW 8 bits Bit 7:4 3:2 Access & Default RO 0h RW 00b Reserved Description Graphics Reset Domain (GRDOM): 00 = Full Graphics Reset will be performed (both render and display clock domain resets asserted 01 = Reserved (Invalid Programming) 10 = Reserved (Invalid Programming) 11 = Reserved (Invalid Programming) 1 0 RO 0b RW 0b Reserved Graphics Reset Enable (GR): Setting this bit asserts graphics-only reset. The clock domains to be reset are determined by GRDOM. Hardware resets this bit when the reset is complete. Setting this bit without waiting for it to clear, is undefined behavior. Once this bit is set to a 1, all GFX core MMIO registers are returned to power on default state. All Ring buffer pointers are reset, command stream fetches are dropped and ongoing render pipeline processing is halted, state machines and State Variables returned to power on default state. If the Display is reset, all display engines are halted (garbage on screen). VGA memory is not available, Store DWords and interrupts are not assured to be completed. Device 2 I/O registers are not available. When issuing the graphics reset, disable the cursor, display, and overlay engines using the MMIO registers. Wait 1 us. Issue the graphics reset by setting this bit to 1. Device 2 Configuration registers continue to be available while graphics reset is asserted. This bit is hardware auto-clear. 262 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.30 PMCAPID—Power Management Capabilities ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI D0–D1h 0001h RWO, RO 16 bits Bit 15:8 Access & Default RWO 00h RO 01h Description Next Capability Pointer (NEXT_PTR): This field contains a pointer to the next item in the capabilities list. BIOS is responsible for writing this to the FLR Capability when applicable. Capability Identifier (CAP_ID): SIG defines this ID is 01h for power management. 7:0 8.1.31 PMCAP—Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI D2–D3h 0022h RO 16 bits This register is a Mirror of Function 0 with the same read/write attributes. The hardware implements a single physical register common to both functions 0 and 1. Bit 15:11 Access & Default RO 00h RO 0b RO 0b RO 000b RO 1b RO 0b RO 0b RO 010b Description PME Support (PMES): This field indicates the power states in which the IGD may assert PME#. Hardwired to 0 to indicate that the IGD does not assert the PME# signal. D2 Support (D2): The D2 power management state is not supported. This bit is hardwired to 0. D1 Support (D1): Hardwired to 0 to indicate that the D1 power management state is not supported. Reserved Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD is required before generic class device driver is to use it. Reserved PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not support PME# generation. Version (VER): Hardwired to 010b to indicate that there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the PCI Power Management Interface Specification. 10 9 8:6 5 4 3 2:0 Datasheet 263 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.32 PMCS—Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI D4–D5h 0000h RO, RW 16 bits Bit 15 14:13 12:9 8 7:2 1:0 Access & Default RO 0b RO 00b RO 0h RO 0b RO 00h RW 00b Description PME Status (PMESTS): This bit is 0 to indicate that IGD does not support PME# generation from D3 (cold). Data Scale (DSCALE): The IGD does not support data register. This bit always returns 00 when read, write operations have no effect. Data Select (DSEL): The IGD does not support data register. This bit always returns 0h when read, write operations have no effect. PME Enable (PME_EN): This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled. Reserved Power State (PWRSTAT): This field indicates the current power state of the IGD and can be used to set the IGD into a new power state. If software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. On a transition from D3 to D0 the graphics controller is optionally reset to initial values. 00 = D0 (Default) 01 = D1 (Not Supported) 10 = D2 (Not Supported) 11 = D3 264 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.1.33 SWSMI—Software SMI B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/0/PCI E0–E1h 0000h RW 16 bits As long as there is the potential that DVO port legacy drivers exist which expect this register at this address, D2, F0 address E0h–E1h must be reserved for this register. Bit 15:8 7:1 0 Access & Default RW 00h RW 00h RW 0b Description Software Scratch Bits (SWSB): Software Flag (SWF): Used to indicate caller and SMI function desired, as well as return result. GMCH Software SMI Event (GSSMIE): When Set this bit will trigger an SMI. Software must write a "0" to clear this bit. Datasheet 265 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2 IGD Configuration Register Details (D2:F1) The Integrated Graphics Device registers are located in Device 2 (D2), Function 0 (F0) and Function 1 (F1). This section provides the descriptions for the D2:F1 registers. Table 8-2 provides an address map of the D2:F1registers listed in ascending order by address offset. Detailed bit descriptions follow the table. Table 8-2. Integrated Graphics Device Register Address Map (D2:F1) Address Offset 00–01h 02–03h 04–05h 06–07h 08h 09–0Bh 0Ch 0Dh 0Eh 10–13h 2C–2Dh 2E–2Fh 30–33h 34h 3Eh 3Fh 40–50h Register Symbol VID2 DID2 PCICMD2 PCISTS2 RID2 CC CLS MLT2 HDR2 MMADR SVID2 SID2 ROMADR CAPPOINT MINGNT MAXLAT CAPID0 Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Register Cache Line Size Master Latency Timer Header Type Memory Mapped Range Address Subsystem Vendor Identification Subsystem Identification Video BIOS ROM Base Address Capabilities Pointer Minimum Grant Maximum Latency Mirror of Dev0 Capability Identifier Default Value 8086h 29C3h 0000h 0090h 00h 038000h 00h 00h 80h 00000000h 0000h 0000h 00000000h D0h 00h 00h 0000000000 0000000100 000000010 B0009h 0030h 000003DBh 00000000h 07800000h 0000h Access RO RO RO, RW RO RO RO RO RO RO RW, RO RO RO RO RO RO RO RO 52–53h 54–57h 58–5Bh 5C–5Fh 60–61h MGGC DEVEN SSRW BSM HSRW Mirror of Dev 0 GMCH Graphics Control Register Device Enable Mirror of Fun 0 Software Scratch Read Write Mirror of Func0 Base of Stolen Memory Mirror of Dev2 Func0 Hardware Scratch Read Write RO RO RO RO RO 266 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Address Offset 62h C0h C1–C3h C4–C7h C8h CA–CBh CC–CDh D0–D1h D2–D3h D4–D5h D8–DBh E0–E1h E4–E7h F0–F3h F4–F7h FC–FFh Register Symbol MSAC GDRST MI_GFX_CG_ DIS RSVD RSVD RSVD GCDGMBUS PMCAPID PMCAP PMCS RSVD SWSMI ASLE GCFGC RSVD ASLS Register Name Mirror of Dev2 Func0 Multi Size Aperture Control Mirror of Dev2 Func0 Graphics Reset Mirror of Fun 0 MI GFX Unit Level Clock Ungating Reserved Reserved Reserved Mirror of Dev2 Func0 Graphics Clock Frequency Register for GMBUS unit Mirror of Fun 0 Power Management Capabilities ID Mirror of Fun 0 Power Management Capabilities Power Management Control/Status Reserved Mirror of Func0 Software SMI Mirror of Dev2 Func0 System Display Event Register Mirror of Dev2 Func0 Graphics Clock Frequency and Gating Control Mirror of Fun 0 Reserved for LBBLegacy Backlight Brightness ASL Storage Default Value 02h 00h 000000h 00000000h 00h 0000h 0000h 0001h 0022h 0000h 00000000h 0000h 00000000h 00000000h 00000000h 00000000h Access RO RO RO RO RO RO RO RO RO RO, RW RO RO RO RO/P, RO RO RW Datasheet 267 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.1 VID2—Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 00–01h 8086h RO 16 bits This register, combined with the Device Identification register, uniquely identifies any PCI device. Bit 15:0 Access & Default RO 8086h Description Vendor Identification Number (VID): PCI standard identification for Intel. 8.2.2 DID2—Device Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 02–03h 29C3h RO 16 bits This register is unique in Function 1 (the Function 0 DID is separate). This difference in Device ID is necessary for allowing distinct Plug and Play enumeration of function 1 when both function 0 and function 1 have the same class code. Bit 15:0 Access & Default RO 29C3h Description Device Identification Number (DID): This is a 16 bit value assigned to the GMCH Graphic device Function 1 268 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.3 PCICMD2—PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 04–05h 0000h RO, RW 16 bits This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory. Bit 15:10 9 8 7 6 Access & Default RO 0s RO 0b RO 0b RO 0b RO 0b Reserved Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0. SERR Enable (SERRE): Not Implemented. Hardwired to 0. Address/Data Stepping Enable (ADSTEP): Not Implemented. Hardwired to 0. Parity Error Enable (PERRE): Not Implemented. Hardwired to 0. Since the IGD belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the IGD ignores any parity error that it detects and continues with normal operation. VGA Palette Snoop Enable (VGASNOOP): This bit is hardwired to 0 to disable snooping. Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does not support memory write and invalidate commands. Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD ignores Special cycles. Bus Master Enable (BME): 0 = Disable IGD bus mastering. 1 = Enable the IGD to function as a PCI compliant master. 1 RW 0b Memory Access Enable (MAE): This bit controls the IGD's response to memory space accesses. 0 = Disable. 1 = Enable. 0 RW 0b I/O Access Enable (IOAE): This bit controls the IGD's response to I/O space accesses. 0 = Disable. 1 = Enable. Description 5 4 3 2 RO 0b RO 0b RO 0b RW 0b Datasheet 269 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.4 PCISTS2—PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 06–07h 0090h RO 16 bits PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD. Bit 15 14 13 12 11 10:9 8 Access & Default RO 0b RO 0b RO 0b RO 0b RO 0b RO 00b RO 0b RO 1b RO 0b RO 0b RO 1b RO 0b RO 000b Description Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always hardwired to 0. Signaled System Error (SSE): The IGD never asserts SERR#, therefore this bit is hardwired to 0. Received Master Abort Status (RMAS): The IGD never gets a Master Abort, therefore this bit is hardwired to 0. Received Target Abort Status (RTAS): The IGD never gets a Target Abort, therefore this bit is hardwired to 0. Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use target abort semantics. DEVSEL Timing (DEVT): N/A. These bits are hardwired to "00". Master Data Parity Error Detected (DPD): Since Parity Error Response is hardwired to disabled (and the IGD does not do any parity detection), this bit is hardwired to 0. Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back when the transactions are not to the same agent. User Defined Format (UDF): Hardwired to 0. 66 MHz PCI Capable (66C): N/A - Hardwired to 0. Capability List (CLIST): This bit is set to 1 to indicate that the register at 34h provides an offset into the function's PCI Configuration Space containing a pointer to the location of the first item in the list. Interrupt Status (INTSTS): Hardwired to 0. Reserved 7 6 5 4 3 2:0 270 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.5 RID2—Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 08h 00h RO 8 bits This register contains the revision number for Device 2 Functions 0 and 1. Bit 7:0 Access & Default RO 00h Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH Device 2. Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 8.2.6 CC—Class Code Register B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 09–0Bh 038000h RO 24 bits This register contains the device programming interface information related to the Sub-Class Code and Base Class Code definition for the IGD. This register also contains the Base Class Code and the function sub-class in relation to the Base Class Code. Bit 23:16 Access & Default RO 03h RO 80h RO 00h Description Base Class Code (BCC): This is an 8-bit value that indicates the base class code for the GMCH. This code has the value 03h, indicating a Display Controller. Sub-Class Code (SUBCC): 80h = Non VGA Programming Interface (PI): 00h = Hardwired as a Display controller. 15:8 7:0 Datasheet 271 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.7 CLS—Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 0Ch 00h RO 8 bits The IGD does not support this register as a PCI slave. Bit 7:0 Access & Default RO 00h Description Cache Line Size (CLS): This field is hardwired to 0s. The IGD as a PCI compliant master does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size. 8.2.8 MLT2—Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI Dh 00h RO 8 bits The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit 7:0 Access & Default RO 00h Description Master Latency Timer Count Value (MLTCV): Hardwired to 0s. 272 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.9 HDR2—Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 0Eh 80h RO 8 bits This register contains the Header Type of the IGD. Bit 7 Access & Default RO 1b Description Multi Function Status (MFUNC): Indicates if the device is a MultiFunction Device. The Value of this register is determined by Device 0, offset 54h, DEVEN[4]. If Device 0 DEVEN[4] is set, the MFUNC bit is also set. Header Code (H): This is a 7-bit value that indicates the Header Code for the IGD. This code has the value 00h, indicating a type 0 configuration space format. 6:0 RO 00h 8.2.10 MMADR—Memory Mapped Range Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 10–13h 00000000h RW, RO 32 bits This register requests allocation for the IGD registers and instruction ports. The allocation is for 512 KB and the base address is defined by bits 31:19. Bit 31:19 18:4 3 2:1 0 Access & Default RW 0000h RO 0000h RO 0b RO 00b RO 0b Description Memory Base Address (MBA): Set by the OS, these bits correspond to address signals 31:19. Address Mask (ADMSK): Hardwired to 0s to indicate 512 KB address range. Prefetchable Memory (PREFMEM): Hardwired to 0 to prevent prefetching. Memory Type (MEMTYP): Hardwired to 0s to indicate 32-bit address. Memory / IO Space (MIOS): Hardwired to 0 to indicate memory space. Datasheet 273 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.11 SVID2—Subsystem Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 2C–2Dh 0000h RO 16 bits Bit 15:0 Access & Default RO 0000h Description Subsystem Vendor ID (SUBVID): This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a Reset. 8.2.12 SID2—Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 2E–2Fh 0000h RO 16 bits Bit 15:0 Access & Default RO 0000h Description Subsystem Identification (SUBID): This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a Reset. 274 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.13 ROMADR—Video BIOS ROM Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 30–33h 00000000h RO 32 bits The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s. Bit 31:18 17:11 10:1 0 Access & Default RO 0000h RO 00h RO 000h RO 0b Description ROM Base Address (RBA): Hardwired to 0s. Address Mask (ADMSK): Hardwired to 0s to indicate 256 KB address range. Reserved. Hardwired to 0s. ROM BIOS Enable (RBE): 0= ROM not accessible. 8.2.14 CAPPOINT—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 34h D0h RO 8 bits Bit 7:0 Access & Default RO D0h Description Capabilities Pointer Value (CPV): This field contains an offset into the function's PCI Configuration Space for the first item in the New Capabilities Linked List, the MSI Capabilities ID registers at the Power Management capability at D0h. Datasheet 275 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.15 MINGNT—Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 3Eh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Minimum Grant Value (MGV): The IGD does not burst as a PCI compliant master. 8.2.16 MAXLAT—Maximum Latency B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 3Fh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Maximum Latency Value (MLV): The IGD has no specific requirements for how often it needs to access the PCI bus. 8.2.17 CAPID0—Mirror of Dev0 Capability Identifier B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/2/1/PCI 40–50h 00000000000000000100000000010B0009h RO 136 bits 000000000000h This register control of bits in this register are only required for customer visible SKU differentiation. Bit 7:0 Access & Default RO 09h Description Capability Identifier (CAP_ID): This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. 276 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.18 MGGC—Mirror of Dev 0 GMCH Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 52–53h 0030h RO 16 bits All the Bits in this register are Intel® TXT lockable. Bit 15:10 9:8 Access & Default RO 00h RO 0h Reserved GTT Graphics Memory Size (GGMS): This field is used to select the amount of main memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is preallocated only when Internal graphics is enabled. 00 = No memory pre-allocated. GTT cycles (Memory and I/O) are not claimed. 01 = No VT mode, 1 MB of memory pre-allocated for GTT. 10 = VT mode, 2 MB of memory pre-allocated for GTT. 11 = reserved Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. Description Datasheet 277 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Bit 7:4 Access & Default RO 0011b Description Graphics Mode Select (GMS) This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled. 0000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and the Sub-Class Code field within Device 2 function 0 Class Code register is 80h. 0001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame buffer. 0010 = DVMT (UMA) mode, 4 MB of memory pre-allocated for frame buffer. 0011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame buffer. 0100 = DVMT (UMA) mode, 16 MB of memory pre-allocated for frame buffer. 0101 = DVMT (UMA) mode, 32 MB of memory pre-allocated for frame buffer. 0110 = DVMT (UMA) mode, 48 MB of memory pre-allocated for frame buffer. 0111 = DVMT (UMA) mode, 64 MB of memory pre-allocated for frame buffer. 1000 = DVMT (UMA) mode, 128 MB of memory pre-allocated for frame buffer. 1001 = DVMT (UMA) mode, 256 MB of memory pre-allocated for frame buffer. Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. BIOS Requirement: BIOS must not set this field to 000 if IVD (bit 1 of this register) is 0. 3:2 1 RO 00b RO 0b Reserved IGD VGA Disable (IVD): 0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the Sub-Class Code within Device 2 Class Code register is 00. 1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and the Sub- Class Code field within Device 2, function 0 Class Code register is 80h. BIOS Requirement: BIOS must not set this bit to 0 if the GMS field (bits 6:4 of this register) pre-allocates no memory. This bit MUST be set to 1 if Device 2 is disabled either via a fuse or fuse override (CAPID0[38] = 1) or via a register (DEVEN[3] = 0). 0 RO 0b Reserved 278 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.19 DEVEN—Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 54–57h 000003DBh RO 32 bits This register allows for enabling/disabling of PCI devices and functions that are within the GMCH. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel® TXT Lockable. Bit 31:15 14 Access & Default RO 00000h RO 0b Reserved Chap Enable (D7EN): 0 = Bus0:Device7 is disabled and not visible. 1 = Bus0:Device7 is enabled and visible. Non-production BIOS code should provide a setup option to enable Bus0:Device7. When enabled, Bus0:Device7 must be initialized in accordance to standard PCI device initialization procedures. 13:10 9 RO 0s RO 1b Reserved EP Function 3 (D3F3EN): 0 = Bus0:Device3:Function3 is disabled and hidden 1 = Bus0:Device3:Function 3 is enabled and visible If Device3:Function0 is disabled and hidden, then Device3:Function3 is also disabled and hidden independent of the state of this bit. 8 RO 1b EP Function 2 (D3F2EN): 0 = Bus0:Device3:Function2 is disabled and hidden 1 = Bus0:Device3:Function2 is enabled and visible If Device3:Function0 is disabled and hidden, then Device3:Function2 is also disabled and hidden independent of the state of this bit. 7 RO 1b EP Function 1 (D3F1EN): 0 = Bus0:Device3:Function1 is disabled and hidden 1 = Bus0:Device3:Function1 is enabled and visible. If this GMCH does not have ME capability (CAPID0[??] = 1), then Device3:Function1 is disabled and hidden independent of the state of this bit. 6 RO 1b EP Function 0 (D3F0EN): 0 = Bus0:Device3:Function0 is disabled and hidden 1 = Bus0:Device3:Function0 is enabled and visible. If this GMCH does not have ME capability (CAPID0[??] = 1), then Device3:Function0 is disabled and hidden independent of the state of this bit. 5 RO 0b Reserved Description Datasheet 279 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Bit 4 Access & Default RO 1b Description Internal Graphics Engine Function 1 (D2F1EN): 0 = Bus 0:Device2:Function1 is disabled and hidden 1 = Bus0:Device2:Function1 is enabled and visible If Device2:Function0 is disabled and hidden, then Device2:Function1 is also disabled and hidden independent of the state of this bit. If this component is not capable of Dual Independent Display (CAPID0[78] = 1), then this bit is hardwired to 0b to hide Device2:Function1. 3 RO 1b Internal Graphics Engine Function 0 (D2F0EN): 0 = Bus0:Device2:Function0 is disabled and hidden 1 = Bus0:Device2:Function0 is enabled and visible If this GMCH does not have internal graphics capability (CAPID0[46] = 1), then Device2:Function0 is disabled and hidden independent of the state of this bit. 2 1 RO RO 1b Reserved PCI Express Port (D1EN): 0 = Bus0:Device1:Function0 is disabled and hidden. 1 = Bus0:Device1:Function0 is enabled and visible. Default value is determined by the device capabilities (see CAPID0 [44]), SDVO Presence hardware strap and the SDVO/PCIe Concurrent hardware strap. Device 1 is Disabled on Reset if the SDVO Presence strap was sampled high, and the SDVO/PCIe Concurrent strap was sampled low at the last assertion of PWROK, and is enabled by default otherwise. 0 RO 1b Host Bridge (D0EN): Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired to 1. 280 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.20 SSRW—Mirror of Fun 0 Software Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 58–5Bh 00000000h RO 32 bits Bit 31:0 Access & Default RO 00000000h Reserved Description 8.2.21 BSM—Mirror of Func0 Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 5C–5Fh 07800000h RO 32 bits Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the top of low used DRAM, GMCH claims 1 to 64 MBs of DRAM for internal graphics if enabled. The base of stolen memory will always be below 4 GB. This is required to prevent aliasing between stolen range and the reclaim region. Bit 31:20 Access & Default RO 078h Description Base of Stolen Memory (BSM): This register contains bits 31:20 of the base address of stolen DRAM memory. The host interface determines the base of Graphics Stolen memory by subtracting the graphics stolen memory size from TOLUD. See Device 0 TOLUD for more explanation. Reserved 19:0 RO 00000h Datasheet 281 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.22 HSRW—Mirror of Dev2 Func0 Hardware Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI 60–61h 0000h RO 16 bits Bit 15:0 Access & Default RO 0000h Reserved Description 8.2.23 GDRST—Mirror of Dev2 Func0 Graphics Reset B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI C0h 00h RO 8 bits This register is a mirror of the Graphics Reset Register in Device 2. Bit 7:4 3:2 Access & Default RO 0h RO 00b Reserved Graphics Reset Domain (GRDOM): 00 = Full Graphics Reset will be performed (both render and display clock domain resets asserted 01 = Reserved (Invalid Programming) 10 = Reserved (Invalid Programming) 11 = Reserved (Invalid Programming) 1 RO 0b Reserved Description 282 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Bit 0 Access & Default RO 0b Description Graphics Reset (GDR): Setting this bit asserts graphics-only reset. The clock domains to be reset are determined by GRDOM. Hardware resets this bit when the reset is complete. Setting this bit without waiting for it to clear, is undefined behavior. Once this bit is set to a 1, all GFX core MMIO registers are returned to power on default state. All Ring buffer pointers are reset, command stream fetches are dropped and ongoing render pipeline processing is halted, state machines and State Variables returned to power on default state. If the Display is reset, all display engines are halted (garbage on screen). VGA memory is not available; Store DWords and interrupts are not ensured to be completed. Device #2 IO registers are not available. Device 2 Configuration registers continue to be available while Graphics reset is asserted. This bit is hardware auto-clear. 8.2.24 PMCAPID—Mirror of Fun 0 Power Management Capabilities ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI D0–D1h 0001h RO 16 bits This register is a mirror of function 0 with the same R/W attributes. The hardware implements a single physical register common to both functions 0 and 1. Bit 15:8 Access & Default RO 00h RO 01h Description Next Capability Pointer (NEXT_PTR): This contains a pointer to next item in capabilities list. This is the final capability in the list and must be set to 00h. Capability Identifier (CAP_ID): SIG defines this ID is 01h for power management. 7:0 Datasheet 283 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.25 PMCAP—Mirror of Fun 0 Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI D2–D3h 0022h RO 16 bits This register is a Mirror of Function 0 with the same read/write attributes. The hardware implements a single physical register common to both functions 0 and 1. Bit 15:11 Access & Default RO 00h RO 0b RO 0b RO 000b RO 1b RO 0b RO 0b RO 010b Description PME Support (PMES): This field indicates the power states in which the IGD may assert PME#. Hardwired to 0 to indicate that the IGD does not assert the PME# signal. D2 Support (D2): The D2 power management state is not supported. This bit is hardwired to 0. D1 Support (D1): Hardwired to 0 to indicate that the D1 power management state is not supported. Reserved Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD is required before generic class device driver is to use it. Reserved PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not support PME# generation. Version (VER): Hardwired to 010b to indicate that there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the PCI Power Management Interface Specification. 10 9 8:6 5 4 3 2:0 284 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.26 PMCS—Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI D4–D5h 0000h RO, RW 16 bits Bit 15 14:13 12:9 8 7:2 1:0 Access & Default RO 0b RO 00b RO 0h RO 0b RO 00h RW 00b Description PME Status (PMESTS): This bit is 0 to indicate that IGD does not support PME# generation from D3 (cold). Data Scale (DSCALE): The IGD does not support data register. This bit always returns 0 when read, write operations have no effect. Data Select (DATASEL): The IGD does not support data register. This bit always returns 0 when read, write operations have no effect. PME Enable (PME_EN): This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled. Reserved Power State (PWRSTAT): This field indicates the current power state of the IGD and can be used to set the IGD into a new power state. If software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. On a transition from D3 to D0 the graphics controller is optionally reset to initial values. 00 = D0 (Default) 01 = D1 (Not Supported) 10 = D2 (Not Supported) 11 = D3 Datasheet 285 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 8.2.27 SWSMI—Mirror of Func0 Software SMI B/D/F/Type: Address Offset: Default Value: Access: Size: 0/2/1/PCI E0–E1h 0000h RO 16 bits As long as there is the potential that DVO port legacy drivers exist which expect this register at this address, D2:F0 address E0h–E1h must be reserved for this register. Bit 15:8 7:1 0 Access & Default RO 00h RO 00h RO 0b Description Software Scratch Bits (SWSB): Software Flag (SWF): This field is used to indicate caller and SMI function desired, as well as return result. GMCH Software SMI Event (GSSMIE): When Set, this bit will trigger an SMI. Software must write a 0 to clear this bit. § 286 Datasheet Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Datasheet 287 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Host Embedded Controller Interface (HECI1) Configuration Register Details (D3:F0) 9.1 Table 9-1. HECI Function in ME Subsystem Register Address Map Address Offset 00–03h 04–05h 06–07h 08h 09–0Bh 0Ch 0Dh 0Eh 0Fh 10–17h 2C–2Fh 34h 3C–3Dh 3Eh 3Fh 40–43h 50–51h 52–53h 54–55h Register Symbol ID CMD STS RID CC CLS MLT HTYPE BIST HECI_MBAR SS CAP INTR MGNT MLAT HFS PID PC PMCS Register Name Identifiers Command Device Status Revision ID Class Code Cache Line Size Master Latency Timer Header Type Built In Self Test HECI MMIO Base Address Sub System Identifiers Capabilities Pointer Interrupt Information Minimum Grant Maximum Latency Host Firmware Status PCI Power Management Capability ID PCI Power Management Capabilities PCI Power Management Control And Status Default Value 29C48086h 0000h 0010h 00h 078000h 00h 00h 80h 00h 0000000000 000004h 00000000h 50h 0100h 00h 00h 00000000h 8C01h C803h 0008h Access RO RO, RW RO RO RO RO RO RO RO RW, RO RWO RO RO, RW RO RO RO RO RO RWC, RO, RW 288 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Address Offset 8C–8Dh 8E–8Fh 90–93h 94–97h 98–99h A0h Register Symbol MID MC MA MUA MD HIDM Register Name Message Signaled Interrupt Identifiers Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Upper Address (Optional) Message Signaled Interrupt Message Data HECI Interrupt Delivery Mode Default Value 0005h 0080h 00000000h 00000000h 0000h 00h Access RO RO, RW RW, RO RW RW RW 9.1.1 ID— Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 00–03h 29C48086h RO 32 bits Bit 31:16 15:0 Access & Default RO 29C4h RO 8086h Description Device ID (DID): Indicates what device number assigned by Intel. Vendor ID (VID): 16-bit field which indicates Intel is the vendor, assigned by the PCI SIG. Datasheet 289 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.2 CMD— Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 04–05h 0000h RO, RW 16 bits Bit 15:11 10 9 8 7 6 5 4 3 2 Access & Default RO 00000b RW 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RW 0b Reserved Description Interrupt Disable (ID): Disables this device from generating PCI line based interrupts. This bit does not have any effect on MSI operation. Fast Back-to-Back Enable (FBE): Not implemented, hardwired to 0. SERR# Enable (SEE): Not implemented, hardwired to 0. Wait Cycle Enable (WCC): Not implemented, hardwired to 0. Parity Error Response Enable (PEE): Not implemented, hardwired to 0. VGA Palette Snooping Enable (VGA): Not implemented, hardwired to 0 Memory Write and Invalidate Enable (MWIE): Not implemented, hardwired to 0. Special Cycle Enable (SCE): Not implemented, hardwired to 0. Bus Master Enable (BME): This bit controls the HECI host controller's ability to act as a system memory master for data transfers. When this bit is cleared, HECI bus master activity stops and any active DMA engines return to an idle condition. 1 = Enable 0 = Disable. HECI is blocked from generating MSI to the host processor. Note that this bit does not block HECI accesses to ME-UMA (i.e., writes or reads to the host and ME circular buffers through the read window and write window registers still cause ME backbone transactions to MEUMA). 1 RW 0b Memory Space Enable (MSE): This bit controls access to the HECI host controller’s memory mapped register space. 0 = Disable 1= Enable 0 RO 0b I/O Space Enable (IOSE): Not implemented, hardwired to 0. 290 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.3 STS— Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 06–07h 0010h RO 16 bits Bit 15 14 13 12 11 10:9 8 7 6 5 4 3 Access & Default RO 0b RO 0b RO 0b RO 0b RO 0b RO 00b RO 0b RO 0b RO 0b RO 0b RO 1b RO 0b Description Detected Parity Error (DPE): Not implemented, hardwired to 0. Signaled System Error (SSE): Not implemented, hardwired to 0. Received Master-Abort (RMA): Not implemented, hardwired to 0. Received Target Abort (RTA): Not implemented, hardwired to 0. Signaled Target-Abort (STA): Not implemented, hardwired to 0. DEVSEL# Timing (DEVT): These bits are hardwired to 00. Master Data Parity Error Detected (DPD): Not implemented, hardwired to 0. Fast Back-to-Back Capable (FBC): Not implemented, hardwired to 0. Reserved 66 MHz Capable (C66): Not implemented, hardwired to 0. Capabilities List (CL): Indicates the presence of a capabilities list, hardwired to 1. Interrupt Status (IS): Indicates the interrupt status of the device 0 = Not asserted 1 = Asserted 2:0 RO 000b Reserved Datasheet 291 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.4 RID— Revision ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 08h 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Revision ID (RID): Indicates stepping of the HECI host controller. Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 9.1.5 CC— Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 09–0Bh 078000h RO 24 bits Bit 23:16 15:8 7:0 Access & Default RO 07h RO 80h RO 00h Description Base Class Code (BCC): Indicates the base class code of the HECI host controller device. Sub Class Code (SCC): Indicates the sub class code of the HECI host controller device. Programming Interface (PI): Indicates the programming interface of the HECI host controller device. 9.1.6 CLS— Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 0Ch 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Cache Line Size (CLS): Not implemented, hardwired to 0. 292 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.7 MLT— Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 0Dh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Master Latency Timer (MLT): Not implemented, hardwired to 0. 9.1.8 HTYPE— Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 0Eh 80h RO 8 bits Bit 7 6:0 Access & Default RO 1b RO 0000000b Description Multi-Function Device (MFD): Indicates the HECI host controller is part of a multi-function device. Header Layout (HL): Indicates that the HECI host controller uses a target device layout. Datasheet 293 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.9 HECI_MBAR— HECI MMIO Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 10–17h 0000000000000004h RW, RO 64 bits Bit 63:4 Access & Default RW 00000000 0000000h RO 0b RO 10b RO 0b Description Base Address (BA): Base address of register memory space. Bits 63:4 correspond to address bits 63:4. Prefetchable (PF): Indicates that this range is not pre-fetchable Type (TP): Indicates that this range can be mapped anywhere in 64bit address space. Resource Type Indicator (RTE): Indicates a request for register memory space. 3 2:1 0 9.1.10 SS— Sub System Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 2C–2Fh 00000000h RWO 32 bits Bit 31:16 Access & Default RWO 0000h RWO 0000h Description Subsystem ID (SSID): Indicates the sub-system identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Subsystem Vendor ID (SSVID): Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. 15:0 294 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.11 CAP— Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 34h 50h RO 8 bits Bit 7:0 Access & Default RO 50h Description Capability Pointer (CP): Indicates the first capability pointer offset. It points to the PCI power management capability offset. 9.1.12 INTR— Interrupt Information B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 3C–3Dh 0100h RO, RW 16 bits Bit 15:8 Access & Default RO 01h Description Interrupt Pin (IPIN): This indicates the interrupt pin the HECI host controller uses. The value of 01h selects INTA# interrupt pin. Note: As HECI is an internal device in the GMCH, the INTA# pin is implemented as an INTA# message to the ICH9. 7:0 RW 00h Interrupt Line (ILINE): Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. 9.1.13 MGNT— Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 3Eh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Grant (GNT): Not implemented, hardwired to 0. Datasheet 295 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.14 MLAT— Maximum Latency B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 3Fh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Latency (LAT): Not implemented, hardwired to 0. 9.1.15 HFS— Host Firmware Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 40–43h 00000000h RO 32 bits Bit 31:0 Access & Default RO 00000000h Description Firmware Status Host Access (FS_HA): Indicates current status of the firmware for the HECI controller. This field is the host's read only access to the FS field in the ME Firmware Status AUX register. 9.1.16 PID— PCI Power Management Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 50–51h 8C01h RO 16 bits Bit 15:8 7:0 Access & Default RO 8Ch RO 01h Description Next Capability (NEXT): Indicates the location of the next capability item in the list. This is the Message Signaled Interrupts capability. Cap ID (CID): Indicates that this pointer is a PCI power management. 296 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.17 PC— PCI Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 52–53h C803h RO 16 bits Bit 15:11 Access & Default RO 11001b Description PME_Support (PSUP): Indicates the states that can generate PME#. HECI can assert PME# from any D-state except D1 or D2 which are not supported by HECI. D2_Support (D2S): The D2 state is not supported for the HECI host controller. D1_Support (D1S): The D1 state is not supported for the HECI host controller. Aux_Current (AUXC): Reports the maximum Suspend well current required when in the D3COLD state. Value of TBD is reported. Device Specific Initialization (DSI): Indicates whether devicespecific initialization is required. Reserved PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#. Version (VS): Indicates support for Revision 1.2 of the PCI Power Management Specification. 10 9 8:6 5 4 3 2:0 RO 0b RO 0b RO 000b RO 0b RO 0b RO 0b RO 011b Datasheet 297 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.18 PMCS— PCI Power Management Control And Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 54–55h 0008h RWC, RO, RW 16 bits Bit 15 Access & Default RWC 0b PME Status (PMES): Description 1 = The PME Status bit in HECI space can be set to 1 by ME FW. 0 = This bit is cleared by host processor writing a 1 to it. ME cannot clear this bit. Host processor writes with value 0 have no effect on this bit. This bit is reset to 0 by MRST# 14:9 8 RO 000000b RW 0b Reserved. PME Enable (PMEE): This bit is read/write, under control of host software. It does not directly have an effect on PME events. However, this bit is shadowed into AUX space so ME FW can monitor it. The ME FW is responsible for ensuring that FW does not cause the PME-S bit to transition to 1 while the PMEE bit is 0, indicating that host software had disabled PME. 0 = Disable 1 = Enable This bit is reset to 0 by MRST#. 7:4 3 RO 0000b RO 1b Reserved No_Soft_Reset (NSR): This bit indicates that when the HECI host controller is transitioning from D3hot to D0 due to power state command, it does not perform and internal reset. Configuration context is preserved. Reserved Power State (PS): This field is used both to determine the current power state of the HECI host controller and to set a new power state. The values are: 00 = D0 state 11 = D3HOT state The D1 and D2 states are not supported for this HECI host controller. When in the D3HOT state, the configuration space is available, but the register memory spaces are not. Additionally, interrupts are blocked. 2 1:0 RO 0b RW 00b 298 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.19 MID— Message Signaled Interrupt Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 8C–8Dh 0005h RO 16 bits Bit 15:8 Access & Default RO 00h RO 05h Description Next Pointer (NEXT): Indicates the next item in the list. This can be other capability pointers (such as PCI-X or PCI-Express) or it can be the last item in the list. Capability ID (CID): Capabilities ID indicates MSI. 7:0 9.1.20 MC— Message Signaled Interrupt Message Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 8E–8Fh 0080h RO, RW 16 bits Bit 15:8 7 Access & Default RO 00h RO 1b Reserved Description 64 Bit Address Capable (C64): Specifies whether capable of generating 64-bit messages. 0 = Not capable 1 = Capable 6:4 3:1 0 RO 000b RO 000b RW 0b Multiple Message Enable (MME): Not implemented, hardwired to 0. Multiple Message Capable (MMC): Not implemented, hardwired to 0. MSI Enable (MSIE): 0 = Disable 1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts. Datasheet 299 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.21 MA— Message Signaled Interrupt Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 90–93h 00000000h RW, RO 32 bits Bit 31:2 Access & Default RW 00000000h Description Address (ADDR): This field provides the lower 32 bits of the system specified message address, always DWord aligned. MSI is not translated in Vtd; therefore, to avoid sending bad MSI with address, bit [31:20] will be masked internally to generate 12'hFEE regardless of content in register. Register attribute remains as RW. 1:0 RO 00b Reserved 9.1.22 MUA— Message Signaled Interrupt Upper Address (Optional) B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 94–97h 00000000h RW 32 bits Bit 31:0 Access & Default RW 00000000h Description Upper Address (UADDR): This field provides the upper 32 bits of the system specified message address. This register is optional and only implemented if MC.C64=1. MSI is not translated in Vtd, therefore, in order to avoid sending bad MSI with address bit [3:0] will be masked internally to generate 4'h0 regardless of content in register. Register attribute remains as RW. 300 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.1.23 MD— Message Signaled Interrupt Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 98–99h 0000h RW 16 bits Bit 15:0 Access & Default RW 0000h Description Data (Data): This 16-bit field is programmed by system software if MSI is enabled. Its content is driven onto the FSB during the data phase of the MSI memory write transaction. 9.1.24 HIDM—HECI Interrupt Delivery Mode B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/3/0/PCI A0h 00h RW 8 bits 00h This register is used to select interrupt delivery mechanism for HECI to Host processor interrupts. Bit 7:2 1:0 Access & Default RO 0h RW 00b Reserved HECI Interrupt Delivery Mode (HIDM): These bits control what type of interrupt the HECI will send when ME FW writes to set the M_IG bit in AUX space. They are interpreted as follows: 00 = Generate Legacy or MSI interrupt 01 = Generate SCI 10 = Generate SMI Description Datasheet 301 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2 HECI2 Configuration Register Details (D3:F1) (Intel® 82Q35 and 82Q33 GMCH only) Table 9-2. Second HECI Function in ME Subsystem Register Address Map Address Offset 00–03h 04–05h 06–07h 08h 09–0Bh 0Ch 0Dh 0Eh 10–17h 2C–2Fh 34h 3C–3Dh 3Eh 3Fh 40–43h 50–51h 52–53h 54–55h 8C–8Dh 8E–8Fh 90–93h 94–97h 98–99h A0h Register Symbol ID CMD STS RID CC CLS MLT HTYPE HECI_MBAR SS CAP INTR MGNT MLAT HFS PID PC PMCS MID MC MA MUA MD HIDM Identifiers Command Device Status Revision ID Class Code Cache Line Size Master Latency Timer Header Type HECI MMIO Base Address Sub System Identifiers Capabilities Pointer Interrupt Information Minimum Grant Maximum Latency Host Firmware Status PCI Power Management Capability ID PCI Power Management Capabilities PCI Power Management Control And Status Message Signaled Interrupt Identifiers Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Upper Address (Optional) Message Signaled Interrupt Message Data HECI Interrupt Delivery Mode Register Name Default Value 29C58086h 0000h 0010h 00h 078000h 00h 00h 80h 0000000000 000004h 00000000h 50h 0400h 00h 00h 00000000h 8C01h C803h 0008h 0005h 0080h 00000000h 00000000h 0000h 00h Access RO RO, RW RO RO RO RO RO RO RO, RW RWO RO RW, RO RO RO RO RO RO RO, RW, RWC RO RW, RO RW, RO RW RW RW 302 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.1 ID— Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 00–03h 29758086h RO 32 bits Bit 31:16 15:0 Access & Default RO 2975h RO 8086h Description Device ID (DID): Indicates what device number assigned by Intel. Vendor ID (VID): 16-bit field which indicates Intel is the vendor, assigned by the PCI SIG. 9.2.2 CMD— Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 04–05h 0000h RO, RW 16 bits Bit 15:11 10 Access & Default RO 00000b RW 0b Reserved Description Interrupt Disable (ID): Disables this device from generating PCI line based interrupts. This bit does not have any effect on MSI operation. 0 = Enable 1 = Disable 9 8 7 6 5 4 3 RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b Fast Back-to-Back Enable (FBE): Not implemented, hardwired to 0. SERR# Enable (SEE): Not implemented, hardwired to 0. Wait Cycle Enable (WCC): Not implemented, hardwired to 0. Parity Error Response Enable (PEE): Not implemented, hardwired to 0. VGA Palette Snooping Enable (VGA): Not implemented, hardwired to 0 Memory Write and Invalidate Enable (MWIE): Not implemented, hardwired to 0. Special Cycle Enable (SCE): Not implemented, hardwired to 0. Datasheet 303 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Bit 2 Access & Default RW 0b Description Bus Master Enable (BME): This bit controls the HECI host controller's ability to act as a system memory master for data transfers. When this bit is cleared, HECI bus master activity stops and any active DMA engines return to an idle condition. 0 = Disable. HECI is blocked from generating MSI to the host processor. 1 = Enable. Note that this bit does not block HECI accesses to ME-UMA (i.e., writes or reads to the host and ME circular buffers through the read window and write window registers still cause ME backbone transactions to MEUMA). 1 RW 0b Memory Space Enable (MSE): This bit controls access to the HECI host controller’s memory mapped register space. 0 = Disable 1 = Enable 0 RO 0b I/O Space Enable (IOSE): Not implemented, hardwired to 0. 304 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.3 STS— Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 06–07h 0010h RO 16 bits Bit 15 14 13 12 11 10:9 8 7 6 5 4 3 Access & Default RO RO 0b RO 0b RO 0b RO 0b RO 00b RO 0b RO 0b RO 0b RO 0b RO 1b RO 0b Description Detected Parity Error (DPE): Not implemented, hardwired to 0. Signaled System Error (SSE): Not implemented, hardwired to 0. Received Master-Abort (RMA): Not implemented, hardwired to 0. Received Target Abort (RTA): Not implemented, hardwired to 0. Signaled Target-Abort (STA): Not implemented, hardwired to 0. DEVSEL# Timing (DEVT): These bits are hardwired to 00. Master Data Parity Error Detected (DPD): Not implemented, hardwired to 0. Fast Back-to-Back Capable (FBC): Not implemented, hardwired to 0. Reserved 66 MHz Capable (C66): Not implemented, hardwired to 0. Capabilities List (CL): Indicates the presence of a capabilities list, hardwired to 1. Interrupt Status (IS): Indicates the interrupt status of the device. 0 = Not asserted 1 = Asserted 2:0 RO 000b Reserved Datasheet 305 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.4 RID— Revision ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 08h 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Revision ID (RID): Indicates stepping of the HECI host controller. Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 9.2.5 CC— Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 09–0Bh 078000h RO 24 bits Bit 23:16 15:8 7:0 Access & Default RO 07h RO 80h RO 00h Description Base Class Code (BCC): Indicates the base class code of the HECI host controller device. Sub Class Code (SCC): Indicates the sub class code of the HECI host controller device. Programming Interface (PI): Indicates the programming interface of the HECI host controller device. 9.2.6 CLS— Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 0Ch 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Cache Line Size (CLS): Not implemented, hardwired to 0. 306 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.7 MLT— Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 0Dh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Master Latency Timer (MLT): Not implemented, hardwired to 0. 9.2.8 HTYPE— Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 0Eh 80h RO 8 bits Bit 7 6:0 Access & Default RO 1b RO 0000000b Description Multi-Function Device (MFD): Indicates the HECI host controller is part of a multi-function device. Header Layout (HL): Indicates that the HECI host controller uses a target device layout. Datasheet 307 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.9 HECI_MBAR— HECI MMIO Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 10–17h 0000000000000004h RO, RW 64 bits This register allocates space for the HECI memory mapped registers defined in Section 1.5.6. Bit 63:4 Access & Default RW 00000000 0000000h RO 0b RO 10b RO 0b Description Base Address (BA): Base address of register memory space. 3 2:1 0 Prefetchable (PF): Indicates that this range is not pre-fetchable Type (TP): Indicates that this range can be mapped anywhere in 32bit address space Resource Type Indicator (RTE): Indicates a request for register memory space. 9.2.10 SS— Sub System Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 2C–2Fh 00000000h RWO 32 bits Bit 31:16 Access & Default RWO 0000h Description Subsystem ID (SSID): This field indicates the sub-system identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Subsystem Vendor ID (SSVID): This field indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. 15:0 RWO 0000h 308 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.11 CAP— Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 34h 50h RO 8 bits Bit 7:0 Access & Default RO 50h Description Capability Pointer (CP): This field indicates the first capability pointer offset. It points to the PCI power management capability offset. 9.2.12 INTR— Interrupt Information B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 3C–3Dh 0400h RW, RO 16 bits Bit 15:8 Access & Default RO 04h Description Interrupt Pin (IPIN): This field indicates the interrupt pin the HECI host controller uses. The value of 01h selects INTA# interrupt pin. Note: As HECI is an internal device in the GMCH, the INTA# pin is implemented as an INTA# message to the ICH9. 7:0 RW 00h Interrupt Line (ILINE): Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. 9.2.13 MGNT— Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 3Eh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Grant (GNT): Not implemented, hardwired to 0. Datasheet 309 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.14 MLAT— Maximum Latency B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 3Fh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Description Latency (LAT): Not implemented, hardwired to 0. 9.2.15 HFS— Host Firmware Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 40–43h 00000000h RO 32 bits Bit 31:0 Access & Default RO 00000000h Description Firmware Status Host Access (FS_HA): This field indicates current status of the firmware for the HECI controller. This field is the host's read only access to the FS field in the ME Firmware Status AUX register. 9.2.16 PID— PCI Power Management Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 50–51h 8C01h RO 16 bits Bit 15:8 Access & Default RO 8Ch RO 01h Description Next Capability (NEXT): This field indicates the location of the next capability item in the list. This is the Message Signaled Interrupts capability. Cap ID (CID): This field indicates that this pointer is a PCI power management. 7:0 310 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.17 PC— PCI Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 52–53h C803h RO 16 bits Bit 15:11 Access & Default RO 11001b Description PME_Support (PSUP): This field indicates the states that can generate PME#. HECI can assert PME# from any D-state except D1 or D2 which are not supported by HECI. 10 9 8:6 5 4 3 2:0 RO 0b RO 0b RO 000b RO 0b RO 0b RO 0b RO 011b D2_Support (D2S): The D2 state is not supported for the HECI host controller. D1_Support (D1S): The D1 state is not supported for the HECI host controller. Aux_Current (AUXC): This field reports the maximum Suspend well current required when in the D3COLD state. Value of TBD is reported. Device Specific Initialization (DSI): Indicates whether devicespecific initialization is required. Reserved PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#. Version (VS): Indicates support for Revision 1.2 of the PCI Power Management Specification. Datasheet 311 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.18 PMCS— PCI Power Management Control And Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 54–55h 0008h RO, RW, RWC 16 bits Bit 15 Access & Default RWC 0b Description PME Status (PMES): The PME Status bit in HECI space can be set to 1 by ME FW performing a write into AUX register to set PMES. This bit is cleared by host processor writing a 1 to it. ME FW cannot clear this bit. Host processor writes with value 0 have no effect on this bit. This bit is reset to 0 by MRST#. 14:9 8 RO 000000b RW 0b Reserved. PME Enable (PMEE): This bit is read/write, under control of host software. It does not directly have an effect on PME events. However, this bit is shadowed into AUX space so ME FW can monitor it. The ME FW is responsible for ensuring that FW does not cause the PME-S bit to transition to 1 while the PMEE bit is 0, indicating that host software had disabled PME. This bit is reset to 0 by MRST#. 7:4 3 RO 0000b RO 1b Reserved No_Soft_Reset (NSR): This bit indicates that when the HECI host controller is transitioning from D3hot to D0 due to power state command, it does not perform an internal reset. Configuration context is preserved: Reserved. Reserved Power State (PS): This field is used both to determine the current power state of the HECI host controller and to set a new power state. 00 = D0 state 11 = D3HOT state The D1 and D2 states are not supported for this HECI host controller. When in the D3HOT state, the configuration space is available, but the register memory spaces are not. Additionally, interrupts are blocked. 2 1:0 RO 0b RW 00b 312 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.19 MID— Message Signaled Interrupt Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 8C–8Dh 0005h RO 16 bits Bit 15:8 Access & Default RO 00h RO 05h Description Next Pointer (NEXT): This field indicates the next item in the list. This can be other capability pointers (such as PCI-X or PCI-Express) or it can be the last item in the list. Capability ID (CID): Capabilities ID indicates MSI. 7:0 9.2.20 MC— Message Signaled Interrupt Message Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 8E–8Fh 0080h RW, RO 16 bits Bit 15:8 7 6:4 3:1 0 Access & Default RO 00h RO 1b RO 000b RO 000b RW 0b Reserved Description 64 Bit Address Capable (C64): This bit specifies whether device is capable of generating 64-bit messages. Multiple Message Enable (MME): Not implemented, hardwired to 0. Multiple Message Capable (MMC): Not implemented, hardwired to 0. MSI Enable (MSIE): 0 = Disable 1 = Enable. MSI is enabled and traditional interrupt pins are not used to generate interrupts. Datasheet 313 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.21 MA— Message Signaled Interrupt Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 90–93h 00000000h RW, RO 32 bits Bit 31:2 Access & Default RW 00000000h Description Address (ADDR): This field provides the lower 32 bits of the system specified message address, always DWord aligned. MSI is not translated in Vtd, therefore, in order to avoid sending bad MSI with address bit [31:20] will be masked internally to generate 12'hFEE regardless of content in register. Register attribute remains as RW. 1:0 RO 00b Reserved 9.2.22 MUA— Message Signaled Interrupt Upper Address (Optional) B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 94–97h 00000000h RW 32 bits Bit 31:0 Access & Default RW 00000000h Description Upper Address (UADDR): Upper 32 bits of the system specified message address. This register is optional and only implemented if MC.C64=1. MSI is not translated in Vtd, therefore, in order to avoid sending bad MSI with address bit [3:0] will be masked internally to generate 4'h0 regardless of content in register. Register attribute remains as RW. 314 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.2.23 MD— Message Signaled Interrupt Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/1/PCI 98–99h 0000h RW 16 bits Bit 15:0 Access & Default RW 0000h Description Data (Data): This 16-bit field is programmed by system software if MSI is enabled. Its content is driven onto the FSB during the data phase of the MSI memory write transaction. 9.2.24 HIDM—HECI Interrupt Delivery Mode B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/3/1/PCI A0h 00h RW 8 bits 00h This register is used to select interrupt delivery mechanism for HECI to Host processor interrupts. Bit 7:2 1:0 Access & Default RO 0h RW 00b Reserved HECI Interrupt Delivery Mode (HIDM): These bits control what type of interrupt the HECI will send when ME FW writes to set the M_IG bit in AUX space. They are interpreted as follows: 00 = Generate Legacy or MSI interrupt 01 = Generate SCI 10 = Generate SMI Description Datasheet 315 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3 IDE Function for Remote Boot and Installations PT IDER Register Details (D3:F2) (Intel® 82Q35 and 82Q33 GMCH Only) Table 9-3. IDE Function for Remote Boot and Installations PT IDER Register Address Map Address Offset 00–3h 04–5h 06–7h 08h 09–Bh 0Ch 0Dh 0Eh 10–13h 14–17h 18–1Bh 1C–1Fh 20–23h 24–27h 2C–2Fh 30–33h 34h 3C–3Dh 3Eh 3Fh C8–C9h CA–CBh CC–CFh D0–D1h D2–D3h Register Symbol ID CMD STS RID CC CLS MLT HTYPE PCMDBA PCTLBA SCMDBA SCTLBA LBAR RSVD SS EROM CAP INTR MGNT MLAT PID PC PMCS MID MC Register Name Identification Command Register Device Status Revision ID Class Codes Cache Line Size Master Latency Timer Header Type Primary Command Block IO Bar Primary Control Block Base Address Secondary Command Block Base Address Secondary Control Block base Address Legacy Bus Master Base Address Reserved Sub System Identifiers Expansion ROM Base Address Capabilities Pointer Interrupt Information Minimum Grant Maximum Latency PCI Power Management Capability ID PCI Power Management Capabilities PCI Power Management Control and Status Message Signaled Interrupt Capability ID Message Signaled Interrupt Message Control Default Value 29C68086h 0000h 00B0h 00h 010185h 00h 00h 00h 00000001h 00000001h 00000001h 00000001h 00000001h 00000000h 00008086h 00000000h C8h 0300h 00h 00h D001h 0023h 00000000h 0005h 0080h Access RO RO, RW RO RO RO RO RO RO RO, RW RO, RW RO, RW RO, RW RO, RW RO RWO RO RO RW, RO RO RO RO RO RO, RW, RO/V RO RO, RW 316 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Address Offset D4–D7h D8–DBh DC–DDh Register Symbol MA MAU MD Register Name Message Signaled Interrupt Message Address Message Signaled Interrupt Message Upper Address Message Signaled Interrupt Message Data Default Value 00000000h 00000000h 0000h Access RO, RW RO, RW RW 9.3.1 ID—Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 00–03h 29C68086h RO 32 bits This register combined with the Device Identification register uniquely identifies any PCI device. Bit 31:16 15:0 Access & Default RO 29C6h RO 8086h Description Device ID (DID): Assigned by Manufacturer, identifies the type of Device. Vendor ID (VID): 16-bit field which indicates the company vendor as Intel. 9.3.2 CMD—Command Register B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 04–05h 0000h RO, RW 16 bits This register provides basic control over the device's ability to respond to and perform Host system related accesses. Note: Reset: Host System reset or D3->D0 transition of function. Datasheet 317 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Bit 15:11 10 Access & Default RO 00h RW 0b Reserved Description Interrupt Disable (ID): This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 0 = Enable. Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 1 = Disable. Internal INTx# messages will not be generated. 9 8 7 6 5 4 3 2 RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RW 0b Fast back-to-back enable (FBE): Reserved SERR# Enable (SEE): The PT function never generates an SERR#. This bit is reserved. Wait Cycle Enable (WCC): Reserved Parity Error Response Enable (PEE): No Parity detection in PT functions. This bit is reserved. VGA Palette Snooping Enable (VGA): Reserved Memory Write and Invalidate Enable (MWIE): Reserved Special Cycle enable (SCE): Reserved Bus Master Enable (BME): This bit controls the PT function's ability to act as a master for data transfers. This bit does not impact the generation of completions for split transaction commands. 0 = Disable 1 = Enable 1 0 RO 0b RW 0b Memory Space Enable (MSE): PT function does not contain target memory space. I/O Space enable (IOSE): This bit controls access to the PT function's target I/O space. 0 = Disable 1 = Enable 318 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.3 STS—Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 06–07h 00B0h RO 16 bits This register is used by the function to reflect its PCI status to the host for the functionality that it implements. Bit 15 14 13 12 11 10:9 8 Access & Default RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 1b RO 0b RO 1b RO 1b RO 0b Description Detected Parity Error (DPE): No parity error on its interface. Signaled System Error (SSE): The PT function will never generate an SERR#. Received Master-Abort Status (RMA): Reserved Received Target-Abort Status (RTA): Reserved Signaled Target-Abort Status (STA): The PT Function will never generate a target abort. This bit is reserved. DEVSEL# Timing Status (DEVT): Controls the device select time for the PT function's PCI interface. Master Data Parity Error Detected) (DPD): PT function (IDER), as a master, does not detect a parity error. Other PT function is not a master and hence this bit is reserved also. Fast back to back capable (RSVD): Reserved Reserved 66MHz capable (RSVD): Capabilities List (CL): This bit indicates that there is a capabilities pointer implemented in the device. Interrupt Status (IS): This bit reflects the state of the interrupt in the function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when this bit is a 1 and ID bit is 0 is the INTc interrupt asserted to the Host Reserved 7 6 5 4 3 2:0 RO 000b Datasheet 319 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.4 RID—Revision ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 08h 00h RO 8 bits This register specifies a device specific revision. Bit 7:0 Access & Default RO 00h Description Revision ID (RID): Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 9.3.5 CC—Class Codes B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 09–0Bh 010185h RO 24 bits This register identifies the basic functionality of the device (i.e., IDE mass storage). Bit 23:0 Access & Default RO 010185h Description Programming Interface BCC SCC (PI BCC SCC): 9.3.6 CLS—Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 0Ch 00h RO 8 bits This register defines the system cache line size in DWORD increments. This register is mandatory for master that use the Memory-Write and Invalidate command. Bit 7:0 Access & Default RO 00h Description Cache Line Size (CLS): All writes to system memory are memory writes. 320 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.7 MLT—Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 0Dh 00h RO 8 bits This register defines the minimum number of PCI clocks the bus master can retain ownership of the bus whenever it initiates new transactions. Bit 7:0 Access & Default RO 00h Description Master Latency Timer (MLT): Not implemented since the function is in (G)MCH. 9.3.8 HTYPE—Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 0Eh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Reserved Description Datasheet 321 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.9 PCMDBA—Primary Command Block IO Bar B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 10–13h 00000001h RO, RW 32 bits This 8-byte I/O space is used in Native Mode for the Primary Controller's Command Block (i.e., BAR0). Note: Reset: Host system Reset or D3->D0 transition of the function. Bit 31:16 15:3 2:1 0 Access & Default RO 0000h RW 0000h RO 00b RO 1b Reserved Base Address (BAR): This field provides the base address of the BAR0 I/O space (8 consecutive I/O locations) Reserved Resource Type Indicator (RTE): Indicates a request for I/O space. Description 9.3.10 PCTLBA—Primary Control Block Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 14–17h 00000001h RO, RW 32 bits This 4-byte I/O space is used in Native Mode for the Primary Controller's Control Block (i.e., BAR1). Note: Reset: Host system Reset or D3->D0 transition of the function. Bit 31:16 15:2 1 0 Access & Default RO 0000h RW 0000h RO 0b RO 1b Reserved Base Address (BAR): This field provides the base address of the BAR1 I/O space (4 consecutive I/O locations) Reserved Resource Type Indicator (RTE): Indicates a request for I/O space Description 322 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.11 SCMDBA—Secondary Command Block Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 18–1Bh 00000001h RO, RW 32 bits This 8-byte I/O space is used in Native Mode for the secondary Controller's Command Block. Secondary Channel is not implemented and reads return 7F7F7F7Fh and all writes are ignored. Note: Reset: Host System Reset or D3->D0 transition of the function. Bit 31:16 15:3 2:1 0 Access & Default RO 0000h RW 0000h RO 00b RO 1b Reserved Base Address (BAR): This field provides the base address of the I/O space (8 consecutive I/O locations) Reserved Resource Type Indicator (RTE): Indicates a request for I/O space Description 9.3.12 SCTLBA—Secondary Control Block base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 1C–1Fh 00000001h RO, RW 32 bits This 4-byte I/O space is used in Native Mode for Secondary Controller's Control block. Secondary Channel is not implemented and reads return 7F7F7F7Fh and all writes are ignored. Note: Reset: Host System Reset or D3->D0 transition. Bit 31:16 15:2 1 0 Access & Default RO 0000h RW 0000h RO 0b RO 1b Reserved Base Address (BAR): This field provides the base address of the I/O space (4 consecutive I/O locations) Reserved Resource Type Indicator (RTE): Indicates a request for I/O space Description Datasheet 323 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.13 LBAR—Legacy Bus Master Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 20–23h 00000001h RO, RW 32 bits This Bar is used to allocate I/O space for the SFF-8038i mode of operation (a.k.a. Bus Master IDE). Note: Reset: Host system Reset or D3->D0 transition. Bit 31:16 15:4 3:1 0 Access & Default RO 0000h RW 000h RO 000b RO 1b Reserved Description Base Address (BA): This field provides the base address of the I/O space (16 consecutive I/O locations). Reserved Resource Type Indicator (RTE): Indicates a request for I/O space. 324 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.14 SS—Sub System Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 2C–2Fh 00008086h RWO 32 bits These registers are used to uniquely identify the add-in card or the subsystem that the device resides within. Note: Reset: Host System Reset. Bit 31:16 15:0 Access & Default RWO 0000h RWO 8086h Description Subsystem ID (SSID): This field is written by BIOS. No hardware action taken on this value. Subsystem Vendor ID (SSVID): This field is written by BIOS. No hardware action taken on this value. 9.3.15 EROM—Expansion ROM Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 30–33h 00000000h RO 32 bits This optional register is not implemented. Bit 31:11 10:1 0 Access & Default RO 000000h RO 000h RO 0b Description Expansion ROM Base Address (ERBAR): Reserved Enable (EN): Enable expansion ROM Access Datasheet 325 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.16 CAP—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 34h C8h RO 8 bits This optional register is used to point to a linked list of new capabilities implemented by the device. Bit 7:0 Access & Default RO C8h Description Capability Pointer (CP): This field indicates that the first capability pointer offset is offset C8h ( the power management capability) 9.3.17 INTR—Interrupt Information B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 3C–3Dh 0300h RW, RO 16 bits See definitions in the registers below. Note: Reset: Host System Reset or D3->D0 reset of the function. Bit 15:8 Access & Default RO 03h Description Interrupt Pin (IPIN): a value of 0x1/0x2/0x3/0x4 indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively Function (2 IDE) Value 03h INTx INTC 7:0 RW 00h Interrupt Line (ILINE): The value written in this register indicates which input of the system interrupt controller, the device's interrupt pin is connected. This value is used by the OS and the device driver, and has no affect on the hardware. 326 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.18 MGNT—Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 3Eh 00h RO 8 bits This optional register is not implemented. Bit 7:0 Access & Default RO 00h Reserved Description 9.3.19 MLAT—Maximum Latency B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI 3Fh 00h RO 8 bits This optional register is not implemented. Bit 7:0 Access & Default RO 00h Reserved Description 9.3.20 PID—PCI Power Management Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: See register definitions below Bit 15:8 7:0 Access & Default RO D0h RO 01h Description Next Capability (NEXT): The value of D0h points to the MSI capability. Cap ID (CID): Indicates that this pointer is a PCI power management. 0/3/2/PCI C8–C9h D001h RO 16 bits Datasheet 327 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.21 PC—PCI Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI CA–CBh 0023h RO 16 bits This register implements the power management capabilities of the function. Bit 15:11 10 9 8:6 5 4 3 2:0 Access & Default RO 00000b RO 0b RO 0b RO 000b RO 1b RO 0b RO 0b RO 011b Description PME Support (PME): Indicates no PME# in the PT function. D2 Support (D2S): The D2 state is not Supported. D1 Support (D1S): The D1 state is not supported. Aux Current (AUXC): PME# from D3 (cold) state is not supported, therefore this field is 000b. Device Specific Initialization (DSI): Indicates that no devicespecific initialization is required. Reserved PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#. Version (VS): Indicates support for revision 1.2 of the PCI power management specification. 9.3.22 PMCS—PCI Power Management Control and Status B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/3/2/PCI CC–CFh 00000000h RO, RW, RO/V 32 bits 0000h This register implements the PCI PM Control and Status Register to allow PM state transitions and Wake up. Note the NSR bit of this register. All registers (PCI configuration and Device Specific) marked with D3->D0 transition reset will only do so if this bit reads a 0. If this bit is a 1, the D3->D0 transition will not reset the registers. Note: Reset: Host System Reset or D3->D0 transition. 328 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Bit 31:16 15 14:9 8 7:4 3 Access & Default RO 0h RO 0b RO 00h RO 0b RO 0000b RO/V 0b Reserved Description PME Status (PMES): Not supported. Reserved PME Enable (PMEE): Not Supported Reserved No Soft Reset (NSR): 1 = Indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. 0 = Devices do perform an internal reset upon transitioning from D3hot to D0 via software control of the PowerState bits. Configuration Context is lost when performing the soft reset. Upon transition from the D3hot to the D0 state, full re-initialization sequence is needed to return the device to D0 Initialized. When this bit is 0, device performs internal reset. When this bit is 1, Device does not perform internal reset. 2 1:0 RO 0b RW 00b Reserved Power State (PS): This field is used both to determine the current power state of the PT function and to set a new power state. The values are: 00 = D0 state 11 = D3HOT state When in the D3HOT state, the controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. If software attempts to write a 10 or 01 to these bits, the write will be ignored. Datasheet 329 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.23 MID—Message Signaled Interrupt Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI D0–D1h 0005h RO 16 bits Message Signaled Interrupt is a feature that allows the device/function to generate an interrupt to the host by performing a DWORD memory write to a system specified address with system specified data. This register is used to identify and configure an MSI capable device. Bit 15:8 7:0 Access & Default RO 00h RO 05h Description Next Pointer (NEXT): Value indicates this is the last item in the capabilities list. Capability ID (CID): Capabilities ID value indicates device is capable of generating an MSI. 9.3.24 MC—Message Signaled Interrupt Message Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI D2–D3h 0080h RO, RW 16 bits This register provides System Software control over MSI. Note: Reset: Host System Reset or D3->D0 transition. Bit 15:8 7 6:4 3:1 0 Access & Default RO 00h RO 1b RW 000b RO 000b RW 0b Reserved Description 64 Bit Address Capable (C64): Capable of generating 64-bit and 32bit messages Multiple Message Enable (MME): These bits are R/W for software compatibility, but only one message is ever sent by the PT function Multiple Message Capable (MMC): Only one message is required MSI Enable (MSIE): If set MSI is enabled and traditional interrupt pins are not used to generate interrupts 330 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.25 MA—Message Signaled Interrupt Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI D4–D7h 00000000h RO, RW 32 bits This register specifies the DWord aligned address programmed by system software for sending MSI. Note: Reset: Host system Reset or D3->D0 transition. Bit 31:2 Access & Default RW 00000000h Description Address (ADDR): Lower 32 bits of the system specified message address, always DWORD aligned Force host MSI address to 0_FEEx_XXXXh before sending to backbone, regardless of values programmed in MA and MUA registers under respective PCI Configuration Space. Note that the MA and MUA registers should continued to be RW (no change to registers implementation, just hardcode 0_FEEh as bit[35:20] for MSI cycles to backbone). 1:0 RO 00b Reserved 9.3.26 MAU—Message Signaled Interrupt Message Upper Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI D8–DBh 00000000h RO, RW 32 bits This register provides the upper 32 bits of the message address for the 64bit address capable device. Note: Reset: Host system Reset or D3->D0 transition. Bit 31:4 3:0 Access & Default RO 0000000h RW 0000b Reserved Description Address (ADDR): Upper 4 bits of the system specified message address Datasheet 331 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.3.27 MD—Message Signaled Interrupt Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/2/PCI DC–DDh 0000h RW 16 bits This 16-bit field is programmed by system software if MSI is enabled. Note: Reset: Host system Reset or D3->D0 transition. Bit 15:0 Access & Default RW 0000h Description Data (DATA): This content is driven onto the lower word of the data bus of the MSI memory write transaction 332 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4 Serial Port for Remote Keyboard and Text KT Redirection Register Details (D3:F3) (Intel® 82Q35 and 82Q33 GMCH Only) Table 9-4. Serial Port for Remote Keyboard and Text KT Redirection Register Address Map Address Offset 00–03h 04–05h 06–07h 08h 09–0Bh 0Ch 0Dh 0Eh 10–13h 14–17h 2C–2Fh 30–33h 34h 3C–3Dh 3Eh 3Fh C8–C9h CA–CBh CC–CFh D0–D1h D2–D3h D4–D7h D8–DBh DC–DDh Register Symbol ID CMD STS RID CC CLS MLT HTYPE KTIBA KTMBA SS EROM CAP INTR MGNT MLAT PID PC PMCS MID MC MA MAU MD Register Name Identification Command Register Device Status Revision ID Class Codes Cache Line Size Master Latency Timer Header Type KT IO Block Base Address KT Memory Block Base Address Sub System Identifiers Expansion ROM Base Address Capabilities Pointer Interrupt Information Minimum Grant Maximum Latency PCI Power Management Capability ID PCI Power Management Capabilities PCI Power Management Control and Status Message Signaled Interrupt Capability ID Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Message Upper Address Message Signaled Interrupt Message Data Default Value 29C78086h 0000h 00B0h 00h 070002h 00h 00h 00h 00000001h 00000000h 00008086h 00000000h C8h 0200h 00h 00h D001h 0023h 00000000h 0005h 0080h 00000000h 00000000h 0000h Access RO RO, RW RO RO RO RO RO RO RO, RW RO, RW RWO RO RO RW, RO RO RO RO RO RO/V, RO, RW RO RO, RW RO, RW RO, RW RW Datasheet 333 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.1 ID—Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 00-03h 29C78086h RO 32 bits This register combined with the Device Identification register uniquely identifies any PCI device. Bit 31:16 15:0 Access & Default RO 29C7h RO 8086h Description Device ID (DID): Assigned by manufacturer, identifies the device Vendor ID (VID): 16-bit field which indicates the company vendor as Intel 9.4.2 CMD—Command Register B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 04-05h 0000h RO, RW 16 bits This register provides basic control over the device's ability to respond to and perform Host system related accesses. Note: Reset: Host System reset or D3->D0 transition. Bit 15:11 10 Access & Default RO 00h RW 0b Reserved Description Interrupt Disable (ID): This bit disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 0 = Enable. Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 1 = Disable. Internal INTx# messages will not be generated. 9 8 7 RO 0b RO 0b RO 0b Fast back-to-back enable (FBE): Reserved SERR# Enable (SEE): The PT function never generates an SERR#. This bit is Reserved. Wait Cycle Enable (WCC): Reserved 334 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Bit 6 5 4 3 2 Access & Default RO 0b RO 0b RO 0b RO 0b RW 0b Description Parity Error Response Enable (PEE): No Parity detection in PT functions. This bit is Reserved. VGA Palette Snooping Enable (VGA): Reserved Memory Write and Invalidate Enable (MWIE): Reserved Special Cycle enable (SCE): Reserved Bus Master Enable (BME): Controls the KT function's ability to act as a master for data transfers. This bit does not impact the generation of completions for split transaction commands. For KT, the only bus mastering activity is MSI generation. 0 = Disable 1 = Enable 1 RW 0b Memory Space Enable (MSE): This bit controls Access to the PT function's target memory space. 0 = Disable 1 = Enable 0 RW 0b I/O Space enable (IOSE): This bit controls access to the PT function's target I/O space. 0 = Disable 1 = Enable Datasheet 335 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.3 STS—Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 06-07h 00B0h RO 16 bits This register is used by the function to reflect its PCI status to the host for the functionality that it implements. Bit 15 14 13 12 11 10:9 8 Access & Default RO 0b RO 0b RO 0b RO 0b RO 0b RO 00b RO 0b RO 1b RO 0b RO 1b RO 1b RO 0b Description Detected Parity Error (DPE): No parity error on its interface Signaled System Error (SSE): The PT function will never generate a SERR#. Received Master-Abort Status (RMA): Reserved Received Target-Abort Status (RTA): Reserved Signaled Target-Abort Status (STA): The PT Function will never generate a target abort. This bit is Reserved. DEVSEL# Timing Status (DEVT): Controls the device select time for the PT function's PCI interface. Master Data Parity Error Detected) (DPD): PT function (IDER), as a master, does not detect a parity error. Other PT function is not a master and hence this bit is reserved. Fast back to back capable (FB2B): Reserved Reserved 66MHz capable (RSVD): Capabilities List (CL): Indicates that there is a capabilities pointer implemented in the device. Interrupt Status (IS): This bit reflects the state of the interrupt in the function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when this bit is a 1 and ID bit is 0 is the INTB interrupt asserted to the Host. Reserved 7 6 5 4 3 2:0 RO 000b 336 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.4 RID—Revision ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 08h 00h RO 8 bits This register specifies a device specific revision. Bit 7:0 Access & Default RO 00h Description Revision ID (RID): Indicates stepping of the silicon. Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 9.4.5 CC—Class Codes B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 09-0Bh 070002h RO 24 bits This register identifies the basic functionality of the device i.e. Serial Com Port. Bit 23:0 Access & Default RO 070002h Description Programming Interface BCC SCC (PI BCC SCC): 9.4.6 CLS—Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 0Ch 00h RO 8 bits This register defines the system cache line size in DWORD increments. This register is mandatory for master that uses the Memory-Write and Invalidate command. Bit 7:0 Access & Default RO 00h Description Cache Line Size (CLS): All writes to system memory are Memory Writes. Datasheet 337 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.7 MLT—Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 0Dh 00h RO 8 bits This register defines the minimum number of PCI clocks the bus master can retain ownership of the bus whenever it initiates new transactions. Bit 7:0 Access & Default RO 00h Description Master Latency Timer (MLT): Not implemented since the function is in (G)MCH. 9.4.8 HTYPE—Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 0Eh 00h RO 8 bits Bit 7:0 Access & Default RO 00h Reserved Description 338 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.9 KTIBA—KT IO Block Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 10–13h 00000001h RO, RW 32 bits This register provides the base address for the 8-byte I/O space for KT. Note: Reset: Host system Reset or D3->D0 transition. Bit 31:16 15:3 2:1 0 Access & Default RO 0000h RW 0000h RO 00b RO 1b Reserved Base Address (BAR): This field provides the base address of the I/O space (8 consecutive I/O locations) Reserved Resource Type Indicator (RTE): Indicates a request for I/O space Description 9.4.10 KTMBA—KT Memory Block Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 14–17h 00000000h RO, RW 32 bits This register provides the base address of memory-mapped space. Note: Reset: Host system Reset or D3->D0 transition. Bit 31:12 11:4 3 2:1 0 Access & Default RW 00000h RO 00h RO 0b RO 00b RO 0b Description Base Address (BAR): This field provides the base address of the memory-mapped IO BAR Reserved Prefetchable (PF): Indicates that this range is not pre-fetchable. Type (TP): Indicates that this range can be mapped anywhere in 32bit address space. Resource Type Indicator (RTE): Indicates a request for register memory space. Datasheet 339 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.11 SS—Sub System Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 2C–2Fh 00008086h RWO 32 bits This registers are used to uniquely identify the add-in card or the subsystem that the device resides within. Note: Reset: Host system Reset. Bit 31:16 15:0 Access & Default RWO 0000h RWO 8086h Description Subsystem ID (SSID): This is written by BIOS. No hardware action taken on this value. Subsystem Vendor ID (SSVID): This is written by BIOS. No hardware action taken on this value. 340 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.12 EROM—Expansion ROM Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 30–33h 00000000h RO 32 bits This optional register is not implemented. Bit 31:11 10:1 0 Access & Default RO 000000h RO 000h RO 0b Description Expansion ROM Base Address (ERBAR): Reserved Enable (EN): Enable expansion ROM Access 9.4.13 CAP—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 34h C8h RO 8 bits This optional register is used to point to a linked list of new capabilities implemented by the device. Bit 7:0 Access & Default RO C8h Description Capability Pointer (CP): This field indicates that the first capability pointer offset is offset c8h ( the power management capability) Datasheet 341 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.14 INTR—Interrupt Information B/D/F/Type: Address Offset: Default Value: Access: Size: See individual Registers below. 0/3/3/PCI 3C–3Dh 0200h RW, RO 16 bits Note: Reset: Host System Reset or D3->D0 reset of the function. Bit 15:8 Access & Default RO 02h Description Interrupt Pin (IPIN): a value of 0x1/0x2/0x3/0x4 indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively Function ( 3 KT/Serial Port) Value 02h INTx INTB 7:0 RW 00h Interrupt Line (ILINE): The value written in this field indicates which input of the system interrupt controller, the device's interrupt pin is connected to. This value is used by the OS and the device driver, and has no affect on the hardware. 9.4.15 MGNT—Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 3Eh 00h RO 8 bits This optional register is not implemented. Bit 7:0 Access & Default RO 00h Reserved Description 342 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.16 MLAT—Maximum Latency B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI 3Fh 00h RO 8 bits This optional register is not implemented. Bit 7:0 Access & Default RO 00h Reserved Description 9.4.17 PID—PCI Power Management Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: See register definitions below. 0/3/3/PCI C8–C9h D001h RO 16 bits Bit 15:8 7:0 Access & Default RO D0h RO 01h Description Next Capability (NEXT): The value of D0h points to the MSI capability Cap ID (CID): This field indicates that this pointer is a PCI power management Datasheet 343 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.18 PC—PCI Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI CA–CBh 0023h RO 16 bits This register implements the power management capabilities of the function. Bit 15:11 10 9 8:6 5 4 3 2:0 Access & Default RO 00000b RO 0b RO 0b RO 000b RO 1b RO 0b RO 0b RO 011b Description PME Support (PME): Indicates no PME# in the PT function. D2 Support (D2S): The D2 state is not Supported. D1 Support (D1S): The D1 state is not supported. Aux Current (AUXC): PME# from D3 (cold) state is not supported; therefore, this field is 000b. Device Specific Initialization (DSI): Indicates that no devicespecific initialization is required. Reserved PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#. Version (VS): Indicates support for revision 1.2 of the PCI power management specification. 344 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.19 PMCS—PCI Power Management Control and Status B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/3/3/PCI CC–CFh 00000000h RO/V, RO, RW 32 bits 0000h This register implements the PCI PM Control and Status Register to allow PM state transitions and Wake up. Note: Note the NSR bit of this register. All registers (PCI configuration and Device Specific) marked with D3->D0 transition reset will only do so if this bit reads a 0. If this bit is a 1, the D3->D0 transition will not reset the registers. Note: Reset: Host System Reset or D3->D0 transition. Bit 31:16 15 14:9 8 7:4 3 Access & Default RO 0h RO 0b RO 00h RO 0b RO 0h RO/V 0b Reserved Description PME Status (PMES): This bit is set when a PME event is to be requested. Not supported Reserved PME Enable (PMEE): Not Supported Reserved No Soft Reset (NSR): 1 = Indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. 0 = Devices do perform an internal reset upon transitioning from D3hot to D0 via software control of the PowerState bits. Configuration Context is lost when performing the soft reset. Upon transition from the D3hot to the D0 state, full re-initialization sequence is needed to return the device to D0 Initialized. When this bit is 0, device performs internal reset. When this bit is 1, device does not perform internal reset. 2 RO 0b Reserved Datasheet 345 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Bit 1:0 Access & Default RW 00b Description Power State (PS): This field is used both to determine the current power state of the PT function and to set a new power state. 00 = D0 state 11 = D3HOT state When in the D3HOT state, the controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. If software attempts to write a 10 or 01 to these bits, the write will be ignored. 9.4.20 MID—Message Signaled Interrupt Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI D0–D1h 0005h RO 16 bits Message Signaled Interrupt is a feature that allows the device/function to generate an interrupt to the host by performing a DWORD memory write to a system specified address with system specified data. This register is used to identify and configure an MSI capable device. Bit 15:8 7:0 Access & Default RO 00h RO 05h Description Next Pointer (NEXT): Value indicates this is the last item in the list. Capability ID (CID): value of Capabilities ID indicates device is capable of generating MSI. 346 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.21 MC—Message Signaled Interrupt Message Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI D2–D3h 0080h RO, RW 16 bits This register provides System Software control over MSI. Note: Reset: Host System Reset or D3->D0 transition. Bit 15:8 7 6:4 3:1 0 Access & Default RO 00h RO 1b RW 000b RO 000b RW 0b Reserved Description 64 Bit Address Capable (C64): Capable of generating 64-bit and 32bit messages. Multiple Message Enable (MME): These bits are R/W for software compatibility, but only one message is ever sent by the PT function. Multiple Message Capable (MMC): Only one message is required. MSI Enable (MSIE): 0 = Disable. 1 = Enable. Traditional interrupt pins are not used to generate interrupts. Datasheet 347 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.22 MA—Message Signaled Interrupt Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI D4–D7h 00000000h RO, RW 32 bits This register specifies the DWord aligned address programmed by system software for sending MSI. Note: Reset: Host system Reset or D3->D0 transition. Bit 31:2 Access & Default RW 00000000h Description Address (ADDR): This field provides the lower 32 bits of the system specified message address, always DWord aligned. Force host MSI address to 0_FEEx_XXXXh before sending to backbone, regardless of values programmed in MA and MUA registers under respective PCI Configuration Space. Note that the MA and MUA registers should continued to be RW (no change to registers implementation, just hardcode 0_FEE as bit[35:20] for MSI cycles to backbone). 1:0 RO 00b Reserved 9.4.23 MAU—Message Signaled Interrupt Message Upper Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI D8–DBh 00000000h RO, RW 32 bits This register provides the upper 32 bits of the message address for the 64bit address capable device. Note: Reset: Host system Reset or D3->D0 transition. Bit 31:4 3:0 Access & Default RO 0000000h RW 0000b Reserved Description Address (ADDR): This field provides the upper 4 bits of the system specified message address. 348 Datasheet Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 9.4.24 MD—Message Signaled Interrupt Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/PCI DC–DDh 0000h RW 16 bits This 16-bit field is programmed by system software if MSI is enabled. Note: Reset: Host system Reset or D3->D0 transition. Bit 15:0 Access & Default RW 0000h Description Data (DATA): This MSI data is driven onto the lower word of the data bus of the MSI memory write transaction. Datasheet 349 Functional Description 10 10.1 Functional Description Host Interface The (G)MCH supports the Intel® Core™2 Duo desktop processor subset of the Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous transfer is used for the address and data signals. The address signals are double pumped and a new address can be generated every other bus clock. At 200/267/333 MHz bus clock the address signals run at 667 MT/s. The data is quad pumped and an entire 64B cache line can be transferred in two bus clocks. At 200/266/333 MHz bus clock, the data signals run at 800/1066/1333 MT/s for a maximum bandwidth of 6.4/8.5/10.6 GB/s. 10.1.1 FSB IOQ Depth The Scalable Bus supports up to 12 simultaneous outstanding transactions. 10.1.2 FSB OOQ Depth The (G)MCH supports only one outstanding deferred transaction on the FSB. 10.1.3 FSB GTL+ Termination The (G)MCH integrates GTL+ termination resistors on die. 10.1.4 FSB Dynamic Bus Inversion The (G)MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from the processor. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase. This decreases the worst-case power consumption of the (G)MCH. FSB_DINVB_3:0 indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase. FSB_DINVB_3:0 FSB_DINVB_0 FSB_DINVB_1 FSB_DINVB_2 FSB_DINVB_3 Data Bits FSB_DB_15:0 FSB_DB_31:16 FSB_DB_47:32 FSB_DB_63:48 350 Datasheet Functional Description When the processor or the (G)MCH drives data, each 16-bit segment is analyzed. If more than 8 of the 16 signals would normally be driven low on the bus, the corresponding HDINV# signal will be asserted, and the data will be inverted prior to being driven on the bus. Whenever the processor or the (G)MCH receives data, it monitors FSB_DINVB_3:0 to determine if the corresponding data segment should be inverted. 10.1.4.1 APIC Cluster Mode Support APIC Cluster mode support is required for backwards compatibility with existing software, including various operating systems. As one example, beginning with Microsoft Windows 2000, there is a mode (boot.ini) that allows an end user to enable the use of cluster addressing support of the APIC. • The (G)MCH supports three types of interrupt re-direction: ⎯ Physical ⎯ Flat-Logical ⎯ Clustered-Logical Datasheet 351 Functional Description 10.2 System Memory Controller The 82G33 GMCH and 82P35 MCH system memory controllers support both DDR2 and DDR3 protocols with two independent 64 bit wide channels; each accessing one or two DIMMs. The (G)MCH supports a maximum of two un-buffered, non-ECC DDR2 or DDR3 DIMMs per channel; thus, allowing up to four device ranks per channel. The 82Q35 GMCH and 82Q33 GMCH only support DDR2. Note: References in this section to DDR3 are for the 82G33 GMCH and 82P35 only. 10.2.1 System Memory Organization Modes The system memory controller supports three memory organization modes, Single Channel, Dual Channel Symmetric, and Dual Channel Asymmetric. 10.2.2 Single Channel Mode In this mode, all memory cycles are directed to a single channel. Single channel mode is used when either Channel A or Channel B DIMMs are populated in any order, but not both. 10.2.3 Dual Channel Symmetric Mode This mode provides maximum performance on real applications. Addresses are pingponged between the channels after each cache line (64 byte boundary). If there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned. If two consecutive cache lines are requested, both may be retrieved simultaneously, since they are ensured to be on opposite channels. Dual channel symmetric mode is used when both Channel A and Channel B DIMMs are populated in any order with the total amount of memory in each channel being the same, but the DRAM device technology and width may vary from one channel to the other. Table 10-1 is a sample dual channel symmetric memory configuration showing the rank organization. 352 Datasheet Functional Description Table 10-1. Sample System Memory Dual Channel Symmetric Organization Mode with Intel® Flex Memory Mode Enabled Rank Channel 0 population 0 MB 256 MB 512 MB 512 MB Cumulative top address in Channel 0 2560 MB 2560 MB 2048 MB 1024 MB Channel 1 population 0 MB 256 MB 512 MB 512 MB Cumulative top address in Channel 1 2560 MB 2560 MB 2048 MB 1024 MB Rank 3 Rank 2 Rank 1 Rank 0 10.2.4 Dual Channel Asymmetric Mode with Intel® Flex Memory Mode Enabled This mode trades performance for system design flexibility. Unlike the previous mode, addresses start in channel 0 and stay there until the end of the highest rank in channel 0, and then addresses continue from the bottom of channel 1 to the top. Normal applications are unlikely to make requests that alternate between addresses that are on opposite channels with this memory organization; so, in most cases, bandwidth will be limited to that of a single channel. Dual channel asymmetric mode is used when both Channel A and Channel B DIMMs are populated in any order with the total amount of memory in each channel being different. Table 10-2 is a sample dual channel asymmetric memory configuration showing the rank organization: Table 10-2. Sample System Memory Dual Channel Asymmetric Organization Mode with Intel® Flex Memory Mode Disabled Rank Channel 0 population 0 MB 256 MB 512 MB 512 MB Cumulative top address in Channel 0 1280 MB 1280 MB 1024 MB 512 MB Channel 1 population 0 MB 0 MB 512 MB 512 MB Cumulative top address in Channel 1 2304 MB 2304 MB 2304 MB 1792 MB Rank 3 Rank 2 Rank 1 Rank 0 Datasheet 353 Functional Description 10.2.5 System Memory Technology Supported The (G)MCH supports the following DDR2 and DDR3 Data Transfer Rates, DIMM Modules, and DRAM Device Technologies: • DDR2 Data Transfer Rates: 667 (PC2-5300) and 800 (PC2-6400) • DDR3 Data Transfer Rates: 800 (PC3-6400) and 1066 (PC3-8500) • DDR2 DIMM Modules: ⎯ Raw Card C - Single Sided x16 un-buffered non-ECC ⎯ Raw Card D - Single Sided x8 un-buffered non-ECC ⎯ Raw Card E - Double Sided x8 un-buffered non-ECC • DDR3 DIMM Modules: ⎯ Raw Card A - Single Sided x8 un-buffered non-ECC ⎯ Raw Card B - Double Sided x8 un-buffered non-ECC ⎯ Raw Card C - Single Sided x16 un-buffered non-ECC ⎯ Raw Card F - Double Sided x16 un-buffered non-ECC • DDR2 and DDR3 DRAM Device Technology: 512 MB and 1 GB Table 10-3 Supported DIMM Module Configurations Memory Type Raw Card Version DIMM Capacity DRAM Device Technology DRAM Organization # of DRAM Devices # of Physical Device Ranks # of Row/Col Address Bits # of Banks Inside DRAM Page Size C DDR2 667 and 800 D 256 MB 512 MB 512 MB 1 GB 1 GB 2 GB 512 MB 1 GB 1 GB 2 GB 256 MB 512 MB 512 MB 1 GB 512 Mb 1 Gb 512 Mb 1 Gb 512 Mb 1 Gb 512 Mb 1 Gb 512 Mb 1 Gb 512 Mb 1 Gb 512 Mb 1 Gb 32M X 16 64M X 16 64M X 8 128M X 8 64M X 8 128M X 8 64M X 8 128M X 8 64M X 8 128M X 8 32M X 16 64M X 16 32M X 16 64M X 16 4 4 8 8 16 16 8 8 16 16 4 4 8 8 1 1 1 1 2 2 1 1 2 2 1 1 2 2 13/10 13/10 14/10 14/10 14/10 14/10 13/10 14/10 13/10 14/10 12/10 13/10 12/10 13/10 4 8 4 8 4 8 8 8 8 8 8 8 8 8 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K E A DDR3 800 and 1066 B C F 354 Datasheet Functional Description 10.3 PCI Express* See Section 1.3.4 for list of PCI Express features, and the PCI Express specification for further details. This (G)MCH is part of a PCI Express root complex. This means it connects a host processor/memory subsystem to a PCI Express hierarchy. The control registers for this functionality are located in device 1 configuration space and two Root Complex Register Blocks (RCRBs). The DMI RCRB contains registers for control of the ICH9 attach ports. 10.3.1 PCI Express* Architecture The PCI Express architecture is specified in layers. Compatibility with the PCI addressing model (a load-store architecture with a flat address space) is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification. The initial speed of 1.25 GHz (250 MHz internally) results in 2.5 GB/s/direction which provides a 250 MB/s communications channel in each direction (500 MB/s total) that is close to twice the data rate of classic PCI per lane. 10.3.2 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer’s primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs. 10.3.3 Data Link Layer The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link management, error detection, and error correction. 10.3.4 Physical Layer The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry. Datasheet 355 Functional Description 10.4 Intel® Serial Digital Video Output (SDVO) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) The SDVO signals on the GMCH are multiplexed with the PCI Express x16 port pins. The Intel® SDVO Port is the second generation of digital video output from compliant Intel® GMCHs. The electrical interface is based on the PCI Express interface, though the protocol and timings are completely unique. Whereas PCI Express runs at a fixed frequency, the frequency of the SDVO interface is dependant upon the active display resolution and timing. The port can be dynamically configured in several modes to support display configurations. Essentially, an SDVO port will transmit display data in a high speed, serial format across differential AC coupled signals. An SDVO port consists of a sideband differential clock pair and a number of differential data pairs. 10.4.1 Intel® SDVO Capabilities SDVO ports can support a variety of display types including LVDS, DVI, Analog CRT, TV-Out and external CE type devices. The GMCH uses an external SDVO device to translate from SDVO protocol and timings to the desired display format and timings. The Internal Graphics Controller can have one or two SDVO ports multiplexed on the x16 PCI Express interface. When an external x16 PCI Express graphics accelerator is not in use, an ADD2 card may be plugged into the x16 connector or if a x16 slot is not present, the SDVO(s) may be located ‘down’ on the motherboard to access the multiplexed SDVO ports and provide a variety of digital display options. The ADD2/Media Expansion card is designed to fit in a x16 PCI Express connector. The ADD2/Media Expansion card can support one or two devices. If a single channel SDVO device is used, it should be attached to the channel B SDVO pins. The ADD2 card can support two separate SDVO devices when the interface is in Dual Independent or Dual Simultaneous Standard modes. The Media Expansion card adds Video in capabilities. The SDVO port defines a two-wire point-to-point communication path between the SDVO device and GMCH. The SDVO control clock and data provide similar functionality to I2C. However unlike I2C, this interface is intended to be point-to-point (from the GMCH to the SDVO device) and requires the SDVO device to act as a switch and direct traffic from the SDVO control bus to the appropriate receiver. Additionally, this control bus will be able to run at faster speeds (up to 1 MHz) than a traditional I2C interface would. 356 Datasheet Functional Description Figure 10-1. sDVO Conceptual Block Diagram Analog RGB Monitor Control Clock Control Data TV Clock In Stall Interrupt PCI Express x16 Port Pins 3rd Party SDVO External Device(s) Digital Display Device(s) or TV SDVO Port C Internal Graphics ClockC RedC / AlphaB GreenC BlueC ClockB RedB GreenB BlueB GMCH SDVO Port B PCI Express* Logic SDVO_BlkDia 10.4.2 Intel® SDVO Modes The port can be dynamically configured in several modes: • Standard. This mode provides baseline SDVO functionality. It supports Pixel Rates between 25 MP/s and 225 MP/s. It uses three data pairs to transfer RGB data. • Dual Standard. This mode uses Standard data streams across both SDVOB and SDVOC. Both channels can only run in Standard mode (3 data pairs) and each channel supports Pixel Rates between 25 MP/s and 225 MP/s. ⎯ Dual Independent Standard. In Dual Independent Standard mode, each SDVO channel sees a different pixel stream. The data stream across SDVOB is not the same as the data stream across SDVOC. ⎯ Dual Simultaneous Standard. In Dual Simultaneous Standard mode, both SDVO channels see the same pixel stream. The data stream across SDVOB is the same as the data stream across SDVOC. The display timings will be identical, but the transfer timings may not be (i.e., SDVOB clocks and data may not be perfectly aligned with SDVOC clock and data as seen at the SDVO device(s)). Since this mode uses just a single data stream, it uses a single pixel pipeline within the GMCH. Datasheet 357 Functional Description 10.4.3 PCI Express* and Internal Graphics Simultaneous Operation Standard PCI Express* Cards and Internal Graphics BIOS control of simultaneous operation is needed to ensure the PCI Express is configured appropriately. 10.4.3.1 10.4.3.2 Media Expansion Cards (Concurrent SDVO and PCI Express*) SDVO lane reversal is supported in the (G)MCH. This functionality allows current SDVO ADD2 cards to work in current ATX and BTX systems instead of requiring a separate card. The GMCH allows SDVO and PCI Express to operate concurrently on the PCI Express Port. The card, which plugs into the x16 connector in this case, is called a Media Expansion card. It uses 4 or 8 lanes for SDVO and up to 8 lanes of standard PCI Express. For the GMCH, the only supported PCI Express width when SDVO is present is x1. This concurrency is supported in reversed and non-reversed configurations. Mirroring / Reversing is always about the axis. Table 10-4. Concurrent SDVO / PCI Express* Configuration Strap Controls Configuration # 1 2 3 4 5 Slot Reversed Strap — Yes — Yes — SDVO Present Strap — — Yes Yes Yes SDVO/PCI Express* Concurrent Strap — — — — Yes Description PCI Express* not reversed PCI Express* Reversed SDVO (ADD2) not reversed SDVO (ADD2) Reversed SDVO & PCI Express* (MEDIA EXPANSION) not reversed SDVO & PCI Express* (MEDIA EXPANSION) Reversed 6 Yes Yes Yes Notes: 1. 2. The Configuration #s refer to the following figures (no intentional relation to validation configurations). Configurations 4, 5, and 6 (required addition of SDVO/PCI Express* Concurrent Strap). 358 Datasheet Functional Description Figure 10-2. Concurrent savon / PCI Express* Non-Reversed Configurations GMCH PEG Signals 0 GMCH PEG Pins 0 x1 PCIe Card Not Reversed 1 3 5 0 0 x4 sDVO (ADD2) Card x8 sDVO (ADD2) Card 0 PCIe Lane 0 PCIe PCIe Lane N 0 PCI Express x16 Connector PCI Express x16 Connector PCI Express x16 Connector 15 Video In x16 PCIe Card MEC Card sDVO Lane 7 sDVO sDVO Lane 0 Video Out 15 15 15 15 SDVO-Conc-PCIe_Non-Reversed_Config Figure 10-3. Concurrent SDVO / PCI Express* Reversed Configurations GMCH GMCH PEG PEG Signals Pins 15 0 2 4 6 15 15 sDVO Lane 0 sDVO sDVO Lane 7 MEC Card 15 PCI Express x16 Connector PCI Express x16 Connector PCI Express x16 Connector 0 Video Out Reversed x16 PCIe Card x8 sDVO (ADD2) Card x4 sDVO (ADD2) Card 0 PCIe Lane N PCIe PCIe Lane 0 x1 PCIe Card 0 15 Video In 0 0 SDVO-Conc-PCIe_Reversed_Config Datasheet 359 Functional Description 10.5 Integrated Graphics Controller (Intel® 82Q35, 82Q33, 82G33 GMCH Only) The major components in the Integrated Graphics Device (IGD) are the engines, planes, pipes, and ports. The GMCH has a 3D/2D instruction processing unit to control the 3D and 2D engines. The IGD’s 3D and 2D engines are fed with data through the memory controller. The output of the engines are surfaces sent to memory that are then retrieved and processed by the GMCH planes. The GMCH contains a variety of planes, such as display, overlay, cursor and VGA. A plane consists of rectangular shaped image that has characteristics such as source, size, position, method, and format. These planes get attached to source surfaces that are rectangular memory surfaces with a similar set of characteristics. They are also associated with a particular destination pipe. A pipe consists of a set of combined planes and a timing generator. The GMCH has two independent display pipes, allowing for support of two independent display streams. A port is the destination for the result of the pipe. The GMCH contains three display ports; 1 analog (DAC) and two digital (SDVO ports B and C). The ports will be explained in more detail later in this chapter. The entire IGD is fed with data from its memory controller. The GMCH’s graphics performance is directly related to the amount of bandwidth available. If the engines are not receiving data fast enough from the memory controller (e.g., single-channel DDR3 1066), the rest of the IGD will also be affected. The rest of this chapter will focus on explaining the IGD components, their limitations, and dependencies. 10.5.1 3D Graphics Pipeline The GMCH graphics is the next step in the evolution of integrated graphics. In addition to running the graphics engine at 400 MHz, the GMCH graphics has two pixel pipelines that provide a 1.3 GB/s fill rate that enables an excellent consumer gaming experience. The 3D graphics pipeline for the GMCH has a deep pipelined architecture in which each stage can simultaneously operate on different primitives or on different portions of the same primitive. The 3D graphics pipeline is divided into four major stages: geometry processing, setup (vertex processing), texture application, and rasterization. The GMCH graphics is optimized for use with current and future Intel® processors for advance software based transform and lighting techniques (geometry processing) as defined by the Microsoft DirectX* API. The other three stages of 3D processing are handled on the integrated graphics device. The setup stage is responsible for vertex processing; converting vertices to pixels. The texture application stage applies textures to pixels. The rasterization engine takes textured pixels and applies lighting and other environmental affects to produce the final pixel value. From the rasterization stage, the final pixel value is written to the frame buffer in memory so it can be displayed. 360 Datasheet Functional Description Figure 10-4. Integrated 3D Graphics Pipeline Processor Geometry: Transform and Lighting, Vertex Shader GMCH Setup Engine: Vertices in, Pixels out Texture Engine: Pixels in, Textured Pixels out Raster Engine: Textured Pixels in, Final Pixels out 3 D-Gfx_Pipeline 10.5.2 3D Engine The 3D engine on the GMCH has been designed with a deep pipelined architecture, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. The GMCH supports Perspective-Correct Texture Mapping, Multitextures, Bump-Mapping, Cubic Environment Maps, Bilinear, Trilinear and Anisotropic MIP mapped filtering, Gouraud shading, Alpha-blending, Vertex, and Per Pixel Fog and Z/W Buffering. The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are the setup engine, scan converter, texture pipeline, and raster pipeline. A typical programming sequence would be to send instructions to set the state of the pipeline followed by rending instructions containing 3D primitive vertex data. The engines’ performance is dependent on the memory bandwidth available. Systems that have more bandwidth available will outperform systems with less bandwidth. The engines’ performance is also dependent on the core clock frequency. The higher the frequency, the more data is processed. Datasheet 361 Functional Description 10.5.3 Texture Engine The GMCH allows an image, pattern, or video to be placed on the surface of a 3D polygon. The texture processor receives the texture coordinate information from the setup engine and the texture blend information from the scan converter. The texture processor performs texture color or ChromaKey matching, texture filtering (anisotropic, trilinear, and bilinear interpolation), and YUV-to-RGB conversions. 10.5.4 Raster Engine The raster engine is where the color data (such as, fogging, specular RGB, texture map blending, etc.) is processed. The final color of the pixel is calculated and the RGBA value combined with the corresponding components resulting from the texture engine. These textured pixels are modified by the specular and fog parameters. These specular highlighted, fogged, textured pixels are color blended with the existing values in the frame buffer. In parallel, stencil, alpha, and depth buffer tests are conducted that determine whether the frame and depth buffers will be updated with the new pixel values. 10.6 Display Interfaces (Intel® 82Q35, 82Q33, 82G33 Only GMCH) The GMCH have three display ports; one analog and two digital. Each port can transmit data according to one or more protocols. The digital ports are connected to an external device that converts one protocol to another. Examples of these are TV encoders, external DACs, LVDS transmitters, HDMI transmitters, and TMDS transmitters. Each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. The GMCH has one dedicated display port, the analog port. SDVO ports B and C are multiplexed with the PCI Express Graphics (PEG) interface and are not available if an external PEG device is in use. When a system uses a PEG connector, SDVO ports B and C can be used via an ADD2 (Advanced Digital Display 2) or MEC (Media Expansion Card). • The (G)MCH’s analog port uses an integrated 350 MHz RAMDAC that can directly drive a standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 75 Hz. • The GMCH’s SDVO ports are each capable of driving a 225MP pixel rate. Each port is capable of driving a digital display up to 1920x1200 @ 60Hz. The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant external device and connector, the GMCH has a high speed interface to a digital display (e.g., flat panel or digital CRT). The GMCH is compliant with HDMI. When combined with a HDMI compliant external device and connector, the external HDMI device can supports standard, enhanced, or high-definition video, plus multi-channel digital audio on a single cable. 362 Datasheet Functional Description 10.6.1 Analog Display Port Characteristics The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT based monitor with a VGA connector. Display devices such as LCD panels with analog inputs may work satisfactory but no functionality added to the signals to enhance that capability. Table 10-1. Analog Port Characteristics Signal Port Characteristic Voltage Range RGB Monitor Sense Analog Copy Protection Sync on Green Voltage Enable/Disable HSYNC VSYNC Polarity adjust Composite Sync Support Special Flat Panel Sync Stereo Sync DDC Voltage Control Support 0.7 V p-p only Analog Compare No No 2.5 V Port control VGA or port control No No No Externally buffered to 5 V Through GPIO interface 10.6.1.1 Integrated RAMDAC The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms the digital data from the graphics and video subsystems to analog data for the CRT monitor. The GMCH’s integrated 350 MHz RAMDAC supports resolutions up to 2048 x 1536 @ 75 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor. 10.6.1.2 Sync Signals HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector. Since these levels cannot be generated internal to the device, external level shifting buffers are required. These signals can be polarity adjusted and individually disabled in one of the two possible states. The sync signals should power up disabled in the high state. No composite sync or special flat panel sync support will be included. 10.6.1.3 VESA/VGA Mode VESA/VGA mode provides compatibility for pre-existing software that set the display mode using the VGA CRTC registers. Timings are generated based on the VGA register values and the timing generator registers are not used. Datasheet 363 Functional Description 10.6.1.4 DDC (Display Data Channel) DDC is a standard defined by VESA. Its purpose is to allow communication between the host system and display. Both configuration and control information can be exchanged allowing plug- and-play systems to be realized. Support for DDC 1 and 2 is implemented. The GMCH uses the DDC_CLK and DDC_DATA signals to communicate with the analog monitor. The GMCH generates these signals at 2.5 V. External pull-up resistors and level shifting circuitry should be implemented on the board. The GMCH implements a hardware GMBus controller that can be used to control these signals allowing for transactions speeds up to 400 kHz. 10.6.2 Digital Display Interface The GMCH has several options for driving digital displays. The GMCH contains two SDVO ports that are multiplexed on the PEG interface. When an external PEG graphics accelerator is not present, the GMCH can use the multiplexed SDVO ports to provide extra digital display options. These additional digital display capabilities may be provided through an ADD2/Media Expansion Card, which is designed to plug in to a PCI Express connector. 10.6.2.1 Multiplexed Digital Display Channels – Intel® SDVOB and Intel® SDVOC The GMCH has the capability to support digital display devices through two SDVO ports multiplexed with the PEG signals. When an external graphics accelerator is used via the PEG port, these SDVO ports are not available. The shared SDVO ports each support a pixel clock up to 200 MHz and can support a variety of transmission devices. SDVOCTRLDATA is an open-drain signal that will act as a strap during reset to tell the GMCH whether the interface is a PCI Express interface or an SDVO interface. When implementing SDVO, either via ADD2 cards or with a down device, a pull-up is placed on this line to signal to the GMCH to run in SDVO mode and for proper GMBus operation. 10.6.2.2 ADD2/Media Expansion Card (MEC) When an Intel® 3 Series Express Chipset platform uses a PEG connector, the multiplexed SDVO ports may be used via an ADD2 or MEC card. The ADD2 card will be designed to fit a standard PCI Express (x16) connector. 10.6.2.3 TMDS Capabilities The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant external device and connector, the GMCH has a high speed interface to a digital display (e.g., flat panel or digital CRT). The GMCH can drive a flat panel up to 1920x1200 or a dCRT/HDTV up to 1400x1050. Flat Panel is a fixed resolution display. The GMCH supports panel fitting in the transmitter, receiver, or an external device, but has no native panel fitting capabilities. The GMCH will however, provide unscaled mode where the display is centered on the panel. 364 Datasheet Functional Description 10.6.2.4 HDMI Capabilities The GMCH is compliant with HDMI. When combined with a HDMI compliant external device and connector, the external HDMI device can support standard, enhanced, or high-definition video, plus multi-channel digital audio on a single cable. The GMCH has a high speed interface to a digital display (e.g., flat panel or digital TV). The GMCH can drive a digital TV up to 1600x1200. 10.6.2.5 LVDS Capabilities The GMCH may use the multiplexed SDVO ports to drive an LVDS transmitter. Flat Panel is a fixed resolution display. The GMCH supports panel fitting in the transmitter, receiver or an external device, but has no native panel fitting capabilities. The GMCH will however, provide unscaled mode where the display is centered on the panel. The GMCH supports scaling in the LVDS transmitter through the SDVO stall input pair. 10.6.2.6 TV-IN Capabilities The GMCH in conjunction with ADD2/Media Expansion Card can function as a TVTuner card capable of taking in both analog or HD signals. 10.6.2.7 TV-Out Capabilities Although traditional TVs are not digital displays, the GMCH uses a digital display channel to communicate with a TV-Out transmitter. For that reason, the GMCH considers a TV-Output to be a digital display. The GMCH supports NTSC/PAL/SECAM standard definition formats. The GMCH will generate the proper timing for the external encoder. The external encoder is responsible for generation of the proper format signal. Since the multiplexed SDVO interface is a NTSC/PAL/SECAM display on the TVout port can be configured to be the boot device. It is necessary to ensure that appropriate BIOS support is provided. If EasyLink is supported in the GMCH, then this mechanism could be used to interrogate the display device. The TV-out interface on GMCH allows an external TV encoder device to drive a pixel clock signal on SDVO_TVClk[+/-] that the GMCH uses as a reference frequency. The frequency of this clock is dependent on the output resolution required. 10.6.2.7.1 Flicker Filter and Overscan Compensation The overscan compensation scaling and the flicker filter is done in the external TV encoder chip. Care must be taken to allow for support of TV sets with high performance de-interlacers and progressive scan displays connected to by way of a non-interlaced signal. Timing will be generated with pixel granularity to allow more overscan ratios to be supported. 10.6.2.7.2 Analog Content Protection Analog content protection will be provided through the external encoder using Macrovision 7.01. DVD software must verify the presence of a Macrovision TV encoder before playback continues. Simple attempts to disable the Macrovision operation must be detected. Datasheet 365 Functional Description 10.6.2.7.3 Connectors Target TV connectors support includes the CVBS, S-Video, Component, HDMI and SCART connectors. The external TV encoder in use will determine the method of support. 10.6.2.8 Control Bus Communication to SDVO registers and if used, ADD2/MEC PROMs and monitor DDCs, are accomplished by using the SDVO_CTRLDATA and SDVO_CTRLCLK signals through the SDVO device. These signals run up to 1 MHz and connect directly to the SDVO device. The SDVO device is then responsible for routing the DDC and PROM data streams to the appropriate location. Consult SDVO device datasheets for level shifting requirements of these signals. Intel® SDVO Modes The port can be dynamically configured in several modes: • Standard. This mode provides baseline SDVO functionality. It supports pixel rates between 25 MP/s and 225 MP/s. It uses three data pairs to transfer RGB data. • Dual Standard. This mode provides Standard data streams across both SDVOB and SDVOC. Both channels can only run in Standard mode (3 data pairs) and each channel supports Pixel Rates between 25 MP/s and 225 MP/s. ⎯ Dual Independent Standard. In Dual Independent Standard mode, each SDVO channel will transmit a different pixel stream. The data stream across SDVOB will not be the same as the data stream across SDVOC. ⎯ Dual Simultaneous Standard. In Dual Simultaneous Standard mode, both SDVO channels will transmit the same pixel stream. The data stream across SDVOB will be the same as the data stream across SDVOC. The display timings will be identical, but the transfer timings may not be (i.e., SDVOB clocks and data may not be perfectly aligned with SDVOC clock and data as seen at the SDVO device(s)). Since this uses just a single data stream, it uses a single pixel pipeline within the GMCH. 10.6.3 Multiple Display Configurations Microsoft Windows* 2000, Windows* XP, and Windows* Vista* operating systems provide support for multi-monitor display. Since the GMCH has several display ports available for its two display pipes, it can support up to two different images on different display devices. Timings and resolutions for these two images may be different. The GMCH supports Dual Display Clone, Dual Display Twin, and Extended Desktop. Dual Display Clone uses both display pipes to drive the same content, at the same resolution and color depth to two different displays. This configuration allows for different refresh rates on each display. Dual Display Twin uses one of the display pipes to drive the same content, at the same resolution, color depth, and refresh rates to two different displays. Extended Desktop uses both display pipes to drive different content, at potentially different resolutions, refresh rates, and color depths to two different displays. This configuration allows for a larger Windows Desktop by using both displays as a work surface. Note: The GMCH is also incapable of operating in parallel with an external PCI Express graphics device. The GMCH can, however, work in conjunction with a PCI graphics adapter. 366 Datasheet Functional Description 10.7 10.7.1 Power Management ACPI The GMCH supports ACPI 2.0 system power states S0, S1, S3, and S5; and processor C0, C1, and C2 states. During S3, the GMCH VCC core, PCI Express, and processor VTT voltage rails are powered down – also known as S3-Cold. Table 10-5. Intel® G33 and P35 Express Chipset (G)MCH Voltage Rails Host State S0 S1 S3 S5 VCC 1.25V 1.25V 0V 0V VCC_CL 1.25V 1.25V 0V 0V VCC_DDR DDR2/DDR3 1.8V / 1.5V 1.8V / 1.5V 1.8V / 1.5V 0V VCC_CKDDR DDR2/DDR3 1.8V / 1.5V 1.8V / 1.5V 1.8V / 1.5V 0V VCC_EXP 1.25V 1.25V 0V 0V Table 10-6. Intel® Q35 and Q33 Express Chipset GMCH Voltage Rails Host State S0 S1 S3 S3 S3 S5 S3 S5 ME State M0 M0 M1 Moff Wake-on-ME Moff M1 Moff Wake-on-ME Moff VCC 1.25V 1.25V 0V 0V 0V 0V 0V 0V VCC_CL 1.25V 1.25V 1.25V 0V 0V 1.25V 0V 0V VCC_DDR 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 0V 0V VCC_CKDDR 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 0V 0V VCC_EXP 1.25V 1.25V 0V 0V 0V 0V 0V 0V The GMCH supports ACPI device power states D0, D1, D2, and D3 for the integrated graphics device. The GMCH supports ACPI device power states D0 and D3 for the PCI Express interface 10.7.2 PCI Express Active State Power Management • PCI Express Link States: L0, L0s, L1, L2/L3 Ready, and L3. Datasheet 367 Functional Description 10.8 Thermal Sensor There are several registers that need to be configured to support the (G)MCH thermal sensor functionality and SMI# generation. Customers must enable the Catastrophic Trip Point at 115 °C as protection for the (G)MCH. If the Catastrophic Trip Point is crossed, then the (G)MCH will instantly turn off all clocks inside the device. Customers may optionally enable the Hot Trip Point between 85 °C and 105 °C to generate SMI#. Customers will be required to then write their own SMI# handler in BIOS that will speed up the (G)MCH (or system) fan to cool the part. 10.8.1 PCI Device 0 Function 0 The SMICMD register requires that a bit be set to generate an SMI# when the Hot trip point is crossed. The ERRSTS register can be inspected for the SMI alert. Register Address C8–C9h CC–CDh Register Symbol ERRSTS SMICMD Register Name Error Status SMI Command Default Value 0000h 0000h Access RO, RWC/S RO, RW 10.8.2 MCHBAR Thermal Sensor Registers The Digital Thermometer Configuration Registers reside in the MCHBAR configuration space. Address Offset CD8h CD9h CDAh CDC–CDFh CE2h CE4h CE6h CEA–CEBh CF1h Symbol TSC1 TSC2 TSS TSTTP TCO THERM1 THERM3 TIS TSMICMD Register Name Thermal Sensor Control 1 Thermal Sensor Control 2 Thermal Sensor Status Thermal Sensor Temperature Trip Point Thermal Calibration Offset Hardware Protection TCO Fuses Thermal Interrupt Status Thermal SMI Command Default Value 00h 00h 00h 00000000h 00h 00h 00h 0000h 00h Access RW/L, RW, RS/WC RW/L, RO RO RO, RW, RW/L RW/L/K, RW/L RW/L, RO, RW/L/K RS/WC, RO RO, RWC RO, RW 368 Datasheet Functional Description 10.8.3 Programming Sequence The following sequence must be followed in BIOS to properly set up the Hot Trip Point and ICH SMI# signal assertion: 1. 2. 3. 4. 5. 6. 7. 8. 9. In Thermal Sensor Control 1 Register (TSC1), set thermal sensor enable bit (TSE) and the hysteresis value (DHA) by writing 99h to MCHBAR CD8h Program the Hot Trip Point Register (TSTTP[HTPS]) by writing the appropriate value to MCHBAR CDCh bits [15:8] Program the Catastrophic Trip Point Setting Register (TSTTP[CTPS]) by writing 2Ch to MCHBAR CDCh bits [7:0] In Thermal Sensor Control 2 Register (TSC2), program the Thermometer Mode Enable and Rate (TE) by writing 04h to MCHBAR CD9h bits [3:0] In the Hardware Protection Register (THERM1), program the Halt on Catastrophic bit (HOC) by writing 08h to MCHBAR CE4h bits [7:0] Lock the Hardware Protection by writing a 1 to the Lock bit (HTL) at MCHBAR CE4h bit [0] In Thermal SMI Command Register (TSMICMD), set the SMI# on Hot bit by writing a 02h to MCHBAR CF1h Program the SMI Command register (SMICMD[TSTSMI]) by writing a 1 to bit 11 to PCI CCh Program the TCO Register (TCO[TSLB]) to lock down the other register settings by writing a 1 to bit 7 of MCHBAR CE2h If the temperature rises above the Hot Trip point: The TIS[Hot Thermal Sensor Interrupt Event] is set when SMI# interrupt is generated. 10. Clear this bit of the TIS register to allow subsequent interrupts of this type to get registered. 11. Clear the global thermal sensor event bit in the Error Status Register, bit 11. 12. 13. In thermal sensor status register (TSS), the Hot trip indicator (HTI) bit is set if this condition is still valid by the time the software gets to read the register. Datasheet 369 Functional Description 10.8.4 Trip Point Temperature Programming The Catastrophic and Hot trip points are programmed in the TSTTP Register. Bits 7:0 are for the Catastrophic Trip Point (CTPS), and bits 15:8 are for the Hot Trip Point (HTPS). Note: The Catastrophic Trip Point is recommended to fixed at 118 C. The Hot Trip Point is recommended to be between 95 C and 105 C. Programming the Hot Trip Point above this range is not recommended. To program both trip point settings, the following polynomial equation should be used. Programmed temp = (0.0016 × value^2) – (1.10707 × value) + 161.05 In this case the “value” is a decimal number between 0 and 128. For the Catastrophic Trip Point, a decimal value of 41 (29h) should be used to hit 118 C. (0.0016 × 41^2) – (1.10707 × 41) + 161.05 = 118.3 C The CTPS should then be programmed with 29h. The Hot Trip Point is also programmed in the same manner. 370 Datasheet Functional Description 10.9 10.9.1 Clocking Overview The (G)MCH has a total of 5 PLLs providing many times that many internal clocks. The PLLs are: • Host PLL – Generates the main core clocks in the host clock domain. Can also be used to generate memory and internal graphics core clocks. Uses the Host clock (H_CLKIN) as a reference. • Memory IO PLL - Optionally generates low jitter clocks for memory IO interface, as opposed to from Host PLL. Uses the Host FSB differential clock (HPL_CLKINP/HPL_CLKINN) as a reference. Low jitter clock source from Memory I/O PLL is required for DDR667 and higher frequencies. • PCI Express PLL – Generates all PCI Express related clocks, including the Direct Media Interface that connects to the ICH. This PLL uses the 100 MHz clock (G_CLKIN) as a reference. • Display PLL A – Generates the internal clocks for Display A. Uses D_REFCLKIN as a reference. • Display PLL B – Generates the internal clocks for Display B. Also uses D_REFCLKIN as a reference. • CK505 is the Clocking chip required for the Intel® 3 Series Express Chipset platform Datasheet 371 Functional Description 10.9.2 Platform Clocks Figure 10-5. Intel® 3 Series Express Chipset Clocking Diagram CPU Diff Pair CPU Diff Pair Memory CPU Diff Pair CK505 56-Pin SSOP C1 C2 Processor XDP Slot 2 Slot 0 X 16 PCI Express Slot 1 Slot 3 C3/S7 PCI Express DIff Pair S6 PCI Express DIff Pair PCI Express GFX PCI Express Slot S5 S4 S3 S2 S1 PCI Express Diff Pair PCI Express Diff Pair PCI Express Diff Pair PCI Express Diff Pair SATA Diff Pair LAN PCI Express Slot (G)MCH DMI D1 U1 R1 DOT 96 MHz Diff Pair USB 48 MHz REF 14 MHz REF 14 MHz PCI 33 MHz SIO LPC Intel® ICH9 P1 PCI 33 MHz PCI Down Device P2 P3 PCI 33 MHz PCI 33 MHz TPM LPC OSC Intel High Definition Audio 24 MHz 32.768 kHz Ref C1-C3 S1-S7 D1 U1 P1-P6 R1 Signal Name P4 P5 P6 PCI 33 MHz PCI 33 MHz PCI 33 MHz BCLK ITPCLK HCLK , , NC NC SATACLK, ICHCLK, MCHCLK, LANCLK, PCIECLK DOTCLK USBCLK PCICLK REFCLK PCI Slot § 372 Datasheet Functional Description Datasheet 373 Electrical Characteristics 11 Electrical Characteristics This chapter contains the DC specifications for the (G)MCH. Note: References to SDVO, IGD, DAC Display Interface are for the 82Q35, 82Q33, and 82G33 GMCH only. 11.1 Absolute Minimum and Maximum Ratings The following table specifies the Intel 82Q35, 82Q33, 82G33 GMCH and 82P35 MCH absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time its reliability will be severely degraded or not function when returned to conditions within the functional operating condition limits. Although the (G)MCH contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. Table 11-1. Absolute Minimum and Maximum Ratings Symbol Tstorage Parameter Storage Temperature (G)MCH Core VCC 1.25 V Core Supply Voltage with respect to VSS -0.3 1.375 V Min -55 Max 150 Unit °C Notes 1 Host Interface (800/1066/1333 MHz) VTT_FSB VCCA_HPLL System Bus Input Voltage with respect to VSS 1.25 V Host PLL Analog Supply Voltage with respect to VSS -0.3 -0.3 1.32 1.375 V V System Memory Interface (DDR2 667/800 MHz, DDR3 800/1066 MHz) VCC_DDR 1.8 V DDR2 / 1.5 V DDR3 System Memory Supply Voltage with respect to VSS -0.3 4.0 V 374 Datasheet Electrical Characteristics Symbol VCC_CKDDR VCCA_MPLL Parameter 1.8 V DDR2 / 1.5 V DDR3 Clock System Memory Supply Voltage with respect to VSS 1.25 V System Memory PLL Analog Supply Voltage with respect to VSS Min -0.3 -0.3 Max 4.0 1.375 Unit V V Notes PCI Express* / Intel® sDVO / DMI Interface VCC_EXP VCCA_EXP VCCAPLL_EXP 1.25 V PCI Express* and DMI Supply Voltage with respect to VSS 3.3 V PCI Express* Analog Supply Voltage with respect to VSS 1.25 V PCI Express* PLL Analog Supply Voltage with respect to VSS -0.3 -0.3 -0.3 1.375 3.63 1.375 V V V R, G, B / CRT DAC Display Interface (8 bit) VCCA_DAC VCCD_CRT VCCDQ_CRT VCCA_DPLLA VCCA_DPLLB 3.3 V Display DAC Analog Supply Voltage with respect to VSS 1.5 V Display DAC Digital Supply Voltage with respect to VSS 1.5 V Display DAC Quiet Digital Supply Voltage with respect to VSS 1.25 V Display PLL A Analog Supply Voltage with respect to VSS 1.25 V Display PLL B Analog Supply Voltage with respect to VSS Controller Link Interface VCC_CL 1.25 V Supply Voltage with respect to VSS CMOS Interface VCC3_3 3.3 V CMOS Supply Voltage with respect to VSS -0.3 3.63 V -0.3 1.375 V -0.3 -0.3 -0.3 -0.3 -0.3 3.63 1.98 1.98 1.375 1.375 V V V V V NOTE: 1. Possible damage to the MCH may occur if the MCH temperature exceeds 150 °C. Intel does not guarantee functionality for parts that have exceeded temperatures above 150 °C due to specification violation. 11.2 Current Consumption The following table shows the current consumption for the (G)MCH in the Advanced Configuration and Power Interface (ACPI) S0 state. Icc max values are determined on a per-interface basis, at the highest frequencies for each interface. Sustained current values or Max current values cannot occur simultaneously on all interfaces. Sustained Values are measured sustained RMS maximum current consumption and includes leakage estimates. The measurements are made with fast silicon at 96 °C Tcase temperature, at the Max voltage listed in Table 11-2. The Max values are maximum theoretical pre-silicon calculated values. In some cases, the Sustained measured values have exceeded the Max theoretical values. Datasheet 375 Electrical Characteristics Table 11-2. Intel® Q35/Q33 Express Chipset – GMCH Current Consumption in S0 Symbol IVCC Parameter 1.25 V Core Supply Current (using integrated graphics) 1.25 V Core Supply Current (using external graphics) IVCC_DDR2 IVCC_CKDDR2 IVCC_EXP DDR2 System Memory Interface (1.8 V) Supply Current DDR2 System Memory Clock Interface (1.8 V) Supply Current 1.25 V PCI Express* / Intel® SDVO and DMI Supply Current (using integrated graphics) 1.25 V PCI Express* / Intel® SDVO and DMI Supply Current (using external graphics) IVCC_CL IVTT_FSB IVCCA_EXP IVCCA_DAC IVCC3_3 IVCCD_CRT IVCCDQ_CRT IVCCAPLL_EXP IVCCA_HPLL IVCCA_DPLLA IVCCA_DPLLB IVCCA_MPLL 1.25 V Controller Supply Current System Bus Supply Current 3.3 V PCI Express* / Intel SDVO and DMI Analog Supply Current 3.3 V Display DAC Analog Supply Current 3.3 V CMOS Supply Current 1.5 V Display Digital Supply Current 1.5 V Display Quiet Digital Supply Current 1.25 V PCI Express* / Intel® SDVO and DMI PLL Analog Supply Current 1.25 V Host PLL Supply Current 1.25 V Display PLL A Supply Current 1.25 V Display PLL B Supply Current 1.25 V System Memory PLL Analog Supply Current 1. 2. 3. ® Signal Names VCC (int gfx) VCC (ext gfx) VCC_DDR VCC_CKDDR VCC_EXP (int gfx) VCC_EXP (ext gfx) VCC_CL VTT_FSB VCCA_EXP VCCA_DAC VCC3_3 VCCD_CRT VCCDQ_CRT VCCAPLL_E XP VCCA_HPLL VCCA_DPLL A VCCA_DPLL B VCCA_MPLL Sustained Max Unit Notes 1,2 5.27 2.34 2.62 180 7.00 A 3.18 3.71 220 A 1, 2, 3 mA 0.46 1.00 A 2 1.43 2.45 0.52 39 74 0.5 20 9 39 20 49 42 115 2.45 3.88 1 72 78 16 30 11 72 30 73 70 173 A A mA mA mA mA mA mA mA mA mA mA 3 2 1 NOTES: Measurements are for current coming through chipset’s supply pins. Rail includes DLLs (and FSB sense amps on VCC). Sustained Measurements are combined because one voltage regulator on the platform supplies both rails on the MCH. 376 Datasheet Electrical Characteristics Table 11-3 shows the maximum power consumption for the MCH in the ACPI S3, S4, and S5 states with Intel® Active Management Technology support. Platforms that utilize Intel Active Management Technology will keep DRAM memory powered in S4 and S5. Current consumption used by the MCH will vary between the “Idle” case and the “Max” case, depending on activity on the Intel® Management Engine. For the majority of the time, the Intel Management Engine will be in the “Idle” state. In addition, Max values are measured with fast silicon at 96° C Tcase temperature, at the Max voltage listed in the following table. The Max values are measured with a synthetic tool that forces maximum allowable bandwidth on the DRAM interface. It is unknown if commercial SW management applications will be able to generate this level of power consumption. Table 11-3. Current Consumption in S3, S4, S5 with Intel® Active Management Technology Operation (82Q35 GMCH Only) Symbol IMCH_CL IDDR2_PLATFORM Parameter 1.25 V Supply Current for MCH with Intel AMT DDR2 System Memory Interface (1.8 V) Supply Current in Standby States with Intel AMT DDR3 System Memory Interface (1.5 V) Supply Current in Standby States with Intel AMT Signal Names VCC_CL, VCCA_MPLL, VCCA_HPLL VCC_DDR, VCC_CKDDR Idle 625 143 Max 1501 431 Unit mA mA Notes 1,2 1,2 IDDR3_PLATFORM VCC_DDR, VCC_CKDDR 143 431 mA 1,2 1. 2. NOTES: Estimate is only for max current coming through chipset’s supply pins, and is the ICC for the MCH only. Icc max values are determined on a per-interface basis. Max currents cannot occur simultaneously on all interfaces. Datasheet 377 Electrical Characteristics 11.3 Signal Groups The signal description includes the type of buffer used for the particular signal. PCI Express* / Intel® sDVO PCI Express interface signals. These signals are compatible with PCI Express 1.1 Signaling Environment AC Specifications and are AC coupled. The buffers are not 3.3 V tolerant. Differential voltage spec = (|D+ – D-|) * 2 = 1.2 Vmax. Single-ended maximum = 1.25 V. Singleended minimum = 0 V. Direct Media Interface signals. These signals are compatible with PCI Express 1.0 Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2Vmax. Single-ended maximum = 1.25 V. Single-ended minimum = 0 V. Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details. Host Clock Signal Level buffers. Current mode differential pair. Differential typical swing = (|D+ – D-|) * 2 = 1.4 V. Single ended input tolerant from -0.35 V to 1.2 V. Typical crossing voltage 0.35 V. Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V tolerant. Stub Series Termination Logic. These are 1.5 V output capable buffers. 1.5 V tolerant. CMOS buffers Analog reference or output. May be used as a threshold voltage or for buffer compensation. DMI GTL+ HCSL SSTL-1.8 SSTL-1.5 CMOS Analog Table 11-4. Signal Groups Signal Type Signals Host Interface Signal Groups GTL+ Input/Outputs FSB_ADSB, FSB_BNRB, FSB_DBSYB, FSB_DINVB_3:0, FSB_DRDYB, FSB_AB_35:3, FSB_ADSTBB_1:0, FSB_DB_63:0, FSB_DSTBPB_3:0, FSB_DSTBNB_3:0, FSB_HITB, FSB_HITMB, FSB_REQB_4:0 FSB_BPRIB, FSB_BREQ0B, FSB_CPURSTB, FSB_DEFERB, FSB_TRDYB, FSB_RSB_2:0 FSB_RCOMP, FSB_SCOMP, FSB_SCOMPB, FSB_SWING, FSB_DVREF, FSB_ACCVREF FSB_LOCKB, BSEL2:0 Notes GTL+ Common Clock Outputs Analog Host I/F Ref & Comp. Signals GTL+ Input 378 Datasheet Electrical Characteristics Signal Type Signals Notes PCI Express* Graphics and Intel® sDVO Interface Signal Groups PCI Express* / Intel® sDVO Input PCI Express* Interface: PEG_RXN_15:0, PEG_RXP_15:0 Intel® sDVO Interface: SDVO_TVCLKIN-, SDVO_TVCLKIN, SDVOB_INT-, SDVOB_INT+, SDVOC_INT-, SDVOC_INT+, SDVO_STALL-, SDVO_STALL+ PCI Express* / Intel® sDVO Output PCI Express* Interface: PEG_TXN_15:0, PEG_TXP_15:0 Intel® sDVO Interface: SDVOB_CLK-, SDVOB_CLK+, SDVOB_RED-, SDVOB_RED+, SDVOB_GREEN-, SDVOBGREEN+, SDVOB_BLUE-, SDVOB_BLUE+, SDVOC_RED-, SDVOC_RED+, SDVOC_GREEN-, SDVOC_GREEN+, SDVOC_BLUE-, SDVOC_BLUE+, SDVOC_CLK-, SDVOC_CLK+, CMOS I/O OD Analog PCI Express* / Intel® sDVO I/F Compensation Signals SDVO_CTRLCLK, SDVO_CTRLDATA EXP_COMPO, EXP_COMPI 1 1 Direct Media Interface Signal Groups DMI Input DMI Output DMI_RXP_3:0, DMI_RXN_3:0 DMI_TXP_3:0, DMI_TXN_3:0 System Memory Interface Signal Groups SSTL-1.8 / SSTL-1.5 Input/Output DDR_A_DQ_63:0, DDR_A_DQS_7:0, DDR_A_DQSB_7:0 DDR_B_DQ_63:0, DDR_B_DQS_7:0, DDR_B_DQSB_7:0 SSTL-1.8 / SSTL-1.5 Output DDR_A_CK_5:0, DDR_A_CKB_5:0, DDR_A_CSB_3:0, DDR3_A_CSB_1, DDR_A_CKE_3:0, DDR_A_ODT_3:0, DDR_A_MA_14:0, DDR3_A_MA_0, DDR_A_BS_2:0, DDR_A_RASB, DDR_A_CASB, DDR_A_WEB, DDR3_A_WEB, DDR_A_DM_7:0 DDR_B_CK_5:0, DDR_B_CKB_5:0, DDR_B_CSB_3:0, DDR_B_CKE_3:0, DDR_B_ODT_3:0, DDR3_B_ODT_3, DDR_B_MA_14:0, DDR_B_BS_2:0, DDR_B_RASB, DDR_B_CASB, DDR_B_WEB, DDR_B_DM_7:0 DDR3_DRAMRST CMOS Input Reference and Comp. Voltages DDR3_DRAM_PWROK DDR_RCOMPXPD, DDR_RCOMPXPU, DDR_RCOMPYPD, DDR_RCOMPYPU, DDR_VREF Controller Link Signal Groups CMOS I/O OD CMOS Input Analog Controller Link Reference Voltage CL_DATA, CL_CLK CL_RSTB, CL_PWROK CL_VREF Datasheet 379 Electrical Characteristics Signal Type Signals R, G, B / CRT DAC Display Signal Groups Notes Analog Current Outputs Analog/Ref DAC Miscellaneous CMOS I/O OD HVCMOS Output CRT_RED, CRT_REDB, CRT_GREEN, CRT_GREENB, CRT_BLUE, CRT_BLUEB CRT_IREF CRT_DDC_CLK, CRT_DDC_DATA CRT_HSYNC, CRT_VSYNC Clocks 2 HCSL HPL_CLKINP, HPL_CLKINN, EXP_CLKINP, EXP_CLKINN, DPL_REFCLKINN, DPL_REFCLKINP Reset, and Miscellaneous Signal Groups CMOS Input CMOS Output EXP_SLR, EXP_EN, PWROK, RSTINB ICH_SYNCB I/O Buffer Supply Voltages System Bus Input Supply Voltage 1.25 V PCI Express* / Intel® sDVO Supply Voltages 3.3 V PCI Express* / Intel® sDVO Analog Supply Voltage 1.8 V DDR2 / 1.5 V DDR3 Supply Voltage 1.8 V DDR2 / 1.5 V DDR3 Clock Supply Voltage 1.25 V MCH Core Supply Voltage 1.25 V Controller Supply Voltage 3.3 V CMOS Supply Voltage 3.3 V R, G, B / CRT DAC Display Analog Supply Voltage 1.5 V DAC Digital Supply Voltages PLL Analog Supply Voltages VTT_FSB VCC_EXP VCCA_EXP VCC_DDR VCC_CKDDR VCC VCC_CL VCC3_3 VCCA_DAC VCCD_CRT, VCCDQ_CRT VCCA_HPLL, VCCAPLL_EXP, VCCA_DPLLA, VCCA_DPLLB, VCCA_MPLL NOTES: 1. See Section 2.10 for Intel® sDVO & PCI Express* Pin Mapping 2. Current Mode Reference pin. DC specification not required. 380 Datasheet Electrical Characteristics 11.4 11.4.1 DC Characteristics I/O Buffer Supply Voltages The I/O buffer supply voltage is measured at the MCH package pins. The tolerances shown in the following table are inclusive of all noise from DC up to 20 MHz. In the lab, the voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of 3 dB/decade above 20 MHz under all operating conditions. The following table indicates which supplies are connected directly to a voltage regulator or to a filtered voltage rail. For voltages that are connected to a filter, they should me measured at the input of the filter. If the recommended platform decoupling guidelines cannot be met, the system designer will have to make tradeoffs between the voltage regulator output DC tolerance and the decoupling performance of the capacitor network to stay within the voltage tolerances listed below. Table 11-5. I/O Buffer Supply Voltage Symbol VCC_DDR Parameter DDR2 I/O Supply Voltage DDR3 I/O Supply Voltage DDR2 Clock Supply Voltage DDR3 Clock Supply Voltage SDVO, PCI Express* Supply Voltage SDVO, PCI Express* Analog Supply Voltage 1.2 V System Bus Input Supply Voltage 1.1 V System Bus Input Supply Voltage MCH Core Supply Voltage Controller Supply Voltage CMOS Supply Voltage Display DAC Analog Supply Voltage Display Digital Supply Voltage Display Quiet Digital Supply Voltage Min 1.7 1.425 1.7 1.425 1.188 3.135 1.14 1.045 1.188 1.188 3.135 3.135 1.425 1.425 1.188 Nom 1.8 1.5 1.8 1.5 1.25 3.3 1.2 1.1 1.25 1.25 3.3 3.3 1.5 1.5 1.25 Max 1.9 1.575 1.9 1.575 1.313 3.465 1.26 1.155 1.313 1.313 3.465 3.465 1.575 1.575 1.313 Unit V V V V V V V V V V V V V V V 3 1 1 2 2 4 2 Notes VCC_CKDDR VCC_EXP VCCA_EXP VTT_FSB VCC VCC_CL VCC3_3 VCCA_DAC VCCD_CRT VCCDQ_CRT VCCA_HPLL, Various PLLs’ Analog Supply Voltages VCCAPLL_EXP, VCCA_DPLLA, VCCA_DPLLB, VCCA_MPLL 1. NOTES: The VCCD_CRT and VCCDQ_CRT can also operate at a nominal 1.8 V +/- 5% input voltage. Only the 1.5 V nominal voltage setting will be validated internally. Datasheet 381 Electrical Characteristics 2. 3. 4. These rails are filtered from other voltage rails on the platform and should be measured at the input of the filter. See the Platform Design Guide for proper implementation of the filter circuits. VCCA_DAC voltage tolerance should only be measured when the DAC is turned ON and at a stable resolution setting. Any noise on the DAC during power on or display resolution changes do not impact the circuit. MCH supports both Vtt=1.2V nominal and Vtt=1.1V nominal depending on the identified processor. 11.4.2 General DC Characteristics Platform Reference Voltages at the top of the following table are specified at DC only. Vref measurements should be made with respect to the supply voltage. Customers should refer to the Platform Design Guide for proper decoupling of the Vref voltage dividers on the platform. Table 11-6. DC Characteristics Symbol Parameter Min Reference Voltages FSB_DVREF FSB_ACCVREF FSB_SWING CL_VREF DDR_VREF Host Data, Address, and Common Clock Signal Reference Voltages Host Compensation Reference Voltage Controller Link Reference Voltage DDR2/DDR3 Reference Voltage 0.666 x VTT_FSB –2% 0.25 x VTT_FSB –2% 0.270 x VCC_CL 0.49 x VCC_DDR Host Interface VIL_H VIH_H VOL_H VOH_H IOL_H Host GTL+ Input Low Voltage Host GTL+ Input High Voltage Host GTL+ Output Low Voltage Host GTL+ Output High Voltage Host GTL+ Output Low Current -0.10 (0.666 x VTT_FSB) + 0.1 — VTT_FSB – 0.1 — 0 VTT_FSB — — — (0.666 x VTT_FSB) - 0.1 VTT_FSB + 0.1 (0.25 x VTT_FSB) + 0.1 VTT_FSB VTT_FSBmax * (1-0.25) / Rttmin 45 V V V V mA Rttmin = 47.5 Ω VOL< Vpad< Vtt_FSB 0.666 x VTT_FSB 0.25 x VTT_FSB 0.279 x VCC_CL 0.50 x VCC_DDR 0.666 x VTT_FSB +2% 0.25 x VTT_FSB +2% 0.287 x VCC_CL 0.51 x VCC_DDR V Nom Max Unit Notes V V V ILEAK_H Host GTL+ Input Leakage Current Host GTL+ Input Capacitance Host GTL+ Input Capacitance (common clock) — — μA CPAD CPCKG 2.0 0.90 — — 2.5 2.5 pF pF 382 Datasheet Electrical Characteristics Symbol Parameter Min Nom Max Unit Notes DDR2 System Memory Interface VIL(DC) VIH(DC) VIL(AC) VIH(AC) VOL VOH ILeak ILeak CI/O DDR2 Input Low Voltage DDR2 Input High Voltage DDR2 Input Low Voltage DDR2 Input High Voltage DDR2 Output Low Voltage DDR2 Output High Voltage Input Leakage Current Input Leakage Current DQ/DQS/DQSB DDR2 Input/Output Pin Capacitance — DDR_VREF + 0.125 — DDR_VREF + 0.20 — 0.8 * VCC_DDR — — 1.0 — — — — — — — — — ±20 ±550 4.0 0.2 * VCC_DDR DDR_VREF – 0.20 DDR_VREF – 0.125 V V V V V V µA µA pF 1 1 4 5 DDR3 System Memory Interface VIL(DC) VIH(DC) VIL(AC) VIH(AC) VOL VOH ILeak ILeak CI/O DDR3 Input Low Voltage DDR3 Input High Voltage DDR3 Input Low Voltage DDR3 Input High Voltage DDR3 Output Low Voltage DDR3 Output High Voltage Input Leakage Current Input Leakage Current DQ/DQS/DQSB DDR3 Input/Output Pin Capacitance — DDR_VREF + 0.100 — DDR_VREF + 0.175 — 0.8 * VCC_DDR — — 1.0 — — — — — — — — — ±20 ±550 4.0 0.2 * VCC_DDR DDR_VREF – 0.175 DDR_VREF – 0.100 V V V V V V µA µA pF 1 1 4 5 1.25V PCI Express* Interface 1.1 (includes PCI Express* and Intel® sDVO) VTX-DIFF P-P VTX_CM-ACp ZTX-DIFF-DC VRX-DIFF p-p Differential Peak to Peak Output Voltage AC Peak Common Mode Output Voltage DC Differential TX Impedance Differential Peak to Peak Input Voltage 0.800 — 80 0.175 — — 100 — 1.2 20 120 1.2 V mV Ω V 3 2 Datasheet 383 Electrical Characteristics Symbol VRX_CM-ACp Parameter AC Peak Common Mode Input Voltage Min — Input Clocks Nom — Max 150 Unit mV Notes VIL VIH VCROSS(ABS) ΔVCROSS(REL) CIN Input Low Voltage Input High Voltage Absolute Crossing Voltage Range of Crossing Points Input Capacitance -0.150 0.660 0.300 N/A 1 0 0.710 N/A N/A N/A 0.850 0.550 0.140 3 V V V V pF 6,7,8 SDVO_CTRLDATA, SDVO_CTRLCLK VIL VIH ILEAK CIN IOL IOH VOL VOH Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance Output Low Current (CMOS Outputs) Output High Current (CMOS Outputs) Output Low Voltage (CMOS Outputs) Output High Voltage (CMOS Outputs) 2.25 1.75 — — — -1 — — — — — — — — 0.4 ± 10 10.0 7.8 0.75 V V μA pF mA mA V V @ 50% swing @ 50% swing CRT_DDC_DATA, CRT_DDC_CLK VIL VIH ILEAK CIN IOL IOH VOL VOH Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance Output Low Current (CMOS Outputs) Output High Current (CMOS Outputs) Output Low Voltage (CMOS Outputs) Output High Voltage (CMOS Outputs) 2.7 CL_DATA, CL_CLK VIL VIH Input Low Voltage Input High Voltage 0.427 — — 0.277 V V 2.1 — — — -1 — — — — — — — — 0.4 ± 10 10.0 27.0 0.9 V V μA pF mA mA V V @ 50% swing @ 50% swing 384 Datasheet Electrical Characteristics Symbol ILEAK CIN IOL IOH VOL VOH Parameter Input Leakage Current Input Capacitance Output Low Current (CMOS Outputs) Output High Current (CMOS Outputs) Output Low Voltage (CMOS Outputs) Output High Voltage (CMOS Outputs) Min — — Nom — — — Max ± 20 1.5 1.0 Unit μA pF mA mA Notes @VOL_HI max @VOH_HI min 6.0 — — 0.06 V V 0.6 — PWROK, CL_PWROK, RSTIN# VIL VIH ILEAK CIN Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance 2.7 — — CL_RST# VIL VIH ILEAK CIN Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance — 1.17 — — ICH_SYNCB IOL IOH VOL VOH Output Low Current (CMOS Outputs) Output High Current (CMOS Outputs) Output Low Voltage (CMOS Outputs) Output High Voltage (CMOS Outputs) — -2.0 — 2.97 EXP_SLR, EXP_EN VIL VIH ILEAK Input Low Voltage Input High Voltage Input Leakage Current -0.10 (0.63 x VTT)+0.1 — 0 VTT — (0.63 x VTT) 0.1 VTT +0.1 20 V V μA VOL< Vpad< Vtt — — — — 2.0 — 0.33 — mA mA V V @VOL_HI max @VOH_HI min — — — — ±20 5.0 0.13 V V μA pF — — — — ±1 6.0 0.3 V V mA pF CIN Input Capacitance 2 — 2.5 pF Datasheet 385 Electrical Characteristics Symbol Parameter Min CRT_HSYNC, CRT_VSYNC Nom Max Unit Notes IOL IOH VOL VOH Output Low Current (CMOS Outputs) Output High Current (CMOS Outputs) Output Low Voltage (CMOS Outputs) Output High Voltage (CMOS Outputs) 1. 2. 3. 4. 5. 6. 7. 8. — -8.0 — 2.4 — — — — 8.0 — 0.5 — mA mA V V @VOL_HI max @VOH_HI min NOTES: Determined with 2x MCH Buffer Strength Settings into a 50 Ω to 0.5xVCC_DDR test load. Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter compliance eye diagram of PCI Express* specification and measured over any 250 consecutive TX Uls. Specified at the measurement point over any 250 consecutive Uls. The test load shown in Receiver compliance eye diagram of PCI Express* spec should be used as the RX device when taking measurements. Applies to pin to VCC or VSS leakage current for the DDR_A_DQ_63:0 and DDR_B_DQ_63:0 signals. Applies to pin to pin leakage current between DDR_A_DQS_7:0, DDR_A_DQSB_7:0, DDR_B_DQS_7:0, and DDR_B_DQSB_7:0 signals. Crossing voltage defined as instantaneous voltage when rising edge of BCLK0 equals falling edge of BCLK1. VHavg is the statistical average of the VH measured by the oscilloscope. The crossing point must meet the absolute and relative crossing point specifications simultaneously. Refer to the appropriate processor Electrical, Mechanical, and Thermal Specifications for further information. 386 Datasheet Electrical Characteristics 11.4.3 R, G, B / CRT DAC Display DC Characteristics (Intel® 82Q35, 82Q33, 82G33 Only) These parameters apply to the GMCH. Table 11-7. R, G, B / CRT DAC Display DC Characteristics: Functional Operating Range (VCCA_DAC = 3.3 V ± 5%) Parameter DAC Resolution Max Luminance (full-scale) Min 8 0.665 Typical — 0.700 Max — 0.770 Units Bits V Notes 1 1, 2, 4 (white video level voltage) 1, 3, 4 (black video level voltage) 4,5 1,6 1,6 7 Min Luminance LSB Current Integral Linearity (INL) Differential Linearity (DNL) Video channel-channel voltage amplitude mismatch Monotonicity — — -1.0 -1.0 — 0.000 73.2 — — — ensured — — +1.0 +1.0 6 V μA LSB LSB % — 1. 2. 3. 4. 5. 6. 7. NOTES: Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000). Max steady-state amplitude Min steady-state amplitude Defined for a double 75 Ω termination. Set by external reference resistor value. INL and DNL measured and calculated according to VESA Video Signal Standards. Max full-scale voltage difference among R, G, B outputs (percentage of steady-state full-scale voltage). Datasheet 387 Ballout and Package Information 12 Ballout and Package Information This chapter provides the ballout and package information. 12.1 Ballout Figure 12-1, Figure 12-2, and Figure 12-3 show the (G)MCH ballout diagram as viewed from the top side of the package. The figures are divided into a left-side view and right-side view of the package. Note: Notes for Figure 12-1, Figure 12-2, and Figure 12-3, and Table 12-1 and Table 12-2. 1. 2. 3. 4. Balls that are listed as RSVD are reserved. Some balls marked as reserved (RSVD) are used in XOR testing. See Chapter 14 for details. Balls that are listed as NC are No Connects. Analog Display Signals (CRT_RED, CRT_REDB, CRT_GREEN, CRT_GREENB, CRT_BLUE, CRT_BLUEB, CRT_IREF, CRT_HSYNC, CRT_VSYNC, CRT_DDC_CLK, CRT_DDC_DATA) and the SDVO_CTRLCLK and SDVO_CTRLDATA signals are not used on the 82P35 MCH. Contact your Intel field representative for proper termination of the corresponding balls. For the 82Q35, 82Q33, 82G33 GMCH, the PCI Express and SDVO signals are multiplexed. However, only the PCI Express signal name is included in the following ballout figures and table. See Section 2.10 for the PCI Express to SDVO signal name mapping. 5. 388 Datasheet Ballout and Package Information Figure 12-1. (G)MCH Ballout Diagram (Top View Left – Columns 43–30) 43 BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A VSS VSS FSB_REQB_3 VSS FSB_DB_15 FSB_DB_20 FSB_DB_52 FSB_DB_16 FSB_DB_14 FSB_DB_50 FSB_DB_17 VSS FSB_DB_53 FSB_DB_23 FSB_DB_13 FSB_REQB_0 FSB_DB_21 FSB_DB_56 FSB_DSTBNB _3 FSB_DSTBPB _3 VSS FSB_DB_26 FSB_BPRIB VSS FSB_DB_18 FSB_DB_19 VSS FSB_DB_22 FSB_DB_57 FSB_DSTBPB _1 VSS FSB_DB_28 FSB_DB_49 FSB_DB_54 FSB_DB_60 VSS FSB_DSTBNB _0 VSS FSB_DEFERB VSS FSB_HITMB VSS DDR_A_DQ_5 7 VSS DDR_A_DQ_4 9 VSS DDR_A_DM_5 VSS DDR_A_DQ_3 8 DDR_A_DQ_3 4 DDR_A_DQ_4 5 VSS DDR_A_DQ_4 6 DDR_A_DQ_4 2 DDR_A_DQ_5 2 VSS DDR_A_DQS_ 6 DDR_A_DQ_5 5 DDR_A_DQ_6 0 VSS DDR_A_DQS_ 7 DDR_A_DQ_6 3 FSB_BREQ0B VSS FSB_BNRB FSB_AB_30 FSB_HITB VSS FSB_DB_4 FSB_AB_20 FSB_DB_7 FSB_DSTBPB _0 FSB_DB_10 FSB_AB_8 FSB_AB_3 FSB_DB_8 FSB_DB_12 FSB_DB_11 FSB_AB_5 FSB_DB_9 VSS FSB_REQB_4 VSS FSB_DINVB_1 FSB_DSTBNB _1 FSB_DB_25 FSB_DB_27 FSB_DINVB_3 FSB_DB_59 FSB_DB_48 FSB_DB_2 FSB_DB_1 FSB_DB_6 FSB_DB_3 FSB_DINVB_0 VSS FSB_AB_18 FSB_DB_5 FSB_AB_4 FSB_AB_16 FSB_AB_11 FSB_REQB_2 FSB_AB_12 VSS FSB_AB_6 VSS FSB_AB_13 FSB_AB_7 FSB_AB_15 VSS FSB_REQB_1 FSB_AB_10 FSB_ADSTBB _0 VSS VSS VSS VSS FSB_DB_29 VSS FSB_DB_30 FSB_AB_9 VSS FSB_DB_34 VSS FSB_DB_36 FSB_DB_32 VSS FSB_DB_0 FSB_AB_21 FSB_AB_23 FSB_AB_19 VSS FSB_AB_26 FSB_AB_14 VSS HPL_CLKINP VSS RSVD VSS FSB_DRDYB FSB_LOCKB FSB_RSB_0 FSB_DBSYB DDR_A_DQSB _7 DDR_A_DQ_5 8 FSB_RSB_1 DDR_A_DQ_5 9 FSB_TRDYB FSB_ADSB VSS FSB_RSB_2 FSB_AB_31 VSS VSS FSB_AB_17 FSB_AB_22 FSB_AB_24 FSB_AB_28 VSS VSS FSB_ADSTBB _1 FSB_AB_27 FSB_AB_25 VSS HPL_CLKINN RSVD RSVD VSS RSVD RSVD FSB_AB_34 VSS FSB_AB_33 FSB_AB_35 VSS DDR_B_DQ_5 9 FSB_AB_32 VSS VSS DDR_B_DQ_5 8 FSB_AB_29 DDR_B_DQ_6 3 VSS VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL DDR_A_DQSB _6 DDR_A_DQ_5 4 DDR_A_DQ_6 1 DDR_A_DQ_5 1 DDR_A_DQ_5 6 DDR_A_DM_7 VSS DDR_A_DQ_6 2 DDR_B_DM_7 VSS DDR_B_DQSB _7 DDR_B_DQ_5 6 DDR_B_DQS_ 7 VSS DDR_B_DQ_6 0 DDR_B_DQ_6 2 VSS DDR_B_DQ_5 7 VCC_CL VCC_CL VCC_CL DDR_B_DQ_4 8 DDR_B_DQ_6 1 DDR_B_DQSB _6 VSS DDR_B_DQS_ 6 DDR_B_DQ_5 0 DDR_B_DQ_5 4 DDR_B_DQ_5 1 DDR_A_DQS_ 5 DDR_A_DQ_4 3 DDR_A_DQ_5 3 DDR_A_DQ_4 8 VSS DDR_B_DQ_4 9 DDR_B_DQ_5 2 VSS DDR_B_DQ_5 3 DDR_B_DQ_4 2 VSS VSS VCC_CL DDR_A_DQS_ 4 DDR_A_DQ_3 9 DDR_A_DQ_4 0 DDR_A_DQ_4 4 VSS DDR_A_DQSB _5 DDR_A_DQ_3 5 DDR_A_DQ_4 1 DDR_A_DQ_4 7 VSS DDR_B_DQ_4 1 DDR_B_DQ_4 3 DDR_B_DQ_3 5 DDR_B_DM_5 DDR_B_DQ_4 6 DDR_B_DQ_3 4 VSS DDR_B_DQ_3 8 DDR_B_DQ_4 0 DDR_B_DQS_ 5 DDR_B_DQ_4 5 DDR_B_DQSB _5 DDR_B_CK_5 DDR_A_DQSB _4 DDR_B_DQ_4 4 VSS DDR_B_DQ_3 9 DDR_B_DQ_3 7 DDR_A_DM_4 VSS TEST0 NC 42 NC VCC_CKDDR 41 VSS VCC_CKDDR 40 39 VCC_DDR 38 37 VSS 36 35 34 VCC_DDR 33 32 VSS 31 30 VCC_DDR BC BB BA AY AW AV AU AT AR AP AN AM AL DDR_RCOMP YPD DDR_RCOMP YPU VCC_DDR DDR_A_ODT_ 3 DDR_A_CSB_ 3 DDR_A_ODT_ 1 DDR_A_MA_1 3 VCC_DDR DDR_A_ODT_ 0 DDR_A_ODT_ 2 DDR3_A_WE B DDR_A_CSB_ 0 DDR_A_CSB_ 2 DDR_A_WEB VCC_DDR DDR_A_MA_1 0 DDR_A_BS_0 DDR_A_MA_0 DDR_B_CSB_ 3 VCC_CKDDR VCC_CKDDR VCC_CKDDR VSS VSS DDR_B_DQS_ 4 DDR_A_DQ_3 6 DDR_A_DQ_3 3 DDR_B_DQSB _4 DDR3_A_CSB 1 DDR_B_DQ_3 2 DDR_A_CSB_ 1 DDR_A_CASB DDR_A_RASB DDR_A_CKB_ 2 DDR_A_CK_2 DDR_A_CKB_ 5 DDR_A_CK_5 VCC_DDR DDR3_B_ODT 3 DDR_B_CK_2 DDR_A_BS_1 RSVD DDR_A_DQ_3 2 VSS VSS DDR_A_DQ_3 7 DDR_B_CK_0 DDR_B_CKB_ 0 DDR_A_CKB_ 0 VSS DDR_B_DQ_3 3 VSS VSS VSS DDR_B_DQ_3 6 DDR_B_DM_4 VSS DDR_B_CKB_ 2 VSS DDR_B_CKB_ 5 RSVD VSS DDR_A_CK_0 DDR_A_CKB_ 3 VSS VSS DDR_B_DQ_4 7 RSVD VSS VSS VSS VCC_CL AK AJ AH VCC_CL DDR_A_DM_6 DDR_B_DM_6 DDR_A_DQ_5 0 VSS VSS DDR_B_DQ_5 5 RSVD VCC_CL VCC_CL AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D VSS RSVD VCC_CL VCC_CL VSS VSS VCC_CL VCC_CL VCC_CL VSS FSB_DB_33 VSS FSB_DB_63 FSB_DB_37 FSB_DB_39 FSB_DB_35 VSS FSB_CPURST B VTT_FSB C B A NC TEST2 NC NC FSB_DB_51 VSS FSB_DB_55 FSB_DB_24 VSS FSB_DB_61 FSB_DB_31 VSS FSB_DB_58 VSS FSB_DB_62 VSS VTT_FSB VTT_FSB 43 42 41 40 39 38 37 36 35 34 33 32 31 30 Datasheet 389 Ballout and Package Information Figure 12-2. (G)MCH Ballout Diagram (Top View Middle– Columns 29–15) 29 28 VSS 27 26 VCC_DDR 25 24 VSS 23 22 VCC_DD R DDR_A_ MA_5 DDR_A_ MA_6 21 20 DDR_A_ MA_12 19 18 VCC_DD R 17 16 DDR3_D RAMRST B 15 BC BB BA AY AW AV AU AT AR AP DDR3_A_MA0 DDR_B_CSB_ 1 DDR_B_ODT_ 3 DDR_B_ODT_ 1 DDR_B_CK_4 DDR_B_CKB_ 3 VSS BC DDR_B_ MA_1 DDR_B_ MA_2 DDR_B_ MA_3 DDR_B_ MA_0 DDR_B_ DQ_22 DDR_B_ DQ_16 VSS DDR_B_ DQSB_2 DDR_B_ DQS_2 DDR3_D RAM_PW ROK CL_PWR OK VCC_CL VCC_CL VCC_CL VCC_DDR DDR_B_ODT_ 0 VCC_DDR DDR_B_WEB VCC_DDR DDR_A_MA_3 DDR_A_ MA_7 DDR_A_ MA_9 DDR_A_ MA_11 DDR_A_ MA_8 VSS DDR_A_ DQ_26 DDR_A_ DQ_27 VSS VCC_DD R DDR_A_ CKE_2 DDR_A_ MA_14 VCC_DD R DDR_A_ CKE_3 DDR_B_ BS_0 DDR_B_ MA_10 DDR_B_ BS_1 VCC_DD R BB BA AY AW AV AU AT AR AP DDR_B_ODT_ DDR_B_CSB_ DDR_B_CSB_ 2 2 0 DDR_B_MA_1 3 DDR_B_CKB_ 4 VSS DDR_B_CAS B VCC_DDR DDR_B_DQS B_3 DDR_A_MA_1 DDR_B_RAS B VCC_DDR DDR_B_DQ_2 4 VSS DDR_A_MA_2 DDR_A_MA_4 DDR_B_DQ_2 9 VSS DDR_B_DQ_2 8 DDR_A_ BS_2 VCC_DD R DDR_A_ DQ_31 VSS DDR_A_ DQS_3 VSS DDR_A_ DQ_30 DDR_A_ CKE_0 DDR_A_ CKE_1 VCC_DD R DDR_A_ DQSB_3 DDR_A_ DQ_24 DDR_A_ DQ_25 VSS DDR_B_ DQ_23 VSS DDR_B_ DQ_18 DDR_B_ DQ_19 VSS DDR_A_ DQ_28 DDR_A_ DQ_29 DDR_B_CK_1 DDR_B_CKB_ DDR_B_DQ_2 1 6 VSS VSS DDR_B_DQ_2 7 DDR_B_DQS_ DDR_B_DQ_2 3 5 DDR_B_DQ_3 0 VSS VSS DDR_B_CK_3 DDR_A_CK_3 DDR_A_CK_1 DDR_B_DM_3 RSVD AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H VSS DDR_A_CKB_ DDR_B_DQ_3 1 1 DDR_A_CKB_ DDR_A_CK_4 4 VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VSS VSS RSVD VSS DDR_A_ DM_3 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H VSS VCC_CL VCC_CL VCC_CL VSS VCC_CL VCC_CL VCC_CL VSS VCC_CL VCC_CL VCC_CL RSVD VCC_CL VCC_CL VCC_CL VSS VCC_CL VCC_CL VCC_CL RSTINB VCC_CL VCC_CL VCC_CL PWROK VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC VCC_CL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_CL VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_CL VCC_CL VCC VCC VCC VCC VCC VCC_CL VCC_CL VCC VCC VCC VCC VCC VSS VSS VCC VSS VCC VCC RSVD VTT_FSB VTT_FSB VTT_FSB VSS FSB_DB_38 VTT_FSB VTT_FSB VSS VSS FSB_DB_42 FSB_DB_43 VTT_FSB VTT_FSB VTT_FSB FSB_DB_47 FSB_DB_45 VSS VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VSS VSS VSS VSS VSS VSS RSVD VCC NC VSS VSS ALLZTES T BSEL1 VCC VSS RSVD RSVD RSVD VSS VCC VSS RSVD VSS RSVD RSVD VCC VCC RSVD VSS RSVD PEG_RX P_1 PEG_RX N_1 VSS FSB_DB_40 VSS FSB_DSTBNB _2 FSB_DSTBPB _2 FSB_DB_46 VTT_FSB VTT_FSB VSS BSEL2 EXP_EN VSS FSB_DB_44 VTT_FSB VTT_FSB VSS VSS RSVD VSS SDVO_C TRLDAT A RSVD SDVO_C TRLCLK VSS VSS G F E D C B A FSB_DINVB_ 2 VTT_FSB VTT_FSB VTT_FSB VSS BSEL0 MTYPE RFU_G1 5 G F E D C B A FSB_DB_41 VSS VTT_FSB VTT_FSB VTT_FSB VSS XORTES T TCEN CRT_BL UEB CRT_GR EENB CRT_GR EEN CRT_BL UE CRT_IRE F VSS VSS EXP_SL R VSS CRT_VS YNC VSS CRT_HS YNC VCCA_D AC VCCA_E XP VCCAPL L_EXP VTT_FSB VTT_FSB VTT_FSB FSB_SCOMP B VSS FSB_SCOMP VSS VTT_FSB VSS VTT_FSB VTT_FSB VTT_FSB FSB_DVREF FSB_RCOMP VCCA_D PLLB VSS VCCA_D PLLA VSS VCCD_C RT VCCDQ_ CRT VTT_FSB VTT_FSB VCCA_HPLL FSB_ACCVR EF VCCA_MPLL CRT_RE DB CRT_RE D VSS VCCA_D AC VCC3_3 VTT_FSB VTT_FSB VTT_FSB VSS FSB_SWING VSS VTT_FSB VSS 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 390 Datasheet Ballout and Package Information Figure 12-3. (G)MCH Ballout Diagram (Top View Right – Columns 14–1) 14 BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A DPL_REFCLKI NP VSS RSVD VCC VCC VSS CRT_DDC_CL K CRT_DDC_DA TA VSS ICH_SYNCB VSS VSS PEG_RXP_0 PEG_RXN_0 DPL_REFCLKI NN VCC EXP_CLKINN EXP_CLKINP VSS VCC VSS PEG_RXP_3 PEG_RXN_3 VSS PEG_RXP_2 PEG_RXN_2 PEG_TXN_0 PEG_RXP_4 PEG_RXN_4 VSS VCC VSS PEG_TXP_0 VSS VCC VSS PEG_TXN_2 VSS PEG_RXP_5 PEG_RXN_5 PEG_TXP_4 PEG_TXN_4 PEG_RXP_8 PEG_RXN_6 PEG_RXP_6 VCC PEG_RXN_8 PEG_TXN_8 PEG_TXP_8 VSS VSS VSS VCC PEG_TXP_7 PEG_TXN_7 PEG_RXN_7 VSS VSS VSS VSS VCC VSS PEG_TXP_9 VCC VCC VSS VSS VSS VCC PEG_RXN_10 VCC PEG_RXP_10 VSS VSS VCC PEG_RXN_12 VSS PEG_RXP_12 PEG_TXN_12 PEG_RXP_11 RSVD RSVD VSS PEG_RXN_13 PEG_RXP_13 VSS PEG_RXN_15 PEG_RXP_15 VSS VCC VCC VCC VCC VCC RSVD VSS RSVD VCC VCC VCC VCC VSS VSS DMI_TXP_0 VSS DMI_TXN_0 VCC VSS VSS PEG_TXN_15 PEG_RXP_14 PEG_RXN_14 VSS PEG_TXP_12 VCC VCC VCC VCC VCC CL_RSTB RSVD RSVD VCC RSVD VSS RSVD DMI_RXN_1 VSS DMI_RXP_1 DMI_RXP_2 VSS DMI_RXN_2 VCC VSS VSS DMI_RXN_3 DMI_TXN_1 DMI_TXP_1 VSS PEG_TXP_15 VCC VCC VCC CL_CLK VCC CL_DATA EXP_COMPI VCC_EXP EXP_COMPO VCC_EXP VSS VCC_EXP DMI_TXN_2 VCC_EXP DMI_TXP_2 VCC_EXP VSS VCC_EXP VCC VCC_EXP VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS VCC_EXP VCC_EXP VCC_EXP DMI_RXP_3 VCC VCC_CL VCC_CL VCC_CL VCC VCC VCC VCC VCC VCC VCC VCC VCC_CL VCC VCC VCC VCC VSS VCC_DDR 13 12 DDR_B_CKE_ 1 11 10 VSS 9 8 7 DDR_A_DQ_2 2 6 5 VSS DDR_A_DQ_1 6 DDR_A_DQ_2 0 4 3 VSS 2 NC 1 TEST1 BC BB BA AY DDR_B_MA_5 DDR_B_MA_8 VCC_DDR DDR_B_MA_1 4 DDR_B_MA_1 2 DDR_B_CKE_ 3 DDR_B_CKE_ 2 DDR_A_DQ_1 9 DDR_A_DQ_1 8 DDR_A_DQ_2 3 DDR_B_DM_1 VSS DDR_A_DM_2 DDR_A_DQSB _2 DDR_A_DQ_2 1 DDR_A_DQ_1 0 VSS DDR_A_DQ_1 1 NC NC DDR_B_MA_4 DDR_B_MA_7 DDR_B_MA_1 1 DDR_B_MA_6 DDR_B_DQ_1 4 DDR_B_DQ_1 5 VSS DDR_B_DQS_ 1 DDR_B_DQSB _1 VSS RSVD DDR_A_DQ_1 5 DDR_A_DM_1 DDR_A_DQ_1 4 DDR_A_DQS_ 1 VSS DDR_A_DQ_1 2 VSS DDR_B_MA_9 DDR_B_BS_2 DDR_B_CKE_ 0 VSS DDR_A_DQS_ 2 DDR_B_DQ_3 DDR_A_DQ_1 7 DDR_B_DQ_2 DDR_B_DQS_ 0 VSS DDR_B_DQSB _0 DDR_B_DM_2 DDR_B_DQ_1 7 DDR_B_DQ_2 0 VSS DDR_B_DQ_1 1 DDR_B_DQ_1 0 VSS DDR_B_DQ_2 1 VCC_CL DDR_A_DQSB _1 AW AV VSS DDR_B_DQ_1 3 VSS DDR_A_DQ_8 DDR_A_DQ_9 DDR_B_DQ_9 DDR_B_DQ_8 DDR_B_DQ_1 2 DDR_B_DQ_7 VSS DDR_A_DQ_1 3 AU AT VSS DDR_B_DM_0 VSS DDR_A_DQ_6 DDR_A_DQ_7 DDR_A_DQ_3 DDR_A_DQSB _0 DDR_A_DQ_2 DDR_A_DQS_ 0 DDR_A_DM_0 DDR_A_DQ_5 DDR_RCOMP XPU VCC_CL VCC_CL VCC VCC VCC VSS VCC_EXP VCC_EXP VSS DMI_TXN_3 DMI_TXP_3 DMI_RXP_0 VSS PEG_TXP_14 PEG_TXN_14 PEG_TXP_13 VSS PEG_TXP_11 PEG_TXN_11 VSS PEG_TXN_13 VSS DMI_RXN_0 VSS VSS VCC_EXP VCC VCC VCC_CL DDR_A_DQ_0 AR VSS AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L VSS VSS DDR_RCOMP VOH VCC_CL DDR_B_DQ_6 VSS DDR_B_DQ_1 DDR_RCOMP VOL VCC_CL DDR_B_DQ_0 VSS DDR_B_DQ_5 DDR_VREF DDR_B_DQ_4 CL_VREF VSS VSS DDR_RCOMP XPD DDR_A_DQ_1 VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL DDR_A_DQ_4 VCC_CL VCC_CL VSS PEG_RXP_9 PEG_RXN_9 VSS VCC VSS PEG_RXN_11 VSS PEG_TXN_9 VCC PEG_TXP_10 VSS VCC PEG_TXN_10 K J H G F E D VSS PEG_TXP_1 PEG_TXP_2 VSS PEG_TXN_1 VCC PEG_TXP_3 PEG_TXN_3 VSS VSS PEG_TXN_5 VSS PEG_TXP_5 VSS VSS PEG_TXN_6 PEG_TXP_6 VSS PEG_RXP_7 NC VSS C B A 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Datasheet 391 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball BC43 BC42 BC41 BC40 BC39 BC38 BC37 BC36 BC35 BC34 BC33 BC32 BC31 BC30 BC29 BC28 BC27 BC26 BC25 BC24 BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16 BC15 BC14 BC13 Signal Name TEST0 NC VSS ---VCC_DDR ---VSS ------VCC_DDR ---VSS ---VCC_DDR ---VSS ---VCC_DDR ---VSS ---VCC_DDR ---DDR_A_MA_12 ---VCC_DDR ---DDR3_DRAMRST B ---VCC_DDR ---- Table 12-1. Ballout – Sorted by Ball Ball BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BB43 BB42 BB41 BB40 BB39 BB38 BB37 BB36 BB35 BB34 BB33 BB32 BB31 BB30 BB29 BB28 BB27 BB26 BB25 Signal Name DDR_B_CKE_1 ---VSS ------DDR_A_DQ_22 ---VSS ---VSS NC TEST1 NC VCC_CKDDR VCC_CKDDR DDR_RCOMPYPD VCC_DDR DDR_A_CSB_3 VCC_DDR ---DDR_A_ODT_0 DDR3_A_WEB DDR_A_CSB_2 VCC_DDR DDR_A_MA_10 DDR_A_MA_0 DDR3_A_MA0 VCC_DDR DDR_B_ODT_0 VCC_DDR DDR_B_WEB Table 12-1. Ballout – Sorted by Ball Ball BB24 BB23 BB22 BB21 BB20 BB19 BB18 BB17 BB16 BB15 BB14 BB13 BB12 BB11 BB10 BB9 BB8 BB7 BB6 BB5 BB4 BB3 BB2 BB1 BA43 BA42 BA41 BA40 BA39 BA38 BA37 Signal Name VCC_DDR DDR_A_MA_3 DDR_A_MA_5 DDR_A_MA_7 VCC_DDR DDR_A_CKE_2 VCC_DDR DDR_B_BS_0 VCC_DDR DDR_B_MA_1 DDR_B_MA_5 DDR_B_MA_8 VCC_DDR DDR_B_MA_14 DDR_B_CKE_3 DDR_A_DQ_19 ---VSS DDR_A_DM_2 DDR_A_DQ_16 DDR_A_DQ_21 DDR_A_DQ_11 NC NC VCC_CKDDR VCC_CKDDR ---DDR_RCOMPYPU DDR_A_ODT_3 DDR_A_ODT_1 ---- 392 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball BA36 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 Signal Name ---DDR_A_ODT_2 DDR_A_CSB_0 DDR_A_WEB ---DDR_A_BS_0 DDR_B_CSB_3 DDR_B_CSB_1 ---DDR_B_ODT_2 DDR_B_CSB_2 DDR_B_CSB_0 ---DDR_A_MA_2 DDR_A_MA_6 DDR_A_MA_9 ---DDR_A_MA_14 DDR_A_CKE_3 DDR_B_MA_10 ---DDR_B_MA_2 DDR_B_MA_4 DDR_B_MA_7 ---DDR_B_MA_12 DDR_B_CKE_2 DDR_A_DQ_18 ------DDR_A_DQSB_2 DDR_A_DQ_20 DDR_A_DQ_10 Table 12-1. Ballout – Sorted by Ball Ball BA3 BA2 BA1 AY43 AY42 AY41 AY40 AY39 AY38 AY37 AY36 AY35 AY34 AY33 AY32 AY31 AY30 AY29 AY28 AY27 AY26 AY25 AY24 AY23 AY22 AY21 AY20 AY19 AY18 AY17 AY16 AY15 AY14 Signal Name ---RSVD VSS ---VCC_CKDDR VSS VSS ---DDR_A_MA_13 DDR3_A_CSB1 ---DDR_A_CSB_1 ---DDR_A_RASB VCC_DDR DDR_A_BS_1 ---DDR_B_ODT_3 ---DDR_B_MA_13 ---DDR_A_MA_1 DDR_B_RASB DDR_A_MA_4 ---DDR_A_MA_11 DDR_A_BS_2 DDR_A_CKE_0 ---DDR_B_BS_1 ---DDR_B_MA_3 ---- Table 12-1. Ballout – Sorted by Ball Ball AY13 AY12 AY11 AY10 AY9 AY8 AY7 AY6 AY5 AY4 AY3 AY2 AY1 AW43 AW42 AW41 AW40 AW39 AW38 AW37 AW36 AW35 AW34 AW33 AW32 AW31 AW30 AW29 AW28 AW27 AW26 AW25 AW24 Signal Name DDR_B_MA_9 DDR_B_MA_11 DDR_B_BS_2 ---DDR_A_DQ_23 ---DDR_A_DQS_2 DDR_A_DQ_17 ---VSS DDR_A_DQ_15 DDR_A_DQ_14 ---VSS RSVD VSS ---DDR_B_DQS_4 ---DDR_B_DQ_32 ---DDR_A_CASB ---DDR_A_CKB_2 DDR3_B_ODT3 DDR_B_CK_0 ---DDR_B_ODT_1 ---DDR_B_CKB_4 DDR_B_CASB ---VCC_DDR Datasheet 393 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AW23 AW22 AW21 AW20 AW19 AW18 AW17 AW16 AW15 AW14 AW13 AW12 AW11 AW10 AW9 AW8 AW7 AW6 AW5 AW4 AW3 AW2 AW1 AV43 AV42 AV41 AV40 AV39 AV38 AV37 AV36 AV35 AV34 Signal Name DDR_B_DQ_29 ---DDR_A_MA_8 VCC_DDR ---DDR_A_CKE_1 DDR_B_DQ_23 ---DDR_B_MA_0 ---DDR_B_DM_2 DDR_B_MA_6 DDR_B_CKE_0 ---DDR_B_DM_1 ---DDR_B_DQ_3 ---DDR_B_DQ_2 ---DDR_A_DM_1 DDR_A_DQS_1 DDR_A_DQSB_1 ---DDR_A_DQ_32 DDR_A_DQ_37 DDR_A_DQ_36 ---DDR_B_DQ_33 VSS ---VSS ---- Table 12-1. Ballout – Sorted by Ball Ball AV33 AV32 AV31 AV30 AV29 AV28 AV27 AV26 AV25 AV24 AV23 AV22 AV21 AV20 AV19 AV18 AV17 AV16 AV15 AV14 AV13 AV12 AV11 AV10 AV9 AV8 AV7 AV6 AV5 AV4 AV3 AV2 AV1 Signal Name DDR_A_CK_2 DDR_B_CK_2 DDR_B_CKB_0 ---DDR_B_CK_4 ---VSS VCC_DDR ---DDR_B_DQ_24 VSS ---VSS DDR_A_DQ_31 ---VCC_DDR VSS ---DDR_B_DQ_22 ---DDR_B_DQ_17 DDR_B_DQ_14 VSS ---VSS ---VSS DDR_B_DQS_0 ---DDR_A_DQ_8 DDR_A_DQ_9 VSS ---- Table 12-1. Ballout – Sorted by Ball Ball AU43 AU42 AU41 AU40 AU39 AU38 AU37 AU36 AU35 AU34 AU33 AU32 AU31 AU30 AU29 AU28 AU27 AU26 AU25 AU24 AU23 AU22 AU21 AU20 AU19 AU18 AU17 AU16 AU15 AU14 AU13 AU12 AU11 Signal Name DDR_A_DM_4 VSS ---DDR_A_DQ_33 DDR_B_DQSB_4 VSS DDR_B_DM_4 ---DDR_B_DQ_36 ---DDR_A_CKB_5 VSS DDR_A_CKB_0 ---DDR_B_CKB_3 ---DDR_B_CK_1 DDR_B_DQSB_3 ---VSS DDR_B_DQ_28 ---DDR_A_DQ_26 VSS ---DDR_A_DQSB_3 DDR_B_DQ_18 ---DDR_B_DQ_16 ---DDR_B_DQ_20 DDR_B_DQ_15 DDR_B_DQ_9 394 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AU10 AU9 AU8 AU7 AU6 AU5 AU4 AU3 AU2 AU1 AT43 AT42 AT41 AT40 AT39 AT38 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 AT29 AT28 AT27 AT26 AT25 AT24 AT23 AT22 AT21 Signal Name ---DDR_B_DQ_13 ---DDR_B_DQ_7 VSS DDR_B_DQSB_0 VSS ---DDR_A_DQ_12 DDR_A_DQ_13 ------------------------------DDR_A_CK_5 DDR_B_CKB_2 VSS ---VSS ---DDR_B_CKB_1 DDR_B_DQ_26 ---DDR_B_DQS_3 DDR_B_DQ_25 ---DDR_A_DQ_27 Table 12-1. Ballout – Sorted by Ball Ball AT20 AT19 AT18 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 AT9 AT8 AT7 AT6 AT5 AT4 AT3 AT2 AT1 AR43 AR42 AR41 AR40 AR39 AR38 AR37 AR36 AR35 AR34 AR33 AR32 AR31 Signal Name DDR_A_DQS_3 ---DDR_A_DQ_24 DDR_B_DQ_19 ---VSS ---VSS VSS DDR_B_DQ_8 ---------------------------------DDR_A_DQ_38 DDR_A_DQS_4 DDR_A_DQSB_4 DDR_B_DQ_44 VSS DDR_B_DQ_39 ---DDR_B_DQ_37 ---VSS VSS DDR_A_CK_0 Table 12-1. Ballout – Sorted by Ball Ball AR30 AR29 AR28 AR27 AR26 AR25 AR24 AR23 AR22 AR21 AR20 AR19 AR18 AR17 AR16 AR15 AR14 AR13 AR12 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AP43 AP42 AP41 Signal Name ---DDR_B_CK_3 ---VSS VSS ---DDR_B_DQ_30 VSS ---VSS VSS ---DDR_A_DQ_25 VSS ---DDR_B_DQSB_2 ---DDR_B_DQ_11 DDR_B_DQS_1 DDR_B_DQ_12 ---VSS ---DDR_B_DM_0 VSS DDR_A_DQ_6 DDR_A_DQ_7 DDR_A_DQ_3 DDR_A_DQ_2 ---VSS DDR_A_DQ_34 DDR_A_DQ_39 Datasheet 395 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AP40 AP39 AP38 AP37 AP36 AP35 AP34 AP33 AP32 AP31 AP30 AP29 AP28 AP27 AP26 AP25 AP24 AP23 AP22 AP21 AP20 AP19 AP18 AP17 AP16 AP15 AP14 AP13 AP12 AP11 AP10 AP9 AP8 Signal Name ------------------------DDR_B_CKB_5 DDR_A_CKB_3 ---DDR_A_CK_3 ---DDR_A_CK_1 DDR_B_DQ_27 ---VSS DDR_B_DM_3 ---RSVD DDR_A_DQ_30 ---VSS DDR_A_DQ_28 ---DDR_B_DQS_2 ---DDR_B_DQ_10 DDR_B_DQSB_1 ------------- Table 12-1. Ballout – Sorted by Ball Ball AP7 AP6 AP5 AP4 AP3 AP2 AP1 AN43 AN42 AN41 AN40 AN39 AN38 AN37 AN36 AN35 AN34 AN33 AN32 AN31 AN30 AN29 AN28 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 Signal Name ------------DDR_A_DQSB_0 DDR_A_DQS_0 VSS ---DDR_A_DQ_45 DDR_A_DQ_40 DDR_A_DQ_44 DDR_A_DQ_35 VSS DDR_B_DQ_35 DDR_B_DQ_34 DDR_B_DQ_38 ---DDR_B_CK_5 RSVD VSS ---VSS ---DDR_A_CKB_1 DDR_B_DQ_31 ---VSS VSS ---RSVD VSS ---DDR_A_DM_3 Table 12-1. Ballout – Sorted by Ball Ball AN17 AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AM43 AM42 AM41 AM40 AM39 AM38 AM37 AM36 AM35 AM34 AM33 AM32 AM31 AM30 AM29 Signal Name DDR_A_DQ_29 ---DDR3_DRAM_PW ROK ---VSS VSS VSS ---DDR_B_DQ_6 DDR_B_DQ_1 DDR_B_DQ_0 DDR_B_DQ_5 DDR_B_DQ_4 VSS DDR_A_DQ_1 DDR_A_DM_0 ---DDR_A_DM_5 VSS ---VSS DDR_A_DQ_41 DDR_B_DQ_41 DDR_B_DM_5 VSS DDR_B_DQ_40 DDR_B_DQ_45 VSS ---RSVD ---VSS 396 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AL43 AL42 AL41 AL40 AL39 Signal Name ---DDR_A_CKB_4 DDR_A_CK_4 ---VSS VSS ---RSVD VSS ---RSTINB PWROK ---CL_PWROK ---DDR_B_DQ_21 ---VSS DDR_RCOMPVOH VSS DDR_RCOMPVOL VSS DDR_VREF CL_VREF VSS ---DDR_A_DQ_5 DDR_A_DQ_0 ---DDR_A_DQ_46 DDR_A_DQS_5 DDR_A_DQSB_5 DDR_A_DQ_47 Table 12-1. Ballout – Sorted by Ball Ball AL38 AL37 AL36 AL35 AL34 AL33 AL32 AL31 AL30 AL29 AL28 AL27 AL26 AL25 AL24 AL23 AL22 AL21 AL20 AL19 AL18 AL17 AL16 AL15 AL14 AL13 AL12 AL11 AL10 AL9 AL8 AL7 AL6 Signal Name DDR_B_DQ_43 DDR_B_DQ_46 VSS DDR_B_DQS_5 DDR_B_DQSB_5 VSS DDR_B_DQ_47 VSS ---VCC_CL ---VCC_CL VCC_CL ---VCC_CL VCC_CL ---VCC_CL VCC_CL ---VCC_CL VCC_CL ---VCC_CL ---VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL Table 12-1. Ballout – Sorted by Ball Ball AL5 AL4 AL3 AL2 AL1 AK43 AK42 AK41 AK40 AK39 AK38 AK37 AK36 AK35 AK34 AK33 AK32 AK31 AK30 AK29 AK28 AK27 AK26 AK25 AK24 AK23 AK22 AK21 AK20 AK19 AK18 AK17 AK16 Signal Name VCC_CL DDR_RCOMPXPD DDR_A_DQ_4 DDR_RCOMPXPU ---VSS DDR_A_DQ_42 DDR_A_DQ_43 ------------------------------VCC_CL VCC_CL ---VCC_CL VCC_CL ---VCC_CL VCC_CL ---VCC_CL VCC_CL ---VCC_CL VCC_CL ---- Datasheet 397 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AK15 AK14 AK13 AK12 AK11 AK10 AK9 AK8 AK7 AK6 AK5 AK4 AK3 AK2 AK1 AJ43 AJ42 AJ41 AJ40 AJ39 AJ38 AJ37 AJ36 AJ35 AJ34 AJ33 AJ32 AJ31 AJ30 AJ29 AJ28 AJ27 AJ26 Signal Name VCC_CL VCC_CL ------------------------------VCC_CL VCC_CL VCC_CL ---DDR_A_DQ_52 DDR_A_DQ_53 DDR_A_DQ_48 VSS DDR_B_DQ_49 DDR_B_DQ_52 VSS DDR_B_DQ_53 DDR_B_DQ_42 VSS VSS VCC_CL VCC_CL VCC_CL ---VCC_CL VCC_CL Table 12-1. Ballout – Sorted by Ball Ball AJ25 AJ24 AJ23 AJ22 AJ21 AJ20 AJ19 AJ18 AJ17 AJ16 AJ15 AJ14 AJ13 AJ12 AJ11 AJ10 AJ9 AJ8 AJ7 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH43 AH42 AH41 AH40 AH39 AH38 AH37 AH36 Signal Name ---VCC_CL VCC_CL ---VCC_CL VCC_CL ---VCC_CL VCC_CL ---VCC_CL VCC_CL VCC_CL VCC VCC VCC VCC VCC VCC VCC VCC VCC_CL VCC_CL VCC_CL ---DDR_A_DQ_49 VSS ------------------- Table 12-1. Ballout – Sorted by Ball Ball AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH25 AH24 AH23 AH22 AH21 AH20 AH19 AH18 AH17 AH16 AH15 AH14 AH13 AH12 AH11 AH10 AH9 AH8 AH7 AH6 AH5 AH4 AH3 Signal Name ---------------------------------------------------------------------------------------------VCC ---- 398 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AH2 AH1 AG43 AG42 AG41 AG40 AG39 AG38 AG37 AG36 AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AG25 AG24 AG23 AG22 AG21 AG20 AG19 AG18 AG17 AG16 AG15 AG14 AG13 Signal Name VCC VCC ---DDR_A_DQS_6 DDR_A_DQSB_6 DDR_A_DM_6 DDR_B_DM_6 DDR_B_DQ_48 VSS DDR_B_DQSB_6 DDR_B_DQS_6 VSS DDR_B_DQ_54 RSVD VCC_CL VCC_CL VCC_CL ---VCC_CL VCC_CL VCC_CL VCC VCC VCC VCC VCC VCC VCC VCC ---VCC VCC VCC Table 12-1. Ballout – Sorted by Ball Ball AG12 AG11 AG10 AG9 AG8 AG7 AG6 AG5 AG4 AG3 AG2 AG1 AF43 AF42 AF41 AF40 AF39 AF38 AF37 AF36 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AF25 AF24 AF23 Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ---VSS DDR_A_DQ_55 DDR_A_DQ_54 ---DDR_A_DQ_50 DDR_B_DQ_61 VSS VSS DDR_B_DQ_50 DDR_B_DQ_55 DDR_B_DQ_51 RSVD VCC_CL VCC_CL VCC_CL ---VCC_CL VCC VCC VCC VSS Table 12-1. Ballout – Sorted by Ball Ball AF22 AF21 AF20 AF19 AF18 AF17 AF16 AF15 AF14 AF13 AF12 AF11 AF10 AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AE43 AE42 AE41 AE40 AE39 AE38 AE37 AE36 AE35 AE34 AE33 Signal Name VCC VSS VCC VSS VCC VCC ---VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS ---VCC VCC VCC ---DDR_A_DQ_60 DDR_A_DQ_61 DDR_A_DQ_51 ---------------------- Datasheet 399 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 AE15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 AE7 AE6 AE5 AE4 AE3 AE2 AE1 AD43 Signal Name ---------------VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC ------------------------------------VSS VSS VSS ---DDR_A_DQ_57 Table 12-1. Ballout – Sorted by Ball Ball AD42 AD41 AD40 AD39 AD38 AD37 AD36 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 Signal Name VSS ---DDR_A_DQ_56 VSS DDR_B_DM_7 VSS DDR_B_DQ_56 VSS DDR_B_DQ_60 VSS VCC_CL VCC_CL VCC_CL VCC_CL ---VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC ---VCC VCC CL_CLK CL_DATA VCC_EXP VCC_EXP Table 12-1. Ballout – Sorted by Ball Ball AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AC43 AC42 AC41 AC40 AC39 AC38 AC37 AC36 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AC25 AC24 AC23 AC22 AC21 AC20 Signal Name VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP ---VCC_EXP VCC_EXP ---DDR_A_DQS_7 DDR_A_DQSB_7 DDR_A_DM_7 DDR_A_DQ_62 VSS DDR_B_DQSB_7 DDR_B_DQS_7 VSS DDR_B_DQ_62 DDR_B_DQ_57 VCC_CL VCC_CL VCC_CL VCC_CL ---VCC VCC VCC VSS VCC VSS VCC VSS 400 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AC19 AC18 AC17 AC16 AC15 AC14 AC13 AC12 AC11 AC10 AC9 AC8 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AB43 AB42 AB41 AB40 AB39 AB38 AB37 AB36 AB35 AB34 AB33 AB32 AB31 AB30 Signal Name VCC VSS VCC ---VCC VCC VCC EXP_COMPI EXP_COMPO VSS DMI_TXN_2 DMI_TXP_2 VSS VCC VSS VCC_EXP VCC_EXP VCC_EXP ---VSS DDR_A_DQ_63 DDR_A_DQ_58 ---------------------------------- Table 12-1. Ballout – Sorted by Ball Ball AB29 AB28 AB27 AB26 AB25 AB24 AB23 AB22 AB21 AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AA43 AA42 AA41 AA40 Signal Name ------VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC ---------------------------------------DMI_RXP_3 VSS VSS ---FSB_BREQ0B FSB_RSB_1 DDR_A_DQ_59 Table 12-1. Ballout – Sorted by Ball Ball AA39 AA38 AA37 AA36 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 AA25 AA24 AA23 AA22 AA21 AA20 AA19 AA18 AA17 AA16 AA15 AA14 AA13 AA12 AA11 AA10 AA9 AA8 AA7 Signal Name RSVD VSS FSB_AB_35 DDR_B_DQ_59 VSS DDR_B_DQ_58 DDR_B_DQ_63 VCC_CL VCC_CL VCC_CL VCC_CL ---VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC ---VCC VCC VCC CL_RSTB RSVD RSVD RSVD VSS DMI_RXP_2 Datasheet 401 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball AA6 AA5 AA4 AA3 AA2 AA1 Y43 Y42 Y41 Y40 Y39 Y38 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Signal Name DMI_RXN_2 VSS DMI_RXN_3 VCC DMI_TXN_3 ---FSB_HITMB VSS ---FSB_TRDYB FSB_AB_34 FSB_AB_33 VSS FSB_AB_32 VSS FSB_AB_29 VSS VCC_CL VCC_CL VCC_CL VCC_CL ---VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC Table 12-1. Ballout – Sorted by Ball Ball Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 W43 W42 W41 W40 W39 W38 W37 W36 W35 W34 W33 W32 W31 W30 W29 W28 W27 Signal Name ---VCC VCC VCC RSVD VCC VSS DMI_RXN_1 DMI_RXP_1 VSS VCC VSS DMI_TXN_1 ---DMI_TXP_3 VSS ---FSB_BNRB FSB_DRDYB FSB_ADSB ------------------------------------VCC Table 12-1. Ballout – Sorted by Ball Ball W26 W25 W24 W23 W22 W21 W20 W19 W18 W17 W16 W15 W14 W13 W12 W11 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 V43 V42 V41 V40 V39 V38 V37 Signal Name VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC ------------------------------------DMI_TXP_1 VSS DMI_RXP_0 ---VSS FSB_AB_30 FSB_LOCKB ---VSS FSB_AB_31 VSS 402 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball V36 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 V25 V24 V23 V22 V21 V20 V19 V18 V17 V16 V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 Signal Name FSB_AB_22 FSB_AB_28 VSS FSB_AB_27 VSS RSVD VSS VSS ---VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ---VCC VCC VCC VCC VSS VCC VCC VSS DMI_TXP_0 DMI_TXN_0 VSS ---- Table 12-1. Ballout – Sorted by Ball Ball V3 V2 V1 U43 U42 U41 U40 U39 U38 U37 U36 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 U25 U24 U23 U22 U21 U20 U19 U18 U17 U16 U15 U14 Signal Name PEG_TXP_15 VSS DMI_RXN_0 ---FSB_HITB FSB_RSB_0 FSB_DBSYB FSB_RSB_2 VSS FSB_AB_17 FSB_AB_24 VSS FSB_ADSTBB_1 FSB_AB_25 HPL_CLKINN RSVD RSVD VSS ---VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ---VCC VCC Table 12-1. Ballout – Sorted by Ball Ball U13 U12 U11 U10 U9 U8 U7 U6 U5 U4 U3 U2 U1 T43 T42 T41 T40 T39 T38 T37 T36 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T25 T24 Signal Name VCC RSVD RSVD VCC VCC VSS VSS VCC VSS PEG_TXN_15 VCC PEG_TXP_14 ---FSB_DEFERB VSS ------------------------------------------------------- Datasheet 403 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball T23 T22 T21 T20 T19 T18 T17 T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 R43 R42 R41 R40 R39 R38 R37 R36 R35 R34 Signal Name ---------------------------------------------------------PEG_RXP_14 ---PEG_TXN_14 VSS ---FSB_DB_4 FSB_DB_2 FSB_DB_0 FSB_AB_21 FSB_AB_23 FSB_AB_19 VSS FSB_AB_26 FSB_AB_14 Table 12-1. Ballout – Sorted by Ball Ball R33 R32 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 Signal Name VSS HPL_CLKINP VSS RSVD RSVD ---VTT_FSB VTT_FSB ---VTT_FSB VTT_FSB ---VSS RSVD ---VCC VCC ---VCC VCC RSVD RSVD VSS PEG_RXN_13 PEG_RXP_13 VSS PEG_RXN_15 PEG_RXP_15 VSS PEG_RXN_14 VSS PEG_TXP_13 ---- Table 12-1. Ballout – Sorted by Ball Ball P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 Signal Name VSS FSB_AB_20 FSB_DB_1 ------------------------------VSS VTT_FSB ---VTT_FSB VTT_FSB ---VTT_FSB VTT_FSB ---VSS VCC ---VSS VSS ---VCC VCC ---------- 404 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 N43 N42 N41 N40 N39 N38 N37 N36 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N25 N24 N23 N22 N21 Signal Name ---------------------PEG_TXP_12 VSS PEG_TXN_13 ---FSB_DB_7 FSB_DB_6 FSB_DB_3 FSB_AB_18 FSB_AB_16 FSB_AB_12 VSS FSB_AB_15 FSB_AB_10 VSS FSB_AB_9 VSS ---VTT_FSB ---VSS VTT_FSB ---VTT_FSB VTT_FSB ---VSS Table 12-1. Ballout – Sorted by Ball Ball N20 N19 N18 N17 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 M43 M42 M41 M40 M39 M38 M37 M36 M35 M34 M33 M32 M31 Signal Name NC ---RSVD RSVD ---RSVD ---VSS VCC VCC VSS VCC VCC VSS VCC VSS PEG_TXN_12 VCC PEG_TXP_11 ---FSB_DSTBNB_0 FSB_DSTBPB_0 ---FSB_DINVB_0 FSB_DB_5 FSB_AB_11 VSS FSB_AB_13 VSS FSB_ADSTBB_0 VSS ---FSB_DB_34 Table 12-1. Ballout – Sorted by Ball Ball M30 M29 M28 M27 M26 M25 M24 M23 M22 M21 M20 M19 M18 M17 M16 M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 L43 L42 L41 Signal Name ---VTT_FSB ---VSS FSB_DB_47 ---VTT_FSB VTT_FSB ---VSS VSS ---RSVD VSS ---VSS ---CRT_DDC_CLK ---VSS VSS PEG_RXN_10 PEG_RXP_10 VSS PEG_RXN_12 PEG_RXP_12 PEG_RXP_11 ---PEG_TXN_11 VSS ---FSB_DB_10 FSB_DB_8 Datasheet 405 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball L40 L39 L38 L37 L36 L35 L34 L33 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 Signal Name VSS FSB_AB_4 FSB_REQB_2 FSB_AB_6 FSB_AB_7 FSB_REQB_1 ---VSS VSS VSS ---VSS ---FSB_DB_42 FSB_DB_45 ---VTT_FSB VTT_FSB ---VSS VSS ---RSVD RSVD ---RSVD ---CRT_DDC_DATA VCC VSS ---PEG_RXP_9 PEG_RXN_9 Table 12-1. Ballout – Sorted by Ball Ball L7 L6 L5 L4 L3 L2 L1 K43 K42 K41 K40 K39 K38 K37 K36 K35 K34 K33 K32 K31 K30 K29 K28 K27 K26 K25 K24 K23 K22 K21 K20 K19 K18 Signal Name VSS VCC VSS PEG_RXN_11 VSS PEG_TXP_10 ---VSS FSB_AB_8 FSB_DB_12 ------------------------FSB_DB_29 FSB_DB_36 ---FSB_DB_38 ---FSB_DB_43 VSS ---VTT_FSB VTT_FSB ---VSS ALLZTEST ---VSS Table 12-1. Ballout – Sorted by Ball Ball K17 K16 K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 J43 J42 J41 J40 J39 J38 J37 J36 J35 J34 J33 J32 J31 J30 J29 J28 Signal Name RSVD ---PEG_RXP_1 ---VSS VSS ------------------------PEG_TXN_9 VSS PEG_TXN_10 ---FSB_AB_3 FSB_DB_11 FSB_AB_5 FSB_DB_9 VSS FSB_REQB_4 ---VSS ---FSB_DINVB_1 VSS FSB_DB_32 ---FSB_DB_40 ---- 406 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball J27 J26 J25 J24 J23 J22 J21 J20 J19 J18 J17 J16 J15 J14 J13 J12 J11 J10 J9 J8 J7 J6 J5 J4 J3 J2 J1 H43 H42 H41 H40 H39 H38 Signal Name VSS FSB_DB_46 ---VTT_FSB VTT_FSB ---VSS BSEL1 ---BSEL2 EXP_EN ---PEG_RXN_1 ---ICH_SYNCB PEG_RXP_3 PEG_RXP_4 ---VSS ---VSS VCC VSS PEG_TXP_9 VCC VCC ---------------------- Table 12-1. Ballout – Sorted by Ball Ball H37 H36 H35 H34 H33 H32 H31 H30 H29 H28 H27 H26 H25 H24 H23 H22 H21 H20 H19 H18 H17 H16 H15 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5 Signal Name ------------FSB_DSTBNB_1 FSB_DB_30 VSS ---VSS ---FSB_DSTBNB_2 FSB_DB_44 ---VTT_FSB VTT_FSB ---VSS VSS ---RSVD VSS ---VSS ---VSS PEG_RXN_3 PEG_RXN_4 ------------------- Table 12-1. Ballout – Sorted by Ball Ball H4 H3 H2 H1 G43 G42 G41 G40 G39 G38 G37 G36 G35 G34 G33 G32 G31 G30 G29 G28 G27 G26 G25 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 Signal Name ------------FSB_REQB_3 VSS ---FSB_DB_13 FSB_BPRIB VSS FSB_DB_19 ---FSB_DSTBPB_1 ---FSB_DB_25 VSS FSB_DB_37 ---FSB_DINVB_2 ---FSB_DSTBPB_2 VTT_FSB ---VTT_FSB VTT_FSB ---VSS BSEL0 ---MTYPE SDVO_CTRLDATA ---RFU_G15 Datasheet 407 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 Signal Name ---VSS VSS VSS ---VSS ---VSS PEG_RXP_8 PEG_RXN_8 PEG_TXN_8 ---VCC VSS ---FSB_DB_15 FSB_DB_14 FSB_REQB_0 ---FSB_DB_18 VSS ---VSS ---FSB_DB_27 FSB_DB_33 FSB_DB_39 ---FSB_DB_41 ---VSS VTT_FSB ---- Table 12-1. Ballout – Sorted by Ball Ball F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 E43 E42 E41 E40 E39 E38 E37 E36 E35 Signal Name VTT_FSB VTT_FSB ---VSS XORTEST ---VSS RSVD ---VSS ---PEG_RXP_0 PEG_RXP_2 VCC ---VCC ---PEG_RXP_5 PEG_RXN_6 ---PEG_TXP_8 VSS PEG_TXP_7 ---VSS FSB_DB_20 FSB_DB_50 ---FSB_DB_21 ---FSB_DB_22 ---FSB_DB_28 Table 12-1. Ballout – Sorted by Ball Ball E34 E33 E32 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 Signal Name ---FSB_DINVB_3 VSS FSB_DB_35 ---VTT_FSB ---VTT_FSB VTT_FSB ---VSS VTT_FSB ---VSS TCEN ---EXP_SLR SDVO_CTRLCLK ---CRT_VSYNC ---PEG_RXN_0 PEG_RXN_2 VSS ---VSS ---PEG_RXN_5 ---PEG_RXP_6 ---VSS PEG_TXN_7 408 Datasheet Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball E1 D43 D42 D41 D40 D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 Signal Name VSS ---FSB_DB_52 FSB_DB_17 VSS ---FSB_DB_56 FSB_DB_57 ---FSB_DB_49 ---FSB_DB_59 FSB_DB_63 VSS ---VTT_FSB VTT_FSB VTT_FSB ---FSB_SCOMPB FSB_DVREF FSB_RCOMP ---VSS CRT_BLUEB CRT_GREENB ---VSS VSS VSS ---DPL_REFCLKINN PEG_TXN_0 Table 12-1. Ballout – Sorted by Ball Ball D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 Signal Name PEG_TXP_0 ---PEG_TXN_2 ---PEG_TXP_4 PEG_TXN_4 ---VCC VSS PEG_RXN_7 ---VSS FSB_DB_16 ---FSB_DB_53 FSB_DB_23 FSB_DSTBNB_3 ------FSB_DB_54 FSB_DB_60 FSB_DB_48 ---FSB_CPURSTB VTT_FSB VTT_FSB ---VTT_FSB VSS FSB_SCOMP ---VCCA_HPLL VCCA_DPLLB Table 12-1. Ballout – Sorted by Ball Ball C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32 Signal Name VCCD_CRT ---CRT_GREEN CRT_REDB VCCA_DAC ---CRT_HSYNC DPL_REFCLKINP VCC ---VSS PEG_TXP_2 VCC ------VSS VSS VSS ---PEG_RXP_7 VSS NC NC FSB_DB_51 FSB_DB_55 FSB_DB_24 FSB_DSTBPB_3 VSS ---FSB_DB_61 FSB_DB_31 FSB_DB_58 VSS Datasheet 409 Ballout and Package Information Table 12-1. Ballout – Sorted by Ball Ball B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 Signal Name VSS VTT_FSB VTT_FSB VTT_FSB VTT_FSB VSS FSB_SWING FSB_ACCVREF VSS VSS VCCDQ_CRT CRT_BLUE VSS CRT_RED VCC3_3 VCCA_DAC VCCAPLL_EXP VSS EXP_CLKINN EXP_CLKINP PEG_TXP_1 VSS PEG_TXP_3 ---PEG_TXN_3 Table 12-1. Ballout – Sorted by Ball Ball B6 B5 B4 B3 B2 B1 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 Signal Name PEG_TXN_5 PEG_TXP_5 PEG_TXN_6 PEG_TXP_6 NC ---TEST2 NC VSS ---VSS ---FSB_DB_26 ------VSS ---FSB_DB_62 ---VTT_FSB ---VTT_FSB ---VSS ---- Table 12-1. Ballout – Sorted by Ball Ball A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Signal Name VCCA_MPLL ---VCCA_DPLLA ---CRT_IREF ---VSS ---VCCA_EXP ---RSVD ---VSS ---PEG_TXN_1 ------VSS ---VSS ---VSS ------- 410 Datasheet Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name ALLZTEST BSEL0 BSEL1 BSEL2 CL_CLK CL_DATA CL_PWROK CL_RSTB CL_VREF CRT_BLUE CRT_BLUEB CRT_DDC_CLK CRT_DDC_DATA CRT_GREEN CRT_GREENB CRT_HSYNC CRT_IREF CRT_RED CRT_REDB CRT_VSYNC DDR_A_BS_0 DDR_A_BS_1 DDR_A_BS_2 DDR_A_CASB DDR_A_CK_0 DDR_A_CK_1 DDR_A_CK_2 DDR_A_CK_3 DDR_A_CK_4 DDR_A_CK_5 DDR_A_CKB_0 Ball K20 G20 J20 J18 AD13 AD12 AM15 AA12 AM5 B20 D20 M13 L13 C19 D19 C15 A20 B18 C18 E15 BA31 AY31 AY20 AW35 AR31 AP27 AV33 AP29 AM26 AT33 AU31 Table 12-2. Ballout – Sorted by Signal Signal Name DDR_A_CKB_1 DDR_A_CKB_2 DDR_A_CKB_3 DDR_A_CKB_4 DDR_A_CKB_5 DDR_A_CKE_0 DDR_A_CKE_1 DDR_A_CKE_2 DDR_A_CKE_3 DDR_A_CSB_0 DDR_A_CSB_1 DDR_A_CSB_2 DDR_A_CSB_3 DDR_A_DM_0 DDR_A_DM_1 DDR_A_DM_2 DDR_A_DM_3 DDR_A_DM_4 DDR_A_DM_5 DDR_A_DM_6 DDR_A_DM_7 DDR_A_DQ_0 DDR_A_DQ_1 DDR_A_DQ_10 DDR_A_DQ_11 DDR_A_DQ_12 DDR_A_DQ_13 DDR_A_DQ_14 DDR_A_DQ_15 DDR_A_DQ_16 DDR_A_DQ_17 Ball AN27 AW33 AP31 AM27 AU33 AY19 AW18 BB19 BA18 BA34 AY35 BB33 BB38 AN2 AW3 BB6 AN18 AU43 AM43 AG40 AC40 AM1 AN3 BA4 BB3 AU2 AU1 AY2 AY3 BB5 AY6 Table 12-2. Ballout – Sorted by Signal Signal Name DDR_A_DQ_18 DDR_A_DQ_19 DDR_A_DQ_2 DDR_A_DQ_20 DDR_A_DQ_21 DDR_A_DQ_22 DDR_A_DQ_23 DDR_A_DQ_24 DDR_A_DQ_25 DDR_A_DQ_26 DDR_A_DQ_27 DDR_A_DQ_28 DDR_A_DQ_29 DDR_A_DQ_3 DDR_A_DQ_30 DDR_A_DQ_31 DDR_A_DQ_32 DDR_A_DQ_33 DDR_A_DQ_34 DDR_A_DQ_35 DDR_A_DQ_36 DDR_A_DQ_37 DDR_A_DQ_38 DDR_A_DQ_39 DDR_A_DQ_4 DDR_A_DQ_40 DDR_A_DQ_41 DDR_A_DQ_42 DDR_A_DQ_43 DDR_A_DQ_44 DDR_A_DQ_45 Ball BA9 BB9 AR2 BA5 BB4 BC7 AY9 AT18 AR18 AU21 AT21 AP17 AN17 AR3 AP20 AV20 AV42 AU40 AP42 AN39 AV40 AV41 AR42 AP41 AL3 AN41 AM39 AK42 AK41 AN40 AN42 Datasheet 411 Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name DDR_A_DQ_46 DDR_A_DQ_47 DDR_A_DQ_48 DDR_A_DQ_49 DDR_A_DQ_5 DDR_A_DQ_50 DDR_A_DQ_51 DDR_A_DQ_52 DDR_A_DQ_53 DDR_A_DQ_54 DDR_A_DQ_55 DDR_A_DQ_56 DDR_A_DQ_57 DDR_A_DQ_58 DDR_A_DQ_59 DDR_A_DQ_6 DDR_A_DQ_60 DDR_A_DQ_61 DDR_A_DQ_62 DDR_A_DQ_63 DDR_A_DQ_7 DDR_A_DQ_8 DDR_A_DQ_9 DDR_A_DQS_0 DDR_A_DQS_1 DDR_A_DQS_2 DDR_A_DQS_3 DDR_A_DQS_4 DDR_A_DQS_5 DDR_A_DQS_6 DDR_A_DQS_7 DDR_A_DQSB_0 DDR_A_DQSB_1 Ball AL42 AL39 AJ40 AH43 AM2 AF39 AE40 AJ42 AJ41 AF41 AF42 AD40 AD43 AB41 AA40 AR5 AE42 AE41 AC39 AB42 AR4 AV4 AV3 AP2 AW2 AY7 AT20 AR41 AL41 AG42 AC42 AP3 AW1 Table 12-2. Ballout – Sorted by Signal Signal Name DDR_A_DQSB_2 DDR_A_DQSB_3 DDR_A_DQSB_4 DDR_A_DQSB_5 DDR_A_DQSB_6 DDR_A_DQSB_7 DDR_A_MA_0 DDR_A_MA_1 DDR_A_MA_10 DDR_A_MA_11 DDR_A_MA_12 DDR_A_MA_13 DDR_A_MA_14 DDR_A_MA_2 DDR_A_MA_3 DDR_A_MA_4 DDR_A_MA_5 DDR_A_MA_6 DDR_A_MA_7 DDR_A_MA_8 DDR_A_MA_9 DDR_A_ODT_0 DDR_A_ODT_1 DDR_A_ODT_2 DDR_A_ODT_3 DDR_A_RASB DDR_A_WEB DDR_B_BS_0 DDR_B_BS_1 DDR_B_BS_2 DDR_B_CASB DDR_B_CK_0 DDR_B_CK_1 Ball BA6 AU18 AR40 AL40 AG41 AC41 BB30 AY25 BB31 AY21 BC20 AY38 BA19 BA23 BB23 AY23 BB22 BA22 BB21 AW21 BA21 BB35 BA38 BA35 BA39 AY33 BA33 BB17 AY17 AY11 AW26 AW31 AU27 Table 12-2. Ballout – Sorted by Signal Signal Name DDR_B_CK_2 DDR_B_CK_3 DDR_B_CK_4 DDR_B_CK_5 DDR_B_CKB_0 DDR_B_CKB_1 DDR_B_CKB_2 DDR_B_CKB_3 DDR_B_CKB_4 DDR_B_CKB_5 DDR_B_CKE_0 DDR_B_CKE_1 DDR_B_CKE_2 DDR_B_CKE_3 DDR_B_CSB_0 DDR_B_CSB_1 DDR_B_CSB_2 DDR_B_CSB_3 DDR_B_DM_0 DDR_B_DM_1 DDR_B_DM_2 DDR_B_DM_3 DDR_B_DM_4 DDR_B_DM_5 DDR_B_DM_6 DDR_B_DM_7 DDR_B_DQ_0 DDR_B_DQ_1 DDR_B_DQ_10 DDR_B_DQ_11 DDR_B_DQ_12 DDR_B_DQ_13 DDR_B_DQ_14 Ball AV32 AR29 AV29 AN33 AV31 AT27 AT32 AU29 AW27 AP32 AW11 BC12 BA10 BB10 BA25 BA29 BA26 BA30 AR7 AW9 AW13 AP23 AU37 AM37 AG39 AD38 AN7 AN8 AP13 AR13 AR11 AU9 AV12 412 Datasheet Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name DDR_B_DQ_15 DDR_B_DQ_16 DDR_B_DQ_17 DDR_B_DQ_18 DDR_B_DQ_19 DDR_B_DQ_2 DDR_B_DQ_20 DDR_B_DQ_21 DDR_B_DQ_22 DDR_B_DQ_23 DDR_B_DQ_24 DDR_B_DQ_25 DDR_B_DQ_26 DDR_B_DQ_27 DDR_B_DQ_28 DDR_B_DQ_29 DDR_B_DQ_3 DDR_B_DQ_30 DDR_B_DQ_31 DDR_B_DQ_32 DDR_B_DQ_33 DDR_B_DQ_34 DDR_B_DQ_35 DDR_B_DQ_36 DDR_B_DQ_37 DDR_B_DQ_38 DDR_B_DQ_39 DDR_B_DQ_4 DDR_B_DQ_40 DDR_B_DQ_41 DDR_B_DQ_42 DDR_B_DQ_43 DDR_B_DQ_44 Ball AU12 AU15 AV13 AU17 AT17 AW5 AU13 AM13 AV15 AW17 AV24 AT23 AT26 AP26 AU23 AW23 AW7 AR24 AN26 AW37 AV38 AN36 AN37 AU35 AR35 AN35 AR37 AN5 AM35 AM38 AJ34 AL38 AR39 Table 12-2. Ballout – Sorted by Signal Signal Name DDR_B_DQ_45 DDR_B_DQ_46 DDR_B_DQ_47 DDR_B_DQ_48 DDR_B_DQ_49 DDR_B_DQ_5 DDR_B_DQ_50 DDR_B_DQ_51 DDR_B_DQ_52 DDR_B_DQ_53 DDR_B_DQ_54 DDR_B_DQ_55 DDR_B_DQ_56 DDR_B_DQ_57 DDR_B_DQ_58 DDR_B_DQ_59 DDR_B_DQ_6 DDR_B_DQ_60 DDR_B_DQ_61 DDR_B_DQ_62 DDR_B_DQ_63 DDR_B_DQ_7 DDR_B_DQ_8 DDR_B_DQ_9 DDR_B_DQS_0 DDR_B_DQS_1 DDR_B_DQS_2 DDR_B_DQS_3 DDR_B_DQS_4 DDR_B_DQS_5 DDR_B_DQS_6 DDR_B_DQS_7 DDR_B_DQSB_0 Ball AM34 AL37 AL32 AG38 AJ38 AN6 AF35 AF33 AJ37 AJ35 AG33 AF34 AD36 AC33 AA34 AA36 AN9 AD34 AF38 AC34 AA33 AU7 AT11 AU11 AV6 AR12 AP15 AT24 AW39 AL35 AG35 AC36 AU5 Table 12-2. Ballout – Sorted by Signal Signal Name DDR_B_DQSB_1 DDR_B_DQSB_2 DDR_B_DQSB_3 DDR_B_DQSB_4 DDR_B_DQSB_5 DDR_B_DQSB_6 DDR_B_DQSB_7 DDR_B_MA_0 DDR_B_MA_1 DDR_B_MA_10 DDR_B_MA_11 DDR_B_MA_12 DDR_B_MA_13 DDR_B_MA_14 DDR_B_MA_2 DDR_B_MA_3 DDR_B_MA_4 DDR_B_MA_5 DDR_B_MA_6 DDR_B_MA_7 DDR_B_MA_8 DDR_B_MA_9 DDR_B_ODT_0 DDR_B_ODT_1 DDR_B_ODT_2 DDR_B_ODT_3 DDR_B_RASB DDR_B_WEB DDR_RCOMPVOH DDR_RCOMPVOL DDR_RCOMPXPD DDR_RCOMPXPU DDR_RCOMPYPD Ball AP12 AR15 AU26 AU39 AL34 AG36 AC37 AW15 BB15 BA17 AY12 BA11 AY27 BB11 BA15 AY15 BA14 BB14 AW12 BA13 BB13 AY13 BB27 AW29 BA27 AY29 AY24 BB25 AM10 AM8 AL4 AL2 BB40 Datasheet 413 Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name DDR_RCOMPYPU DDR_VREF DDR3_A_CSB1 DDR3_A_MA0 DDR3_A_WEB DDR3_B_ODT3 DDR3_DRAM_PW ROK DDR3_DRAMRST B DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 DPL_REFCLKINN DPL_REFCLKINP EXP_CLKINN EXP_CLKINP EXP_COMPI EXP_COMPO EXP_EN Ball BA40 AM6 AY37 BB29 BB34 AW32 AN15 BC16 V1 Y9 AA6 AA4 W2 Y8 AA7 AB3 V6 Y4 AC9 AA2 V7 W4 AC8 Y2 D13 C14 B13 B12 AC12 AC11 J17 Table 12-2. Ballout – Sorted by Signal Signal Name EXP_SLR FSB_AB_10 FSB_AB_11 FSB_AB_12 FSB_AB_13 FSB_AB_14 FSB_AB_15 FSB_AB_16 FSB_AB_17 FSB_AB_18 FSB_AB_19 FSB_AB_20 FSB_AB_21 FSB_AB_22 FSB_AB_23 FSB_AB_24 FSB_AB_25 FSB_AB_26 FSB_AB_27 FSB_AB_28 FSB_AB_29 FSB_AB_3 FSB_AB_30 FSB_AB_31 FSB_AB_32 FSB_AB_33 FSB_AB_34 FSB_AB_35 FSB_AB_4 FSB_AB_5 FSB_AB_6 FSB_AB_7 FSB_AB_8 Ball E18 N34 M38 N37 M36 R34 N35 N38 U37 N39 R37 P42 R39 V36 R38 U36 U33 R35 V33 V35 Y34 J42 V42 V38 Y36 Y38 Y39 AA37 L39 J40 L37 L36 K42 Table 12-2. Ballout – Sorted by Signal Signal Name FSB_AB_9 FSB_ACCVREF FSB_ADSB FSB_ADSTBB_0 FSB_ADSTBB_1 FSB_BNRB FSB_BPRIB FSB_BREQ0B FSB_CPURSTB FSB_DB_0 FSB_DB_1 FSB_DB_10 FSB_DB_11 FSB_DB_12 FSB_DB_13 FSB_DB_14 FSB_DB_15 FSB_DB_16 FSB_DB_17 FSB_DB_18 FSB_DB_19 FSB_DB_2 FSB_DB_20 FSB_DB_21 FSB_DB_22 FSB_DB_23 FSB_DB_24 FSB_DB_25 FSB_DB_26 FSB_DB_27 FSB_DB_28 FSB_DB_29 FSB_DB_3 Ball N32 B24 W40 M34 U34 W42 G39 AA42 C31 R40 P41 L42 J41 K41 G40 F41 F42 C42 D41 F38 G37 R41 E42 E39 E37 C39 B39 G33 A37 F33 E35 K32 N40 414 Datasheet Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name FSB_DB_30 FSB_DB_31 FSB_DB_32 FSB_DB_33 FSB_DB_34 FSB_DB_35 FSB_DB_36 FSB_DB_37 FSB_DB_38 FSB_DB_39 FSB_DB_4 FSB_DB_40 FSB_DB_41 FSB_DB_42 FSB_DB_43 FSB_DB_44 FSB_DB_45 FSB_DB_46 FSB_DB_47 FSB_DB_48 FSB_DB_49 FSB_DB_5 FSB_DB_50 FSB_DB_51 FSB_DB_52 FSB_DB_53 FSB_DB_54 FSB_DB_55 FSB_DB_56 FSB_DB_57 FSB_DB_58 FSB_DB_59 FSB_DB_6 Ball H32 B34 J31 F32 M31 E31 K31 G31 K29 F31 R42 J29 F29 L27 K27 H26 L26 J26 M26 C33 D35 M39 E41 B41 D42 C40 C35 B40 D38 D37 B33 D33 N41 Table 12-2. Ballout – Sorted by Signal Signal Name FSB_DB_60 FSB_DB_61 FSB_DB_62 FSB_DB_63 FSB_DB_7 FSB_DB_8 FSB_DB_9 FSB_DBSYB FSB_DEFERB FSB_DINVB_0 FSB_DINVB_1 FSB_DINVB_2 FSB_DINVB_3 FSB_DRDYB FSB_DSTBNB_0 FSB_DSTBNB_1 FSB_DSTBNB_2 FSB_DSTBNB_3 FSB_DSTBPB_0 FSB_DSTBPB_1 FSB_DSTBPB_2 FSB_DSTBPB_3 FSB_DVREF FSB_HITB FSB_HITMB FSB_LOCKB FSB_RCOMP FSB_REQB_0 FSB_REQB_1 FSB_REQB_2 FSB_REQB_3 FSB_REQB_4 FSB_RSB_0 Ball C34 B35 A32 D32 N42 L41 J39 U40 T43 M40 J33 G29 E33 W41 M43 H33 H27 C38 M42 G35 G27 B38 D24 U42 Y43 V41 D23 F40 L35 L38 G43 J37 U41 Table 12-2. Ballout – Sorted by Signal Signal Name FSB_RSB_1 FSB_RSB_2 FSB_SCOMP FSB_SCOMPB FSB_SWING FSB_TRDYB HPL_CLKINN HPL_CLKINP ICH_SYNCB MTYPE NC NC NC NC NC NC NC NC NC NC PEG_RXN_0 PEG_RXN_1 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 Ball AA41 U39 C25 D25 B25 Y40 U32 R32 J13 G18 BC42 BC2 BB43 BB2 BB1 N20 B43 B42 B2 A42 E13 J15 M9 L4 M6 R10 R4 R7 E12 H12 H11 E7 F6 Datasheet 415 Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name PEG_RXN_7 PEG_RXN_8 PEG_RXN_9 PEG_RXP_0 PEG_RXP_1 PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15 PEG_RXP_2 PEG_RXP_3 PEG_RXP_4 PEG_RXP_5 PEG_RXP_6 PEG_RXP_7 PEG_RXP_8 PEG_RXP_9 PEG_TXN_0 PEG_TXN_1 PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15 PEG_TXN_2 PEG_TXN_3 PEG_TXN_4 PEG_TXN_5 PEG_TXN_6 PEG_TXN_7 Ball D2 G5 L8 F13 K15 M8 M4 M5 R9 T4 R6 F12 J12 J11 F7 E5 C2 G6 L9 D12 A10 K1 M2 N4 P1 T2 U4 D9 B7 D6 B6 B4 E2 Table 12-2. Ballout – Sorted by Signal Signal Name PEG_TXN_8 PEG_TXN_9 PEG_TXP_0 PEG_TXP_1 PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15 PEG_TXP_2 PEG_TXP_3 PEG_TXP_4 PEG_TXP_5 PEG_TXP_6 PEG_TXP_7 PEG_TXP_8 PEG_TXP_9 PWROK RFU_G15 RSTINB RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Ball G4 K3 D11 B11 L2 N2 P3 R2 U2 V3 C10 B9 D7 B5 B3 F2 F4 J4 AM17 G15 AM18 BA2 AW42 AP21 AN32 AN21 AM31 AM21 AG32 AF32 AA39 AA11 AA10 Table 12-2. Ballout – Sorted by Signal Signal Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SDVO_CTRLCLK SDVO_CTRLDATA TCEN TEST0 TEST1 TEST2 VCC VCC VCC VCC Ball AA9 Y12 V31 U31 U30 U12 U11 R30 R29 R20 R13 R12 N18 N17 N15 M18 L18 L17 L15 K17 H18 F17 A14 E17 G17 E20 BC43 BC1 A43 AJ12 AJ11 AJ10 AJ9 416 Datasheet Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball AJ8 AJ7 AJ6 AJ5 AH4 AH2 AH1 AG24 AG23 AG22 AG21 AG20 AG19 AG18 AG17 AG15 AG14 AG13 AG12 AG11 AG10 AG9 AG8 AG7 AG6 AG5 AG4 AG3 AG2 AF26 AF25 AF24 AF22 Table 12-2. Ballout – Sorted by Signal Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball AF20 AF18 AF17 AF15 AF14 AF13 AF12 AF11 AF3 AF2 AF1 AE27 AE26 AE25 AE23 AE21 AE19 AE17 AD27 AD26 AD24 AD22 AD20 AD18 AD17 AD15 AD14 AC27 AC26 AC25 AC23 AC21 AC19 Table 12-2. Ballout – Sorted by Signal Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball AC17 AC15 AC14 AC13 AC6 AB27 AB26 AB24 AB22 AB20 AB18 AB17 AA27 AA26 AA25 AA23 AA21 AA19 AA17 AA15 AA14 AA13 AA3 Y27 Y26 Y24 Y22 Y20 Y18 Y17 Y15 Y14 Y13 Datasheet 417 Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball Y11 Y6 W27 W26 W25 W23 W21 W19 W18 W17 V27 V26 V25 V24 V23 V22 V21 V20 V19 V18 V17 V15 V14 V13 V12 V10 V9 U26 U25 U24 U23 U22 U21 Table 12-2. Ballout – Sorted by Signal Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball U20 U19 U18 U17 U15 U14 U13 U10 U9 U6 U3 R18 R17 R15 R14 P20 P15 P14 N12 N11 N9 N8 N6 N3 L12 L6 J6 J3 J2 G2 F11 F9 D4 Table 12-2. Ballout – Sorted by Signal Signal Name VCC VCC VCC_CKDDR VCC_CKDDR VCC_CKDDR VCC_CKDDR VCC_CKDDR VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL Ball C13 C9 BB42 BB41 BA43 BA42 AY42 AL29 AL27 AL26 AL24 AL23 AL21 AL20 AL18 AL17 AL15 AL13 AL12 AL11 AL10 AL9 AL8 AL7 AL6 AL5 AK30 AK29 AK27 AK26 AK24 AK23 AK21 418 Datasheet Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL Ball AK20 AK18 AK17 AK15 AK14 AK3 AK2 AK1 AJ31 AJ30 AJ29 AJ27 AJ26 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AJ15 AJ14 AJ13 AJ4 AJ3 AJ2 AG31 AG30 AG29 AG27 AG26 AG25 AF31 AF30 Table 12-2. Ballout – Sorted by Signal Signal Name VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR Ball AF29 AF27 AD32 AD31 AD30 AD29 AC32 AC31 AC30 AC29 AA32 AA31 AA30 AA29 Y32 Y31 Y30 Y29 BC39 BC34 BC30 BC26 BC22 BC18 BC14 BB39 BB37 BB32 BB28 BB26 BB24 BB20 BB18 Table 12-2. Ballout – Sorted by Signal Signal Name VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC3_3 VCCA_DAC VCCA_DAC VCCA_DPLLA VCCA_DPLLB VCCA_EXP VCCA_HPLL VCCA_MPLL VCCAPLL_EXP VCCD_CRT VCCDQ_CRT VSS VSS Ball BB16 BB12 AY32 AW24 AW20 AV26 AV18 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD2 AD1 AC4 AC3 AC2 B17 C17 B16 A22 C22 A16 C23 A24 B15 C21 B21 BC41 BC37 Datasheet 419 Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball BC32 BC28 BC24 BC10 BC5 BC3 BB7 BA1 AY41 AY40 AY4 AW43 AW41 AV37 AV35 AV27 AV23 AV21 AV17 AV11 AV9 AV7 AV2 AU42 AU38 AU32 AU24 AU20 AU6 AU4 AT31 AT29 AT15 Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball AT13 AT12 AR38 AR33 AR32 AR27 AR26 AR23 AR21 AR20 AR17 AR9 AR6 AP43 AP24 AP18 AP1 AN38 AN31 AN29 AN24 AN23 AN20 AN13 AN12 AN11 AN4 AM42 AM40 AM36 AM33 AM29 AM24 Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball AM23 AM20 AM11 AM9 AM7 AM4 AL36 AL33 AL31 AK43 AJ39 AJ36 AJ33 AJ32 AH42 AG37 AG34 AF43 AF37 AF36 AF23 AF21 AF19 AF10 AF9 AF8 AF7 AF6 AF5 AE24 AE22 AE20 AE18 420 Datasheet Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball AE4 AE3 AE2 AD42 AD39 AD37 AD35 AD33 AD25 AD23 AD21 AD19 AC38 AC35 AC24 AC22 AC20 AC18 AC10 AC7 AC5 AB43 AB25 AB23 AB21 AB19 AB2 AB1 AA38 AA35 AA24 AA22 AA20 Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball AA18 AA8 AA5 Y42 Y37 Y35 Y33 Y25 Y23 Y21 Y19 Y10 Y7 Y5 Y1 W24 W22 W20 W3 V43 V39 V37 V34 V32 V30 V29 V11 V8 V5 V2 U38 U35 U29 Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball U27 U8 U7 U5 T42 T1 R36 R33 R31 R21 R11 R8 R5 R3 P43 P30 P21 P18 P17 P2 N36 N33 N31 N27 N21 N13 N10 N7 N5 M37 M35 M33 M27 Datasheet 421 Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball M21 M20 M17 M15 M11 M10 M7 M1 L40 L33 L32 L31 L29 L21 L20 L11 L7 L5 L3 K43 K26 K21 K18 K13 K12 K2 J38 J35 J32 J27 J21 J9 J7 Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball J5 H31 H29 H21 H20 H17 H15 H13 G42 G38 G32 G21 G13 G12 G11 G9 G7 G1 F37 F35 F27 F21 F18 F15 F3 E43 E32 E24 E21 E11 E9 E3 E1 Table 12-2. Ballout – Sorted by Signal Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT_FSB Ball D40 D31 D21 D17 D16 D15 D3 C43 C26 C11 C6 C5 C4 C1 B37 B32 B31 B26 B23 B22 B19 B14 B10 A41 A39 A34 A26 A18 A12 A7 A5 A3 R27 422 Datasheet Ballout and Package Information Table 12-2. Ballout – Sorted by Signal Signal Name VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB Ball R26 R24 R23 P29 P27 P26 P24 P23 N29 N26 N24 N23 M29 M24 M23 L24 L23 Table 12-2. Ballout – Sorted by Signal Signal Name VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB Ball K24 K23 J24 J23 H24 H23 G26 G24 G23 F26 F24 F23 E29 E27 E26 E23 D29 Table 12-2. Ballout – Sorted by Signal Signal Name VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB XORTEST Ball D28 D27 C30 C29 C27 B30 B29 B28 B27 A30 A28 F20 Datasheet 423 Package Specifications 13 Package Specifications The (G)MCH is available in a 34 mm [1.34 in] x 34 mm [1.34 in] Flip Chip Ball Grid Array (FC-BGA) package with 1226 solder balls. The (G)MCH package uses a “balls anywhere” concept. Minimum ball pitch is 0.8 mm [0.031 in], but ball ordering does not follow a 0.8 mm grid. Figure 13-1 shows the package dimensions. 424 Datasheet Package Specifications Figure 13-1. (G)MCH Package Drawing § Datasheet 425 Testability 14 Testability In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin connected to it which allows for pad to ball to trace connection testing. The XOR testing methodology is to boot the part using straps to enter XOR mode (A description of the boot process follows). Once in XOR mode, all of the pins of an XOR chain are driven to logic 1. This action will force the output of that XOR chain to either a 1 if the number of the pins making up the chain is even or a 0 if the number of the pins making up the chain is odd. Once a valid output is detected on the XOR chain output, a walking 0 pattern is moved from one end of the chain to the other. Every time the walking 0 is applied to a pin on the chain, the output will toggle. If the output does not toggle, there is a disconnect somewhere between die, package, and board and the system can be considered a failure. 14.1 XOR Test Mode Initialization Figure 14-1. XOR Test Mode Initialization Cycles CL_PWROK PWROK CL_RST# RSTIN# STRAP PINS HCLKP/GCLKP HCLKN/GCLKN XOR inputs XOR output X XOR 426 Datasheet Testability The above figure shows the wave forms to be able to boot the part into XOR mode. The straps that need to be controlled during this boot process are BSEL[2:0], SDVO_CTRLDATA, EXP_EM, EXP_SLR, and XORTEST. On Broadwater platforms, all strap values must be driven before PWROK asserts. BSEL0 must be a 1. BSEL[2:1] need to be defined values, but logic value in any order will do. XORTEST must be driven to 0. If SDVO is present in the design, SDVO_CTRLDATA must be pulled to logic 1. Depending on if Static Lane Reversal is used and if the SDVO/PCI Express Coexistence is selected, EXP_SLR and EXP_EN must be pulled in a valid manner. Because of the different functionalities of the SDVO/PCI Express interface, not all of the pins will be used in all implementations. Due to the need to minimize test points and unnecessary routing, the XOR Chain 14 is dynamic depending on the values of SDVO_CTRLDATA, EXP_SLR, and EXP_EN. See Table 14-1 for what parts of XOR Chain 14 become valid XOR inputs depending on the use of SDVO_CTRLDATA, EXP_SLR, and EXP_EN. Table 14-1. XOR Chain 14 functionality SDVO_CTRLDATA EXP_EN EXP_SLR XOR Chain 14 EXP_RXP[15:0] EXP_RXN[15:0] EXP_TXP[15:0] EXP_TXN[15:0] EXP_RXP[15:0] EXP_RXN[15:0] EXP_TXP[15:0] EXP_TXN[15:0] EXP_RXP[15:8] EXP_RXN[15:8] EXP_TXP[15:8] EXP_TXN[15:8] EXP_RXP[7:0] EXP_RXN[7:0] EXP_TXP[7:0] EXP_TXN[7:0] EXP_RXP[15:0] EXP_RXN[15:0] EXP_TXP[15:0] EXP_TXN[15:0] EXP_RXP[15:0] EXP_RXN[15:0] EXP_TXP[15:0] EXP_TXN[15:0] 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Datasheet 427 Testability 14.2 XOR Chain Definition The (G)MCH chipset has 15 XOR chains. The XOR chain outputs are driven out on the following output pins. During full-width testing, XOR chain outputs will be visible on both pins. Table 14-2. XOR Chain Outputs XOR Chain xor_out0 xor_out1 xor_out2 xor_out3 xor_out4 xor_out5 xor_out6 xor_out7 xor_out8 xor_out9 xor_out10 xor_out11 xor_out12 xor_out13 xor_out14 Output Pins ALLZTEST XORTEST ICH_SYNC# RSVD RSVD RSVD BSEL1 BSEL2 RSVD RSVD EXP_SLR EXP_EN MTYPE RSVD BSEL0 Coordinate Location K20 F20 J13 F17 AA9 AA10 J20 J18 AA11 Y12 E18 J17 G18 K17 G20 428 Datasheet Testability 14.3 XOR Chains The following tables lists the XOR chains. Table 14-3. XOR Chain 0 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Ball B33 D35 B40 E41 C40 B41 A32 B35 C33 C35 D38 D37 D42 C34 D32 D33 B34 A37 B39 D41 C42 C39 E37 E35 E42 F38 E39 G33 F33 Signal Name FSB_DB_58 FSB_DB_49 FSB_DB_55 FSB_DB_50 FSB_DB_53 FSB_DB_51 FSB_DB_62 FSB_DB_61 FSB_DB_48 FSB_DB_54 FSB_DB_56 FSB_DB_57 FSB_DB_52 FSB_DB_60 FSB_DB_63 FSB_DB_59 FSB_DB_31 FSB_DB_26 FSB_DB_24 FSB_DB_17 FSB_DB_16 FSB_DB_23 FSB_DB_22 FSB_DB_28 FSB_DB_20 FSB_DB_18 FSB_DB_21 FSB_DB_25 FSB_DB_27 Table 14-3. XOR Chain 0 Pin Count 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Ball G37 H32 K32 F29 H26 J26 G31 F32 F31 E31 J29 M26 L26 J31 K27 L27 K29 K31 M31 J41 R42 F42 M39 F41 G40 J39 K41 N40 N41 Signal Name FSB_DB_19 FSB_DB_30 FSB_DB_29 FSB_DB_41 FSB_DB_44 FSB_DB_46 FSB_DB_37 FSB_DB_33 FSB_DB_39 FSB_DB_35 FSB_DB_40 FSB_DB_47 FSB_DB_45 FSB_DB_32 FSB_DB_43 FSB_DB_42 FSB_DB_38 FSB_DB_36 FSB_DB_34 FSB_DB_11 FSB_DB_4 FSB_DB_15 FSB_DB_5 FSB_DB_14 FSB_DB_13 FSB_DB_9 FSB_DB_12 FSB_DB_3 FSB_DB_6 Datasheet 429 Testability Table 14-3. XOR Chain 0 Pin Count 59 60 61 62 63 64 Ball R41 L42 L41 P41 N42 R40 Signal Name FSB_DB_2 FSB_DB_10 FSB_DB_8 FSB_DB_1 FSB_DB_7 FSB_DB_0 Table 14-4. XOR Chain 1 Pin Count 23 24 25 26 27 28 29 Ball # V42 R35 U36 U33 Y39 V33 V36 R38 U34 R37 AA37 U37 N39 V38 R39 Y36 V35 P42 Signal Name FSB_AB_30 FSB_AB_26 FSB_AB_24 FSB_AB_25 FSB_AB_34 FSB_AB_27 FSB_AB_22 FSB_AB_23 FSB_ADSTBB_1 FSB_AB_19 FSB_AB_35 FSB_AB_17 FSB_AB_18 FSB_AB_31 FSB_AB_21 FSB_AB_32 FSB_AB_28 FSB_AB_20 Table 14-4. XOR Chain 1 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Ball # L37 N35 L36 L39 M38 L38 J37 N34 L35 F40 M34 M36 N37 J40 K42 R34 N32 N38 G43 J42 Y38 Y34 Signal Name FSB_AB_6 FSB_AB_15 FSB_AB_7 FSB_AB_4 FSB_AB_11 FSB_REQB_2 FSB_REQB_4 FSB_AB_10 FSB_REQB_1 FSB_REQB_0 FSB_ADSTBB_0 FSB_AB_13 FSB_AB_12 FSB_AB_5 FSB_AB_8 FSB_AB_14 FSB_AB_9 FSB_AB_16 FSB_REQB_3 FSB_AB_3 FSB_AB_33 FSB_AB_29 30 31 32 33 34 35 36 37 38 39 40 Table 14-5. XOR Chain 2 Pin Count 1 2 3 4 5 6 7 8 9 10 Ball # G35 H33 U42 Y40 AA41 Y43 G27 H27 M42 M43 Signal Name FSB_DSTBPB_1 FSB_DSTBNB_1 FSB_HITB FSB_TRDYB FSB_RSB_1 FSB_HITMB FSB_DSTBPB_2 FSB_DSTBNB_2 FSB_DSTBPB_0 FSB_DSTBNB_0 430 Datasheet Testability Table 14-5. XOR Chain 2 Pin Count 11 12 13 14 Ball # V41 W42 C31 G39 Signal Name FSB_LOCKB FSB_BNRB FSB_CPURSTB FSB_BPRIB Table 14-7. XOR Chain 4 Pin Count 8 9 10 11 12 Ball # BB30 AW33 AV33 AR31 AU31 AN27 AP27 BA21 BA23 BB23 AY23 BB21 AW18 BB22 AY25 AW21 BA22 AY19 AU18 AN18 BA6 BB6 AW1 AW3 AP3 AN2 Signal Name DDR_A_MA_0 DDR_A_CKB_2 DDR_A_CK_2 DDR_A_CK_0 DDR_A_CKB_0 DDR_A_CKB_1 DDR_A_CK_1 DDR_A_MA_9 DDR_A_MA_2 DDR_A_MA_3 DDR_A_MA_4 DDR_A_MA_7 DDR_A_CKE_1 DDR_A_MA_5 DDR_A_MA_1 DDR_A_MA_8 DDR_A_MA_6 DDR_A_CKE_0 DDR_A_DQSB_3 DDR_A_DM_3 DDR_A_DQSB_2 DDR_A_DM_2 DDR_A_DQSB_1 DDR_A_DM_1 DDR_A_DQSB_0 DDR_A_DM_0 Table 14-6. XOR Chain 3 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 Ball # B38 C38 E33 J33 U40 U39 W41 U41 T43 G29 M40 W40 AA42 Signal Name FSB_DSTBPB_3 FSB_DSTBNB_3 FSB_DINVB_3 FSB_DINVB_1 FSB_DBSYB FSB_RSB_2 FSB_DRDYB FSB_RSB_0 FSB_DEFERB FSB_DINVB_2 FSB_DINVB_0 FSB_ADSB FSB_BREQ0B 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Table 14-7. XOR Chain 4 Pin Count 1 2 3 4 5 6 7 Ball # BB35 AY35 AY37 BA38 BB31 BA34 BB29 Signal Name DDR_A_ODT_0 DDR_A_CSB_1 DDR3_A_CSB1 DDR_A_ODT_1 DDR_A_MA_10 DDR_A_CSB_0 DDR3_A_MA0 30 31 32 33 Datasheet 431 Testability Table 14-9. XOR Chain 6 Table 14-8. XOR Chain 5 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ball # AC41 AC40 AG41 AG40 AL40 AM43 AR40 AU43 AY38 AW35 AY31 BA31 BB34 AY33 BA33 AY20 AY21 BA19 BC20 Signal Name DDR_A_DQSB_7 DDR_A_DM_7 DDR_A_DQSB_6 DDR_A_DM_6 DDR_A_DQSB_5 DDR_A_DM_5 DDR_A_DQSB_4 DDR_A_DM_4 DDR_A_MA_13 DDR_A_CASB DDR_A_BS_1 DDR_A_BS_0 DDR3_A_WEB DDR_A_RASB DDR_A_WEB DDR_A_BS_2 DDR_A_MA_11 DDR_A_MA_14 DDR_A_MA_12 Pin Count 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Ball # AD40 AG42 AH43 AE40 AJ41 AF42 AF41 AJ42 AJ40 AF39 AL41 AL39 AN40 AM39 AL42 AN41 AK42 AN42 AK41 AR41 AV40 AV42 AP41 AN39 AU40 AV41 AP42 AR42 AT20 AR18 AU21 AV20 AP20 Signal Name DDR_A_DQ_56 DDR_A_DQS_6 DDR_A_DQ_49 DDR_A_DQ_51 DDR_A_DQ_53 DDR_A_DQ_55 DDR_A_DQ_54 DDR_A_DQ_52 DDR_A_DQ_48 DDR_A_DQ_50 DDR_A_DQS_5 DDR_A_DQ_47 DDR_A_DQ_44 DDR_A_DQ_41 DDR_A_DQ_46 DDR_A_DQ_40 DDR_A_DQ_42 DDR_A_DQ_45 DDR_A_DQ_43 DDR_A_DQS_4 DDR_A_DQ_36 DDR_A_DQ_32 DDR_A_DQ_39 DDR_A_DQ_35 DDR_A_DQ_33 DDR_A_DQ_37 DDR_A_DQ_34 DDR_A_DQ_38 DDR_A_DQS_3 DDR_A_DQ_25 DDR_A_DQ_26 DDR_A_DQ_31 DDR_A_DQ_30 Table 14-9. XOR Chain 6 Pin Count 1 2 3 4 5 6 7 8 Ball # AC42 AB41 AE42 AD43 AB42 AA40 AC39 AE41 Signal Name DDR_A_DQS_7 DDR_A_DQ_58 DDR_A_DQ_60 DDR_A_DQ_57 DDR_A_DQ_63 DDR_A_DQ_59 DDR_A_DQ_62 DDR_A_DQ_61 30 31 32 33 34 35 36 37 38 39 40 41 432 Datasheet Testability Table 14-9. XOR Chain 6 Pin Count 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball # AT18 AN17 AT21 AP17 AY7 BB9 BC7 BA9 AY6 BB4 AY9 BB5 BA5 AW2 AY3 BA4 BB3 AY2 AV4 AV3 AU1 AU2 AP2 AR2 AN3 AM1 AM2 AR4 AR5 AL3 AR3 Signal Name DDR_A_DQ_24 DDR_A_DQ_29 DDR_A_DQ_27 DDR_A_DQ_28 DDR_A_DQS_2 DDR_A_DQ_19 DDR_A_DQ_22 DDR_A_DQ_18 DDR_A_DQ_17 DDR_A_DQ_21 DDR_A_DQ_23 DDR_A_DQ_16 DDR_A_DQ_20 DDR_A_DQS_1 DDR_A_DQ_15 DDR_A_DQ_10 DDR_A_DQ_11 DDR_A_DQ_14 DDR_A_DQ_8 DDR_A_DQ_9 DDR_A_DQ_13 DDR_A_DQ_12 DDR_A_DQS_0 DDR_A_DQ_2 DDR_A_DQ_1 DDR_A_DQ_0 DDR_A_DQ_5 DDR_A_DQ_7 DDR_A_DQ_6 DDR_A_DQ_4 DDR_A_DQ_3 Table 14-10. XOR Chain 7 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 Ball # BA5 BC25 BA9 BC21 AR29 AR31 AU42 AW6 AN11 AN12 BC3 AM2 AR41 Signal Name DDR_A_CSB_2 DDR_A_ODT_3 DDR_A_CSB_3 DDR_A_ODT_2 DDR_A_CK_3 DDR_A_CKB_3 DDR_A_CK_5 DDR_A_CKB_5 DDR_A_CK_4 DDR_A_CKB_4 DDR_A_CKE_3 DDR_A_CKE_2 DDR3_DRAMRST Table 14-11. XOR Chain 8 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ball # AV31 AW31 AT32 AU27 AT27 AV32 BA29 AW29 BB27 BA25 BA14 BB15 BB13 BB14 BA17 Signal Name DDR_B_CKB_0 DDR_B_CK_0 DDR_B_CKB_2 DDR_B_CK_1 DDR_B_CKB_1 DDR_B_CK_2 DDR_B_CSB_1 DDR_B_ODT_1 DDR_B_ODT_0 DDR_B_CSB_0 DDR_B_MA_4 DDR_B_MA_1 DDR_B_MA_8 DDR_B_MA_5 DDR_B_MA_10 Datasheet 433 Testability Table 14-11. XOR Chain 8 Pin Count 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Ball # BC12 BA13 BA15 AW11 AY13 AW15 AW12 AY15 AU26 AP23 AR15 AW13 AP12 AW9 AU5 AR7 Signal Name DDR_B_CKE_1 DDR_B_MA_7 DDR_B_MA_2 DDR_B_CKE_0 DDR_B_MA_9 DDR_B_MA_0 DDR_B_MA_6 DDR_B_MA_3 DDR_B_DQSB_3 DDR_B_DM_3 DDR_B_DQSB_2 DDR_B_DM_2 DDR_B_DQSB_1 DDR_B_DM_1 DDR_B_DQSB_0 DDR_B_DM_0 Table 14-12. XOR Chain 9 Pin Count 13 14 15 16 17 18 Ball # AY17 BB17 BB11 AY11 BA11 AY12 Signal Name DDR_B_BS_1 DDR_B_BS_0 DDR_B_MA_14 DDR_B_BS_2 DDR_B_MA_12 DDR_B_MA_11 Table 14-13. XOR Chain 10 Pin Count 1 2 3 4 5 6 7 Ball # AC36 AF38 AC34 AA34 AA33 AA36 AD36 AC33 AD34 AG35 AF34 AJ38 AF33 AJ35 AG33 AG38 AJ37 AF35 AL35 AL38 AJ34 AM34 Signal Name DDR_B_DQS_7 DDR_B_DQ_61 DDR_B_DQ_62 DDR_B_DQ_58 DDR_B_DQ_63 DDR_B_DQ_59 DDR_B_DQ_56 DDR_B_DQ_57 DDR_B_DQ_60 DDR_B_DQS_6 DDR_B_DQ_55 DDR_B_DQ_49 DDR_B_DQ_51 DDR_B_DQ_53 DDR_B_DQ_54 DDR_B_DQ_48 DDR_B_DQ_52 DDR_B_DQ_50 DDR_B_DQS_5 DDR_B_DQ_43 DDR_B_DQ_42 DDR_B_DQ_45 Table 14-12. XOR Chain 9 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 Ball # AC37 AD38 AG36 AG39 AL34 AM37 AU39 AU37 AY27 AY24 AW26 BB25 Signal Name DDR_B_DQSB_7 DDR_B_DM_7 DDR_B_DQSB_6 DDR_B_DM_6 DDR_B_DQSB_5 DDR_B_DM_5 DDR_B_DQSB_4 DDR_B_DM_4 DDR_B_MA_13 DDR_B_RASB DDR_B_CASB DDR_B_WEB 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 434 Datasheet Testability Table 14-13. XOR Chain 10 Pin Count 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Ball # AL32 AM38 AM35 AL37 AR39 AW39 AV38 AN35 AN36 AR37 AW37 AU35 AN37 AR35 AT24 AP26 AU23 AT23 AV24 AR24 AW23 AT26 AN26 AP15 AM13 AU15 AT17 AU17 AW17 AV13 AV15 AU13 AR12 Signal Name DDR_B_DQ_47 DDR_B_DQ_41 DDR_B_DQ_40 DDR_B_DQ_46 DDR_B_DQ_44 DDR_B_DQS_4 DDR_B_DQ_33 DDR_B_DQ_38 DDR_B_DQ_34 DDR_B_DQ_39 DDR_B_DQ_32 DDR_B_DQ_36 DDR_B_DQ_35 DDR_B_DQ_37 DDR_B_DQS_3 DDR_B_DQ_27 DDR_B_DQ_28 DDR_B_DQ_25 DDR_B_DQ_24 DDR_B_DQ_30 DDR_B_DQ_29 DDR_B_DQ_26 DDR_B_DQ_31 DDR_B_DQS_2 DDR_B_DQ_21 DDR_B_DQ_16 DDR_B_DQ_19 DDR_B_DQ_18 DDR_B_DQ_23 DDR_B_DQ_17 DDR_B_DQ_22 DDR_B_DQ_20 DDR_B_DQS_1 Table 14-13. XOR Chain 10 Pin Count 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball # AR11 AV12 AU11 AU12 AR13 AU9 AP13 AT11 AV6 AU7 AW7 AN6 AW5 AN9 AN5 AN7 AN8 Signal Name DDR_B_DQ_12 DDR_B_DQ_14 DDR_B_DQ_9 DDR_B_DQ_15 DDR_B_DQ_11 DDR_B_DQ_13 DDR_B_DQ_10 DDR_B_DQ_8 DDR_B_DQS_0 DDR_B_DQ_7 DDR_B_DQ_3 DDR_B_DQ_5 DDR_B_DQ_2 DDR_B_DQ_6 DDR_B_DQ_4 DDR_B_DQ_0 DDR_B_DQ_1 Table 14-14. XOR Chain 11 Pin Count 1 2 3 4 5 6 7 8 9 10 11 Ball # BA30 AP32 AN33 AW27 AV29 AR29 AU29 AY29 BA27 BA26 AW32 Signal Name DDR_B_CSB_3 DDR_B_CKB_5 DDR_B_CK_5 DDR_B_CKB_4 DDR_B_CK_4 DDR_B_CK_3 DDR_B_CKB_3 DDR_B_ODT_3 DDR_B_ODT_2 DDR_B_CSB_2 DDR3_B_ODT3 Datasheet 435 Testability Table 14-14. XOR Chain 11 Pin Count 12 13 Ball # BB10 BA10 Signal Name DDR_B_CKE_3 DDR_B_CKE_2 Table 14-17. XOR Chain 14 Pin Count 1 2 3 Ball # U4 V3 R7 R6 T2 U2 R4 T4 P1 R2 R10 R9 N4 P3 M6 M5 M2 N2 L4 M4 K1 L2 M9 M8 K3 J4 L8 L9 G4 F4 G5 G6 E2 Signal Name PEG_TXN_15 PEG_TXP_15 PEG_RXN_15 PEG_RXP_15 PEG_TXN_14 PEG_TXP_14 PEG_RXN_14 PEG_RXP_14 PEG_TXN_13 PEG_TXP_13 PEG_RXN_13 PEG_RXP_13 PEG_TXN_12 PEG_TXP_12 PEG_RXN_12 PEG_RXP_12 PEG_TXN_11 PEG_TXP_11 PEG_RXN_11 PEG_RXP_11 PEG_TXN_10 PEG_TXP_10 PEG_RXN_10 PEG_RXP_10 PEG_TXN_9 PEG_TXP_9 PEG_RXN_9 PEG_RXP_9 PEG_TXN_8 PEG_TXP_8 PEG_RXN_8 PEG_RXP_8 PEG_TXN_7 Table 14-15. XOR Chain 12 Pin Count 1 2 3 4 Ball # G17 E17 L13 M13 Signal Name SDVO_CTRLDATA SDVO_CTRLCLK CRT_DDC_DATA CRT_DDC_CLK 4 5 6 7 8 9 10 11 Table 14-16. XOR Chain 13 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Ball # AA2 Y2 AA4 AB3 AC9 AC8 AA6 AA7 Y4 W4 Y9 Y8 V6 V7 V1 W2 Signal Name DMI_TXN_3 DMI_TXP_3 DMI_RXN_3 DMI_RXP_3 DMI_TXN_2 DMI_TXP_2 DMI_RXN_2 DMI_RXP_2 DMI_TXN_1 DMI_TXP_1 DMI_RXN_1 DMI_RXP_1 DMI_TXN_0 DMI_TXP_0 DMI_RXN_0 DMI_RXP_0 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 436 Datasheet Testability Table 14-17. XOR Chain 14 Pin Count 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Ball # F2 D2 C2 B4 B3 F6 E5 B6 B5 E7 F7 D6 D7 H11 J11 B7 Signal Name PEG_TXP_7 PEG_RXN_7 PEG_RXP_7 PEG_TXN_6 PEG_TXP_6 PEG_RXN_6 PEG_RXP_6 PEG_TXN_5 PEG_TXP_5 PEG_RXN_5 PEG_RXP_5 PEG_TXN_4 PEG_TXP_4 PEG_RXN_4 PEG_RXP_4 PEG_TXN_3 Table 14-17. XOR Chain 14 Pin Count 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Ball # B9 H12 J12 D9 C10 E12 F12 A10 B11 J15 K15 D12 D11 E13 F13 Signal Name PEG_TXP_3 PEG_RXN_3 PEG_RXP_3 PEG_TXN_2 PEG_TXP_2 PEG_RXN_2 PEG_RXP_2 PEG_TXN_1 PEG_TXP_1 PEG_RXN_1 PEG_RXP_1 PEG_TXN_0 PEG_TXP_0 PEG_RXN_0 PEG_RXP_0 § Datasheet 437