87C196JQ

87C196KR KQ 87C196JV JT 87C196JR JQ ADVANCED 16-BIT CHMOS MICROCONTROLLER Automotive Y Y Y Y b 40 C to a 125 C Ambient Y High Performance CHMOS 16-Bit CPU Up to 48 Kbytes of On-Chip EPROM Up to 1 5 Kbytes of On-Chip Register RAM Up to 512 Bytes of Additional RAM (Code RAM) Register-Register Architecture Up to 8 Channel 10-Bit A D with Sample Hold Up to 37 Prioritized Interrupt Sources Up to Seven 8-Bit (56) I O Ports Full Duplex Serial I O Port Dedicated Baud Rate Generator Interprocessor Communication Slave Port Device Pins Package 68-pin PLCC 68-pin PLCC 52-pin PLCC 52-pin PLCC 52-pin PLCC 52-pin PLCC EPROM 16K 12K 48K 32K 16K 12K Reg RAM 488 360 1 5K 1 0K 488 360 Y Y Y High Speed Peripheral Transaction Server (PTS) Two 16-Bit Software Timers 10 High Speed Capture Compare (EPA) Full Duplex Synchronous Serial I O Port (SSIO) Two Flexible 16-Bit Timer Counters Quadrature Counting Inputs Flexible 8- 16-Bit External Bus Programmable Bus (HLD HLDA) 1 75 ms 16 x 16 Multiply 3 ms 32 16 Divide 68-Pin and 52-Pin PLCC Packages Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Code RAM 256 128 512 512 256 128 IO 56 56 41 41 41 41 EPA 10 10 6 6 6 6 SIO Y Y Y Y Y Y SSIO Y Y Y Y Y Y AD 8 8 6 6 6 6 87C196KR 87C196KQ 87C196JV 87C196JT 87C196JR 87C196JQ The 87C196KR KQ JV JT JR JQ devices represent the fourth generation of MCS 96 Microcontroller products implemented on Intel’s advanced 1 micron process technology These products are based on the 80C196KB device with improvements for automotive applications The instruction set is a true super set of 80C196KB The 87C196JR is a 52-pin version of the 87C196KR device while the 87C196KQ JQ are memory scalars of the 87C196KR JR The 87C196JV JT A-step devices (JV-A JT-A) are the newest members of the MCS 96 microcontroller family These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and electrical compatibility The JT-A has 32 Kbytes of on-chip EPROM 1 0 Kbytes of Register RAM and 512 bytes of Code RAM The JV-A has 48 Kbytes of on-chip EPROM 1 5 Kbytes of Register RAM and 512 bytes of Code RAM Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 November 1995 Order Number 270827-006 87C196KR KQ 87C196JV JT 87C196JR JQ The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU The 87C196Kx Jx family members listed above are composed of the high-speed (16 MHz) core as well as the following peripherals up to 48 Kbytes of Programmable EPROM up to 1 5 Kbytes of Register RAM 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space an eight channel-10-Bit g 3 LSB analog to digital converter with programmable S H times with conversion times k 5 ms at 16 MHz an asynchronous synchronous serial I O port (8096 compatible) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port (8096 compatible) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port with full duplex master slave transceivers a flexible timer counter structure with prescaler cascading and quadrature capabilities 10 modularized multiplexed high speed I O for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) The PTS has several channel modes including single burst block transfers from any memory location to any memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an A D scan mode Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area Please refer to the following datasheets for higher frequency versions of devices contained within this datasheet 20 MHz 87C196JT Order 272529 20 MHz 87C196JV Order Number 272580     Up to 37 Interrupt Vectors Up to 512 Bytes of Code RAM Up to 1 5 Kbytes of Register RAM ‘‘Windowing’’ Allows 8-Bit Addressing to Some 16-Bit Addresses  1 75 ms 16 x 16 Multiply  3 ms 32 16 Divide  Oscillator Fail Detect PERIPHERAL FEATURES  Programmable A D Conversion and S H Times  10 Capture Compare I O with 2 Flexible Timers  Synchronous Serial I O Port for Full Duplex Serial I O  Total Utilization of ALL Available Pins (I O Mux’d with Control)  2 16-Bit Timers with Prescale Cascading and Quadrature Counting Capabilities  Up to 12 Externally Triggered Interrupts NEW INSTRUCTIONS XCH XCHB Exchange the contents of two locations either Word or Byte is supported BMOVi Interruptable Block Move Instruction allows the user to be interrupted during long executing Block Moves ARCHITECTURE The 87C196KR KQ JV JT JR JQ are members of the MCS 96 microcontroller family has the same architecture and uses the same instruction set as the 80C196KB KC Many new features have been added including TIJMP Table Indirect JUMP This instruction incorporates a way to do complex CASE level branches through one instruction An example of such code savings several interrupt sources and only one interrupt vector The TIJMP instruction will sort through the sources and branch to the appropriate sub-code level in one instruction This instruction was added especially for the EPA structure but has other code saving advantages CPU FEATURES  Powerdown and Idle Modes  16 MHz Operating Frequency  A High Performance Peripheral Transaction Server (PTS) EPTS DPTS Enable and Disable PTS Interrupts (Works like EI and DI) 2 87C196KR KQ 87C196JV JT 87C196JR JQ SFR OPERATION An additional 256 bytes of SFR registers were added to the 8XC196KR devices These locations were added to support the wide range of on-chip peripherals that the 8XC196KR has This memory space (1F00 – 1FFFH) has the ability to be addressed as direct 8-bit addresses through the ‘‘windowing’’ technique Any 32- 64- or 128-byte section can be relocated in the upper 32 64 or 128 bytes of the internal register RAM (080 – FFH) address space 270827 – 1 Figure 1 Block Diagram 270827 – 15 Figure 2 The 8XC196KR Family Nomenclature 3 87C196KR KQ 87C196JV JT 87C196JR JQ 270827 – 2 270827 – 3 Figure 3 Package Diagrams 4 87C196KR KQ 87C196JV JT 87C196JR JQ PIN DESCRIPTIONS Symbol VCC VSS VSS VSS VREF Main supply voltage ( a 5V) Digital circuit ground (0V) There are three VSS pins all of which MUST be connected to a single ground plane Reference for the A D converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Programming voltage for the EPROM parts It should be a 12 5V for programming It is also the timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this function is not used VPP may be tied to VCC Reference ground for the A D converter Must be held at nominally the same potential as VSS Input of the oscillator inverter and the internal clock generator Output of the oscillator inverter Output of the internal clock generator The frequency is frequency It has a 50% duty cycle Also LSIO pin the oscillator Name and Function VPP ANGND XTAL1 XTAL2 P2 7 CLKOUT RESET Reset input to the chip Input low for at least 16 state times will reset the chip The subsequent low to high transition resynchronizes CLKOUT and commences a 10state time sequence in which the PSW is cleared bytes are read from 2018H and 201AH loading the CCBs and a jump to location 2080H is executed Input high for normal operation RESET has an internal pullup Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin dynamically controls the Bus width of the bus cycle in progress If BUSWIDTH is low an 8-bit cycle occurs If BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’ all bus cycles are 16-bit CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal Also an LSIO pin when not used as BUSWIDTH A positive transition causes a non-maskable interrupt vector through memory location 203EH Used by Intel (GND this pin) Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal EP ROM fetches INST is held low Also LSIO when not INST Input for memory select (External Access) EA equal to a high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM ROM EA equal to a low causes accesses to these locations to be directed to offchip memory EA e a 12 5V causes execution to begin in the Programming Mode EA latched at reset Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip select for external memory ALE ADV is active only during external memory accesses Also LSIO when not used as ALE P5 7 BUSWIDTH NMI P5 1 INST EA P5 0 ALE ADV 5 87C196KR KQ 87C196JV JT 87C196JR JQ PIN DESCRIPTIONS (Continued) Symbol P5 3 RD P5 2 WR WRL Name and Function Read signal output to external memory RD is active only during external memory reads or LSIO when not used as RD Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is active during external memory writes Also an LSIO pin when not used as WR WRL Byte High Enable or Write High output as selected by the CCR BHE e 0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0 selects that bank of memory that is connectd to the low byte Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH is only valid during 16-bit external memory write cycles Also an LSIO pin when not BHE WRH Ready input to lengthen external memory cycles for interfacing with slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high When external memory is not used READY has no effect The max number of wait states inserted into the bus cycle is controlled by the CCR CCR1 Also an LSIO pin when READY is not selected Dual functional I O pin As a bidirectional port pin or as a system function The system function is a Slave Port Interrupt Output Pin Dual function I O pin Primary function is that of a bidirectional I O pin however it may also be used as a TIMER1 Clock input The TIMER1 will increment or decrement on both positive and negative edges of this pin Dual function I Opin Primary function is that of a bidirectional I O pin however it may also be used as a TIMER1 Direction input The TIMER1 will increment when this pin is high and decrements when this pin is low Dual function I O port pins Primary function is that of bidirectional I O System function is that of High Speed capture and compare EPA0 and EPA2 have yet another function of T2CLK and T2DIR of the TIMER2 timer counter 8-bit high impedance input-only port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter These pins are also used as inputs to EPROM parts to select the Programming Mode Dual function I O ports that have a system function as Synchronous Serial I O Two pins are clocks and two pins are data providing full duplex capability 8-bit multi-functional port All of its pins are shared with other functions 8-bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups P5 5 BHE WRH P5 6 READY P5 4 SLPINT P6 2 T1CLK P6 3 T1DIR PORT1 EPA0–7 P6 0–6 1 EPA8–9 PORT 0 ACH0–7 P6 4–6 7 SSIO PORT 2 PORT 3 and 4 6 87C196KR KQ 87C196JV JT 87C196JR JQ ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Storage Temperature Voltage from VPP or EA to VSS or ANGND b 60 C to a 150 C b 0 5V to a 13 0V NOTICE This is a production data sheet The specifications are subject to change without notice WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability Voltage from Any Other Pin b 0 5V to a 7 0V to VSS or ANGND This includes VPP on ROM and CPU devices Power Dissipation 0 5W OPERATING CONDITIONS Symbol TA VCC VREF FOSC Parameter Ambient Temperature under Bias Digital Supply Voltage Analog Supply Voltage Oscillator Frequency Min b 40 Max a 125 Units C V V MHz(4) 4 50 4 50 4 5 50 5 50 16 NOTE ANGND and VSS should be nominally at the same potential DC CHARACTERISTICS Symbol ICC Parameter VCC Supply Current ( b 40 C to a 125 C Ambient) Active Mode Supply Current (Typical) A D Reference Supply Current Idle Mode Current Powerdown Mode Current Input Low Voltage (All Pins) Input High Voltage (All Pins) Output Low Voltage (Outputs Configured as Push Pull) (Under Listed Operating Conditions) Min Typ Max 75 (JV e 80) 50 50 (JV e 55) 2 15 5 30 (JV e 32) TBD 0 3 VCC VCC a 0 5 03 0 45 15 mA mA XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V VCC e VPP e VREF e 5 5V (Note 6) mA Units mA Test Conditions XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V (While Device in Reset) ICC1 IREF IIDLE IPD VIL VIH VOL 50 b 0 5V mA V V V V V 0 7 VCC (Note 7) IOL e 200 mA (Notes 3 5) IOL e 3 2 mA IOL e 7 0 mA 7 87C196KR KQ 87C196JV JT 87C196JR JQ DC CHARACTERISTICS Symbol VOH Parameter (Under Listed Operating Conditions) (Continued) Min VCC b 0 3 VCC b 0 7 VCC b 1 5 g8 JT JV g 10 g1 JT JV g 2 Typ Max Units V V V mA mA mA V Test Conditions IOH e b 200 mA (Notes 3 5) IOH e b 3 2 mA IOH e b 7 0 mA VSS s VIN s VCC (Note 2) VSS s VIN s VREF VSS s VIN s VCC IOH e b 15 mA (Notes 1 8) VOH2 e VCC b 1 0V VOH2 e VCC b 2 5V VOH2 e VCC b 4 0V VOH2 e VCC b 1 0V VOH2 e VCC b 2 5V VOH2 e VCC b 4 0V IOL3 e 4 mA (Note 9) IOL3 e 6 mA IOL3 e 10 mA FTEST e 1 0 MHz (Note 6) Output High Voltage (Outputs Configured as Push Pull) Input Leakage Current (Std Inputs) Input Leakage Current (Port 0 A D Inputs) Input High Current (NMI Pin) Output High Voltage in RESET Output High Current in RESET ILI ILI1 IIH VOH2 IOH2 (KR KQ) a 175 VCC b 1V b6 b 15 b 20 b 30 b 75 b 90 b 35 b 60 b 70 b 120 b 240 b 280 mA mA mA mA mA mA X V V V pF X IOH2 Output High (JV JT Current in JR-D JQ-D) RESET RRST VOL3 Reset Pullup Resistor Output Low Voltage in RESET (RESET Pin only) Pin Capacitance (Any Pin to VSS) Weak Pullup Resistance (Approx) 6K 65K 03 05 08 10 150K CS RWPU NOTES 1 All BD (bidirectional) pins except P5 1 INST and P2 7 CLKOUT which are excluded due to their not being weakly pulled high in reset BD pins include Port1 Port2 Port3 Port4 Port5 and Port6 2 Standard Input pins include XTAL1 EA RESET and Ports 1 2 3 4 5 6 when configured as inputs 3 All Bidirectional I O pins when configured as Outputs (Push Pull) 4 Device is Static and should operate below 1 Hz but only tested down to 4 MHz 5 Maximum IOL IOH currents per pin will be characterized and published at a later date Target values are g 10 mA 6 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and VREF e VCC e 5 0V 7 VIH max for Port0 is VREF a 0 5V 8 Refer to ‘‘VOH2 IOH2 Specification’’ errata 1 in errata section of this datasheet 9 This specification is not tested in production and is based upon theoretical estimates and or product characterization 8 87C196KR KQ 87C196JV JT 87C196JR JQ KR KQ JR JQ ICC vs Frequency 270827 – 4 NOTES ICC Max e 3 88 c Freq a 13 43 IIDLE Max e 1 65 c Freq a 2 2 JT ICC vs Frequency 270827 – 19 NOTES ICC Max e 3 25 c Freq a 23 IIDLE Max e 1 25 c Freq a 15 9 87C196KR KQ 87C196JV JT 87C196JR JQ AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns FOSC e 16 MHz The system must meet these specifications to work with the 87C196KR KQ JV JT JR JQ Symbol TAVYV TLLYV TYLYH TCLYX TLLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRXDX Parameter Address Valid to READY Setup ALE Low to READY Setup Non READY Time READY Hold after CLKOUT Low READY Hold after ALE Low Address Valid to Buswidth Setup ALE Low to Buswidth Setup Buswidth Hold after CLKOUT Low Address Valid to Input Data Valid RD Active to Input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD Inactive 0 0 3 TOSC b 55 TOSC b 22 TOSC b 50 TOSC 0 TOSC b 15 Min Max 2 TOSC b 75 TOSC b 70 No Upper Limit TOSC b 30 2 TOSC b 40 2 TOSC b 75 TOSC b 60 Units ns ns ns ns(1) ns(1) ns ns ns ns ns ns ns ns NOTE 1 If max is exceeded additional wait states will occur The 87C196KR KQ JV JT JR JQ will meet these specifications Symbol FXTAL TOSC TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL Parameter Oscillator Frequency Oscillator Period (1 Fxtal) XTAL1 High to CLKOUT High or Low CLKOUT Period CLKOUT High Period CLKOUT Falling Edge to ALE Rising ALE ADV Falling Edge to CLKOUT Rising ALE ADV Cycle Time ALE ADV High Period Address Setup to ALE ADV Falling Edge Address Hold after ALE ADV Falling Edge ALE ADV Falling Edge to RD Falling Edge TOSC b 10 TOSC b 15 TOSC b 40 TOSC b 30 TOSC b 10 b 10 b 20 Min 40 62 5 20 2 TOSC Max 16 0 250 110 Units MHz(1) ns ns(2) ns TOSC a 15 15 15 4 TOSC TOSC a 10 ns ns ns ns ns ns ns ns 10 87C196KR KQ 87C196JV JT 87C196JR JQ AC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns FOSC e 16 MHz The 87C196KR KQ JV JT JR JQ will meet these specifications Symbol TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Parameter RD Low to CLKOUT Falling Edge RD Low Period RD Rising Edge to ALE ADV Rising Edge RD Low to Address Float ALE ADV Falling Edge to WR Falling Edge CLKOUT Low to WR Falling Edge Data Stable to WR Rising Edge CLKOUT High to WR Rising Edge WR Low Period Data Hold after WR Rising Edge WR Rising Edge to ALE ADV Rising Edge BHE INST Hold after WR Rising Edge AD8–15 Hold after WR Rising Edge BHE INST Hold after RD Rising Edge AD8–15 Hold after RD Rising Edge TOSC b 10 b5 Min 4 TOSC b 5 TOSC Max 30 Units ns ns TOSC a 25 5 ns(3) ns(5) ns 25 ns ns TOSC b 23 b 10 15 ns ns ns ns(3) ns ns ns ns TOSC b 20 TOSC b 25 TOSC b 10 TOSC b 10 TOSC b 30(4) TOSC b 10 TOSC b 30(4) TOSC a 15 NOTES 1 Testing performed at 4 0 MHz however the device is static by design and will typically operate below 1 Hz 2 Typical specifications not guaranteed 3 Assuming back-to-back bus cycles 4 8-bit bus only 5 TRLAZ (max) e 5 ns by design 11 87C196KR KQ 87C196JV JT 87C196JR JQ System Bus Timing 270827 – 5 READY BUSWIDTH TIMING 270827 – 6 12 87C196KR KQ 87C196JV JT 87C196JR JQ EXTERNAL CLOCK DRIVE Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period (TOSC) High Time Low Time Rise Time Fall Time Min 40 62 5 0 35 TOSC 0 35 TOSC Max 16 250 0 65 TOSC 0 65 TOSC 10 10 Units MHz ns ns ns ns ns EXTERNAL CLOCK DRIVE WAVEFORMS 270827 – 7 AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 270827 – 8 270827 – 9 NOTE AC Testing Inputs are driven at 3 5V for a logic ‘‘1’’ and 0 45V for a logic ‘‘0’’ Timing measurements are made at 2 0V for a logic ‘‘1’’ and 0 8V for logic ‘‘0’’ NOTE For timing purposes a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH VOL level occurs IOL IOH s 15 mA THERMAL CHARACTERISTICS Device and Package AN87C196KR KQ (68-Lead PLCC) AN87C196JV JT JR JQ (52-Lead PLCC) iJA 41 C W 42 C W iJC 14 C W 15 C W NOTES 1 iJA e Thermal resistance between junction and the surrounding environment (ambient) Measurements are taken 1 ft away from case in air flow environment iJC e Thermal resistance between junction and package surface (case) 2 All values of iJA and iJC may fluctuate depending on the environment (with or without airflow and how much airflow) and device power dissipation at temperature of operation Typical variations are g 2 C W 3 Values listed are at a maximum power dissipation of 0 50W 13 87C196KR KQ 87C196JV JT 87C196JR JQ EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘t’’ for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points Conditions H L V X Z High Low Valid No Longer Valid Floating Signals A B C D G H Address BHE CLKOUT DATA Buswidth HOLD HA L R W X Y HLDA ALE ADV RD WR WRH WRI XTAL1 READY EPROM SPECIFICATIONS AC EPROM PROGRAMMING CHARACTERISTICS Operating Conditions Load Capacitance e 150 pF TC e 25 C g 5 C VREF e 5 0V g 0 5V VSS ANGND e 0V VPP e 12 5V g 0 25V EA e 12 5V g 0 25V FOSC e 5 0 MHz Symbol TAVLL TLLAX TDVPL TPLDX TLLLH TPLPH TLHPL TPHLL TPHDX TPHPL TPLDV TSHLL TPHIL TILIH TILVH TILPL TPHVL Parameter Address Setup Time Address Hold Time Data Setup Time Data Hold Time PALE Pulse Width PROG Pulse Width(3) PALE High to PROG Low PROG High to Next PALE Low Word Dump Hold Time PROG High to Next PROG Low PROG Low to Word Dump Valid RESET High to First PALE Low PROG High to AINC Low AINC Pulse Width PVER Hold after AINC Low AINC Low to PROG Low PROG High to PVER Valid 1100 0 240 50 170 220 220 50 Min 0 100 0 400 50 50 220 220 50 Max Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC NOTES 1 Run time programming is done with FOSC e 6 0 MHz to 10 0 MHz VCC VPD VREF e 5V g 0 5V TC e 25 C g 5 C and VPP e 12 5V g 0 25V For run-time programming over a full operating range contact factory 2 Programming Specifications are not tested but guaranteed by design 3 This specification is for the word dump mode For programming pulses use 300 TOSC a 100 ms DC EPROM PROGRAMMING CHARACTERISTICS Symbol IPP Parameter VPP Programming Supply Current Min Max 100 Units mA NOTE VPP must be within 1V of VCC while VCC k 4 5V VPP must not have a low impedance path to ground or VSS while VCC l 4 5V 14 87C196KR KQ 87C196JV JT 87C196JR JQ EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 270827 – 10 SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT 270827 – 11 SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT 270827 – 12 15 87C196KR KQ 87C196JV JT 87C196JR JQ A TO D CONVERTER SPECIFICATIONS The speed of the A D converter in the 10-bit or 8-bit modes can be adjusted by setting the AD TIME special function register to the appropriate value The AD TIME register only programs the speed at which the conversions are performed not the speed at which it can convert correctly The converter is ratiometric so absolute accuracy is dependent on the accuracy and stability of VREF A D OPERATING CONDITIONS(1) Symbol TA VCC VREF TSAM TCONV FOSC Description Automotive Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min b 40 VREF must not exceed VCC by more than 0 5V since it supplies both the resistor ladder and the digital portion of the converter and input port pins For testing purposes after a conversion is started the device is placed in the IDLE mode until the conversion is complete Testing is performed at VREF e 5 12V and 16 MHz operating frequency There is an AD TEST register that allows for conversion on ANGND and VREF as well as zero offset adjustment The absolute error listed is without doing any adjustments Max a 125 Units C V V ms(4) ms(4) MHz 4 50 4 50 20 16 5 4 5 50 5 50(2 3) 19 5 16 NOTES 1 ANGND and VSS should nominally be at the same potential 2 VREF must not exceed VCC by more than a 0 5V 3 Testing is performed at VREF e 5 12V 4 The value of AD TIME must be selected to meet these specifications Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Fullscale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Typical (1) Min 1024 10 0 Max 1024 10 b3 a3 Units Level Bits LSBs LSBs LSBs g2 g2 g3 l b0 5 g 0 25 LSBs LSBs LSBs LSBs(1) LSB C(1) LSB C(1) LSB C(1) dB(1 2 3) dB(1 2) dB(1 2) X(1) mA a0 5 g1 0 0 0 009 0 009 0 009 b 60 b 60 b 60 750 0 1 2K g1 JT JV e g 2 NOTES These values are expected for most parts at 25 C but are not tested or guaranteed An ‘‘LSB’’ as used here has a value of approximately 5 mV (See Automotive Handbook for A D glossary of terms) 1 These values are not tested in production and are based on theoretical estimates and or laboratory test 2 DC to 100 KHz 3 Multiplexer Break-Before-Make Guaranteed 16 87C196KR KQ 87C196JV JT 87C196JR JQ HOLD HLDA Timings Symbol THVCH TCLHAL TCLBRL TAZHAL TBZHAL TCLHAH TCLBRH THAHAX THAHBV TCLLH HOLD Setup CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float HLDA Low to BHE INST RD WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address Valid HLDA High to BHE INST RD WR Valid CLKOUT Low to ALE High b 15 b 15 b 15 b 10 b 10 Description Min 65 b 15 b 15 Max 15 15 25 25 15 15 Units ns ns ns ns ns ns ns ns ns Notes (Note 1) 15 ns NOTE 1 To guarantee recognition at next clock DC SPECIFICATIONS IN HOLD Parameter Weak Pullups on ADV RD WR WRL BHE Weak Pulldowns on ALE INST Min 50K 10K Max 250K 50K Units VCC e 5 5V VIN e 0 45V VCC e 5 5V VIN e 2 4 270827 – 16 17 87C196KR KQ 87C196JV JT 87C196JR JQ AC CHARACTERISTICS SLAVE PORT WAVEFORM SLAVE PORT (SLPL e 0) 270827 – 17 SLAVE PORT TIMING Symbol TSAVWL TSRHAV TSRLRH TSWLWH TSRLDV TSDVWH TSWHQX TSRHDZ (SLPL e 0)(1 2 3) Parameter Address Valid to WR Low RD High to Address Valid RD Low Period WR Low Period RD Low to Output Data Valid Input Data Setup to WR High WR High to Data Invalid RD High to Data Float 20 30 15 Min 50 60 TOSC TOSC 60 Max Units ns ns ns ns ns ns ns ns NOTES 1 Test Conditions FOSC e 16 MHz TOSC e 60 ns Rise Fall Time e 10 ns Capacitive Pin Load e 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change 18 87C196KR KQ 87C196JV JT 87C196JR JQ AC CHARACTERISTICS SLAVE PORT WAVEFORM SLAVE PORT (Continued) (SLPL e 1) 270827 – 18 SLAVE PORT TIMING Symbol TSELLL TSRHEH TSLLRL TSRLRH TSWLWH TSAVLL TSLLAX TSRLDV TSDVWH TSWHQX TSRHDZ (SLPL e 1)(1 2 3) Parameter CS Low to ALE Low RD or WR High to CS High ALE Low to RD Low RD Low Period WR Low Period Address Valid to ALE Low ALE Low to Address Invalid RD Low to Output Data Valid Input Data Setup to WR High WR High to Data Invalid RD High to Data Float 20 30 15 Min 20 60 TOSC TOSC TOSC 20 20 60 Max Units ns ns ns ns ns ns ns ns ns ns ns NOTES 1 Test Conditions FOSC e 16 MHz TOSC e 60 ns Rise Fall Time e 10 ns Capacitive Pin Load e 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change 19 87C196KR KQ 87C196JV JT 87C196JR JQ AC CHARACTERISTICS SERIAL PORT SHIFT REGISTER MODE SERIAL PORT TIMING SHIFT REGISTER MODE Test Conditions TA e b 40 C to a 125 C VCC e 5 0V g 10% VSS e 0 0V Load Capacitance e 100 pF Symbol TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX(1) TXHQZ(1) NOTES 1 Parameter not tested Parameter Serial Port Clock Period Serial Port Clock Falling Edge to Rising Edge Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float Min 8 TOSC 4 TOSC b 50 3 TOSC 2 TOSC b 50 Max Units ns 4 TOSC a 50 ns ns ns 2 TOSC a 50 2 TOSC a 200 0 5 TOSC ns ns ns ns WAVEFORM SERIAL PORT SHIFT REGISTER MODE 0 SERIAL PORT WAVEFORM SHIFT REGISTER MODE 270827 – 13 20 87C196KR KQ 87C196JV JT 87C196JR JQ (6) Slave Port Support The Slave port cannot be easily used on 52-lead devices due to P5 4 SLPINT and P5 1 SLPCS not being bonded-out (7) Port Functions Some port pins have been removed P5 7 P5 6 P5 5 P5 1 P6 2 P6 3 P1 4 through P1 7 P2 3 P2 5 P0 0 and P0 1 The PxREG PxSSEL and PxIO registers can still be updated and read The programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software Treat these bits as RESERVED Additionally these port pins should be setup internally by software as follows 1 Written to PxREG as ‘‘1’’ or ‘‘0’’ 2 Configured as Push Pull PxIO as ‘‘0’’ 3 Configured as LSIO This configuration will effectively strap the pin either high or low DO NOT Configure as Open Drain output ‘’1’’ or as an Input pin This device is CMOS 52-LEAD DEVICES Intel offers 52-lead versions of the 87C196KR device the 87C196JV JT JR JQ devices The first samples and production units use the 87C196KR die and bond it out in a 52-lead package It is important to point out some functionality differences because of future devices or to remain software consistent with the 68-lead device Because of the absence of pins on the 52-lead device some functions are not supported 52-Lead Unsupported Functions Analog Channels 0 and 1 INST Pin Functionality SLPINT Pin Support HLD HLDA Functionality External Clocking Direction of Timer1 WRH or BHE Functions Dynamic Buswidth Dynamic Wait State Control The following is a list of recommended practices when using the 52-lead device (1) External Memory Use an 8-bit bus mode only There is neither a WRH or BUSWIDTH pin The bus cannot dynamically switch from 8- to 16-bit or vice versa Set the CCB bytes to an 8-bit only mode using WR function only (2) Wait State Control Use the CCB bytes to configure the maximum number of wait states If the READY pin is selected to be a system function the device will lockup waiting for READY If the READY pin is configured as LSIO (default after RESET) the internal logic will receive a logic ‘‘0’’ level and insert the CCB defined number of wait states in the bus cycle DON’T USE IRC e ‘‘111’’ (3) NMI Support The NMI is not bonded out Make the NMI vector at location 203Eh vector to a Return instruction This is for glitch safety protection only (4) Auto-Programming Mode The 52-lead device will ONLY support the 16-bit zero wait state bus during auto-programming (5) EPA4 through EPA7 Since the JR and JQ devices use the KR silicon these functions are in the device just not bonded out A programmer can use these as compare only channels or for other functions like software timer start an A D conversion or reset timers 87C196KR KQ JV JT JR JQ ERRATA 1 VOH2 IOH2 Specification (Note C) In the DC Characteristics section of this datasheet VOH2 indicates the strength of the internal weak pullups that are active during and after reset until the user writes to the PxMODE register C-step devices do not meet this specification The new specification for C-step devices is VOH2 (min) e VCC b 1V at IOH2 e b 6 mA Note that JR JQ D-step devices are not affected by this errata and meet the published specification 2 1B00h – 1BDFh External Addressing (Notes C D) Affected devices cannot access external memory locations 1B00h – 1BDFh A bus cycle does not occur when these addresses are accessed If attempting to read from 1B00h – 1BDFh a value of FFh is returned even though a read cycle is not generated Writing to these locations will not generate an external bus cycle either This errata has been corrected on JV and JT devices 3 Port3 Push-Pull Operation (Note C) If Port3 is operating as a push-pull LSIO (LowSpeed I O) port and an address data bus cycle occurs Port3 will continue to drive the address data bus with its LSIO data during the bus cycle It is rather unlikely that this errata would affect an 21 87C196KR KQ 87C196JV JT 87C196JR JQ application because the application would have to use Port3 for both LSIO and as an external addr data bus If an application uses external memory Port3 should not be selected as pushpull LSIO NOTES ‘‘C’’ e Present on C-step devices ‘‘D’’ e Present on D-step devices ‘‘V’’ e Present on JV A-step devices ‘‘T’’ e Present on JT A-step devices Devices can be identified by a special mark following the eight-digit FPO number on the top of the package The following chart specifies what these markings are for various device steppings Device KR KQ C-step JR JQ D-step JV JT A-step Topside Marking ‘‘C’’ ‘‘D’’ ‘‘A’’ 5 Indirect Shift Instruction The upper 3 bits of the byte register holding the shift count are not masked completely If the shift count register has the value 32 c n where n e 1 3 5 or 7 the operand will be shifted 32 times This should have resulted in no shift taking place 6 P2 7 (CLKOUT) P2 7 (CLKOUT) does not operate in open drain mode 7 CLKOUT The CLKOUT signal is active on P2 7 during RESET for the KR KQ JV JT JR and JQ devices Note that CLKOUT is not active on P2 7 in RESET for the KT 8 EPA Overruns EPA ‘‘lock-up’’ can occur if overruns are not handled correctly refer to Intel Techbit DB0459 ‘‘Understanding EPA Capture Overruns’’ dated 12-9-93 Applies to EPA channels with interrupts and overruns enabled (ON RT bit in EPA CONTROL register set to ‘‘1’’) 9 Indirect Addressing with Auto-Increment For the special case of a pointer pointing to itself using auto-increment an incorrect access of the incremented pointer address will occur instead of an access to the original pointer address All other indirect auto-increment accesses will note be affected Please refer to Techbit MC0593 Incorrect sequence ld ax ax ldb bx ax 0 Results in ax being incremented by 1 and the contents of the address pointed to by ax a 1 to be loaded into bx 87C196KR KQ JV JT JR JQ DESIGN CONSIDERATIONS 1 EPA Timer RESET Write Conflict If the user writes to the EPA timer at the same time that the timer is reset it is indeterminate which will take precedence Users should not write to a timer if using EPA signals to reset it 2 Valid Time Matches The timer must increment decrement to the compare value for a match to occur A match does not occur if the timer is loaded with a value equal to an EPA compare value Matches also do not occur if a timer is reset and 0 is the EPA compare value 3 P6 PIN 4– 7 Not Updated Immediately Values written to P6 REG are temporarily held in a buffer If P6 MODE is cleared the buffer is loaded into P6 REG x If P6 MODE is set the value stays in the buffer and is loaded into P6 REG x when P6 MODE x is cleared Since reading P6 REG returns the current value in P6 REG and not the buffer changes to P6 REG cannot be read until unless P6 MODE x is cleared 4 Write Cycle during Reset If RESET occurs during a write cycle the contents of the external memory device may be corrupted Correct sequence where ax i bx Results in the contents of the address pointed to by ax to be loaded into bx and ax incremented by 1 10 JV Additional Register RAM The 8XC196JV has a total of 1 5 Kbytes of register RAM The RAM is located in two memory ranges 0000h – 03FFh and 1C00h – 1DFFh ld ax bx ldb cx ax 0 87C196JR JQ C-step to JR JQ D-step – or – JV JT A-step DESIGN CONSIDERATIONS This section documents differences between the 87C197JV A-step (JV-A) 87C196JT A-step (JT-A) 22 87C196KR KQ 87C196JV JT 87C196JR JQ 87C196JR D-step (JR-D) and the 87C196JR C-step (JR-C) For a list of design considerations between 68-lead and 52-lead devices please refer to the 52-lead Device Design Considerations section of this datasheet Since the 87C196JV JT JQ are simply memory scalars of the 87C196JR the term ‘‘JR’’ in this section will refer to JV JT JR and JQ versions of the device unless otherwise noted The JR-C is simply a 87C196KR C-step (KR-C) device packaged within a 52-lead package This reduction in pin count necessitated not bonding-out certain pins of the KR-C device The fact that these ‘‘removed pins’’ were still present on the device but not available to the outside world allowed the programmer to take advantage of some of the 68-lead KR features The JR-D is a fully-optimized 52-lead device based on the 87C196KR C-step device The KR-C design data base was used to assure that the JR-D would be fully compatible with the KR-C JR-C and other Kx family members The main differences between the JR-D and the JR-C is that several of the unused (not bonded-out) functions on the JR-C were removed altogether on the JR-D Following is a list of differences between the JR-C and the JR-D 1 Port3 Push-Pull Operation It was discovered on JR-C that if Port3 is selected for push-pull operation (P34 DRV register) during low speed I O (LSIO) the port was driving data when the system bus was attempting to input data It is rather unlikely that this errata would affect an application because the application would have to use Port3 for both LSIO and as an external addr data bus Nonetheless this errata was corrected on the JR-D 2 VOH2 Strengthened The DC Characteristics section of the Automotive KR datasheet contains a parameter VOH2 (Output High Voltage in RESET (BD ports)) which is specified at VCC –1V min at IOH2 e b 15 mA This specification indicates the strength of the internal weak pull-ups that are active during and after reset These weak pull-ups stay active until the user writes to PxMODE (previously known as PxSSEL) and configures the port pin as desired These pull-ups do not meet this VOH2 spec on the JR-C The weak pull-ups on specified JR-D ports have been enhanced to meet the published specification of IOH2 e b 15 mA 3 ONCE Mode ONCE mode is entered by holding a single pin On the KR low on the rising edge of RESET this pin is P5 4 SLPINT The JR-C does not support ONCE mode since P5 4 SLPINT (ONCE mode entry pin) is not bonded-out on these devices To provide ONCE mode on the JR-D the ONCE mode entry function was moved from P5 4 SLPINT to P2 6 HLDA This will allow the JR-D to enter ONCE mode using P2 6 instead of removed pin P5 4 4 Port0 On the JR-C P0 0 and P0 1 are not bonded out However these inputs are present in the device and reading them will provide an indeterminate result On the JR-D the analog inputs for these two channels at the miltiplexer are tied to VREF Therefore initiating an analog conversion on ACH0 or ACH1 will result in a value equal to full scale (3FFh) On the JR-D the digital inputs for these two channels are tied to ground therefore reading P0 0 or P0 1 will result in a digital ‘‘0’’ 5 Port1 On the JR-C P1 4 P1 5 P1 6 and P1 7 are not bonded out but are present internally on the device This allows the programmer to write to the port registers and clear set or read the pin even though it is not available to the outside world However to maintain compatibility with D-step and future devices it is recommended that the corresponding bits associated with the removed pins NOT be used to conditionally branch in software These bits should be treated as reserved On the JR-D unused port logic for these four port pins has been removed from the device and is not available to the programmer Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following results when read Register Bits P1 P1 P1 P1 PIN x REG x DIR x MODE x (x e 4 5 6 7) (x e 4 5 6 7) (x e 4 5 6 7) (x e 4 5 6 7) When Read 1 1 1 0 Writing to these bits will have no effect 23 87C196KR KQ 87C196JV JT 87C196JR JQ 6 Port2 On the JR-C P2 3 and P2 5 are not bonded out but are present internally on the device This allows the programmer to write to the port registers and clear set or read the pin even though it is not available to the outside world However to maintain compatibility with D-step and future devices it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software These bits should be treated as reserved On the JR-D unused port logic for these two port pins has been removed from the device and is not available to the programmer Corresponding bits in the port registers have been ‘‘hardwired’’ to provide the following results when read Register Bits P2 P2 P2 P2 PIN x REG x DIR x MODE x (x e 3 5) (x e 3 5) (x e 3 5) (x e 3 5) When Read 1 1 1 0 Register Bits P5 P5 P5 P5 P5 P5 P5 PIN x REG x DIR x MODE x MODE x MODE x MODE x (x e 1 4 5 6 7) (x e 1 4 5 6 7) (x e 1 4 5 6 7) (x e 1 4 6) (x e 5) (EA (x e 5) (EA (x e 7) e 0) e 1) When Read 1 1 1 0 1 0 1 Writing to these bits will have no effect 8 Port6 On the JR-C P6 2 and P6 3 are not bonded out but are present internally on the device This allows the programmer to write to the port registers and clear set or read the pin even though it is not available to the outside world However to maintain compatibility with D-step and future devices it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software These bits should be treated as reserved On the JR-D unused port logic for these two port pins has been removed from the device and is not available to the programmer Corresponding bits in the port registers have been ‘‘hardwired’’ to provide the following results when read Register Bits P6 P6 P6 P6 PIN x REG x DIR x MODE x (x e 2 3) (x e 2 3) (x e 2 3) (x e 2 3) When Read 1 1 1 0 Writing to these bits will have no effect 7 Port5 On the JR-C P5 1 P5 4 P5 5 P5 6 and P5 7 are not bonded out but are present internally on the device This allows the programmer to write to the port registers and clear set or read the pin even though it is not available to the outside world However to maintain compatibility with Dstep and future devices it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software These bits should be treated as reserved On the JR-D unused port logic for these five port pins has been removed from the device and is not available to the programmer Corresponding bits in the port registers have been ‘‘hardwired’’ to provide the following results when read Writing to these bits will have no effect 9 8XC196JQ Internal to External Memory Roll-over Point 8XC196JQ devices are simply 8XC196JR devices with less memory Both the JQ-C and JQ-D are fabricated from the JR-C and JR-D respectfully The difference between JQ and JR devices is that memory locations beyond the supported boundaries on the JQ are not tested in production and should not be used Any software which relies upon reading or writing these locations may not function correctly Following are the supported memory maps for these devices 24 87C196KR KQ 87C196JV JT 87C196JR JQ 2 A ‘‘by design’’ note was added to the TRLAZ specification 3 In the Design Considerations section the 7 CLKOUT design consideration was corrected 4 Only the two most current revision histories of this datasheet were retained in the datasheet revision history section The following differences exist between the -004 version and the -005 version 1 The 87C196JT and 87C196JV 16 MHz devices were added to the list of products covered by this datasheet The 87C196JT and 87C196JV are simply higher memory versions of the 87C196JR device For 20 MHz datasheets of these devices please refer to the following datasheets 20 MHz 87C196JT order 272529-001 20 MHz 87C196JV order 272580-001 2 The status of the datasheet has been moved from ‘‘Advanced Information’’ to that of no-marking Datasheets with no markings reflect specifications that have reached full production status Although the 87C196JV device is included within this datasheet its specifications are actually at the design phase of development Do not finalize a design with this information Revised information will be published when the 87C196JV device becomes available 3 The title of the datasheet as well as the features and design considerations list has been revised to include the 87C196JT and 87C196JV devices 4 Notes were added as appropriate to call out where 87C196JV specifications are expected to differ from those of other products listed within this datasheet Specifications which are expected to differ are ICC ICC1 IIDLE and ILI and DC Input Leakage on A D channels 5 The VOH2 (min) specification was supplemented with more comprehensive IOH2 (min max) specifications 6 A VOL3 (RESET pin only) specification was added to indicate the strength of the RESET pulldown device 7 All 87C196KR A-step errata was removed from the Errata section of this datasheet 8 For the JT the DC input leakage (max) as specified in the previous JT datasheet (272374-002) has been corrected to 2 mA to match the ILI specification of 2 mA These specifications both specify the same parameter 9 CerQuad package references have been removed JQ C and D-Step JR C and D-Step Register RAM Internal (Code) RAM 18h to 17Fh 400h to 47Fh 18h to 1FFh 400h to 4FFh 2000h to 5FFFh Internal ROM EPROM 2000h to 4FFFh It is important to note that the internal to external memory roll-over point for both the JR and JQ devices is the same (6000h and above goes external) Two guidelines the programmer should follow to insure no problems are encountered when using JQ devices are a) For JQ devices the program must contain a jump to a location greater than 5FFFh before the 12K boundary (4FFFh) is reached This is necessary only if greater than 12K of program memory is required with a JQ device and portions of the program execute from internal ROM EPROM b) For JQ devices with EA tied to ground use only internal program memory from 2000h to 4FFFh Do not use the unsupported locations from 5000h to 5FFFh 10 EPA Channels 4 through 7 The JR C-step device is simply a 68-lead KR-C device packaged in a 52-lead package The reduced pin-out is achieved by not bonding-out the unsupported pins EPA4–EPA7 are among these pins that are not bonded-out The fact that EPA4–EPA7 are still present allows the programmer to use these channels as software timers to start A D conversions reset timers etc All of the port pin logic is still present and it is possible to use the EPA to toggle these pins internally Please refer to the 52-Lead Device section in this datasheet for further information On the JR D-step the EPA4–EPA7 logic has NOT been removed from the device This allows the programmer to still use these channels (as on the C-step) for software timers etc The only difference is that the associated port pin logic has been removed and does not exist internally To maintain C-step to D-step compatibility programmers should make sure that their software does not rely upon the removed pins DATASHEET REVISION HISTORY This is the -006 version of the 87C196KR Datasheet The following differences exist between the -005 version and the -006 version 1 The 87C196JV datasheet status has been moved from ‘‘Product Preview’’ to that of ‘‘no marking ’’ 25