87C196KD

87C196KD 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER Automotive Y Y Y Y Y Y Y Y Y Y Y Y Y b 40 C to a 125 C Y Y Y Y Y Y Y Full Duplex Serial Port High Speed I O Subsystem 16-Bit Timer 16-Bit Up Down Counter with Capture 3 Pulse-Width-Modulated Outputs Four 16-Bit Software Timers 8- or 10-Bit 8-Channel A D Converter with Sample Hold HOLD HLDA Bus Protocol OTP One-Time Programmable and QROM Versions Available in 12 MHz and 16 MHz Versions 16 MHz Operation 32 Kbytes of On-Chip EPROM 232 Byte Register File 768 Bytes of Additional RAM Register-to-Register Architecture 28 Interrupt Sources 16 Vectors Peripheral Transaction Server 1 75 ms 16 x 16 Multiply (16 MHz) 3 0 ms 32 16 Divide (16 MHz) Powerdown and Idle Modes Five 8-Bit I O Ports 16-Bit Watchdog Timer Dynamically Configurable 8-Bit or 16-Bit Buswidth Y Y Y Y The 87C196KD 16-bit microcontroller is a high-performance member of the MCS 96 microcontroller family The 87C196KD is an enhanced 8XC196KC device with 1000 bytes RAM 16 MHz operation and 32 Kbytes of on-chip EPROM Intel’s CHMOS process provides a high-performance processor along with low power consumption Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or start an A D conversion Events can be based on the timer or up down counter NOTICE This datasheet contains information on products in full production Specifications within this datasheet are subject to change without notice Verify with your local Intel sales office that you have the latest datasheet before finalizing a design MCS 96 is a registered trademark of Intel Corporation Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 January 1995 Order Number 272168-002 AUTOMOTIVE 87C196KD 272168 – 1 Figure 1 87C196KD Block Diagram 272168 – 2 Figure 2 The 87C196KD Family Nomenclature 87C196KD Enhanced Feature Set over the 87C196KC 1 The 87C196KD has twice the RAM and twice the EPROM of the 87C196KC 2 The vertical windowing scheme has been extended to allow all 1000 bytes of register RAM to be windowed into the lower register file 3 A CLKOUT disable bit has been added to the IOC3 SFR This can be used to reduce noise in systems not requiring the CLKOUT signal 2 AUTOMOTIVE 87C196KD PACKAGING PLCC 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 Description ACH7 P0 7 ACH6 P0 6 ACH2 P0 2 ACH0 P0 0 ACH1 P0 1 ACH3 P0 3 NMI EA VCC VSS XTAL1 XTAL2 CLKOUT BUSWIDTH INST ALE ADV RD AD0 P3 0 AD1 P3 1 AD2 P3 2 AD3 P3 3 AD4 P3 4 AD5 P3 5 PLCC 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Description AD6 P3 6 AD7 P3 7 AD8 P4 0 AD9 P4 1 AD10 P4 2 AD11 P4 3 AD12 P4 4 AD13 P4 5 AD14 P4 6 AD15 P4 7 T2CLK P2 3 READY T2RST P2 4 BHE WRH WR WRL PWM0 P2 5 P2 7 T2CAPTURE VPP VSS HSO 3 HSO 2 P2 6 T2UP-DN P1 7 HOLD PLCC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Description P1 6 HLDA P1 5 BREQ HSO 1 HSO 0 HSO 5 HSI 3 HSO 4 HSI 2 HSI 1 HSI 0 P1 4 PWM2 P1 3 PWM1 P1 2 P1 1 P1 0 TXD P2 0 RXD P2 1 RESET EXTINT P2 2 VSS VREF ANGND ACH4 P 04 ACH5 P 05 Figure 3 68-Pin PLCC Functional Pin-out 3 AUTOMOTIVE 87C196KD 272168 – 3 Figure 4 68-Pin PLCC Package Table 1 Prefix Identification PLCC 87C196KD OTP Version AN87C196KD 4 AUTOMOTIVE 87C196KD PIN DESCRIPTIONS Symbol VCC VSS VREF Main supply voltage (5V) Digital circuit ground (0V) There are three VSS pins all of which must be connected Reference voltage for the A D converter (5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference ground for the A D converter Must be held at nominally the same potential as VSS Timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this function is not used VPP may be tied to VCC This pin is the programming voltage on the EPROM device Input of the oscillator inverter and of the internal clock generator Output of the oscillator inverter Output of the internal clock generator The frequency of CLKOUT is frequency Reset input to the chip Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH is a 0 an 8-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus A positive transition causes a vector through 203EH Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is activated only during external memory accesses and output low for a data fetch Input for memory select (External Access) EA equal to a TTL-high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip ROM EPROM EA equal to a TTL-low causes accesses to those locations to be directed to off-chip memory Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a signal to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during external memory accesses Read signal output to external memory RD is activated only during external memory reads Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is activated only during external memory writes Bus High Enable or Write High output to external memory as selected by the CCR BHE e 0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0 selects the bank of memory that is connected to the low byte of the data bus Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH is valid only during 16-bit external memory write cycles the oscillator Name and Function ANGND VPP XTAL1 XTAL2 CLKOUT RESET BUSWIDTH NMI INST EA ALE ADV RD WR WRL BHE WRH 5 AUTOMOTIVE 87C196KD PIN DESCRIPTIONS (Continued) Symbol READY HSI HSO Port 0 Port 1 Port 2 Ports 3 and 4 HOLD HLDA BREQ Name and Function Ready input to lengthen external memory cycles for interfacing to slow or dynamic memory or for bus sharing When the external memory is not being used READY has no effect Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and HSI 3 Two of them (HSI 2 and HSI 3) are shared with the HSO Unit Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSI 3 HSO 4 and HSO 5 Two of them (HSO 4 and HSO 5) are shared with the HSI Unit 8-bit high impedance input-only port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter 8-bit quasi-bidirectional I O port 8-bit multi-functional port All of its pins are shared with other functions in the 87C196KD 8-bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus Bus Hold input requesting control of the bus Bus Hold acknowledge output indicating release of the bus Bus Request output activated when the bus controller has a pending external memory cycle 6 AUTOMOTIVE 87C196KD ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient Temperature Under Bias Storage Temperature Voltage On Any Pin to VSS Except EA and VPP Voltage from EA or VPP to VSS Power Dissipation b 40 C to a 125 C b 65 C to a 150 C b 0 5V to a 7 0V b 0 5V to a 13 0V NOTICE This is a production data sheet The specifications are subject to change without notice WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability 0 43W OPERATING CONDITIONS Symbol TA VCC VREF FOSC Description Ambient Temperature Under Bias Digital Supply Voltage Analog Supply Voltage Oscillator Frequency Min b 40 Max a 125 Units C V V MHz 4 50 4 50 4 5 50 5 50 16 NOTE ANGND and VSS should be nominally at the same potential DC CHARACTERISTICS Symbol VIL VIH VIH1 VIH2 VOL Input Low Voltage (Over Specified Operating Conditions) Min b0 5 Description Max 08 VCC a 0 5 VCC a 0 5 VCC a 0 5 03 0 45 15 08 Units V V V V V V V V V V V V V V mA Test Conditions Input High Voltage (Note 1) Input High Voltage on XTAL 1 EA Input High Voltage on RESET Output Low Voltage 0 2 VCC a 1 0 0 7 VCC 22 IOL e 200 mA IOL e 2 8 mA IOL e 7 mA IOL e a 0 2 mA IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 mA IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA VIH e VCC b 1 5 V VOL1 VOH Output Low Voltage in RESET on P2 5 (Note 2) Output High Voltage (Standard Outputs) Output High Voltage (Quasi-bidirectional Outputs) Output High Current In RESET on P2 0 (Note 2) VCC b 0 3 VCC b 0 7 VCC b 1 5 VCC b 0 3 VCC b 0 7 VCC b 1 5 b0 8 VOH1 IOH2 NOTES 1 All pins except RESET XTAL1 and EA 2 Violating these specifications in Reset may cause the part to enter test modes 7 AUTOMOTIVE 87C196KD DC CHARACTERISTICS Symbol ILI ILI1 ITL IIL ICC IREF IIDLE RRST CS (Over Specified Operating Conditions) Min Typ Max g 10 g3 Description Input Leakage Current (Std Inputs) Input Leakage Current (Port 0) 1 to 0 Transition Current (QBD Pins) Logical 0 Input Current (QBD Pins) Active Mode Current in Reset A D Converter Reference Current Idle Mode Current Reset Pullup Resistor Pin Capacitance (Any Pin to VSS) Units mA mA mA mA mA mA mA X pF Test Conditions 0 k VIN k VCC b 0 3V 0 k VIN k VREF VIN e 2 0V VIN e 0 45V XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V b 650 b 70 65 2 15 6K 75 5 30 65K 10 VCC e 5 0V VIN e 4 0V NOTES (Notes apply to all specifications) 1 QBD (Quasi-bidirectional) pins include Port 1 P2 6 and P2 7 2 Standard Outputs include AD0–15 RD WR ALE BHE INST HSO pins PWM P2 5 CLKOUT RESET Ports 3 and 4 TXD P2 0 and RXD (in serial mode 0) The VOH specification is not valid for RESET Ports 3 and 4 are open-drain outputs 3 Standard Inputs include HSI pins READY BUSWIDTH NMI RXD P2 1 EXTINT P2 2 T2CLK P2 3 and T2RST P2 4 4 Maximum current per pin must be externally limited to the following values if VOL is held above 0 45V or VOH is held below VCC b 0 7V IOL on Output pins 10 mA IOH on quasi-bidirectional pins self limiting IOH on Standard Output pins 10 mA 5 Maximum current per bus pin (data and control) during normal operation is g 3 2 mA 6 During normal (non-transient) conditions the following total current limits apply IOH is self limiting Port 1 P2 6 IOL 29 mA IOH 26 mA HSO P2 0 RXD RESET IOL 29 mA IOL 13 mA IOH 11 mA P2 5 P2 7 WR BHE IOH 52 mA AD0 – AD15 IOL 52 mA IOH 13 mA RD ALE INST–CLKOUT IOL 13 mA 8 AUTOMOTIVE 87C196KD ICC MAX e 3 88 c Freq a 8 43 IIDLE MAX e 1 65 c Freq a 2 2 272168 – 4 Figure 5 ICC and IIDLE vs Frequency AC CHARACTERISTICS For use over specified operating conditions Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 MHz The system must meet these specifications to work with the 87C196KD Symbol TAVYV TLLYV TYLYH TCLYX TLLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRXDX Description Address Valid to READY Setup ALE Low to READY Setup Non READY Time READY Hold after CLKOUT Low READY Hold after ALE Low Address Valid to Buswidth Setup ALE Low to Buswidth Setup Buswidth Hold after CLKOUT Low Address Valid to Input Data Valid RD Active to Input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD Inactive 0 0 3 TOSC b 55 TOSC b 25 TOSC b 45 TOSC 0 TOSC b 15 Min Max 2 TOSC b 75 TOSC b 77 No upper limit TOSC b 30 2 TOSC b 40 2 TOSC b 75 TOSC b 65 Units ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 2) (Note 1) (Note 1) Notes NOTES 1 If max is exceeded additional wait states will occur 2 If wait states are used add 2 TOSC N where N e number of wait states 9 AUTOMOTIVE 87C196KD AC CHARACTERISTICS (Continued) For use over specified operating conditions Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 MHz The 87C196KD will meet these specifications Symbol FXTAL TOSC TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Description Frequency on XTAL1 I FXTAL XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling Edge to ALE Rising ALE Falling Edge to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Falling Edge Address Hold after ALE Falling Edge ALE Falling Edge to RD Falling Edge RD Low to CLKOUT Falling Edge RD Low Period RD Rising Edge to ALE Rising Edge RD Low to Address Float ALE Falling Edge to WR Falling Edge CLKOUT Low to WR Falling Edge Data Stable to WR Rising Edge CLKOUT High to WR Rising Edge WR Low Period Data Hold after WR Rising Edge WR Rising Edge to ALE Rising Edge BHE INST after WR Rising Edge AD8–15 HOLD after WR Rising BHE INST after RD Rising Edge AD8–15 HOLD after RD Rising TOSC b 10 0 TOSC b 30 b5 Min 40 62 5 20 2 TOSC TOSC b 10 b5 b 25 Max 16 250 110 Units MHz ns ns ns ns ns ns ns ns Notes (Note 1) TOSC a 15 15 a 15 4 TOSC TOSC b 10 TOSC b 15 TOSC b 35 TOSC b 35 0 TOSC b 5 TOSC TOSC a 25 5 35 TOSC a 10 (Note 4) ns ns ns ns ns ns ns 25 ns (Note 4) 15 ns ns ns TOSC a 15 ns ns ns ns ns (Note 3) (Note 3) (Note 2) (Note 4) (Note 4) (Note 2) TOSC b 30 TOSC b 25 TOSC b 10 TOSC b 10 TOSC b 30 TOSC b 10 TOSC b 25 NOTES 1 Testing performed at 4 0 MHz However the device is static by design and will typically operate below 1 Hz 2 Assuming back-to-back bus cycles 3 8-Bit bus only 4 If wait states are used add 2 TOSC N where N e number of wait states 10 AUTOMOTIVE 87C196KD System Bus Timings 272168 – 5 11 AUTOMOTIVE 87C196KD READY Timings (One Wait State) 272168 – 6 Buswidth Timings 272168 – 7 12 AUTOMOTIVE 87C196KD HOLD HLDA Timings Symbol THVCH TCLHAL TCLBRL THALAZ THALBZ TCLHAH TCLBRH THAHAX THAHBV TCLLH HOLD Setup CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float HLDA Low to BHE INST RD WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE INST RD WR Valid CLKOUT Low to ALE High b 15 b 15 b 15 b 10 b5 Description Min 60 b 15 b 15 Max Units ns Notes (Note 1) 15 15 15 20 15 15 ns ns ns ns ns ns ns 15 15 ns ns NOTE 1 To guarantee recognition at next clock DC SPECIFICATIONS IN HOLD Min Weak Pullups on ADV RD WR WRL BHE Weak Pulldowns on ALE INST 50K Max 250K Units VCC e 5 5V VIN e 0 45V 10K 50K VCC e 5 5V VIN e 2 4 272168 – 8 13 AUTOMOTIVE 87C196KD EXTERNAL CLOCK DRIVE Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Frequency High Time Low Time Rise Time Fall Time Min 40 62 5 22 22 10 10 Max 16 0 250 Units MHz ns ns ns ns ns EXTERNAL CLOCK DRIVE WAVEFORMS 272168 – 9 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 272168 – 10 AC Testing inputs are driven at 2 4V for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0’’ Timing measurements are made at 2 0V for a Logic ‘‘1’’ and 0 8V for a Logic ‘‘0’’ 272168 – 11 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH VOL level occurs IOL IOH e g 15 mA EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points Conditions H High L Low V Valid X No Longer Valid Z Floating Signals A Address B BHE C D G H HA CLKOUT DATA Buswidth HOLD HLDA L BR R W X Y Q ALE ADV BREQ RD WR WRH WRL XTAL1 READY Data Out 14 AUTOMOTIVE 87C196KD AC CHARACTERISTICS SERIAL PORT TIMING Symbol TXLXL TXLXH TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ SERIAL PORT SHIFT REGISTER MODE SHIFT REGISTER MODE Parameter Min 6 TOSC 4 TOSC b 50 4 TOSC 2 TOSC b 50 2 TOSC b 50 2 TOSC b 50 2 TOSC a 50 TOSC a 50 0 1 TOSC 2 TOSC a 50 4 TOSC a 50 Max Units ns ns ns ns ns ns ns ns ns ns Serial Port Clock Period (BRR t 8002H) Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) Serial Port Clock Period (BRR e 8001H) Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float WAVEFORM SERIAL PORT SHIFT REGISTER MODE SERIAL PORT WAVEFORM SHIFT REGISTER MODE 272168 – 12 15 AUTOMOTIVE 87C196KD EPROM SPECIFICATIONS AC EPROM Programming Characteristics Operating Conditions Load Capacitance e 150 pF TA e a 25 C g 5 C VCC VREF e 5V VSS ANGND e 0V VPP e 12 50V g 0 25V EA e 12 50V g 0 25V Symbol TSHLL TLLLH TAVLL TLLAX TPLDV TPHDX TDVPL TPLDX TPLPH(2) TPHLL TLHPL TPHPL TPHIL TILIH TILVH TILPL TPHVL Description Reset High to First PALE Low PALE Pulse Width Address Setup Time Address Hold Time PROG Low to Word Dump Valid Word Dump Data Hold Data Setup Time Data Hold Time PROG Pulse Width PROG High to Next PALE Low PALE High to PROG Low PROG High to Next PROG Low PROG High to AINC Low AINC Pulse Width PVER Hold after AINC Low AINC Low to PROG Low PROG High to PVER Valid 0 400 50 220 220 220 0 240 50 170 220 Min 1100 50 0 100 50 50 Max Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC NOTES 1 Run Time Programming is done with FOSC e 6 0 MHz to 12 0 MHz VREF e 5V g 0 50V TA e a 25 C to g 5 C and VPP e 12 50V For run-time programming over a full operating range contact the factory 2 This specification is for the Word Dump Mode For programming pulses use 300 TOSC a 100 ms DC EPROM Programming Characteristics Symbol IPP Description VPP Supply Current (When Programming) Min Max 100 Units mA NOTE VPP must be within 1V of VCC while VCC k 4 5V VPP must not have a low impedance path to ground of VSS while VCC l 4 5V 16 AUTOMOTIVE 87C196KD EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 272168 – 13 SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT 272168 – 14 17 AUTOMOTIVE 87C196KD SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT 272168 – 15 18 AUTOMOTIVE 87C196KD of VREF VREF must be close to VCC since it supplies both the resistor ladder and the digital section of the converter 10-BIT A D CHARACTERISTICS The speed of the A D converter in the 10-bit mode can be adjusted by setting a clock prescaler on or off At high frequencies more time is needed for the comparator to settle The maximum frequency with the clock prescaler disabled is 6 MHz The conversion times with the prescaler turned on or off is shown in the table below The AD TIME register has not been characterized for the 10-bit mode The converter is ratiometric so the absolute accuracy is dependent on the accuracy and stability Clock Prescaler On IOC2 4 e 0 156 5 States 19 5 ms 16 MHz Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Error Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Sample Time Prescaler On Prescaler Off Input Capacitance 16 8 3 b 60 b 60 g 0 25 g3 g3 A D CONVERTER SPECIFICATIONS The specifications given below assume adherence to the Operating Conditions section of this datasheet Testing is performed with VREF e 5 12V Clock Prescaler Off IOC2 4 e 1 89 5 States 29 8 ms 6 MHz Minimum 1024 10 0 Maximum 1024 10 g4 Typical (3) Units Levels Bits LSBs LSBs LSBs Notes 0 l b1 g4 LSBs LSBs LSBs LSBs LSB C LSB C LSB C a2 g1 0 0 009 0 009 0 009 b 60 dB dB dB 12 1 1 750 0 1 2K 30 X mA States States pF NOTES An ‘‘LSB’’ as used here has a value of approximately 5 mV 1 DC to 100 KHz 2 Multiplexer Break-Before-Make Guaranteed 3 Typical values are expected for most devices at 25 C 19 AUTOMOTIVE 87C196KD 8-BIT MODE A D CHARACTERISTICS The 8-bit mode trades off resolution for a faster conversion time The AD TIME register must be used when performing an 8-bit conversion The following specifications are tested 16 MHz with OA6H in AD TIME The actual AD TIME register is tested with all possible values to ensure functionality but the accuracy of the A D converter is not Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Error Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity g 0 25 g1 g2 Sample Time 20 States Convert Time 56 States A6H in AD TIME 9 8 ms 16 MHz Typical Minimum 256 8 0 Maximum 256 8 g2 Units Levels Bits LSBs LSBs LSBs Notes 0 l b1 g2 LSBs LSBs LSBs LSBs LSB C LSB C LSB C a1 g1 0 003 0 003 0 003 NOTES An ‘‘LSB’’ as used here has a value of approximately 20 mV 1 Typical values are expected for most devices at 25 C 8XC196KB TO 87C196KD DESIGN CONSIDERATIONS 1 Memory Map The 87C196KD has 512 bytes of RAM SFRs and 32K of ROM EPROM The extra 256 bytes of RAM will reside in locations 100H – 1FFH and the extra 24K of EPROM will reside in locations 4000H–9FFFH These locations are external memory on the 87C196KB 2 The CDE pin on the KB has become a VSS pin on the KC to support 16 MHz operation 3 EPROM programming The 87C196KD has a different programming algorithm to support 32K of on-board memory When performing Run-Time Programming use the section of code on page 99 of the 80C196KC User’s Guide Order Number 270704 4 ONCE Mode Entry The ONCE mode is entered on the 87C196KD by driving the TXD pin low on the rising edge of RESET The TXD pin is held high by a pullup that is specified at 1 4 mA and remain at 2 0V This Pullup must not be overridden or the 87C196KD will enter the ONCE mode 5 During the bus HOLD state the 87C196KD weakly holds RD WR ALE BHE and INST in their inactive states The 87C196KB only holds ALE in its inactive state 6 A RESET pulse from the 87C196KD is 16 states rather than 4 states as on the 87C196KB (i e a watchdog timer overflow) This provides a longer RESET pulse for other devices in the system 20 AUTOMOTIVE 87C196KD 2 In Mode 0 the serial port does not work if the highest baud rate is selected (SP BAUD e 8001h) Data shifted into the device will not be correctly read at this baud rate 8XC196KD ERRATA 1 It is possible for the device to fail to recognize an interrupt on EXTINIT for both P2 2 and P0 7 and NMI The problem is most likely to occur on P0 7 while the device is operating at low voltage ( k 4 7V) high frequency (16 MHz) and high temperature ( l 85 C) There is a window of about 2 ns near clockout falling during which these interrupts may be missed DATASHEET REVISION HISTORY The following are the key differences between this datasheet and the -005 version 1 The ‘‘preliminary’’ status was dropped and replaced with production status (no label) Trademarks were updated 21