87C51

87C51 80C51BH 80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial Express 87C51 80C51BH 80C51BHP 80C31BH See Table 1 for Proliferation Options Y Y Y High Performance CHMOS EPROM 24 MHz Operation Improved Quick-Pulse Programming Algorithm 3-Level Program Memory Lock Boolean Processor 128-Byte Data RAM 32 Programmable I O Lines Two 16-Bit Timer Counters Extended Temperature Range ( b 40 C to a 85 C) Y Y Y 5 Interrupt Sources Programmable Serial Port TTL- and CMOS-Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space ONCE Mode Facilitates System Testing Power Control Modes Idle Power Down Y Y Y Y Y Y Y Y Y Y MEMORY ORGANIZATION PROGRAM MEMORY Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH) In addition the device can address up to 64K of program memory external to the chip DATA MEMORY This microcontroller has a 128 x 8 on-chip RAM In addition it can address up to 64 Kbytes of external data memory The Intel 87C51 80C51BH 80C31BH is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology Being a member of the MCS 51 controller family the 87C51 80C51BH 80C31BH uses the same powerful instruction set has the same architecture and is pin-forpin compatible with the existing MCS 51 controller family of products The 80C51BHP is identical to the 80C51BH When ordering the 80C51BHP customers must submit the 64 byte encryption table together with the ROM code Lock bit 1 will be set to enable the internal ROM code protection and at the same time allows code verification The extremely low operating power along with the two reduced power modes Idle and Power Down make this part very suitable for low power applications The Idle mode freezes the CPU while allowing the RAM timer counters serial port and interrupt system to continue functioning The Power Down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative For the remainder of this document the 87C51 80C51BH and 80C31BH will be referred to as the 87C51 BH unless information applies to a specific device Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 October 1995 Order Number 272335-003 87C51 80C51BH 80C31BH Table 1 Proliferation Options Standard 80C31BH 80C51BH 80C51BHP 87C51 NOTES 35 -1 3 5 -2 0 5 -24 3 5 MHz MHz MHz MHz to to to to 12 16 12 24 MHz MHz MHz MHz VCC VCC VCC VCC e e e e -1 X X X X -2 X X X X -24 X X X X X X X X 5V 5V 5V 5V g 20% g 20% g 20% g 20% 272335 – 1 Figure 1 87C51 BH Block Diagram 2 87C51 80C51BH 80C31BH PROCESS INFORMATION The 87C51 BH is manufactured on the CHMOS III-E process Additional process and reliability information is available in Intel’s Components Quality and Reliability Handbook Order No 210997 PACKAGES Part 87C51 BH Prefix P D N S Package Type 40-Pin Plastic DIP (OTP) 40-Pin CERDIP (EPROM) 44-Pin PLCC (OTP) 44-Pin QFP (OTP) 272335 – 3 272335 – 2 PLCC DIP 272335 – 4 Do not connect reserved pins QFP Figure 2 Pin Connections 3 87C51 80C51BH 80C31BH Port 2 also receives some control signals and the high-order address bits during EPROM programming and program verification Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (IIL on the data sheet) because of the pullups Port 3 also serves the functions of various special features of the MCS-51 Family as listed below Pin P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Name RXD TXD INT0 INT1 T0 T1 WR RD Alternate Function Serial input line Serial output line External Interrupt 0 External Interrupt 1 Timer 0 external input Timer 1 external input External Data Memory Write strobe External Data Memory Read strobe PIN DESCRIPTION VCC Supply voltage during normal Idle and Power Down operations VSS Circuit ground Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1’s written to them float and in that state can be used as high-impedance inputs Port 0 is also the multiplexed low-order address and data bus during accesses to external memory In this application it uses strong internal pullups when emitting 1’s Port 0 also receives the code bytes during EPROM programming and outputs the code bytes during program verification External pullups are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups Port 1 also receives the low-order address bytes during EPROM programming and program verification Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups Port 2 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups Port 2 emits the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX DPTR) In this application it uses strong internal pullups when emitting 1’s During accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Port 3 also receives some control signals for EPROM programming and program verification RST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device The port pins will be driven to their reset condition when a minimum VIH1 voltage is applied whether the oscillator is running or not An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC ALE PROG Address Latch Enable output signal for latching the low byte of the address during accesses to external memory This pin is also the program pulse input (PROG) during EPROM programming for the 87C51 If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With this bit set the pin is weakly pulled high However the ALE disable feature will be suspended during a MOVX or MOVC instruction idle mode power down mode and ICE mode The ALE disable feature will be terminated by reset When the ALE disable feature is suspended or terminated the ALE pin will no longer be pulled up weakly Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode 4 87C51 80C51BH 80C31BH In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory PSEN Program Store Enable is the Read strobe to External Program Memory When the 87C51 BH is executing from Internal Program Memory PSEN is inactive (high) When the device is executing code from External Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to External Data Memory EA VPP External Access enable EA must be strapped to VSS in order to enable the 87C51 BH to fetch code from External Program Memory locations starting at 0000H up to FFFFH Note however that if either of the Lock Bits is programmed the logic level at EA is internally latched during reset EA must be strapped to VCC for internal program execution This pin also receives the programming supply voltage (VPP) during EPROM programming XTAL1 Input to the inverting oscillator amplifier XTAL2 Output from the inverting oscillator amplifier OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 3 To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected as shown in Figure 4 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data sheet must be observed An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF 272335 – 6 Figure 4 External Clock Drive 272335 – 5 Figure 3 Using the On-Chip Oscillator 5 87C51 80C51BH 80C31BH the on-chip RAM An external interrupt allows both the SFRs and on-chip RAM to retain their values To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms) With an external interrupt INT0 and INT1 must be enabled and configured as level-sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction to be executed after RET1 will be the one following the instruction that put the device into Power Down IDLE MODE In Idle Mode the CPU puts itself to sleep while all the on-chip peripherals remain active The mode is invoked by software The content of the on-chip RAM and all the Special Functions Registers remain unchanged during this mode The Idle Mode can be terminated by any enabled interrupt or by a hardware reset It should be noted that when Idle is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory DESIGN CONSIDERATIONS  Exposure to light when the device is in operation may cause logic errors For this reason it is suggested that an opaque label be placed over the window when the die is exposed to ambient light POWER DOWN MODE To save even more power a Power Down mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power Down mode is transmitted On the 87C51 BH either a hardware reset or an external interrupt can cause an exit from Power Down Reset redefines all the SFR’s but does not change  The 87C51 BH now have some additional features The features are asynchronous port reset 4 interrupt priority levels power off flag ALE disable serial port automatic address recognition serial port framing error detection 64-byte encryption array and 3 program lock bits These features cannot be used with the older versions of 80C51BH 80C31BH The newer version of 80C51BH 80C31BH will have change identifier ‘‘A’’ appended to the lot number Table 2 Status of the External Pins during Idle and Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data 6 87C51 80C51BH 80C31BH Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number The prefixes are listed in Table 3 For the extended temperature range option this data sheet specifies the parameters which deviate from their commercial temperature range limits Table 3 Prefix Identification Prefix P D N S TP TD Package Type Plastic Cerdip PLCC QFP Plastic Cerdip PLCC QFP Plastic Cerdip PLCC Temperature Range Commercial Commercial Commercial Commercial Extended Extended Extended Extended Extended Extended Extended Burn-in No No No No No No No No Yes Yes Yes ONCE MODE The ONCE (‘‘On-Circuit Emulation’’) mode facilitates testing and debugging of systems using the 87C51 BH without the 87C51 BH having to be removed from the circuit The ONCE mode is invoked by 1 Pull ALE low while the device is in reset and PSEN is high 2 Hold ALE low as RST is deactivated While the device is in ONCE mode the Port 0 pins float and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the 87C51 BH is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied 87C51 BH EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the MCS-51 family of microcontrollers These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial temperature The EXPRESS program includes the commercial standard temperature range with burn-in and an extended temperature range with or without burn-in With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 C to 70 C With the extended temperature range option operational characteristics are guaranteed over the range of b 40 C to a 85 C The optional burn-in is dynamic for a minimum time of 160 hours at 125 C with VCC e 6 9V g 0 25V following guidelines in MIL-STD-883 Method 1015 TN TS LP LD LN NOTE Contact distributor or local sales office to match EXPRESS prefix to proper device Examples P87C51 indicates 87C51 in a plastic package and specified for commercial temperature range without burn-in LD87C51 indicates 87C51 in a cerdip package and specified for extended temperature range with burnin 7 87C51 80C51BH 80C31BH ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias b 40 C to a 85 C Storage Temperature Voltage on EA VPP Pin to VSS Voltage on Any Other Pin to VSS Maximum IOL per I O Pin b 65 C to a 150 C 0V to a 13 0V b 0 5V to a 6 5V NOTICE This data sheet contains preliminary information on new products in production It is valid for the devices indicated in the revision history The specifications are subject to change without notice 15 mA Power Dissipation 1 5W (Based on package heat transfer limitations not device power consumption ) WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability OPERATING CONDITIONS Symbol TA Description Ambient Temperature Under Bias Commercial Express Supply Voltage Oscillator Frequency 87C51 BH 87C51-1 BH-1 87C51-2 BH-2 87C51-24 BH-24 Min 0 b 40 Max a 70 a 85 Unit C C V MHz VCC fOSC 45 35 35 05 35 55 12 16 12 24 DC CHARACTERISTICS Symbol VIL Parameter Input Low Voltage Commercial Express (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated Min b0 5 b0 5 Typ(1) Max 0 2 VCC b 0 1 0 2 VCC b 0 15 0 2 VCC b 0 3 0 2 VCC b 0 35 Unit V V V V Test Conditions VIL1 Input Low Voltage EA Commercial Express Input High Voltage (Except XTAL1 RST) Commercial Express Input High Voltage (XTAL1 RST) Commercial Express Output Low Voltage(6) (Ports 1 2 3) 0 b0 5 VIH 0 2 VCC a 0 9 0 2 VCC a 1 VCC a 0 5 VCC a 0 5 V V VIH1 0 7 VCC 0 7 VCC a 0 1 VCC a 0 5 VCC a 0 5 03 0 45 10 V V V V V IOL e 100 mA(2) IOL e 1 6 mA(2) IOL e 3 5 mA(2) VOL 8 87C51 80C51BH 80C31BH DC CHARACTERISTICS Symbol VOL1 (Over Operating Conditions) (Continued) Min Typ(1) Max 03 0 45 10 VCC b 0 3 VCC b 0 7 VCC b 1 5 VCC b 0 3 VCC b 0 7 VCC b 1 5 Unit V V V V V V V V V Test Conditions IOL e 200 mA(2) IOL e 3 2 mA (2) IOL e 7 0 mA(2) IOH e b 10 mA(3) IOH e b 30 mA(3) IOH e b 60 mA(3) IOH e b 200 mA(3) IOH e b 3 2 mA(3) IOH e b 7 0 mA(3) VIN e 0 45V b 50 b 75 g 10 Parameter Output Low Voltage(6) (Port 0 ALE PSEN) VOH Output High Voltage (Ports 1 2 3 ALE PSEN) VOH1 Output High Voltage (Port 0 in External Bus Mode) IIL Logical 0 Input Current (Ports 1 2 3) Commercial Express Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Ports 1 2 3) Commercial Express RST Pulldown Resistor Pin Capacitance Power Supply Current Active Mode 12 MHz (Figure 5) 16 MHz 24 MHz Idle Mode 12 MHz (Figure 5) 16 MHz 24 MHz Power Down Mode 40 10 mA mA mA 0 45 k VIN k VCC VIN e 2V ILI ITL b 650 b 750 mA mA kX pF 1 MHz 25 C (Note 4) RRST CIO ICC 225 11 5 20 26 38 75 95 13 5 50 mA mA mA mA mA mA mA 35 5 9 87C51 80C51BH 80C31BH NOTES 1 ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed The values listed are at room temp 5V 2 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the VOLs of ALE and Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic 3 Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0 9VCC specification when the address bits are stabilizing 4 See Figures 6 through 8 for ICC test conditions Minimum VCC for Power Down is 2V 5 Under steady state (non-transient) conditions IOL must be externally limited as follows 10 mA Maximum IOL per port pin Maximum IOL per 8-bit port Port 0 26 mA Ports 1 2 and 3 15 mA 71 mA Maximum total IOL for all output pins If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink greater than the listed test conditions 272335 – 26 Figure 5 87C51 BH ICC vs Frequency 10 87C51 80C51BH 80C31BH 272335 – 10 Figure 6 ICC Test Condition Active Mode All other pins are disconnected 272335 – 8 272335 – 9 Figure 7 ICC Test Condition Idle Mode All other pins are disconnected Figure 9 ICC Test Condition Power Down Mode All other pins are disconnected VCC e 2V to 5 5V 272335 – 11 Figure 8 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns 11 87C51 80C51BH 80C31BH L Logic level LOW or ALE P PSEN Q Output data R RD signal T Time V Valid W WR signal X No longer a valid logic level Z Float For example TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters The first character is always a ‘T’ (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input data H Logic level HIGH I Instruction (program memory contents) AC CHARACTERISTICS (Over Operating Conditions Load Capacitance for Port 0 ALE and PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to 87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2 Oscillator Symbol 1 TCLCL Parameter Oscillator Frequency 87C51 BH 87C51-1 BH-1 87C51-2 BH-2 87C51-24 BH-24 ALE Pulse Width Address Valid to ALE Low 87C51 BH 87C51-24 BH-24 Address Hold After ALE Low ALE Low to Valid Instr In 87C51 BH 87C51-24 BH-24 ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instr In 87C51 BH 87C51-24 BH-24 53 205 145 35 127 43 12 53 234 91 12 80 TCLCL b 30 3TCLCL b 45 3TCLCL b 105 3TCLCL b 90 12 43 12 MHz Min Max 24 MHz Min Max Min 35 35 05 35 2TCLCL b 40 TCLCL b 40 TCLCL b 30 TCLCL b 30 4TCLCL b 100 4TCLCL b 75 Variable Max 12 16 12 24 MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns Units TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV 12 87C51 80C51BH 80C31BH EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to 87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2 (Continued) Oscillator Symbol Parameter 12 MHz Min TPXIX TPXIZ Input Instr Hold After PSEN Input Instr Float After PSEN 87C51 BH 87C51-24 BH-24 Address to Valid Instr In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In 87C51 BH 87C51-24 BH-24 Data Hold After RD Data Float After RD ALE Low to Valid Data In 87C51 BH 87C51-24 BH-24 Address to Valid Data In 87C51 BH 87C51-24 BH-24 ALE Low to RD or WR Low Address to RD or WR Low 87C51 BH 87C51-24 BH-24 Data Valid to WR Transition 87C51 BH 80C51-24 BH-24 200 203 77 33 12 0 107 517 243 585 285 300 75 175 3TCLCL b 50 4TCLCL b 130 4TCLCL b 90 TCLCL b 50 TCLCL b 30 400 400 252 113 0 23 0 2TCLCL b 60 8TCLCL b 150 8TCLCL b 90 9TCLCL b 165 9TCLCL b 90 3TCLCL a 50 0 59 21 312 10 150 150 103 10 6TCLCL b 100 6TCLCL b 100 5TCLCL b 165 5TCLCL b 95 Max 24 MHz Min 0 Max Min 0 TCLCL b 25 TCLCL b 20 5TCLCL b 105 10 Variable Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX 13 87C51 80C51BH 80C31BH EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to 87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2 (Continued) Oscillator Symbol Parameter 12 MHz Min TWHQX Data Hold After WR 87C51 BH 87C51-24 BH-24 Data Valid to WR High 87C51 BH 87C51-24 BH-24 RD Low to Address Float RD or WR High to ALE High 87C51 BH 87C51-24 BH-24 43 33 7 433 222 0 123 12 71 0 TCLCL b 40 TCLCL b 30 Max 24 MHz Min Max Min TCLCL b 50 TCLCL b 35 7TCLCL b 150 7TCLCL b 70 0 TCLCL a 40 TCLCL a 30 Variable Max ns ns ns ns ns ns ns Units TQVWH TRLAZ TWHLH EXTERNAL PROGRAM MEMORY READ CYCLE 272335 – 12 EXTERNAL DATA MEMORY READ CYCLE 272335 – 13 14 87C51 80C51BH 80C31BH EXTERNAL DATA MEMORY WRITE CYCLE 272335-14 EXTERNAL CLOCK DRIVE All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to 87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2 Symbol 1 TCLCL Parameter Oscillator Frequency 87C51 BH 87C51-1 BH-1 87C51-2 BH-2 87C51-24 BH-24 High Time 87C51 BH 8751-24 BH-24 Low Time 87C51 BH 87C51-24 BH-24 Rise Time 87C51 BH 87C51-24 BH-24 Fall Time 87C51 BH 87C51-24 BH-24 Min 35 35 05 35 20 0 35TCLCL 20 0 35TCLCL Max 12 16 12 24 Units MHz MHz MHz MHz ns ns ns ns ns ns ns ns TCHCX 0 65TCLCL TCLCX 0 65TCLCL 20 10 20 10 TCLCH TCHCL EXTERNAL CLOCK DRIVE WAVEFORM 272335 – 15 15 87C51 80C51BH 80C31BH SERIAL PORT TIMING Symbol SHIFT REGISTER MODE 12 MHz Oscillator Min Max 24 MHz Oscillator Min 0 500 284 Max Variable Oscillator Min 12TCLCL 10TCLCL b 133 Max ms ns ns Units Parameter TXLXL TQVXH TXHQX Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge 87C51 BH 87C51-24 BH-24 Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 10 700 50 34 0 0 2TCLCL b 117 2TCLCL b 34 0 ns TXHDX TXHDV 700 283 10TCLCL b 133 ns SHIFT REGISTER MODE TIMING WAVEFORMS 272335 – 18 AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 272335 – 19 AC inputs during testing are driven at VCC b 0 5 for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0 ’’ Timing measurements are made at VIH min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’ 272335 – 20 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH VOL level occurs IOL IOH e g 20 mA 16 87C51 80C51BH 80C31BH PROGRAMMING THE 87C51 The part must be running with a 4 MHz to 6 MHz oscillator The address of an EPROM location to be programmed is applied to address lines while the code byte to be programmed in that location is applied to data lines Control and program signals must be held at the levels indicated in Table 4 Normally EA VPP is held at logic high until just before ALE PROG is to be pulsed The EA VPP is raised to VPP ALE PROG is pulsed low and then EA VPP is returned to a high (also refer to timing diagrams) NOTE DEFINITION OF TERMS ADDRESS LINES P1 0 – P1 7 P2 0 – P2 5 P3 4 respectively for A0 – A14 DATA LINES P0 0 – P0 7 for D0 – D7 CONTROL SIGNALS RST PSEN P2 6 P2 7 P3 3 P3 6 P3 7 PROGRAM SIGNALS ALE PROG EA VPP  Exceeding the VPP maximum for any amount of time could damage the device permanently The VPP source must be well regulated and free of glitches Table 4 EPROM Programming Modes Mode Program Code Data Verify Code Data Program Encryption Array Address 0–3F Program Lock Bits Bit 1 Bit 2 Bit 3 Read Signature Byte RST H H H H H H H PSEN L L L L L L L H H ALE PROG EA VPP 12 75V H 12 75V 12 75V 12 75V 12 75V H P2 6 L L L H H H L P2 7 H L H H H L L P3 3 H L H H H H L P3 6 H H L H L H L P3 7 H H H H L L L 272335 – 21 See Table 4 for proper input on these pins Figure 10 Programming the EPROM 17 87C51 80C51BH 80C31BH 272335 – 22 For compatibility 25 pulses may be used Figure 11 Programming Waveforms PROGRAMMING ALGORITHM Refer to Table 4 and Figures 10 and 11 for address data and control signals set up To program the 87C51 the following sequence must be exercised 1 Input the valid address on the address lines 2 Input the appropriate data byte on the data lines 3 Activate the correct combination of control signals 4 Raise EA VPP from VCC to 12 75V g 0 25V 5 Pulse ALE PROG 5 times for the EPROM array and 25 times for the encryption table and the lock bits Repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached The 80C51BH has a one level program lock system and a 64-byte encryption table If program protection is desired the user submits the encryption table with their code and both the lock bit and encryption array are programmed by the factory The encryption array is not available without the lock bit For the lock bit to be programmed the user must submit an encryption table The 87C51 has a 3-level program lock system and a 64-byte encryption array Since this is an EPROM device all locations are user-programmable See Table 5 Encryption Array Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1’s) Every time that a byte is addressed during a verify 6 address lines are used to select a byte of the Encryption Array This byte is then exclusive-NOR’ed (XNOR) with the code byte creating an Encryption Verify byte The algorithm with the array in the unprogrammed state (all 1’s) will return the code in its original unmodified form For programming the Encryption Array refer to Table 4 (Programming the EPROM) When using the encryption array one important factor needs to be considered lf a code byte has the value 0FFH verifying the byte will produce the encryption byte value lf a large block ( l 64 bytes) of code is left unprogrammed a verification routine will display the contents of the encryption array For this reason all unused code bytes should be programmed with some value other than 0FFH and not all of them the same value This will ensure maximum program protection Program Verify Verification may be done after programming either one byte or a block of bytes In either case a complete verify of the array will ensure reliable programming of the 87C51 The lock bits cannot be directly verified Verification of the lock bits is done by observing that their features are enabled ROM and EPROM Lock System The program lock system when programmed protects the onboard program against software piracy 18 87C51 80C51BH 80C31BH Program Lock Bits The 87C51 has 3 programmable lock bits that when programmed according to Table 5 will provide different levels of protection for the on-chip code and data Erasing the EPROM also erases the encryption array and the program lock bits returning the part to full functionality Erasure Characteristics (Windowed Devices Only) Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4 000 Angstroms Since sunlight and fluorescent lighting have wavelengths in this range exposure to these light sources over an extended time (about 1 week in sunlight or 3 years in room level fluorescent lighting) could cause inadvertent erasure If an application subjects the device to this type of exposure it is suggested that an opaque label be placed over the window The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec cm2 Exposing the EPROM to an ultraviolet lamp of 12 000 mW cm2 rating for 30 minutes at a distance of about 1 inch should be sufficient Erasure leaves the array in an all 1’s state Reading the Signature Bytes The 87C51 and 80C51BH have 3 signature bytes in locations 30H 31H and 60H To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 4 for Read Signature Byte Location 30H 31H 60H Device All All 87C51 80C51BH Contents 89H 58H 51H 11H Table 5 Program Lock Bits and the Features Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U Protection Type No program lock features enabled (Code verify will still be encrypted by the encryption array if programmed ) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset and further programming of the EPROM is disabled Same as 2 also verify is disabled Same as 3 also external execution is disabled 3 4 P P P P U P 19 87C51 80C51BH 80C31BH EPROM PROGRAMMING EPROM AND ROM VERIFICATION CHARACTERISTICS (TA e 21 C to 27 C VCC e 5V g 10% VSS e 0V) Symbol VPP IPP 1 TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold After PROG Data Setup to PROG Low Data Hold After PROG P2 7 (ENABLE) High to VPP VPP Setup to PROG Low VPP Hold After PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float After ENABLE PROG High to PROG Low 0 10 4 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 10 10 90 110 48TCLCL 48TCLCL 48TCLCL ms ms ms ms Min 12 5 Max 13 0 75 6 Units V mA MHz EPROM PROGRAMMING EPROM AND ROM VERIFICATION WAVEFORMS 272335 – 23 For programming conditions see Figure 10 5 pulses for the EPROM array 25 pulses for the encryption table and lock bits 20 87C51 80C51BH 80C31BH 3 80C51BHP is replaced by 80C51BH with 64-byte encryption table submitted and lock bit 1 set 4 80C51BH 80C31BH are now having some additional features as 87C51 5 Revised PRST value and ICC idle values 6 Added P3 3 control pin to programming and verification 7 Added 80C51BH signature byte Package P D N S iJA 45 75 45 36 46 98 C C C C C C W W W W W W iJC 16 23 15 13 16 24 C C C C C C W W W W W W Device 87C51 BH 87C51 BH All All The following differences exist between the ‘‘-002’’ and the ‘‘-001’’ version of the 87C51 80C51BH 80C31BH datasheet 1 Removed b L IOL e g 10 mA from Float Waveforms figure 2 Removed QP QD and QN (commercial with extended burn-in) from Table 3 Prefix Identification Thermal Impedance All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operating conditions and applications See the Intel Packaging Handbook (Order No 240800) for a description of Intel’s thermal impedance test methodology DATA SHEET REVISION HISTORY Data sheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices The following differences exist between this datasheet (272335-003) and the previous version (272335-002) 1 Removed b 20 and b 3 spec replaced with b 24 spec 2 Added b 24 spec This data sheet (272335-001) replaces the following 80C51BH 80C31BH Express 270218-003 80C51BHP 270603-004 87C51 80C51BH 80C31BH 270147-008 87C51 Express 270430-002 87C51-20 -3 272082-002 21