87L58

8XL52 54 58 LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS Commercial Express 87L52 80L52 87L54 80L54 87L58 80L58 Y Y Y High Performance CHMOS OTP ROM Low Voltage Operation 20 MHz Commercial 16 MHz Express Operation Three 16-Bit Timer Counters Up Down Timer Counter Three Level Program Lock System 8K 16K 32K On-Chip Program Memory 256 Bytes of On-Chip Data RAM Improved Quick Pulse Programming Algorithm Boolean Processor 32 Programmable I O Lines Y Y Y 6 Interrupt Sources Four Level Interrupt Priority Programmable Serial Channel with Framing Error Detection Automatic Address Recognition 64K External Program Memory Space 64K External Data Memory Space MCS 51 Microcontroller Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode Extended Temperature Range ( b 40 C to a 85 C) Y Y Y Y Y Y Y Y Y Y Y Y Y Y MEMORY ORGANIZATION OTP ROM Version 87L52 87L54 87L58 ROM Version 80L52 80L54 80L58 ROM OTP ROM Bytes 8K 16K 32K RAM Bytes 256 256 256 These devices can address up to 64 Kbytes of external program data memory The Intel 8XL52 8XL54 8XL58 is a single-chip control oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology Being a member of the MCS 51 microcontroller family the 8XL52 8XL54 8XL58 uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with the existing MCS 51 microcontroller products The 8XL5X is a 3V version of current 8XC5X and will operate from 2 7V to 3 6V at a frequency range of 3 5 MHz to 16 MHz (Express) 20 MHz (Commercial) For the remainder of this document the 8XL52 8XL54 8XL58 will be referred to as the 8XL5X unless information applies to a specific device Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 November 1994 Order Number 272468-002 8XL52 54 58 NOTE Standard -1 -20 Standard 80L52 87L52 80L54 87L54 80L58 87L58 X X X X X X -1 X X X X X X -20 X X X X X X 3 5 MHz to 12 MHz 2 7V to 3 6V 3 5 MHz to 16 MHz 2 7V to 3 6V 3 5 MHz to 20 MHz 2 7V to 3 6V Only available for commercial standard temperature range not available at express temperature range 272468 – 1 Figure 1 8XL5X Block Diagram 2 8XL52 54 58 PROCESS INFORMATION The 8XL52 8XL54 8XL58 is manufactured on P629 5 a CHMOS III-E process Additional process and reliability information is available in Intel’s Components Quality and Reliability Handbook Order Number 210997 PACKAGES Part 8XL5X Prefix N S Package Type 44-Pin PLCC (OTP) 44-Pin QFP (OTP) 272468 – 2 PLCC 272468 – 3 QFP Figure 2 Pin Connections 3 8XL52 54 58 them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR) In this application it uses strong internal pullups when emitting 1’s During accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Some Port 2 pins receive the high-order address bits during OTP ROM programming and program verification Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive several inputs Port 3 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (IIL on the data sheet) because of the pullups Port 3 also serves the functions of various special features of the MCS-51 Family as listed below Port Pin P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) PIN DESCRIPTIONS VCC Supply voltage VSS Circuit ground Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several inputs Port 0 pins that have 1’s written to them float and in that state can be used as high-impedance inputs Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory In this application it uses strong internal pullups when emitting 1’s and can source and sink several inputs Port 0 also receives the code bytes during OTP ROM programming and outputs the code bytes during program verification External pullup resistors are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive several inputs Port 1 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups In addition Port 1 serves the functions of the following special features of the 8XL5X Port Pin P1 0 Alternate Function T2 (External Count Input to Timer Counter 2) Clock Out T2EX (Timer Counter 2 Capture Reload Trigger and Direction Control) P1 1 Port 1 receives the low-order address bytes during OTP ROM programming and verifying Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups The Port 2 output buffers can drive several inputs Port 2 pins that have 1’s written to RST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device The port pins will be driven to their reset condition when a minimum VIH2 voltage is applied whether the oscillator is running or not An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC 4 8XL52 54 58 ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory This pin (ALE PROG) is also the program pulse input during OTP ROM programming for the 87L5X In normal operation ALE is emitted at a constant rate of the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With this bit set the pin is weakly pulled high However the ALE disable feature will be suspended during a MOVX or MOVC instruction idle mode power down mode and ICE mode The ALE disable feature will be terminated by reset When the ALE disable feature is suspended or terminated the ALE pin will no longer be pulled up weakly Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode Throughout the remainder of this data sheet ALE will refer to the signal coming out of the ALE PROG pin and the pin will be referred to as the ALE PROG pin PSEN Program Store Enable is the read strobe to external Program Memory When the 8XL5X is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data Memory EA VPP External Access enable EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory locations 0000H to 0FFFH Note however that if either of the Program Lock bits are programmed EA will be internally latched on reset EA must be strapped to VCC for internal program executions This pin also receives the programming supply voltage (VPP) during OTP ROM programming XTAL1 Input to the inverting oscillator amplifier XTAL2 Output from the inverting oscillator amplifier 272468 – 4 C1 C2 e 30 pF g 10 pF for Crystals For Ceramic Resonators contact resonator manufacturer may be used More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155 ‘‘Oscillators for Microcontrollers ’’ To drive the device from an external clock source XTAL1 should be driven while XTAL2 floats as shown in Figure 4 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data sheet must be observed An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF Figure 3 Oscillator Connections 272468 – 5 Figure 4 External Clock Drive Configuration IDLE MODE The user’s software can invoke the Idle Mode When the microcontroller is in this mode power consumption is reduced The Special Function Registers and the onboard RAM retain their values during Idle but the processor stops executing instructions Idle Mode will be exited if the chip is reset or if an enabled interrupt occurs The PCA timer counter can optionally be left running or paused during Idle Mode 5 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of a inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 3 Either a quartz crystal or ceramic resonator 8XL52 54 58 POWER DOWN MODE To save even more power a Power Down mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated On the 8XL5X either hardware reset or external interrupt can cause an exit from Power Down Reset redefines all the SFRs but does not change the onchip RAM An external interrupt allows both the SFRs and the on-chip RAM to retain their values To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms) With an external interrupt INT0 or INT1 must be enabled and configured as level-sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down  All VCC and VSS pins must be connected Please refer to Figure 2 Pin Connections for the specific pins  When the idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory ONCE MODE The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates testing and debugging of systems using the 8XL5X without the 8XL5X having to be removed from the circuit The ONCE Mode is invoked by 1) Pull ALE low while the device is in reset and PSEN is high 2) Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins float and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the 8XL5X is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied DESIGN CONSIDERATION  The 8XL5X will operate from 2 7V to 3 6V with a frequency range of 3 5 MHz to 16 MHz (Express) 20 MHz (Commercial) Operating beyond these specifications could cause improper device functionality Table 1 Status of the External Pins during Idle and Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data NOTE For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors 270646 and Application Note AP-252 (Embedded Applications Handbook) 270648 ‘‘Designing Handbook Volume I with the 80C51BH ’’ 6 8XL52 54 58 For the extended temperature range option this data sheet specifies the parameters which deviate from their commercial temperature range limits Table 2 Prefix Identification Prefix N The EXPRESS program includes the commercial standard temperature range with burn-in and an extended temperature range with or without burn-in With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 C to 70 C With the extended temperature range option operational characteristics are guaranteed over the range of b 40 C to a 85 C Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number The prefixes are listed in Table 2 S TN TS Package Type PLCC QFP PLCC QFP Temperature Range Commercial Commercial Extended Extended 8XL5X EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the MCS-51 family of microcontrollers These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards NOTE Contact your distributor or local sales office to match the EXPRESS prefix with the proper device EXAMPLES N87L51FC indicates 87L51FC in a PLCC package and specified for commercial temperature range without burnin TN87L51FC indicates 87L51FC in a PLCC package and specified for extended temperature range with burn-in 7 8XL52 54 58 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias b 40 C to a 85 C Storage Temperature Voltage on EA VPP Pin to VSS Voltage on Any Other Pin to VSS IOL per I O Pin b 65 C to a 150 C 0V to a 13 0V b 0 5V to a 6 5V NOTICE This data sheet contains information on products in the sampling and initial production phases of development It is valid for the devices indicated in the revision history The specifications are subject to change without notice 15 mA Power Dissipation 1 5W (based on PACKAGE heat transfer limitations not device power consumption) WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability OPERATING CONDITIONS Symbol TA Description Ambient Temperature Under Bias Commercial Express Supply Voltage Min 0 b 40 Max a 70 a 85 Units C C V VCC 27 36 DC CHARACTERISTICS Symbol VIL VIL1 VIH VIH1 VIH2 VOL VOL1 VOH VOH1 IIL ILI (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated Parameter Input Low Voltage (except XTAL1 RST) Input Low Voltage (XTAL1 RST) Input High Voltage (Except XTAL1 RST EA) Input High Voltage (EA) Input High Voltage (XTAL1 RST) Output Low Voltage (Note 4) (Ports 1 2 and 3) Output Low Voltage (Note 4) (Port 0 ALE PSEN) Output High Voltage (Ports 1 2 and 3 ALE PSEN Output High Voltage (Port 0 in External Bus Mode) Logical 0 Input Current (Ports 1 2 and 3) Input Leakage Current (Port 0) VCC b 0 7 24 b 50 g 10 Min b0 5 b0 5 Max 08 0 2 VCC b 0 1 VCC a 0 5 VCC a 0 5 VCC a 0 5 04 04 Units V V V V V V V V V mA mA Test Conditions 20 VCC b 1 0 0 7 VCC IOL e 1 6 mA (Note 1) IOL e 3 2 mA (Note 1) IOH e b 30 mA (Note 2) IOH e b 1 0 mA (Note 2) VIN e 0 4V 0 k VIN k VCC 8 8XL52 54 58 DC CHARACTERISTICS Symbol ITL (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated (Continued) Parameter Logical 1 to 0 Transition Current (Ports 1 2 and 3) RST Pulldown Resistor Power Supply Current Active Mode at 16 MHz Idle Mode at 16 MHz Power-Down Mode 40 Min Max b 350 Units mA Test Conditions VIN e 1 4V RRST ICC 225 25 8 30 KX (Note 3) mA mA mA NOTES 1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the VOLs of ALE and Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0 In applications where capacitance loading exceeds 100 pF the noise pulses on these signals may exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic 2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0 9 VCC specification when the address lines are stabilizing 3 See Figures 6–9 for test conditions Minimum VCC for power down is 2V 4 Under steady state (non-transient) conditions IOL must be externally limited as follows 10 mA Maximum IOL per port pin Maximum IOL per 8-bit port Port 0 26 mA Ports 1 2 and 3 15 mA 71 mA Maximum total IOL for all output pins If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions Running the device with EA at a higher voltage than VCC sinks additional currrent 272468 – 6 ICC Max at other frequencies (3 5 MHz to 20 MHz) is given by Active Mode ICC MAX e 1 1 c FREQ a 7 6 Idle Mode ICC MAX e 0 4 c FREQ a 1 8 Where FREQ is in MHz ICCMAX is given in mA Figure 5 ICC vs Frequency 9 8XL52 54 58 272468 – 7 All other pins disconnected TCLCH e TCHCL e 5 ns All other pins disconnected TCLCH e TCHCL e 5 ns 272468 – 8 Figure 6 ICC Test Condition Active Mode Figure 7 ICC Test Condition Idle Mode 272468 – 9 All other pins disconnected Figure 8 ICC Test Condition Power Down Mode VCC e 2 7V to 3 6V 272468 – 10 Figure 9 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns 10 8XL52 54 58 L Logic level LOW or ALE P PSEN Q Output Data R RD signal T Time V Valid W WR signal X No longer a valid logic level Z Float For example TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters The first character is always a ‘T’ (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input Data H Logic level HIGH I Instruction (program memory contents) AC CHARACTERISTICS (Over Operating Conditions Load Capacitance for Port 0 ALE PROG and PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 8XL5X refers to 8XL5X and 8XL5X-1 Symbol 1 TCLCL Parameter Oscillator Frequency 8XL5X 8XL5X-1 8XL5X-20 ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In 8XL5X 8XL5X-20 ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In 8XL5X 8XL5X-20 Input Instruction Hold After PSEN 0 53 205 127 43 53 60 10 20 12 MHz Oscillator Min Max 20 MHz Oscillator Min Max Min 35 35 35 2 TCLCL b 40 TCLCL b 40 TCLCL b 30 Variable Oscillator Max 12 16 20 MHz MHz MHz ns ns ns Units TLHLL TAVLL TLLAX TLLIV 234 125 20 105 TCLCL b 30 3 TCLCL b 45 4 TCLCL b 100 4 TCLCL b 75 ns ns ns ns TLLPL TPLPH TPLIV 145 60 0 0 3 TCLCL b 105 3 TCLCL b 90 ns ns ns TPXIX 11 8XL52 54 58 EXTERNAL MEMORY CHARACTERISTICS (Continued) All parameter values apply to all devices unless otherwise indicated Symbol Parameter 12 MHz Oscillator Min TPXIZ Input Instruction Float After PSEN 8XL5X 8XL5X-20 Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In 8XL5X 8XL5X-20 Data Hold After RD Data Float After RD ALE Low to Valid Data In 8XL5X 8XL5X-20 Address to Valid Data In 8XL5X 8XL5X-20 ALE Low to RD or WR Low Address Valid to WR Low 8XL5X 8XL5X-20 Data Valid before WR 8XL5X 8XL5X-20 Data Hold after WR 8XL5X 8XL5X-20 Data Valid to WR High 8XL5X 8XL5X-20 RD Low to Address Float RD or WR High to ALE High 43 200 0 107 517 310 585 360 300 100 200 3 TCLCL b 50 400 400 252 155 0 40 0 2 TCLCL b 60 8 TCLCL b 150 8 TCLCL b 90 9 TCLCL b 165 9 TCLCL b 90 3 TCLCL a 50 Max 20 MHz Oscillator Min Max Min Variable Oscillator Max Units 59 30 312 10 200 200 145 10 6 TCLCL b 100 6 TCLCL b 100 TCLCL b 25 TCLCL b 20 5 TCLCL b 105 10 ns ns ns ns ns ns TAVIV TPLAZ TRLRH TWLWH TRLDV 5 TCLCL b 165 5 TCLCL b 95 ns ns ns ns ns ns ns ns ns TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL 203 110 33 15 33 10 433 280 0 123 10 0 90 4 TCLCL b 130 4 TCLCL b 90 TCLCL b 50 TCLCL b 35 TCLCL b 50 TCLCL b 40 7 TCLCL b 150 7 TCLCL b 70 0 TCLCL b 40 TCLCL a 40 ns ns ns ns ns ns ns ns ns ns TQVWX TWHQX TQVWH TRLAZ TWHLH 12 8XL52 54 58 EXTERNAL PROGRAM MEMORY READ CYCLE 272468 – 11 EXTERNAL DATA MEMORY READ CYCLE 272468 – 12 EXTERNAL DATA MEMORY WRITE CYCLE 272468 – 13 13 8XL52 54 58 SERIAL PORT TIMING - SHIFT REGISTER MODE Test Conditions Symbol Over Operating Conditions Load Capacitance e 80 pF 12 MHz Oscillator Min Max 20 MHz Oscillator Min 0 600 367 Max Min 12 TCLCL 10 TCLCL b 133 Variable Oscillator Max ms ns Units Parameter TXLXL TQVXH TXHQX Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge 8XL5X 8XL5X-20 Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 1 700 50 50 0 700 0 367 2 TCLCL b 117 2 TCLCL b 50 0 10 TCLCL b 133 ns ns ns ns TXHDX TXHDV SHIFT REGISTER MODE TIMING WAVEFORMS 272468 – 14 14 8XL52 54 58 EXTERNAL CLOCK DRIVE Symbol 1 TCLCL Parameter Oscillator Frequency 8XL5X 8XL5X-1 8XL5X-20 High Time Low Time Rise Time Fall Time Min 35 35 35 20 20 20 20 Max 12 16 20 Units MHz TCHCX TCLCX TCLCH TCHCL ns ns ns ns EXTERNAL CLOCK DRIVE WAVEFORM 272468 – 15 AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 272468 – 16 AC Inputs during testing are driven at VCC b 0 5V for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0’’ Timing measurements are made at VIH min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’ 272468 – 17 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH VOL level occurs IOL IOH e g 20 mA (-L IOL IOH e g 10 mA) 15 8XL52 54 58 Normally EA VPP is held at logic high until just before ALE PROG is to be pulsed Then EA VPP is raised to VPP ALE PROG is pulsed low and then EA VPP is returned to a valid high voltage The voltage on the EA VPP pin must be at the valid EA VPP high level before a verify is attempted Waveforms and detailed timing specifications are shown in later sections of this data sheet NOTE PROGRAMMING THE OTP ROM To be programmed the part must be running with a 4 to 6 MHz oscillator (The reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appropriate internal OTP ROM locations ) The address of an OTP ROM location to be programmed is applied to Port 1 and pins P2 0 - P2 4 of Port 2 while the code byte to be programmed into that location is applied to Port 0 The other Port 2 and 3 pins RST PSEN and EA VPP should be held at the ‘‘Program’’ levels indicated in Table 3 ALE PROG is pulsed low to program the code byte into the addressed OTP ROM location The setup is shown in Figure 10  EA VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time Even a narrow glitch above that voltage level can cause permanent damage to the device The VPP source should be well regulated and free of glitches Table 3 OTP ROM Programming Modes (H e 2 7V to 3 6V H1 e 5V g 10%) Mode Program Code Data Verify Code Data Program Encryption Array Address 0–3FH Program Lock Bits Bit 1 Bit 2 Bit 3 Read Signature Byte RST H1 H H1 H1 H1 H1 H PSEN L L L L L L L H H ALE PROG EA VPP 12 75V H 12 75V 12 75V 12 75V 12 75V H P2 6 L L L H1 H1 H1 L P2 7 H1 L H1 H1 H1 L L P3 3 H1 L H1 H1 H1 H1 L P3 6 H1 H L H1 L H1 L P3 7 H1 H H1 H1 L L L VCC H1 H H1 H1 H1 H1 H 272468 – 18 See Table 2 for proper input on these pins Figure 10 Programming the OTP ROM 16 8XL52 54 58 Repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached PROGRAMMING ALGORITHM Refer to Table 3 and Figures 10 and 11 for address data and control signals set up To program the 87L5X the following sequence must be exercised 1 Input the valid address on the address lines 2 Input the appropriate data byte on the data lines 3 Activate the correct combination of control signals 4 Raise EA VPP from VCC to 12 75V g 0 25V 5 Pulse ALE PROG 5 times for the OTP ROM array and 25 times for the encryption table and the lock bits PROGRAM VERIFY Program verify may be done after each byte or block of bytes is programmed In either case a complete verify of the programmed array will ensure reliable programming of the 8XL5X The lock bits cannot be directly verified Verification of the lock bits is done by observing that their features are enabled 272468 – 19 Figure 11 Programming Signals Waveforms ROM and OTP ROM Lock System The 87L5X program lock system when programmed protects the onboard program against software piracy The 80L5X has a one-level program lock system and a 64-byte encryption table See line 2 of Table 4 If program protection is desired the user submits the encryption table with their code and both the lockbit and encryption array are programmed by the factory The encryption array is not available without the lock bit For the lock bit to be programmed the user must submit an encryption table The 87L5X has a 3-level program lock system and a 64-byte encryption array Since this is an OTP ROM device all locations are user-programmable See Table 4 Encryption Array Within the OTP ROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1’s) Every time that a byte is addressed during a verify 6 address lines are used to select a byte of the Encryption Array This byte is then exclusive-NOR’ed (XNOR) with the code byte creating an Encryption Verify byte The algorithm with the array in the unprogrammed state (all 1’s) will return the code in its original unmodified form For programming the Encryption Array refer to Table 3 (Programming the OTP ROM) When using the encryption array one important factor needs to be considered If a code byte has the value 0FFH verifying the byte will produce the encryption byte value lf a large block ( l 64 bytes) of code is left unprogrammed a verification routine will display the contents of the encryption array For this reason all unused code bytes should be programmed with some value other than 0FFH and not all of them the same value This will ensure maximum program protection 17 8XL52 54 58 Table 4 Program Lock Bits and the Features Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U No Program Lock features enabled (Code verify will still be encrypted by the Encryption Array if programmed ) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on Reset and further programming of the OTP ROM is disabled Same as 2 also verify is disabled Same as 3 also external execution is disabled ProtectIon Type 3 4 P P P P U P Any other combination of the lock bits is not defined Program Lock Bits The 8XL5X has 3 programmable lock bits that when programmed according to Table 4 will provide different levels of protection for the on-chip code and data Location 30H 31H 60H Device All All 80L52 87L52 80L54 87L54 80L58 87L58 Contents 89H 58H 30 B0 31 B1 32 B2 Reading the Signature Bytes The 87L5X 80L5X has 3 signature bytes in locations 30H 31H and 60H To read these bytes follow the procedure for OTP ROM verify but activate the control lines provided in Table 3 for Read Signature Byte 18 8XL52 54 58 OTP ROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (TA e 21 C to 27 C VCC e 2 7V to 3 6V VSS e 0V) Symbol VPP IPP 1 TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low Data Hold after PROG P2 7 (ENABLE) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float after ENABLE PROG High to PROG Low 0 10 4 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 10 10 90 100 48TCLCL 48TCLCL 48TCLCL ms ms ms ms Min 12 5 Max 13 0 75 6 Units V mA MHz OTP ROM PROGRAMMING AND VERIFICATION WAVEFORMS 272468 – 20 NOTE 5 pulses for the OTP ROM array 25 pulses for the encryption table and lock bits 19 8XL52 54 58 Thermal Impedance All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operating conditions and applications See the Intel Packaging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology Package N S iJA 46 87 96 90 C C C C W W W W iJC 16 18 24 22 C C C C W W W W Device All 52 54 58 DATA SHEET REVISION HISTORY This is the first issue of this data sheet 20