8XC51RB

8XC51RA RB RC CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial Express 87C51RA 83C51RA 80C51RA 87C51RB 83C51RB 87C51RC 83C51RC See Table 1 for Proliferation Options Y High Performance CHMOS EPROM ROM CPU 24 MHz Operation 512 Bytes of On-Chip Data RAM Dedicated Hardware Watchdog Timer (One-Time Enabled with Reset-Out) Three 16-Bit Timer Counters Programmable Clock Out Up Down Timer Counter Three Level Program Lock System 8K 16K 32K On-Chip Program Memory Improved Quick Pulse Programming Algorithm Boolean Processor 32 Programmable I O Lines Y Y 6 Interrupt Sources Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS 51 Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode Four-Level Interrupt Priority Extended Temperature Range ( b 40 C to a 85 C) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y MEMORY ORGANIZATION ROMless Device 80C51RA 80C51RA 80C51RA ROM Device 83C51RA 83C51RB 83C51RC EPROM Version 87C51RA 87C51RB 87C51RC ROM EPROM Bytes 8K 16K 32K RAM Bytes 512 512 512 These devices can address up to 64 Kbytes of external program data memory The Intel 8XC51RA 8XC51RB 8XC51RC is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology Being a member of the MCS 51 family of controllers the 8XC51RA 8XC51RB 8XC51RC uses the same powerful instruction set has the same architecture and is pinfor-pin compatible with the existing MCS 51 family of products The 8XC51RA 8XC51RB 8XC51RC is an enhanced version of the 8XC52 8XC54 8XC58 The added features make it an even more powerful microcontroller for applications that require 512 bytes of on-chip data RAM and dedicated hardware WatchDog Timer with reset-out features Throughout this document 8XC51RX will refer to the 8XC51RA 8XC51RB and 8XC51RC unless information applies to a specific device For a detailed description of 8XC51RA RB RC refer to the 8XC51RA RB RC Hardware Description order number 272668 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 December 1995 Order Number 272659-002 8XC51RA RB RC Table 1 Proliferations Options 80C51RA 83C51RA 87C51RA 83C51RB 87C51RB 83C51RC 87C51RC Standard 1 X X X X X X X -1 X X X X X X X -20 X X X X X X X -24 X X X X X X X NOTES 1 35 -1 3 5 -20 3 5 -24 3 5 MHz MHz MHz MHz to to to to 12 16 20 24 MHz MHz MHz MHz 5V 5V 5V 5V g 20% g 20% g 20% g 10% 272659 – 4 Figure 1 8XC51RX Block Diagram 2 8XC51RA RB RC PROCESS INFORMATION This device is manufactured on P629 5 a CHMOS III-E process Additional process and reliability information is available in Intel’s Components Quality and Reliability Handbook Order No 210997 PACKAGES Part 8XC51RX 8XC51RX 8XC51RX Prefix P N S Package Type 40-Pin Plastic DIP (OTP) 44-Pin PLCC (OTP) 44-Pin QFP (OTP) 272659 – 2 PLCC 272659 – 1 DIP 272659 – 3 Do not connect reserved pins QFP Figure 2 Pin Connections 3 8XC51RA RB RC LS TTL inputs Port 2 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR) In this application it uses strong internal pullups when emitting 1’s During accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Some Port 2 pins receive the high-order address bits during EPROM programming and program verification Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (IIL on the data sheet) because of the pullups Port 3 also serves the functions of various special features of the 8051 Family as listed below Port Pin P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) PIN DESCRIPTIONS VCC Supply voltage VSS Circuit ground VSS1 Secondary ground (not on DIP) Provided to reduce ground bounce and improve power supply by-passing NOTE This pin is not a substitute for the VSS pin (pin 22) (Connection not necessary for proper operation ) Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1’s written to them float and in that state can be used as high-impedance inputs Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory In this application it uses strong internal pullups when emitting 1’s and can source and sink several LS TTL inputs Port 0 also receives the code bytes during EPROM programming and outputs the code bytes during program verification External pullup resistors are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups In addition Port 1 serves the functions of the following special features of the 8XC51RX Port Pin P1 0 P1 1 Alternate Function T2 (External Count Input to Timer Counter 2) Clock-Out T2EX (Timer Counter 2 Capture Reload Trigger and Direction Control) Port 1 receives the low-order address bytes during EPROM programming and verifying Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups The Port 2 output buffers can drive RST Reset I O A high on this pin for two machine cycles while the oscillator is running resets the device The port pins will be driven to their reset condition when a minimum VIHI voltage is applied whether the oscillator is running or not An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC After a WatchDog Timer overflow this RST pin will drive an output high pulse at a minimum VOH2 for 96 x TOSC duration while the internal reset signal is active ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to ex- 4 8XC51RA RB RC ternal memory This pin (ALE PROG) is also the program pulse input during EPROM programming for the 87C51RX In normal operation ALE is emitted at a constant rate of the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With this bit set the pin is weakly pulled high However the ALE disable feature will be suspended during a MOVX or MOVC instruction idle mode power down mode and ICE mode The ALE disable feature will be terminated by reset When the ALE disable feature is suspended or terminated the ALE pin will no longer be pulled up weakly Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode Throughout the remainder of this data sheet ALE will refer to the signal coming out of the ALE PROG pin and the pin will be referred to as the ALE PROG pin PSEN Program Store Enable is the read strobe to external Program Memory When the 8XC51RX is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data Memory EA VPP External Access enable EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory locations 0000H to 0FFFFH Note however that if any of the Lock bits are programmed EA will be internally latched on reset EA should be strapped to VCC for internal program executions This pin also receives the programming supply voltage (VPP) during EPROM programming XTAL1 Input to the inverting oscillator amplifier XTAL2 Output from the inverting oscillator amplifier 272659 – 6 ured for use as an on-chip oscillator as shown in Figure 3 Either a quartz crystal or ceramic resonator may be used More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155 ‘‘Oscillators for Microcontrollers’’ Order No 230659 272659 – 5 C1 C2 e 30 pF g 10 pF for Crystals For Ceramic Resonators contact resonator manufacturer Figure 3 Oscillator Connections To drive the device from an external clock source XTAL1 should be driven while XTAL2 floats as shown in Figure 4 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data sheet must be observed An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF Figure 4 External Clock Drive Configuration IDLE MODE The user’s software can invoke the Idle Mode When the microcontroller is in this mode power consumption is reduced The Special Function Registers and the onboard RAM retain their values during Idle but the processor stops executing instructions Idle OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of a inverting amplifier which can be config- 5 8XC51RA RB RC Table 2 Status of the External Pins during Idle and Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data Mode will be exited if the chip is reset or if an enabled interrupt occurs POWER DOWN MODE To save even more power a Power Down mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated On the 8XC51RX either a hardware reset or an external interrupt can cause an exit from Power Down Reset redefines all the SFRs but does not change the on-chip RAM An external interrupt allows both the SFRs and on-chip RAM to retain their values To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms) With an external interrupt INT0 and INT1 must be enabled and configured as level-sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down ware upset WDT is disabled upon power-up To enable the WDT user must write 1EH and E1H in sequence to WDTRST Special Function Register Once the WDT is enabled the 14-bit counter will increment every machine cycle While the oscillator is running the WDT will be incrementing and cannot be disabled The counter is reset by writing 1EH and E1H in sequence to the WDTRST If the counter is not reset before it reaches 3FFFH (16383D) the chip will be forced into reset sequence and the WDT will be disabled as upon power-up During this reset the chip will drive an output Reset-High pulse for the duration of 96 x TOSC at the RST pin The duration of the Reset-High pulse works out to 6 00 ms 16 MHz While in the Idle mode the WDT continues to count If the user does not wish to exit the Idle mode with a reset then the processor must periodically ‘‘woken up’’ to service the WDT In Power Down mode the WDT stops counting and holds its current value DESIGN CONSIDERATION  The window on the D87C51RX must be covered by an opaque label Otherwise the DC and AC characteristics may not be met and the device may be functionally impaired  When the idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory DEDICATED HARDWARE WATCHDOG TIMER (One-Time Enabled with Reset-Out) The 8XC51RX contains a dedicated WatchDog Timer (WDT) to allow recovery from software or hard- NOTE For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded Applications Handbook Order No 270648) ‘‘Designing with the 80C51BH ’’ 6 8XC51RA RB RC whose operating requirements exceed commercial standards The EXPRESS program includes the commercial standard temperature range with burn-in and an extended temperature range with or without burn-in With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 C to a 70 C With the extended temperature range option operational characteristics are guaranteed over the range of b 40 C to a 85 C The optional burn-in is dynamic for a minimum time of 168 hours at 125 C with VCC e 6 9V g 0 25V following guidelines in MIL-STD-883 Method 1015 Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number The prefixes are listed in Table 3 For the extended temperature range option this data sheet specifies the parameters which deviate from their commercial temperature range limits ONCE MODE The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates testing and debugging of systems using the 8XC51RX without the 8XC51RX having to be removed from the circuit The ONCE Mode is invoked by 1) Pull ALE low while the device is in reset and PSEN is high 2) Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins float and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the 8XC51RX is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied 8XC51RX EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the MCS 51 family of microcontrollers These EXPRESS products are designed to meet the needs of those applications Table 3 Prefix Identification Prefix P N S TP TN TS LP LN LS Package Type Plastic PLCC QFP Plastic PLCC QFP Plastic PLCC QFP Temperature Range Commercial Commercial Commercial Extended Extended Extended Extended Extended Extended Burn-In No No No No No No Yes Yes Yes NOTE Contact distributor or local sales office to match EXPRESS prefix with proper device EXAMPLES P80C51RA indicates 80C51RA in a plastic package and specified for commercial temperature range without burn-in TS87C51RC indicates 87C51RC in a QFP package and specified for extended temperature range without burn-in 7 8XC51RA RB RC ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias b 40 C to a 85 C Storage Temperature Voltage on EA VPP Pin to VSS Voltage on Any Other Pin to VSS IOL Per I O Pin b 65 C to a 150 C 0V to a 13 0V b 0 5V to a 6 5V NOTICE This data sheet contains information on products in the sampling and initial production phases of development The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design 15 mA Power Dissipation 1 5W (based on PACKAGE heat transfer limitations not device power consumption) WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability OPERATING CONDITIONS Symbol TA Description Ambient Temperature Under Bias Commercial Express Supply Voltage All Others 8XC51RX-24 0scillator Frequency 8XC51RX 8XC51RX-1 8XC51RX-20 8XC51RX-24 Min 0 b 40 Max a 70 a 85 Units C C V V MHz MHz MHz MHz VCC 40 45 35 35 35 35 60 55 12 16 20 24 fOSC DC CHARACTERISTICS Symbol VIL VIL1 VIH VIH1 VOL Parameter Input Low Voltage Input Low Voltage EA Input High Voltage (Except XTAL1 RST) Input High Voltage (XTAL1 RST) (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated Min b0 5 Typ (Note 4) Max 0 2 VCC b 0 1 0 2 VCC b 0 3 VCC a 0 5 VCC a 0 5 03 0 45 10 03 0 45 10 Unit V V V V V V V V V V V V V Test Conditions 0 0 2 VCC a 0 9 0 7 VCC Output Low Voltage (Note 5) (Ports 1 2 and 3) IOL e 100 mA (Note 1) IOL e 1 6 mA (Note 1) IOL e 3 5 mA (Note 1) IOL e 200 mA (Note 1) IOL e 3 2 mA (Note 1) IOL e 7 0 mA (Note 1) IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA VOL1 Output Low Voltage (Note 5) (Port 0 ALE PSEN) VOH Output High Voltage (Ports 1 2 and 3 ALE PSEN) VCC b 0 3 VCC b 0 7 VCC b 1 5 8 8XC51RA RB RC DC CHARACTERISTICS Symbol VOH1 (Over Operating Conditions) (Continued) All parameter values apply to all devices unless otherwise indicated Parameter Output High Voltage (Port 0 in External Bus Mode) Min VCC b 0 3 VCC b 0 7 VCC b 1 5 VOH2 Output High Voltage (RST) 0 5 VCC 0 75 VCC 0 9 VCC IIL ILI ITL Logical 0 Input Current (Ports 1 2 and 3) Input leakage Current (Port 0) Logical 1 to 0 Transition Current (Ports 1 2 and 3) Commercial Express RST Pulldown Resistor Pin Capacitance Power Supply Current Active Mode at 12 MHz (Figure 5) at 16 MHz at 20 MHz at 24 MHz Idle Mode at 12 MHz (Figure 5) at 16 MHz at 20 MHz at 24 MHz Power Down Mode 40 10 b 50 g 10 Typ (Note 4) Max Unit V V V V V V mA mA Test Conditions IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 0 mA IOH e b 800 mA IOH e b 300 mA IOH e b 80 mA VIN e 0 45V VIN e VIL or VIH b 675 b 775 mA mA KX pF VIN e 2V RRST CIO ICC 225 1 MHz 25 C (Note 3) 15 30 38 47 56 75 95 11 5 13 5 75 mA mA mA mA mA mA mA mA mA 5 5 NOTES 1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the VOLs of ALE and Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt Triggers or CMOS-level input logic 2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0 9 VCC specification when the address lines are stabilizing 3 See Figures 6–9 for test conditions Minimum VCC for Power Down is 2V 4 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature and 5V 5 Under steady state (non-transient) conditions IOL must be externally limited as follows 10mA Maximum IOL per port pin Maximum IOL per 8-bit port Port 0 26 mA Ports 1 2 and 3 15 mA 71 mA Maximum total IOL for all output pins If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 9 8XC51RA RB RC 272659 – 7 ICC Max at other frequencies is given by Active Mode ICC Max e 2 2 c Freq a 3 1 Idle Mode ICC Max e 0 5 c Freq a 1 5 Where Freq is in MHz ICC Max is given in mA 272659 – 8 All other pins disconnected TCLCH e TCHCL e 5 ns Figure 5 ICC vs Frequency Figure 6 ICC Test Condition Active Mode 272659 – 9 All other pins disconnected TCLCH e TCHCL e 5 ns All other pins disconnected 272659 – 10 Figure 7 ICC Test Condition Idle Mode Figure 8 ICC Test Condition Power Down Mode VCC e 2 0V to 6 0V 272659 – 11 Figure 9 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns 10 8XC51RA RB RC L Logic level LOW or ALE P PSEN Q Output Data R RD signal T Time V Valid W WR signal X No longer a valid logic level Z Float For example TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters The first character is always a ‘T’ (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input Data H Logic level HIGH I Instruction (program memory contents) AC CHARACTERISTICS (Over Operating Conditions Load Capacitance for Port 0 ALE PROG and PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 8XC51RX refers to 8XC51RX and 8XC51RX-1 8XC51RX-24 refers to 8XC51RX-20 and 8XC51RX-24 Symbol 1 TCLCL Description Oscillator Frequency 8XC51RX 8XC51RX-1 8XC51RX-20 8XC51RX-24 ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In 8XC51RX 8XC51RX-24 ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In 8XC51RX 8XC51RX-24 Input Instruction Hold After PSEN 0 53 205 127 43 53 60 10 20 43 12 12 12 MHz Oscillator Min Max 20 MHz Oscillator Min Max 24 MHz Oscillator Min Max Min 35 35 35 35 2 TCLCL b 40 TCLCL b 40 TCLCL b 30 Variable Oscillator Max 12 16 20 24 MHz MHz MHz MHz ns ns ns Units TLHLL TAVLL TLLAX TLLIV 234 125 20 105 12 80 91 TCLCL b 30 3 TCLCL b 45 4 TCLCL b 100 4 TCLCL b 75 ns ns ns ns TLLPL TPLPH TPLIV 145 60 0 0 35 0 3 TCLCL b 105 3 TCLCL b 90 ns ns ns TPXIX 11 8XC51RA RB RC EXTERNAL MEMORY CHARACTERISTICS (Continued) All parameter values apply to all devices unless otherwise indicated Symbol Description 12 MHz Oscillator Min TPXIZ Input Instruction Float After PSEN 8XC51RX 8XC51RX-24 Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In 8XC51RX 8XC51RX-24 Data Hold After RD Data Float After RD ALE Low to Valid Data In 8XC51RX 8XC51RX-24 Address to Valid Data In 8XC51RX 8XC51RX-24 ALE Low to RD or WR Low Address Valid to WR Low 8XC51RX 8XC51RX-24 Data Valid before WR 8XC51RX 8XC51RX-20 8XC51RX-24 Data Hold after WR 8XC51RX 8XC51RX-20 8XC51RX-24 Data Valid to WR High 8XC51RX 8XC51RX-24 RD Low to Address Float RD or WR High to ALE High 8XC51RX 8XC51RX-24 43 200 203 110 33 15 12 33 10 7 433 280 0 123 10 0 90 12 71 222 0 TCLCLb40 TCLCLb30 77 0 107 517 310 585 360 300 100 200 75 285 175 3 TCLCLb50 4 TCLCLb130 4 TCLCLb90 TCLCLb50 TCLCLb35 TCLCLb30 TCLCLb50 TCLCLb40 TCLCLb30 7 TCLCLb150 7 TCLCLb70 0 TCLCL a 40 TCLCL a 30 243 400 400 252 155 0 40 0 23 113 0 2 TCLCLb60 8 TCLCLb150 8 TCLCLb90 9 TCLCLb165 9 TCLCLb90 3 TCLCL a 50 Max 20 MHz Oscillator Min Max 24 MHz Oscillator Min Max Min Variable Oscillator Max Units 59 30 312 10 200 200 145 10 150 150 21 103 10 6 TCLCLb100 6 TCLCLb100 TCLCLb25 TCLCLb20 5 TCLCLb105 10 ns ns ns ns ns ns TAVIV TPLAZ TRLRH TWLWH TRLDV 5 TCLCLb165 5 TCLCLb95 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TWHQX TQVWH TRLAZ TWHLH 12 8XC51RA RB RC EXTERNAL PROGRAM MEMORY READ CYCLE 272659 – 12 EXTERNAL DATA MEMORY READ CYCLE 272659 – 13 EXTERNAL DATA MEMORY WRITE CYCLE 272659 – 14 13 8XC51RA RB RC SERIAL PORT TIMING - SHIFT REGISTER MODE Test Conditions Symbol Over Operating Conditions Load Capacitance e 80 pF 12 MHz Oscillator Min Max 20 MHz Oscillator Min 0 600 367 Max 24 MHz Oscillator Min 0 500 284 Max Min 12 TCLCL 10 TCLCL b 133 Variable Oscillator Max ms ns Units Parameter TXLXL TQVXH Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge 8XC51RX 8XC51RX-24 Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 1 700 TXHQX 50 50 0 0 34 0 2 TCLCL b 117 2 TCLCL b 50 0 ns ns ns TXHDX TXHDV 700 367 284 10 TCLCL b 133 ns SHIFT REGISTER MODE TIMING WAVEFORMS 272659 – 15 14 8XC51RA RB RC EXTERNAL CLOCK DRIVE Symbol 1 TCLCL Parameter Oscillator Frequency 8XC51RX 8XC51RX-1 8XC51RX-20 8XC51RX-24 High Time Low Time Rise Time 8XC51RX 8XC51RX-24 Fall Time20 8XC51RX 8XC51RX-24 Min 35 35 35 35 0 35 TOSC 0 35 TOSC Max 12 16 20 24 0 65 TOSC 0 65 TOSC 20 10 20 10 Units MHz TCHCX TCLCX TCLCH ns ns ns ns ns ns ns TCHCL EXTERNAL CLOCK DRIVE WAVEFORM 272659 – 16 AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 272659 – 17 AC Inputs during testing are driven at VCC b 0 5V for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0’’ Timing measurements are made at VIH min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’ 272659 – 18 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH VOL level occurs IOL IOH e g 20 mA 15 8XC51RA RB RC PROGRAMMING THE EPROM The part must be running with a 4 MHz to 6 MHz oscillator The address of an EPROM location to be programmed is applied to address lines while the code byte to be programmed in that location is applied to data lines Control and program signals must be held at the levels indicated in Table 4 Normally EA VPP is held at logic high until just before ALE PROG is to be pulsed The EA VPP is raised to VPP ALE PROG is pulsed low and then EA VPP is returned to a high (also refer to timing diagrams) NOTES DEFINITION OF TERMS ADDRESS LINES P1 0 – P1 7 P2 0 – P2 5 respectively for A0 – A13 DATA LINES P0 0 – P0 7 for D0 – D7 CONTROL SIGNALS RST PSEN P2 6 P2 7 P3 3 P3 6 P3 7 PROGRAM SIGNALS ALE PROG EA VPP  Exceeding the VPP maximum for any amount of time could damage the device permanently The VPP source must be well regulated and free of glitches Table 4 EPROM Programming Modes Mode Program Code Data Verify Code Data Program Encryption Array Address 0–3FH Program Lock Bits Bit 1 Bit 2 Bit 3 Read Signature Byte RST H H H H H H H PSEN L L L L L L L H H ALE PROG EA VPP 12 75V H 12 75V 12 75V 12 75V 12 75V H P2 6 L L L H H H L P2 7 H L H H H L L P3 3 H L H H H H L P3 6 H H L H L H L P3 7 H H H H L L L 16 8XC51RA RB RC 272659 – 19 See Table 4 for proper input on these pins Figure 10 Programming the EPROM PROGRAMMING ALGORITHM Refer to Table 4 and Figures 10 and 11 for address data and control signals set up To program the 87C51RX the following sequence must be exercised 1 Input the valid address on the address lines 2 Input the appropriate data byte on the data lines 3 Activate the correct combination of control signals 4 Raise EA VPP from VCC to 12 75V g 0 25V 5 Pulse ALE PROG 5 times for the EPROM array and 25 times for the encryption table and the lock bits Repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached PROGRAM VERIFY Program verify may be done after each byte or block of bytes is programmed In either case a complete verify of the programmed array will ensure reliable programming of the 87C51RX The lock bits cannot be directly verified Verification of the lock bits is done by observing that their features are enabled 272659 – 20 Figure 11 Programming Signal’s Waveforms 17 8XC51RA RB RC If any program lock bits were programmed erasing the EPROM will not erase the program lock bits and programming of the EPROM is disabled ROM and EPROM Lock System The program lock system when programmed protects the onboard program against software piracy The 83C51RX has a one-level program lock system and a 64-byte encryption table See line 2 of Table 5 If program protection is desired the user submits the encryption table with their code and both the lock-bit and encryption array are programmed by the factory The encryption array is not available without the lock bit For the lock bit to be programmed the user must submit an encryption table The 87C51RX has a 3-level program lock system and a 64-byte encryption array Since this is an EPROM device all locations are user-programmable See Table 5 Reading the Signature Bytes The 8XC51RX has 3 signature bytes in locations 30H 31H and 60H To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 4 for Read Signature Byte Location 30H 31H 60H Device All All 87C51RC 87C51RB Contents 89H 58H C2H C1H C0H 42H C2H 41H C1H 40H C0H Encryption Array Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1’s) Every time that a byte is addressed during a verify 6 address lines are used to select a byte of the Encryption Array This byte is then exclusive-NOR’ed (XNOR) with the code byte creating an Encryption Verify byte The algorithm with the array in the unprogrammed state (all 1’s) will return the code in its original unmodified form For programming the Encryption Array refer to Table 4 (Programming the EPROM) When using the encryption array one important factor needs to be considered If a code byte has the value 0FFH verifying the byte will produce the encryption byte value If a large block ( l 64 bytes) of code is left unprogrammed a verification routine will display the contents of the encryption array For this reason all unused code bytes should be programmed with some value other than 0FFH and not all of them the same value This will ensure maximum program protection 87C51RA 83C51RC 83C51RB 83C51RA Erasure Characteristics (Windowed Packages Only) Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4 000 Angstroms Since sunlight and fluorescent lighting have wavelengths in this range exposure to these light sources over an extended time (about 1 week in sunlight or 3 years in roomlevel fluorescent lighting) could cause inadvertent erasure If an application subjects the device to this type of exposure it is suggested that an opaque label be placed over the window The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec cm2 Exposing the EPROM to an ultraviolet lamp of 12 000 mW cm2 rating for 30 minutes at a distance of about 1 inch should be sufficient Erasure leaves all the EPROM Cells in a 1’s state Program Lock Bits The 87C51RX has 3 programmable lock bits that when programmed according to Table 5 will provide different levels of protection for the on-chip code and data 18 8XC51RA RB RC Table 5 Program Lock Bits and the Features Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U Protection Type No Program Lock features enabled (Code verify will still be encrypted by the Encryption Array if programmed ) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on Reset and further programming of the EPROM is disabled Same as 2 also verify is disabled Same as 3 also external execution is disabled 3 4 P P P P U P NOTE Any other combination of the lock bits is not defined EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (TA e 21 C to 27 C VCC e 5V g 20% VSS e 0V) Symbol VPP IPP 1 TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low Data Hold after PROG (Enable) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float after ENABLE PROG High to PROG Low 0 10 4 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 10 10 90 110 48TCLCL 48TCLCL 48TCLCL ms ms ms ms Min 12 5 Max 13 0 75 6 Units V mA MHz 19 8XC51RA RB RC EPROM PROGRAMMING AND VERIFICATION WAVEFORMS 272659 – 21 5 pulses for the EPROM array 25 pulses for the encryption table and lock bits Thermal Impedance All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operating conditions and applications See the Intel Packaging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology Package P N S iJA 45 46 87 96 90 C C C C C W W W W W iJC 16 16 18 24 22 C C C C C W W W W W Device All All 51RA 51RB 51RC DATA SHEET REVISION HISTORY Data sheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices The following differences exist between this datasheet (272659-002) and the previous version (272659-001) 1 ADVANCE INFORMATION datasheet replaces PRODUCT PREVIEW datasheet 2 ITL (Commercial) changed from b 650 mA to b 675 mA 3 ITL (Express) changed from b 750 mA to b 775 mA 4 8XC51RX-24 VCC changed from 5V g 20% to 5V g 10% 5 Remove all CERDIP package types (prefix D TD LD) INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080 INTEL CORPORATION (U K ) Ltd Swindon United Kingdom Tel (0793) 696 000 INTEL JAPAN k k Ibaraki-ken Tel 029747-8511