9100

Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050 Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040 Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030 Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9020 Dual-Core Intel® Itanium® Processor 1.4 GHz with 12 MB L3 Cache 9015 Intel® Itanium® Processor 1.6 GHz with 6 MB L3 Cache 9010 Dual-Core Intel® Itanium® Processor 1.66/1.6 GHz with 24 MB L3 Cache 9152 Dual-Core Intel® Itanium® Processor 1.66 GHz with 24 MB L3 Cache 9150M Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9150N Dual-Core Intel® Itanium® Processor 1.66 GHz with 18 MB L3 Cache 9140M Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9140N Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9120N Dual-Core Intel® Itanium® Processor 1.66 GHz with 8 MB L3 Cache 9130M Intel® Itanium® Processor 1.6 GHz with 12 MB L3 Cache 9110N Datasheet October 2007 Document Number: 314054-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Dual-Core Intel® Itanium® 9000 and 9100 series processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548-4725, or by visiting Intel's website at http://www.intel.com. Intel, Itanium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © 2002-2007, Intel Corporation *Other names and brands may be claimed as the property of others. I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel. Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips Electronics, N.V. and North American Phillips Corporation. 2 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Contents 1 Introduction............................................................................................................... 11 1.1 Overview ......................................................................................................... 11 1.2 Processor Abstraction Layer ................................................................................ 11 1.3 Mixing Processors of Different Frequencies and Cache Sizes .................................... 12 1.4 Terminology ..................................................................................................... 12 1.5 State of Data .................................................................................................... 12 1.6 Reference Documents ........................................................................................ 13 Electrical Specifications ............................................................................................... 15 2.1 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series System Bus .................. 15 2.1.1 System Bus Power Pins ........................................................................ 15 2.1.2 System Bus No Connect ....................................................................... 15 2.2 System Bus Signals ........................................................................................... 15 2.2.1 Signal Groups ..................................................................................... 15 2.2.2 Signal Descriptions .............................................................................. 17 2.3 Package Specifications ....................................................................................... 18 2.4 Signal Specifications .......................................................................................... 18 2.4.1 Maximum Ratings ................................................................................ 22 2.5 System Bus Signal Quality Specifications and Measurement Guidelines ..................... 23 2.5.1 Overshoot/Undershoot Magnitude .......................................................... 23 2.5.2 Overshoot/Undershoot Pulse Duration .................................................... 24 2.5.3 Activity Factor..................................................................................... 24 2.5.4 Reading Overshoot/Undershoot Specification Tables ................................. 24 2.5.5 Determining if a System Meets the Overshoot/Undershoot Specifications...................................................................................... 25 2.5.6 Wired-OR Signals ................................................................................ 25 2.6 Voltage Regulator Connector Signals.................................................................... 27 2.7 System Bus Clock and Processor Clocking............................................................. 31 2.8 Recommended Connections for Unused Pins.......................................................... 33 Pinout Specifications ................................................................................................... 35 Mechanical Specifications............................................................................................. 65 4.1 Processor Package Dimensions ............................................................................ 65 4.1.1 Voltage Regulator (MVR) to Processor Package Interface........................... 71 4.2 Package Marking ............................................................................................... 72 4.2.1 Processor Top-Side Marking .................................................................. 72 4.2.2 Processor Bottom-Side Marking ............................................................. 73 Thermal Specifications ................................................................................................ 75 5.1 Thermal Features .............................................................................................. 75 5.1.1 Thermal Alert...................................................................................... 75 5.1.2 Enhanced Thermal Management ............................................................ 76 5.1.3 Power Trip .......................................................................................... 76 5.1.4 Thermal Trip ....................................................................................... 76 5.2 Case Temperature ............................................................................................. 76 System Management Feature Specifications ................................................................... 79 6.1 System Management Bus ................................................................................... 79 6.1.1 System Management Bus Interface ........................................................ 79 6.1.2 System Management Interface Signals ................................................... 79 6.1.3 SMBus Device Addressing ..................................................................... 81 6.2 Processor Information ROM ................................................................................ 82 6.3 Scratch EEPROM ............................................................................................... 85 2 3 4 5 6 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 3 6.4 6.5 6.6 6.7 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions .....................................................................................................85 Thermal Sensing Device .....................................................................................86 Thermal Sensing Device Supported SMBus Transactions..........................................87 Thermal Sensing Device Registers........................................................................88 6.7.1 Thermal Reference Registers .................................................................88 6.7.2 Thermal Limit Registers ........................................................................89 6.7.3 Status Register ....................................................................................89 6.7.4 Configuration Register ..........................................................................89 6.7.5 Conversion Rate Register ......................................................................90 A Signals Reference .......................................................................................................91 A.1 Alphabetical Signals Reference ............................................................................91 A.1.1 A[49:3]# (I/O).......................................................................................91 A.1.2 A20M# (I) .............................................................................................91 A.1.3 ADS# (I/O)............................................................................................91 A.1.4 AP[1:0]# (I/O).......................................................................................91 A.1.5 ASZ[1:0]# (I/O).....................................................................................91 A.1.6 ATTR[3:0]# (I/O) ...................................................................................92 A.1.7 BCLKp/BCLKn (I) ....................................................................................92 A.1.8 BE[7:0]# (I/O).......................................................................................92 A.1.9 BERR# (I/O) ..........................................................................................93 A.1.10 BINIT# (I/O)..........................................................................................94 A.1.11 BNR# (I/O)............................................................................................94 A.1.12 BPM[5:0]# (I/O) ....................................................................................94 A.1.13 BPRI# (I) ..............................................................................................94 A.1.14 BR[0]# (I/O) and BR[3:1]# (I).................................................................94 A.1.15 BREQ[3:0]# (I/O)...................................................................................95 A.1.16 CCL# (I/O) ............................................................................................96 A.1.17 CPUPRES# (O) .......................................................................................96 A.1.18 D[127:0]# (I/O).....................................................................................96 A.1.19 D/C# (I/O) ............................................................................................96 A.1.20 DBSY# (I/O) ..........................................................................................96 A.1.21 DBSY_C1# (O) .......................................................................................96 A.1.22 DBSY_C2# (O) .......................................................................................96 A.1.23 DEFER# (I) ............................................................................................96 A.1.24 DEN# (I/O)............................................................................................97 A.1.25 DEP[15:0]# (I/O) ...................................................................................97 A.1.26 DHIT# (I) ..............................................................................................97 A.1.27 DPS# (I/O) ............................................................................................98 A.1.28 DRDY# (I/O)..........................................................................................98 A.1.29 DRDY_C1# (O).......................................................................................98 A.1.30 DRDY_C2# (O).......................................................................................98 A.1.31 DSZ[1:0]# (I/O) ....................................................................................98 A.1.32 EXF[4:0]# (I/O) .....................................................................................98 A.1.33 FCL# (I/O) ............................................................................................99 A.1.34 FERR# (O).............................................................................................99 A.1.35 GSEQ# (I) .............................................................................................99 A.1.36 HIT# (I/O) and HITM# (I/O) ....................................................................99 A.1.37 ID[9:0]# (I) ..........................................................................................99 A.1.38 IDS# (I)................................................................................................99 A.1.39 IGNNE# (I)............................................................................................99 A.1.40 INIT# (I) ...............................................................................................99 A.1.41 INT (I) ................................................................................................ 100 A.1.42 IP[1:0]# (I) ......................................................................................... 100 A.1.43 LEN[2:0]# (I/O) ................................................................................... 100 A.1.44 LINT[1:0] (I) ....................................................................................... 100 4 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet A.2 A.1.45 LOCK# (I/O)........................................................................................ 100 A.1.46 NMI (I) ............................................................................................... 101 A.1.47 OWN# (I/O) ........................................................................................ 101 A.1.48 PMI# (I) ............................................................................................. 101 A.1.49 PWRGOOD (I) ...................................................................................... 101 A.1.50 REQ[5:0]# (I/O) .................................................................................. 101 A.1.51 RESET# (I) ......................................................................................... 102 A.1.52 RP# (I/O) ........................................................................................... 102 A.1.53 RS[2:0]# (I) ....................................................................................... 103 A.1.54 RSP# (I) ............................................................................................. 103 A.1.55 SBSY# (I/O)........................................................................................ 103 A.1.56 SBSY_C1# (O)..................................................................................... 103 A.1.57 SBSY_C2# (O)..................................................................................... 103 A.1.58 SPLCK# (I/O) ...................................................................................... 103 A.1.59 STBn[7:0]# and STBp[7:0]# (I/O) ......................................................... 103 A.1.60 TCK (I) ............................................................................................... 104 A.1.61 TDI (I)................................................................................................ 104 A.1.62 TDO (O).............................................................................................. 104 A.1.63 THRMTRIP# (O) ................................................................................... 104 A.1.64 THRMALERT# (O)................................................................................. 104 A.1.65 TMS (I) ............................................................................................... 104 A.1.66 TND# (I/O) ......................................................................................... 104 A.1.67 TRDY# (I) ........................................................................................... 105 A.1.68 TRST# (I) ........................................................................................... 105 A.1.69 WSNP# (I/O)....................................................................................... 105 Signal Summaries ........................................................................................... 105 Figures 2-1 2-2 2-3 2-4 2-5 2-6 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 6-1 Generic Clock Waveform .................................................................................... 21 SMSC Clock Waveform ....................................................................................... 22 System Bus Signal Waveform Exhibiting Overshoot/Undershoot............................... 23 Processors Power Tab Physical Layout .................................................................. 28 System Bus Reset and Configuration Timings for Cold Reset.................................... 31 System Bus Reset and Configuration Timings for Warm Reset ................................. 32 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Pinout.......................... 35 Processor Package............................................................................................. 66 Package Height and Pin Dimensions ..................................................................... 67 Processor Package Mechanical Interface Dimensions .............................................. 69 Processor Package Top-Side Components Height Dimensions .................................. 70 Processor Package Bottom-Side Components Height Dimensions ............................. 70 Processor to MVR Interface Loads ........................................................................ 71 Processor Top-Side Marking on IHS ..................................................................... 73 Processor Bottom-Side Marking Placement on Interposer ........................................ 74 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Thermal Features .......................................................................................................... 75 Itanium® Processor Package Thermocouple Location .............................................. 77 Logical Schematic of SMBus Circuitry ................................................................... 80 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 5 Tables 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 3-1 3-2 4-1 4-2 4-3 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 Itanium® Processor System Bus Signal Groups ......................................................16 Nominal Resistance Values for Tuner1, Tuner2, and Tuner3 .....................................17 Processor Package Specifications .........................................................................18 AGTL+ Signals DC Specifications..........................................................................19 Power Good Signal DC Specifications ....................................................................19 System Bus Clock Differential HSTL DC Specifications .............................................19 TAP Connection DC Specifications ........................................................................19 SMBus DC Specifications.....................................................................................20 LVTTL Signal DC Specifications ............................................................................20 System Bus Clock Differential HSTL AC Specifications .............................................20 SMBus AC Specifications .....................................................................................21 Dual-Core Intel® Itanium® Processor Absolute Maximum Ratings.............................22 Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group Absolute Overshoot/Undershoot Tolerance ............................................................25 Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/ Undershoot Tolerance for 400-MHz System Bus .....................................................26 Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot Tolerance for 400-MHz System Bus......................................26 Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/ Undershoot Tolerance for 533-MHz System Bus .....................................................26 Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot Tolerance for 533-MHz System Bus......................................27 VR Connector Signals .........................................................................................27 Power Connector Pinouts ....................................................................................28 Processors Core Voltage Identification Code (VCORE and VCACHE) ...........................30 Connection for Unused Pins .................................................................................33 TUNER1/TUNER3 Translation Table.......................................................................34 Pin/Signal Information Sorted by Pin Name ...........................................................36 Pin/Signal Information Sorted by Pin Location........................................................50 Processor Package Dimensions ............................................................................67 Processor Package Mechanical Interface Dimensions...............................................68 Processor Package Load Limits at Power Tab .........................................................71 Case Temperature Specification ...........................................................................77 System Management Interface Signal Descriptions .................................................79 Thermal Sensing Device SMBus Addressing on the Dual-Core Intel® Itanium® Processor 9000 and 9100 series.............................................................81 EEPROM SMBus Addressing on the Dual-Core Intel® Itanium® Processor 9000 and 9100 Series ........................................................................................82 Processor Information ROM Format ......................................................................82 Current Address Read SMBus Packet ....................................................................85 Random Address Read SMBus Packet ...................................................................86 Byte Write SMBus Packet ....................................................................................86 Write Byte SMBus Packet ....................................................................................87 Read Byte SMBus Packet ....................................................................................87 Send Byte SMBus Packet ....................................................................................87 Receive Byte SMBus Packet.................................................................................87 ARA SMBus Packet .............................................................................................87 Command Byte Bit Assignment ............................................................................88 Thermal Sensing Device Status Register ...............................................................89 Thermal Sensing Device Configuration Register......................................................89 Thermal Sensing Device Conversion Rate Register..................................................90 6 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet A-1 A-2 A-3 A-5 A-4 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 Address Space Size ........................................................................................... 92 Effective Memory Type Signal Encoding ................................................................ 92 Special Transaction Encoding on Byte Enables ....................................................... 93 BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect ...................... 95 BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect ...................... 95 BR[3:0]# Signals and Agent IDs ......................................................................... 95 DID[9:0]# Encoding .......................................................................................... 97 Extended Function Signals .................................................................................. 98 Length of Data Transfers .................................................................................. 100 Transaction Types Defined by REQa#/REQb# Signals ........................................... 102 STBp[7:0]# and STBn[7:0]# Associations .......................................................... 104 Output Signals ................................................................................................ 105 Input Signals .................................................................................................. 105 Input/Output Signals (Single Driver) .................................................................. 106 Input/Output Signals (Multiple Driver)................................................................ 107 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 7 Revision History Document Number 314054 314054 Revision Number -002 -001 • • Description Updated with 9100 series product information; updated brand name from “Itanium 2” to “Itanium”. Initial release of the document. Date October 2007 July 2006 8 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050 Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040 Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030 Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9020 Dual-Core Intel® Itanium® Processor 1.4 GHz with 12 MB L3 Cache 9015 Intel® Itanium® Processor 1.6 GHz with 6 MB L3 Cache 9010 Dual-Core Intel® Itanium® Processor 1.66 GHz with 24 MB L3 Cache 9150M Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9150N Dual-Core Intel® Itanium® Processor 1.66 GHz with 18 MB L3 Cache 9140M Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9140N Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9120N Dual-Core Intel® Itanium® Processor 1.66 GHz with 8 MB L3 Cache 9130M Intel® Itanium® Processor 1.6 GHz with 12 MB L3 Cache 9110N Product Features Dual Core — Two complete 64-bit processing cores on one processor. EPIC (Explicitly Parallel Instruction Computing) Technology for current and future requirements of high-end enterprise and technical workloads — Provide a variety of advanced implementations of parallelism, predication, and speculation, resulting in superior Instruction-Level Parallelism (ILP). Hyper-Threading Technology — Two times the number of OS threads per core provided by earlier single-thread implementations. Wide, parallel hardware based on architecture for high performance: — Integrated on-die L3 cache of up to 24MB; cache hints for L1, L2, and L3 caches for reduced memory latency. — 128 general and 128 floating-point registers supporting register rotation. — Register stack engine for effective management of processor resources. — Support for predication and speculation. Intel® Itanium® Intel® Virtualization Technology for virtualization for data-intensive applications. — Reduces virtualization complexity. — Improves virtualization performance. — Increases operating system compatibility. Intel® Cache Safe Technology ensures mainframecaliber availability. — Minimize L3 cache errors. Outstanding Energy Efficiency. — 20 percent less power than previous Intel Itanium processor. — 2.5 times higher performance per watt. High-bandwidth system bus for multiprocessor scalability: — Up to 8.53GB/s bandwidth. — 128-bit wide data bus. — 50-bits of physical memory addressing and 64-bits of virtual addressing. — Up to four physical processors on the same system bus at 400-MHz or 533-MHz data bus frequency. — Expandable to systems with multiple system buses. Features to support flexible platform environments: — IA-32 Execution Layer supports IA-32 application binaries. — Bi-endian support. — Processor abstraction layer eliminates processor dependencies. 667-MHz, 1.66-GHz, 3-load busa — This feature enables increased bandwidth for Enterprise and HPC. Demand Based Switching (DBS)a — Provides additional power management capability. Extensive RAS features for business-critical applications: — Full SMBus compatibility. — Enhanced machine check architecture with extensive ECC and parity protection. — Enhanced thermal management. — Built-in processor information ROM (PIROM). — Built-in programmable EEPROM. — Socket Level Lockstep — Core Level Lockstep a. This feature is applicable to only the 9100 series processors Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 9 The Dual-Core Intel® Itanium® processor 9000 and 9100 series delivers new levels of flexibility, reliability, performance, and cost-effective scalability for your most data-intensive business and technical applications. With double the performance of previous Intel Itanium processors, the DualCore Intel Itanium processor 9000 and 9100 series provides more reasons than ever to migrate your business-critical applications off RISC and mainframe systems and onto cost-effective Intel architecture servers. The Dual-Core Intel Itanium processor 9000 and 9100 series provides close to triple the amount of L3 cache (24 megabytes), Hyper-Threading Technology for increased performance, Intel® Virtualization Technology for improved virtualization, Intel® Cache Safe Technology for increased availability, and 20 percent lower power consumption. Dual-Core Itanium®-based systems are available from leading OEMs worldwide and run popular 64bit operating systems such as Microsoft* Windows Server* 2003; Linux* from SuSE, Red Hat, Red Flag, and other distributions; HP NonStop*; OpenVMS*; and HP-UX*. More than 7,000 applications are available for Itanium-based systems, from vendors such as Microsoft, BEA, IBM, Ansys, Gaussian, Symantec/VERITAS, Oracle, SAP, and SAS. And with industry support growing and future Intel Itanium processor family advances already in development, your Itanium-based server investment will continue to deliver performance advances and savings for your most demanding applications. § 10 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Introduction 1 1.1 Introduction Overview The Dual-Core Intel Itanium processor 9000 and 9100 series employs Explicitly Parallel Instruction Computing (EPIC) design concepts for a tighter coupling between hardware and software. In this design style, the interface between hardware and software is engineered to enable the software to exploit all available compile-time information and efficiently deliver this information to the hardware. It addresses several fundamental performance bottlenecks in modern computers, such as memory latency, memory address disambiguation, and control flow dependencies. The EPIC constructs provide powerful architectural semantics and enable the software to make global optimizations across a large scheduling scope, thereby exposing available Instruction Level Parallelism (ILP) to the hardware. The hardware takes advantage of this enhanced ILP, and provides abundant execution resources. Additionally, it focuses on dynamic runtime optimizations to enable the compiled code schedule to flow at high throughput. This strategy increases the synergy between hardware and software, and leads to greater overall performance. The Dual-Core Intel Itanium processor 9000 and 9100 series provides a 6-wide and 8stage deep pipeline, running at up to 1.6 GHz. This provides a combination of abundant resources to exploit ILP as well as increased frequency for minimizing the latency of each instruction. The resources consist of six integer units, six multimedia units, two load and two store units, three branch units, two extended-precision floating-point units, and one additional single-precision floating-point unit per core. The hardware employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking caches to optimize for compile-time non-determinism. Three levels of on-die cache minimize overall memory latency. This includes up to a 24 MB L3 cache, accessed at core speed, providing up to 8.53 GB/sec. of data bandwidth. The system bus is designed to support up to four physical processors (on a single system bus), and can be used as an effective building block for very large systems. The balanced core and memory subsystem provide high performance for a wide range of applications ranging from commercial workloads to high-performance technical computing. The Dual-Core Intel Itanium processor 9000 and 9100 series supports a range of computing needs and configurations from a two-way to large SMP servers. This document provides the electrical, mechanical and thermal specifications for the DualCore Intel Itanium processor 9000 and 9100 series for use while employing systems with the processors. 1.2 Processor Abstraction Layer The Dual-Core Intel Itanium processor 9000 and 9100 series requires implementationspecific Processor Abstraction Layer (PAL) firmware. PAL firmware supports processor initialization, error recovery, and other functionality. It provides a consistent interface to system firmware and operating systems across processor hardware implementations. The Intel® Itanium® Architecture Software Developer’s Manual, Volume 2: System Architecture, describes PAL. Platforms must provide access to the firmware address space and PAL at reset to allow the processors to initialize. Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 11 Introduction The System Abstraction Layer (SAL) firmware contains platform-specific firmware to initialize the platform, boot to an operating system, and provide runtime functionality. Further information about SAL is available in the Intel® Itanium® Processor Family System Abstraction Layer Specification. 1.3 Mixing Processors of Different Frequencies and Cache Sizes All Dual-Core Intel Itanium processor 9000 and 9100 series on the same system bus are required to have the same cache size (24 MB, 18 MB, 12 MB, 8 MB or 6 MB) and identical core frequency. Mixing components of different core frequencies and cache sizes is not supported and has not been validated by Intel. Operating system support for multiprocessing with mixed components should also be considered. While Intel has done nothing to specifically prevent processors within a multiprocessor environment from operating at differing frequencies and differing cache sizes, there may be uncharacterized errata that exist in such configurations. Customers would be fully responsible for validation of system configurations with mixed components other than the supported configurations described above. 1.4 Terminology In this document, “the processor” refers to the “Dual-Core Intel Itanium processor 9000 and 9100 series” processor, unless otherwise indicated. A ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when RESET# is low, a processor reset has been requested. When NMI is high, a non-maskable interrupt has occurred. In the case of lines where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also refers to a hex ‘A’ (H = High logic level, L = Low logic level). The term “system bus” refers to the interface between the processor, system core logic, and other bus agents. The system bus is a multiprocessing interface to processors, memory, and I/O. A signal name has all capitalized letters, for example, VCTERM. A symbol referring to a voltage level, current level, or a time value carries a plain subscript, for example, Vcore, or a capitalized, abbreviated subscript, for example, TCO. 1.5 State of Data The data contained in this document is subject to change. It is the best information that Intel is able to provide at the publication date of this document. 12 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Introduction 1.6 Reference Documents The reader of this specification should also be familiar with material and concepts presented in the following documents: Intel® Itanium® 2 Processor Specification Update Intel® Itanium® Architecture Software Developer’s Manual, Volume 1: Application Architecture Intel® Itanium® Architecture Software Developer’s Manual, Volume 2: System Architecture Intel® Itanium® Architecture Software Developer’s Manual, Volume 3: Instruction Set Reference Intel® Itanium® 2 Processor Reference Manual for Software Development and Optimization Intel® Itanium® Processor Family System Abstraction Layer Specification ITP700 Debug Port Design Guide System Management Bus Specification Note: Contact your Intel representative or check http://developer.intel.com for the latest revision of the reference documents. § Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 13 Introduction 14 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Electrical Specifications 2 Electrical Specifications This chapter describes the electrical specifications of the Dual-Core Intel Itanium Processor 9000 and 9100 series. 2.1 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series System Bus Most Dual-Core Intel Itanium processor 9000 and 9100 series signals use the Itanium processor’s assisted gunning transceiver logic (AGTL+) signaling technology. The termination voltage, VCTERM, is generated on the baseboard and is the system bus high reference voltage. The buffers that drive most of the system bus signals on the processor are actively driven to VCTERM during a low-to-high transition to improve rise times and reduce noise. These signals should still be considered open-drain and require termination to VCTERM which provides the high level. The processor system bus is terminated to VCTERM at each end of the bus. There is also support of off-die termination, in which case, the termination is provided by external resistors connected to VCTERM. AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used by the receivers to determine if a signal is a logical 0 or a logical 1. The processor generates VREF on-die, thereby eliminating the need for an off-chip reference voltage source. 2.1.1 System Bus Power Pins VCTERM (1.2 V) input pins on the processor provide power to the driver buffers and ondie termination. The GND pins, in addition to the GND input at the power tab connector, provide ground to the processor. Power for the processor core is supplied through the power tab connector by VCore, VCache, Vfixed. The 3.3 V pin is included on the processor to provide power to the system management bus (SMBus). The VCTERM, 3.3 V, and GND pins must remain electrically separated from each other. 2.1.2 System Bus No Connect All pins designated as “N/C” or “No Connect” must remain unconnected. 2.2 2.2.1 System Bus Signals Signal Groups Table 2-1 shows processor system bus signals that have been combined into groups by buffer type and whether they are inputs, outputs, or bidirectional, with respect to the processor. Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 15 Electrical Specifications .. Table 2-1. Itanium® Processor System Bus Signal Groups Group Name AGTL+ Input Signals AGTL+ I/O Signals Signals BPRI#, BR[3:1]#, DEFER#, GSEQ#, ID[9:0]#, IDS#, RESET#1, RS[2:0]#, RSP#, TRDY# A[49:3]#, ADS#, AP[1:0]#, BERR#, BINIT#, BNR#, BPM[5:0]#1, BR0#, D[127:0]#, DBSY#, DEP[15:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[5:0]#, RP#, SBSY#, STBN[7:0]#, STBP[7:0]#, TND# FERR#, THRMTRIP#, DBSY[1:0]#, DRDY[1:0]#, SBSY[1:0]# A20M#, IGNNE#, INIT#, LINT[1,0], PMI# PWRGOOD BCLKn, BCLKp TCK, TDI, TMS, TRST# TDO Signals1 3.3 V, SMA[2:0], SMSC, SMSD, SMWP, THRMALERT# GND, VCTERM 1 AGTL+ Output Signals Special AGTL+ Asynchronous Interrupt Input Signals Power Good Signal1 HSTL Clock Signals TAP Input Signals1 TAP Output Signals1 System Management Power Signals LVTTL Power Pod Signals Other Notes: CPUPRES#, OUTEN, PPODGD# TERMA, TERMB, TUNER1, TUNER2, TUNER3, VCCMON, VSSMON 1. Signals will not be terminated on-die even when on-die termination (ODT) is enabled. See the Intel® Itanium® 2 Processor Hardware Developer’s Manual for further details. All system bus outputs should be treated as open drain signals and require a high-level source provided by the VCTERM supply. AGTL+ inputs have differential input buffers which use VREF as a reference level. AGTL+ output signals require termination to VCTERM. In this document, “AGTL+ Input Signals” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output Signals” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. The Test Access Port (TAP) connection input signals use a non-differential receiver with levels that are similar to AGTL+. No reference voltage is required for these signals. The TAP Connection Output signals are AGTL+ output signals. The processor system bus requires termination on both ends of the bus. The processor system bus supports both on-die and off-die termination controlled by two pins, TERMA and TERMB. Please see the TERMA and TERMB pin description in Section 2.2.2. The HSTL clock signals are the differential clock inputs for the processor. The SMBus signals and LVTTL power pod signals are driven using the 3.3 V CMOS logic levels listed in Table 2-8 and Table 2-9, respectively. 16 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Electrical Specifications 2.2.2 Signal Descriptions Appendix A, “Signals Reference”, contains functional descriptions of all system bus signals and LVTTL power pod signals. Further descriptions of the system management signals are contained in Chapter 6. The signals listed under the “Power” and “Other” group are described here: VCTERM GND N/C TERMA, TERMB System bus termination voltage. System ground. No connection can be made to these pins. The processor uses two pins to control the on-die termination function: TERMA and TERMB. Both of these termination pins must be pulled to VCTERM in order to terminate the system bus using the on-die termination resistors. Both of these termination pins must be pulled to GND in order to use off-die termination. The TUNER1 Pin can either be left as a no-connect or left connected to VCTERM via resistor for the majority of platforms supporting the Dual-Core Intel Itanium processor 9000 and 9100 series. The TUNER2 resistor is used to control the termination resistance for the system bus I/O buffers. A lower resistance will cause a lower on-die termination resistance. Ondie termination mode will only be selected if the TERMA and TERMB pins are terminated as indicated above. The TUNER3 pin will not be required for the majority of platforms supporting the Dual-Core Intel Itanium processor 9000 and 9100 series. The TUNER3 pin is used only in the case where A[21:17]# are driven to all zeros or all ones during the configuration cycles at reset. When all zeros or all ones are observed by the processor the presence of the TUNER3 and TUNER1 pins is used to determine system bus frequency. See Table 2-22 for the various TUNER pin combinations and resulting system bus frequency and slew rate combination. These pins allows remote measurement of on-die Vcore voltage. No connections that constitute a current load can be made to these pins. TUNER1, TUNER2, TUNER3 VCCMON, VSSMON Table 2-2. Nominal Resistance Values for Tuner1, Tuner2, and Tuner3 400 MHz 5-Load Platform (Ohms) Tuner1: NC1 Tuner2: 150 Tuner3: NC1 Notes: 1. Depending on system configuration, the processor may or may not require a resistor on the TUNER pin. OEMs may leave the pin unconnected or connect it to VCTERM through a 150 or 100 ohm resistor. If A[21:17]:# are driven to all 0’s or all 1’s at reset, see Table 2-22 for proper use of the TUNER Pins. 400 MHz 3-Load Platform (Ohms) Tuner1: NC1 Tuner2: 150 Tuner3: NC1 533 MHz 3-Load Platform (Ohms) Tuner1: NC1 Tuner2: 150 Tuner3: NC1 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 17 Electrical Specifications 2.3 Package Specifications Table 2-3 through Table 2-9 list the DC voltage, current, and power specifications for the processor. The voltage and current specifications are defined at the processor pins. Operational specifications listed in Table 2-3 through Table 2-9 are only valid while meeting specifications for case temperature, clock frequency, and input voltages. Table 2-3. Processor Package Specifications Symbol Vcore, PS Vcache, PS Vfixed, PS VCTERM RTERM VTAP Icore,PS Icache,PS Ifixed,PS ICTERM PSTT Parameter VCC from the Voltage Regulator Vcache from the Voltage Regulator Vfixed from the Voltage Regulator Termination Voltage Recommended Termination Resistance Test Access Port Voltage (VCCTAP) Core Current Required from Power Supply Cache Current Required from Power Supply Fixed Current Required from Power Supply Termination Voltage Current Power Supply Slew Rate for the Termination Voltage at the Processor Pins Max Power Thermal Power Envelope Thermal Design Power – dual core Thermal Design Power – single core Notes: 1. The range for Vcore is 1.0875 V to 1.25 V. 2. Vcache typical is 1.025 V. 3. The processor system bus is terminated at each end of the system bus. The processor supports both on-die and off-die termination which is selected by the TERMA and TERMB pins. Termination tolerance is ±15% for on-die termination measured at VOL and ±1% for off-die termination. 4. This is measured for On-Die Termination with a 45-ohm pull up resistor. 5. Max power is peak electrical power that must be provided for brief periods by the VR. 6. Represents the TDP level that should be used for system thermal design. Sustained power for all real-world applications will remain at or below this power level. Core Frequency All All All All All All All All All All All Minimum VID-17 mV VID-17 mV 1.25-20 mV 1.2-1.5% 45-15% 1.2-1.5% 2.8 2.0 0.7 Typ VID VID 1.25 1.2 45 1.2 89 17 9.2 Maximum VID+17 mV VID+17 mV 1.25+20 mV 1.2+1.5% 45+15% 1.5 121 18 11 7.2 0.05 Unit V V V V Ohm V A A A A A/ns 4 3 Notes 1 2 PWRmax PWRTPE PWRTDP All All All 1.6 GHz 177 130 104 75 W W W W 5 6 2.4 Signal Specifications This section describes the DC specifications of the system bus signals. The processor signal’s DC specifications are defined at the processor pins. Table 2-4 through Table 2-9 describe the DC specifications for the AGTL+, PWRGOOD, HSTL clock, TAP port, system management, and LVTTL signals. Please refer to the ITP700 Debug Port Design Guide for the TAP connection signals’ DC specifications at the debug port. 18 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Electrical Specifications Table 2-4. AGTL+ Signals DC Specifications Symbol VIL VIH VOL VOH IOL IOL IL CAGTL+ Notes: 1. The typical transition point between VIL and VIH assuming 125 mV VREF uncertainty for ODT. VREF_high and VREF_low levels are VREF ±100 mV, respectively, for a system bus agent using on-board termination. VREF_high and VREF_low levels are VREF ±125 mV, respectively, for a system bus agent using on-die termination. 2. Parameter measured into a 22.5 ohm resistor to 1.2 V. Minimum VOL and IOL are guaranteed by design/ characterization. 3. Calculated using off-die termination through two 45 ohm ±1% resistors in parallel. 4. Calculated using on-die termination to a 45 ±15% resistor measured at VOL. 5. At 1.2 V ±1.5%. VCTERM, minimum ≤Vpin ≤VCTERM, maximum. 6. Total of I/O buffer with ESD structure and processor parasitics if applicable. Capacitance values guaranteed by design for all AGTL+ buffers. Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current @ 0.3 V Output Low Current @ 0.3 V Leakage Current AGTL+ Pad Capacitance Core Frequency All All All All All All All All VCTERM, minimum 34 17 ±100 2 0.875 0.3 VCTERM 0.4 VCTERM, maximum Minimum Typ Maximum 0.625 Unit V V V V mA mA µA pF 3 4 5 6 Notes 1 1 2 Table 2-5. Power Good Signal DC Specifications Symbol VIL VIH Parameter Input Low Voltage Input High Voltage 0.875 Minimum Maximum 0.440 Unit V V Notes Table 2-6. System Bus Clock Differential HSTL DC Specifications Symbol VIH VIL VX CCLK Parameter Input High Voltage Input Low Voltage Input Crossover Voltage Input (Pad) Capacitance Minimum 0.78 –0.3 0.55 Maximum 1.3 0.5 0.85 1.75 Unit V V V pF Notes Table 2-7. TAP Connection DC Specifications Symbol VIL VIH VOL VOH IOL IIC Notes: 1. 2. 3. 4. There is a 100 mV hysteresis on TCK. VIH, MAX = 1.5 V + 5%, VOH, MAX = 1.2 V +5%. There is no internal pull-up. An external pull-up is always assumed. Max voltage tolerated at TDO is 1.5 V. Per input pin. Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Input Current 1.2 20 690 Minimum –0.3 1.1 Maximum 0.5 1.57 0.3 Unit V V V V mA uA 4 2, 3 Notes 1 1, 2 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 19 Electrical Specifications Table 2-8. SMBus DC Specifications Symbol 3.3V VIL VIH Parameter VCC for the System Management Components Input Low Voltage Input High Voltage Minimum 3.14 –0.3 2.31 Typ 3.3 Maximum 3.47 0.3*3.3 V 3.47 Unit V V V Max = 3.3 +5% Min + 0.7*3.3V Notes 3.3 V ±5 VOL I3.3V IOL IOL2 ILI ILO Notes: Output Low Voltage 3.3V Supply Current Output Low Current Output Low Current Input Leakage Current Output Leakage Current 6 5.0 0.4 30.0 3 10 10 V mA mA mA µA µA 1 2 1. The value specified for IOL applies to all signals except for THRMALERT#. 2. The value specified for IOL2 applies only to THRMALERT#, which is an open drain signal. Table 2-9. LVTTL Signal DC Specifications Symbol VIL VIH VOL VOH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 2.0 Minimum Maximum 0.8 3.63 0.4 Unit V V V V Notes Table 2-10 through Table 2-11 list the AC specifications for the processor’s clock and SMBus (timing diagrams begin with Figure 2-1). The processor uses a differential HSTL clocking scheme with a frequency of 200, 266, or 333 MHz. The SMBus is a subset of the I2C* interface which supports operation of up to 100 kHz. Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 1 of 2) Symbol Parameter System Bus Clock (MHz) 200 200 200 200 200 200 266 266 266 266 266 266 1.69 1.69 1.88 1.88 266 2.25 2.25 2.5 2.5 3.75 60 266 50 2.06 2.06 200 Minimum Typ Maximum Unit Figure Notes Tperiod Tskew fBCLK Tjitter Thigh Tlow Tperiod Tskew fBCLK Tjitter Thigh Tlow BCLKp Period System Clock Skew BCLKp Frequency BCLKp Input Jitter BCLKp High Time BCLKp Low Time BCLKp Period System Clock Skew BCLKp Frequency BCLKp Input Jitter BCLKp High Time BCLKp Low Time 5.0 100 200 100 2.75 2.75 ns ps MHz ps ns ns ns ps MHz ps ns ns Figure 2-1 1 Figure 2-1 Figure 2-1 Figure 2-1 Figure 2-1 Figure 2-1 2 3 4 4 5 Figure 2-1 Figure 2-1 Figure 2-1 Figure 2-1 2 3 4 4 20 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Electrical Specifications Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2) Symbol Parameter BCLKp Rise Time7 BCLKp Fall Time7 Minimum Input Swing System Bus Clock (MHz) All All All Minimum Typ Maximum Unit Figure Notes Trise Tfall VPP Notes: 333 333 500 500 600 667 667 ps ps mV Figure 2-1 Figure 2-1 Figure 2-1 20–80% 20–80% 6 1. The system clock skew is ±100 ps. 2. Measured on cross-point of rising edge of BCLKp and falling edge of BCLKn. Long-term jitter is defined as peak-to-peak variation measured by accumulating a large number of clock cycles and recording peak-to-peak jitter. 3. Cycle-to-cycle jitter is defined as peak-to-peak variation measured over 10,000 cycles peak-to-peak jitter. 4. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn. 5. The system clock skew is ±60 ps. 6. VPPmin is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing. 7. The measurement is taken at 40-60% of the signal and extrapolated to 20-80%. Table 2-11. SMBus AC Specifications Symbol fSMSC TSMSC thigh tlow trise tfall tVALID tSU tHLD tFREE Notes: 1. Please refer to Figure 2-2 for the Standard Microsystems Corporation (SMSC)* clock waveform. 2. Bus Free Time is the minimum time allowed between request cycles. Parameter SMSC Clock Frequency SMSC Clock Period SMSC Clock High Time SMSC Clock Low Time SMSC Clock Rise Time SMSC Clock Fall Time SMBus Output Valid Delay SMBus Input Setup Time SMBus Input Hold Time Bus Free Time 250 0 4.7 10 4.0 4.7 1.0 0.3 1.0 Minimum Maximum 100 Unit kHz µs µs µs µs µs µs ns ns µs 2 1 1 1 1 Notes Figure 2-1. Generic Clock Waveform Thigh Trise Vpp 80% 20% Tperiod BCLKP Tlow Tfall BCLKN Tjitter Trise = Rise Time Tfall = Fall Time Thigh = High Time Tlow = Low Time Tperiod = Period Tjitter Vpp = Long Term Peak-to-Peak Jitter = Peak-to-Peak Swing 000615 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 21 Electrical Specifications Figure 2-2. SMSC Clock Waveform Thigh Trise SMSC 75% Vcc 25% Vcc Tfall Tlow 90% Vcc Vcc (3.3V) Trise = Rise Time Tfall = Fall Time Thigh = High Time Tlow = Low Time 000618 2.4.1 Maximum Ratings Table 2-12 contains the processor stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid static voltages or electric fields. Table 2-12. Dual-Core Intel® Itanium® Processor Absolute Maximum Ratings Symbol Tstorage Tshipping Vcore Vcache Vfixed 3.3V Vin, SMBus Vin, AGTL+ VCTERM Vin,TAP Notes: 1. 2. 3. 4. 5. Storage temperature is temperature in which the processor can be stored for up to one year. Shipping temperature is temperature in which the processor can be shipped for up to 24 hours. Parameters are from third-party vendor specifications. Maximum instantaneous voltage at receiver buffer input. Specification includes Vin,AGTL+ and Vin,AGTL+ ASYNCHRONOUS (AGTL+ asynchronous buffer DC input voltage with respect to GND. Parameter Processor Storage Temperature Processor Shipping Temperature Any Vcore Voltage with Respect to GND Any Vcache Voltage with Respect to GND Any Vfixed Voltage with Respect to GND Any 3.3 V Supply Voltage with Respect to GND SMBus Buffer DC Input Voltage with Respect to GND AGTL+ Buffer DC Input Voltage with Respect to GND Any VCTERM Voltage with Respect to GND TAP Buffer DC Input Voltage with Respect to GND. Minimum –10 –45 -0.3 -0.3 -0.3 –0.3 –0.1 –0.45 -0.45 -0.45 Maximum 45 75 1.55 1.55 1.55 5.5 6.0 1.65 1.65 1.65 Unit °C °C V V V V V V V V 4 3 Notes 1 2 3 4, 5 22 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet Electrical Specifications 2.5 System Bus Signal Quality Specifications and Measurement Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal VCTERM voltage (or below GND), as shown in Table 2-3. The overshoot/ undershoot specifications limit transitions beyond VCTERM or GND due to the fast signal edge rates. The processor can be permanently damaged by repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (that is, if the overshoot/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse duration, and the activity factor (AF). 2.5.1 Overshoot/Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the processor, both are referenced to GND, as shown in Figure 2-3. It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently. Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in Table 2-13 through Table 2-17. These specifications must not be violated at any time, regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse duration. Provided that the magnitude of the overshoot/ undershoot is within the absolute maximum specifications, the pulse magnitude, duration, and activity factors must all be used to determine if the overshoot/ undershoot pulse is within specifications. Figure 2-3. System Bus Signal Waveform Exhibiting Overshoot/Undershoot Maximum Absolute Overshoot VMAX VCTERM Time-dependent Overshoot VREF VOL GND VMIN Maximum Absolute Undershoot Time-dependent Undershoot 000588 Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet 23 Electrical Specifications 2.5.2 Overshoot/Undershoot Pulse Duration Pulse duration describes the total time that an overshoot/undershoot event exceeds the overshoot/undershoot reference voltage (VCTERM/GND). The total time could encompass several oscillations above the reference voltage. Multiple overshoot/ undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration. Note: Oscillations below the reference voltage cannot be subtracted from the total overshoot/ undershoot pulse duration. 2.5.3 Activity Factor Activity factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any common clock signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For source synchronous signals (data, and associated strobes), the activity factor is in reference to the strobe edge. The highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. So, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other strobe cycle. The specifications provided in Table 2-14 through Table 2-17 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF