A80186

80186 80188 HIGH-INTEGRATION 16-BIT MICROPROCESSORS Y Integrated Feature Set Enhanced 8086-2 CPU Clock Generator 2 Independent DMA Channels Programmable Interrupt Controller 3 Programmable 16-bit Timers Programmable Memory and Peripheral Chip-Select Logic Programmable Wait State Generator Local Bus Controller Available in 10 MHz and 8 MHz Versions High-Performance Processor 4 Mbyte Sec Bus Bandwidth Interface 8 MHz (80186) 5 Mbyte Sec Bus Bandwidth Interface 10 MHz (80186) Y Direct Addressing Capability to 1 Mbyte of Memory and 64 Kbyte I O Completely Object Code Compatible with All Existing 8086 8088 Software 10 New Instruction Types Numerics Coprocessing Capability Through 8087 Interface Available in 68 Pin Plastic Leaded Chip Carrier (PLCC) Ceramic Pin Grid Array (PGA) Ceramic Leadless Chip Carrier (LCC) Available in EXPRESS Standard Temperature with Burn-In Extended Temperature Range ( b 40 C to a 85 C) Y Y Y Y Y Y 272430 – 1 Figure 1 Block Diagram Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata November 1994 COPYRIGHT INTEL CORPORATION 1995 Order Number 272430-002 1 80186 80188 High-Integration 16-Bit Microprocessors CONTENTS FUNCTIONAL DESCRIPTION Introduction CLOCK GENERATOR Oscillator Clock Generator READY Synchronization RESET Logic LOCAL BUS CONTROLLER Memory Peripheral Control Local Bus Arbitration Local Bus Controller and Reset PERIPHERAL ARCHITECTURE Chip-Select Ready Generation Logic DMA Channels Timers Interrupt Controller PAGE 9 9 9 9 9 9 9 9 10 10 10 10 10 11 11 12 CONTENTS ABSOLUTE MAXIMUM RATINGS D C CHARACTERISTICS A C CHARACTERISTICS EXPLANATION OF THE AC SYMBOLS WAVEFORMS EXPRESS EXECUTION TIMINGS INSTRUCTION SET SUMMARY FOOTNOTES REVISION HISTORY PAGE 15 15 16 18 19 25 26 27 32 33 2 2 80186 80188 Contacts Facing Down Contacts Facing Up 272430 – 2 Figure 2 Ceramic Leadless Chip Carrier (JEDEC Type A) Pins Facing Up Pins Facing Down 272430 – 3 Figure 3 Ceramic Pin Grid Array NOTE Pin names in parentheses apply to the 80188 3 3 80186 80188 Leads Facing Up Leads Facing Down 272430 – 4 Figure 4 Plastic Leaded Chip Carrier NOTE Pin names in parentheses apply to the 80188 4 4 80186 80188 Table 1 Pin Descriptions Symbol VCC VSS RESET Pin No 9 43 26 60 57 Type I I O Name and Function SYSTEM POWER a 5 volt power supply System Ground Reset Output indicates that the CPU is being reset and can be used as a system reset It is active HIGH synchronized with the processor clock and lasts an integer number of clock periods corresponding to the length of the RES signal Crystal Inputs X1 and X2 provide external connections for a fundamental mode parallel resonant crystal for the internal oscillator Instead of using a crystal an external clock may be applied to X1 while minimizing stray capacitance on X2 The input or oscillator frequency is internally divided by two to generate the clock signal (CLKOUT) Clock Output provides the system with a 50% duty cycle waveform All device pin timings are specified relative to CLKOUT An active RES causes the processor to immediately terminate its present activity clear the internal logic and enter a dormant state This signal may be asynchronous to the processor clock The processor begins fetching instructions approximately 6 clock cycles after RES is returned HIGH For proper initialization VCC must be within specifications and the clock signal must be stable for more than 4 clocks with RES held LOW RES is internally synchronized This input is provided with a Schmitt-trigger to facilitate power-on RES generation via an RC network TEST is examined by the WAIT instruction If the TEST input is HIGH when ‘‘WAIT’’ execution begins instruction execution will suspend TEST will be resampled until it goes LOW at which time execution will resume If interrupts are enabled while the processor is waiting for TEST interrupts will be serviced During power-up active RES is required to configure TEST as an input This pin is synchronized internally Timer Inputs are used either as clock or control signals depending upon the programmed timer mode These inputs are active HIGH (or LOW-to-HIGH transitions are counted) and internally synchronized Timer outputs are used to provide single pulse or continous waveform generation depending upon the timer mode selected DMA Request is asserted HIGH by an external device when it is ready for DMA Channel 0 or 1 to perform a transfer These signals are level-triggered and internally synchronized The Non-Maskable Interrupt input causes a Type 2 interrupt An NMI transition from LOW to HIGH is latched and synchronized internally and initiates the interrupt at the next instruction boundary NMI must be asserted for at least one clock The Non-Maskable Interrupt cannot be avoided by programming Maskable Interrupt Requests can be requested by activating one of these pins When configured as inputs these pins are active HIGH Interrupt Requests are synchronized internally INT2 and INT3 may be configured to provide activeLOW interrupt-acknowledge output signals All interrupt inputs may be configured to be either edge- or level-triggered To ensure recognition all interrupt requests must remain active until the interrupt is acknowledged When Slave Mode is selected the function of these pins changes (see Interrupt Controller section of this data sheet) X1 X2 59 58 I O CLKOUT RES 56 24 O I TEST 47 IO TMR IN 0 TMR IN 1 TMR OUT 0 TMR OUT 1 DRQ0 DRQ1 NMI 20 21 22 23 18 19 46 I I O O I I I INT0 INT1 SELECT INT2 INTA0 INT3 INTA1 IRQ 45 44 42 41 I I IO IO NOTE Pin names in parentheses apply to the 80188 5 5 80186 80188 Table 1 Pin Descriptions (Continued) Symbol A19 A18 A17 A16 S6 S5 S4 S3 Pin No 65 66 67 68 1 3 5 7 10 12 14 16 2 4 6 8 11 13 15 17 64 I I I I I I I I I I I I I I I I Type O O O O O O O O O O O O O O O O O O O O O Name and Function Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most significant address bits during T1 These signals are active HIGH During T2 T3 TW and T4 the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a DMA-initiated bus cycle During the same T-states S3 S4 and S5 are always LOW The status pins float during bus HOLD or RESET Address Data Bus signals constitute the time multiplexed memory or I O address (T1) and data (T2 T3 TW and T4) bus The bus is active HIGH A0 is analogous to BHE for the lower byte of the data bus pins D7 through D0 It is LOW during T1 when a byte is to be transferred onto the lower portion of the bus in memory or I O operations BHE does not exist on the 80188 as the data bus is only 8 bits wide AD15 (A15) AD14 (A14) AD13 (A13) AD12 (A12) AD11 (A11) AD10 (A10) AD9 (A9) AD8 (A8) AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 BHE S7 (S7) During T1 the Bus High Enable signal should be used to determine if data is to be enabled onto the most significant half of the data bus pins D15 –D8 BHE is LOW during T1 for read write and interrupt acknowledge cycles when a byte is to be transferred on the higher half of the bus The S7 status information is available during T2 T3 and T4 S7 is logically equivalent to BHE BHE S7 floats during HOLD On the 80188 S7 is high during normal operation BHE and A0 Encodings (80186 Only) BHE Value 0 0 1 1 A0 Value 0 1 0 1 Function Word Transfer Byte Transfer on upper half of data bus (D15–D8) Byte Transfer on lower half of data bus (D7 –D0) Reserved ALE QS0 61 O Address Latch Enable Queue Status 0 is provided by the processor to latch the address ALE is active HIGH Addresses are guaranteed to be valid on the trailing edge of ALE The ALE rising edge is generated off the rising edge of the CLKOUT immediately preceding T1 of the associated bus cycle effectively one-half clock cycle earlier than in the 8086 The trailing edge is generated off the CLKOUT rising edge in T1 as in the 8086 Note that ALE is never floated Write Strobe Queue Status 1 indicates that the data on the bus is to be written into a memory or an I O device WR is active for T2 T3 and TW of any write cycle It is active LOW and floats during HOLD When the processor is in queue status mode the ALE QS0 and WR QS1 pins provide information about processor instruction queue interaction QS1 0 0 1 1 QS0 0 1 1 0 Queue Operation No queue operation First opcode byte fetched from the queue Subsequent byte fetched from the queue Empty the queue WR QS1 63 O NOTE Pin names in parentheses apply to the 80188 6 6 80186 80188 Table 1 Pin Descriptions (Continued) Symbol RD QSMD Pin No 62 Type IO Name and Function Read Strobe is an active LOW signal which indicates that the processor is performing a memory or I O read cycle It is guaranteed not to go LOW before the A D bus is floated An internal pull-up ensures that RD is HIGH during RESET Following RESET the pin is sampled to determine whether the processor is to provide ALE RD and WR or queue status information To enable Queue Status Mode RD must be connected to GND RD will float during bus HOLD Asynchronous Ready informs the processor that the addressed memory space or I O device will complete a data transfer The ARDY pin accepts a rising edge that is asynchronous to CLKOUT and is active HIGH The falling edge of ARDY must be synchronized to the processor clock Connecting ARDY HIGH will always assert the ready condition to the CPU If this line is unused it should be tied LOW to yield control to the SRDY pin Synchronous Ready informs the processor that the addressed memory space or I O device will complete a data transfer The SRDY pin accepts an active-HIGH input synchronized to CLKOUT The use of SRDY allows a relaxed system timing over ARDY This is accomplished by elimination of the one-half clock cycle required to internally synchronize the ARDY input signal Connecting SRDY high will always assert the ready condition to the CPU If this line is unused it should be tied LOW to yield control to the ARDY pin LOCK output indicates that other system bus masters are not to gain control of the system bus while LOCK is active LOW The LOCK signal is requested by the LOCK prefix instruction and is activated at the beginning of the first data cycle associated with the instruction following the LOCK prefix It remains active until the completion of that instruction No instruction prefetching will occur while LOCK is asserted When executing more than one LOCK instruction always make sure there are 6 bytes of code between the end of the first LOCK instruction and the start of the second LOCK instruction LOCK is driven HIGH for one clock during RESET and then floated Bus cycle status S0 –S2 are encoded to provide bus-transaction information Bus Cycle Status Information S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge Read I O Write I O Halt Instruction Fetch Read Data from Memory Write Data to Memory Passive (no bus cycle) ARDY 55 I SRDY 49 I LOCK 48 O S0 S1 S2 52 53 54 O O O The status pins float during HOLD S2 may be used as a logical M IO indicator and S1 as a DT R indicator NOTE Pin names in parentheses apply to the 80188 7 7 80186 80188 Table 1 Pin Descriptions (Continued) Symbol HOLD HLDA Pin No 50 51 Type I O Name and Function HOLD indicates that another bus master is requesting the local bus The HOLD input is active HIGH HOLD may be asynchronous with respect to the processor clock The processor will issue a HLDA (HIGH) in response to a HOLD request at the end of T4 or Ti Simultaneous with the issuance of HLDA the processor will float the local bus and control lines After HOLD is detected as being LOW the processor will lower HLDA When the processor needs to run another bus cycle it will again drive the local bus and control lines Upper Memory Chip Select is an active LOW output whenever a memory reference is made to the defined upper portion (1K – 256K block) of memory This line is not floated during bus HOLD The address range activating UCS is software programmable Lower Memory Chip Select is active LOW whenever a memory reference is made to the defined lower portion (1K – 256K) of memory This line is not floated during bus HOLD The address range activating LCS is software programmable Mid-Range Memory Chip Select signals are active LOW when a memory reference is made to the defined mid-range portion of memory (8K – 512K) These lines are not floated during bus HOLD The address ranges activating MCS0 –3 are software programmable Peripheral Chip Select signals 0 – 4 are active LOW when a reference is made to the defined peripheral area (64 Kbyte I O space) These lines are not floated during bus HOLD The address ranges activating PCS0 – 4 are software programmable Peripheral Chip Select 5 or Latched A1 may be programmed to provide a sixth peripheral chip select or to provide an internally latched A1 signal The address range activating PCS5 is software-programmable PCS5 A1 does not float during bus HOLD When programmed to provide latched A1 this pin will retain the previously latched value during HOLD Peripheral Chip Select 6 or Latched A2 may be programmed to provide a seventh peripheral chip select or to provide an internally latched A2 signal The address range activating PCS6 is software programmable PCS6 A2 does not float during bus HOLD When programmed to provide latched A2 this pin will retain the previously latched value during HOLD Data Transmit Receive controls the direction of data flow through an external data bus transceiver When LOW data is transferred to the processsor When HIGH the processor places write data on the data bus Data Enable is provided as a data bus transceiver output enable DEN is active LOW during each memory and I O access DEN is HIGH whenever DT R changes state During RESET DEN is driven HIGH for one clock then floated DEN also floats during HOLD UCS 34 O LCS 33 O MCS0 MCS1 MCS2 MCS3 PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 A1 38 37 36 35 25 27 28 29 30 31 O O O O O O O O O O PCS6 A2 32 O DT R 40 O DEN 39 O NOTE Pin names in parentheses apply to the 80188 8 8 80186 80188 Intel recommends the following values for crystal selection parameters Temperature Range 0 to 70 C ESR (Equivalent Series Resistance) 30X max C0 (Shunt Capacitance of Crystal) 7 0 pf max 20 pf g 2 pf C1 (Load Capacitance) Drive Level 1 mW max FUNCTIONAL DESCRIPTION Introduction The following Functional Description describes the base architecture of the 80186 The 80186 is a very high integration 16-bit microprocessor It combines 15–20 of the most common microprocessor system components onto one chip while providing twice the performance of the standard 8086 The 80186 is object code compatible with the 8086 8088 microprocessors and adds 10 new instruction types to the 8086 8088 instruction set For more detailed information on the architecture please refer to the 80C186XL 80C188XL User’s Manual The 80186 and the 80186XL devices are functionally and register compatible Clock Generator The clock generator provides the 50% duty cycle processor clock for the processor It does this by dividing the oscillator output by 2 forming the symmetrical clock If an external oscillator is used the state of the clock generator will change on the falling edge of the oscillator signal The CLKOUT pin provides the processor clock signal for use outside the device This may be used to drive other system components All timings are referenced to the output clock CLOCK GENERATOR The processor provides an on-chip clock generator for both internal and external clock generation The clock generator features a crystal oscillator a divideby-two counter synchronous and asynchronous ready inputs and reset circuitry READY Synchronization The processor provides both synchronous and asynchronous ready inputs In addition the processor as part of the integrated chip-select logic has the capability to program WAIT states for memory and peripheral blocks Oscillator The oscillator circuit is designed to be used with a parallel resonant fundamental mode crystal This is used as the time base for the processor The crystal frequency selected will be double the CPU clock frequency Use of an LC or RC circuit is not recommended with this oscillator If an external oscillator is used it can be connected directly to the input pin X1 in lieu of a crystal The output of the oscillator is not directly available outside the processor The recommended crystal configuration is shown in Figure 5 RESET Logic The processor provides both a RES input pin and a synchronized RESET output pin for use with other system components The RES input pin is provided with hysteresis in order to facilitate power-on Reset generation via an RC network RESET output is guaranteed to remain active for at least five clocks given a RES input of at least six clocks LOCAL BUS CONTROLLER The processor provides a local bus controller to generate the local bus control signals In addition it employs a HOLD HLDA protocol for relinquishing the local bus to other bus masters It also provides outputs that can be used to enable external buffers and to direct the flow of data on and off the local bus x 80186-10 (10 MHz) 20 80186 (8 MHz) 16 272430 – 5 Figure 5 Recommended Crystal Configuration 9 9 80186 80188 either memory or I O space Internal logic will recognize control block addresses and respond to bus cycles During bus cycles to internal registers the bus controller will signal the operation externally (i e the RD WR status address data etc lines will be driven as in a normal bus cycle) but D15–0 (D7–0) SRDY and ARDY will be ignored The base address of the control block must be on an even 256-byte boundary (i e the lower 8 bits of the base address are all zeros) The control block base address is programmed by a 16-bit relocation register contained within the control block at offset FEH from the base address of the control block It provides the upper 12 bits of the base address of the control block In addition to providing relocation information for the control block the relocation register contains bits which place the interrupt controller into Slave Mode and cause the CPU to interrupt upon encountering ESC instructions Memory Peripheral Control The processor provides ALE RD and WR bus control signals The RD and WR signals are used to strobe data from memory or I O to the processor or to strobe data from the processor to memory or I O The ALE line provides a strobe to latch the address when it is valid The local bus controller does not provide a memory I O signal If this is required use the S2 signal (which will require external latching) make the memory and I O spaces nonoverlapping or use only the integrated chip-select circuitry Local Bus Arbitration The processor uses a HOLD HLDA system of local bus exchange This provides an asynchronous bus exchange mechanism This means multiple masters utilizing the same bus can operate at separate clock frequencies The processor provides a single HOLD HLDA pair through which all other bus masters may gain control of the local bus External circuitry must arbitrate which external device will gain control of the bus when there is more than one alternate local bus master When the processor relinquishes control of the local bus it floats DEN RD WR S0 –S2 LOCK AD0–AD15 (AD0–AD7) A16–A19 (A8–A19) BHE (S7) and DT R to allow another master to drive these lines directly Chip-Select Ready Generation Logic The processor contains logic which provides programmable chip-select generation for both memories and peripherals In addition it can be programmed to provide READY (or WAIT state) generation It can also provide latched address bits A1 and A2 The chip-select lines are active for all memory and I O cycles in their programmed areas whether they be generated by the CPU or by the integrated DMA unit MEMORY CHIP SELECTS The processor provides 6 memory chip select outputs for 3 address areas upper memory lower memory and midrange memory One each is provided for upper memory and lower memory while four are provided for midrange memory UPPER MEMORY CS The processor provides a chip select called UCS for the top of memory The top of memory is usually used as the system memory because after reset the processor begins executing at memory location FFFF0H LOWER MEMORY CS The processor provides a chip select for low memory called LCS The bottom of memory contains the interrupt vector table starting at location 00000H Local Bus Controller and Reset During RESET the local bus controller will perform the following action  Drive DEN RD and WR HIGH for one clock cycle then float NOTE RD is also provided with an internal pull-up device to prevent the processor from inadvertently entering Queue Status Mode during RESET  Drive S0 –S2 to the inactive state (all HIGH) and then float  Drive LOCK HIGH and then float  Float AD0–15 (AD0–AD7) A16–19 (A8–A19) BHE (S7) DT R  Drive ALE LOW (ALE is never floated)  Drive HLDA LOW PERIPHERAL ARCHITECTURE All of the integrated peripherals are controlled by 16-bit registers contained within an internal 256-byte control block The control block may be mapped into 10 10 80186 80188 The lower limit of memory defined by this chip select is always 0H while the upper limit is programmable By programming the upper limit the size of the memory block is defined MID-RANGE MEMORY CS The processor provides four MCS lines which are active within a user-locatable memory block This block can be located within the 1-Mbyte memory address space exclusive of the areas defined by UCS and LCS Both the base address and size of this memory block are programmable PERIPHERAL CHIP SELECTS The processor can generate chip selects for up to seven peripheral devices These chip selects are active for seven contiguous blocks of 128 bytes above a programmable base address The base address may be located in either memory or I O space Seven CS lines called PCS0 –6 are generated by the processor PCS5 and PCS6 can also be programmed to provide latched address bits A1 and A2 If so programmed they cannot be used as peripheral selects These outputs can be connected directly to the A0 and A1 pins used for selecting internal registers of 8-bit peripheral chips READY GENERATION LOGIC The processor can generate a READY signal internally for each of the memory or peripheral CS lines The number of WAIT states to be inserted for each peripheral or memory is programmable to provide 0–3 wait states for all accesses to the area for which the chip select is active In addition the processor may be programmed to either ignore external READY for each chip-select range individually or to factor external READY with the integrated ready generator CHIP SELECT READY LOGIC AND RESET Upon RESET the Chip-Select Ready Logic will perform the following actions DMA CHANNELS AND RESET Upon RESET the DMA channels will perform the following actions  Upon leaving RESET the UCS line will be programmed to provide chip selects to a 1K block with the accompanying READY control bits set at 011 to insert 3 wait states in conjunction with external READY (i e UMCS resets to FFFBH)  No other chip select or READY control registers have any predefined values after RESET They will not become active until the CPU accesses their control registers Both the PACS and MPCS registers must be accessed before the PCS lines will become active DMA Channels The DMA controller provides two independent DMA channels Data transfers can occur between memory and I O spaces (e g Memory to I O) or within the same space (e g Memory to Memory or I O to I O) Data can be transferred either in bytes or in words (80186 only) to or from even or odd addresses Each DMA channel maintains both a 20-bit source and destination pointer which can be optionally incremented or decremented after each data transfer (by one or two depending on byte or word transfers) Each data transfer consumes 2 bus cycles (a minimum of 8 clocks) one cycle to fetch data and the other to store data This provides a maximum data transfer rate of 1 25 Mword sec or 2 5 Mbytes sec at 10 MHz (half of this rate for the 80188)  The Start Stop bit for each channel will be reset to STOP  Any transfer in progress is aborted Timers The processor provides three internal 16-bit programmable timers Two of these are highly flexible and are connected to four external pins (2 per timer) They can be used to count external events time external events generate nonrepetitive waveforms etc The third timer is not connected to any external pins and is useful for real-time coding and time delay applications In addition the third timer can be used as a prescaler to the other two or as a DMA request source  All chip-select outputs will be driven HIGH 11 11 80186 80188 TIMERS AND RESET Upon RESET the Timers will perform the following actions INTERRUPT CONTROLLER AND RESET Upon RESET the interrupt controller will perform the following actions  All SFNM bits reset to 0 implying Fully Nested Mode  All PR bits in the various control registers set to 1 This places all sources at lowest priority (level 111)  All EN (Enable) bits are reset preventing timer counting  For Timers 0 and 1 the RIU bits are reset to zero and the ALT bits are set to one This results in the Timer Out pins going high  All LTM bits reset to 0 resulting in edge-sense Interrupt Controller The processor can receive interrupts from a number of sources both internal and external The internal interrupt controller serves to merge these requests on a priority basis for individual service by the CPU Internal interrupt sources (Timers and DMA channels) can be disabled by their own control registers or by mask bits within the interrupt controller The interrupt controller has its own control register that sets the mode of operation for the controller mode      All Interrupt Service bits reset to 0 All Interrupt Request bits reset to 0 All MSK (Interrupt Mask) bits set to 1 (mask) All C (Cascade) bits reset to 0 (non-Cascade) All PRM (Priority Mask) bits set to 1 implying no levels masked  Initialized to Master Mode 12 12 80186 80188 272430 – 6 NOTE Pin names in parenthesis apply to 80188 (1) BHE does not exist on the 80188 this is only required for a 16-bit data bus Figure 6 Typical 80186 80188 Computer 13 13 80186 80188 272430 – 7 NOTE Pin names in parentheses apply to 80188 (1) BHE does not exist on the 80188 this is only required for a 16-bit data bus Figure 7 Typical 80186 80188 Multi-Master Bus Interface 14 14 80186 80188 ABSOLUTE MAXIMUM RATINGS Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to Ground Power Dissipation 0 C to 70 C b 65 C to a 150 C b 1 0V to a 7V NOTICE This is a production data sheet The specifications are subject to change without notice 3W WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability D C CHARACTERISTICS Symbol VIL VIH VIH1 VOL VOH ICC Parameter Input Low Voltage (TA e 0 C to a 70 C VCC e 5V g 10%) Applicable to 8 MHz and 10 MHz devices Min b0 5 Max a0 8 Units V V V V V Test Conditions Input High Voltage (All except X1 and (RES) Input High Voltage (RES) Output Low Voltage Output High Voltage Power Supply Current 20 30 VCC a 0 5 VCC a 0 5 0 45 Ia e 2 5 mA for S0 –S2 Ia e 2 0 mA for all other Outputs Ioa e b 400 mA TA e b 40 C TA e 0 C TA e a 70 C 0V k VIN k VCC 0 45V k VOUT k VCC Ia e 4 0 mA Ioa e b 200 mA 24 600 550 415 mA mA mA mA mA V V ILI ILO VCLO VCHO VCLI VCHI CIN CIO Input Leakage Current Output Leakage Current Clock Output Low Clock Output High Clock Input Low Voltage Clock Input High Voltage Input Capacitance I O Capacitance 40 b0 5 g 10 g 10 06 06 VCC a 1 0 10 20 V V pF pF 39 For extended temperature parts only 15 15 80186 80188 A C CHARACTERISTICS Symbol TDVCL TCLDX TARYHCH Parameter Data in Setup (A D) Data in Hold (A D) Asynchronous Ready (ARDY) Active Setup Time(1) (TA e 0 C to a 70 C VCC e 5V g 10%) Timing Requirements All Timings Measured At 1 5V Unless Otherwise Noted 8 MHz Min 20 10 20 Max 10 MHz Min 15 8 15 Max ns ns ns Units Test Conditions TARYLCL TCLARX TARYCHL TSRYCL TCLSRY THVCL TINVCH TINVCL ARDY Inactive Setup Time ARDY Hold Time Asynchronous Ready Inactive Hold Time Synchronous Ready (SRDY) Transition Setup Time(2) SRDY Transition Hold Time(2) HOLD Setup(1) INTR NMI TEST TIM IN Setup(1) DRQ0 DRQ1 Setup(1) 35 15 15 20 15 25 25 25 25 15 15 20 15 20 25 20 ns ns ns ns ns ns ns ns Master Interface Timing Responses TCLAV TCLAX TCLAZ TCHCZ TCHCV TLHLL TCHLH TCHLL TLLAX TCLDV TCLDOX TWHDX TCVCTV TCHCTV TCVCTX TCVDEX Address Valid Delay Address Hold Address Float Delay Command Lines Float Delay Command Lines Valid Delay (after Float) ALE Width ALE Active Delay ALE Inactive Delay Address Hold from ALE Inactive Data Valid Delay Data Hold Time Data Hold after WR Control Active Delay 1 Control Active Delay 2 Control Inactive Delay DEN Inactive Delay (Non-Write Cycle) TCHCL b 25 10 10 TCLCL b 40 5 10 5 10 50 55 55 70 44 TCLCL b 35 35 35 TCHCL b 20 10 10 TCLCL b 34 5 10 5 10 40 44 44 56 40 5 10 TCLAX 35 45 55 TCLCL b 30 30 30 55 5 10 TCLAX 30 40 45 44 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL e 20 pF–200 pF all Outputs (Except TCLTMV) 8 MHz and 10 MHz 1 To guarantee recognition at next clock 2 To guarantee proper operation 16 16 80186 80188 A C CHARACTERISTICS (TA e 0 C to a 70 C VCC e 5V g 10%) (Continued) Master Interface Timing Responses (Continued) Symbol TAZRL TCLRL TCLRH TRHAV TCLHAV TRLRH TWLWH TAVLL TCHSV TCLSH TCLTMV TCLRO TCHQSV TCHDX TAVCH TCLLV Parameter Address Float to RD Active RD Active Delay RD Inactive Delay RD Inactive to Address Active HLDA Valid Delay RD Width WR Width Address Valid to ALE Low Status Active Delay Status Inactive Delay Timer Output Delay Reset Delay Queue Status Delay Status Hold Time Address Valid to Clock High LOCK Valid Invalid Delay 10 10 5 65 8 MHz Min 0 10 10 TCLCL b 40 5 2TCLCL b 50 2TCLCL b 40 TCLCH b 25 10 10 55 65 60 60 35 10 10 5 60 50 70 55 Max 10 MHz Min 0 10 10 TCLCL b 40 5 2TCLCL b 46 2TCLCL b 34 TCLCH b 19 10 10 45 50 48 48 28 40 56 44 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 pF max 8 10 MHz Units Test Conditions Chip-Select Timing Responses TCLCSV TCXCSX TCHCSX Chip-Select Active Delay Chip-Select Hold from Command Inactive Chip-Select Inactive Delay 35 5 35 66 35 5 32 45 ns ns ns CLKIN Requirements TCKIN TCKHL TCKLH TCLCK TCHCK CLKIN Period CLKIN Fall Time CLKIN Rise Time CLKIN Low Time CLKIN High Time 25 25 62 5 250 10 10 20 20 50 250 10 10 ns ns ns ns ns 3 5 to 1 0V 1 0 to 3 5V 1 5V 1 5V CLKOUT Timing (200 pF load) TCICO TCLCL TCLCH TCHCL TCH1CH2 TCL2CL1 CLKIN to CLKOUT Skew CLKOUT Period CLKOUT Low Time CLKOUT High Time CLKOUT Rise Time CLKOUT Fall Time 125 TCLCL b 7 5 TCLCL b 7 5 15 15 50 500 100 TCLCL b 6 0 TCLCL b 6 0 12 12 25 500 ns ns ns ns ns ns 1 5V 1 5V 1 0 to 3 5V 3 5 to 1 0V 17 17 80186 80188 EXPLANATION OF THE AC SYMBOLS Each timing symbol has from 5 to 7 characters The first character is always a ‘‘T’’ (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A ARY C CK CS CT D DE H Address Asynchronous Ready Input Clock Output Clock Input Chip Select Control (DT R DEN ) Data Input DEN Logic Level High IN L O QS R S SRY V W X Z Input (DRQ0 TIM0 ) Logic Level Low or ALE Output Queue Status (QS1 QS2) RD signal RESET signal Status (S0 S1 S2) Synchronous Ready Input Valid WR Signal No Longer a Valid Logic Level Float Examples TCLAV TCHLH TCLCSV Time from Clock low to Address valid Time from Clock high to ALE high Time from Clock low to Chip Select valid 18 18 80186 80188 WAVEFORMS MAJOR CYCLE TIMING 272430 – 8 NOTE Pin names in parentheses apply to the 80188 19 19 80186 80188 WAVEFORMS (Continued) MAJOR CYCLE TIMING (Continued) NOTES 1 INTA occurs one clock later in slave mode 2 Status inactive just prior to T4 3 If latched A1 and A2 are selected instead of PCS5 and PCS6 only TCLCSV is applicable 4 Pin names in parentheses apply to the 80188 272430 – 9 20 20 80186 80188 WAVEFORMS (Continued) 272430 – 10 272430 – 11 272430 – 12 21 21 80186 80188 WAVEFORMS (Continued) 272430 – 13 272430 – 14 22 22 80186 80188 WAVEFORMS (Continued) READY TIMING 272430 – 15 23 23 80186 80188 272430 – 16 NOTE Pin names in parentheses apply to the 80188 24 24 80186 80188 WAVEFORMS (Continued) 272430 – 17 EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the microprocessor EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards The EXPRESS program includes the commercial standard temperature range with burn-in and an extended temperature range without burn-in With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 C to a 70 C With the extended temperature range option operational characteristics are guaranteed over the range of b 40 C to a 85 C The optional burn-in is dynamic for a minimum time of 160 hours at a 125 C with VCC e 5 5V g 0 25V following guidelines in MIL-STD-883 Method 1015 Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number The prefixes are listed in Table 2 All A C and D C specifications not mentioned in this section are the same for both commercial and EXPRESS parts Table 2 Prefix Identification Prefix A N R TA QA QR Package Type PGA PLCC LCC PGA PGA LCC Temperature Range Commercial Commercial Commercial Extended Commercial Commercial Burn-In No No No No Yes Yes NOTE Not all package temperature range speed combinations are available 25 25 80186 80188 All instructions which involve memory accesses can also require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address The 80186 has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time Therefore actual program execution time will not be substantially greater than that derived from adding the instruction timings shown The 80188 is noticeably limited in its performance relative to the execution unit A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time Therefore actual program execution time may be substantially greater than that derived from adding the instruction timings shown EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions The following instruction timings represent the minimum execution time in clock cycles for each instruction The timings given are based on the following assumptions  The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed  No wait states or bus HOLDS occur  All word-data is located on even-address boundaries 26 26 80186 80188 INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV e Move Register to Register Memory Register memory to register Immediate to register memory Immediate to register Memory to accumulator Accumulator to memory Register memory to segment register Segment register to register memory PUSH e Push Memory Register Segment register Immediate PUSHA e Push All POP e Pop Memory Register Segment register POPA e Pop All XCHG e Exchange Register memory with register Register with accumulator IN e Input from Fixed port Variable port OUT e Output to Fixed port Variable port XLAT e Translate byte to AL LEA e Load EA to register LDS e Load pointer to DS LES e Load pointer to ES LAHF e Load AH with flags SAHF e Store AH into flags PUSHF e Push flags POPF e Pop flags 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r m mod reg r m mod reg r m (mod i 11) (mod i 11) port 9 7 11 6 18 18 2 3 9 8 9 7 15 6 26 26 2 3 13 12 1110010w 1110110w port 10 8 10 8 1000011w 1 0 0 1 0 reg mod reg r m 4 17 3 4 17 3 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 01100001 (reg i 01) mod 0 0 0 r m 20 10 8 51 24 14 12 83 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 011010s0 01100000 data data if s e 0 mod 1 1 0 r m 16 10 9 10 36 20 14 13 14 68 1000100w 1000101w 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 mod reg r m mod reg r m mod 000 r m data addr-low addr-low mod 0 reg r m mod 0 reg r m data data if w e 1 addr-high addr-high data if w e 1 2 12 29 12 13 34 8 9 29 2 11 2 12 29 12 13 34 8 9 2 13 2 15 8 16-bit 8 16-bit Format 80186 Clock Cycles 80188 Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer 27 27 80186 80188 INSTRUCTION SET SUMMARY (Continued) Function DATA TRANSFER (Continued) SEGMENT e Segment Override CS SS DS ES ARITHMETIC ADD e Add Reg memory with register to either Immediate to register memory Immediate to accumulator ADC e Add with carry Reg memory with register to either Immediate to register memory Immediate to accumulator INC e Increment Register memory Register SUB e Subtract Reg memory and register to either Immediate from register memory Immediate from accumulator SBB e Subtract with borrow Reg memory and register to either Immediate from register memory Immediate from accumulator DEC e Decrement Register memory Register CMP e Compare Register memory with register Register with register memory Immediate with register memory Immediate with accumulator NEG e Change sign register memory AAA e ASCII adjust for add DAA e Decimal adjust for add AAS e ASCII adjust for subtract DAS e Decimal adjust for subtract MUL e Multiply (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word 0011101w 0011100w 100000sw 0011110w 1111011w 00110111 00100111 00111111 00101111 1111011w mod 100 r m 26–28 35–37 32–34 41–43 26–28 35–37 32–34 41–43 mod reg r m mod reg r m mod 1 1 1 r m data mod 0 1 1 r m data data if w e 1 data if s w e 01 3 10 3 10 3 10 34 3 10 8 4 7 4 3 10 3 10 3 10 34 3 10 8 4 7 4 8 16-bit 1111111w 0 1 0 0 1 reg mod 0 0 1 r m 3 15 3 3 15 3 000110dw 100000sw 0001110w mod reg r m mod 0 1 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 001010dw 100000sw 0010110w mod reg r m mod 1 0 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 1111111w 0 1 0 0 0 reg mod 0 0 0 r m 3 15 3 3 15 3 000100dw 100000sw 0001010w mod reg r m mod 0 1 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 000000dw 100000sw 0000010w mod reg r m mod 0 0 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 00101110 00110110 00111110 00100110 2 2 2 2 2 2 2 2 Format 80186 Clock Cycles 80188 Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer 28 28 80186 80188 INSTRUCTION SET SUMMARY (Continued) Function ARITHMETIC (Continued) IMUL e Integer multiply (signed) Register-Byte Register-Word Memory-Byte Memory-Word IMUL e Integer Immediate multiply (signed) DIV e Divide (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word IDIV e Integer divide (signed) Register-Byte Register-Word Memory-Byte Memory-Word AAM e ASCII adjust for multiply AAD e ASCII adjust for divide CBW e Convert byte to word CWD e Convert word to double word LOGIC Shift Rotate Instructions Register Memory by 1 Register Memory by CL Register Memory by Count 1101000w 1101001w 1100000w mod TTT r m mod TTT r m mod TTT r m TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL SAL 101 SHR 111 SAR AND e And Reg memory and register to either Immediate to register memory Immediate to accumulator TEST e And function to flags no result Register memory and register Immediate data and register memory Immediate data and accumulator OR e Or Reg memory and register to either Immediate to register memory Immediate to accumulator 000010dw 1000000w 0000110w mod reg r m mod 0 0 1 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit 1000010w 1111011w 1010100w mod reg r m mod 0 0 0 r m data data data if w e 1 data if w e 1 3 10 4 10 34 3 10 4 10 34 8 16-bit 001000dw 1000000w 0010010w mod reg r m mod 1 0 0 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit count 2 15 2 15 11010100 11010101 10011000 10011001 00001010 00001010 1111011w mod 1 1 1 r m 44–52 53–61 50–58 59–67 19 15 2 4 44–52 53–61 50–58 59–67 19 15 2 4 011010s1 mod reg r m data data if s e 0 1111011w mod 1 0 1 r m 25–28 34–37 31–34 40–43 22–25 29–32 25–28 34–37 31–34 40–43 22–25 29–32 Format 80186 Clock Cycles 80188 Clock Cycles Comments 1111011w mod 1 1 0 r m 29 38 35 44 29 38 35 44 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer 29 29 80186 80188 INSTRUCTION SET SUMMARY (Continued) Function LOGIC (Continued) XOR e Exclusive or Reg memory and register to either Immediate to register memory Immediate to accumulator NOT e Invert register memory STRING MANIPULATION MOVS e Move byte word CMPS e Compare byte word SCAS e Scan byte word LODS e Load byte wd to AL AX STOS e Store byte wd from AL AX INS e Input byte wd from DX port OUTS e Output byte wd to DX port 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 14 22 15 12 10 14 14 14 22 15 12 10 14 14 001100dw 1000000w 0011010w 1111011w mod reg r m mod 1 1 0 r m data mod 0 1 0 r m data data if w e 1 data if w e 1 3 10 4 16 34 3 10 3 10 4 16 34 3 10 8 16-bit Format 80186 Clock Cycles 80188 Clock Cycles Comments Repeated by count in CX (REP REPE REPZ REPNE REPNZ) MOVS e Move string CMPS e Compare string SCAS e Scan string LODS e Load string STOS e Store string INS e Input string OUTS e Output string CONTROL TRANSFER CALL e Call Direct within segment Register memory indirect within segment Direct intersegment 11101000 11111111 disp-low mod 0 1 0 r m disp-high 15 13 19 19 17 27 11110010 1111001z 1111001z 11110010 11110010 11110010 11110010 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 10011010 segment offset segment selector 23 31 Indirect intersegment JMP e Unconditional jump Short long Direct within segment Register memory indirect within segment Direct intersegment 11111111 mod 0 1 1 r m (mod i 11) 38 54 11101011 11101001 11111111 disp-low disp-low mod 1 0 0 r m disp-high 14 14 11 17 14 14 11 21 11101010 segment offset segment selector 14 14 Indirect intersegment 11111111 mod 1 0 1 r m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer 30 30 80186 80188 INSTRUCTION SET SUMMARY (Continued) Function CONTROL TRANSFER (Continued) RET e Return from CALL Within segment Within seg adding immed to SP Intersegment Intersegment adding immediate to SP JE JZ e Jump on equal zero JL JNGE e Jump on less not greater or equal JLE JNG e Jump on less or equal not greater JB JNAE e Jump on below not above or equal JBE JNA e Jump on below or equal not above JP JPE e Jump on parity parity even JO e Jump on overflow JS e Jump on sign JNE JNZ e Jump on not equal not zero JNL JGE e Jump on not less greater or equal JNLE JG e Jump on not less or equal greater JNB JAE e Jump on not below above or equal JNBE JA e Jump on not below or equal above JNP JPO e Jump on not par par odd JNO e Jump on not overflow JNS e Jump on not sign JCXZ e Jump on CX zero LOOP e Loop CX times LOOPZ LOOPE e Loop while zero equal LOOPNZ LOOPNE e Loop while not zero equal ENTER e Enter Procedure Le0 Le1 Ll1 LEAVE e Leave Procedure INT e Interrupt Type specified Type 3 INTO e Interrupt on overflow 11001101 11001100 11001110 type 47 45 48 4 47 45 48 4 if INT taken if INT not taken 11001001 11000011 11000010 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110 000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100011 11100010 11100001 11100000 11001000 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-low data-high L 15 25 22 a 16(n b 1) 8 19 29 26 a 20(n b 1) 8 data-high data-low data-high 16 18 22 25 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 20 22 30 33 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 LOOP not taken LOOP taken JMP not taken JMP taken Format 80186 Clock Cycles 80188 Clock Cycles Comments IRET e Interrupt return BOUND e Detect value out of range 11001111 01100010 mod reg r m 28 33–35 28 33–35 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer 31 31 80186 80188 INSTRUCTION SET SUMMARY (Continued) Function PROCESSOR CONTROL CLC e Clear carry CMC e Complement carry STC e Set carry CLD e Clear direction STD e Set direction CLI e Clear interrupt STI e Set interrupt HLT e Halt WAIT e Wait LOCK e Bus lock prefix ESC e Processor Extension Escape 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 11011TTT mod LLL r m 2 2 2 2 2 2 2 2 6 2 6 2 2 2 2 2 2 2 2 6 3 6 if TEST e 0 Format 80186 Clock Cycles 80188 Clock Cycles Comments (TTT LLL are opcode to processor extension) NOP e No Operation 10010000 3 3 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer FOOTNOTES The Effective Address (EA) of the memory operand is computed according to the mod and r m fields if mod e 11 then r m is treated as REG field if mod e 00 then DISP e 0 disp-low and disp-high are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits disp-high is absent if mod e 10 then DISP e disp-high disp-low if r m e 000 then EA e (BX) a (SI) a DISP if r m e 001 then EA e (BX) a (DI) a DISP if r m e 010 then EA e (BP) a (SI) a DISP if r m e 011 then EA e (BP) a (DI) a DISP if r m e 100 then EA e (SI) a DISP if r m e 101 then EA e (DI) a DISP if r m e 110 then EA e (BP) a DISP if r m e 111 then EA e (BX) a DISP reg is assigned according to the following reg 00 01 10 11 Segment Register ES CS SS DS REG is assigned according to the following table 16-Bit (w e 1) 000 AX 001 CX 010 DX 011 BX 100 SP 101 BP 110 SI 111 DI 8-Bit (w e 0) 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH DISP follows 2nd byte of instruction (before data if required) except if mod e 00 and r m e 110 then EA e disp-high disp-low EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenever appropriate Segment Override Prefix 0 0 1 reg 1 1 0 The physical addresses of all operands addressed by the BP register are computed using the SS segment register The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment which may not be overridden 32 32 80186 80188 REVISION HISTORY This data sheet replaces the following data sheets 210706-011 80188 210451-011 80186 33 33