AN80196CB

87C196CA 87C196CB 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2 0 Automotive Y High Performance CHMOS 16-Bit CPU (up to 20 MHz Operation) Register-Register Architecture Up to 56 Kbytes of On-Chip EPROM Up to 1 5 Kbyte of On-Chip Register RAM Up to 512 Bytes of Additional RAM (Code RAM) Up to 16 Mbyte Linear Address Space Supports CAN (Controller Area Network) Specification 2 0 15 Message Objects of 8 Bytes Data Length 10-Bit A D with Sample Hold 38 Prioritized Interrupts Up to Seven 8-Bit (60) I O Ports Full Duplex Serial Port (SIO) with Dedicated Baudrate Generator Y Full Duplex Synchronous Serial I O Port (SSIO) Interprocessor Communication Slave Port Selectable Bus Timing Modes for Flexible Interfacing Oscillator Fail Detection Circuitry High Speed Peripheral Transaction Server (PTS) Two Dedicated 16-Bit High-Speed Compare Registers High Speed Capture Compare (EPA) Two Flexible 16-Bit Timer Counters Flexible 8- 16-Bit External Bus (Programmable) Programmable Bus (HLD HLDA) 1 4 ms 16 x 16 Multiply 2 4 ms 32 16 Divide Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y b 40 C to a 125 C Ambient Device 87C196CB 87C196CB 87C196CA Pins Package 84-Pin PLCC 100-Pin QFP 68-Pin PLCC EPROM 56K 56K 32K Reg RAM 1 5K 1 5K 1 0K Code RAM 512b 512b 256b IO 56 60 38 EPA 10 10 6 SIO Y Y Y SSIO Y Y Y CAN Y Y Y AD 8 8 6 Address Space 1 Mbyte 16 Mbyte 64 Kbyte The 87C196CA CB are new members of the MCS 96 microcontroller family These devices are based upon the MCS 96 Kx Jx microcontroller product families with enhancements ideal for automotive and industrial applications The CA CB are the first devices in the Kx family to support networking through the integration of the CAN 2 0 (Controller Area Network) peripheral on-chip The 87C196CB offers the highests memory density of the MCS 96 microcontroller family with 56K of on-chip EPROM 1 5K of on-chip register RAM and 512 bytes of additional RAM (Code RAM) In addition the 87C196CB provides up to 16 Mbyte of Linear Address Space The 87C196CA is a sub-set of the CB offering 32K of on-chip EPROM up to 1 0K of on-chip register RAM and 256 bytes of additional RAM (Code RAM) Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 April 1996 Order Number 272405-004 87C196CA 87C196CB The MCS 96 microcontroller family members are all high-performance microcontrollers with a 16-bit CPU The 87C196CB is composed of the high-speed (20 MHz) macrocore with up to 16 Mbyte linear address space 56 Kbytes of program EPROM up to 1 5 Kbytes of register RAM and up to 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space It supports the high-speed serial communications protocol CAN 2 0 with 15 message objects of 8 bytes data length an 8-channel 10-bit 3 LSB analog to digital converter with programmable S H times and conversion times k 20 ms at 20 MHz It has an asynchronous synchronous serial I O port (SIO) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port (SSIO) with full duplex master slave transceivers a flexible timer counter structure with prescaler cascading and quadrature capabilities There are ten modularized multiplexed highspeed I O for capture and compare (called Event Processor Array) with 200 ns resolution and double buffered inputs and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) implementing several channel modes including single burst block transfers from any memory location to any memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an A D scan mode NOTICE This is an advance information data sheet The A C and D C parameters contained within this data sheet may change after full automotive temperature characterization of the device has been performed Contact your local sales office before finalizing the timing and D C characteristics of a design to verify you have the latest information 272405 – 30 Figure 1 8XC196CB Block Diagram 2 87C196CA 87C196CB All thermal impedance data is approximate for static air conditions at 1 0W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology PROCESS INFORMATION These devices are manufactured on P629 5 a CHMOS III-E process Additional process and reliability information is available in Intel’s Components Quality and Reliability Handbook Order Number 210997 272405 – 2 Figure 2 The 87C196CA CB Familiy Nomenclature Thermal Characteristics Device and Package AN87C196CB (84-Lead PLCC Package) AN87C196CA (68-Lead PLCC Package) iJA 35 0 C W 36 5 C W iJC 11 0 C W 10 0 C W NOTES 1 iJA e Thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft away from case in air flow environment iJC e Thermal resistance between junction and package face (case) 2 All values of iJA and iJC may fluctuate depending on the environment (with or without airflow and how much airflow) and device power dissipation at temperature of operation Typical variations are g 2 C W 3 Values listed are at a maximum power dissipation of 1 0W 3 87C196CA 87C196CB 272405 – 14 Figure 3 84-Pin PLCC AN87C196CB Diagram 4 87C196CA 87C196CB 272405 – 33 Figure 4 100-Pin QFP AS87C196CB Diagram 5 87C196CA 87C196CB 272405 – 3 Figure 5 68-Pin PLCC 87C196CA Diagram 6 87C196CA 87C196CB Symbol VCC VSS VSS1 VREF Main Supply Voltage ( a 5V) Name and Function Digital circuit ground (0V) There are 7 VSS pins CB (4 on CA) all of which MUST be connected to a single ground plane Reference for the A D converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference ground for the A D converter Must be held at nominally the same potential as VSS Programming voltage for EPROM parts It should be a 12 5V for programming It is also the timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to VSS and a 1Mohm resistor to VCC If this function is not used VPP may be tied to VCC Input of the oscillator inverter and the internal clock generator Output of the Oscillator Inverter Reset input to the chip Input low for at least 16 state times will reset the chip The subsequent low to high transition resynchronizes CLKOUT and commences a 10-state time sequence in which the PSW is cleared bytes are read from 2018H 201Ah and 201CH (if enabled) loading the CCB’s and a jump to location 2080H is executed Input high for normal operation RESET has an internal pullup A positive transition causes a non-maskable interrupt vector through memory location 203EH If not used this pin should be tied to VSS May be used by Intel Evaluation boards Input for memory select (External Access) EA equal to a high causes memory accesses to locations 0FF2000H through 0FFFFFFH to be directed to on-chip EPROM ROM EA equal to a low causes accesses to these locations to be directed to off-chip memory EA e a 12 5V causes execution to begin in the Programming Mode EA is latched at reset Selects between PLL mode or PLL bypass mode This pin must be either tied high or low PLLEN pin e 0 bypass PLL mode PLLEN pin e 1 places a 4x PLL at the input of the crystal oscillator Allows for a low frequency crystal to drive the device (i e 5 MHz e 20 MHz operation) Dual function I O ports have a system function as Synchronous Serial I O Two pins are clocks and two pins are data providing for full duplex capability Also LSIO when not used as SSIO Dual function I O pin Primary function is that of a bidirectional I O pin however it may also be used as a TIMER1 Direction input The TIMER1 will increment when this pin is high and decrements when this pin is low Dual function I O pin Primary function is that of a bidirectional I O pin however may also be used as a TIMER1 Clock input The TIMER1 will increment or decrement on both positive and negative edges of this pin Dual function I O port pins Primary function is that of bidirectional I O System function is that of High Speed capture and compare ANGND VPP XTAL1 XTAL2 RESET NMI EA PLLEN (196CB only) P6 4–6 7 SSIO P6 3 T1DIR (CB only) P6 2 T1CLK (CB only) P6 0–6 1 EPA8–9 7 87C196CA 87C196CB Symbol P5 7 BUSWIDTH (CB only) Name and Function Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin dynamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low an 8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’ all bus cycles are 16-bit CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal Also an LSIO pin when not used as BUSWIDTH Ready input to lengthen external memory cycles for interfacing with slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait state mode until the next opositive transition in CLKOUT occurs with READY high When external memory is not used READY has no effect The max number of wait states inserted into the bus cycle is controlled by the CCR CCR1 Also an LSIO if READY is not selected P5 6 READY P5 5 BHE WRH Byte High Enable or Write High output as selected by the CCR BHE e 0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0 selects the bank of memory that is connected to the low byte Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH is only valid during 16-bit external Also an LSIO pin when not BHE WRH Dual function I O pin As a bidirectional port pin or as a system function The system function is a Slave Port Interrupt Output Pin (on CA bidirectional port pin only) Read signal output to external memory RD reads or LSIO when not used as RD is active only during external memory P5 4 SLPINT P5 3 RD P5 2 WR WRL Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is active during external memory writes Also an LSIO pin when not used as WR WRL Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal EPROM fetches INST is held low Also LSIO when not INST Address Latch Enable or Address Valid Output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip select for external memory ALE ADV is active only during external memory accesses Also LSIO when not used as ALE P5 1 INST (CB only) P5 0 ALE ADV 8 87C196CA 87C196CB Symbol PORT 3 and 4 P2 7 CLKOUT P2 6 HLDA Name and Function 8-bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups Output of the internal clock generator The frequency is the oscillator frequency CLKOUT has a 50% duty cycle Also LSIO pin when not used as CLKOUT Bus Hold Acknowledge Active-low output indicates that the bus controller has relinquished control of the bus Occurs in response to an external device asserting the HLD signal Also LSIO when not used as HLDA Bus Hold Active-low signal indictes that an external device is requesting control of the bus Also LSIO when not used as HLD Interrupt Output This active-low output indicates that a pending interrupt requires use of the external bus Also LSIO when not used as INTOUT Bus Request This active-low output signal is asserted during a HOLD cycle when the bus controller has a pending external memory cycle Also LSIO when not used as BREQ A positive transition on this pin causes a maskable interrupt vector through memory location 203CH Also LSIO when not used as EXTINT Receive data input pin for the Serial I O port Also LSIO if not used as RXD Transmit data output pin for the Serial I O port Also LSIO if not used as TXD Dual function I O port pins Primary function is that of bidirectional I O System function is that of High Speed capture and compare EPA0 and EPA2 have another function of T2CLK and T2DIR of the TIMER2 timer counter 8-bit high impedance input-only port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter These pins are also used as inputs to EPROM parts to select the Programming Mode 8-bit bidirectional standard and I O Port These bits are shared with the extended address bus A16–A19 for CB PLCC A16 – A23 for CB QFP Pin function is selected on a per pin basis Push-pull output to the CAN bus line High impedance input-only from the CAN bus line P2 5 HLD (CB only) P2 4 INTOUT P2 3 BREQ (CB only) P2 2 EXTINT P2 1 RXD P2 0 TXD PORT 1 EPA0–7 PORT 0 ACH0–7 EPORT (CB only) TXCAN RXCAN 9 87C196CA 87C196CB 87C196CB Memory Map Address FFFFFFH FF2080H FF207FH FF2000H FF1FFFH FF0600H FF05FFH FF0400H FF03FFH FF0100H FF00FFH FF0000H FEFFFFH 0F0000H 0EFFFFH 010000H 00FFFFH 002080H 00207FH 002000H 001FFFH 001FE0H 001FDFH 001F00H 001EFFH 001E00H 001DFFH 001C00H 001BFFH 000600H 0005FFH 000400H 0003FFH 000100H Description Program Memory - Internal EPROM or External Memory (Determined by EA Pin) Special Purpose Memory (Internal EPROM or External Memory) (Determined by EA Pin) External Memory Internal RAM (Identically Mapped into 00400H – 005FFH) External Memory Reserved for ICE Overlayed Memory (External) Accesses into Memory Ranges 0F0000H to FEFFFFH will Overlay Page 15 (0FH) for CB QFP package External Memory (5) 900 Kbytes External Memory External Memory or Remapped OTPROM (Program Memory)(1) External Memory or Remapped OTPROM (Special Purpose Memory)(1 3) Memory Mapped Special Function Registers (SFR’s) Internal Peripheral Special Function Registers (SFR’s)(5) Internal CAN Peripheral Memory(5) Internal Register RAM External Memory Internal RAM (Code RAM) (Address with Indirect or Indexed Modes) Register RAM – Upper Register File (Address with Indirect or Indexed Modes or through Windows )(2) 10 87C196CA 87C196CB 87C196CB Memory Map (Continued) Address 0000FFH 000018H 000017H 000000H Description Register RAM – Lower Register File (Address with Direct Indirect or Indexed Modes )(2) CPU SFR’s(4) NOTES 1 These areas are mapped internal EPROM if the REMAP bit (CCB2 2) is set and EA memory 2 Code executed in locations 0000H to 003FFH will be forced external 3 Reserved memory locations must contain 0FFH unless noted 4 Reserved SFR bit locations must be written with 0 5 Refer to 8XC196CB User’s Guide for SFR CAN and Paging Descriptions e 5V Otherwise they are external 87C196CA Memory Map Address 00FFFFH 00A000H 009FFFH 002080H 00207FH 002000H 001FFFH 001FE0H 001FDFH 001F00H 001EFFH 001E00H 001DFFH 000500H 0004FFH 000400H 0003FFH 000100H 0000FFH 000018H 000017H 000000H External Memory Internal EPROM (32 Kbytes) Reserved Memory (Internal EPROM or External Memory) (Determined by EA Pin) Memory Mapped Special Function Registers (SFR’s) Internal Special Function Registers (SFR’s)(1) Internal CAN Peripheral Memory External Memory Internal RAM (Code RAM) (Address with Indirect or Indexed Modes) Internal Register RAM – Upper Register File (Address with Indirect or Indexed Modes or through Windows)(2) Internal Register RAM – Lower Register File (Address with Direct Indirect or Indexed Modes(2) CPU Special Function Registers (SFR’s)(2 4) Description NOTES 1 Refer to 8XC196KX Family User’s Guide for SFR Description 2 Code executed in locations 0000H to 03FFH will be forced external 3 Reserved SFR bit locations must be written with 0 11 87C196CA 87C196CB CCB 0 1 2 3 4 5 6 7 PD BW0 WR ALE IRC0 IRC1 LOC0 LOC1 (2018h Byte) e e e e e e e e CCB1 (201Ah Byte) 0 1 BHE ‘‘0’’ e WRL WRH 2 3 4 5 6 7 CCR2 IRC2 BW1 WDE 1 0 MEMSEL0 MEMSEL1 e e e e e e e e ‘‘1’’ Enables Powerdown See Table ‘‘1’’ e WR ‘‘1’’ e ALE See Table See Table See Table See Table ‘‘1’’ fetch CCB2 (‘‘0’’ for CA) See Table See Table ‘‘0’’ e Always Enabled Reserved Must Be ‘‘1’’ Reserved Must Be ‘‘0’’ See Table (‘‘1’’ for CA) See Table (‘‘1’’ for CA) ‘‘0’’ e ADV CCB2 (201Ch Byte) (CB Only) 0 1 2 3 4 5 6 7 0 MODE16 REMAP 1 1 1 1 1 e e e e e e e e Reserved Must be ‘‘0’’ Select 16-Bit or 24-Bit Mode ( ‘‘1’’ ‘‘0’’ Select EPROM CODERAM in Segment 0FFH only Select Both Segment 0FFH and Segment 00H Reserved Must be ‘‘1’’ Reserved Must be ‘‘1’’ Reserved Must be ‘‘1’’ Reserved Must be ‘‘1’’ Reserved Must be ‘‘1’’ LOC1 0 0 1 1 LOC0 0 1 0 1 Function Read and Write Protected Write Protected Only Read Protected Only No Protection ‘‘CB’’ Bus Timing Mode Mode 0 (1-Wait KR) Reserved Must Not Be Used Reserved Must Not Be Used Mode 3 (KR) IRC2 0 1 1 1 1 BW1 0 0 1 1 IRC1 0 0 0 1 1 BW0 0 1 0 1 IRC0 0 0 1 0 1 Max Wait States Zero Wait States 1 Wait State 2 Wait States 3 Wait States INFINITE Bus Width ILLEGAL 16-Bit Only 8-Bit Only BW Pin Controlled MSEL1 MSEL0 0 0 1 1 Mode 0 (1-Wait KR) 0 1 0 1 Designed to be similar to the 87C196KR bus timing with 1 automatic wait state See AC Timings section for actual timings data Mode 3 (KR) Designed to be similar to the 87C196KR bus timing See AC Timings section for actual timings data 12 87C196CA 87C196CB ABSOLUTE MAXIMUM RATINGS Storage Temperature Voltage from VPP or EA to VSS or ANGND b 60 C to a 150 C b 0 5V to a 13 0V Voltage from Any Other Pin b 0 5 to a 7 0V to VSS or ANGND This includes VPP on ROM and CPU devices Power Dissipation 1 0W NOTICE This data sheet contains information on products in the sampling and initial production phases of development The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability OPERATING CONDITIONS Symbol TA VCC VREF FOSC Parameter Ambient Temperature Under Bias Digital Supply Voltage Analog Supply Voltage Oscillator Frequency Min b 40 Max a 125 Units C V V MHz(4) 4 50 4 50 4 5 50 5 50 20 NOTE ANGND and VSS should be nominally at the same potential DC CHARACTERISTICS Symbol ICC Parameter (Under Listed Operating Conditions) Test Conditions Min Typ Max Units VCC Supply Current XTAL1 e 20 MHz ( b 40 C to a 125 C Ambient) VCC e VPP e VREF e 5 5V CA (While device in Reset) CB A D Reference Supply Current Idle Mode Current XTAL1 e 20 MHz CA VCC e VPP e VREF e 5 5V CB VCC e VPP e VREF e 5 5V(6 9) For PORT0(8) For PORT0(8) IOL e 200 mA(3 5) IOL e 3 2 mA IOL e 7 0 mA IOH e b 200mA(3 5) IOH e b 3 2 mA IOH e b 7 0 mA VCC b 0 3 VCC b 0 7 VCC b 1 5 b 0 5V 90 100 5 40 35 50 TBD 0 3 VCC VCC a 0 5 03 0 45 15 mA mA mA mA mA mA V V V V V V V V IREF IIDLE IPD VIL VIH VOL Powerdown Mode Current Input Low Voltage (all pins) Input High Voltage Output Low Voltage (Outputs Configured as Complementary) Output High Voltage (Outputs Configured as Complementary) 0 7 VCC VOH 13 87C196CA 87C196CB 87C196CB ICC vs Frequency 272405 – 31 87C196CA ICC vs Frequency 272405 – 32 14 87C196CA 87C196CB DC CHARACTERISTICS Symbol ILI ILI1 VOH1 VOH2 CS RWPU RRST RRST (Under Listed Operating Conditions) (Continued) Test Conditions VSS k VIN k VCC VSS k VIN k VREF IOH e 0 8 mA(7) IOH e b 15 mA(1) ftest e 1 0 MHz(6) (Note 6) For CB For CA 65K 6K 150K 180K 65K 20 VCC b 1V 10 Min Typ Max g 10 Parameter Input Leakage Current (Std Inputs) Input Leakage Current (Port 0) SLPINT (P5 4) and HLDA (P2 6) Output High Voltage in RESET Output High Voltage in RESET Pin Capacitance (Any pin to VSS) Weak Pullup Resistance Reset Pullup Resistor Reset Pullup Resistor CA Units mA mA V V pF X X X CA g 1 5 CB g 1 0 NOTES 1 All BD (bidirectional) pins except INST and CLKOUT INST and CLKOUT are excluded due to their not being weakly pulled high in reset BD pins include Port1 Port2 Port3 Port4 Port5 and Port6 except SPLINT (P5 4) and HLDA (P2 6) 2 Standard input pins include XTAL1 EA RESET and Port 1 2 5 6 when setup as inputs 3 All bidirectional I O pins when configured as Outputs (Push Pull) 4 Device is static and should operate below 1 Hz but only tested down to 4 MHz 5 Maximum IOL IOH currents per pin will be characterized and published at a later date 6 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and VREF e VCC e 5 0V 7 Violating these specifications in reset may cause the device to enter test modes (P5 4 and P2 6) 8 When P0 is used as analog inputs refer to A D specifications for this characteristic 9 For temperatures k100 C typical is 10 mA 8XC196CB ADDITIONAL BUS TIMING MODES The 8XC196CB device has 2 bus timing modes for external memory interfacing MODE 3 Mode 3 is the standard timing mode Use this mode for systems that emulate the 8XC196KR bus timings MODE 0 Mode 0 is the standard timing mode but 1 (minimum) wait state is always inserted in external bus cycles 15 87C196CA 87C196CB AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns The 87C196CA CB will meet these specifications Symbol FXTAL TOSC TXHCH TOFD TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL Parameter Frequency on XTAL1 XTAL1 Period (1 FXTAL) XTAL1 High to CLKOUT High or Low Clock Failure to Reset Pulled Low(6) CLKOUT Period CLKOUT High Period CLKOUT Low to ALE ADV High ALE ADV Low to CLKOUT High ALE ADV Cycle Time ALE ADV High Time Address Valid to ALE Low Address Hold After ALE ADV Low ALE ADV Low to RD Low RD Low to CLKOUT Low CA CB TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH RD Low Period RD High to ALE ADV High RD Low to Address Float ALE ADV Low to WR Low CLKOUT Low to WR Low Data Valid before WR High CLKOUT High to WR High WR Low Period CB CA TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Data Hold after WR High WR High to ALE ADV High BHE INST Hold after WR High AD8–15 Hold after WR High BHE INST Hold after RD High AD8–15 Hold after RD High TOSC b 30 TOSC b 20 TOSC b 25 TOSC b 10 TOSC b 10 TOSC b 30 TOSC b 10 TOSC b 30 TOSC a 15 ns(5) ns ns(3) ns ns(4) ns ns(4) TOSC b 10 b5 a 25 a4 b8 a 30 a 20 Min 40 50 0 a 20 Max 20 250 110 40 2 TOSC Units MHz(1) ns ns ms ns 4 TOSC b 10 b 15 b 20 TOSC a 15 a 10 a 15 ns ns ns ns(5) 4 TOSC TOSC b 10 TOSC b 15 TOSC b 40 TOSC b 30 TOSC a 10 ns ns ns ns ns ns ns(5) TOSC b 10 TOSC TOSC a 25 5 ns(3) ns ns ns ns TOSC b 23 b 10 a 15 ns NOTES 1 Testing performed at 4 0 MHz however the device is static by design and will typically operate below 1 Hz 2 Typical specifications not guaranteed 3 Assuming back-to-back bus cycles 4 8-bit bus only 5 If wait states are used add 2 Tosc c n where n e number of wait states If mode 0 (1 automatic wait state added) operation is selected add 2 TOSC to specification 6 TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H Programming the CDE bit enables oscillator fail detection 16 87C196CA 87C196CB AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise anf Fall Times e 10 ns The system must meet these specifications to work with the 87C196CA CB Symbol TAVYV TLLYV TYLYH TCLYX TAVGV TLLGV TCLGX TAVDV TRLDV Parameter Address Valid to Ready Setup ALE Low to READY Setup Non READY Time READY Hold after CLKOUT Low Address Valid to BUSWIDTH Setup ALE Low to BUSWIDTH Setup BUSWIDTH Hold after CLKOUT Low Address Valid to Input Data Valid RD active to input Data Valid CA CB TCLDV TRHDZ TRHDX CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD High 0 TOSC b 22 TOSC b 30 TOSC b 50 TOSC ns(2) ns(2) ns ns ns 0 3 TOSC b 55 0 Min Max 2 TOSC b 75 TOSC b 70 No Upper Limit TOSC b 30 2 TOSC b 75 TOSC b 60 Units ns(3) ns(3) ns ns(1) ns(2 3) ns(2 3) ns ns(2) NOTES 1 If Max is exceeded additional wait states will occur 2 If wait states are used add 2 Tosc c n where n e number of wait states 3 If mode 0 is selected one wait state minimum is always added If additional wait states are required add 2 Tosc to the specification 17 87C196CA 87C196CB 87C196CA CB SYSTEM BUS TIMING 272405 – 17 If mode 0 operation is selected add 2 Tosc to this time 18 87C196CA 87C196CB 87C196CA CB READY TIMINGS (ONE WAIT STATE) 272405 – 18 If mode 0 selected (CB only) one wait state is always added If additional wait states are required add 2 Tosc to these specifications 87C196CB BUSWIDTH TIMINGS 272405 – 19 If mode 0 selected (CB only) add 2 Tosc to these specifications 19 87C196CA 87C196CB 8XC196CB HOLD HOLDA TIMINGS Symbol THVCH TCLHAL TCLBRL TAZHAL TBZHAL TCLHAH TCLBRH THAHAX THAHBV HOLD Setup Time CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float (Over Specified Operation Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns Parameter Min a 65 b 15 b 15 a 15 a 15 a 20 a 25 b 15 b 25 b 15 b 10 a 15 a 15 a 25 Max Units ns(1) ns ns ns ns ns ns ns ns HLDA Low to BHE INST RD WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE INST RD WR Valid NOTE 1 To guarantee recognition at next clock 8XC196CB HOLD HOLDA TIMINGS 272405 – 20 20 87C196CA 87C196CB 8XC196CB AC CHARACTERISTICS SLAVE PORT WAVEFORM (SLPL e 0) SLAVE PORT 272405 – 21 SLAVE PORT TIMING Symbol TSAVWL TSRHAV TSRLRH TSWLWH TSRLDV TSDVWH TSWHQX TSRHDZ (SLPL e 0 1 2 3) Parameter Address Valid to WR Low RD High to Address Valid RD Low Period WR Low Period RD Low to Output Data Valid Input Data Setup to WR High WR High to Data Invalid RD High to Data Float 20 30 15 Min 50 60 TOSC TOSC 60 Max Units ns ns ns ns ns ns ns ns NOTES 1 Test Conditions FOSC e 20 MHz TOSC e 60 ns Rise Fall Time e 10 ns Capacitive Pin Load e 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change 21 87C196CA 87C196CB AC CHARACTERISTICS SLAVE PORT WAVEFORM SLAVE PORT (Continued) (SLPL e 1) 272405 – 22 SLAVE PORT TIMING Symbol TSELLL TSRHEH TSLLRL TSRLRH TSWLWH TSAVLL TSLLAX TSRLDV TSDVWH TSWHQX TSRHDZ (SLPL e 1 2 3) Parameter CS Low to ALE Low RD or WR High to CS High ALE Low to RD Low RD Low Period WR Low Period Address Valid to ALE Low ALE Low to Address Invalid RD Low to Output Data Valid Input Data Setup to WRHigh WR High to Data Invalid RD High to Data Float 20 30 15 Min 20 60 TOSC TOSC TOSC 20 20 60 Max Units ns ns ns ns ns ns ns ns ns ns ns NOTES 1 Test Conditions FOSC e 20 MHz TOSC e 60 ns Rise Fall Time e 10 ns Capacitive Pin Load e 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change 22 87C196CA 87C196CB t e 1 state time (125 ns 16 MHz) NORMAL MASTER SLAVE OPERATION Symbol TCHCH TCLCH TCLDV TCLDV1 TDVCH Clock Period Clock Low Time Clock High Time Clock Falling to Data Out Valid (Master) Clock Falling to Data Out Valid (Slave) Data In Setup to Clock Rising Edge Parameter Min 4t 2t b 10 0 5t 0 5t 10 t a 15 1 5t a 20 1 5t a 50 Max Units ns ns(1) ns ns ns ns TCHDX Clock Rising Edge to Data in Invalid Timings are guaranteed by design HANDSHAKE OPERATION Symbol TCHCH TCLCH TCLDV TCLDV1 TDVCH TCLDX Clock Period Clock Low Time Clock High Time Clock Falling to Data Out Valid (Master) Clock Falling to Data Out Valid (Slave) Data In Setup to Clock Rising Edge Clock Rising Edge to Data in Invalid Parameter Min 4t 2t b 10 0 5t 0 5t 10 t a 15 Max Units ns ns(1) 1 5t a 20 1 5t a 50 ns ns ns ns Timings are guaranteed by design NOTE 1 This specification refers to input clocks during slave operation During master operation the device will output a nominal 50% duty cycle clock 272405 – 34 NOTE The top SCx signal assumes that the SSIO is configured to sample on the leading edge with an active-high clock signal The SCx signal will be different for other configurations however setup and hold timings will still be the same in relation to the latching edge of SCx Figure 6 Synchronous Serial Port 23 87C196CA 87C196CB EXTERNAL CLOCK DRIVE Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period (TOSC) High Time Low Time Rise Time Fall Time Min 4 50 0 0 35 c TOSC 0 35 c TOSC Max 20 250 0 65 TOSC 0 65 TOSC 10 10 Units MHz ns ns ns ns ns EXTERNAL CLOCK DRIVE WAVEFORMS 272405 – 23 AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 272405 – 25 272405 – 24 AC Testing inputs are driven at 3 5V for a logic ‘‘1’’ and 0 45V for a logic ‘‘0’’ Timing measurements are made at 2 0V for a logic ‘‘1’’ and 0 8V for logic ‘‘0’’ For timing purposes a Port Pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH VOL level occurs IOL IOH s 15 mA EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points Conditions H High L Low V Valid X No Longer Valid Z Floating Signals A Address B BHE BR BREQ C CLKOUT D DATA G Buswidth H HOLD HA HLDA L ALE ADV Q Data Out RD RD W WR WRH WRI X XTAL1 Y READY 24 87C196CA 87C196CB EPROM SPECIFICATIONS AC EPROM PROGRAMMING CHARACTERISTICS Operating Conditions Load Capacitance e 150 pF TC e 25 C g 5 C VCC VREF e 5 0V g 0 5V VSS ANGND e 0V VPP e 12 5V g 0 25V EA e 12 5V g 0 25V Fosc e 5 0 MHz Symbol TAVLL TLLAX TDVPL TPLDX TLLLH TPLPH Parameter Address Setup Time Address Hold Time Data Setup Time Data Hold Time PALE Pulse Width PROG Pulse Width(2) CA CB TLHPL TPHLL TPHDX TPHPL TLHPL TPLDV PALE High to PROG Low PROG High to next PALE Low Word Dump Hold Time PROG High to next PROG Low PALE High to PROG Low PROG Low to Word Dump Valid CA CB RESET High to First PALE Low PROG High to AINC Low AINC Pulse Width PVER Hold after AINC Low AINC Low to PROG Low PROG High to PVER Valid 1100 0 240 50 170 220 220 220 50 100 50 100 220 220 50 TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC Min 0 100 0 400 50 Max Units TOSC TOSC TOSC TOSC TOSC TSHLL TPHIL TILIH TILVH TILPL TPHVL NOTES 1 Run-time programming is done with Fosc e 6 0 MHz to 10 0 MHz VCC VPD VREF e 5V g 0 5V TC e 25 C g 5 C and VPP e 12 5V g 0 25V For run-time programming over a full operating range contact factory 2 Programming specifications are not tested but guaranteed by design 3 This specification is for the word dump mode For programming pulses use 300 Tosc a 100 ms DC EPROM PROGRAMMING CHARACTERISTICS Symbol IPP Parameter VPP Programming Supply Current Min Max 200 Units mA NOTE VPP must be within 1V of VCC while VCC k 4 5V VPP must not have a low impedance path to ground or VSS while VCC l 4 5V 25 87C196CA 87C196CB EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 272405 – 26 SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT 272405 – 27 26 87C196CA 87C196CB SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT 272405 – 28 AC CHARACTERISTICS SERIAL PORT-SHIFT REGISTER MODE SERIAL PORT TIMING SHIFT REGISTER MODE 0 Test Conditions TA e b 40 C to a 125 C VCC e 5 0V g 10% VSS e 0 0V Load Capacitance e pF Symbol TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX(8) TXHQZ(8) Parameter Serial Port Clock Period Serial Port Clock Falling Edge to Rising Edge Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float 2 TOSC a 200 0 5 TOSC Min 8 TOSC 4 TOSC b 50 3 TOSC 2 TOSC b 50 2 TOSC a 50 4 TOSC a 50 Max Units ns ns ns ns ns ns ns ns NOTE 8 Parameters not tested 27 87C196CA 87C196CB WAVEFORM SERIAL PORT SHIFT REGISTER MODE SERIAL PORT WAVEFORM SHIFT REGISTER MODE 272405 – 29 A TO D CHARACTERISTICS The sample and conversion time of the A D converter in the 8-bit or 10-bit modes is programmed by loading a byte into the AD TIME Special Function Register This allows optimizing the A D operation for specific applications The AD TIME register is functional for all possible values but the accuracy of the A D converter is only guaranteed for the times specified in the operating conditions table The value loaded into AD TIME bits 5 6 7 determines the sample time SAMP The value loaded into AD TIME bits 0 1 2 3 and 4 determines the bit conversion time CONV These bits as well as the equation for calculating the total conversion time T are shown in the following table AD TIME 7 6 Sample Time (SAMP) 4n a 1 state times n e 1 to 7 5 4 The converter is ratiometric so absolute accuracy is dependent on the accuracy and stability of VREF VREF must be close to VCC since it supplies both the resistor ladder and the analog portion of the converter and input port pins There is also an AD TEST SFR that allows for conversion on ANGND and VREF as well as adjusting the zero offset The absolute error listed is without doing any adjustments A D CONVERTER SPECIFICATION The specifications given assume adherence to the operating conditions section of this data sheet Testing is performed with VREF e 5 12V and 20 MHz operating frequency After a conversion is started the device is placed in IDLE mode until the conversion is complete 1FAFH Byte 3 2 1 0 Bit Conversion Time (CONV) n a 1 state times n e 2 to 31 Equation T e (SAMP) a Bx (CONV) a 2 5 T e total conversion time (states) B e number of bits conversion (8 or 10) n e programmed register value 28 87C196CA 87C196CB 10-BIT MODE A D OPERATING CONDITIONS Symbol TA VCC VREF TSAM TCONV FOSC Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min b40 Max a 125 Units C V V(1) ms(2) 4 50 4 50 20 15 40 5 50 5 50 18 20 0 ms(2) MHz NOTES 1 VREF must be within 0 5V of VCC 2 The value of AD TIME is selected to meet these specifications 10-BIT MODE A D CHARACTERISTICS Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Voltage on Analog Input Pin Sampling Capacitor 30 g1 0 g0 1 g 0 25 (Using Above Operating Conditions)(6) Min 1024 10 0 Max 1024 10 g3 0 Typ (1) Units Level Bits LSBs LSBs LSBs 0 25 g 0 5 0 25 g 0 5 1 0 g2 0 b0 75 g3 0 LSBs LSBs LSBs LSBs(1) LSB C(1) LSB C(1) LSB C(1) a 0 75 g1 0 0 0 0 009 0 009 0 009 b60 b60 b60 dB(1 2 3) dB(1 2) dB(1 2) 750 0 ANGND b 0 5 1 2K g3 0 X(4) mA V(5) pF VREF a 0 5 An ‘‘LSB’’ as used here has a value of approximately 5 mV NOTES 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer break-before-make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 Applying voltages beyond these specifications will degrade the accuracy of other channels being converted 6 All conversions performed with processor in IDLE mode 29 87C196CA 87C196CB 8-BIT MODE A D OPERATING CONDITIONS Symbol TA VCC VREF TSAM TCONV FOSC Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min b40 Max a 125 Units C V V(1) ms(2) 4 50 4 50 20 12 40 5 50 5 50 15 20 0 ms(2) MHz NOTES 1 VREF must be within 0 5V of VCC 2 The value of AD TIME is selected to meet these specifications 8-BIT MODE A D CHARACTERISTICS Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Voltage on Analog Input Pin Sampling Capacitor 30 g1 0 g 0 25 g0 5 g0 5 (Using Above Operating Conditions)(6) Min 256 8 0 Max 256 8 g1 0 Typ (1) Units Level Bits LSBs LSBs LSBs 0 b0 5 g1 0 LSBs LSBs LSBs LSBs(1) LSB C(1) LSB C(1) LSB C(1) a0 5 g1 0 0 0 0 003 0 003 0 003 b60 b60 b60 dB(1 2 3) dB(1 2) dB(1 2) 750 0 ANGND b 0 5 1 2K g1 5 X(4) mA V(5) pF VREF a 0 5 An ‘‘LSB’’ as used here has a value of approximately 20 mV NOTES 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer break-before-make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 Applying voltage beyond these specifications will degrade the accuracy of other channels being converted 6 All conversions performed with processor in IDLE mode 30 87C196CA 87C196CB Additionally these port pins should be setup internally by software as follows 1 Written to PxREG as ‘‘1’’ or ‘‘0’’ 2 Configured as Push Pull PxIO as ‘‘0’’ 3 Configured as LSIO This configuration will effectively strap the pin either high or low DO NOT Configure as Open Drain output ‘’1’’ or as an Input pin This device is CMOS (6) EPA Timer RESET Write Conflict If the user writes to the EPA timer at the same time that the timer is reset it is indeterminate which will take precedence Users should not write to a timer if using EPA signals to reset it (7) Valid Time Matches The timer must increment decrement to the compare value for a match to occur A match does not occur if the timer is loaded with a value equal to an EPA compare value Matches also do not occur if a timer is reset and 0 is the EPA compare value (8) Write Cycle during Reset If RESET occurs during a write cycle the contents of the external memory device may be corrupted (9) Indirect Shift Instruction The upper 3 bits of the byte register holding the shift count are not masked completely If the shift count register has the value 32 c n where n e 1 3 5 or 7 the operand will be shifted 32 times This should have resulted in no shift taking place (10) P2 7 (CLKOUT) P2 7 (CLKOUT) does not operate in open drain mode 87C196CA DESIGN CONSIDERATIONS The 87C196CA device is a memory scalar of the 87C196KR device with integrated CAN 2 0 The CA is designed for strict functional and electrical compatibility to the Kx family as well as integration of onchip networking capability The 87C196CA has fewer peripheral functions than the 196KR due in part to the integration of the CAN peripheral Following are the functionality differences between the 196KR and 196CA devices 196KR Features Unsupported on the 196CA Analog Channels 0 and 1 INST Pin Functionality SLPINT and SLPCS Pin Support HLD HLDA Functionality External Clocking Direction of Timer 1 Quadrature Clocking Timer 1 Dynamic Buswidth EPA Capture Channels 4–7 (1) External Memory Removal of the Buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus mode or vice versa The programmer must define the bus mode by setting the associated bits in the CCB (2) Auto-Programming Mode The 87C196CA device will ONLY support the 16-bit zero wait state bus during auto-programming (3) EPA4 through EPA7 Since the CA device is based on the KR design these functions are in the device however there are no associated pins A programmer can use these as compareonly channels or for other functions like software timer start an A D conversion or reset timers (4) Slave Port Support The Slave port can not be used on the 196CA due to a function change for P5 4 SLPINT and P5 1 SLPCS not being bonded-out (5) Port Functions Some port pins have been removed P5 1 P6 2 P6 3 P1 4 through P1 7 P2 3 P2 5 P0 0 and P0 1 The PxREG PxSSEL and PxIO registers can still be updated and read The programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software Treat these bits as RESERVED 31 87C196CA 87C196CB 87C196CA ERRATA This data sheet was published prior to first available silicon Consequently there is no known errata at this time Register Bits P2 P2 P2 PIN x REG x DIR x MODE x (x e 3 5) (x e 3 5) (x e 3 5) (x e 3 5) When Read 1 1 1 0 87C196CA DESIGN CONSIDERATIONS 1 PORT0 P2 Writing to these bits will have no effect 4 PORT5 On the 87C196CA the analog inputs for P0 0 and P0 1 have been multiplexed and tied to VREF Therefore initiating an analog conversion on ACH0 or ACH1 will result in a value equal to full scale (3FFh) On the CA the digital inputs for these two channels are tied to ground therefore reading P0 0 or P0 1 will result in a digital ‘‘0’’ 2 PORT1 On the 87C196CA P1 4 P1 5 P1 6 and P1 7 have been removed from the device and is unavailable to the programmer Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following results when read Register Bits P1 P1 P1 P1 PIN x REG x DIR x MODE x (x e 4 5 6 7) (x e 4 5 6 7) (x e 4 5 6 7) (x e 4 5 6 7) When Read 1 1 1 0 On the 87C196CA P5 1 and P5 7 have been removed from the device and are not available to the programmer Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following results when read Register Bits P5 P5 P5 P5 P5 PIN x REG x DIR x MODE x MODE x (x e 1 7) (x e 1 7) (x e 1 7) (x e 1) (x e 7) When Read 1 1 1 0 1 Writing to these bits will have no effect 5 PORT6 On the 87C196CA P6 2 and P6 3 have been removed from the device and are not available to the programmer Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following results when read Register Bits P6 P6 P6 P6 PIN x REG x DIR x MODE x (x e 2 3) (x e 2 3) (x e 2 3) (x e 2 3) When Read 1 1 1 0 Writing to these bits will have no effect 3 PORT2 On the 87C196CA P2 3 and P2 5 have been removed from the device and are not available to the programmer Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following results when read Writing to these bits will have no effect 32 87C196CA 87C196CB 7 The electrical characteristics for the CAN module were removed The electrical characteristics for TXCAN and RXCAN are identical to standard port pins 8 tOSC (1 freq) was modified to reflect 20 Mhz timings 9 tOFD (Oscillator Fail Detect Specification) for clock failure to RESET pin pulled low was added to the data sheet (4 ms min 40 ms max) 10 tWHQX has been increased to tOSC b 25 ns min from tOSC b 30 ns min 11 tRXDX has been replaced by tRHDX tRLAZ has been increased to 20 ns max from 5 ns max 12 IPP programming supply current has been increased to 200 mA from 100 mA 13 tCONV Conversion time for 10 bit A D conversions has been decreased to reflect 20 Mhz operation 14 RRST was added for the 87C196CA (min e 6 kX max e 65 kX 15 tCLLH min max parameters switched to accurately reflect this timing parameter 16 tRLCL Separate timings for the 87C196CA vs 87C196CB tRLCL for the CB is min b 8 ns max a 20 ns For the CA tRLCL min a 4 ns max a 30 ns 17 tRLRH changed to TOSC b 10 ns from TOSC b 5 ns 18 tAVGV added for the 87C196CB 19 20 21 tLLGV added for the 87C196CB tCLGX added for the 87C196CB tRLDV Separate timings for 87C196CB tRLDV max e TOSC b 30 ns For the 87C196CA tRLDV max e TOSC b 22 ns 22 HOLD HOLDA timings added for the 87C196CB DATA SHEET REVISION HISTORY This is the -003 revision of the 87C196CA CB data sheet The following differences exist between the -002 version and the -003 revision 1 The data sheet has been revised to ADVANCE from PRELIMINARY indicaitng the specifications have been verified through electrical tests 2 The 87C196CB 100-ld QFP package and device pinout has been added to the data sheet 3 The 87C196CB 100-ld QFP device supports up the 16 Mbyte of linear address space 4 The package thermal characteristics for the PLCC packages was added to the data sheet for the CB iJA e 35 0 C W iJC e 11 0 C W For the CA iJA e 36 5 C W and iJA e 10 0 C W 5 The AN87C196CB pin package diagram was corrected to show EA as opposed to EA 6 The REMAP bit funciton for CCB2 was corrected Setting this bit to 0 selects EPROM CODERAM in segment 0FFH only Setting this bit to 1 selects both segment 0FFH and segment 00H 7 tRLAZ has been changed to 5 ns from 20 ns 8 tWLWH for the CA has been changed to tOSC b 20 from tOSC b 30 9 tCLGX has been changed to 0 ns min from tOSC b 46 max 10 Timing specifications for the SSIO are now added These timings are currently guaranteed by design 11 Added frequency designation to family nomenclature Figure 2 This is the -002 revision of the 87C196CA data sheet The following difference exist between the -001 version and the -002 revision 1 This data sheet now includes the specifications for the 87C196CB as well as the 87C196CA 2 ABSOLUTE MAXIMUM RATINGS have been added 3 Maximum Frequency has been increased to 20 MHz 4 Maximum ICC has been increased from 75 mA to 100 mA for the CB 90 mA for the CA 5 Idle Mode current has been increased to 35 mA from 30 mA for the CB 40 mA for the CA 6 Input leakage current for Port 0 (ILI1) was decreased to 1 5 mA from 2 0 mA for the CA 23 Slave Port Timings added for the 87C196CB 24 Separate specifications for tPLPH for the 87C196CB tPLPH min e 100 TOSC For the 87C196CA tPLPH min e 50 TOSC 25 Separate specificatons for tPLDV for the 87C196CB tPLDV min e 100 TOSC for the 87C196CA tPLDV min e 50 TOSC 26 8-Bit mode A D characteristics added 33