AN87C54

87C54 87C54-20 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM Automotive Y Extended Automotive Temperature Range ( b 40 C to a 125 C Ambient) High Performance CHMOS EPROM Three 16-Bit Timer Counters One-to-Three Level Program Data Lock System 16K On-Chip EPROM ROM 256 Bytes of On-Chip Data RAM Quick Pulse Programming Algorithm Boolean Processor 32 Programmable I O Lines 7 Interrupt Sources Y Y Y Y Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS -51 Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode RFI Reduction Mode Available in 12 MHz 16 MHz and 20 MHz Versions Available in PLCC and DIP Packages (See Packaging Spec Order 231369) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y MEMORY ORGANIZATION PROGRAM MEMORY Up to 16 Kbytes of the program memory can reside in the on-chip EPROM The device can also address up to 64K of program memory external to the chip DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of external data memory The Intel 87C54 is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS EPROM technology Being a member of the MCS-51 family the 87C54 uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with the existing MCS-51 family of products The 87C54 is an enhanced version of the 87C51FB Its added features of 16 Kbytes of program memory make it an even more powerful microcontroller for applications that require High Speed I O and up down counting capabilities such as brake and traction control Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 February 1994 Order Number 270849-004 AUTOMOTIVE 87C54 87C54-20 270849 – 1 Figure 1 87C54 Block Diagram 2 AUTOMOTIVE 87C54 87C54-20 characteristics are guaranteed over the temperature range of b 40 C to a 85 C ambient For the automotive temperature range option operational characteristics are guaranteed over the temperature range of b 40 C to a 125 C ambient The automotive extended and commercial temperature versions of the MCS-51 product families are available with or without burn-in options As shown in Figure 2 temperature burn-in and package options are identified by a one- or two-letter prefix to the part number 87C54 PRODUCT OPTIONS Intel’s extended and automotive temperature range products are designed to meet the needs of those applications whose operating requirements exceed commercial standards With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 C to a 70 C ambient With the extended temperature range option operational 270849 – 4 Example AN87C54 indicates an automotive temperature range version of the 87C54 in a PLCC package with 16 Kbyte EPROM program memory Figure 2 Package Options Table 1 Temperature Options Temperature Classification Extended Automotive Temperature Designation T L A B Operating Temperature C Ambient b 40 to a 85 b 40 to a 85 b 40 to a 125 b 40 to a 125 Burn-In Options Standard Extended Standard Extended 3 AUTOMOTIVE 87C54 87C54-20 Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1’s written to them float and in that state can be used as high-impedance inputs Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory In this application it uses strong internal pullups when emitting1’s and can source and sink several LS TTL inputs Port 0 also receives the code bytes during EPROM programming and outputs the code bytes during program verification External pullup resistors are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups 270849 – 2 PACKAGES Part 87C54 87C54 Prefix AP AN Package Type 40-Pin Plastic DIP 44-Pin PLCC DIP (PDIP) In addition Port 1 serves the functions of the following special features of the 87C54 Port Pin P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 Alternate Function T2 (External Count Input to Timer Counter 2) Clock-Out T2EX (Timer Counter 2 Capture Reload Trigger and Direction Control) ECI (External Count Input to the PCA) CEX0 (External I O for Compare Capture Module 0) CEX1 (External I O for Compare Capture Module 1) CEX2 (External I O for Compare Capture Module 2) CEX3 (External I O for Compare Capture Module 3) CEX4 (External I O for Compare Capture Module 4) 270849 – 3 Do not connect reserved pins P1 6 P1 7 PAD (PLCC) Figure 3 Pin Connections PIN DESCRIPTIONS VCC Supply voltage VSS Circuit ground VSS1 Secondary ground (in PLCC only) Provided to reduce ground bounce and improve power supply by-passing NOTE This pin is not a substitute for the VSS pin (pin 22) 4 Port 1 receives the low-order address bytes during EPROM programming and verifying Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups The Port 2 output buffers can drive LS TTL inputs Port 2 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups AUTOMOTIVE 87C54 87C54-20 Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR) In this application it uses strong internal pullups when emitting 1’s During accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Some Port 2 pins receive the high-order address bits during EPROM programming and program verification Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (IIL on the data sheet) because of the pullups Port 3 also serves the functions of various special features of the MCS-51 Family as listed below Port Pin P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) In normal operation ALE is emitted at a constant rate of the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory Throughout the remainder of this data sheet ALE will refer to the signal coming out of the ALE PROG pin and the pin will be referred to as the ALE PROG pin PSEN Program Store Enable is the read strobe to external Program Memory When the 87C54 is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data Memory EA VPP External Access enable EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory locations 0000H to 0FFFFH Note however that if any of the Lock bits are programmed EA will be internally latched on reset EA should be strapped to VCC for internal program executions This pin also receives the programming supply voltage (VPP) during EPROM programming XTAL1 Input to the inverting oscillator amplifier In addition some Port 3 pins receive the high-order address bits and act as control signals during EPROM programming and programming verification RST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device The port pins will be driven to their reset condition when a minimum VIH1 is applied whether the oscillator is running or not An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory This pin (ALE PROG) is also the program pulse input during EPROM programming for the 87C54 XTAL2 Output from the inverting oscillator amplifier OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of a inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 4 Either a quartz crystal or ceramic resonator may be used More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155 ‘‘Oscillators for Microcontrollers ’’ 5 AUTOMOTIVE 87C54 87C54-20 POWER DOWN MODE To save even more power a Power Down mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated On the 87C54 either a hardware reset or an external interrupt can cause an exit from Power Down Reset redefines all the SFRs but does not change the onchip RAM An external interrupt allows both the SFRs and on-chip RAM to retain their values To properly terminate Power down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms) With an external interrupt INT0 or INT1 must be enabled and configured as level-sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit (The oscillator must be allowed time to stabilize after start up before this pin is released high ) Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down 270849 – 5 C1 C2 e 30 pF g 10 pF for Crystals For Ceramic Resonators contact resonator manufacturer Figure 4 Oscillator Connections To drive the device from an external clock source XTAL1 should be driven while XTAL2 floats as shown in Figure 5 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data sheet must be observed An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF DESIGN CONSIDERATION When the idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control Onchip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory 270849 – 6 Figure 5 External Clock Drive Configuration IDLE MODE The user’s software can invoke the Idle Mode When the microcontroller is in this mode power consumption is reduced The Special Function Registers and the onboard RAM retain their values during Idle but the processor stops executing instructions Idle Mode will be exited if the chip is reset or if an enabled interrupt occurs 6 AUTOMOTIVE 87C54 87C54-20 ONCE MODE The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates testing and debugging of systems using the 87C54 without the 87C54 having to be removed from the circuit The ONCE Mode is invoked by 1) Pull ALE low while the device is in reset and PSEN is high 2) Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins float and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the 87C54 is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied RFI REDUCTION MODE The RFI reduction feature can be used only if external program memory is not required since this mode disables the ALE pin during instruction code fetches By writing a logical one to the LSB of the Auxiliary Register (address 08EH) the ALE is disabled for instruction code fetches and the output is weakly held high When a logical zero is written the ALE pin is enabled allowing it to generate the Address Latch Enable signal This bit is cleared by reset Once disabled ALE remains disabled until it is reset by software or until a hardware reset occurs Table 2 Status of the External Pins during Idle and Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data NOTE For more detailed information on the reduced power modes refer to current Embedded Applications Handbook and Application Note AP-252 ‘‘Designing with the 80C51BH ’’ 7 AUTOMOTIVE 87C54 87C54-20 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias b 40 C to a 125 C Storage Temperature Voltage on EA VPP Pin to VSS Voltage on Any Other Pin to VSS IOL Per I O Pin b 65 C to a 150 C 0V to a 13 0V b 0 5V to a 6 5V NOTICE This data sheet contains information on products in the sampling and initial production phases of development The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design 15 mA Power Dissipation 1 5W (Based on package heat transfer limitations not device power consumption) a 135 C Typical Junction Temperature (Based on ambient temperature at a 125 C) Typical Thermal Resistance Junction-to-Ambient (iJA) PDIP 45 C W PLCC 46 C W WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability ADVANCED INFORMATION CONTACT INTEL FOR DESIGN-IN INFORMATION DC CHARACTERISTICS (TA e b 40 C to a 125 C VCC e 5V g 20% VSS e 0V) Symbol VIL VIL1 VIH VIH1 VOL Parameter Input Low Voltage Input Low Voltage EA Input High Voltage (Except XTAL1 RST EA) Input High Voltage (XTAL1 RST) Output Low Voltage (Note 5) (Ports 1 2 and 3) Min b0 5 Typ (Note 4) Max 0 2 VCC b 0 1 0 2 VCC b 0 3 VCC a 0 5 VCC a 0 5 03 0 45 10 03 0 45 10 Unit V V V V V V V V V V V V V V V V Test Conditions 0 0 2 VCC a 0 9 0 7 VCC a 0 1V IOL e 100 mA (Note 1) IOL e 1 6 mA (Note 1) IOL e 3 5 mA (Note 1 4) IOL e 200 mA (Note 1) IOL e 3 2 mA (Note 1) IOL e 7 0 mA (Note 1 4) IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA IOH e b 200 mA IOH e b 3 2 mA (Note 4) IOH e b 7 0 mA VOL1 Output Low Voltage (Note 5) (Port 0 ALE PSEN) VOH Output High Voltage (Ports 1 2 and 3) VCC b 0 3 VCC b 0 7 VCC b 1 5 VCC b 0 5 VCC b 0 7 VCC b 1 5 b 75 g 10 VOH1 Output High Voltage (Port 0 in External Bus Mode) IIL ILI ITL RRST CIO ICC Logical 0 Input Current (Ports 1 2 and 3) Input leakage Current (Port 0) Logical 1 to 0 Transition Current (Ports 1 2 and 3) RST Pulldown Resistor Pin Capacitance Power Supply Current Running at 16 20 MHz (Figure 5) Idle Mode at 16 20 MHz (Figure 5) Power Down Mode 40 10 20 25 5 15 mA VIN e 0 45V mA VILMAX k VIN k VCC mA VIN e 2V KX pF 1 MHz 25 C (Note 3) b 750 225 28 33 12 14 100 mA mA mA 8 AUTOMOTIVE 87C54 87C54-20 NOTES 1 Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the VOLs of ALE and Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations In applications where capacitance loading exceeds 100 pFs the noise pulse on the ALE signal may exceed 0 8V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch with a Schmitt Trigger Strobe input 2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0 9 VCC specification when the address lines are stabilizing 3 See Figures 6–9 for test conditions Minimum VCC for Power Down is 2V 4 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and 5V 5 Under steady state (non-transient) conditions IOL must be externally limited as follows 10mA Maximum IOL per port pin Maximum IOL per 8-bit port Port 0 26 mA Ports 1 2 and 3 15 mA 71 mA Maximum total IOL for all output pins If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 270849 – 7 ICC Max at other frequencies is given by Active Mode ICC Max e (1 25 c Osc Freq) a 8 Idle Mode ICC Max e (0 5 c Osc Freq) a 4 Where Osc Freq is in MHz ICC is in mA 270849 – 8 All other pins disconnected TCLCH e TCHCL e 5 ns Figure 7 ICC Test Condition Active Mode Figure 6 ICC vs Frequency 270849 – 9 All other pins disconnected TCLCH e TCHCL e 5 ns 270849 – 10 All other pins disconnected Figure 8 ICC Test Condition Idle Mode Figure 9 ICC Test Condition Power Down Mode VCC e 2 0V to 6 0V 270849 – 11 Figure 10 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns 9 AUTOMOTIVE 87C54 87C54-20 P PSEN Q Output Data R RD signal T Time V Valid W WR signal X No longer a valid logic level Z Float For example TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters The first character is always a ‘T’ (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input Data H Logic level HIGH I Instruction (program memory contents) L Logic level LOW or ALE AC CHARACTERISTICS (TA e b 40 C to a 125 C VCC e 5V g 20% VSS e 0V Load Capacitance for Port 0 ALE PROG and PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF) ADVANCED INFORMATION CONTACT INTEL FOR DESIGN-IN INFORMATION EXTERNAL MEMORY CHARACTERISTICS 12 MHz Oscillator Symbol Parameter Min 1 TCLCL TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address Valid to Valid Instruction In PSEN Low to Address Float 0 59 312 10 53 205 145 0 TCLCL b 25 TCLCL b 20 5 TCLCL b 105 10 127 43 53 234 TCLCL b 30 3 TCLCL b 45 3 TCLCL b 105 3 TCLCL b 90 Max Variable Oscillator 87C54 87C54-20 Min 35 2 TCLCL b 40 TCLCL b 40 TCLCL b 30 4 TCLCL b 100 4 TCLCL b 75 Max 16 20 MHz ns ns ns ns ns ns ns ns ns ns ns Units 10 AUTOMOTIVE 87C54 87C54-20 EXTERNAL MEMORY CHARACTERISTICS (Continued) 12 MHz Oscillator Symbol Parameter Min TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TWHQX TQVWH TRLAZ TWHLH RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD High Data Float After RD High ALE Low to Valid Data In Address Valid to Valid Data In ALE Low to RD or WR Low Address Valid to WR Low Data Valid before WR Low Data Hold after WR High Data Valid to WR High RD Low to Address Float RD or WR High to ALE High 43 200 203 33 33 433 0 123 TCLCL b 40 0 107 517 585 300 3 TCLCL b 50 4 TCLCL b 130 4 TCLCL b 90 TCLCL b 50 TCLCL b 35 TCLCL b 50 TCLCL b 40 7 TCLCL b 150 7 TCLCL b 70 0 TCLCL a 40 400 400 252 0 2 TCLCL b 60 8 TCLCL b 150 8 TCLCL b 90 9 TCLCL b 165 9 TCLCL b 90 3 TCLCL a 50 Max Variable Oscillator 87C54 87C54-20 Min 6 TCLCL b 100 6 TCLCL b 100 5 TCLCL b 165 5 TCLCL 95 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units NOTE Timings speicified for the 87C54-20 are valid at 20 MHz only For timings below 20 MHz use the 87C54 timings 11 AUTOMOTIVE 87C54 87C54-20 EXTERNAL PROGRAM MEMORY READ CYCLE 270849 – 12 EXTERNAL DATA MEMORY READ CYCLE 270849 – 13 EXTERNAL DATA MEMORY WRITE CYCLE 270849 – 14 12 AUTOMOTIVE 87C54 87C54-20 SERIAL PORT TIMING Test Conditions Symbol TXLXL TQVXH TXHQX TXHDX TXHDV SHIFT REGISTER MODE TA e b 40 C to a 125 C VCC e 5V g 20% VSS e 0V Load Capacitance e 80 pF 12 MHz Oscillator Min Max Variable Oscillator Min 12TCLCL 10TCLCL b 133 2TCLCL b 117 0 700 10TCLCL b 133 Max ms ns ns ns ns Units Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 1 700 50 0 SHIFT REGISTER MODE TIMING WAVEFORMS 270849 – 15 EXTERNAL CLOCK DRIVE Symbol 1 TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency 87C54 High Time Low Time Rise Time Fall Time Min 35 20 20 20 20 Max 16 20 Units MHz ns ns ns ns EXTERNAL CLOCK DRIVE WAVEFORMS 270849 – 16 13 AUTOMOTIVE 87C54 87C54-20 AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 270849 – 17 AC Inputs during testing are driven at VCC b 0 5V for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0’’ Timing measurements are made at VIH min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’ 270849 – 18 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH VOL level occurs IOL IOH t g 20 mA EPROM CHARACTERISTICS Table 3 shows the logic levels for programming the Program Memory the Encryption Table and the Lock Bits and for reading the signature bytes Table 3 EPROM Programming Modes Mode Program Code Data Verify Code Data Program Encryption Array Address 0–3FH Program Lock Bits Bit 1 Bit 2 Bit 3 Read Signature Byte RST H H H H H H H PSEN L L L L L L L H H ALE PROG EA VPP 12 75V H 12 75V 12 75V 12 75V 12 75V H P2 6 L L L H H H L P2 7 H L H H H L L P3 3 H L H H H H L P3 6 H H L H L H L P3 7 H H H H L L L DEFINITION OF TERMS ADDRESS LINES P1 0–P1 7 P2 0–P2 5 respectively for A0–A13 DATA LINES P0 0–P0 7 for D0–D7 CONTROL SIGNALS RST PSEN P2 6 P2 7 P3 3 P3 6 P3 7 PROGRAM SIGNALS ALE PROG EA VPP PROGRAMMING THE EPROM To be programmed the part must be running with a 4 MHz to 6 MHz oscillator (The reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appropriate internal EPROM locations ) The address of an EPROM location to be programmed is applied to Port 1 and pins P2 0 – P2 5 of Port 2 while the code byte to be programmed into that location is applied to Port 0 The other Port 2 and 3 pins RST PSEN and EA VPP should be held at the ‘‘Program’’ levels indicated in Table 3 ALE PROG is pulsed low to program the code byte into the addressed EPROM location The setup is shown in Figure 11 14 AUTOMOTIVE 87C54 87C54-20 Normally EA VPP is held at logic high until just before ALE PROG is to be pulsed Then EA VPP is raised to VPP ALE PROG is pulsed low and then EA VPP is returned to a valid high voltage The voltage on the EA VPP pin must be at the valid EA VPP high level before a verify is attempted Waveforms and detailed timing specifications are shown in later sections of this data sheet Note that the EA VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time Even a narrow glitch above that voltage level can cause permanent damage to the device The VPP source should be well regulated and free of glitches 270849 – 19 See Table 3 for proper input on these pins Figure 11 Programming the EPROM Quick Pulse Programming Algorithm The 87C54 can be programmed using the Quick Pulse Programming Algorithm for microcontrollers The features of the new programming method are a lower VPP (12 75V as compared to 21V) and a shorter programming pulse It is possible to program the entire 16K bytes of EPROM memory in less than 50 seconds with this algorithm To program the part using the new algorithm VPP must be 12 75V g 0 25V ALE PROG is pulsed low for 100 ms 25 times as shown in Figure 12 Then the byte just programmed may be verified After programming the entire array should be verified The Program Lock features are programmed using the same method but with the setup as shown in Table 3 The only difference in programming Program Lock features is that the Program Lock features cannot be directly verified Instead verification of programming is by observing that their features are enabled Program Verification If the Program Lock Bits have not been programmed the on-chip Program Memory can be read out for verification purposes if desired either during or after the programming operation The address of the Program Memory location to be read is applied to Port 1 and pins P2 0 – P2 5 The other pins should be held at the ‘‘Verify’’ levels indicated in Table 3 The contents of the addressed locations will come out on Port 0 External pullups are required on Port 0 for this operation If the Encryption Array in the EPROM has been programmed the data present at Port 0 will be Code Data XNOR Encryption Data The user must know the Encryption Array contents to manually ‘‘unencrypt’’ the data during verify The setup which is shown in Figure 13 is the same as for programming the EPROM except that pin P2 7 is held at a logic low or may be used as an active low read strobe 15 AUTOMOTIVE 87C54 87C54-20 270849 – 22 Figure 12 PROG Waveforms 270849 – 23 Figure 13 Verifying the EPROM 16 AUTOMOTIVE 87C54 87C54-20 PROGRAMMING ALGORITHM Refer to Table 3 and Figures 11 and 14 for address data and control signals set up To program the 87C54 the following sequence must be exercised 1 Input the valid address on the address lines 2 Input the appropriate data byte on the data lines 3 Activate the correct combination of control signals 4 Raise EA VPP from VCC to 12 75V g 0 25V 5 Pulse ALE PROG 5 times for the EPROM array and 25 times for the encryption table and the lock bits Repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached PROGRAM VERIFY Program verify may be done after each byte or block of bytes is programmed In either case a complete verify of programmed array will ensure reliable programming of the 87C54 The lock bits cannot be directly verified Verification of the lock bits is done by observing that their features are enabled Refer to the EPROM Program Lock section in this data sheet 270849 – 25 5 Pulses Figure 14 Programming Signal’s Waveforms 17 AUTOMOTIVE 87C54 87C54-20 dress lines are used to select a byte of the Encryption Array This byte is then exclusive-NOR’ed (XNOR) with the code byte creating an Encryption Verify byte The algorithm with the array in the unprogrammed state (all 1’s) will return the code in it’s original unmodified form For programming the Encryption Array refer to Table 3 (EPROM Programming Modes) EPROM Program Lock The 87C54 program lock system when programmed protect the onboard program against software piracy The 87C54 has a 3-level program lock system and a 64-byte encryption array Since this is an EPROM device all locations are user programmable See Table 4 Reading the Signature Bytes Program Lock Bits The 87C54 has 3 programmable lock bits that when programmed according to Table 4 will provide different levels of protection for the on-chip code and data See Table 3 Erasing the EPROM also erases the encryption array and the program lock bits returning the part to full functionality The 87C54 has 3 signature bytes in locations 30H 31H and 60H To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 3 for Read Signature Byte Location 30H 31H 60H Contents 87C54 89H 58H 54H Encryption Array Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1’s) Every time that a byte is addressed during a verify 6 adTable 4 Program Lock Bits and the Features Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U No Program Lock features enabled (Code verify will still be encrypted by the Encryption Array if programmed ) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on Reset and further programming of the EPROM is disabled Same as 2 also verify is disabled Same as 3 also external execution is disabled Protection Type 3 4 P P P P U P Any other combination of the lock bits is not defined 18 AUTOMOTIVE 87C54 87C54-20 EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (TA e 21 C to 27 C VCC e 5V g 20% VSS e 0V) ADVANCED INFORMATION Symbol VPP IPP 1 TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL CONTACT INTEL FOR DESIGN-IN INFORMATION Min 12 5 Max 13 0 75 4 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 10 10 90 110 48TCLCL 48TCLCL 0 10 48TCLCL ms ms ms ms 6 Units V mA MHz Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low Data Hold after PROG (Enable) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float after ENABLE PROG High to PROG Low EPROM PROGRAMMING AND VERIFICATION WAVEFORMS 270849 – 26 19 AUTOMOTIVE 87C54 87C54-20 DATA SHEET REVISION HISTORY The following are key differences between this data sheet and the -003 version of the data sheet 1 The data sheet has been revised to include the 20 MHz 87C54 The title was changed from 87C54 to 87C54 87C54-20 2 RST pin in Figure 3 has been changed to RESET pin 3 Max ICC has been corrected to reflect test program conditions 4 Figure 6 ICC vs Frequency has been changed to reflect new ICC specifications 5 87C54-20 A C Timings have been added to the External Memory Characteristics Table The following are key differences between this data sheet and the -002 version of the data sheet 1 ‘‘NC’’ pin labels changed to ‘‘Reserved’’ in Figure 3 2 Capacitor value for ceramic resonators deleted in Figure 4 3 Replaced A0–A15 with P1 0–P1 7 P2 0–P2 5 (EPROM programming and verification waveforms) 4 Replaced D0–D7 with P0 (EPROM programming and verification waveforms) The following are the key differences between the -001 and the -002 versions of this data sheet 1 The RST description has been modified to clarify the reset operation when the oscillator is not running 2 Figure 4 (Oscillator Connections) has been changed for Ceramic Resonators 3 A description of RFI Reduction Mode has been added 4 VIL IIL ITL and ICC DC Characteristics have been revised 5 AC and DC Characteristics are specified to g 10% VCC revised from g 20% VCC 20