F28F008SA-85

28F008SA 8-MBIT (1-MBIT x 8) FlashFile TM MEMORY Extended Temperature Specifications Included Y High-Density Symmetrically-Blocked Architecture Sixteen 64-Kbyte Blocks Extended Cycling Capability 100 000 Block Erase Cycles 1 6 Million Block Erase Cycles per Chip Automated Byte Write and Block Erase Command User Interface Status Register System Performance Enhancements RY BY Status Output Erase Suspend Capability Y Deep Power-Down Mode 0 20 mA ICC Typical Very High-Performance Read 85 ns Maximum Access Time SRAM-Compatible Write Interface Hardware Data Protection Feature Erase Write Lockout during Power Transitions Industry Standard Packaging 40-Lead TSOP 44-Lead PSOP ETOX III Nonvolatile Flash Technology 12V Byte Write Block Erase Y Y Y Y Y Y Y Y Intel’s 28F008SA 8-Mbit FlashFile TM Memory is the highest density nonvolatile read write solution for solid-state storage The 28F008SA’s extended cycling symmetrically blocked architecture fast access time write automation and low power consumption provide a more reliable lower power lighter weight and higher performance alternative to traditional rotating disk technology The 28F008SA brings new capabilities to portable computing Application and operating system software stored in resident flash memory arrays provide instant-on rapid execute-in-place and protection from obsolescence through in-system software updates Resident software also extends system battery life and increases reliability by reducing disk drive accesses For high density data acquisition applications the 28F008SA offers a more cost-effective and reliable alternative to SRAM and battery Traditional high density embedded applications such as telecommunications can take advantage of the 28F008SA’s nonvolatility blocking and minimal system code requirements for flexible firmware and modular software designs The 28F008SA is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write The 28F008SA memory map consists of 16 separately erasable 64-Kbyte blocks Intel’s 28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity Its 85 ns access time provides superior performance when compared with magnetic storage media A deep powerdown mode lowers power consumption to 1 mW typical thru VCC crucial in portable computing handheld instrumentation and other low-power applications The RP power control input also provides absolute data protection during system powerup down Manufactured on Intel’s 0 8 micron ETOX process the 28F008SA provides the highest levels of quality reliability and cost-effectiveness Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 November 1995 Order Number 290429-005 28F008SA The Status Register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation The RY BY output gives an additional indicator of WSM activity providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase for example) Status polling using RY BY minimizes both CPU overhead and system power consumption When low RY BY indicates that the WSM is performing a block erase or byte write operation RY BY high indicates that the WSM is ready for new commands block erase is suspended or the device is in deep powerdown mode Maximum access time is 85 ns (tACC) over the commercial temperature range (0 C to a 70 C) and over VCC supply voltage range (4 5V to 5 5V and 4 75V to 5 25V) ICC active current (CMOS Read) is 20 mA typical 35 mA maximum at 8 MHz When the CE and RP pins are at VCC the ICC CMOS Standby mode is enabled A Deep Powerdown mode is enabled when the RP pin is at GND minimizing power consumption and providing write protection ICC current in deep powerdown is 0 20 mA typical Reset time of 400 ns is required from RP switching high until outputs are valid to read attempts Equivalently the device has a wake time of 1 ms from RP high until writes to the Command User Interface are recognized by the 28F008SA With RP at GND the WSM is reset and the Status Register is cleared PRODUCT OVERVIEW The 28F008SA is a high-performance 8-Mbit (8 388 608 bit) memory organized as 1 Mbyte (1 048 576 bytes) of 8 bits each Sixteen 64-Kbyte (65 536 byte) blocks are included on the 28F008SA A memory map is shown in Figure 6 of this specification A block erase operation erases one of the sixteen blocks of memory in typically 1 6 seconds independent of the remaining blocks Each block can be independently erased and written 100 000 cycles Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the 28F008SA The 28F008SA is available in the 40-lead TSOP (Thin Small Outline Package 1 2 mm thick) and 44lead PSOP (Plastic Small Outline) packages Pinouts are shown in Figures 2 and 4 of this specification The Command User Interface serves as the interface between the microprocessor or microcontroller and the internal operation of the 28F008SA Byte Write and Block Erase Automation allow byte write and block erase operations to be executed using a two-write command sequence to the Command User Interface The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for byte write and block erase operations including verifications thereby unburdening the microprocessor or microcontroller Writing of memory data is performed in byte increments typically within 9 ms an 80% improvement over current flash memory products IPP byte write and block erase currents are 10 mA typical 30 mA maximum VPP byte write and block erase voltage is 11 4V to 12 6V 2 28F008SA Figure 1 Block Diagram 3 290429– 1 28F008SA Table 1 Pin Description Symbol A0 –A19 DQ0 –DQ7 Type INPUT INPUT OUTPUT Name and Function ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle DATA INPUT OUTPUTS Inputs data and commands during Command User Interface write cycles outputs data during memory array Status Register and Identifier read cycles The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled Data is internally latched during a write cycle CHIP ENABLE Activates the device’s control logic input buffers decoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels RESET DEEP POWERDOWN Puts the device in deep powerdown mode RP is active low RP high gates normal operation RP also locks out block erase or byte write operations when active low providing data protection during power transitions RP active resets internal automation Exit from Deep Powerdown sets device to read-array mode OUTPUT ENABLE Gates the device’s outputs through the data buffers during a read cycle OE is active low WRITE ENABLE Controls writes to the Command User Interface and array blocks WE is active low Addresses and data are latched on the rising edge of the WE pulse READY BUSY Indicates the status of the internal Write State Machine When low it indicates that the WSM is performing a block erase or byte write operation RY BY high indicates that the WSM is ready for new commands block erase is suspended or the device is in deep powerdown mode RY BY is always active and does NOT float to tri-state off when the chip is deselected or data outputs are disabled BLOCK ERASE BYTE WRITE POWER SUPPLY for erasing blocks of the array or writing bytes of each block NOTE With VPP k VPPLMAX memory contents cannot be altered DEVICE POWER SUPPLY (5V g 10% 5V g 5%) GROUND CE INPUT RP INPUT OE WE INPUT INPUT RY BY OUTPUT VPP VCC GND 4 28F008SA Standard Pinout 290429 – 2 Reverse Pinout 290429 – 3 Figure 2 TSOP Lead Configurations 5 28F008SA Figure 3 TSOP Serpentine Layout NOTE 1 Connect all VCC and GND pins of each device to common power supply outputs DO NOT leave VCC or GND inputs disconnected 6 290429– 4 28F008SA 290429 – 19 Figure 4 PSOP Lead Configuration 7 28F008SA 290429 – 5 Figure 5 28F008SA Array Interface to Intel386SL Microprocessor Superset through PI Bus (Including RY BY Masking and Selective Powerdown) for DRAM Backup during System SUSPEND Resident O S and Applications and Motherboard Solid-State Disk 8 28F008SA PRINCIPLES OF OPERATION FFFFF The 28F008SA includes on-chip write automation to manage write and erase functions The Write State Machine allows for 100% TTL-level control inputs fixed power supplies during block erasure and byte write and minimal processor overhead with RAMlike interface timings After initial device powerup or after return from deep powerdown mode (see Bus Operations) the 28F008SA functions as a read-only memory Manipulation of external memory-control pins allow array read standby and output disable operations Both Status Register and intelligent identifiers can also be accessed through the Command User Interface when VPP e VPPL This same subset of operations is also available when high voltage is applied to the VPP pin In addition high voltage on VPP enables successful block erasure and byte writing of the device All functions associated with altering memory contents byte write block erase status and intelligent identifier are accessed via the Command User Interface and verified thru the Status Register Commands are written using standard microprocessor write timings Command User Interface contents serve as input to the WSM which controls the block erase and byte write circuitry Write cycles also internally latch addresses and data needed for byte write or block erase operations With the appropriate command written to the register standard microprocessor read timings output array data access the intelligent identifier codes or output byte write and block erase status for verification Interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the 28F008SA blocks This code is copied to and executed from system RAM during actual flash memory update After successful completion of byte write and or block erase code data reads from the 28F008SA are again possible via the Read Array command Erase suspend resume capability allows system software to suspend block erase to read data and execute code from any other block F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block Figure 6 Memory Map Command User Interface and Write Automation An on-chip state machine controls block erase and byte write freeing the system processor for other tasks After receiving the Erase Setup and Erase Confirm commands the state machine controls block pre-conditioning and erase returning progress via the Status Register and RY BY output Byte write is similarly controlled after destination address and expected data are supplied The program and erase algorithms of past Intel flash memories are now regulated by the state machine including pulse repetition where required and internal verification and margining of data 9 28F008SA The first task is to write the appropriate read mode command to the Command User Interface (array intelligent identifier or Status Register) The 28F008SA automatically resets to Read Array mode upon initial device powerup or after exit from deep powerdown The 28F008SA has four control pins two of which must be logically active to obtain data at the outputs Chip Enable (CE ) is the device selection control and when active enables the selected memory device Output Enable (OE ) is the data input output (DQ0 –DQ7) direction control and when active drives data from the selected memory onto the I O bus RP and WE must also be at VIH Figure 10 illustrates read bus cycle waveforms Data Protection Depending on the application the system designer may choose to make the VPP power supply switchable (available only when memory byte writes block erases are required) or hardwired to VPPH When VPP e VPPL memory contents cannot be altered The 28F008SA Command User Interface architecture provides protection from unwanted byte write or block erase operations even when high voltage is applied to VPP Additionally all functions are disabled whenever VCC is below the write lockout voltage VLKO or when RP is at VIL The 28F008SA accommodates either design practice and encourages optimization of the processor-memory interface The two-step byte write block erase Command User Interface write sequence provides additional software write protection Output Disable With OE at a logic-high level (VIH) the device outputs are disabled Output pins (DQ0 –DQ7) are placed in a high-impedance state BUS OPERATION Flash memory reads erases and writes in-system via the local CPU All bus cycles to or from the flash memory conform to standard microprocessor bus cycles Standby CE at a logic-high level (VIH) places the 28F008SA in standby mode Standby operation disables much of the 28F008SA’s circuitry and substantially reduces device power consumption The outputs (DQ0 – DQ7) are placed in a high-impedence state independent of the status of OE If the 28F008SA is deselected during block erase or byte write the device will continue functioning and consuming normal active power until the operation completes Read The 28F008SA has three read modes The memory can be read from any of its blocks and information can be read from the intelligent identifier or Status Register VPP can be at either VPPL or VPPH Table 2 Bus Operations Mode Read Output Disable Standby Deep PowerDown Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write Notes 123 123 123 12 12 12 12345 RP VIH VIH VIH VIL VIH VIH VIH CE VIL VIL VIH X VIL VIL VIL OE VIL VIH X X VIL VIL VIH WE VIH VIH X X VIH VIH VIL A0 X X X X VIL VIH X VPP X X X X X X X DQ0–7 DOUT High Z High Z High Z 89H A2H DIN RY BY X X X VOH VOH VOH X NOTES 1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not written or erased 2 X can be VIL or VIH for control pins and addresses and VPPL or VPPH for VPP See DC Characteristics for VPPL and VPPH voltages 3 RY BY is VOL when the Write State Machine is executing internal block erase or byte write algorithms It is VOH when the WSM is not busy in Erase Suspend mode or deep powerdown mode 4 Command writes involving block erase or byte write are only successfully executed when VPP e VPPH 5 Refer to Table 3 for valid DIN during a write operation 10 28F008SA status information when accessed during write erase modes If a CPU reset occurs with no flash memory reset proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data Intel’s Flash Memories allow proper CPU initialization following a system reset through the use of the RP input In this application RP is controlled by the same RESET signal that resets the system CPU Deep Power-Down The 28F008SA offers a deep power-down feature entered when RP is at VIL Current draw thru VCC is 0 20 mA typical in deep power-down mode with current draw through VPP typically 0 1 mA During read modes RP -low deselects the memory places output drivers in a high-impedence state and turns off all internal circuits The 28F008SA requires time tPHQV (see AC Characteristics-Read-Only Operations) after return from powerdown until initial memory access outputs are valid After this wakeup interval normal operation is restored The Command User Interface is reset to Read Array and the upper 5 bits of the Status Register are cleared to value 10000 upon return to normal operation During block erase or byte write modes RP low will abort either operation Memory contents of the block being altered are no longer valid as the data will be partially written or erased Time tPHWL after RP goes to logic-high (VIH) is required before another command can be written This use of RP during system reset is important with automated write erase devices When the system comes out of reset it expects to read from the flash memory Automated flash memories provide Intelligent Identifier Operation The intelligent identifier operation outputs the manufacturer code 89H and the device code A2H for the 28F008SA The system CPU can then automatically match the device with its proper block erase and byte write algorithms The manufacturer- and device-codes are read via the Command User Interface Following a write of 90H to the Command User Interface a read from address location 00000H outputs the manufacturer code (89H) A read from address 00001H outputs the device code (A2H) It is not necessary to have high voltage applied to VPP to read the intelligent identifiers from the Command User Interface Table 3 Command Definitions Command Read Array Reset Intelligent Identifier Read Status Register Clear Status Register Erase Setup Erase Confirm Erase Suspend Erase Resume Byte Write Setup Write Alternate Byte Write Setup Write Bus First Bus Cycle Second Bus Cycle Cycles Notes Req’d Operation Address Data Operation Address Data 1 3 2 1 2 2 2 2 235 235 2 1 234 3 Write Write Write Write Write Write Write Write X X X X BA X WA WA FFH 90H 70H 50H 20H B0H 40H 10H Write Write Write Write BA X WA WA D0H D0H WD WD Read Read IA X IID SRD NOTES 1 Bus operations are defined in Table 2 2 IA e Identifier Address 00H for manufacturer code 01H for device code BA e Address within the block being erased WA e Address of memory location to be written 3 SRD e Data read from Status Register See Table 4 for a description of the Status Register bits WD e Data to be written at location WA Data is latched on the rising edge of WE IID e Data read from Intelligent Identifiers 4 Following the Intelligent Identifier command two read operations access manufacture and device codes 5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command 6 Commands other than those shown above are reserved by Intel for future device implementations and should not be used 11 28F008SA Write Writes to the Command User Interface enable reading of device data and Intelligent Identifiers They also control inspection and clearing of the Status Register Additionally when VPP e VPPH the Command User Interface controls block erasure and byte write The contents of the interface register serve as input to the internal state machine The Command User Interface itself does not occupy an addressable memory location The interface register is a latch used to store the command and address and data information needed to execute the command Erase Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased The Byte Write Setup command requires both appropriate command data and the address of the location to be written while the Byte Write command consists of the data to be written and the address of the location to be written The Command User Interface is written by bringing WE to a logic-low level (VIL) while CE is low Addresses and data are latched on the rising edge of WE Standard microprocessor write timings are used Refer to AC Write Characteristics and the AC Waveforms for Write Operations Figure 11 for specific timing parameters COMMAND DEFINITIONS When VPPL is applied to the VPP pin read operations from the Status Register intelligent identifiers or array blocks are enabled Placing VPPH on VPP enables successful byte write and block erase operations as well Device operations are selected by writing specific commands into the Command User Interface Table 3 defines the 28F008SA commands Read Array Command Upon initial device powerup and after exit from deep powerdown mode the 28F008SA defaults to Read Array mode This operation is also initiated by writing FFH into the Command User Interface Microprocessor read cycles retrieve array data The device remains enabled for reads until the Command User Interface contents are altered Once the internal Write State Machine has started a block erase or byte write operation the device will not recognize the Read Array command until the WSM has completed its operation The Read Array command is functional when VPP e VPPL or VPPH Table 4 Status Register Definitions WSMS 7 ESS 6 ES 5 BWS 4 VPPS 3 R 2 R 1 R 0 SR 7 e WRITE STATE MACHINE STATUS 1 e Ready 0 e Busy SR 6 e ERASE SUSPEND STATUS 1 e Erase Suspended 0 e Erase in Progress Completed SR 5 e ERASE STATUS 1 e Error in Block Erasure 0 e Successful Block Erase SR 4 e BYTE WRITE STATUS 1 e Error in Byte Write 0 e Successful Byte Write SR 3 e VPP STATUS 1 e VPP Low Detect Operation Abort 0 e VPP OK SR 2–SR 0 e RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register NOTES RY BY or the Write State Machine Status bit must first be checked to determine byte write or block erase completion before the Byte Write or Erase Status bit are checked for success If the Byte Write AND Erase Status bits are set to ‘‘1’’s during a block erase attempt an improper command sequence was entered Attempt the operation again If VPP low status is detected the Status Register must be cleared before another byte write or block erase operation is attempted The VPP Status bit unlike an A D converter does not provide continuous indication of VPP level The WSM interrogates the VPP level only after the byte write or block erase command sequences have been entered and informs the system if VPP has not been switched on The VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH 12 28F008SA command (20H) is first written to the Command User Interface followed by the Erase Confirm command (D0H) These commands require both appropriate sequencing and an address within the block to be erased to FFH Block preconditioning erase and verify are all handled internally by the Write State Machine invisible to the system After the two-command erase sequence is written to it the 28F008SA automatically outputs Status Register data when read (see Figure 8 Block Erase Flowchart) The CPU can detect the completion of the erase event by analyzing the output of the RY BY pin or the WSM Status bit of the Status Register When erase is completed the Erase Status bit should be checked If erase error is detected the Status Register should be cleared The Command User Interface remains in Read Status Register mode until further commands are issued to it This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased Also reliable block erasure can only occur when VPP e VPPH In the absence of this high voltage memory contents are protected against erasure If block erase is attempted while VPP e VPPL the VPP Status bit will be set to ‘‘1’’ Erase attempts while VPPL k VPP k VPPH produce spurious results and should not be attempted Intelligent Identifier Command The 28F008SA contains an Intelligent Identifier operation initiated by writing 90H into the Command User Interface Following the command write a read cycle from address 00000H retrieves the manufacturer code of 89H A read cycle from address 00001H returns the device code of A2H To terminate the operation it is necessary to write another valid command into the register Like the Read Array command the Intelligent Identifier command is functional when VPP e VPPL or VPPH Read Status Register Command The 28F008SA contains a Status Register which may be read to determine when a byte write or block erase operation is complete and whether that operation completed successfully The Status Register may be read at any time by writing the Read Status Register command (70H) to the Command User Interface After writing this command all subsequent read operations output data from the Status Register until another valid command is written to the Command User Interface The contents of the Status Register are latched on the falling edge of OE or CE whichever occurs last in the read cycle OE or CE must be toggled to VIH before further reads to update the Status Register latch The Read Status Register command functions when VPP e VPPL or VPPH Erase Suspend Erase Resume Commands The Erase Suspend command allows block erase interruption in order to read data from another block of memory Once the erase process starts writing the Erase Suspend command (B0H) to the Command User Interface requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm The 28F008SA continues to output Status Register data when read after the Erase Suspend command is written to it Polling the WSM Status and Erase Suspend Status bits will determine when the erase operation has been suspended (both will be set to ‘‘1’’) RY BY will also transition to VOH At this point a Read Array command can be written to the Command User Interface to read data from blocks other than that which is suspended The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H) at which time the WSM will continue with the erase process The Erase Suspend Status and WSM Status bits of the Status Register will be automatically cleared and RY BY will return to VOL After the Erase Resume command is written to it the 28F008SA automatically outputs Status Register data when read (see Figure 9 Erase Suspend Resume Flowchart) VPP must remain at VPPH while the 28F008SA is in Erase Suspend 13 Clear Status Register Command The Erase Status and Byte Write Status bits are set to ‘‘1’’s by the Write State Machine and can only be reset by the Clear Status Register Command These bits indicate various failure conditions (see Table 4) By allowing system software to control the resetting of these bits several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in sequence) The Status Register may then be polled to determine if an error occurred during that sequence This adds flexibility to the way the device may be used Additionally the VPP Status bit (SR 3) MUST be reset by system software before further byte writes or block erases are attempted To clear the Status Register the Clear Status Register command (50H) is written to the Command User Interface The Clear Status Register command is functional when VPP e VPPL or VPPH Erase Setup Erase Confirm Commands Erase is executed one block at a time initiated by a two-cycle command sequence An Erase Setup 28F008SA Byte Write Setup Write Commands (40H or 10H) Byte write is executed by a two-command sequence The Byte Write Setup command (40H or 10H) is written to the Command User Interface followed by a second write specifying the address and data (latched on the rising edge of WE ) to be written The WSM then takes over controlling the byte write and write verify algorithms internally After the twocommand byte write sequence is written to it the 28F008SA automatically outputs Status Register data when read (see Figure 7 Byte Write Flowchart) The CPU can detect the completion of the byte write event by analyzing the output of the RY BY pin or the WSM Status bit of the Status Register Only the Read Status Register command is valid while byte write is active When byte write is complete the Byte Write Status bit should be checked If byte write error is detected the Status Register should be cleared The internal WSM verify only detects errors for ‘‘1’’s that do not successfully write to ‘‘0’’s The Command User Interface remains in Read Status Register mode until further commands are issued to it If byte write is attempted while VPP e VPPL the VPP Status bit will be set to ‘‘1’’ Byte write attempts while VPPL k VPP k VPPH produce spurious results and should not be attempted system software flowchart for device byte write The entire sequence is performed with VPP at VPPH Byte write abort occurs when RP transitions to VIL or VPP drops to VPPL Although the WSM is halted byte data is partially written at the location where byte write was aborted Block erasure or a repeat of byte write is required to initialize this data to a known value AUTOMATED BLOCK ERASE As above the Quick-Erase algorithm of prior Intel Flash devices is now implemented internally including all preconditioning of block data WSM operation erase success and VPP high voltage presence are monitored and reported through RY BY and the Status Register Additionally if a command other than Erase Confirm is written to the device following Erase Setup both the Erase Status and Byte Write Status bits will be set to ‘‘1’’s When issuing the Erase Setup and Erase Confirm commands they should be written to an address within the address range of the block to be erased Figure 8 shows a system software flowchart for block erase Erase typically takes 1 6 seconds per block The Erase Suspend Erase Resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed A system software flowchart is shown in Figure 9 The entire sequence is performed with VPP at VPPH Abort occurs when RP transitions to VIL or VPP falls to VPPL while erase is in progress Block data is partially erased by this operation and a repeat of erase is required to obtain a fully erased block EXTENDED BLOCK ERASE BYTE WRITE CYCLING Intel has designed extended cycling capability into its ETOX flash memory technologies The 28F008SA is designed for 100 000 byte write block erase cycles on each of the sixteen 64-Kbyte blocks Low electric fields advanced oxides and minimal oxide area per cell subjected to the tunneling electric field combine to greatly reduce oxide stress and the probability of failure A 20-Mbyte solid-state drive using an array of 28F008SAs has a MTBF (Mean Time Between Failure) of 33 3 million hours(1) over 600 times more reliable than equivalent rotating disk technology DESIGN CONSIDERATIONS Three-Line Output Control The 28F008SA will often be used in large memory arrays Intel provides three control inputs to accommodate multiple memory connections Three-line control provides for a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs an address decoder should enable CE while OE should be connected to all memory devices and the system’s READ control line This assures that only selected memory devices have active outputs while deselected memory devices are in Standby Mode RP should be connected to the system Powergood signal to prevent unintended writes during system power transitions Powergood should also toggle during system reset AUTOMATED BYTE WRITE The 28F008SA integrates the Quick-Pulse programming algorithm of prior Intel Flash devices on-chip using the Command User Interface Status Register and Write State Machine (WSM) On-chip integration dramatically simplifies system software and provides processor interface timings to the Command User Interface and Status Register WSM operation internal verify and VPP high voltage presence are monitored and reported via the RY BY output and appropriate Status Register bits Figure 7 shows a (1)Assumptions 10-Kbyte file written every 10 minutes (20-Mbyte array) (10-Kbyte file) e 2 000 file writes before erase required (2000 files writes erase) c (100 000 cycles per 28F008SA block) e 200 million file writes (200 c 106 file writes) c (10 min write) c (1 hr 60 min) e 33 3 c 106 MTBF 14 28F008SA 28F008SA and returns to VOH when the WSM has finished executing the internal algorithm RY BY can be connected to the interrupt input of the system CPU or controller It is active at all times not tristated if the 28F008SA CE or OE inputs are brought to VIH RY BY is also VOH when the device is in Erase Suspend or deep powerdown modes Bus Operation Write RY BY Polling and Byte Write Block Erase RY BY is a full CMOS output that provides a hardware method of detecting byte write and block erase completion It transitions low time tWHRL after a write or erase command sequence is written to the Command Byte Write Setup Comments Data e 40H (10H) Address e Byte to be written Write Byte Write Data to be written Address e Byte to be written Standby Read Check RY BY VOH e Ready VOL e Busy or Read Status Register Check SR 7 1 e Ready 0 e Busy Toggle OE or CE to update Status Register Repeat for subsequent bytes 290429 – 6 Full status check can be done after each byte or after a sequence of bytes Write FFH after the last byte write operation to reset the device to Ready Array Mode FULL STATUS CHECK PROCEDURE Bus Operation Optional Read Command Comments CPU may already have read Status Register data in WSM Ready polling above Check SR 3 1 e VPP Low Detect Standby Standby Check SR 4 1 e Byte Write Error SR 3 MUST be cleared if set during a byte write attempt before further attempts are allowed by the Write State Machine SR 4 is only cleared by the Clear Status Register Command in cases where multiple bytes are written before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery 290429 – 7 Figure 7 Automated Byte Write Flowchart 15 28F008SA Bus Operation Write Command Erase Setup Comments Data e 20H Address e Within block to be erased Data e D0H Address e Within block to be erased Check RY BY VOH e Ready VOL e Busy or Read Status Register Check SR 7 1 e Ready 0 e Busy Toggle OE or CE to update Status Register Write Erase Standby Read Repeat for subsequent bytes Full status check can be done after each block or after a sequence of blocks Write FFH after the last block erase operation to reset the device to Ready Array Mode 290429 – 8 FULL STATUS CHECK PROCEDURE Bus Operation Optional Read Command Comments CPU may already have read Status Register data in WSM Ready polling above Check SR 3 1 e VPP Low Detect Standby Standby Check SR 4 5 Both 1 e Command Sequence Error Standby Check SR 5 1 e Block Erase Error SR 3 MUST be cleared if set during a block erase attempt before further attempts are allowed by the Write State Machine 290429 – 9 SR 5 is only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery Figure 8 Automated Block Erase Flowchart 16 28F008SA Bus Operation Write Command Erase Suspend Read Status Register Comments Data e B0H Write Data e 70H Standby Read Check RY BY VOH e Ready VOL e Busy or Read Status Register Check SR 7 1 e Ready 0 e Busy Toggle OE or CE to Update Status Register Standby Check SR 6 1 e Suspended Write Read Array Data e FFH Read Read array data from block other than that being erased Erase Resume Data e D0H Write 290429 – 10 Figure 9 Erase Suspend Resume Flowchart Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling System designers are interested in 3 supply current issues standby current levels (ISB) active current levels (ICC) and transient peaks produced by falling and rising edges Transient current magnitudes depend on of CE the device outputs’ capacitive and inductive loading Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks Each device should have a 0 1 mF ceramic capacitor connected between each VCC and GND and between its VPP and GND These high frequency low inherent-inductance capacitors should be placed as close as possible to package leads Additionally for every 8 devices a 4 7 mF electrolytic capacitor should be placed at the array’s power supply connection between VCC and GND The bulk capacitor will overcome voltage slumps caused by PC board trace inductances VPP Trace on Printed Circuit Boards Writing flash memories while they reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace The VPP pin supplies the memory cell current for writing and erasing Use similar trace widths and layout considerations given to the VCC power bus Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots 17 28F008SA ensures that the Command User Interface is reset to the Read Array mode on power up A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active Since both WE and CE must be low for a command write driving either to VIH will inhibit writes The Command User Interface architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences Finally the device is disabled until RP is brought to VIH regardless of the state of its control inputs This provides an additional level of memory protection VCC VPP RP Transitions and the Command Status Registers Byte write and block erase completion are not guaranteed if VPP drops below VPPH If the VPP Status bit of the Status Register (SR 3) is set to ‘‘1’’ a Clear Status Register command MUST be issued before further byte write block erase attempts are allowed by the WSM Otherwise the Byte Write (SR 4) or Erase (SR 5) Status bits of the Status Register will be set to ‘‘1’’s if error is detected RP transitions to VIL during byte write and block erase also abort the operations Data is partially altered in either case and the command sequence must be repeated after normal operation is restored Device poweroff or RP transitions to VIL clear the Status Register to initial value 10000 for the upper 5 bits The Command User Interface latches commands as issued by system software and is not altered by VPP or CE transitions or WSM actions Its state upon powerup after exit from deep powerdown or after VCC transitions below VLKO is Read Array Mode After byte write or block erase is complete even after VPP transitions down to VPPL the Command User Interface must be reset to Read Array mode via the Read Array command if access to the memory array is desired Power Dissipation When designing portable systems designers must consider battery power consumption not only during device operation but also for data retention during system idle time Flash nonvolatility increases usable battery life because the 28F008SA does not consume any power to retain code or data when the system is off In addition the 28F008SA’s deep powerdown mode ensures extremely low power dissipation even when system power is applied For example portable PCs and other power sensitive applications using an array of 28F008SAs for solid-state storage can lower RP to VIL in standby or sleep modes producing negligable power consumption If access to the 28F008SA is again needed the part can again be read following the tPHQV and tPHWL wakeup cycles required after RP is first raised back to VIH See AC Characteristics Read-Only and Write Operations and Figures 10 and 11 for more information Power Up Down Protection The 28F008SA is designed to offer protection against accidental block erasure or byte writing during power transitions Upon power-up the 28F008SA is indifferent as to which power supply VPP or VCC powers up first Power supply sequencing is not required Internal circuitry in the 28F008SA 18 28F008SA ABSOLUTE MAXIMUM RATINGS Operating Temperature During Read During Block Erase Byte Write Temperature Under Bias Storage Temperature Voltage on Any Pin (except VCC and VPP) with Respect to GND VPP Program Voltage with Respect to GND during Block Erase Byte Write VCC Supply Voltage with Respect to GND Output Short Circuit Current 0 C to a 70 C(1) 0 C to a 70 C b 10 C to a 80 C b 65 C to a 125 C NOTICE This data sheet contains preliminary information on new products in production The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design b 2 0V to a 7 0V(2) WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability b 2 0V to a 14 0V(2 3) b 2 0V to a 7 0V(2) 100 mA(4) NOTES 1 Operating temperature is for commercial product defined by this specification 2 Minimum DC voltage is b0 5V on input output pins During transitions this level may undershoot to b2 0V for periods k 20 ns Maximum DC voltage on input output pins is VCC a 0 5V which during transitions may overshoot to VCC a 2 0V for periods k20 ns 3 Maximum DC voltage on VPP may overshoot to a 14 0V for periods k20 ns 4 Output shorted for no more than one second No more than one output shorted at a time 5 5% VCC specifications reference the 28F008SA-85 in its High Speed configuration 10% VCC specifications reference the 28F008SA-85 in its Standard configuration and the 28F008SA-120 OPERATING CONDITIONS Symbol TA VCC VCC Parameter Operating Temperature VCC Supply Voltage (10%) VCC Supply Voltage (5%) 5 5 Notes Min 0 4 50 4 75 Max 70 5 50 5 25 Unit C V V DC CHARACTERISTICS Symbol ILI ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 13 10 30 ICCD ICCR VCC Deep PowerDown Current VCC Read Current 1 1 0 20 20 Min Typ Max g1 0 g 10 Unit mA mA mA mA mA mA Test Condition VCC e VCC Max VIN e VCC or GND VCC e VCC Max VOUT e VCC or GND VCC e VCC Max CE e RP e VIH VCC e VCC Max CE e RP e VCC g 0 2V RP e GND g 0 2V IOUT (RY BY ) e 0 mA VCC e VCC Max CE e GND f e 8 MHz IOUT e 0 mA CMOS Inputs VCC e VCC Max CE e VIL f e 8 MHz IOUT e 0 mA TTL Inputs 19 20 100 12 35 25 50 mA 28F008SA DC CHARACTERISTICS (Continued) Symbol ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPE IPPES VIL VIH VOL VOH1 VOH2 Parameter VCC Byte Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep PowerDown Current VPP Read Current VPP Byte Write Current VPP Block Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) 3 3 24 0 85 VCC VCC b 0 4 VPPL VPPH VLKO VPP during Normal Operations VPP during Erase Write Operations VCC Erase Write Lock Voltage 4 00 11 4 20 12 0 65 12 6 V V V 1 1 1 b0 5 Notes 1 1 12 1 1 Min Typ 10 10 5 g1 Max 30 30 10 g 15 Unit Test Condition mA Byte Write In Progress mA Block Erase In Progress mA Block Erase Suspended CE e VIH mA mA mA VPP s VCC RP e GND g 0 2V 0 10 50 200 VPP l VCC 10 10 90 30 30 200 08 VCC a 0 5 0 45 mA VPP e VPPH Byte Write in Progress mA VPP e VPPH Block Erase in Progress mA V V V V V VCC e VCC Min IOL e 5 8 mA VCC e VCC Min IOH e b 2 5 mA IOH e b 2 5 mA VCC e VCC Min IOH e b 100 mA VCC e VCC Min VPP e VPPH Block Erase Suspended 20 20 28F008SA EXTENDED TEMPERATURE OPERATING CONDITIONS Symbol TA VCC VCC Parameter Operating Temperature VCC Supply Voltage (10%) VCC Supply Voltage (5%) 5 5 Notes Min b 40 Max a 85 Unit C V V 4 50 4 75 5 50 5 25 DC CHARACTERISTICS EXTENDED TEMPERATURE OPERATION Symbol ILI ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 13 10 30 ICCD ICCR VCC Deep PowerDown Current VCC Read Current 1 1 0 20 20 Min Typ Max g1 0 g 10 Unit mA mA mA mA mA mA Test Condition VCC e VCC Max VIN e VCC or GND VCC e VCC Max VOUT e VCC or GND VCC e VCC Max CE e RP e VIH VCC e VCC Max CE e RP e VCC g 0 2V RP e GND g 0 2V IOUT (RY BY ) e 0 mA VCC e VCC Max CE e GND f e 8 MHz IOUT e 0 mA CMOS Inputs VCC e VCC Max CE e VIL f e 8 MHz IOUT e 0 mA TTL Inputs Byte Write In Progress Block Erase In Progress Block Erase Suspended CE e VIH VPP s VCC RP e GND g 0 2V 20 100 20 35 25 50 mA ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPE IPPES VCC Byte Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep PowerDown Current VPP Read Current VPP Byte Write Current VPP Block Erase Current VPP Erase Suspend Current 1 1 12 1 1 10 10 5 g1 30 30 10 g 15 mA mA mA mA mA mA mA mA mA 0 10 50 200 VPP l VCC VPP e VPPH Byte Write in Progress VPP e VPPH Block Erase in Progress VPP e VPPH Block Erase Suspended 1 1 1 10 10 90 30 30 200 21 28F008SA DC CHARACTERISTICS EXTENDED TEMPERATURE OPERATION (Continued) Symbol VIL VIH VOL VOH1 VOH2 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) 3 3 24 0 85 VCC VCC b 0 4 VPPL VPPH VLKO VPP during Normal Operations VPP during Erase Write Operations VCC Erase Write Lock Voltage 4 00 11 4 20 12 0 65 12 6 V V V Notes Min b0 5 Typ Max 08 VCC a 0 5 0 45 Unit V V V V V Test Condition 20 VCC e VCC Min IOL e 5 8 mA VCC e VCC Min IOH e b 2 5 mA IOH e b 2 5 mA VCC e VCC Min IOH e b 100 mA VCC e VCC Min CAPACITANCE(5) Symbol CIN COUT TA e 25 C f e 1 MHz Typ 6 8 Max 8 12 Unit pF pF Condition VIN e 0V VOUT e 0V Parameter Input Capacitance Output Capacitance NOTES 1 All currents are in RMS unless otherwise noted Typical values at VCC e 5 0V VPP e 12 0V T e 25 C These currents are valid for all product versions (packages and speeds) 2 ICCES is specified with the device deselected If the 28F008SA is read while in Erase Suspend Mode current draw is the sum of ICCES and ICCR 3 Includes RY BY 4 Block Erases Byte Writes are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL 5 Sampled not 100% tested 22 28F008SA AC INPUT OUTPUT REFERENCE WAVEFORM(1) AC TESTING LOAD CIRCUIT(1) 290429 – 11 AC test inputs are driven at VOH (2 4 VTTL) for a Logic ‘‘1’’ and VOL (0 45 VTTL) for a Logic ‘‘0’’ Input timing begins at VIH (2 0 VTTL) and VIL (0 8 VTTL) Output timing ends at VIH and VIL Input rise and fall times (10% to 90%) k 10 ns CL e 100 pF CL Includes Jig Capacitance RL e 3 3 kX 290429 – 12 HIGH SPEED AC INPUT OUTPUT REFERENCE WAVEFORM(2) HIGH SPEED AC TESTING LOAD CIRCUIT(2) 290429 – 17 AC test inputs are driven at 3 0V for a Logic ‘‘1’’ and 0 0V for a Logic ‘‘0’’ Input timing begins and output timing ends at 1 5V Input rise and fall times (10% to 90%) k 10 ns CL e 30 pF CL Includes Jig Capacitance RL e 3 3 kX 290429 – 18 NOTES 1 Testing characteristics for 28F008SA-85 in Standard configuration and 28F008SA-120 2 Testing characteristics for 28F008SA-85 in High Speed configuration AC CHARACTERISTICS Versions Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tRC tACC tCE tPWH tOE tLZ tHZ tOLZ tDF tOH Parameter Read Cycle Time Read-Only Operations(1) VCC g 5% VCC g 10% Notes Min 85 85 2 85 400 2 3 3 3 3 3 0 0 30 0 0 55 0 30 0 40 0 55 0 30 Max 28F008SA-85(4) 28F008SA-85(5) Min 90 90 90 400 45 0 55 Max 28F008SA-120(5) Min 120 120 120 400 50 Max ns ns ns ns ns ns ns ns ns ns Unit Address to Output Delay CE RP OE CE CE OE OE to Output Delay High to Output Delay to Output Delay to Output Low Z High to Output High Z to Output Low Z High to Output High Z Output Hold from Addresses CE or OE Change Whichever is First NOTES 1 See AC Input Output Reference Waveform for timing measurements 2 OE may be delayed up to tCE – tOE after the falling edge of CE without impact on tCE 3 Sampled not 100% tested 4 See High Speed AC Input Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics 5 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics 23 28F008SA EXTENDED TEMPERATURE OPERATION AC CHARACTERISTICS Read-Only Operations(1) Versions Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tRC tACC tCE tPWH tOE tLZ tHZ tOLZ tDF tOH Read Cycle Time Address to Output Delay CE RP OE CE CE OE OE to Output Delay High to Output Delay to Output Delay to Output Low Z High to Output High Z to Output Low Z High to Output High Z or 2 3 3 3 3 3 0 0 30 0 55 2 Parameter VCC g 10% Notes 28F008SA-100(5) Min 100 100 100 400 55 Max ns ns ns ns ns ns ns ns ns ns Unit Output Hold from Addresses CE OE Change Whichever is First NOTES 1 See AC Input Output Reference Waveform for timing measurements 2 OE may be delayed up to tCE – tOE after the falling edge of CE without impact on tCE 3 Sampled not 100% tested 4 See High Speed AC Input Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics 5 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics 24 28F008SA Figure 10 AC Waveform for Read Operations 25 290429– 13 28F008SA AC CHARACTERISTICS Versions Symbol tAVAV tPHWL tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHQV1 tWHQV2 tWHGL tQVVL tVPH tWC tPS tCS tWP tVPS tAS tDS tDH tAH tCH tWPH Parameter Write Cycle Time Write Operations(1) VCC g 5% VCC g 10% Notes Min 85 2 1 10 40 Going 2 3 4 100 40 40 5 5 10 30 100 56 56 6 03 0 26 0 6 03 0 0 Max 28F008SA-85(7) 28F008SA-85(8) Min 90 1 10 40 100 40 40 5 5 10 30 100 6 03 0 0 Max 28F008SA-120(8) Min 120 1 10 40 100 40 40 5 5 10 30 100 Max ns ms ns ns ns ns ns ns ns ns ns ns ms sec ms ns Unit RP High Recovery to WE Going Low CE Setup to WE Low WE Pulse Width Going VPP Setup to WE High Address Setup to WE Going High Data Setup to WE High Data Hold from WE Going High Address Hold from WE High CE WE Hold from WE High Pulse Width High WE High to RY BY Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read VPP Hold from Valid SRD RY BY High NOTES 1 Read timing characteristics during erase and byte write operations are the same as during read-only operations Refer to AC Characteristics for Read-Only Operations 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte write or block erasure 4 Refer to Table 3 for valid DIN for byte write or block erasure 5 The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory including byte program and verify (byte write) and block precondition precondition verify erase and erase verify (block erase) 6 Byte write and block erase durations are measured to completion (SR 7 e 1 RY BY e VOH) VPP should be held at VPPH until determination of byte write block erase success (SR 3 4 5 e 0) 7 See High Speed AC Input Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics 8 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics 26 28F008SA BLOCK ERASE AND BYTE WRITE PERFORMANCE Parameter Block Erase Time Block Write Time Byte Write Time Notes 2 2 28F008SA-85 Min Typ(1) 16 06 8 Max 10 21 (Note 3) Min 28F008SA-120 Typ(1) 16 06 8 Max 10 21 (Note 3) Unit sec sec ms NOTES 1 25 C 12 0 VPP 2 Excludes System-Level Overhead 3 Contact your Intel representative for information on the maximum byte write specification EXTENDED TEMPERATURE OPERATION AC CHARACTERISTICS Write Operations(1) Versions Symbol tAVAV tPHWL tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHQV1 tWHQV2 tWHGL tQVVL tVPH tWC tPS tCS tWP tVPS tAS tDS tDH tAH tCH tWPH Write Cycle Time RP CE WE High Recovery to WE Setup to WE Pulse Width Going High Going High 2 3 4 Going Low 2 Parameter VCC g 10% Notes 28F008SA-100(8) Min 100 1 10 40 100 40 40 5 5 10 30 Going Low 56 56 6 03 0 High 26 0 100 Max ns ms ns ns ns ns ns ns ns ns ns ns ms sec ms ns Unit Going Low VPP Setup to WE Address Setup to WE Data Setup to WE Data Hold from WE Going High High High Address Hold from WE CE WE WE Hold from WE High Pulse Width High High to RY BY Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read VPP Hold from Valid SRD RY BY NOTES 1 Read timing characteristics during erase and byte write operations are the same as during read-only operations Refer to AC Characteristics for Read-Only Operations 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte write or block erasure 4 Refer to Table 3 for valid DIN for byte write or block erasure 5 The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory including byte program and verify (byte write) and block precondition precondition verify erase and erase verify (block erase) 6 Byte write and block erase durations are measured to completion (SR 7 e 1 RY BY e VOH) VPP should be held at VPPH until determination of byte write block erase success (SR 3 4 5 e 0) 7 See High Speed AC Input Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics 8 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics 27 28F008SA EXTENDED TEMPERATURE OPERATION BLOCK ERASE AND BYTE WRITE PERFORMANCE Parameter Block Erase Time Block Write Time Byte Write Time NOTES 1 25 C 12 0 VPP 2 Excludes System-Level Overhead 3 Contact your Intel representative for information on the maximum byte write specification Notes 2 2 28F008SA-100 Min Typ(1) 16 06 8 Max 10 21 (Note 3) Unit sec sec ms 28 28F008SA Figure 11 AC Waveform for Write Operations 29 290429– 14 28F008SA ALTERNATIVE CE -CONTROLLED WRITES Versions Symbol tAVAV tPHEL tWLEL tELEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHQV1 tEHQV2 tEHGL tQVVL tVPH tWC tPS tWS tCP tVPS tAS tDS tDH tAH tWH tEPH Parameter Write Cycle Time RP CE High Recovery to Going Low Going 2 VCC g 5% VCC g 10% Notes Min 85 1 0 50 Going 2 3 4 100 40 40 5 5 0 25 100 5 5 6 03 0 25 0 6 03 0 0 Max 28F008SA-85(6) 28F008SA-85(7) Min 90 1 0 50 100 40 40 5 5 0 25 100 6 03 0 0 Max 28F008SA-120(7) Min 120 1 0 50 100 40 40 5 5 0 25 100 Max ns ms ns ns ns ns ns ns ns ns ns ns ms sec ms ns Unit WE Setup to CE Low CE Pulse Width VPP Setup to CE High Address Setup to CE Going High Data Setup to CE High Data Hold from CE Going High Address Hold from CE High WE CE Hold from CE High Pulse Width High CE High to RY BY Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read VPP Hold from Valid SRD RY BY High NOTES 1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where CE defines the write pulsewidth (within a longer WE timing waveform) all setup hold and inactive WE times should be measured relative to the CE waveform 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte write or block erasure 4 Refer to Table 3 for valid DIN for byte write or block erasure 5 Byte write and block erase durations are measured to completion (SR 7 e 1 RY BY e VOH) VPP should be held at VPPH until determination of byte write block erase success (SR 3 4 5 e 0) 6 See High Speed AC Input Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics 7 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics 30 28F008SA EXTENDED TEMPERATURE OPERATION ALTERNATIVE CE -CONTROLLED WRITES Versions Symbol tAVAV tPHEL tWLEL tELEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHQV1 tEHQV2 tEHGL tQVVL tVPH tWC tPS tWS tCP tVPS tAS tDS tDH tAH tWH tEPH Write Cycle Time RP WE CE High Recovery to CE Setup to CE Pulse Width Going High Going High 2 3 4 Going Low 2 Parameter VCC g 10% Notes 28F008SA-100(7) Min 100 1 0 50 100 40 40 5 5 0 25 Going Low 5 5 6 03 0 High 25 0 100 Max ns ms ns ns ns ns ns ns ns ns ns ns ms sec ms ns Unit Going Low VPP Setup to CE Address Setup to CE Data Setup to CE Data Hold from CE Going High High High Address Hold from CE WE CE CE Hold from CE High Pulse Width High High to RY BY Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read VPP Hold from Valid SRD RY BY NOTES 1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where CE defines the write pulsewidth (within a longer WE timing waveform) all setup hold and inactive WE times should be measured relative to the CE waveform 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte write or block erasure 4 Refer to Table 3 for valid DIN for byte write or block erasure 5 Byte write and block erase durations are measured to completion (SR 7 e 1 RY BY e VOH) VPP should be held at VPPH until determination of byte write block erase success (SR 3 4 5 e 0) 6 See High Speed AC Input Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics 7 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics 31 28F008SA Figure 12 Alternate AC Waveform for Write Operations 32 290429– 15 28F008SA ORDERING INFORMATION 290429 – 16 VALID COMBINATIONS E28F008SA-85 F28F008SA-85 E28F008SA-120 F28F008SA-120 PA28F008SA-85 PA28F008SA-120 TE28F008SA-100 TF28F008SA-100 TB28F008SA-100 ADDITIONAL INFORMATION Order Number 290435 271296 292094 292095 292099 294011 290412 AP-359 AP-360 AP-364 ER-27 ER-28 28F008SA-L Datasheet ‘‘28F008SA 8-Mbit (1-Mbit x 8) Flash Memory SmartDie TM Product Specification’’ ‘‘28F008SA Hardware Interfacing’’ ‘‘28F008SA Software Drivers’’ ‘‘28F008SA Automation and Algorithms’’ ‘‘The Intel 28F008SA Flash Memory’’ ‘‘ETOX TM III Flash Memory Technology’’ REVISION HISTORY Number 002 Description Revised from Advanced Information to Preliminary Modified Erase Suspend Flowchart Removed -90 speed bin Integrated -90 characteristics into -85 speed bin Combined VPP Standby current and VPP Read current into one VPP Standby current spec with two test conditions (DC Characteristics table) Lowered VLKO from 2 2V to 2 0V PWD renamed to RP for JEDEC standardization compatibility Changed IPPS Standby current spec from g 10 mA to g 15 mA in DC Characteristics table Added Extended Temperature Specs for 28F008SA Added IPPR Spec Corrected IPPS Spec Type Added VOHZ (Output High Voltage CMOS) Spec Added Byte Write Time Spec 004 005 33