GE28F320J3C-125

Intel StrataFlash® Memory (J3) 256-Mbit (x8/x16) Datasheet Product Features ■ ■ ■ Performance — 110/115/120/150 ns Initial Access Speed — 125 ns Initial Access Speed (256 Mbit density only) — 25 ns Asynchronous Page mode Reads — 30 ns Asynchronous Page mode Reads (256Mbit density only) — 32-Byte Write Buffer —6.8 µs per byte effective programming time Software — Program and Erase suspend support — Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Security — 128-bit Protection Register —64-bit Unique Device Identifier —64-bit User Programmable OTP Cells — Absolute Protection with VPEN = GND — Individual Block Locking — Block Erase/Program Lockout during Power Transitions ■ ■ ■ Architecture — Multi-Level Cell Technology: High Density at Low Cost — High-Density Symmetrical 128-Kbyte Blocks —256 Mbit (256 Blocks) (0.18µm only) —128 Mbit (128 Blocks) —64 Mbit (64 Blocks) —32 Mbit (32 Blocks) Quality and Reliability — Operating Temperature: -40 °C to +85 °C — 100K Minimum Erase Cycles per Block — 0.18 µm ETOX™ VII Process (J3C) — 0.25 µm ETOX™ VI Process (J3A) Packaging and Voltage — 56-Lead TSOP Package — 64-Ball Intel® Easy BGA Package — Lead-free packages available — 48-Ball Intel® VF BGA Package (32 and 64 Mbit) (x16 only) — VCC = 2.7 V to 3.6 V — VCCQ = 2.7 V to 3.6 V Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash® Memory (J3) device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bitper-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging. By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash® memory (28F640J5 and 28F320J5) devices. J3 memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash® memory devices. Manufactured on Intel® 0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device provides the highest levels of quality and reliability. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number: 290667-021 March 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 3 Volt Intel StrataFlash® Memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 2 Datasheet Contents Contents 1.0 Introduction ....................................................................................................................................7 1.1 1.2 2.0 2.1 2.2 3.0 3.1 3.2 3.3 4.0 4.1 4.2 4.3 4.4 5.0 5.1 5.2 6.0 6.1 6.2 7.0 7.1 7.2 7.3 7.4 7.5 7.6 8.0 8.1 8.2 8.3 9.0 9.1 Nomenclature .......................................................................................................................7 Conventions..........................................................................................................................7 Block Diagram ......................................................................................................................9 Memory Map .......................................................................................................................10 56-Lead TSOP Package .....................................................................................................11 Easy BGA (J3) Package .....................................................................................................12 VF-BGA (J3) Package ........................................................................................................13 Easy BGA Ballout (32/64/128/256 Mbit) .............................................................................14 56-Lead TSOP (32/64/128/256 Mbit)..................................................................................15 VF BGA Ballout (32 and 64 Mbit) .......................................................................................15 Signal Descriptions .............................................................................................................16 Absolute Maximum Ratings ................................................................................................18 Operating Conditions ..........................................................................................................18 DC Current Characteristics .................................................................................................19 DC Voltage Characteristics.................................................................................................20 Read Operations.................................................................................................................22 Write Operations .................................................................................................................26 Block Erase, Program, and Lock-Bit Configuration Performance .......................................27 Reset Operation..................................................................................................................29 AC Test Conditions.............................................................................................................29 Capacitance ........................................................................................................................30 Power-Up/Down Characteristics.........................................................................................31 Power Supply Decoupling...................................................................................................31 Reset Characteristics..........................................................................................................31 Bus Operations Overview ...................................................................................................32 9.1.1 Bus Read Operation ..............................................................................................33 9.1.2 Bus Write Operation ..............................................................................................33 9.1.3 Output Disable .......................................................................................................33 9.1.4 Standby..................................................................................................................34 9.1.5 Reset/Power-Down ................................................................................................34 Functional Overview .....................................................................................................................8 Package Information ...................................................................................................................11 Ballout and Signal Descriptions ................................................................................................14 Maximum Ratings and Operating Conditions ...........................................................................18 Electrical Specifications .............................................................................................................19 AC Characteristics ......................................................................................................................22 Power and Reset Specifications ................................................................................................31 Bus Operations ............................................................................................................................32 Datasheet 3 Contents 9.2 Device Commands ............................................................................................................. 35 10.0 Read Operations .......................................................................................................................... 37 10.1 Read Array.......................................................................................................................... 37 10.1.1 Asynchronous Page Mode Read ........................................................................... 37 10.1.2 Enhanced Configuration Register (ECR)............................................................... 38 Read Identifier Codes ......................................................................................................... 39 10.2.1 Read Status Register............................................................................................. 39 Read Query/CFI.................................................................................................................. 41 Byte/Word Program ............................................................................................................ 42 Write to Buffer..................................................................................................................... 42 Program Suspend............................................................................................................... 43 Program Resume................................................................................................................ 43 Block Erase......................................................................................................................... 44 Block Erase Suspend ......................................................................................................... 44 Erase Resume .................................................................................................................... 45 Set Block Lock-Bit............................................................................................................... 46 Clear Block Lock-Bits.......................................................................................................... 46 Protection Register Program .............................................................................................. 47 13.3.1 Reading the Protection Register............................................................................ 47 13.3.2 Programming the Protection Register.................................................................... 47 13.3.3 Locking the Protection Register............................................................................. 47 Array Protection .................................................................................................................. 49 Set Read Configuration Register Command ...................................................................... 50 Status (STS) ....................................................................................................................... 50 10.2 10.3 11.1 11.2 11.3 11.4 12.1 12.2 12.3 13.1 13.2 13.3 11.0 Programming Operations ........................................................................................................... 42 12.0 Erase Operations ......................................................................................................................... 44 13.0 Security Modes ............................................................................................................................ 46 13.4 14.1 14.2 14.0 Special Modes.............................................................................................................................. 50 Appendix A Common Flash Interface .................................................................................................52 Appendix B Flow Charts ......................................................................................................................59 Appendix C Design Considerations ...................................................................................................68 Appendix D Additional Information ....................................................................................................70 Appendix E Ordering Information .......................................................................................................71 4 Datasheet Contents Revision History Date of Revision 07/07/99 08/03/99 09/07/99 Version -001 -002 -003 Original Version A0–A2 indicated on block diagram Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode currents. Modified RP# on AC Waveform for Write Operations Changed Block Erase time and tAVWH Removed all references to 5 V I/O operation Corrected Ordering Information, Valid Combinations entries 12/16/99 -004 Changed Min program time to 211 µs Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart Added Program Max time Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter table Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2 03/16/00 -005 Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed VOL of 0.45 V; Removed VOH of 2.4 V Updated ICCR Typ values Added Max lock-bit program and lock times Added note on max measurements Updated cover sheet statement of 700 million units to one billion 06/26/00 -006 Corrected Table 10 to show correct maximum program times Corrected error in Max block program time in section 6.7 Corrected typical erase time in section 6.7 Updated cover page to reflect 100K minimum erase cycles Updated cover page to reflect 110 ns 32M read speed Removed Set Read Configuration command from Table 4 Updated Table 8 to reflect reserved bits are 1-7; not 2-7 Updated Table 16 bit 2 definition from R to PSS 2/15/01 -007 Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC Characteristics Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5, AC Characteristics–Read-Only Operations (1,2) Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section 6.6, AC Characteristics–Write Operations Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75 µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance Description (1,2,3) 04/13/01 -008 Revised Section 7.0, Ordering Information Datasheet 5 Contents Date of Revision Version Description Added Figure 4, 3 Volt Intel StrataFlash® Memory VF BGA Package (32 Mbit) Added Figure 5, 3 Volt Intel StrataFlash® Memory VF BGA Mechanical Specifications Updated Operating Temperature Range to Extended (Section 6.1 and Table 22) 07/27/01 -009 Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns Added parameter values for –40 °C operation to Lock-Bit and Suspend Latency Updated VLKO and VPENLK to 2.2 V Removed Note #4, Section 6.4 and Section 6.6 Minor text edits Added notes under lead descriptions for VF BGA Package Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics 10/31/01 -010 Removed byte mode read current row un DC characteristics Added ordering information for VF BGA Package Minor text edits Changed datasheet to reflect the best known methods Updated max value for Clear Block Lock-Bits time Minor text edits Added nomenclature for J3C (0.18 µm) devices. Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128 Mb J3C device. Added “TE” package designator for J3C TSOP package. Revised Asynchronous Page Read description. Revised Write-to-Buffer flow chart. Updated timing waveforms. Added 256-Mbit J3C pinout. Added 256Mbit device timings, device ID, and CFI information. Also corrected VLKO specification. Corrected memory block count from 257 to 255. Memory block count fix. Restructured the datasheet layout. Added lead-free part numbers and 8-word page information. Added Note to DC Voltage Characteristics table; “Speed Bin” to Read Operations table; Corrected format for AC Waveform for Reset Operation figure; Corrected “R” and “8W” headings in Enhanced Configuration Register table because they were transposed; Added 802 and 803 to ordering information and corrected 56Lead TSOP combination number. Corrected ordering information. 03/21/02 -011 12/12/02 01/24/03 12/09/03 1/3/04 1/23/04 1/23/04 5/19/04 7/7/04 -012 -013 -014 -015 -016 -016 -018 -019 11/23/04 -020 3/24/05 -021 6 Datasheet 256-Mbit J3 (x8/x16) 1.0 Introduction This document describes the Intel StrataFlash® Memory (J3) device. It includes a description of device features, operations, and specifications. 1.1 Nomenclature AMIN: AMAX: AMIN = A0 for x8 AMIN = A1 for x16 32 Mbit AMAX = A21 64 Mbit AMAX = A22 128 Mbit AMAX = A23 256 Mbit AMAX = A24 A group of flash cells that share common erase circuitry and erase simultaneously Indicates a logic zero (0) Command User Interface Multi-Level Cell One Time Programmable Protection Lock Register Protection Register Protection Register Data To write data to the flash array Reserved for Future Use Indicates a logic one (1) Status Register Status Register Data Refers to a signal or package connection name Refers to timing or voltage levels Write State Machine Extended Configuration Register eXtended Status Register Block: Clear: CUI: MLC: OTP: PLR: PR: PRD Program: RFU: Set: SR: SRD: VPEN: VPEN: WSM: ECR: XSR: 1.2 Conventions 0x: 0b: k (noun): M (noun): Nibble Byte: Word: Kword: Kb: KB: Mb: MB: Brackets: Hexadecimal prefix Binary prefix 1,000 1,000,000 4 bits 8 bits 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e., A[21:1], SR[4,1] and D[15:0]). Datasheet 7 256-Mbit J3 (x8/x16) 2.0 Functional Overview The Intel StrataFlash® memory family contains high-density memories organized as 32 Mbytes or 16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundredtwenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixtyfour 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks. A 128-bit Protection Register has multiple uses, including unique flash device identification. The device’s optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second— independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes. Blocks are selectively and individually lockable in-system.Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands). The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lockbit configuration. STS-high indicates that the WSM is ready for a new command, block erase is 8 Datasheet 256-Mbit J3 (x8/x16) suspended (and programming is inactive), program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are used to enable and disable the device. A unique CE logic design (see Table 13, “Chip Enable Truth Table” on page 33) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4chip miniature card or SIMM module. The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A device block diagram is shown in Figure 4 on page 14. When the device is disabled (see Table 13 on page 33), with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# going high until data outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and the Status Register is cleared. 2.1 Block Diagram Figure 1. 3 Volt Intel StrataFlash® Memory Block Diagram D[15:0] VCCQ Output Buffer Input Buffer Query Output Latch/Multiplexer Write Buffer Identifier Register Status Register I/O Logic Data Register CE Logic VCC BYTE# CE0 CE1 CE2 WE# OE# RP# Command User Interface A[2:0] Multiplexer Data Comparator Y-Decoder A[MAX:MIN] Input Buffer Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 128-Kbyte Blocks Write State Machine Program/Erase Voltage Switch STS VPEN Address Latch Address Counter X-Decoder VCC GND Datasheet 9 256-Mbit J3 (x8/x16) 2.2 Memory Map Figure 2. Intel StrataFlash® Memory (J3) Memory Map A[24-0]: 256 Mbit A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit 1FFFFFF A[24-1]: 256 Mbit A [23-1]: 128 Mbit A [22-1]: 64 Mbit A [21-1]: 32 Mbit FFFFFF 128-Kbyte Block 1FE0000 255 64-Kword Block FF0000 255 0FFFFFF 0FE0000 128-Kbyte Block 7FFFFF 127 7F0000 64-Kword Block 127 07FFFFF 3FFFFF 128-Kbyte Block 07E0000 63 3F0000 64-Kword Block 63 128-Kbyte Block 31 1F0000 64-Kword Block 31 03E0000 003FFFF 01FFFF 128-Kbyte Block 0020000 001FFFF 0000000 1 010000 00FFFF 0 000000 64-Kword Block 64-Kword Block 1 0 128-Kbyte Block Byte-Wide (x8) Mode Word Wide (x16) Mode 10 32-Mbit 64-Mbit 03FFFFF 1FFFFF Datasheet 1 28-Mbit 256-Mbit 256-Mbit J3 (x8/x16) 3.0 3.1 Package Information 56-Lead TSOP Package Figure 3. 56-Lead TSOP Package Drawing and Specifications Z See Notes 1 and 3 Pin 1 See Note 2 A2 e E See Detail B Y D1 D A1 Seating Plane See Detail A A Detail A Detail B C 0 b L Table 1. 56-Lead TSOP Dimension Table Millimeters Sym Min Nom Max 1.200 0.050 0.965 0.100 0.100 18.200 13.800 0.995 0.150 0.150 18.400 14.000 0.500 19.800 0.500 20.00 0.600 56 0° 3° 5° 0.100 0.150 0.250 0.350 0.006 0.010 0° 20.200 0.700 0.780 0.020 1.025 0.200 0.200 18.600 14.200 4 4 0.002 0.038 0.004 0.004 0.717 0.543 0.039 0.006 0.006 0.724 0.551 0.0197 0.787 0.024 56 3° 5° 0.004 0.014 0.795 0.028 0.040 0.008 0.008 0.732 0.559 4 4 Notes Min Inches Nom Max 0.047 Notes Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset A A1 A2 b c D1 E e D L N ∅ Y Z Datasheet 11 256-Mbit J3 (x8/x16) 3.2 Easy BGA (J3) Package Figure 4. Intel StrataFlash® Memory (J3) Easy BGA Mechanical Specifications Ball A1 Corner Ball A1 Corner S1 D 1 A B C D E E F G H 2 3 4 5 6 7 8 A B C D E F G 8 7 6 5 4 3 2 1 S2 b e H Top View - Ball side down Bottom View - Ball Side Up A1 A2 A Seating Plane Y Note: Drawing not to scale Table 2. Easy BGA Package Dimensions Millimeters Symbol Min Nom Max 1.200 0.250 0.780 0.330 9.900 12.900 14.900 0.430 10.000 13.000 15.000 1.000 64 0.100 1.400 2.900 3.900 1.500 3.000 4.000 1.600 3.100 4.100 1 1 1 0.0551 0.1142 0.1535 0.0591 0.1181 0.1575 0.530 10.100 13.100 15.100 1 1 1 0.0130 0.3898 0.5079 0.5866 0.0098 0.0307 0.0169 0.3937 0.5118 0.5906 0.0394 64 0.0039 0.0630 0.1220 0.1614 0.0209 0.3976 0.5157 0.5945 Notes Min Inches Nom Max 0.0472 Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width (32 Mb, 64 Mb, 128 Mb, 256 Mb) Package Body Length (32 Mb, 64 Mb, 128 Mb) Package Body Length (256 Mb) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D (32/64/128/256 Mb) Corner to Ball A1 Distance Along E (32/64/128 Mb) Corner to Ball A1 Distance Along E (256 Mb) A A1 A2 b D E E [e] N Y S1 S2 S2 NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information see www.intel.com/design/packtech/index.htm 12 Datasheet 256-Mbit J3 (x8/x16) 3.3 VF-BGA (J3) Package Figure 5. Intel StrataFlash® Memory (J3) VF BGA Mechanical Specifications B a ll A 1 C o rn e r D S1 B all A1 C o rn e r S2 1 A B C E D E F 2 3 4 5 6 7 8 A B C D E F b e 8 7 6 5 4 3 2 1 T o p V ie w - B u m p S id e D o w n B o tt o m V ie w - B a ll S id e U p A1 A2 A S e a t in g P la n e S id e V ie w N o te : D r a w in g n o t t o s ca le Y D im e n s io n s T a b le M illim e te rs In ch es Sym b ol M in Nom M a x N o te s M in Pa c k a g e H e ig h t A 1.000 0 .1 5 0 0 .0 0 5 9 Ba ll H e ig h t A1 Pa c k a g e B o d y T h ic k n e s s A2 0 .6 6 5 Ba ll (L e a d ) W id th b 0 .3 2 5 0 .3 7 5 0.425 0 .0 1 2 8 D 7 .1 8 6 7 .2 8 6 7.386 1 0 .2 8 2 9 Pa c k a g e B o d y L e n g t h E 1 0 .7 5 0 10.850 1 0 .9 5 0 1 0 .4 2 3 2 Pitc h [e] 0 .7 5 0 Ba ll (L e a d ) C o u n t N 48 Se a tin g P la n e C o p la n a r ity Y 0.100 Co r n e r to B a ll A 1 D is ta n c e A lo n g D S1 0 .9 1 8 1 .0 1 8 1.118 1 0 .0 3 6 1 Co r n e r to B a ll A 1 D is ta n c e A lo n g E S2 3 .4 5 0 3 .5 5 0 3.650 1 0 .1 3 5 8 N o te : ( 1 ) P a c k a g e d im e n s io n s a re f o r r e f e re n c e o n ly . T h e s e d im e n s io n s a re e s t im a te s b a s e d o n d ie s iz e , a n d a r e su bj e c t t o c h a ng e . N om M ax 0 .0 3 9 4 0 .0 2 6 2 0 .0 1 4 8 0 .2 8 6 8 0 .4 2 7 2 0 .0 2 9 5 48 0 .0 4 0 1 0 .1 3 9 8 0 .0 1 6 7 0 .2 9 0 8 0 .4 3 1 1 0 .0 0 3 9 0 .0 4 4 0 0 .1 4 3 7 NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm Datasheet 13 256-Mbit J3 (x8/x16) 4.0 Ballout and Signal Descriptions Intel StrataFlash® memory is available in three package types. Each density of the J3C is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. A 48-ball VF BGA package is available on 32 and 64 Mbit devices. Figure 6, Figure 7, and Figure 8 show the pinouts. 4.1 Easy BGA Ballout (32/64/128/256 Mbit) Figure 6. Intel StrataFlash® Memory Easy BGA Ballout (32/64/128/256 Mbit) 1 A A1 B A2 C A3 D A4 E D8 F BYTE# D0 G A23 128M H CE2# RFU VCC VSS D13 VSS Easy BGA Top View- Ball side down D7 A24 256M A24 D7 256M VSS D13 VSS VCC RFU CE2# Easy BGA Bottom View- Ball side up A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23 128M H D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE# G D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8 F A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4 E A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3 D VSS A9 CEO# A14 RFU A19 CE1# CE1# A19 RFU A14 CEO# A9 VSS A2 C A6 A8 VPEN A13 VCC A18 A22 A22 A18 VCC A13 VPEN A8 A6 A1 B 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A NOTES: 1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC). 2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC). 3. Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC). 14 Datasheet 256-Mbit J3 (x8/x16) 4.2 56-Lead TSOP (32/64/128/256 Mbit) Figure 7. Intel StrataFlash® Memory 56-Lead TSOP (32/64/128/256 Mbit) 3 Volt Intel StrataFlash Memory 28F160S3 NC CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 28F320J5 NC CE1 A21 A20 A19 A18 A17 A16 VCC(4) A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 32/64/128M A22(1) CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3 Volt Intel StrataFlash Memory 32/64/128M A24(3) WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# A23(2) CE2 28F320J5 NC WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC(4) DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 28F160S3 WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC 3 Volt Intel StrataFlash® Memory 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View Highlights pinout changes NOTES: 1. A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this signal is a no-connect (NC). 2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC). 3. A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this signal is a no-connect (NC). 4. VCC = 5 V ± 10% for the 28F640J5/28F320J5. 4.3 VF BGA Ballout (32 and 64 Mbit) Figure 8. Intel StrataFlash® Memory VF BGA Ballout (32 and 64 Mbit) 1 A A 14 B A5 1 C A 16 D A 17 E 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A 12 A 9 VE PN VC C A0 2 A 8 A 5 A 5 A 8 A0 2 VC C VE PN A 9 A2 1 A 14 B A1 1 W# E R# P A9 1 A 18 A 6 A 3 A 3 A 6 A8 1 A 19 R# P W# E A 11 A 15 C A3 1 A 10 A2 2 A1 2 A 7 A 4 A 2 A 2 A 4 A 7 A1 2 A 22 A0 1 A 13 A6 1 D D 14 D 5 D1 1 D 2 D 8 C# E A 1 A 1 C# E D 8 D 2 D1 1 D 5 D 14 A7 1 E VC CQ D 15 F VS S D 7 D 6 D2 1 D 3 D 9 D 0 VS S VS S D 0 D 9 D 3 D2 1 D 6 D 15 VC CQ F D 13 D 4 VC C D0 1 D 1 O# E O# E D 1 D0 1 VC C D 4 D 13 D 7 VS S V B A6 8 FG x T pV w- B ll S eD w o ie a id o n V B A6x FG 8 B tto V w- B S eU o m ie all id p NOTES: 1. CE# is equivalent to CE0, and CE1 and CE2 are internally grounded. 2. A22 exists on the 64 Mb density only. On the 32-Mbit density, this signal is a no-connect (NC). 3. STS not supported in this package. 4. x8 not supported in this package. Datasheet 15 256-Mbit J3 (x8/x16) 4.4 Signal Descriptions Table 3 describes active signals used. Table 3. Symbol A0 Signal Descriptions (Sheet 1 of 2) Type Input Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. 32-Mbit: A[21:0] 64-Mbit: A[22:0] 128-Mbit: A[23:0] 256-Mbit: A[24:0] LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data is internally latched during write operations. HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 13 on page 33), power reduces to standby levels. All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of CE0, CE1, or CE2 that disables the device (see Table 13 on page 33). RESET/ POWER-DOWN: RP#-low resets internal automation and puts the device in powerdown mode. RP#-high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of WE#. STATUS: Indicates the status of the internal state machine. When configured in level mode (default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS signal, see the Configurations command. STS is to be tied to VCCQ with a pull-up resistor. BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#high places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order address bit. ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. With VPEN ≤ VPENLK, memory contents cannot be altered. CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited when VCC ≤ VLKO. Device operation at invalid Vcc voltages should not be attempted. I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to VCC. A[MAX:1] Input D[7:0] Input/Output D[15:8] Input/Output CE0, CE1, CE2 Input RP# Input OE# WE# Input Input STS Open Drain Output BYTE# Input VPEN Input VCC VCCQ Power Power 16 Datasheet 256-Mbit J3 (x8/x16) Table 3. Symbol GND NC RFU Signal Descriptions (Sheet 2 of 2) Type Supply — — Name and Function GROUND: Do not float any ground signals. NO CONNECT: Lead is not internally connected; it may be driven or floated. RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for future device functionality and enhancement. Datasheet 17 256-Mbit J3 (x8/x16) 5.0 5.1 Maximum Ratings and Operating Conditions Absolute Maximum Ratings This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Absolute maximum ratings are shown in Table 4. Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Absolute Maximum Ratings Parameter Temperature under Bias Extended Storage Temperature Voltage On Any signal Output Short Circuit Current Maximum Rating –40 °C to +85 °C –65 °C to +125 °C –2.0 V to +5.0 V(1) 100 mA(2) Table 4. NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on VCC and VPEN signals. During transitions, this level may undershoot to –2.0 V for periods