L7200

Intel® Core™2 Duo Mobile Processor for Intel® Centrino® Duo Mobile Processor Technology Datasheet September 2007 Document Number: 314078-004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines and Disclaimers UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Enhanced Intel SpeedStep® Technology for specified units of this processor available Q2/06. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. Intel, Centrino, Pentium, Intel Core 2, Intel SpeedStep, MMX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006 - 2007, Intel Corporation. All rights reserved. 2 Datasheet Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 9 1.2 References ....................................................................................................... 10 Low Power Features ................................................................................................ 11 2.1 Clock Control and Low Power States .................................................................... 11 2.1.1 Core Low Power State Descriptions ........................................................... 13 2.1.2 Package Low Power State Descriptions ...................................................... 15 2.2 Enhanced Intel SpeedStep® Technology .............................................................. 18 2.3 Extended Low Power States ................................................................................ 19 2.4 FSB Low Power Enhancements ............................................................................ 19 2.5 Processor Power Status Indicator (PSI#) Signal..................................................... 20 Electrical Specifications ........................................................................................... 21 3.1 Power and Ground Pins ...................................................................................... 21 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................... 21 3.3 Voltage Identification ......................................................................................... 21 3.4 Catastrophic Thermal Protection .......................................................................... 25 3.5 Reserved and Unused Pins.................................................................................. 25 3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 26 3.7 FSB Signal Groups............................................................................................. 26 3.8 CMOS Signals ................................................................................................... 28 3.9 Maximum Ratings.............................................................................................. 28 3.10 Processor DC Specifications ................................................................................ 29 Package Mechanical Specifications and Pin Information .......................................... 39 4.1 Package Mechanical Specifications ....................................................................... 39 4.2 Processor Pinout and Pin List .............................................................................. 49 4.3 Alphabetical Signals Reference ............................................................................ 73 Thermal Specifications and Design Considerations .................................................. 81 5.1 Thermal Specifications ....................................................................................... 85 5.1.1 Thermal Diode ....................................................................................... 85 5.1.2 Thermal Diode Offset .............................................................................. 85 5.1.3 Intel® Thermal Monitor........................................................................... 87 5.1.4 Digital Thermal Sensor............................................................................ 89 5.1.5 Out of Specification Detection .................................................................. 90 5.1.6 PROCHOT# Signal Pin ............................................................................. 90 2 3 4 5 Datasheet 3 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Core Low Power States..............................................................................................12 Package Low Power States.........................................................................................13 Deeper Sleep VCC and ICC Loadline for Dual-core Standard Voltage Processors..................34 Deeper Sleep VCC and ICC Loadline for Dual-core Low Voltage and Ultra Low Voltage Processor .......................................................................................35 Active VCC and ICC Loadline for Intel Core 2 Solo Processor, Ultra Low Voltage..................36 4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing .....................................40 4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing .....................................41 2-MB Micro-FCPGA Processor Package Drawing.............................................................42 2-MB Micro-FCPGA Processor Package Drawing.............................................................43 4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing .....................................44 4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing .....................................45 2-MB Micro-FCBGA Processor Package Drawing ............................................................46 1-MB Micro-FCBGA Processor Package Drawing (2 of 2) .................................................47 1-MB Micro-FCBGA Processor Package Drawing (2 of 2) .................................................48 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Coordination of Core Low Power States at the Package Level ..........................................13 Voltage Identification Definition ..................................................................................22 BSEL[2:0] Encoding for BCLK Frequency......................................................................26 FSB Pin Groups ........................................................................................................27 Processor Absolute Maximum Ratings..........................................................................28 Voltage and Current Specifications for Dual-core Standard Voltage Processors ..................29 Voltage and Current Specifications for Dual-core Low Voltage Processors .........................31 Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage Processors ..32 AGTL+ Signal Group DC Specifications ........................................................................37 CMOS Signal Group DC Specifications..........................................................................38 Open Drain Signal Group DC Specifications ..................................................................38 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 1 of 2) ..........................................................................................................50 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of 2) ..........................................................................................................51 Pin Listing by Pin Name .............................................................................................53 Pin Listing by Pin Number ..........................................................................................64 Signal Description.....................................................................................................73 Power Specifications for the Dual-core Standard Voltage Processor..................................82 Power Specifications for the Dual-core Low Voltage Processor.........................................83 Power Specifications for the Single and Dual-core Ultra Low Voltage Processor..................84 Thermal Diode ntrim and Diode Correction Toffset ........................................................86 Thermal Diode Interface ............................................................................................86 Thermal Diode Parameters using Diode Mode ...............................................................86 Thermal Diode Parameters Using Transistor Model ........................................................87 4 Datasheet Revision History Revision Number -001 -002 -003 Initial release • • • • • • • • Added Information for L7400 and L7200 Low-Voltage Processors Updated Table 08 in Chapter 3 Updated Table 17 in Chapter 5 Added L-2 die package information Added Information for U2200 and U2100 Ultra Low-Voltage Processors Updated Electrical Specifications in Chapter 3 for ULV Processors Updated Thermal Specifications in Chapter 5 for ULV Processors Added A-1 die package information Description Revision Date August 2006 December 2006 May 2007 -004 September 2007 §§ Datasheet 5 6 Datasheet Introduction 1 Introduction The Intel® Core™2 Duo mobile processor for Intel® Centrino® Duo mobile technology based on the Intel® 945 Express Chipset family is built on 65-nanometer process technology and is the next generation high-performance, low-power mobile processor based on the Intel® Core™ architecture. Note: All references to the word “processor” in this document are references to the Intel Core 2 Duo mobile processor with 533- and 667-MHz front side bus (FSB), unless specified otherwise. The following list provides some of the key features on this processor: • Dual-core processor for mobile with enhanced performance • Intel® 64 architecture • Supports Intel Architecture with Dynamic Execution • On-die, primary 32-kB instruction cache and 32-kB write-back data cache per core • On-die, up to 4-MB second level shared cache with Advanced Transfer Cache Architecture • Data Prefetch Logic • Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3) • 667-MHz, Source-Synchronous FSB for Standard Voltage processors • Advanced Power Management features including Enhanced Intel SpeedStep® Technology • Intel® Enhanced Deeper Sleep state and Dynamic Cache Sizing • Digital Thermal Sensor • Micro-FCPGA and Micro-FCBGA packaging technologies • Intel® Virtualization Technology • Execute Disable Bit support for enhanced security Note: 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64 architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. The Intel Core 2 Duo mobile processor will be manufactured on Intel’s 65-nanometer process technology. The processor maintains support for MMXTM technology, Streaming SIMD instructions, and full compatibility with IA-32 software. In addition, the Intel Core 2 Duo mobile processor supports Intel 64 architecture which is enabled by 64-bit operating systems and consists of 64-bit instructions and registers. Further details on Intel Extended Memory 64 Technology and its programming model can be found in the Intel Extended Memory 64 Technology Software Developer’s Guide. The Intel Core 2 Duo mobile processor features on-die, 32-kB level 1 instruction and data caches and features up to a 4-MB level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before the L1 cache requests occurs, resulting in reduced bus cycle penalties. The processor includes the Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, the Write Order Buffer depth is enhanced to help with the write-back latency performance. Datasheet 7 Introduction In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3), the processor supports Supplemental Streaming SIMD Extensions 3 (SSSE3) to speed up media algorithms like encoding and decoding. Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. Streaming SIMD3 (SSE3) instructions provide highly efficient double-precision floating point, SIMD integer, and memory management operations. Also, these instructions enhance the performance of optimized applications for the digital home such as video, image processing and media compression technology. The processor features Enhanced Intel SpeedStep Technology, which enables real-time dynamic switching between multiple voltage and frequency points. The processor features the Auto Halt, Stop Grant, Deep Sleep, and Intel Enhanced Deeper Sleep Cstates. Enhanced thermal management capabilities are implemented including Intel® Thermal Monitor 1 and Intel Thermal Monitor 2 to provide efficient and effective cooling in high temperatures. The Intel Core 2 Duo mobile processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket. Intel Core 2 Duo mobile processor supports the Execute Disable Bit capability. This feature combined with a supporting operating system allows memory to be marked as executable or non executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual for more detailed information. Intel Virtualization Technology is a set of hardware enhancements to Intel server and client systems that combined with the appropriate software, will enable enhanced virtualization robustness and performance for both enterprise and consumer uses. Intel Virtualization Technology forms the foundation of Intel technologies focused on improved virtualization, safer computing, and system stability. For client systems, Intel Virtualization Technology’s hardware-based isolation helps provide the foundation for highly available and more secure client virtualization partitions. 8 Datasheet Introduction 1.1 Terminology Term Definition A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and XXXX means that the specification or value is yet to be determined. Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors. Refers to the interface between the processor and system core logic (also known as the chipset components). Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core. Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. The processor core power supply The processor ground reference # AGTL+ Front Side Bus (FSB) Intel® Virtualization Technology Processor Core Storage Conditions VCC VSS Datasheet 9 Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Also note that with Intel Centrino Duo technology, the Intel Core 2 Duo mobile processor supports Mobile Intel® 945GM/GT/GMS/PM and 940GML Express Chipset family and Intel® 82801GBM (also known as ICH7M). Document Intel® Core™2 Duo Processor for Intel® Centrino® Duo Technology Specification Update Mobile Intel® 945 Express Chipset Family Chipset Datasheet Mobile Intel® 945 Express Chipset Family Chipset Specification Update Intel® I/O Controller Hub 7 (ICH7) Family Datasheet Intel® I/O Controller Hub 7 (ICH7) Family Specification Update Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes AP-485 Intel® Processor Identification and the CPUID Instruction 253665 253666 253667 253668 253669 252046 241618 Document Number 314079 309219 309220 307013 307014 §§ 10 Datasheet Low Power Features 2 2.1 Low Power Features Clock Control and Low Power States The Intel Core 2 Duo mobile processor supports low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states. Refer to Figure 1 for a visual representation of the core low power states for the processor. When both cores coincide in a common core low power state, the central power management logic ensures the entire Intel Core 2 Duo mobile processor enters the respective package low power state by initiating a P_LVLx (P_LVL2, P_LVL3, and P_LVL4) I/O read to the Intel 945GM/GT/GMS/PM and 940GML Express Chipset family. Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep, Deep Sleep, and Deeper Sleep. Refer to Figure 2 for a visual representation of the package low power states for the Intel Core 2 Duo mobile processor and to Table 1 for a mapping of core low power states to package low power states. The Intel Core 2 Duo mobile processor implements two software interfaces for requesting low power states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The monitor address does not need to be setup before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through a software programmable Model Specific Register (MSR). If a core encounters a chipset break event while STPCLK# is asserted, then it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the Intel Core 2 Duo mobile processor should return to the Normal state. Datasheet 11 Low Power Features Figure 1. Core Low Power States Stop Grant STPCLK# asserted STPCLK# de-asserted STPCLK# de-asserted STPCLK# asserted C1/ MWAIT STPCLK# de-asserted STPCLK# asserted Core state break MWAIT(C1) C1/Auto Halt HLT instruction Halt break C0 Core State break P_LVL4 or MWAIT(C4) P_LVL2 or MWAIT(C2) Core state break Core P_LVL3 or state MWAIT(C3) break C4 †‡ C2 † C3 † halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) † — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ — Core C4 state includes the Intel Enhanced Deeper Sleep state. 12 Datasheet Low Power Features Figure 2. Package Low Power States STPCLK# asserted SLP# asserted DPSLP# asserted DPRSTP# asserted Normal STPCLK# de-asserted Stop Grant SLP# de-asserted Sleep DPSLP# de-asserted Deep Sleep DPRSTP# de-asserted Deeper † Sleep Snoop serviced Snoop occurs Stop Grant Snoop † — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state. Table 1. Coordination of Core Low Power States at the Package Level Package State Core0 State C0 C1/AutoHALT/ MWAIT C2 C3 C0 Normal Normal Normal Normal C1/Auto HALT/ MWAIT Normal Normal Normal Normal Core1 State C2 Normal Normal Stop-Grant Stop-Grant C3 Normal Normal Stop-Grant Deep Sleep C4 Normal Normal Stop-Grant Deep Sleep Deeper Sleep/ C4 Normal Normal Stop-Grant Deep Sleep Intel® Enhanced Deeper Sleep 2.1.1 2.1.1.1 Core Low Power State Descriptions Core C0 State This is the normal operating state for cores in the processor. 2.1.1.2 Core C1/AutoHALT Powerdown State C1/AutoHALT is a low power state entered when a core executes the HALT instruction. The processor core will transition to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. Datasheet 13 Low Power Features While in AutoHALT Powerdown state, the Intel Core 2 Duo mobile processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT Powerdown state. 2.1.1.3 Core C1/MWAIT Powerdown State C1/MWAIT is a low power state entered when the processor core executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information. 2.1.1.4 Core C2 State Individual cores of the Intel Core 2 Duo mobile processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in the C2 state, the Intel Core 2 Duo mobile processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the C2 state. 2.1.1.5 Core C3 State Individual cores of the Intel Core 2 Duo mobile processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the Intel Core 2 Duo mobile processor accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself. 2.1.1.6 Core C4 State Individual cores of the Intel Core 2 Duo mobile processor can enter the C4 state by initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core behavior in the C4 state is nearly identical to the behavior in the C3 state. The only difference is that if both processor cores are in C4, then the central power management logic will request that the entire Intel Core 2 Duo mobile processor enter the Deeper Sleep package low power state (see Section 2.1.2.6). To enable the package level Intel® Enhanced Deeper Sleep state, Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software programmable MSR to enable the Intel Enhanced Deeper Sleep state. 14 Datasheet Low Power Features 2.1.2 2.1.2.1 Package Low Power State Descriptions Normal State This is the normal operating state for the processor. The Intel Core 2 Duo mobile processor remains in the Normal state when at least one of its cores is in the C0, C1/ AutoHALT, or C1/MWAIT state. 2.1.2.2 Stop-Grant State When the STPCLK# pin is asserted, each core of the Intel Core 2 Duo mobile processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low power state. When the STPCLK# pin is deasserted, each core returns to its previous core low power state. Note: Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to RESET# deassertion (AC Specification T45). When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP# (AC Specification T75). While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state. The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor should return to the Normal state. A transition to the Stop-Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) will occur with the assertion of the SLP# signal. 2.1.2.3 Stop-Grant Snoop State The processor will respond to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor will return to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched. 2.1.2.4 Sleep State The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Datasheet 15 Low Power Features Note: In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5.). While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur. 2.1.2.5 Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on Intel 945GM/GT/GMS/PM and 940GML Express Chipset family based platforms with the CK410M clock chip are as follows: • Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep. • Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding tosnoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. 2.1.2.6 Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but reduces core voltage to one of two lower levels. One lower core voltage level is achieved by entering the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper Sleep state of Deeper Sleep state. The Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.2 for further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state. In response to entering Deeper Sleep, the Intel Core 2 Duo mobile processor will drive the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins. 16 Datasheet Low Power Features Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point. 2.1.2.6.1 Intel Enhanced Deeper Sleep State Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power saving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters Intel Enhanced Deeper Sleep state: • The last core entering C4 issues a P_LVL4 I/O Read or an MWAIT(C4). • The processor triggers a special chipset sequence to notify the chipset to redirect all FSB traffic, except APIC messages, to memory. The snoops are replied as misses by the chipset and are directed to main memory instead of the L2 cache. • The processor will drive the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID[6:0] pins. 2.1.2.6.2 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions: • The second core is already in C4 and core sub-state Intel Enhanced Deeper Sleep state is enabled (as specified in Section 2.1.2.6.1). • The C0 timer, which tracks continuous residency in the Normal package state, has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed. • The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold. If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing decisions. Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways. If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not the one currently entering the interrupt routine) requests the C1, C2, or C3 states, then the whole L2 will be expanded when the next INTR event would occur. L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled, then the Intel Core 2 Duo mobile processor does not enter the Intel Enhanced Deeper Sleep state since the L2 cache remains valid and in full size. Datasheet 17 Low Power Features 2.2 Enhanced Intel SpeedStep® Technology The Intel Core 2 Duo mobile processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power. • Voltage and frequency selection is software controlled by writing to processor MSRs: — . If the target frequency is higher than the current frequency, Vcc is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency. — If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition completes. • The processor controls voltage ramp rates internally to ensure glitch free transitions. • Low transition latency and large number of transitions possible per second: — Processor core (including L2 cache) is unavailable for up to 10 μs during the frequency transition. — The bus protocol (BNR# mechanism) is used to block snooping. • Improved Intel Thermal Monitor mode: — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency and voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management. • Enhanced thermal management features. — Digital Thermal Sensor and Out of Specification detection. — Intel Thermal Monitor 1 in addition to Intel Thermal Monitor 2 in case of unsuccessful Intel Thermal Monitor 2 transition. — Dual-core thermal management synchronization. Each core in the processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage, then the processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests, then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage. 18 Datasheet Low Power Features 2.3 Extended Low Power States Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state. Instead of directly transitioning into the package low power state, the extended low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the package low power states. Note: Long-term reliability may not be assured if Extended Low Power States are not enabled. The processor implements two software interfaces for requesting extended package low power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring a software programmable MSR to automatically promote package low power states to extended package low power states. Note: Extended Stop-Grant and Extended Deeper Sleep must be enabled via the BIOS for the processor to remain within specification. Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E configuration is enabled through a software programmable MSR. This Extended Deeper Sleep state configuration will lower the core voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency. The transition to the lowest operating point or back to the original software requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases. 2.4 FSB Low Power Enhancements The processor incorporates FSB low power enhancements: • Dynamic FSB Power Down • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On-die Termination disabling • Low VCCP (I/O termination voltage) Datasheet 19 Low Power Features The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On-die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times. 2.5 Processor Power Status Indicator (PSI#) Signal The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous Intel® Pentium® M processors. For Intel Core 2 processor with Intel Centrino Duo mobile technology, PSI# signal functionality is supported only in idle state. §§ 20 Datasheet Electrical Specifications 3 3.1 Electrical Specifications Power and Ground Pins For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please contact your Intel representative for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the core frequency is a multiple of the BCLK[1:0] frequency. The processor uses a differential clocking implementation. 3.3 Voltage Identification The processor uses seven voltage identification pins, VID[6:0], to support automatic selection of power supply voltages. The VID pins for processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to lowvoltage level. Datasheet 21 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 1 of 4) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vcc (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 22 Datasheet Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 4) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vcc (V) 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 Datasheet 23 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 4) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vcc (V) 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 24 Datasheet Electrical Specifications Table 2. Voltage Identification Definition (Sheet 4 of 4) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vcc (V) 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 3.4 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. THERMTRIP# functionality is not guaranteed if the PWRGOOD signal is not asserted. 3.5 Reserved and Unused Pins All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Figure 12 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected. The TEST1 and TEST2 pin must have a stuffing option connection to VSS separately via 1-kΩ, pull-down resistors. Datasheet 25 Electrical Specifications For testing purposes it is recommended, but not required, to route the TEST3 and TEST4 pins through a ground referenced 55-Ω trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the Intel 945GM/ GT/GMS/PM and 940GML Express Chipset family on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3. Table 3. BSEL[2:0] Encoding for BCLK Frequency BSEL[2] L L L L BSEL[1] L L H H BSEL[0] L H L H BCLK Frequency RESERVED 133 MHz RESERVED 166 MHz 3.7 FSB Signal Groups In order to simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous. 26 Datasheet Electrical Specifications Table 4. FSB Pin Groups Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Synchronous to assoc. strobe Signals REQ[4:0]#, A[16:3]# A[35:17]#6 D[15:0]#, DINV0# D[31:16]#, DINV1# D[47:32]#, DINV2# D[63:48]#, DINV3# Associated Strobe ADSTB[0]# ADSTB[1]# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# Signals1 BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, DPWR#, TRDY# ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3 Signal Group AGTL+ Common Clock Input AGTL+ Common Clock I/O AGTL+ Source Synchronous I/O AGTL+ Strobes CMOS Input Open Drain Output Open Drain I/O CMOS Output CMOS Input Open Drain Output FSB Clock Power/Other Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK Clock ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, IERR#, THERMTRIP# PROCHOT#4 PSI#, VID[6:0], BSEL[2:0] TCK, TDI, TMS, TRST# TDO BCLK[1:0] COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, VCC, VCCA, VCCP, VCC_SENSE, VSS, VSS_SENSE NOTES: 1. Refer to Chapter 4, “Package Mechanical Specifications and Pin Information” for signal descriptions and termination requirements. 2. In processor systems without a debug port implemented on the board, these signals are used to support debug port interposers. In systems with the debug port implemented on the board, these signals are no connects. 3. BPM[2:1]# and PRDY# are AGTL+ output only signals. 4. PROCHOT# signal type is open drain output and CMOS input. 5. On-die termination differs from other AGTL+ signals, please contact your Intel representative for more details. 6. When paired with a chipset limited to 32-bit addressing, A[35:32] should remain unconnected. Datasheet 27 Electrical Specifications 3.8 CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs in order for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups. 3.9 Maximum Ratings Table 5 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. Table 5. Processor Absolute Maximum Ratings Symbol TSTORAGE VCC VinAGTL+ VinAsynch_CMOS Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS CMOS buffer DC input voltage with respect to VSS Min -40 -0.3 -0.1 -0.1 Max 85 1.55 1.55 1.55 Unit °C V V V Notes1 2,3,4 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. For functional operation, please refer to the processor case temperature specifications. 3. This rating applies to the processor and does not include any tray or packaging. 4. Failure to adhere to this specification can affect the long term reliability of the processor. 28 Datasheet Electrical Specifications 3.10 Note: Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 9. DC specifications for the CMOS group are listed in Table 10. Table 6 through Table 11 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on the processor. Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the processor are at Tjunction = 100°C. Care should be taken to read all notes associated with each parameter. Table 6. Symbol VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for Dual-core Standard Voltage Processors (Sheet 1 of 2) Parameter VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep Voltage VCC at Intel® Enhanced Deeper Sleep Voltage ICC for Processors Recommended Design Targets: ICC for Processors Processor Number T7600 Core Frequency/Voltage 2.33 GHz and HFM VCC 2.17 GHz and HFM VCC 2.00 GHz and HFM VCC 1.83 GHz and HFM VCC 1.67 GHz and HFM VCC 1.00 GHz and LFM VCC 41 41 41 41 41 27.3 18.0 26.7 17.8 26.1 A 3,4 A A 3, 8, 12 3, 8, 12 3, 8, 12 3, 8, 13 3, 8, 13 44 A 5 1.00 1.425 0.60 0.55 Min 1.0375 0.75 1.20 1.05 1.5 1.10 1.575 0.80 0.70 Typ Max 1.3000 0.95 Unit V V V V V V V 1, 2, 12 1,2 Notes 1, 2 1, 2 2, 8 ICC T7400 T7200 T5600 T5500 IAH, ISGNT ICC Auto-Halt and Stop-Grant LFM HFM ICC Sleep LFM HFM 3,4 ISLP Datasheet 29 Electrical Specifications Table 6. Symbol Voltage and Current Specifications for Dual-core Standard Voltage Processors (Sheet 2 of 2) Parameter ICC Deep Sleep LFM HFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable Min Typ Max 17.0 23.7 12.1 9.9 600 130 4.5 2.5 A/µs mA A A 9 10 A 3,4 4 6, 7 Unit A Notes 3,4 IDSLP IDPRSLP ICCDC4 dICC/DT ICCA ICCP NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the VID voltage. 5. The ICCDES(max) specification of 44 A comprehends processor ICC design target for Intel Core2 Duo mobile processor for Intel Centrino Duo mobile technology. 6. Base on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Measured at the bulk capacitors on the motherboard. 8. Specified at nominal VCC. 9. This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high. 10. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 11. If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the Intel Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID. 12. T7600, T7400, T7200 processors feature 4-MB cache. 13. T5600, T5500 processors feature 2-MB cache. 30 Datasheet Electrical Specifications Table 7. Symbol VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for Dual-core Low Voltage Processors Parameter VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep Voltage VCC at Intel® Enhanced Deeper Sleep Voltage ICC for Processors Recommended Design Targets: Processor Number Core Frequency/Voltage 23 A 5 1.00 1.425 0.6 0.55 Min 0.9 0.75 1.20 1.05 1.5 1.10 1.575 0.8 0.7 Typ Max 1.1 0.95 Unit V V V V V V V 1, 2, 12 1,2 Notes 1, 2 1, 2 2, 8 ICC L7400 L7200 1.50 GHz and HFM VCC 1.33 GHz and HFM VCC 1.00 GHz and LFM VCC 23 23 19.7 10.4 11.5 10.1 11.2 9.4 9.9 7.4 5.4 600 130 4.5 2.5 A 3,9,13 3,9,13 IAH, ISGNT ICC Auto-Halt & Stop-Grant LFM HFM ICC Sleep LFM HFM ICC Deep Sleep A 3,4 ISLP A 3,4 IDSLP IDPRSLP IDC4 dICC/DT ICCA ICCP LFM HFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep State VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable A A 3,4 3,4 3,4 A/µs mA A A 6, 7 10 11 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. Datasheet 31 Electrical Specifications 4. 5. 6. 7. 8. 9. 10. 11. 12. Specified at the VID voltage. The ICCDES(max) specification of 23 A comprehends only Intel Core 2 Duo mobile processor HFM frequencies with Intel Centrino Duo mobile technology. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. Measured at the bulk capacitors on the motherboard. VCC,BOOT tolerance shown in Figure 3. Specified at nominal VCC. This is a steady-state Icc current specification, which is applicable when both VCCP and VCC_CORE are high. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the Intel Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID Table 8. Symbol VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage Processors (Sheet 1 of 2) Parameter VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep Voltage VCC at Intel® Enhanced Deeper Sleep Voltage ICC for Processors Recommended Design Targets: Processor Number U7600 1.00 1.425 0.60 0.55 Min 0.8 0.75 1.20 1.05 1.5 1.10 1.575 0.80 0.70 17 (dual core) 8 (single core) Typ Max 0.975 0.95 Unit V V V V V V V 1, 2, 12 1, 2 Notes 1, 2 1, 2 2, 8 ICCDES A 5 Core Frequency/Voltage 1.20 GHz and HFM VCC 1.06 GHz and HFM VCC 1.20 GHz and HFM VCC 1.06 GHz and HFM VCC 0.80 GHz and LFM VCC 16 16 8 8 13.8-DC 6.9-SC 6.5 7.4 6.3 7.3 5.7 6.2 4.9 4.0 A A 3, 4 3, 4 A 3, 4 A 3, 4 A 3, 4 A 3, 9 ICC U7500 U2200 U2100 IAH, ISGNT ICC Auto-Halt & Stop-Grant LFM HFM ICC Sleep LFM HFM ICC Deep Sleep ISLP IDSLP IDPRSLP ICCDC4 LFM HFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep 32 Datasheet Electrical Specifications Table 8. Symbol dICC/DT ICCA ICCP Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage Processors (Sheet 2 of 2) Parameter VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCASupply ICC for VCCPSupply before VCC Stable ICC for VCCP Supply after VCC Stable Min Typ Max 600 130 4.5 2.5 Unit A/µs mA A A 10 11 Notes 6, 7 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the VID voltage. 5. The ICCDES(max) specification of 17 A comprehends only Intel Core 2 Duo mobile processor HFM frequencies on Intel Centrino Duo mobile technology. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Measured at the bulk capacitors on the motherboard. 8. VCC,BOOT tolerance shown in Figure 3. 9. Specified at nominal VCC. 10. This is a steady-state Icc current specification, which is applicable when both VCCP and VCC_CORE are high. 11. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 12. If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the Intel Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID 13. 2-M cache. Datasheet 33 Electrical Specifications Figure 3. Deeper Sleep VCC and ICC Loadline for Dual-core Standard Voltage Processors VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {Deeper Sleep} VCC-CORE, DC max {Deeper Sleep} VCC-CORE nom {Deeper Sleep} 13mV= RIPPLE for PSI# Asserted VCC-CORE, DC min {Deeper Sleep} VCC-CORE min {Deeper Sleep} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ 0 Tolerance - PSI# Ripple -----------------------------+/-[(VID*1.5%) - 3 mV] +/-(11.5 mV - 3 mV) +/- (25 mV - 3 mV) ICC-CORE max {Deeper Sleep} ICC-CORE [A] Note 1/ Deeper Sl eep V C C - C O R E S et Poi nt Error Tolerance is per below: V C C - C O R E V ID Voltage Range -------------------------------------------------------V C C - C O R E > 0 .7500V 0.7500V < V C C - C O R E < 0.5000V 0.5000V < V C C - C O R E < 0.4125V 34 Datasheet Electrical Specifications Figure 4. Deeper Sleep VCC and ICC Loadline for Dual-core Low Voltage and Ultra Low Voltage Processor VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {Deeper Sleep} VCC-CORE, DC max {Deeper Sleep} VCC-CORE nom {Deeper Sleep} 10 mV= RIPPLE VCC-CORE, DC min {Deeper Sleep} VCC-CORE min {Deeper Sleep} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ 0 Tolerance -----------------------------+/- (VID*1.5%) +/- 11.5 mV +/- 25 mV ICC-CORE max {Deeper Sleep} ICC-CORE [A] Note 1 / Deeper Sleep V CC- COR E S et Point Error Tolerance is per below: V CC-C ORE V ID Voltage Range -------------------------------------------------------V CC-C ORE > 0.7500V 0.7500V < V CC- CO RE < 0.5000V 0.5000V < V CC- CO RE < 0.4125V NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis. 4. For Vin (Input Voltage) between 0 V and VH. 5. Cpad includes die capacitance only. No package parasitics are included. 6. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2. Datasheet 35 Electrical Specifications Figure 5. Active VCC and ICC Loadline for Intel Core 2 Solo Processor, Ultra Low Voltage VCC-CORE [V] Slope = -5.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ 0 Note 1/ VCC-CORE Set Point Error Tolerance is per below: ICC-CORE max {HFM|LFM} Tolerance VCC-CORE VID Voltage Range --------------- -------------------------------------------------------+/-1.5% VCC-CORE > 0.7500V +/-11.5mV 0.75000V < VCC-CORE < 0.5000V 36 Datasheet Electrical Specifications Table 9. Symbol VCCP GTLREF RCOMP RODT VIH VIL VOH RTT RON ILI Cpad AGTL+ Signal Group DC Specifications Parameter I/O Voltage Reference Voltage Compensation Resistor Termination Resistor Input High Voltage Input Low Voltage Output High Voltage Termination Resistance Buffer On Resistance Input Leakage Current Pad Capacitance 1.6 2.1 GTLREF +0.10 -0.10 VCCP -0.10 50 22 27.23 Min 1.00 Typ 1.05 2/3 VCCP 27.5 55 VCCP 0 VCCP 55 25 VCCP +0.10 GTLREF-0.10 VCCP 61 28 ±100 2.55 27.78 Max 1.10 Unit V V 6 10 11 3,6 2,4 6 Notes1 Ω Ω V V Ω Ω µA pF 7 5 8 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull-down driver resistance. Measured at 0.31*VCCP. RON (min) = 0.38*RTT. RON (typ) = 0.45*RTT. RON (max) = 0.52*RTT. 6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VCCP. RTT is connected to VCCP on-die. 8. Specified with on-die RTT and RON are turned off. Vin (Input Voltage) between 0 and VCCP. 9. Cpad includes die capacitance only. No package parasitics are included. 10. This is the external resistor on the comp pins. 11. On-die termination resistance, measured at 0.33*VCCP. Datasheet 37 Electrical Specifications . Table 10. Symbol VCCP VIH VIL VOH VOL IOH IOL ILI Cpad1 Cpad2 CMOS Signal Group DC Specifications Parameter I/O Voltage Input High Voltage Input Low Voltage CMOS Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current Pad Capacitance Pad Capacitance for CMOS Input 1.6 0.95 2.1 1.2 Min 1.00 0.7*VCCP -0.10 0.9*VCCP -0.10 1.5 1.5 Typ 1.05 VCCP 0.00 VCCP 0 Max 1.10 VCCP+0.1 0.3*VCCP VCCP+0.1 0.1*VCCP 4.1 4.1 ± 100 2.55 1.45 Unit V V V V V mA mA µA pF 2 2 2 2 4 3 5 6 7 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VCCP referred to in these specifications refers to instantaneous VCCP. 3. Measured at 0.1*VCCP. 4. Measured at 0.9*VCCP. 5. For Vin (Input Voltage) between 0 V and VCCP. Measured when the driver is tristated. 6. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are included. 7. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included. Table 11. Symbol VOH VOL IOL ILO Cpad Open Drain Signal Group DC Specifications Parameter Output High Voltage Output Low Voltage Output Low Current Output Leakage Current Pad Capacitance 1.9 2.2 Min VCCP-5% 0 16 Typ VCCP Max VCCP+5% 0.20 50 ± 200 2.45 Unit V V mA µA pF 2 4 5 Notes1 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2 V. 3. VOH is determined by value of the external pull-up resistor to VCCP. 4. For Vin (Input Voltage) between 0 V and VOH. 5. Cpad includes die capacitance only. No package parasitics are included. §§ 38 Datasheet Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information Package Mechanical Specifications The processor will be available in 4-MB and 2-MB L2 cache versions for 478-pin microFCPGA and 4-MB, 2-MB and 1-MB L2 Cache 479-ball micro-FCBGA packages. The package mechanical dimensions are shown in Figure 6 through Figure 14. Table 12 shows a top-view of package pinout. The micro-FCBGA package incorporates land-side capacitors. The land-side capacitors are electrically conductive so care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors and possibly damage the device or render it inactive. 4.1 Datasheet 39 Package Mechanical Specifications and Pin Information Figure 6. 4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION B B1 H1 G2 C2 G2 B2 H2 C1 Top View A J2 J1 478 Pins Bottom View A Front View Side View Underfill Package Substrate Ø0.37 MAX Die SYMBOL 2.03±0.08 F2 0.65 MAX F3 C Ø0.65 MAX Detail A Scale 20 ØP MILLIMETERS MIN MAX 34.95 35.05 B1 34.95 35.05 B2 C1 10.5 C2 13.8 0.89 F1 1.903 2.163 F2 31.75 BASIC G1 31.75 BASIC G2 15.875 BASIC H1 15.875 BASIC H2 1.27 BASIC J1 1.27 BASIC J2 0.255 0.355 P P Die 689kPa 6g W Keying Pins COMMENTS Ø0.356 M C A B Ø0.254 M C A1, B2 B6595-01 40 Datasheet Datasheet Figure 7. THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. 4x 700 4X 700 Package Mechanical Specifications and Pin Information Ø0.305±0.25 Ø0.406 M C A B Ø0.254 M C 13.97 6.985 1.625 1.625 13.97 6.985 EDGE KEEP OUT ZONE 4X Top View 4X 500 CORNER KEEP OUT ZONE 4X Side View 1.5 MAX ALLOWABLE COMPONENT HEIGHT Bottom View B6596-01 4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing 41 Package Mechanical Specifications and Pin Information Figure 8. 2-MB Micro-FCPGA Processor Package Drawing G1 B B1 H1 G2 C2 B2 H2 C1 J2 A J1 Top View Bottom View 478 Pins A Front View Side View SYMBOL B1 B2 MILLIMETERS MIN MAX COMMENTS 34.95 34.95 10 35.05 35.05 Die Underfill Package Substrate C1 C2 F2 F3 F2 0.65 MAX G1 F3 G2 H1 H2 2.03±0.08 C J1 J2 P P DIE W 10.3 0.89 1.823 2.063 0.37 MAX 31.75 BASIC 31.75 BASIC 15.875 BASIC 15.875 BASIC 1.27 BASIC 1.27 BASIC 0.255 0.355 ø0.356 ø0.254 MCAB MC 0.65 MAX oP Detail A Scale 20 689 kPa 6g Keying Pins A1, B1 B6152-02 42 Datasheet Package Mechanical Specifications and Pin Information Figure 9. 2-MB Micro-FCPGA Processor Package Drawing 4X 7.00 4X 7.00 Edge Keep Out Zone 4X 4X 5.00 Top View Corner Keep Out Zone 4X Side View ø0.305±0.25 ø0.406 M C A B ø0.254 M C 13.97 6.985 1.625 1.625 13.97 6.985 1.5 Max Allowable Component Height Bottom View B6153-01 Datasheet 43 Package Mechanical Specifications and Pin Information Figure 10. 4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing B B1 B H1 G1 C2 B2 H2 J2 C1 J1 G2 A Top View Bottom View 479 Balls M A Front View Detail B Scale 50 SYMBOL B1 B2 C1 C2 F2 F3 G1 G2 H1 H2 J1 J2 M N P DIE W MILLIMETERS 34.95 35.05 34.95 35.05 10.5 13.8 0.89 1.903 2.163 31.75 BASIC 31.75 BASIC 15.875 BASIC 15.875 BASIC 1.27 BASIC 1.27 BASIC 0.61 0.69 0.6 0.8 689 kPa 6g MIN MAX COMMENTS Side View Die Package Substrate Underfill F2 N F3 C ø0.203 L C A B ø0.071 L 0.203 Detail A Scale 20 B6597-01 44 Datasheet Package Mechanical Specifications and Pin Information Figure 11. 4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. 4X 7.00 4X 7.00 Edge Keep Out Zone 4X 4X 5.00 Top View 13.97 6.985 Corner Keep Out Zone 4X Side View 1.625 1.625 13.97 6.985 0.55 Max Allowable Component Height Bottom View B6598-01 Datasheet 45 Package Mechanical Specifications and Pin Information Figure 12. 2-MB Micro-FCBGA Processor Package Drawing B B1 B H1 G1 C2 B2 H2 J2 C1 J1 G2 A Top View Bottom View 479 Balls M A Front View Detail B Scale 50 SYMBOL B1 B2 C1 C2 F2 F3 G1 G2 H1 H2 J1 J2 M N P DIE W MILLIMETERS 34.95 34.95 MIN Side View Die 35.05 35.05 MAX COMMENTS Package Substrate Underfill F2 N F3 C 0.203 Detail A Scale 20 10 10.3 0.89 1.903 2.163 31.75 BASIC 31.75 BASIC 15.875 BASIC 15.875 BASIC 1.27 BASIC 1.27 BASIC 0.61 0.69 0.6 0.8 689 kPa 6g ø0.203 L C A B ø0.071 L B6154-02 46 Datasheet Datasheet B1 H1 Figure 13. B B 479 Balls G1 C2 B2 G2 H2 J2 Package Mechanical Specifications and Pin Information C1 A SYMBOL MIN MAX Side View MILLIMETERS COMMENTS J1 Top View Bottom View A OM H1 H2 J1 J2 M N P DIE W Front View B1 B2 C1 C2 F2 F3 34.95 35.05 34.95 35.05 7.4 10.9 0.89 G1 G2 1.903 2.163 31.75 BASIC 31.75 BASIC Package Substrate Underfill Die F2 F3 N 1-MB Micro-FCBGA Processor Package Drawing (2 of 2) C ø0.203 L ø0.071 L CAB Detail A Scale 20 0.203 Detail B Scale 50 15.875 BASIC 15.875 BASIC 1.27 BASIC 1.27 BASIC 0.61 0.69 0.6 0.8 689 kPa 6g 47 48 Figure 14. , , 4X 7.00 6.985 13.97 1.625 4X 7.00 1.625 13.97 6.985 1-MB Micro-FCBGA Processor Package Drawing (2 of 2) EDGE KEEP OUT ZONE 4X 4X 5.00 CORNER KEEP OUT ZONE 4X Side View 0.55 MAX ALLOWABLE COMPONENT HEIGHT Package Mechanical Specifications and Pin Information Top View Bottom View Datasheet Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Table 12 shows the top view pinout of the processor. The pin list, arranged in two different formats, is shown in the following pages. Datasheet 49 Package Mechanical Specifications and Pin Information Table 12. The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 1 of 2) 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF RESET# RSVD] VSS DBSY# BR0# VSS ADS# A[9]# VSS A[13]# A[7]# VSS A[15]# A[16]# VSS COMP[2] COMP[3] VSS A[31]# A[32]# VSS PREQ# BPM[2]# VSS TEST3 1 RSVD VSS RSVD BNR# VSS TRDY# REQ[1] # VSS REQ[2] # ADSTB[ 0]# VSS A[8]# A[12]# VSS RSVD A[23]# VSS A[30]# A[17]# VSS A[34]# PRDY# VSS VID[6] VID[5] 2 2 3 SMI# INIT# RSVD RSVD VSS RS[0]# RS[2]# VSS REQ[3] # REQ[0] # VSS A[5]# A[10]# VSS A[19]# A[26]# VSS RSVD A[27]# VSS A[35]# TDO VSS BPM[1] # VID[4] VSS 3 4 VSS LINT1 IGNNE # VSS HITM# RS[1]# VSS LOCK# A[3]# VSS A[4]# RSVD VSS A[14]# A[24]# VSS A[21]# ADSTB[ 1]# VSS A[29]# A[33]# VSS BPM[3] # BPM[0] # VSS VID[3] 4 5 FERR# DPSLP# VSS STPCLK # DPRSTP # VSS BPRI# DEFER# VSS A[6]# REQ[4] # VSS RSVD A[11]# VSS A[25]# A[18]# VSS A[28]# A[22]# VSS TMS TCK VSS VID[2] VID[1] 5 6 A20M# VSS LINT0 PWRGO OD VSS RSVD HIT# VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP A[20]# VSS TDI TRST# VSS VID[0] PSI# VSS 6 VCC VCC VCC VCC VSS SENSE VCC SENSE 7 VSS VSS VSS VSS VSS VSS 8 VCC VCC VCC VCC VCC VCC 9 VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS 11 VCC VCC VCC VCC VCC VCC 12 VCC VSS VCC VSS VCC VSS 13 7 VCC VCC THERM TRIP# SLP# VCC VCC 8 VSS VSS VSS VSS VSS VSS 9 VCC VCC VCC VCC VCC VCC 10 VCC VCC VCC VCC VCC VCC 11 VSS VSS VSS VSS VSS VSS 12 VCC VCC VCC VCC VCC VCC 13 VCC VSS VCC VSS VCC VSS A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 50 Datasheet Package Mechanical Specifications and Pin Information Table 13. 14 A B C D E F G H J K L M N P R T U V W Y AA AB AC A D AE AF VSS VCC VSS VCC VSS VCC 14 VCC VCC VCC VCC VCC VCC 15 VSS VCC VSS VCC VSS VCC 15 VCC VCC VCC VCC VCC VCC The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of 2) 16 VSS VSS VSS VSS VSS VSS 17 VCC VCC VCC VCC VCC VCC 18 VCC VCC VCC VCC VCC VCC 19 VSS VSS VSS VSS VSS VSS 20 VCC VCC DBR# IERR# VCC VCC 21 BCLK[1] VSS BSEL[2] PROCHO T# VSS DRDY# VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VSS VSS VSS VSS VSS VSS 16 VCC VCC VCC VCC VCC VCC 17 VCC VCC VCC VCC VCC VCC 18 VSS VSS VSS VSS VSS VSS 19 VCC VCC DINV[3 ]# D[54]# VCC VCC 20 D[51]# D[52]# VSS D[59]# D[58]# VSS 21 22 BCLK[0] BSEL[0] VSS RSVD D[0]# VSS DSTBP[0] # D[3]# VSS D[14]# D[21]# VSS D[16]# D[25]# VSS RSVD D[39]# VSS D[41]# D[45]# VSS D[50]# D[48]# VSS D[55]# D[62]# 22 23 VSS BSEL[1] RSVD VSS D[7]# D[4]# VSS DSTBN[0] # D[11]# VSS D[22]# D[23]# VSS D[26]# D[19]# VSS D[37]# DINV[2]# VSS D[42]# D[32]# VSS D[49]# DSTBN[3] # VSS D[56]# 23 24 THRMDA VSS RSVD DPWR# VSS D[1]# D[9]# VSS D[10]# D[8]# VSS DSTBN[1] # D[31]# VSS D[28]# D[27]# VSS D[34]# DSTBN[2] # VSS D[47]# D[33]# VSS D[57]# DSTBP[3] # VSS 24 25 THRMDC TEST4 VSS TEST2 D[6]# VSS D[5]# D[15]# VSS D[17]# D[20]# VSS DSTBP[1] # D[24]# VSS D[30]# D[38]# VSS D[36]# DSTBP[2] # VSS D[40]# D[53]# VSS D[60]# D[61]# 25 26 VSS VCCA TEST1 VSS D[2]# D[13]# VSS D[12]# DINV[0 ]# VSS D[29]# DINV[1 ]# VSS D[18]# COMP [0] VSS COMP[1 ] D[35]# VSS D[44]# D[43]# VSS D[46]# GTLREF VSS D[63]# 26 A B C D E F G H J K L M N P R T U V W Y A A A B AC A D AE AF Datasheet 51 Package Mechanical Specifications and Pin Information This page is intentionally left blank. 52 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 1 of 22) Pin Number J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Table 14. Pin Listing by Pin Name (Sheet 2 of 22) Pin Number R4 T5 T3 W3 W5 Y4 W2 Y1 AA1 AA4 AB2 AA3 A6 H1 L2 V4 A22 A21 E2 AD4 AD3 AD1 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Source Synch Source Synch Bus Clock Bus Clock Common Clock Common Clock Common Clock Common Clock Direction Pin Name Pin Name A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# A20M# ADS# ADSTB[0]# ADSTB[1]# BCLK[0] BCLK[1] BNR# BPM[0]# Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Output Output Input/Output BPM[1]# Input/Output BPM[2]# Input/Output Datasheet 53 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 3 of 22) Pin Number AC4 G5 F1 B22 B23 C21 R26 U26 U1 V1 E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 Signal Buffer Type Common Clock Common Clock Common Clock CMOS CMOS CMOS Power/ Other Power/ Other Power/ Other Power/ Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Table 14. Pin Listing by Pin Name (Sheet 4 of 22) Pin Number H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Pin Name Pin Name BPM[3]# BPRI# BR0# BSEL[0] BSEL[1] BSEL[2] COMP[0] COMP[1] COMP[2] COMP[3] D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# Input/Output Input Input/Output Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output D[12]# D[13]# D[14]# D[15]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# D[32]# Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 54 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 5 of 22) Pin Number AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Table 14. Pin Listing by Pin Name (Sheet 6 of 22) Pin Number AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 C20 E1 H5 J26 M26 V23 AC20 E5 B5 D24 F21 H23 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch CMOS CMOS Common Clock Common Clock Source Synch Direction Pin Name Pin Name D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DBR# DBSY# DEFER# Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output DINV[0]# Input/Output DINV[1]# Input/Output DINV[2]# Input/Output DINV[3]# Input/Output DPRSTP# Input/Output Input/Output Input/Output Input/Output DPSLP# DPWR# DRDY# DSTBN[0]# Datasheet 55 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 7 of 22) Pin Number M24 W24 AD23 G22 N25 Y25 AE24 A5 AD26 G6 E4 D20 C4 B3 C6 B4 H4 AC2 AC1 D21 AE6 D6 K3 H2 K2 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Open Drain Power/ Other Common Clock Common Clock Open Drain CMOS CMOS CMOS CMOS Common Clock Common Clock Common Clock Open Drain CMOS CMOS Source Synch Source Synch Source Synch Direction Table 14. Pin Listing by Pin Name (Sheet 8 of 22) Pin Number J3 L5 B1 F3 F4 G3 D2 F6 D3 C1 D22 C23 C24 M4 N5 T2 V3 B2 C3 T22 D7 A3 D5 AC5 AA6 AB3 C26 D25 AF1 B25 A24 Signal Buffer Type Source Synch Source Synch Common Clock Common Clock Common Clock Common Clock Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CMOS CMOS CMOS CMOS CMOS Open Drain Test Test Test Test Power/ Other Input Input Input Input Input Output Direction Pin Name Pin Name DSTBN[1]# DSTBN[2]# DSTBN[3]# DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR# GTLREF HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# PRDY# PREQ# PROCHOT# PSI# PWRGOOD REQ[0]# REQ[1]# REQ[2]# Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input/Output Input/Output Output Input Input Input Input Input/Output Output Input Input/Output Output Input Input/Output Input/Output Input/Output REQ[3]# REQ[4]# RESET# RS[0]# RS[1]# RS[2]# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SLP# SMI# STPCLK# TCK TDI TDO TEST1 TEST2 TEST3 TEST4 THERMDA Input/Output Input/Output Input Input Input Input 56 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 9 of 22) Pin Number A25 C7 AB5 G2 AB6 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17 AE18 AE17 AB15 Signal Buffer Type Power/ Other Open Drain CMOS Common Clock CMOS Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Output Input Input Input Direction Table 14. Pin Listing by Pin Name (Sheet 10 of 22) Pin Number AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Pin Name Pin Name THERMDC THERMTRIP# TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Datasheet 57 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 11 of 22) Pin Number AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Table 14. Pin Listing by Pin Name (Sheet 12 of 22) Pin Number D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Pin Name Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 58 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 13 of 22) Pin Number D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7 E7 B26 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Table 14. Pin Listing by Pin Name (Sheet 14 of 22) Pin Number K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21 AF7 AD6 AF5 AE5 AF4 AE3 AF2 AE2 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other CMOS CMOS CMOS CMOS CMOS CMOS CMOS Output Output Output Output Output Output Output Direction Pin Name Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCSENSE VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] Datasheet 59 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 15 of 22) Pin Number AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Table 14. Pin Listing by Pin Name (Sheet 16 of 22) Pin Number AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Pin Name Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 60 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 17 of 22) Pin Number AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Table 14. Pin Listing by Pin Name (Sheet 18 of 22) Pin Number R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Pin Name Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Datasheet 61 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 19 of 22) Pin Number K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Table 14. Pin Listing by Pin Name (Sheet 20 of 22) Pin Number A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Pin Name Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 62 Datasheet Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Name (Sheet 21 of 22) Pin Number F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Direction Table 14. Pin Listing by Pin Name (Sheet 22 of 22) Pin Number P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21 AE7 Signal Buffer Type Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Power/ Other Output Direction Pin Name Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE Datasheet 63 Package Mechanical Specifications and Pin Information Table 15. Table 15. Pin Listing by Pin Number (Sheet 1 of 17) Pin Name SMI# VSS FERR# A20M# VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THERMDA THERMDC VSS A[32]# VSS A[35]# A[33]# VSS TDI VCC VSS Signal Buffer Type CMOS Power/Other Open Drain CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Bus Clock Bus Clock Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other CMOS Power/Other Power/other Input Input/ Output Input/ Output Input/ Output Input Input Output Input Direction Input Pin Listing by Pin Number (Sheet 2 of 17) Pin Name VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC D[51]# VSS D[32]# D[47]# VSS D[43]# VSS A[34]# TDO VSS TMS TRST# VCC VSS VCC VCC VSS VCC VSS VCC Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Open Drain Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input/ Output Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Number AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 Pin Number A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 64 Datasheet Package Mechanical Specifications and Pin Information Table 15. Pin Listing by Pin Number (Sheet 3 of 17) Pin Name VCC VSS VCC VCC VSS VCC D[52]# D[50]# VSS D[33]# D[40]# VSS PREQ# PRDY# VSS BPM[3]# TCK VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/ Output Input Input Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 15. Pin Listing by Pin Number (Sheet 4 of 17) Pin Name Signal Buffer Type Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Output Output Input/ Output Input/ Output Input/ Output Output Input/ Output Input/ Output Direction Input/ Output Pin Number AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 Pin Number AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 DINV[3]# VSS D[48]# D[49]# VSS D[53]# D[46]# BPM[2]# VSS BPM[1]# BPM[0]# VSS VID[0] VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS D[54]# D[59]# VSS Datasheet 65 Package Mechanical Specifications and Pin Information Table 15. Pin Listing by Pin Number (Sheet 5 of 17) Pin Name Signal Buffer Type Source Synch Source Synch Power/Other Power/Other Power/Other CMOS CMOS Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Test CMOS Output Input/ Output Input/ Output Input/ Output Input/ Output Output Output Output Output Output Input Direction Input/ Output Input/ Output Table 15. Pin Listing by Pin Number (Sheet 6 of 17) Pin Name VSS VID[3] VID[1] VSS VCCSENSE VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS D[62]# D[56]# VSS D[61]# D[63]# RESET# RSVD INIT# LINT1 DPSLP# VSS VCC VSS Signal Buffer Type Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Common Clock Reserved CMOS CMOS CMOS Power/Other Power/Other Power/Other Input Input Input Input/ Output Input/ Output Input Input/ Output Input/ Output Output Output Direction Pin Number AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 Pin Number AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 DSTBN[3]# D[57]# VSS GTLREF VSS VID[6] VID[4] VSS VID[2] PSI# VSSSENSE VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC D[58]# D[55]# VSS DSTBP[3]# D[60]# VSS TEST3 VID[5] 66 Datasheet Package Mechanical Specifications and Pin Information Table 15. Pin Listing by Pin Number (Sheet 7 of 17) Pin Name VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS BSEL[0] BSEL[1] VSS TEST4 VCCA RSVD VSS RSVD IGNNE# VSS LINT0 THERMTRIP# VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Power/Other Test Power/Other Reserved Power/Other Reserved CMOS Power/Other CMOS Open Drain Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Input Output Output Direction Table 15. Pin Listing by Pin Number (Sheet 8 of 17) Pin Name VSS DBR# BSEL[2] VSS RSVD RSVD VSS TEST1 VSS RSVD RSVD VSS STPCLK# PWRGOOD SLP# VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS IERR# PROCHOT# RSVD VSS DPWR# TEST2 VSS Signal Buffer Type Power/Other CMOS CMOS Power/Other Reserved Reserved Power/Other Test Power/Other Reserved Reserved Power/Other CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain Open Drain Reserved Power/Other Common Clock Test Power/Other Input Output Input/ Output Input Input Input Output Output Direction Pin Number B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 Pin Number C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Datasheet 67 Package Mechanical Specifications and Pin Information Table 15. Pin Listing by Pin Number (Sheet 9 of 17) Pin Name Signal Buffer Type Common Clock Common Clock Power/Other Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Common Clock Power/Other Common Clock Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Direction Input/ Output Input/ Output Table 15. Pin Listing by Pin Number (Sheet 10 of 17) Pin Name Signal Buffer Type Common Clock Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Common Clock Common Clock Power/Other Common Clock Common Clock Power/Other Input Input/ Output Input Input Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Number E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 Pin Number F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G21 DBSY# BNR# VSS HITM# DPRSTP# VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS D[0]# D[7]# VSS D[6]# D[2]# BR0# VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC DRDY# VSS D[4]# D[1]# VSS D[13]# VSS TRDY# RS[2]# VSS BPRI# HIT# VCCP Input 68 Datasheet Package Mechanical Specifications and Pin Information Table 15. Pin Listing by Pin Number (Sheet 11 of 17) Pin Name Signal Buffer Type Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Common Clock Common Clock Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Table 15. Pin Listing by Pin Number (Sheet 12 of 17) Pin Name Signal Buffer Type Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Pin Number G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 Pin Number J24 J25 J26 K1 K2 K3 K4 K5 K6 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L21 L22 L23 L24 L25 DSTBP[0]# VSS D[9]# D[5]# VSS ADS# REQ[1]# VSS LOCK# DEFER# VSS VSS D[3]# DSTBN[0]# VSS D[15]# D[12]# A[9]# VSS REQ[3]# A[3]# VSS VCCP VCCP VSS D[11]# D[10]# VSS DINV[0]# VSS REQ[2]# REQ[0]# VSS A[6]# VCCP VCCP D[14]# VSS D[8]# D[17]# VSS A[13]# ADSTB[0]# VSS A[4]# REQ[4]# VSS VSS D[21]# D[22]# VSS D[20]# Datasheet 69 Package Mechanical Specifications and Pin Information Table 15. Pin Listing by Pin Number (Sheet 13 of 17) Pin Name Signal Buffer Type Source Synch Source Synch Power/Other Source Synch Reserved Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Reserved Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output Table 15. Pin Listing by Pin Number (Sheet 14 of 17) Pin Name VSS A[14]# A[11]# VSS VSS D[25]# D[26]# VSS D[24]# D[18]# A[16]# VSS A[19]# A[24]# VSS VCCP VCCP VSS D[19]# D[28]# VSS COMP[0] VSS RSVD A[26]# VSS Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Reserved Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Number L26 M1 M2 M3 M4 M5 M6 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N21 N22 N23 N24 N25 N26 P1 P2 Pin Number P3 P4 P5 P6 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 D[29]# A[7]# VSS A[5]# RSVD VSS VCCP VCCP VSS D[23]# DSTBN[1]# VSS DINV[1]# VSS A[8]# A[10]# VSS RSVD VCCP VCCP D[16]# VSS D[31]# DSTBP[1]# VSS A[15]# A[12]# 70 Datasheet Package Mechanical Specifications and Pin Information Table 15. Pin Listing by Pin Number (Sheet 15 of 17) Pin Name Signal Buffer Type Source Synch Power/Other Power/Other Reserved Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Reserved Source Synch Power/Other Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Table 15. Pin Listing by Pin Number (Sheet 16 of 17) Pin Name VSS DINV[2]# D[34]# VSS D[35]# VSS A[30]# A[27]# VSS A[28]# A[20]# VCCP D[41]# VSS DSTBN[2]# D[36]# VSS A[31]# A[17]# VSS A[29]# A[22]# VSS VSS D[45]# Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Number T5 T6 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V21 Pin Number V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 A[25]# VCCP VCCP RSVD VSS D[27]# D[30]# VSS COMP[2] A[23]# VSS A[21]# A[18]# VSS VSS D[39]# D[37]# VSS D[38]# COMP[1] COMP[3] VSS RSVD ADSTB[1]# VSS VCCP VCCP Datasheet 71 Package Mechanical Specifications and Pin Information Table 15. Pin Listing by Pin Number (Sheet 17 of 17) Pin Name Signal Buffer Type Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Direction Input/ Output Pin Number Y23 Y24 Y25 Y26 D[42]# VSS DSTBP[2]# D[44]# § 72 Datasheet Package Mechanical Specifications and Pin Information 4.3 Table 16. Alphabetical Signals Reference Signal Description (Sheet 1 of 8) Name Type Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. NOTE: When paired with a chipset limited to 32-bit addressing, A[35:32] should remain unconnected. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. ADSTB[1:0]# Input/ Output A[35:3]# Input/ Output A20M# Input ADS# Input/ Output Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB[0]# ADSTB[1]# BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BNR# Input/ Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. Datasheet 73 Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 2 of 8) Name Type Output Input/ Output Description BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all processor FSB agents.This includes debug or performance monitoring tools. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. The arbitration is done between processor (Symmetric Agent) and GMCH-M (High Priority Agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The processor operates at 667-MHz system bus frequency (166-MHz BCLK[1:0] frequency). COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DINV# 0 1 2 3 BPM[2:1]# BPM[3,0]# BPRI# Input BR0# Input/ Output BSEL[2:0] Output COMP[3:0] Analog Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. 74 Datasheet Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 3 of 8) Name Type Description DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/ Output agent. This signal must connect the appropriate pins of both FSB agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment To Data Bus DINV[3:0]# Input/ Output Bus Signal DINV[3]# DINV[2]# DINV[1]# DINV[0]# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]# DBR# Output DBSY# Input/ Output DEFER# Input DPRSTP# Input DPRSTP# when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state. In order to return to the Deep Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the ICH7M chipset. DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the ICH7M chipset. DPWR# is a control signal from the Intel® 945GM/GT/GMS/PM and 940GML Express Chipset family used to reduce power on the processor data bus input buffers. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. DPSLP# Input DPWR# Input DRDY# Input/ Output Datasheet 75 Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 4 of 8) Name Type Description Data strobe used to latch in D[63:0]#. Signals DSTBN[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR#/PBE# Output FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volumes 3A/3B of the Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual and AP-485 Intel® Processor Identification and the CPUID Instruction application note. GTLREF Input Input/ Output Input/ Output GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. HIT# HITM# 76 Datasheet Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 5 of 8) Name Type Description IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST) LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. IERR# Output IGNNE# Input INIT# Input LINT[1:0] Input LOCK# Input/ Output PRDY# Output Datasheet 77 Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 6 of 8) Name PREQ# Type Input Description Probe Request signal used by debug tools to request debug operation of the processor. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system deasserts PROCHOT#. This signal may require voltage translation on the motherboard. PSI# Output Processor Power Status Indicator signal. This signal is asserted when the processor is in a lower state (Deep Sleep and Deeper Sleep). PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. Input/ Output REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. PROCHOT# Input/ Output PWRGOOD Input REQ[4:0]# RESET# Input RS[2:0]# Input Reserved /No Connect RSVD 78 Datasheet Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 7 of 8) Name Type Description SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to StopGrant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TEST1 and TEST2 must have a stuffing option of separate pull down resistors to VSS. Input For testing purposes it is recommended, but not required, to route the TEST3 and TEST4 pins through a ground referenced 55-Ω trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. Thermal Diode Anode. Thermal Diode Cathode. The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. SLP# Input SMI# Input STPCLK# Input TCK TDI Input Input TDO Output TEST1, TEST2, TEST3, TEST4 THERMDA THERMDC Other Other THERMTRIP# Output Datasheet 79 Package Mechanical Specifications and Pin Information Table 16. Signal Description (Sheet 8 of 8) Name Type Description TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Please contact your Intel representative for termination requirements TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Processor core power supply. VCCA provides isolated power for the internal processor core PLL’s. Processor I/O Power Supply. VCC_SENSE together with VSS_SENSE are voltage feedback signals to Intel® MVP 6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense or measure power near the silicon with little noise. VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike some previous generations of processors, these are CMOS signals that are driven by the processor. The voltage supply for these pins must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSS_SENSE together with VCC_SENSE are voltage feedback signals to Intel MVP 6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense or measure ground near the silicon with little noise. TMS Input TRDY# Input TRST# VCC VCCA VCCP VCC_SENSE Input Input Input Input Output VID[6:0] Output VSS_SENSE Output §§ 80 Datasheet Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the exposed processor die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally-coupled to the processor via a heat pipe or direct die attachment. A secondary fan or air from the processor fan may also be used to cool other platform components or to lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 17. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. The maximum junction temperature is defined by an activation of the processor Intel Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 17. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification. Datasheet 81 Thermal Specifications and Design Considerations Table 17. Power Specifications for the Dual-core Standard Voltage Processor Symbol Processor Number T7600 T7400 TDP T7200 T5600 T5500 Symbol PAH, PSGNT at HFM VCC at LFM VCC Sleep Power PSLP at HFM VCC at LFM VCC Deep Sleep Power PDSLP PDPRSLP PDC4 TJ at HFM VCC at LFM VCC Deeper Sleep Power Intel® Enhanced Deeper Sleep Power Junction Temperature 0 7.6 4.5 2.0 1.2 100 W W °C 2, 9 2, 9 3, 4 W 2, 9 12.4 7.0 W 2, 8 Core Frequency & Voltage 2.33 GHz & HFM VCC 2.17 GHz & HFM VCC 2.00 GHz & HFM VCC 1.83 GHz & HFM VCC 1.67 GHz & HFM VCC 1.00 GHz & LFM VCC Parameter Auto Halt, Stop Grant Power 13.0 7.3 W 2, 8 Min Thermal Design Power 34 34 34 34 34 20 Typ Max Unit W Unit Notes 1,4,5,7 1,4,5,7 1,4,5,7 1,4,6,7 1,4,6,7 NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. T7600, T7400, T7200 processors feature 4-MB cache. 6. T5600, T5500 processors feature 2-MB cache. 7. At Tj of 100°C. 8. At Tj of 50°C. 9. At Tj of 35°C. 82 Datasheet Thermal Specifications and Design Considerations Table 18. Power Specifications for the Dual-core Low Voltage Processor Symbol Processor Number L7400 TDP Symbol PAH, PSGNT at HFM VCC at LFM VCC Sleep Power PSLP at HFM VCC at LFM VCC Deep Sleep Power PDSLP PDPRSLP PDC4 TJ at HFM VCC at LFM VCC Deeper Sleep Power Intel Enhanced Deeper Sleep Power Junction Temperature 0 2.9 2.8 1.5 0.9 100 W W °C 2, 9 2, 9 3, 4 W 2, 9 4.9 4.4 W 2, 8 L7200 Core Frequency & Voltage 1.50 GHz & HFM VCC 1.33 GHz & HFM VCC 1.00 GHz & LFM VCC Parameter Auto Halt, Stop Grant Power 5.2 4.6 W 2, 8 Min Thermal Design Power 17 17 15.1 Typ Max Unit W 1, 4, 7 Unit Notes NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. 4-M cache. 6. 2-M cache. 7. At Tj of 100°C. 8. At Tj of 50°C. 9. At Tj of 35°C. Datasheet 83 Thermal Specifications and Design Considerations Table 19. Power Specifications for the Single and Dual-core Ultra Low Voltage Processor Symbol Processor Number U7600 TDP U7500 U2200 U2100 Symbol PAH, PSGNT Core Frequency & Voltage 1.20 GHz & HFM VCC 1.06 GHz & HFM VCC 1.20 GHz & HFM VCC 1.06 GHz & HFM VCC 0.80 GHz & LFM VCC Parameter Auto Halt, Stop Grant Power at HFM VCC at LFM VCC Sleep Power PSLP at HFM VCC at LFM VCC Deep Sleep Power PDSLP at HFM VCC at LFM VCC PDPRSLP PDC4 TJ Deeper Sleep Power Intel® Enhanced Deeper Sleep Power Junction Temperature 0 Min Thermal Design Power 10 10 5.5 5.5 9.2- DC 4.6-SC Typ Max 3.1- DC 2.6-DC 1.7-SC 1.4-SC 3.0-DC 2.5-DC 1.6- SC 1.3-SC 1.5-DC 1.3-DC 0.8-SC 0.7-SC 1.0-DC 0.6-SC 0.7-DC 0.4-SC 100 W W °C 2, 9 2, 9 3, 4 W 2, 9 W 2, 8 W 2, 8 Unit W 1, 4, 7 Unit Notes NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. 4-M cache. 6. 2-M cache. 7. At Tj of 100°C. 8. At Tj of 50°C. 9. At Tj of 35°C. 84 Datasheet Thermal Specifications and Design Considerations 5.1 Thermal Specifications The processor incorporates three methods of monitoring die temperature: the digital thermal sensor, Intel Thermal Monitor and the thermal “diode.” The Intel Thermal Monitor (detailed in Section 5.1.3) must be used to determine when the maximum specified processor junction temperature has been reached. 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to Ground. The thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor Model Specific Register (MSR) and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage recommendation when the PROCHOT# signal is not asserted. Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change. Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of the thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the processor MSR. Table 20 through Table 23 provides the diode interface and specifications. Two different sets of diode parameters are listed in Table 22 and Table 23. The diode model parameters apply to the traditional thermal sensors that use the diode equation to determine the processor temperature. Transistor model parameters have been added to support thermal sensors that use the transistor equation method. The Transistor model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. Please contact your external sensor supplier for their recommendation. The thermal diode is separate from the Intel Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor. 5.1.2 Thermal Diode Offset In order to improve the accuracy of the diode based temperature measurements, a temperature offset value (specified as Toffset) will be programmed in the processor Model Specific Register (MSR) which will contain thermal diode characterization data. During manufacturing each processor thermal diode will be evaluated for its behavior relative to the theoretical diode. Using the equation above, the temperature error created by the difference ntrim and the actual ideality of the particular processor will be calculated. Datasheet 85 Thermal Specifications and Design Considerations If the ntrim value used to calculate the Toffset differs from the ntrim value used to in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the ntrim as defined in the temperature sensor manufacturer’s datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 20. Table 20. Thermal Diode ntrim and Diode Correction Toffset Symbol ntrim Parameter Diode Ideality used to calculate Toffset 1.01 Unit Table 21. Thermal Diode Interface Signal Name THERMDA THERMDC Pin/Ball Number A24 A25 Signal Description Thermal diode anode Thermal diode cathode Table 22. Thermal Diode Parameters using Diode Mode Symbol IFW n RTT Parameter Forward Bias Current Diode Ideality Factor Series Resistance Min 5 1.000 2.79 Typ N/A 1.009 4.52 Max 200 1.050 6.24 Unit µA N/A Ω Notes 1 2, 3, 4 2, 3, 5 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. Characterized across a temperature range of 50-100 °C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVD/nkT) -1), where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RTT, is provided to allow for a more accurate measurement of the diode junction temperature. RTT as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RTT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RTT*(N-1)*IFWmin]/[(no/q)*ln N] where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, and q = electronic charge. 86 Datasheet Thermal Specifications and Design Considerations Table 23. Thermal Diode Parameters Using Transistor Model Symbol IFW IE nQ Beta RTT Series Resistance Parameter Forward Bias Current Emitter Current Transistor Ideality Min 5 5 0.997 0.3 2.79 4.52 1.001 Typ Max 200 200 1.005 0.760 6.24 Ω Unit µA µA Notes 1, 2 1 3, 4, 5 3, 4 3, 6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 22 3. Characterized across a temperature range of 50-100 °C. 4. Not 100% tested. Specified by design characterization. 5. The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the equation for the collector current: IC=Is *(e(qVBE/nQkT) -1) where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin). 6. The series resistance, RTT, provided in the Diode Model Table (Table 22) can be used for more accurate readings as needed. When calculating a temperature based on the thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 22. In most sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode, the ideality value (also called ntrim) will be 1.000. Given that most diodes are not perfect, the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. If the processor diode ideality deviates from that of the ntrim, each calculated temperature will be offset by a fixed amount. This temperature offset can be calculated with the equation: Terror(nf) = Tmeasured * (1 - nactual/ntrim) Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing device. 5.1.3 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An under- Datasheet 87 Thermal Specifications and Design Considerations designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and on-demand mode. If both modes are activated, automatic mode takes precedence. Note: The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. There are two automatic modes called Intel Thermal Monitor 1 and Intel Thermal Monitor 2. These modes are selected by writing values to the MSRs of the processor. After automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. Likewise, when Intel Thermal Monitor 2 is enabled and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep Technology transition to a lower operating point. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. Intel Thermal Monitor 1 and Intel Thermal Monitor 2 can co-exist within the processor. If both Intel Thermal Monitor 1 and Intel Thermal Monitor 2 bits are enabled in the auto-throttle MSR, Intel Thermal Monitor 2 will take precedence over Intel Thermal Monitor 1. However, if Intel Thermal Monitor 2 is not sufficient to cool the processor below the maximum operating temperature then Intel Thermal Monitor 1 will also activate to help cool down the processor. Intel recommends Intel Thermal Monitor 1 and Intel Thermal Monitor 2 be enabled on the processors. If a processor load based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when an Intel Thermal Monitor 2 period is active, there are two possible results: 1. If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is higher than the Intel Thermal Monitor 2 transition based target frequency, the processor load-based transition will be deferred until the Intel Thermal Monitor 2 event has been completed. 2. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the Intel Thermal Monitor 2 transition based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep Technology target frequency point. When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a noncritical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. 88 Datasheet Thermal Specifications and Design Considerations The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states, hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3. 5.1.4 Digital Thermal Sensor The processor also contains an on-die digital thermal sensor that can be read via a MSR (no I/O interface). In a dual-core implementation of the processor, each core will have a unique digital thermal sensor whose temperature is accessible via processor MSR. The digital thermal sensor is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor. The digital thermal sensor is only valid while the processor is in the normal operating state (C0 state). Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature relative to the maximum supported operating temperature of the processor (TJ,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the digital thermal sensor will always be at or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. Datasheet 89 Thermal Specifications and Design Considerations The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the Intel Thermal Monitor (Intel Thermal Monitor 1/Intel Thermal Monitor 2) trigger point. When the DTS indicates maximum processor core temperature has been reached the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 hardware thermal control mechanism will activate. The DTS and Intel Thermal Monitor 1/Intel Thermal Monitor 2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications. Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual for specific register and programming details. 5.1.5 Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s Intel Thermal Monitor 1 or Intel Thermal Monitor 2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt. 5.1.6 PROCHOT# Signal Pin An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled (note that the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from over-heating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. In a dual-core implementation, only a single PROCHOT# pin exists at a package level. When either core's thermal sensor trips, PROCHOT# signal will be driven by the processor package. If only Intel Thermal Monitor 1 is enabled, PROCHOT# will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated. If Intel Thermal Monitor 2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed Intel Thermal Monitor 2 performance state. It is important to note that Intel recommends both Intel Thermal Monitor 1 and Intel Thermal Monitor 2 to be enabled. When PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is enabled on both cores, then both processor cores will have their core clocks modulated. If Intel Thermal Monitor 2 is enabled on both cores, then both processor core will enter the lowest programmed Intel Thermal Monitor 2 performance state. One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and 90 Datasheet Thermal Specifications and Design Considerations activating the TCC, the VR can cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An underdesigned thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. §§ Datasheet 91