LN80C51FA

80C51FA 83C51FA EVENT-CONTROL CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Automotive Y Extended Automotive Temperature Range ( b 40 C to a 125 C Ambient) High Performance CHMOS Process Three 16-Bit Timer Counters Timer 2 is an Up Down Timer Counter Programmable Counter Array with High Speed Output Compare Capture Pulse Width Modulator Watchdog Timer Capabilities 8K On-Chip ROM 256 Bytes of On-Chip Data RAM Boolean Processor 32 Programmable I O Lines 7 Interrupt Sources Y Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS 51 Microcontroller Fully Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode Available in PLCC and PDIP Packages (See Packaging Specification Order 231369) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Available in 12 MHz and 16 MHz Versions MEMORY ORGANIZATION PROGRAM MEMORY Up to 8 Kbytes of the program memory can reside in the on-chip ROM In addition the device can address up to 64K of program memory external to the chip DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of external data memory The Intel 80C51FA 83C51FA is a single-chip control oriented microcontroller which is fabricated on Intel’s CHMOS III (83C51FA) ROM technology For the remainder of this datasheet references to the ROMless (80C51FA) and ROM (83C51FA) versions will be denoted as 83C51FA Being a member of the MCS 51 microcontroller family the 83C51FA uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with the existing MCS 51 microcontroller products The 83C51FA is an enhanced version of the 87C51 It’s added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation High Speed I O and up down counting capabilities such as brake and traction control It also has a more versatile serial channel that facilitates multi-processor communications NOTICE This datasheet contains information on products in full production Specifications within this datasheet are subject to change without notice Verify with your local Intel sales office that you have the latest datasheet before finalizing a design Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 February 1995 Order Number 270501-007 AUTOMOTIVE 80C51FA 83C51FA 270501 – 1 Figure 1 83C51FA Block Diagram 2 AUTOMOTIVE 80C51FA 83C51FA temperature range of 0 C to 70 C ambient With the extended temperature range option operational characteristics are guaranteed over the temperature range of b 40 C to a 85 C ambient For the automotive temperature range option operational characteristics are guaranteed over the temperature range of b 40 C to a 125 C ambient As shown in Figure 2 temperature burn-in and package options are identified by a one- or two-letter prefix to the part number 80C51FA 83C51FA PRODUCT OPTIONS Intel’s extended and automotive temperature range products are designed to meet the needs of those applications whose operating requirements exceed commercial standards With the commercial standard temperature range operational characteristics are guaranteed over the 270501 – 2 Example AN83C51FA indicates an automotive temperature range version of the 83C51FA in a PLCC package with 8 Kbyte ROM program memory Figure 2 MCS 51 Microcontroller Product Family Nomenclature Table 1 Temperature Options Temperature Classification Extended Automotive Temperature Designation T L A B Operating Temperature C Ambient b 40 to a 85 b 40 to a 85 b 40 to a 125 b 40 to a 125 Burn-In Options Standard Extended Standard Extended 3 AUTOMOTIVE 80C51FA 83C51FA PIN DESCRIPTIONS VCC Supply voltage VSS Circuit ground Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1’s written to them float and in that state can be used as high-impedance inputs Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory In this application it uses strong internal pullups when emitting1’s and can source and sink several LS TTL inputs Port 0 outputs the code bytes during program verification External pullup resistors are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally pulled low will source current (IIL on the datasheet) because of the internal pullups In addition Port 1 serves the functions of the following special features of the 83C51FA Port Pin P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 Alternate Function T2 (External Count Input to Timer Counter 2) T2EX (Timer Counter 2 Capture Reload Trigger and Direction Control) ECI (External Count Input to the PCA) CEX0 (External I O for Compare Capture Module 0) CEX1 (External I O for Compare Capture Module 1) CEX2 (External I O for Compare Capture Module 2) CEX3 (External I O for Compare Capture Module 3) CEX4 (External I O for Compare Capture Module 4) Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups The Port 2 output buffers can drive LS TTL inputs Port 2 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally pulled low will source current (IIL on the datasheet) because of the internal pullups Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR) In this application it uses strong internal pullups when emitting 1’s During accesses to external Data Memory that use 8-bit Pad (PLCC) Pin (PDIP) 270501 – 3 270501 – 4 Do not connect reserved pins Diagrams are for pin reference only Package sizes are not to scale Figure 3 Pin Connections 4 AUTOMOTIVE 80C51FA 83C51FA addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (IIL on the datasheet) because of the pullups Port 3 also serves the functions of various special features of the MCS 51 microcontroller family as listed below Port Pin P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) EA VPP External Access enable EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory locations 0000H to 0FFFFH Note however that if either of the Program Lock bits are programmed EA will be internally latched on reset EA should be strapped to VCC for internal program executions XTAL1 Input to the inverting oscillator amplifier XTAL2 Output from the inverting oscillator amplifier OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of a inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 4 Either a quartz crystal or ceramic resonator may be used More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155 ‘‘Oscillators for Microcontrollers ’’ To drive the device from an external clock source XTAL1 should be driven while XTAL2 floats as shown in Figure 5 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the datasheet must be observed An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF RESET Reset input A high on this pin for two machine cycles while the oscillator is running resets the device An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC ALE PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory In normal operation ALE is emitted at a constant rate of the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory Throughout the remainder of this datasheet ALE will refer to the signal coming out of the ALE PROG pin and the pin will be referred to as the ALE PROG pin PSEN Program Store Enable is the read strobe to external Program Memory When the 83C51FA is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data Memory 270501 – 5 C1 C2 e 30 pF g 10 pF for Crystals For Ceramic Resonators contact resonator manufacturer Figure 4 Oscillator Connections 5 AUTOMOTIVE 80C51FA 83C51FA restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms) With an external interrupt INT0 or INT1 must be enabled and configured as level-sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down 270501 – 6 Figure 5 External Clock Drive Configuration DESIGN CONSIDERATION IDLE MODE The user’s software can invoke the Idle Mode When the microcontroller is in this mode power consumption is reduced The Special Function Registers and the onboard RAM retain their values during Idle but the processor stops executing instructions Idle Mode will be exited if the chip is reset or if an enabled interrupt occurs The PCA timer counter can optionally be left running or paused during Idle Mode When the Idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control Onchip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory POWER DOWN MODE To save even more power a Power Down mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values if the Power Down mode is terminated with an interrupt On the 83C51FA either a hardware reset or external interrupt can cause an exit from Power Down Reset redefines all the SFRs but does not change the onchip RAM An external interrupt allows both the SFRs and the on-chip RAM to retain their values To properly terminate Power Down the reset or external interrupt should not be executed before VCC is ONCE MODE The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates testing and debugging of systems using the 83C51FA without the 83C51FA having to be removed from the circuit The ONCE Mode is invoked by 1) Pull ALE low while the device is in reset and PSEN is high 2) Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins float the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the 83C51FA is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied Table 2 Status of the External Pins during Idle and Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data NOTE For more detailed information on the reduced power modes refer to current Embedded Applications Handbook and Application Note AP-252 ‘‘Designing with the 80C51BH ’’ 6 AUTOMOTIVE 80C51FA 83C51FA ABSOLUTE MAXIMUM RATINGS b 40 C to a 125 C b 65 C to a 150 C Storage Temperature b 0 5V to a 6 5V Voltage on Any Other Pin to VSS NOTICE This is a production data sheet The specifications are subject to change without notice Ambient Temperature Under Bias IOL I O Pin 15 mA WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability Power Dissipation 1 5W (Based on PACKAGE heat transfer limitations not device power consumption) a 135 C Typical Junction Temperature (TJ) (Based upon Ambient Temperature at a 125 C) Typical Thermal Resistance Junction-to-Ambient (iJA) PDIP PLCC 45 C W 46 C W DC CHARACTERISTICS Symbol VIL VIL1 VIH VIH1 VOL VOL1 Parameter Input Low Voltage Input Low Voltage EA (TA e b 40 C to a 125 C VCC e 5V g 10% VSS e 0V) Min b0 5 Typ Max 0 2 VCC b 0 1 0 2 VCC b 0 3 VCC a 0 5 VCC a 0 5 0 45 0 45 Unit V V V V V V Test Conditions 0 0 2 VCC a 0 9 0 7 VCC Input High Voltage (Except XTAL2 RST EA) Input High Voltage (XTAL RST) Output Low Voltage (Ports 1 2 and 3) Output Low Voltage (Port 0 ALE PROG PSEN) Output High Voltage (Ports 1 2 and 3 ALE PROG and PSEN) Output High Voltage (Port 0 in External Bus Mode) IOL e 1 6 mA(1) IOL e 20 IOL e 3 2 mA(1) IOL e 7 0 mA IOH e b 60 mA IOH e b 10 mA(2) IOH e b 800 mA IOH e b 80 mA(2) VIN e 0 45V VIN e VIL or VIH VOH 24 0 9 VCC 24 0 9 VCC b 10 b 50 g 10 V V V V mA mA VOH1 IIL ILI Logical 0 Input Current (Ports 1 2 and 3) Input leakage Current (Port 0) 0 02 7 AUTOMOTIVE 80C51FA 83C51FA DC CHARACTERISTICS Symbol ITL RRST CIO ICC (TA e b 40 C to a 125 C VCC e 5V g 10% VSS e 0V) (Continued) Min Typ b 265 Parameter Logical 1 to 0 Transition Current (Ports 1 2 and 3) RST Pulldown Resistor Pin Capacitance Power Supply Current Running at 12 MHz (Figure 5) Idle Mode at 12 MHz (Figure 5) Power Down Mode (IPD) Max b 650 Unit mA KX pF Test Conditions VIN e 2V 40 100 10 225 1MHz 25 C (Note 3) 40 15 150 mA mA mA NOTES 1 Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations In applications where capacitance loading exceeds 100 pFs the noise pulse on the ALE signal may exceed 0 8V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch with a Schmitt Trigger Strobe input 2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0 9 VCC specification when the address lines are stabilizing 3 See Figures 6–9 for test conditions Minimum VCC for Power Down is 2 0V 4 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and 5 0V 5 Under steady state (non-transient) conditions IOL must be externally limited as follows 10 mA Maximum IOL per Port Pin Maximum IOL per 8-Bit Port Port 0 26 mA Ports 1 2 and 3 15 mA 71 mA Maximum Total IOL for all Output Pins If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 6 Contact Intel for design-in information 8 AUTOMOTIVE 80C51FA 83C51FA 270501 – 7 ICC Max at other frequencies is given by Active Mode ICC Max e (3 c Osc Freq) a 4 Idle Mode ICC Max e (0 49 c Osc Freq) a 1 6 Where Osc Freq is in MHz ICC is in mA 270501 – 8 TCLCH e TCHCL e 5 ns Figure 7 ICC Test Condition Active Mode All other pins disconnected Figure 6 ICC vs Frequency 270501 – 10 270501 – 9 TCLCH e TCHCL e 5 ns Figure 8 ICC Test Condition Idle Mode All other pins disconnected Figure 9 ICC Test Condition Power Down Mode All other pins disconnected VCC e 2 0V to 5 5V 270501 – 11 Figure 10 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns 9 AUTOMOTIVE 80C51FA 83C51FA L Logic level LOW or ALE P PSEN Q Output Data R RD signal T Time V Valid W WR signal X No longer a valid logic level Z Float For example TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters The first character is always a ‘T’ (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input Data H Logic level HIGH I Instruction (program memory contents) AC CHARACTERISTICS (TA e b 40 C to a 125 C VCC e 5V g 10% VSS e 0V Load Capacitance for Port 0 ALE PROG and PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS Symbol 1 TCLCL TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TWHQX TQVWH TRLAZ TWHLH Parameter Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instr Hold After PSEN Trans Input Instr Float After PSEN Trans Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD High Data Float After RD High ALE Low to Valid Data In Address Valid to Valid Data In ALE Low to RD or WR Low Data Valid to WR Low Address Valid before WR Low Data Hold after WR High Data Valid to WE High RD Low to Address Float RD or WR High to ALE High 43 200 203 23 33 433 0 123 TCLCL b 40 b 10 12 MHz Oscillator Min 127 43 53 224 53 205 135 0 59 302 10 400 400 242 Max Variable Oscillator Min 35 2TCLCL b 40 TCLCL b 40 TCLCL b 30 4TCLCL b 110 TCLCL b 30 3TCLCL b 45 3TCLCL b 115 0 TCLCL b 25 5TCLCL b 115 10 6TCLCL b 100 6TCLCL b 100 5TCLCL b 175 b 10 Max 16 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 107 507 575 300 3TCLCL b 50 4TCLCL b 130 TCLCL b 50 TCLCL b 50 7TCLCL b 150 2TCLCL b 60 8TCLCL b 160 9TCLCL b 175 3TCLCL a 50 0 TCLCL a 40 ns ns 10 AUTOMOTIVE 80C51FA 83C51FA EXTERNAL PROGRAM MEMORY READ CYCLE 270501 – 12 EXTERNAL DATA MEMORY READ CYCLE 270501 – 13 EXTERNAL DATA MEMORY WRITE CYCLE 270501 – 14 11 AUTOMOTIVE 80C51FA 83C51FA SERIAL PORT TIMING Test Conditions Symbol TXLXL TQVXH TXHQX TXHDX TXHDV SHIFT REGISTER MODE TA e b 40 C to a 125 C VCC e 5V g 10% VSS e 0V Load Capacitance e 80 pF 12 MHz Oscillator Variable Oscillator Parameter Units Min Max Min Max 1 700 50 0 700 12TCLCL 10TCLCL b 133 2TCLCL b 117 0 10TCLCL b 133 ms ns ns ns ns Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 270501 – 15 EXTERNAL CLOCK DRIVE Symbol 1 TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency High Time Low Time Rise Time Fall Time Min 35 20 20 20 20 Max 16 Units MHz ns ns ns ns EXTERNAL CLOCK DRIVE WAVEFORM 270501 – 16 12 AUTOMOTIVE 80C51FA 83C51FA AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 270501 – 17 AC Inputs during testing are driven at VCC b 0 5V for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0’’ Timing measurements are made at VIH min for a Logic ‘‘1’’ and VOL max for a Logic ‘‘0’’ 270501 – 18 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH VOL level occurs IOL IOH t g 20 mA This is for Ports 1 2 and 3 DATASHEET REVISION HISTORY The following are key differences between this datasheet and the -006 version 1 The ‘‘preliminary’’ status was dropped and replaced with production status (no label) 2 Trademarks were updated The following are key differences between the -006 and the -005 version of the datasheet 1 Preliminary notice has been added to the Title page 2 Figure 3 Pin Connections has been modified RST pin is now RESET pin 3 RST pin description is now RESET pin description 4 Figure 6 ICC vs Frequency has been corrected to show test conditions 5 ICC Max spec has been corrected 6 A C Characteristic table 1 TCLCL spec has been changed to have a Max frequency of 16 MHz The following are key differences between the -005 and the -004 version of the datasheet 1 ‘‘NC’’ pin labels changed to ‘‘Reserved’’ in Figure 3 2 Capacitor value for ceramic resonators deleted in Figure 4 The following are the key differences between the -003 version of the 8XC51FA datasheet and the -004 version of the 80C51FA 83C51FA datasheet 1 Removed references to EPROM from the 8XC51FA datasheet 2 Revised Figure 4 ‘‘Oscillator Connections’’ The following are the key differences between the -002 and the -003 version of this datasheet 1 Dropped word ‘‘maximum’’ from IOL in the Absolute Maximum Rating table 2 Dropped EA from ILI specification of the DC table 3 Corrected TQVWH specification (from TTCLCL b 70 to TCLCL b 150) 4 Added note on external clock capacitance loading 5 Changed the title to 80C51FA 83C51FA Event-Control CHMOS Single-Chip 8-Bit Microcontroller 6 Added pin count to Figure 1 7 Changed ILI to g 10 mA 8 Added ICC Power Down Mode 150 nA 13