LU82541ER

82541ER Gigabit Ethernet Controller Networking Silicon Datasheet Product Features ■ ■ ■ PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — 3.3 V (5 V tolerant PCI signaling) MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers PHY Specific — Integrated for 10/100/1000 Mb/s operation — IEEE 802.3ab Auto-Negotiation support — IEEE 802.3ab PHY compliance and compatibility — State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation ■ ■ ■ ■ — Automatic polarity detection — Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation — Advanced packed filtering — Jumbo frame support up to 16 KB — Intelligent Interrupt generation (multiple packets per interrupt) Manageabiltiy — Network Device Class Power Management Specification 1.1 — Compliance with PCI Power Management 1.1 and ACPI 2.0 — SNMP and RMON statistic counters — D0 and D3 power states Additional Device — Four programmable LED outputs — On-chip power control circuitry — BIOS LAN Disable pin — JTAG (IEEE 1149.1) Test Access Port built in silicon Lead-freea 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at 1.8V > 1.2V. This is important to avoid stress in the ESD protection circuits. After 3.3V reaches 10% of its final value, all voltage rails (1.8V and 1.2V) have 150 ms to reach their final operating values. 3.3V Supply Voltage Ramp Parameter Rise Time Monotonicity Slope Operational Range Ripple Overshoot Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth equal to 50 MHz Maximum voltage allowed 3 Min 0.1 Max 100 0 28800 3.6 70 4 Unit ms mV V/s V mV V Table 3. Table 4. 1.8V Supply Voltage Ramp Symbol Rise Time Monotonicity Slope Operational Range Operational Range Operational Range Operational Range Parameter Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions (PNP’s)a Voltage range for normal operating conditions (PNP’s) Voltage range for normal operating conditions (external regulator) Voltage range for normal operating conditions (external regulator) 1.674 -7 1.71 -5 Min 0.1 Max 100 0 57600 1.89 5 1.89 5 Unit ms mV V/s V % V % 16 Datasheet 82541ER Gigabit Ethernet Controller Table 4. 1.8V Supply Voltage Ramp Ripple Overshoot Output Capacitance Input Capacitance Capacitance ESR Ictrl_18 Maximum voltage ripple at a bandwidth equal to 50 MHz Maximum voltage allowed Capacitance range when using PNP circuit Capacitance range when using PNP circuit Equivalent series resistance of output capacitanceb Maximum output current rating to CTRL18 4.7 4.7 5 20 2.2 20 20 100 20 mV V µF µF mΩ mA a. Operating with an internal regulator (PNP) supports a wider tolerance output voltage due to process tracking. b. Tantalum capacitors must not be used. Table 5. 1.2V Supply Voltage Ramp Symbol Rise Time Monotonicity Slope Operational Range Operational Range Operational Range Operational Range Ripple Overshoot Output Capacitance Input Capacitance Capacitance ESR Ictrl_12 Parameter Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions (PNP’s)a Voltage range for normal operating conditions (PNP’s) Voltage range for normal operating conditions (external regulator) Voltage range for normal operating conditions (external regulator) Maximum voltage ripple at a bandwidth equal to 50 MHz Maximum voltage allowed Capacitance range when using PNP circuit Capacitance range when using PNP circuit Equivalent series resistance of output capacitanceb Maximum output current rating to CTRL_12 4.7 4.7 5 1.116 -7 1.14 -5 Min 0.025 0 38400 1.26 5 1.26 5 20 1.45 20 20 100 20 Max Unit ms mV V/s V % V % mV V µF µF mΩ mA a. Operating with an internal regulator (PNP) supports a wider tolerance output voltage due to process tracking. b. Tantalum capacitors must not be used. Datasheet 17 82541ER Gigabit Ethernet Controller 4.3 Table 6. DC Specifications DC Characteristics Symbol VDD (3.3) VDD (1.8) VDD (1.2) Parameter DC supply voltage on 3.3 V pins DC supply voltage on 1.8 V pins DC supply voltage on 1.2 V pins Condition Min 3.00 1.71a 1.14c Typ 3.3 1.8 1.2 Max 3.60 1.89b 1.26d Units V V V a. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.67 V. b. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is 1.926 V. c. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.12 V. d. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is 1.284 V. Table 7. Power Specifications - D0a D0a unplugged no link Typ Icc (mA)a 3.3V 1.8V 1.2V Total Device Power 3 14 30 @10 Mbps Typ Icc (mA)a 5 85 85 @100 Mbps Typ Icc (mA)a 13 110 90 @ 1000 Mbps Typ Icc (mA)a 30 315 380 Max Icc (mA)b 5 15 35 Max Icc (mA)b 10 85 90 Max Icc (mA)b 15 115 100 Max Icc (mA)b 40 320 400 75 mW 270 mW 355 mW 1.1 W 1.2 W a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface. Table 8. Power Specifications - D3cold D3cold - wake-up enableda unplugged link Typ Icc (mA)b 3.3V 2 @10 Mbps Typ Icc (mA)a 2 @100 Mbps Typ Icc (mA)a 2 D3cold-wake disabled Typ Icc (mA)a 4 Max Icc (mA)c 3 Max Icc (mA)b 3 Max Icc (mA)b 3 Max Icc (mA)b 5 18 Datasheet 82541ER Gigabit Ethernet Controller Table 8. Power Specifications - D3cold D3cold - wake-up enableda unplugged link Typ Icc (mA)b 1.8V 1.2V Total Device Power 14 21 @10 Mbps Typ Icc (mA)a 20 30 @100 Mbps Typ Icc (mA)a 110 80 D3cold-wake disabled Typ Icc (mA)a 1 7 Max Icc (mA)c 15 25 Max Icc (mA)b 25 35 Max Icc (mA)b 115 85 Max Icc (mA)b 2 10 60 mW 80 mW 305 mW 25 mW a. The power consumption for 1000 Mbps is not shown since the controller moves to the 10/100 Mbps mode before going into the D3 state to conserve power. b. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. c. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface. Table 9. Power Specifications D(r) Uninitialized) D(r) Uninitialized (FLSH_SO/LAN_DISABLE # = 0) Typ Icc (mA) 3.3V 1.8V 1.2V Total Device Power 5 1 12 Max Icc (mA) 10 2 15 35 mW Table 10. Power Specifications - Complete Subsystem Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits D3cold - wake disabled Max Icc (mA)b 5 D3cold wakeenabled @ 10 Mbps Typ Icc (mA)a 7 D0 @10 Mbps active Max Icc (mA)b D0 @100 Mbps active Max Icc (mA)b 15 D0 @ 1000 Mbps active Typ Icc (mA)a 33 Typ Icc (mA)a 3.3 V 4 Max Icc (mA)b 10 Typ Icc (mA)a Typ Icc (mA)a 12 Max Icc (mA)b 45 Datasheet 19 82541ER Gigabit Ethernet Controller Table 10. Power Specifications - Complete Subsystem Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits D3cold - wake disabled Max Icc (mA)b 7 7 D3cold wakeenabled @ 10 Mbps Typ Icc (mA)a 2 10 D0 @10 Mbps active Max Icc (mA)b D0 @100 Mbps active Max Icc (mA)b 135 80 D0 @ 1000 Mbps active Typ Icc (mA)a 140 85 Typ Icc (mA)a 1.8 V 1.2 V Subsystem 3.3V Current 1 Max Icc (mA)b 30 30 Typ Icc (mA)a Typ Icc (mA)a 35 35 Max Icc (mA)b 410 380 10 40 120 710 a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface. Table 11. I/O Characteristics (Sheet 1 of 2) Symbol VIH VIL Parameter Input high voltage Input low voltage Input current Input with pulldown resistor (50 KΩ) Inputs with pull-up resistor (50 KΩ) Condition 3.3 V PCI 3.3 V PCIa 0 < VIN < VDD(3.3) VIN = VDD(3.3) Min 0.5 * VDD(3.3) VSS -10 28 Typ Max VDD(3.3) or VIO 0.3 * VDD(3.3) 10 191 Units V V IIN µA VIN = VSS 3.3 V PCI -28 -191 2.09 100 * VOUT mA IOL Output low current 0 ≤ VOUT ≤ 3.6V 0 ≤ VOUT ≤ 1.3V 1.3V ≤ VOUT ≤ 3.6V 0 ≤ (VDD-VOUT) ≤ 3.6V 48 * VOUT 5.7 * VOUT+ 55 -74 * (VDD VOUT) -32 * (VDD VOUT) -11 * (VDD VOUT)-25.2 -1.8 * (VDD VOUT)-42.7 V IOH Output high current: 0 ≤ (VDD-VOUT) ≤ 1.2V 1.2V ≤ (VDD-VOUT) ≤ 1.9V 1.9V ≤ (VDD-VOUT) ≤ 3.6V mA VOH Output high voltage: 3.3 V PCI IOH = -500 mA 0.9 * VDD(3.3) 20 Datasheet 82541ER Gigabit Ethernet Controller Table 11. I/O Characteristics (Sheet 2 of 2) (Continued) Symbol Parameter Output low voltage: 3.3 V PCI IOZ IOS CIN Off-state output leakage current Output short circuit current Input capacitanceb Input and bidirectional buffers 8 IOL = 1500 mA VO = VDD or VSS -10 0.1 * VDD(3.3) 10 -250 µA mA pF Condition Min Typ Max Units VOL V a. The maximum VIL is 0.6 V for the following Pins: A13, C5, C8, J4, L7, L12, L13, M8, M12, M13, N10, N11, N13, N14, P9, and P13. b. VDD (3.3) = 0 V; TA = 25 C; f = 1 Mhz 4.4 AC Characteristics Table 12. AC Characteristics: 3.3 V Interfacing Symbol PCICLK Parameter Clock frequency in PCI mode Min Typ Max 66 Unit MHz Table 13. 25 MHz Clock Input Requirements Specifications Symbol f0 df0 Dc tr tf Jptp Cin T Aptp Vcm Frequency Frequency variation Duty cycle Rise time Fall time Clock jitter (peak-to-peak) Input capacitance Operating temperature Input clock amplitude (peak-to-peak) Clock common mode 1.0 1.2 0.6 a Parameter Min Typ 25 -50 40 +30 60 5 5 250 20 70 1.3 Units Max MHz ppm % ns ns ps pF °C V V a. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000BASE-T Standard (at least 105 clock edges, filtered by HPF with cut off frequency 5000 Hz). Datasheet 21 82541ER Gigabit Ethernet Controller Table 14. Reference Crystal Specification Requirements Specification Vibrational Mode Nominal Frequency Frequency Tolerance Temperature Stability Calibration Mode Load Capacitance Shunt Capacitance Series Resistance, Rs Drive Level Aging Insulation Resistance Fundamental 25.000 MHz at 25° C ±30 ppm ±30 ppm at 0° C to 70° C Parallel 20 pF to 24 pF 6 pF maximum 50 W maximum 0.5 mW maximum ±5.0 ppm per year maximum 500 MΩ at DC 100 V Value Table 15. Link Interface Clock Requirements Symbol fGTX a Parameter GTX_CLK frequency Min Typ 125 Max Unit MHz a. GTX_CLK is used externally for test purposes only. Table 16. EEPROM Interface Clock Requirements Symbol fSK SPI EEPROM Clock 2 MHz Parameter Microwire EEPROM Clock Min Typ Max 1 Unit MHz Table 17. AC Test Loads for General Output Pins Symbol CL CL CL CL TDO SDP[3:0] EEDI, EESK LED[3:0] Signal Name Value 10 16 18 20 Units pF pF pF pF 22 Datasheet 82541ER Gigabit Ethernet Controller CL Figure 2. AC Test Loads for General Output Pins 4.5 4.5.1 4.5.1.1 Timing Specifications PCI Bus Interface PCI Bus Interface Clock Table 18. PCI Bus Interface Clock Parameters PCI 66 MHz Symbol TCYC TH TL PCI 33 MHz Units Min 30 11 11 Parametera Min CLK cycle time CLK high time CLK low time CLK slew rate RST# slew rateb 15 6 6 1.5 50 4 Max 30 Max ns ns ns 4 V/ns mV/ns 1 50 a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown. b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot render a monotonic signal to appear bouncing in the switching range. Tcyc 3.3 V Clock Th 0.6 Vcc 0.4 Vcc p-to-p (minimum) 0.5 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc Tl PCI Clock Timing.vsd Figure 3. PCI Clock Timing Datasheet 23 82541ER Gigabit Ethernet Controller 4.5.1.2 PCI/PCI-X Bus Interface Timing Table 19. PCI Bus Interface Timing Parameters PCI 66MHz Symbol Parameter Min TVAL TVAL(ptp) TON TOFF TSU TSU(ptp) TH CLK to signal valid delay: bussed signals CLK to signal valid delay: pointto-point signals Float to active delay Active to float delay Input setup time to CLK: bussed signals Input setup time to CLK: point-topoint signals Input hold time from CLK 3 5 0 2 2 2 14 7 10, 12 0 PCI 33 MHz Units Min 2 2 2 28 Max 6 6 Max 11 12 ns ns ns ns ns ns ns NOTES: 1. Output timing measurements are as shown. 2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed. 3. Input timing measurements are as shown. VTH PCI_CLK VTEST VTL Output Delay output current ≤ leakage current VTEST VSTEP (3.3V Signalling) Tri-State Output TON TOFF Figure 4. PCI Bus Interface Output Timing Measurement 24 Datasheet 82541ER Gigabit Ethernet Controller VTH PCI_CLK VTEST VTL TSU VTH Input VTL VTEST Input Valid VTEST VMAX TH Figure 5. PCI Bus Interface Input Timing Measurement Conditions Table 20. PCI Bus Interface Timing Measurement Conditions Symbol VTH VTL VTEST Parameter Input measurement test voltage (high) Input measurement test voltage (low) Output measurement test voltage Input signal slew rate PCI 66 MHz 3.3 v 0.6 * VCC 0.2 * VCC 0.4 * VCC 1.5 Unit V V V V/ns Pin 1/2 inch max. Test Point 25Ω 10 pF Figure 6. TVAL (max) Rising Edge Test Load Datasheet 25 82541ER Gigabit Ethernet Controller Pin 1/2 inch max. Test Point 10 pF 25Ω VCC Figure 7. TVAL (max) Falling Edge Test Load Figure 8. TVAL (min) Test Load Pin 1/2 inch max. Test Point 50 pF Figure 9. TVAL Test Load (PCI 5 V Signaling Environment) NOTE: Note: 50 pF load used for maximum times. Minimum times are specified with 0 pF load. 26 Datasheet 82541ER Gigabit Ethernet Controller 4.5.2 Link Interface Timing Table 21. Rise and Fall Times Symbol TR TF TR TF Parameter Clock rise time Clock fall time Data rise time Data fall time Condition 0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 to 2.0 V 2.0 V to 0.8 V Min 0.7 0.7 0.7 0.7 Max Unit ns ns ns ns 2.0 V 0.8 V TR TF Figure 10. Link Interface Rise/Fall Timing 4.5.3 EEPROM Interface Table 22. Link Interface Clock Requirements Symbol Parametera Microwire EESK pulse width TPW SPI EESK pulse width a. The EEPROM clock is derived from a 125 MHz internal clock. TPERIOD x Min Typ TPERIOD x 64 32 Max Unit ns ns Table 23. Link Interface Clock Requirements Symbol TDOS TDOH Parametera EEDO setup time EEDO hold time Min TCYC*2 0 Typ Max Unit ns ns a. The EE_DO setup and hold time is a function of the PCI bus clock cycle time but is referenced to O_EE_SK. Datasheet 27 82541ER Gigabit Ethernet Controller Note: This page is intentionally left blank. 28 Datasheet 82541ER Gigabit Ethernet Controller 5.0 Package and Pinout Information This section describes the device physical characteristics. The pin number-to-signal mapping is indicated beginning with Table 25. 5.1 Package Information The 82541ER device is a 196-lead plastic ball grid array (BGA) measuring 15 mm by 15mm. The package dimensions are detailed below. The nominal ball pitch is 1 mm. 1.56 +/-0.19 0.85 30 o 0.40 +/-0.10 0.32 +/-0.04 Seating Plate Figure 11. 82541ER Mechanical Specifications Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Datasheet 29 82541ER Gigabit Ethernet Controller Detail Area 0.45 Solder Resist Opening 0.60 Metal Diameter Figure 12. 196 PBGA Package Pad Detail As illustrated in Figure 12, the Ethernet controller package uses solder mask defined pads. The copper area is 0.60 mm and the opening in the solder mask is 0.45mm. The nominal ball sphere diameter is 0.50 mm. 30 Datasheet 82541ER Gigabit Ethernet Controller 5.2 Thermal Specifications The 82541ER device is specified for operation when the ambient temperature (TA) is within the range of 0° C to 70° C. TC (case temperature) is calculated using the equation: TC = TA + P (θJA - θJC) TJ (junction temperature) is calculated using the equation: TJ = TA + P θJA P (power consumption) is calculated by using the typical ICC and nominal VCC. The preliminary thermal resistances are shown in Table 24. Table 24. Thermal Characteristics Symbol Parameter Preliminary Value at specified airflow (m/s) 0 θJA θJC Thermal resistance, junction-to-ambient Thermal resistance, junction-to-case 29 11.1 Units 1 25.0 11.1 2 23.5 11.1 C/Watt C/Watt Thermal resistances are determined empirically with test devices mounted on standard thermal test boards. Real system designs may have different characteristics due to board thickness, arrangement of ground planes, and proximity of other components. The case temperature measurements should be used to assure that the 82541ER device is operating under recommended conditions. Datasheet 31 82541ER Gigabit Ethernet Controller 5.3 Pinout Information Table 25. PCI Address, Data and Control Signals Signal AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] Pin N7 M7 P6 P5 N5 M5 P4 N4 P3 N3 N2 M1 M2 M3 L1 L2 Signal AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] Pin K1 E3 D1 D2 D3 C1 B1 B2 B4 A5 B5 B6 C6 C7 A8 B8 Signal C/BE#[0] C/BE#[1] C/BE#[2] C/BE#[3] PAR FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL VIO Pin M4 L3 F3 C4 J1 F2 F1 G3 H1 H3 A4 G2 Table 26. PCI Arbitration Signals Signal REQ# GNT# Pin C3 J3 Table 27. Interrupt Signals Signal INTA# Pin H2 Table 28. System Signals Signal CLK M66EN Pin G1 C2 RST# Signal Pin B9 32 Datasheet 82541ER Gigabit Ethernet Controller Table 29. Error Reporting Signals Signal SERR# Pin A2 Signal PERR# Pin J2 Table 30. Power Management Signals Signal LAN_PWR_GOOD AUX_PWR Pin A9 J12 Table 31. Serial EEPROM Interface Signals Signal EESK EEDO Pin M10 N10 EEDI Signal Pin P10 J4 Signal EECS Pin P7 EEMODE Table 32. Serial FLASH Interface Signals Signal FLSH_SCK FLSH_SO/LAN_DISABLE# Pin N9 P9 Signal FLSH_SI Pin M11 Signal FLSH_CE# Pin M9 Table 33. LED Signals Signal LINK_UP# ACTIVITY# Pin A12 C11 Signal LINK100# LINK1000# Pin B11 B12 Table 34. Other Signals Signal SDP[0] SDP[1] N14 P13 Pin Signal SDP[2] SDP[3] N13 Pin M12 Datasheet 33 82541ER Gigabit Ethernet Controller Table 35. IEEE Test Signals Signal IEEE_TEST- Pin D14 Signal IEEE_TEST+ Pin B14 Table 36. PHY Signals Signal MDI[0]MDI[0]+ MDI[1]MDI[1]+ C14 C13 E14 E13 Pin Signal MDI[2]MDI[2]+ MDI[3]MDI[3]+ F14 F13 H14 H13 Pin Signal XTAL1 XTAL2 K14 J14 Pin Table 37. Test Interface Signals Signal JTAG_TCK JTAG_TDI Pin L14 M13 Signal JTAG_TDO JTAG_TMS Pin M14 L12 Signal JTAG_TRST# TEST Pin L13 A13 Table 38. Digital Power Signals Signal 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V A3 A7 A11 E1 K3 K4 K13 N6 N8 P2 P12 Pin 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Signal G5 G6 H5 H6 H7 H8 J10 J11 J5 J6 J7 J8 Pin 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Signal J9 K10 K11 K5 K6 K7 K8 K9 L10 L4 L5 L9 Pin 34 Datasheet 82541ER Gigabit Ethernet Controller Table 39. Analog Power Signals Signal ANALOG_1.2V ANALOG_1.2V ANALOG_1.2V ANALOG_1.2V E11 E12 G13 H11 Pin Signal ANALOG_1.8V ANALOG_1.8V PLL_1.2V PLL_1.2V D11 Pin Signal CLKR_1.8V XTAL_1.8V D12 J13 Pin G12 G4 H4 Table 40. Grounds and No Connect Signals Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin B3 B7 C10 D5 D6 D7 D8 E10 E2 E5 E6 E7 E8 E9 F4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal Pin F5 F6 F7 F8 F9 F10 G7 G8 G9 G10 H9 H10 K2 L6 L11 Signal VSS VSS VSS VSS AVSS AVSS AVSS AVSS AVSS AVSS NC NC NC NC NC Pin M6 N1 N12 P8 C12 D13 F11 G11 G14 K12 A1 A14 D9 D10 H12 Signal NC NC NC Pull up to VCCa Pull up to VCCa Pull up to VCCa VSS VSS NC NC NC NC NC NC NC Pin L8 P1 P14 A10 B10 C9 D4 E4 A6 C5 F12 L7 M8 N11 C8 a. Use a 1 K Ω resistor. Table 41. Voltage Regulation Control Signals Signal CTRL18 Pin B13 Signal CTRL12 Pin P11 Datasheet 35 82541ER Gigabit Ethernet Controller Table 42. Signal Names in Pin Order (Sheet 1 of 6) Signal Name NC SERR# 3.3V IDSEL AD[25] NC 3.3V AD[30] LAN_PWR_GOOD Pull up to VCCa 3.3V LINK_LED# TEST NC AD[22] AD[23] VSS AD[24] AD[26] AD[27] VSS AD[31] RST# Pull up to VCCa LINK100# LINK1000# CTRL18 IEEE_TEST+ AD[21] M66EN REQ# C/BE#[3] NC Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 36 Datasheet 82541ER Gigabit Ethernet Controller Table 42. Signal Names in Pin Order (Sheet 2 of 6) (Continued) AD[28] AD[29] NC Pull up to VCCa VSS ACTIVITY# AVSS MDI[0]+ MDI[0]AD[18] AD[19] AD[20] VSS VSS VSS VSS VSS NC NC ANALOG_1.8V CLKR_1.8V AVSS IEEE_TEST3.3V VSS AD[17] VSS VSS VSS VSS VSS VSS VSS ANALOG_1.2V ANALOG_1.2V MDI[1]+ C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 Datasheet 37 82541ER Gigabit Ethernet Controller Table 42. Signal Names in Pin Order (Sheet 3 of 6) (Continued) MDI[1]IRDY# FRAME# C/BE#[2] VSS VSS VSS VSS VSS VSS VSS AVSS NC MDI[2]+ MDI[2]CLK VIO TRDY# PLL_1.2V 1.2V 1.2V VSS VSS VSS VSS AVSS ANALOG_1.8V ANALOG_1.2V AVSS STOP# INTA# DEVSEL# PLL_1.2V 1.2V 1.2V 1.2V E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 38 Datasheet 82541ER Gigabit Ethernet Controller Table 42. Signal Names in Pin Order (Sheet 4 of 6) (Continued) 1.2V VSS VSS ANALOG_1.2V NC MDI[3]+ MDI[3]PAR PERR# GNT# EEMODE 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AUX_PWR XTAL_1.8V XTAL2 AD[16] VSS 3.3V 3.3V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AVSS 3.3V XTAL1 AD[14] H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 Datasheet 39 82541ER Gigabit Ethernet Controller Table 42. Signal Names in Pin Order (Sheet 5 of 6) (Continued) AD[15] C/BE#[1] 1.2V 1.2V VSS NC NC 1.2V 1.2V VSS JTAG_TMS JTAG_TRST# JTAG_TCK AD[11] AD[12] AD[13] C/BE#[0]# AD[5] VSS AD[1] NC FLSH_CE# EESK FLSH_SI SDP[3] JTAG_TDI JTAG_TDO VSS AD[10] AD[9] AD[7] AD[4] 3.3V AD[0] 3.3V FLSH_SCK L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 40 Datasheet 82541ER Gigabit Ethernet Controller Table 42. Signal Names in Pin Order (Sheet 6 of 6) (Continued) EEDO NC VSS SDP[2] SDP[0] NC 3.3V AD[8] AD[6] AD[3] AD[2] EECS VSS FLSH_SO EEDI CTRL12 3.3V SDP[1] NC a. Use a 1 K Ω resistor. N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Datasheet 41 82541ER Gigabit Ethernet Controller 5.4 A 1 NC Visual Pin Assignments B AD[22] C AD[21] D AD[18] E 3.3V F IRDY# G CLK H STOP# J PAR K AD[16] L AD[14] M AD[11] N VSS P NC 2 SERR# AD[23] M66EN AD[19] VSS FRAME# VIO INTA# PERR# VSS AD[15] AD[12] AD[10] 3.3V 3 3.3V VSS REQ# AD[20] AD[17] C/BE#[2] TRDY# DVSEL# GNT# 3.3V C/B3#[1] AD[13] AD[9] AD[8] 4 IDSEL AD[24] C/BE#[3] VSS VSS VSS PLL_1.2V PLL_1.2V EEMODE 3.3V 1.2V C/BE#[0] AD[7] AD[6] 5 AD[25] AD[26] NC VSS VSS VSS 1.2V 1.2V 1.2V 1.2V 1.2V AD[5] AD[4] AD[3] 6 NC AD[27] AD[28] VSS VSS VSS 1.2V 1.2V 1.2V 1.2V VSS VSS 3.3V AD[2] 7 3.3V VSS AD[29] VSS VSS VSS VSS 1.2V 1.2V 1.2V NC AD[1] AD[0] EECS 8 AD[30] AD[31] NC VSS VSS VSS VSS 1.2V 1.2V 1.2V NC NC 3.3V VSS 9 LAN_PWR_ GOOD RST# Pull Up To VCC NC VSS VSS VSS VSS 1.2V 1.2V 1.2V FLSH_CE# FLSH_SCK FLSH_SO 10 Pull Up To VCC Pull Up To VCC VSS NC VSS VSS VSS VSS 1.2V 1.2V 1.2V EESK EEDO EEDI 11 3.3V LINK100# ACTIVITY# ANALOG_ 1.8V ANALOG_ 1.2V AVSS AVSS ANALOG_ 1.2V 1.2V 1.2V VSS FLSH_SI NC CTRL12 12 LINK_LED# LINK1000# AVSS CLKR_ 1.8V ANALOG_ 1.2V NC ANALOG_ 1.8V NC AUX_PWR AVSS JTAG_TMS SDP[3] VSS 3.3V 13 TEST CTRL18 MDI[0]+ AVSS MDI[1]+ MDI[2]+ ANALOG_ 1.2V MDI[3]+ XTAL_1.8V 3.3V JTAG_TRST# JTAG_TDI SDP[2] SDP[1] 14 NC IEEE_TEST+ MDI[0]- IEEE_TEST- MDI[1]- MDI[2]- AVSS MDI[3]- XTAL2 XTAL1 JTAG_TCK JTAG_TDO SDP[0] NC Pins A10, B-10, and C9 - Use 1K ohm resistors. Figure 13. Visual Pin Assignments 42 Datasheet