M87C51FC

M87C51FC CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 32 KBYTES USER PROGRAMMABLE EPROM Military M87C51FC 3 5 MHz to 12 MHz VCC e 5V g 20% M87C51FC-1 3 5 MHz to 16 MHz VCC e 5V g 20% Y Y Y Y High Performance CHMOS EPROM Three 16-Bit Timer Counters Programmable Clock Out Programmable Counter Array with High Speed Output Compare Capture Pulse Width Modulator Watchdog Timer Capabilities Up Down Timer Counter Three Level Program Lock System 32K On-Chip EPROM 256 Bytes of On-Chip Data RAM Improved Quick Pulse Programming Algorithm Boolean Processor Available in 40-pin Cerdip and 44-pin LCC Packages Y Y Y 32 Programmable I O Lines 7 Interrupt Sources Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS -51 Fully Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode Available in Two Product Grades MIL-STD-883 b 55 C to a 125 C (TC) Military Temperature Only (MTO) b 55 C to a 125 C (TC) Y Y Y Y Y Y Y Y Y Y Y Y Y Y MEMORY ORGANIZATION PROGRAM MEMORY Up to 32 Kbytes of the program memory can reside in the on-chip EPROM In addition the device can address up to 64K of program memory external to the chip DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of external data memory The Intel M87C51FC is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology Being a member of the MCS-51 family the M87C51FC uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with the existing MCS-51 family of products The M87C51FC is an enhanced version of the 87C51 Its added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation High Speed I O and up down counting capabilities such as motor control It also has a more versatile serial channel that facilitates multiprocessor communications January 1994 Order Number 271114-004 M87C51FC 271114 – 1 Figure 1 M87C51FC Block Diagram 2 M87C51FC Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory In this application it uses strong internal pullups when emitting1’s and can source and sink several LS TTL inputs Port 0 also receives the code bytes during EPROM programming and outputs the code bytes during program verification External pullup resistors are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current (IIL on the data sheet) because of the internal pullups In addition Port 1 serves the functions of the following special features of the M87C51FC Port Pin 271114 – 2 PACKAGES Part 87C51FC Prefix D R Package Type 40-Pin CERDIP 44-Pin LCC Alternate Function T2 (External Count Input to Timer Counter 2) Clock-Out T2EX (Timer Counter 2 Capture Reload Trigger and Direction Control) ECI (External Count Input to the PCA) CEX0 (External I O for Compare Capture Module 0) CEX1 (External I O for Compare Capture Module 1) CEX2 (External I O for Compare Capture Module 2) CEX3 (External I O for Compare Capture Module 3) CEX4 (External I O for Compare Capture Module 4) P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 DIP 271114 – 3 LCC Figure 2 Pin Connections Port 1 receives the low-order address bytes during EPROM programming and verifying Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups The Port 2 output buffers can drive LS TTL inputs Port 2 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current (IIL on the data sheet) because of the internal pullups PIN DESCRIPTIONS VCC Supply voltage VSS Circuit ground Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1’s written to them float and in that state can be used as high-impedance inputs 3 M87C51FC Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR) In this application it uses strong internal pullups when emitting 1’s During accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Some Port 2 pins receive the high-order address bits during EPROM programming and program verification Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current (IIL on the data sheet) because of the pullups Port 3 also serves the functions of various special features of the MCS-51 Family as listed below Port Pin P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) PSEN Program Store Enable is the read strobe to external Program Memory When the M87C51FC is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data Memory EA VPP External Access enable EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory locations 0000H to 0FFFFH Note however that if either of the Program Lock bits are programmed EA will be internally latched on reset EA should be strapped to VCC for internal program executions This pin also receives the programming supply voltage (VPP) during EPROM programming XTAL1 Input to the inverting oscillator amplifier XTAL2 Output from the inverting oscillator amplifier OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of a inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 3 Either a quartz crystal or ceramic resonator may be used More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155 ‘‘Oscillators for Microcontrollers ’’ To drive the device from an external clock source XTAL1 should be driven while XTAL2 floats as shown in Figure 4 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data sheet must be observed An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF Some Port 3 pins receive the high-order address bits during EPROM programming and program verification RST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device An internal pulldown resistor permits a poweron reset with only a capacitor connected to VCC ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory This pin (ALE PROG) is also the program pulse input during EPROM programming for the M87C51FC In normal operation ALE is emitted at a constant rate of the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory Throughout the remainder of this data sheet ALE will refer to the signal coming out of the ALE PROG pin and the pin will be referred to as the ALE PROG pin 4 C1 C2 e 30 pF g 10 pF for Crystals e 10 pF for Ceramic Resonators 271114 – 4 Figure 3 Oscillator Connections M87C51FC With an external interrupt INT0 and INT1 must be enabled and configured as level-sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down 271114 – 5 Figure 4 External Clock Drive Configuration DESIGN CONSIDERATION  The window on the M87C51FC must be covered by an opaque label Otherwise the DC and AC characteristics may not be met and the device may functionally be impaired IDLE MODE The user’s software can invoke the Idle Mode When the microcontroller is in this mode power consumption is reduced The Special Function Registers and the onboard RAM retain their values during Idle but the processor stops executing instructions Idle Mode will be exited if the chip is reset or if an enabled interrupt occurs The PCA timer counter can optionally be left running or paused during Idle Mode  When the idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory POWER DOWN MODE To save even more power a Power Down mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated On the M87C51FC either a hardware reset or an external interrupt can cause an exit from Power Down Reset redefines all the SFRs but does not change the on-chip RAM An external interrupt allows both the SFRs and on-chip RAM to retain their values To properly terminate Power down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms) ONCE MODE The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates testing and debugging of systems using the M87C51FC without the M87C51FC having to be removed from the circuit The ONCE Mode is invoked by 1) Pull ALE low while the device is in reset and PSEN is high 2) Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins go into a float state and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the M87C51FC is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied Table 1 Status of the External Pins during Idle and Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data NOTE For more detailed information on the reduced power modes refer to Application Note AP-255 ‘‘Military CHMOS Designing with the M80C51BH ’’ 5 M87C51FC ABSOLUTE MAXIMUM RATINGS Case Temperature Under Bias Storage Temperature Voltage on EA VPP Pin to VSS Voltage on Any Other Pin to VSS IOL Per I O Pin b 55 C to a 125 C b 65 C to a 150 C 0V to a 13 0V b 0 5V to a 6 5V NOTICE This data sheet contains information on products in the sampling and initial production phases of development The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design 15 mA Power Dissipation 1 5W (based on PACKAGE heat transfer limitations not device power consumption) WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability ADVANCED INFORMATION OPERATING CONDITIONS MIL-STD-883 Symbol TC VCC fOSC CONTACT INTEL FOR DESIGN-IN INFORMATION Parameter Case Temperature (Instant On) Digital Supply Voltage Oscillator Frequency Min b 55 Max a 125 Units C V MHz 4 00 35 6 00 16 Military Temperature (MTO) Symbol TC VCC fOSC Parameter Case Temperature (Instant On) Digital Supply Voltage Oscillator Frequency Min b 55 Max a 125 Units C V MHz 4 00 35 6 00 16 DC CHARACTERISTICS Symbol VIL VIH VIH1 VOL Input Low Voltage (Over Specified Operating Conditions) Min b0 5 Parameter Max 0 2 VCC b 0 1 VCC a 0 5 VCC a 0 5 03 0 45 10 Unit V V V V V V V V V V V V Comments Input High Voltage (Except XTAL1 RST) Input High Voltage (XTAL1 RST) Output Low Voltage (Note 4) (Ports 1 2 and 3) 0 2 VCC a 0 9 0 7 VCC IOL e 100 mA (Note 1) IOL e 1 6 mA (Note 1) IOL e 3 5 mA (Note 1) IOL e 200 mA (Note 1) IOL e 3 2 mA (Note 1) IOL e 7 0 mA (Note 1) IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA VOL1 Output Low Voltage (Note 4) (Port 0 ALE PSEN) 03 0 45 10 VOH Output High Voltage (Ports 1 2 and 3 ALE PSEN) VCC b 0 3 VCC b 0 7 VCC b 1 5 6 M87C51FC DC CHARACTERISTICS Symbol VOH1 (Over Specified Operating Conditions) (Continued) Min VCC b 0 3 VCC b 0 7 VCC b 1 5 b 75 g 10 Parameter Output High Voltage (Port 0 in External Bus Mode) Max Unit V V V mA mA mA KX pF mA mA mA mA mA mA Comments IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 0 mA VIN e 0 45V 0 k VIN k VCC VIN e 2V IIL ILI ITL RRST CIO ICC Logical 0 Input Current (Ports 1 2 and 3) Input leakage Current (Port 0) Logical 1 to 0 Transition Current (Ports 1 2 and 3) RST Pulldown Resistor Pin Capacitance Power Supply Current Running at 12 MHz (Figure 6) Idle Mode at 12 MHz (Figure 7) Power Down Mode (Figure 8) Running at 16 MHz Idle Mode at 16 MHz Power Down Mode 16 MHz 40 b 750 225 10 40 10 100 45 15 130 1 MHz 25 C (Note 3) NOTES 1 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations In applications where capacitance loading exceeds 100 pFs the noise pulse on the ALE signal may exceed 0 8V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch with a Schmitt Trigger Strobe input 2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0 9 VCC specification when the address lines are stabilizing 3 See Figures 6–9 for load circuits Minimum VCC for Power Down is 2V 4 Under steady state (non-transient) conditions IOL must be externally limited as follows Maximum IOL per port pin 10mA Maximum IOL per 8-bit port Port 0 26 mA Ports 1 2 and 3 15 mA Maximum total IOL for all output pins 71 mA If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 271114 – 7 271114 – 6 ICC Max at other frequencies is given by Active Mode ICC Max e (Osc Freq c 3) a 4 Idle Mode ICC Max e (Osc Freq c 0 5) a 4 Where Osc Freq is in MHz ICC is in mA All other pins disconnected TCLCH e TCHCL e 5 ns Figure 6 ICC Load Circuits Active Mode Figure 5 ICC vs Frequency 7 M87C51FC 271114 – 8 All other pins disconnected TCLCH e TCHCL e 5 ns All other pins disconnected 271114 – 9 Figure 7 ICC Load Circuit Idle Mode Figure 8 ICC Load Circuit Power Down Mode VCC e 2 0V to 5 5V 271114 – 10 Figure 9 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters The first character is always a ‘T’ (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input Data H Logic level HIGH I Instruction (program memory contents) L Logic level LOW or ALE P PSEN Q Output Data R RD signal T Time V Valid W WR signal X No longer a valid logic level Z Float For example TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low 8 M87C51FC AC CHARACTERISTICS (Over Specified Operating Conditions Load Capacitance for Port 0 ALE PROG and PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF) ADVANCED INFORMATION CONTACT INTEL FOR DESIGN-IN INFORMATION EXTERNAL PROGRAM MEMORY CHARACTERISTICS Symbol 1 TCLCL TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TWHQX TQVWH TRLAZ TWHLH Parameter Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float Float After PSEN Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address Valid to WR Low Data Valid before WR Data Hold after WR Data Valid to WR High RD Low to Address Float RD or WR High to ALE High 43 200 203 33 33 433 0 123 23 0 107 517 585 300 138 120 13 13 288 0 103 TCLCL b 40 400 400 252 0 65 350 398 238 3TCLCL b 50 4TCLCL b 130 TCLCL b 50 TCLCL b 50 7TCLCL b 150 0 TCLCL a 40 0 59 312 10 275 275 147 5 0 2TCLCL b 60 8TCLCL b 150 9TCLCL b 165 3TCLCL a 50 53 205 145 0 38 208 10 6TCLCL b 100 6TCLCL b 100 5TCLCL b 165 127 43 53 234 33 143 83 0 TCLCL b 25 5TCLCL b 105 10 85 23 33 150 TCLCL b 30 3TCLCL b 45 3TCLCL b 105 12 MHz Oscillator Min Max 16 MHz Oscillator Min Max Min 35 2TCLCL b 40 TCLCL b 40 TCLCL b 30 4TCLCL b 100 Variable Oscillator Max 16 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units 9 M87C51FC EXTERNAL PROGRAM MEMORY READ CYCLE 271114 – 11 EXTERNAL DATA MEMORY READ CYCLE 271114 – 12 EXTERNAL DATA MEMORY WRITE CYCLE 271114 – 13 10 M87C51FC SERIAL PORT TIMING - SHIFT REGISTER MODE Test Conditions Symbol TXLXL TQVXH TXHQX TXHDX TXHDV TC e b 55 C to a 125 C VCC e 5V g 10% VSS e 0V Load Capacitance e 80 pF 12 MHz 16 MHz Variable Oscillator Oscillator Oscillator Parameter Units Min Max Min Max Min Max Serial Port Clock 1 0 75 12TCLCL ms Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 700 50 0 700 492 8 0 492 10TCLCL b 133 2TCLCL b 117 0 10TCLCL b 133 ns ns ns ns SHIFT REGISTER MODE TIMING WAVEFORMS 271114 – 14 EXTERNAL CLOCK DRIVE Symbol 1 TCLCL Parameter Oscillator Frequency M87C51FC M87C51FC-16 High Time Low Time Rise Time Fall Time Min 35 35 20 20 Max 12 16 Units MHz ns ns 20 20 ns ns TCHCX TCLCX TCLCH TCHCL EXTERNAL CLOCK DRIVE WAVEFORM 271114 – 15 11 M87C51FC AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 271114 – 16 AC Inputs during testing are driven at VCC b 0 5V for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0’’ Timing measurements are made at VIH min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’ 271114 – 17 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH VOL level occurs IOL IOH t g 20 mA Table 2 EPROM Programming Modes Mode Program Code Data Verify Code Data Program Encryption Array Address 0–3FH Program Lock Bits Bit 1 Bit 2 Bit 3 Read Signature Byte RST H H H H H H H PSEN L L L L L L L H H ALE PROG EA VPP 12 75V H 12 75V 12 75V 12 75V 12 75V H P2 6 L L L H H H L P2 7 H L H H H L L P3 3 H L H H H H L P3 6 H H L H L H L P3 7 H H H H L L L DEFINITION OF TERMS ADDRESS LINES P1 0–P1 7 P2 0–P2 5 P3 4 – P3 5 respectively for A0–A15 DATA LINES P0 0–P0 7 for D0–D7 CONTROL SIGNALS RST PSEN P2 6 P2 7 P3 3 P3 6 P3 7 PROGRAM SIGNALS ALE PROG EA VPP PROGRAMMING THE EPROM The part must be running with a 4 MHz to 6 MHz oscillator The address of an EPROM location to be programmed is applied to address lines while the code byte to be programmed in that location is applied to data lines Control and program signals must be held at the levels indicated in Table 2 Normally EA VPP is held at logic high until just before ALE PROG is to be pulsed The EA VPP is raised to VPP ALE PROG is pulsed low and then EA VPP is returned to a high (also refer to timing diagrams) NOTE Exceeding the VPP maximum for any amount of time could damage the device permanently The VPP source must be well regulated and free of glitches 12 M87C51FC See Table 2 for proper input on these pins 271114 – 18 Figure 10 Programming the EPROM PROGRAMMING ALGORITHM Refer to Table 2 and Figures 10 and 11 for address data and control signals set up To program the M87C51FC the following sequence must be exercised 1 Input the valid address on the address lines 2 Input the appropriate data byte on the data lines 3 Activate the correct combination of control signals 4 Raise EA VPP from VCC to 12 75V g 0 25V 5 Pulse ALE PROG 5 times for the EPROM array and 25 times for the encryption table and the lock bits Repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached PROGRAM VERIFY Program verify may be done after each byte that is programmed or after a block of bytes that is programmed In either case a complete verify of the entire array that has been programmed will ensure a reliable programming of the M87C51FC The lock bits cannot be directly verified Verification of the lock bits is done by observing that their features are enabled Refer to the EPROM Program Lock section in this data sheet 5 Pulses 271114 – 19 Figure 11 Programming Signal’s Waveforms 13 M87C51FC EPROM Program Lock The M87C51FC has a 3-bit program lock system and a 64-byte encryption array which are designed to protect the onboard program and data against software piracy Reading the Signature Bytes The M87C51FC has 3 signature bytes in locations 30H 31H and 60H To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 2 for Read Signature Byte Location 30H e 89H 31H e 58H 60H e FCH Encryption Array Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1’s) Every time that a byte is addressed during a verify 5 address lines are used to select a byte of the Encryption Array This byte is then exclusive-NOR’ed (XNOR) with the code byte creating an Encryption Verify byte The algorithm with the array in the unprogrammed state (all 1’s) will return the code in it’s original unmodified form For programming the Encryption Array refer to Table 2 (Programming the EPROM) Erasure Characteristics Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4 000 Angstroms Since sunlight and fluorescent lighting have wavelengths in this range exposure to these light sources over an extended time (about 1 week in sunlight or 3 years in roomlevel fluorescent lighting) could cause inadvertent erasure If an application subjects the device to this type of exposure it is suggested that an opaque label be placed over the window The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec cm2 Exposing the EPROM to an ultraviolet lamp of 12 000 mW cm2 rating for 30 minutes at a distance of about 1 inch should be sufficient Erasure leaves all the EPROM Cells in a 1’s state Program Lock Bits The M87C51FC has 3 programmable lock bits that when programmed according to Table 3 will provide different levels of protection for the on-chip code and data Erasing the EPROM also erases the encryption array and the program lock bits returning the part to full functionality Table 3 Program Lock Bits and the Features Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U No Program Lock features enabled (Code verify will still be encrypted by the Encryption Array if programmed ) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on Reset and further programming of the EPROM is disabled Same as 2 also verify is disabled Same as 3 also external execution is disabled Protection Type 3 4 P P P P U P Any other combination of the lock bits is not defined 14 M87C51FC EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (TA e 21 C to 27 C VCC e 5V g 10% VSS e 0V) ADVANCED INFORMATION Symbol VPP IPP 1 TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL CONTACT INTEL FOR DESIGN-IN INFORMATION Min 12 5 Max 13 0 75 4 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 10 10 90 110 48TCLCL 48TCLCL 0 10 48TCLCL ms ms ms ms 6 Units V mA MHz Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low Data Hold after PROG (Enable) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float after ENABLE PROG High to PROG Low EPROM PROGRAMMING AND VERIFICATION WAVEFORMS 271114 – 20 15