N87C198

8XC198 COMMERCIAL EXPRESS CHMOS MICROCONTROLLER 8 Kbytes of OTPROM Y Y Y Y Y Y Y Y Y 8 Kbytes of On-Chip OTPROM or ROM 232 Byte Register File Register-to-Register Architecture 28 Interrupt Sources 16 Vectors 1 75 ms 16 x 16 Multiply (16 MHz) 3 0 ms 32 16 Divide (16 MHz) Powerdown and Idle Modes 16-Bit Watchdog Timer 8-Bit External Bus Y Y Y Y Y Y Y Y Y 16 MHz Standard Full Duplex Serial Port High Speed I O Subsystem 16-Bit Timer 16-Bit Counter Pulse-Width-Modulated Output Four 16-Bit Software Timers 10-Bit A D Converter with Sample Hold Extended Temperature Available The 8XC198 family offers low-cost entry into Intel’s powerful MCS -96 16-bit microcontroller architecture Intel’s CHMOS process provides a high performance processor along with low power consumption To further reduce power requirements the processor can be placed into Idle or Powerdown Mode The 8XC198 is the 8-bit bus version of the 8XC196KB The prefixes mean 80 (ROMless) 83 (ROM) 87 (OTP) One Time Programmable The ROM and OTP are available in 8 Kbytes Bit byte word and some 32-bit operations are available on the 8XC198 With a 16 MHz oscillator a 16-bit addition takes 0 50 ms and the instruction times average 0 37 ms to 1 1 ms in typical applications Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or start an A D conversion Events can be based on the timer or counter Also provided on-chip are an A D converter serial port watchdog timer and a pulse-width-modulated output signal With the commercial (standard) temperature option operational characteristics are guaranteed over the temperature range of 0 C to a 70 C Wth the extended temperature range option operational characteristics are guaranteed over the temperature range of b 40 C to a 85 C MCS -96 is a registered trademark of Intel Corporation Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 October 1992 Order Number 272034-003 8XC198 272034 – 1 Figure 1 87C198 Block Diagram 0FFFFH EXTERNAL MEMORY OR I O 4000H INTERNAL ROM EPROM OR EXTERNAL MEMORY 2080H RESERVED 2040H UPPER 8 INTERRUPT VECTORS 2030H ROM OTP SECURITY KEY 2020H RESERVED 2019H CHIP CONFIGURATION BYTE 2018H RESERVED 2014H LOWER 8 INTERRUPT VECTORS PLUS 2 SPECIAL INTERRUPTS 2000H PORT 3 AND PORT 4 1FFEH EXTERNAL MEMORY OR I O 0100H INTERNAL DATA MEMORY - REGISTER FILE (STACK POINTER RAM AND SFRS) EXTERNAL PROGRAM CODE MEMORY 272034 – 7 Figure 3 Chip Configuration (2018H) 0000H Figure 2 Memory Map WARNING Reserved memory locations must not be written or read The contents and or function of these locations may change with future revisions of the device Therefore a program that relies on one or more of these locations may not function properly 2 8XC198 PACKAGING The 8XC198 is available in a 52-pin PLCC package and an 80-pin QFP package Contact your local sales office to determine the exact ordering code for the part desired Package Designators N e 52-pin PLCC S e 80-pin QFP Thermal Characteristics Package Type PLCC QFP ija 40 C W 70 C W 4C W ijc All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operating conditions and application See the Intel Packaging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology 272034 – 2 Figure 4 52-Pin PLCC Package NOTE The above pinout diagram applies to the OTP (87C198) device The OTP device uses all of the programming pins shown above The ROM (83C198) device only uses programming pins AINC PALE PMODE n and PROG The ROMless (80C198) doesn’t use any of the programming pins 3 8XC198 272034 – 4 NOTE N C means No Connect (do not connect these pins) Figure 5 80-Pin QFP Package NOTE The above pinout diagram applies to the OTP (87C198) device The OTP device uses all of the programming pins shown above The ROM (83C198) device only uses programming pins AINC PALE PMODE n and PROG The ROMless (80C198) doesn’t use any of the programming pins 4 8XC198 PIN DESCRIPTIONS Symbol VCC VSS VREF Main supply voltage (5V) The PLCC package has 5 VSS pins and the QFP package has 12 VSS pins All must be connected to digital ground Reference voltage for the A D converter (5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference ground for the A D converter Must be held at nominally the same potential as VSS Programming Voltage Also timing pin for the return from powerdown circuit Input of the oscillator inverter and of the internal clock generator Output of the oscillator inverter Reset input to and open-drain output from the chip Input low for at least 4 state times to reset the chip The subsequent low-to-high transition commences the 10-state Reset Sequence Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is activated only during external memory accesses and output low for a data fetch Input for memory select (External Access) EA equal to a TTL-high causes memory accesses to locations 2000H through 3FFFH to be directed to on-chip ROM EPROM EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during external memory accesses Read signal output to external memory RD is activated only during external memory reads Write output to external memory WR will go low for every external write Ready input to lengthen external memory cycles When the external memory is not being used READY has no effect Internal control of the number of wait states inserted into a bus cycle held not ready is available through configuration of CCR Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and HSI 3 Two of them (HSI 2 and HSI 3) are shared with the HSO Unit Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSO 3 HSO 4 and HSO 5 Two of them (HSO 4 and HSO 5) are shared with the HSI Unit 4-bit high impedance input-only port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter These pins set the Programming Mode on the EPROM device Name and Function ANGND VPP XTAL1 XTAL2 RESET INST EA ALE ADV RD WR READY HSI HSO Port 0 5 8XC198 PIN DESCRIPTIONS (Continued) Symbol Port 2 Ports 3 and 4 Name and Function Multi-functional port All of its pins are shared with other functions in the 80C198 8-bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups Available as I O only on the ROM and EPROM devices The TxD pin is used for serial port transmission in Modes 1 2 and 3 In mode 0 the pin is used as the serial clock output Serial Port Receive pin used for serial port reception In mode 0 the pin functions as input or output data A positive transition on the EXTINT pin will generate an external interrupt The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input A rising edge on the T2RST pin will reset Timer2 The PWM output Programming Mode Select Determines the EPROM programming algorithm that is performed PMODE is sampled after a chip reset and should be static while the part is operating Slave ID Number Used to assign each slave a pin of Port 3 or 4 to use for passing programming verification acknowledgement Programming ALE Input Accepted by the 87C196KB when it is in Slave Programming Mode Used to indicate that Ports 3 and 4 contain a command address Programming Falling edge indicates valid data on PBUS and the beginning of programming Rising edge indicates end of programming Program Valid This signal indicates the success or failure of programming in the Auto Programming Mode A zero indicates successful programming Program Verification Used in Slave Programming and Auto CLB Programming Modes Signal is low after rising edge of PROG if the programming was not successful Auto Increment Active low signal indicates that the auto increment mode is enabled Auto Increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write Address Command Data Bus Used to pass commands addresses and data to and from slave mode 87C196KBs Used by chips in Auto Programming Mode to pass command addresses and data to slaves Also used in the Auto Programming Mode as a regular system bus to access external memory Should have pullups to VCC (15 kX) TxD RxD EXTINT T2CLK T2RST PWM PMODE SID PALE PROG PVAL PVER AINC PORTS 3 and 4 (when programming) 6 8XC198 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Ambient Temperature under Bias Storage Temperature Voltage on VPP or EA to VSS or ANGND Voltage on Any Other Pin to VSS Power Dissipation(1) b 55 C to a 125 C b 65 C to a 150 C b 0 3V to a 13 0V b 0 5V to a 7 0V NOTICE This data sheet contains preliminary information on new products in production It is valid for the devices indicated in the revision history The specifications are subject to change without notice WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability 1 5W NOTE 1 Power dissipation is based on package heat transfer limitations not device power consumption OPERATING CONDITIONS (All characteristics in this data sheet apply to these operating conditions unless otherwise noted ) Symbol TA VCC VREF FOSC Description Ambient Temperature Under Bias Digital Supply Voltage Analog Supply Voltage Oscillator Frequency 16 MHz Min 0 4 50 4 50 35 Max a 70 Units C V V MHz 5 50 5 50 16 NOTE ANGND and VSS should be nominally at the same potential DC CHARACTERISTICS Symbol VIL VIH VIH1 VIH2 VOL Description Input Low Voltage Input High Voltage (1) Input High Voltage on XTAL1 Input High Voltage on RESET Output Low Voltage Min b0 5 Max 08 VCC a 0 5 VCC a 0 5 03 0 45 15 Units V V V V V V V V V V Test Conditions 0 2 VCC a 0 9 VCC a 0 5 0 7 VCC 26 IOL e 200 mA IOL e 32 mA IOL e 7 mA IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 mA 0 k VIN k VCC b 0 3V 0 k VIN k VREF VIN e 0 45 V VOH Output High Voltage (Standard Outputs) Input Leakage Current (Std Inputs) Input Leakage Current (Port 0) Logical 0 Input Current in Reset (ALE RD INST) Hysteresis on RESET Pin VCC b 0 3 VCC b 0 7 VCC b 1 5 g 10 ILI ILI1 IIL1 Hyst mA mA mA mV a3 b6 300 NOTE 1 All pins except RESET and XTAL1 7 8XC198 DC CHARACTERISTICS (Continued) Symbol ICC IREF IIDLE ICC1 IPD RRST CS Description Active Mode Current in Reset A D Converter Reference Current Idle Mode Current Active Mode Current Powerdown Mode Current Reset Pullup Resistor Pin Capacitance (Any Pin to VSS) 6K Min Typ(6) 50 2 10 15 5 Max 60 5 25 25 30 50K 10 Units mA mA mA mA mA X pF FTEST e 1 0 MHz XTAL1 e 3 5 MHz VCC e VPP e VREF e 5 5V Test Conditions XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V NOTES (Notes apply to all specifications) 1 Standard Outputs include AD0–15 RD WR ALE INST HSO pins PWM P2 5 RESET Ports 3 and 4 TXD P2 0 and RXD (in serial mode 0) The VOH specification is not valid for RESET Ports 3 and 4 are open-drain outputs 2 Standard Inputs include HSI pins EA READY RXD P2 1 EXTINT P2 2 T2CLK P2 3 and T2RST P2 4 3 Maximum current per pin must be externally limited to the following values if VOL is held above 0 45V or VOH is held below VCC b 0 7V IOL on Output pins 10 mA IOH on Standard Output pins 10 mA 4 Maximum current per bus pin (data and control) during normal operation is g 3 2 mA 5 During normal (non-transient) conditions the following total current limits apply IOL 29 mA IOH 26 mA HSO P2 0 RXD RESET IOL 13 mA IOH 11 mA P2 5 WR IOH 52 mA AD0 – AD15 IOL 52 mA IOL 13 mA IOH 13 mA RD ALE INST 6 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature and VREF e VCC e 5V ICC Max e 3 88 c FREQ a 8 43 IIDLE Max e 1 65 c FREQ a 2 2 272034 – 22 Figure 8 ICC and IIDLE vs Frequency 8 8XC198 AC CHARACTERISTICS Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 12 16 MHz The system must meet these specifications to work with the 87C198 Symbol TAVYV TYLYH TLLYX TAVDV TRLDV TRHDZ TRXDX Description Address Valid to Ready Setup Non READY Time READY Hold after ALE Low Address Valid to Input Data Valid RD Active to Input Data Valid End of RD to Input Data Float Data Hold after RD Inactive 0 Min Max 2 TOSC b 75 No upper limit TOSC b 15 2 TOSC b 40 3 TOSC b 55 TOSC b 23 TOSC b 20 Units ns ns ns ns ns ns ns (Note 1) (Note 2) (Note 2) Notes NOTES 1 If max is exceeded additional wait states will occur 2 When using wait states add 2 TOSC c n where n e number of wait states 9 8XC198 AC CHARACTERISTICS Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 12 16 MHz The 87C198 will meet these specifications Symbol FXTAL FXTAL TOSC TOSC TLHLH TLHLL TAVLL TLLAX TLLRL TRLRH TRHLH TRLAZ TLLWL TQVWH TWLWH TWHQX TWHLH TWHBX TLLBX TRHBX TWHAX TRHAX Description Frequency on XTAL1 12 MHz Frequency on XTAL1 16 MHz 1 FXTAL 12 MHz 1 FXTAL 16 MHz ALE Cycle Time ALE High Period Address Setup to ALE Falling Edge Address Hold after ALE Falling Edge ALE Falling Edge to RD Falling Edge RD Low Period RD Rising Edge to ALE Rising Edge RD Low to Address Float ALE Falling Edge to WR Falling Edge Data Stable to WR Rising Edge WR Low Period Data Hold after WR Rising Edge WR Rising Edge to ALE Rising Edge INST Hold after WR Rising Edge INST Hold after ALE Rising Edge INST Hold after RD Rising Edge AD8–15 Hold after WR Rising Edge AD8–15 Hold after RD Rising Edge TOSC b 10 TOSC b 23 TOSC b 15 TOSC b 15 TOSC b 15 TOSC b 15 TOSC b 10 TOSC b 10 TOSC b 30 TOSC b 25 TOSC a 10 TOSC a 5 Min 35 35 83 3 62 5 4 TOSC TOSC b 10 TOSC b 20 TOSC b 40 TOSC b 35 TOSC b 5 TOSC TOSC a 25 TOSC a 25 5 TOSC a 10 Max 12 16 286 286 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 3) (Note 3) (Note 3) (Note 2) (Note 3) Notes (Note 1) (Note 1) NOTES 1 Testing performed at 3 5 MHz However the part is static by design and will typically operate below 1 Hz 2 Assuming back-to-back bus cycles 3 When using wait states add 2 TOSC c n where n e number of wait states 10 8XC198 System Bus Timings 272034 – 23 11 8XC198 READY Timings (One Wait State) 272034 – 24 EXTERNAL CLOCK DRIVE Symbol 1 TXLXL 1 TXLXL TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency 12 MHz Oscillator Frequency 16 MHz Oscillator Period 12 MHz Oscillator Period 16 MHz High Time Low Time Rise Time Fall Time Min 35 35 83 3 62 5 21 25 21 25 10 10 Max 12 0 16 0 286 286 Units MHz MHz ns ns ns ns ns ns EXTERNAL CLOCK DRIVE WAVEFORMS 272034 – 25 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF 12 8XC198 EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS 272034 – 32 272034 – 33 NOTE Keep oscillator components close to chip and use short direct traces to XTAL1 XTAL2 and VSS When using crystals C1 e 20 pF C2 e 20 pF When using ceramic resonators consult manufacturer for recommended capacitor values NOTE Required if open collector TTL driver used Not needed if CMOS driver is used AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 272034 – 26 AC Testing inputs are driven at 2 4V for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0’’ Timing measurements are made at 2 0V for a Logic ‘‘1’’ and 0 8V for a Logic ‘‘0’’ 272034 – 27 For Timing Purposes a Port Pin is no Longer Floating when a 200 mV change from Load Voltage Occurs and Begins to Float when a 200 mV change from the Loaded VOH VOL Level occurs IOL IOH e g 15 mA EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points Conditions Signals H L V X Z - High - Low - Valid - No Longer Valid - Floating A D L Q R W X Y - Address - DATA IN - ALE ADV - DATA OUT - RD - WR - XTAL1 - READY 13 8XC198 State times are calculated as follows state time e 2 fXTAL1 10-BIT AID CHARACTERISTICS At a clock speed of 6 MHz or less the clock prescaler should be disabled This is accomplished by setting IOC2 4 e 1 At higher frequencies (greater than 6 MHz) the clock prescaler should be turned on (IOC2 4 e 0) to allow the comparator to settle The table below shows two different clock speeds and their corresponding A D conversion and sample times The converter is ratiometric so the absolute accuracy is directly dependent on the accuracy and stability of VREF VREF must be close to VCC since it supplies both the resistor ladder and the digital section of the converter See the MCS-96 A D Converter Quick Reference for definition of A D terms Example Sample and Conversion Times AID Clock Prescaler IOC2 4 e 0 IOC2 4 e 1 Clock Speed (MHz) 16 6 Sample Time (States) 15 8 Sample Time at Clock Speed (ms) 1 875 2 667 Conversion Time (States) 156 5 89 5 Conversion Time at Clock Speed (ms) 19 6 29 8 x ON x OFF A D CONVERTER SPECIFICATIONS Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Error Differential Non-Linearity Error Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance DC Input Leakage Sample Time Prescaler On Prescaler Off Sampling Capacitor 15 8 3 b 60 b 60 g0 1 g 0 25 Typical(1) Minimum 1024 10 0 Maximum 1024 10 g3 Units Levels Bits LSBs LSBs LSBs Notes 0 25 g 0 50 b 0 25 g 0 50 1 5 g2 5 0 l b1 g3 LSBs LSBs LSBs LSBs LSB C LSB C LSB C a2 g1 0 0 009 0 009 0 009 b 60 dB dB dB 23 2 2 4 750 0 1 2K 30 X mA States States pF NOTES An ‘‘LSB’’ as used here has a value of approximately 5 mV 1 Typical values are expected for most devices at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer Break-Before-Make Guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 14 8XC198 EPROM SPECIFICATIONS EPROM PROGRAMMING OPERATING CONDITIONS Symbol TA VCC VPD VREF(1) VEA VPP VSS ANGND(3) FOSC Parameter Ambient Temperature during Programming Supply Voltages during Programming Programming Mode Supply Voltage EPROM Programming Supply Voltage Digital and Analog Ground Oscillator Frequency 16 MHz Min 20 45 12 50 12 50 0 60 Max 30 55 13 0 13 0 0 16 0 Units C V V(2) V(2) V MHz NOTES 1 VCC VPD and VREF should nominally be at the same voltage during programming 2 VEA and VPP must never exceed the maximum voltage for any amount of time or the device may be damaged 3 VSS and ANGND should nominally be at the same voltage (0V) during programming AC EPROM PROGRAMMING CHARACTERISTICS Symbol TSHLL TLLLH TAVLL TLLAX TLLVL TPLDV TPHDX TDVPL TPLDX TPLPH TPHLL TLHPL TPHPL TPHIL TILIH TILVH TILPL TPHVL Description Reset High to First PALE Low PALE Pulse Width Address Setup Time Address Hold Time PALE Low to PVER Low PROG Low to Word Dump Valid Word Dump Data Hold Data Setup Time Data Hold Time PROG Pulse Width PROG High to Next PALE Low PALE High to PROG Low PROG High to Next PROG Low PROG High to AINC Low AINC Pulse Width PVER Hold after AINC Low AINC Low to PROG Low PROG High to PVER Low 0 50 40 120 220 120 0 40 50 170 90 Min 1100 40 0 50 60 50 50 Max Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC DC EPROM PROGRAMMING CHARACTERISTICS Symbol IPP Description VPP Supply Current (When Programming) Min Max 100 Units mA 15 8XC198 EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 272034 – 28 SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT 272034 – 29 16 8XC198 SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT 272034 – 30 17 8XC198 AC CHARACTERISTICS SERIAL PORT TIMING Symbol TXLXL TXLXH TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ SERIAL PORT SHIFT REGISTER MODE SHIFT REGISTER MODE Parameter Min 6 TOSC 4 TOSC b 50 4 TOSC 2 TOSC b 50 2 TOSC b 50 2 TOSC b 50 2 TOSC a 50 TOSC a 50 0 2 TOSC 2 TOSC a 50 4 TOSC a 50 Max Units ns ns ns ns ns ns ns ns ns ns Serial Port Clock Period (BRR t 8002H) Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) Serial Port Clock Period (BRR e 8001H) Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float WAVEFORM SERIAL PORT SHIFT REGISTER MODE SERIAL PORT WAVEFORM SHIFT REGISTER MODE 272034 – 31 18 8XC198 FUNCTIONAL DEVIATIONS Devices marked with an ‘‘E’’ ‘‘F’’ or ‘‘G’’ have the following errata 1 HIGH SPEED INPUTS The High Speed Input (HSI) has three deviations from the specifications NOTE ‘‘Events’’ are defined as one or more pin transitions ‘‘Entries’’ are defined as the recording of one or more events A The resolution is nine states instead of eight states Events occurring on the same pin more frequently than once every nine states may be lost B A mismatch between the nine state HSI resolution and the eight state hardware timer causes one time-tag value to be skipped every nine timer counts Events may receive a time-tag one count later than expected C If the FIFO and Holding Register are empty the first event will transfer into the Holding Register leaving the FIFO empty again The next event that occurs will be the first event loaded into the empty FIFO If the first two events into an empty FIFO (not counting the Holding Register) occur coincident with each other both are recorded as one entry with one time-tag If the second event occurs within 9 states after the first the events will be entered separately with time-tags at least one count apart If the second event enters the FIFO coincident with the ‘‘skipped’’ time-tag situation (see B above) the time-tags will be at least two counts apart 2 CMPL with R0 Using CMPL with register 0 can set incorrect flags Don’t use register 0 with the compare long instruction Use another long word register and set it equal to zero See Techbit MC0692 REVISION HISTORY This data sheet (272034-003) is valid for devices marked with an ‘‘E’’ ‘‘F’’ or ‘‘G’’ at the end of the top side tracking number Data sheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices The following differences exist between this data sheet and the previous version (-002) 1 This data sheet added the ROMless and ROM devices 80C198 and 83C198 respectively 2 The description of the A D converter prescalar bit was improved 19