PXA210

Intel® PXA250 and PXA210 Applications Processors Electrical, Mechanical, and Thermal Specification Datasheet Product Features High Performance Processor — Intel® XScale™ Microarchitecture — 32 KB Instruction Cache — 32 KB Data Cache — 2 KB “mini” Data Cache — Extensive Data Buffering Intel® Media Processing Technology — Enhanced 16-bit Multiply — 40-bit Accumulator Flexible Clocking — CPU clock from 66 to 300 MHz — Flexible memory clock ratios — Frequency change modes Rich Serial Peripheral Set — AC97 Audio Port — I2S Audio Port — USB Client Controller — High Speed UART — Second UART with flow control — FIR and SIR infrared comm ports Low Power — Less than 500 mW Typical Internal Dissipation — Supply Voltage may be Reduced to 0.85 V — Low Power/Sleep Modes High Performance Memory Controller — Four Banks of SDRAM - up to 100 MHz — Five Static Chip Selects — Support for PCMCIA or Compact Flash — Companion Chip interface Additional Peripherals for system connectivity — Multimedia Card Controller (MMC) — SSP Controller — I2C Controller — Two Pulse Width Modulators (PWMs) — All peripheral pins double as GPIOs. Hardware debug features Hardware Performance Monitoring features Order Number: 278524-001 February, 2002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® PXA250 and PXA210 Applications Processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2002 *Other names and brands may be claimed as the property of others. 2 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Contents 1.0 2.0 3.0 About this Document .............................................................................................7 Functional Overview .............................................................................................. 7 Package Information .............................................................................................. 8 3.1 Package Introduction..................................................................................... 8 3.1.1 Functional Signal Definitions ............................................................ 9 3.1.1.1 PXA250 Signal Pin Descriptions ...................................... 9 3.1.1.2 PXA210 Signal Pin Descriptions .................................... 19 Package Power Ratings ..............................................................................29 Absolute Maximum Ratings.........................................................................29 Operating Conditions...................................................................................30 Targeted DC Specifications.........................................................................31 Targeted AC Specifications.........................................................................32 Oscillator Electrical Specifications...............................................................33 4.5.1 32.768 kHz Oscillator Specifications ..............................................33 4.5.2 3.6864 MHz Oscillator Specifications .............................................34 Reset and Power AC Timing Specifications ................................................35 4.6.1 Power On Timing............................................................................35 4.6.2 Hardware Reset Timing..................................................................36 4.6.3 Watchdog Reset Timing ................................................................. 37 4.6.4 GPIO Reset Timing ........................................................................37 4.6.5 Sleep Mode Timing ........................................................................38 Memory Bus and PCMCIA AC Specifications ............................................. 39 Peripheral Module AC Specifications .......................................................... 42 4.8.1 LCD Module AC Timing..................................................................43 4.8.2 SSP Module AC Timing..................................................................43 4.8.3 Boundary Scan Test Signal Timings .............................................. 44 AC Test Conditions .....................................................................................45 3.2 4.0 4.1 4.2 4.3 4.4 4.5 Electrical Specifications ......................................................................................29 4.6 4.7 4.8 4.9 Datasheet 3 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Figures 1 2 3 4 5 6 7 8 9 10 Applications Processor Block Diagram ................................................................. 8 PXA250 Applications Processor ......................................................................... 16 PXA210 Applications Processor ......................................................................... 26 Power-On Reset Timing ...................................................................................... 36 Hardware Reset Timing ...................................................................................... 37 GPIO Reset Timing ............................................................................................. 37 Sleep Mode Timing ............................................................................................. 38 LCD AC Timing Definitions ................................................................................. 43 SSP AC Timing Definitions ................................................................................. 44 AC Test Load ...................................................................................................... 45 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Related Documentation......................................................................................... 7 Pin and Signal Descriptions for the PXA250 Applications Processor ................... 9 PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order.............. 17 Pin and Signal Descriptions for the PXA210 Applications Processor ................. 19 PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order ............ 27 JA and Maximum Power Ratings........................................................................ 29 Absolute Maximum Ratings ................................................................................ 29 Voltage, Temperature, and Frequency Electrical Specifications......................... 30 Standard Input, Output, and I/O Pin DC Operating Conditions........................... 31 Standard Input, Output, and I/O Pin AC Operating Conditions ........................... 32 32.768 kHz Oscillator Specifications ................................................................... 33 3.6864 MHz Oscillator Specifications.................................................................. 34 Power-On Timing Specifications ......................................................................... 36 Hardware Reset Timing Specifications ............................................................... 37 GPIO Reset Timing Specifications...................................................................... 38 Sleep Mode Timing Specifications ...................................................................... 39 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications.................... 39 Variable Latency I/O Interface AC Specifications ............................................... 40 Card Interface (PCMCIA or Compact Flash) AC Specifications ......................... 41 Synchronous Memory Interface AC Specifications1............................................ 42 LCD AC Timing Specifications ............................................................................ 43 SSP AC Timing Specifications ............................................................................ 44 Boundary Scan Test Signal Timing..................................................................... 44 4 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Revision History Date 7/6/01 2/8/02 Revision 0.5 -001 First Release First public release of the EMTS Description Datasheet 5 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification 6 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 1.0 About this Document This is the Electrical, Mechanical, and Thermal Specification datasheet for the Intel® PXA250 and PXA210 applications processors. This datasheet contains a functional overview, mechanical data, package signal locations, targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the Intel® PXA250 and PXA210 Applications Processors Developer's Manual. Refer to Table 1, “Related Documentation” for a list of documents that support the PXA250 and PXA210 applications processors. Table 1. Related Documentation Document Title Intel® PXA250 and PXA210 Applications Processors Developer's Manual Intel® XScaleTM Microarchitecture for the PXA250 and PXA210 Applications Processors Developer's Manual Intel® PXA250 and PXA210 Applications Processors Design Guide Order / Contact Intel Order # 278522 Intel Order # 278525 Intel Order # 278523 2.0 Functional Overview The PXA250 and PXA210 applications processors provide high integration, high performance and low power consumption for portable handheld and handset devices. These applications processors incorporate Intel’s XScaleTM Microarchitecture based on the ARM* V5TE architecture. Refer to the Intel® XScaleTM Microarchitecture for the Intel® PXA250 and PXA210 Applications Processors Developer's Manual for implementation details, extensions, and options implemented by Intel’s XScaleTM Microarchitecture. The applications processor ’s memory interface supports a variety of memory types that allow flexibility in design requirements. Hooks for connection to two companion chips permit glueless connection to external devices. An integrated LCD display controller provides support for displays, and permits 1, 2 and 4 bit grayscale and 8 or 16 bit color pixels. A 256-byte palette RAM provides flexibility in color mapping. A rich set of serial devices as well as general system resources provide enough compute and connectivity capability for many applications. For details on the programming model and theory of operation of each of these units, refer to the Intel® PXA250 and PXA210 Applications Processors Developer's Manual. For the applications processor ’s block diagram refer to Figure 1, “Applications Processor Block Diagram” on page 8. Datasheet 7 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Figure 1. Applications Processor Block Diagram RTC OS Timer PWM(2) Int Contr . Clocks & Pwr Man. IS I2 C AC97 UART1 UART2 Slow IrDA Fast IrDA SSP USB Client MMC 2 Color or Grayscale LCD Controller Memory Controller DMA Controller And Bridge System Bus Variable Latency I/O Control ASIC Socket 0 PCMCIA & CF Control XCVR Socket 1 Megacell Core Dynamic Memory Control Static Memory Control SDRAM/ SMROM 4 banks ROM/ Flash/ SRAM 4 Banks 3.6864 32.768 MHz KHz Osc Osc 3.0 3.1 Package Information Package Introduction The applications processor is offered in two packages; • The PXA250 applications processor, 256-pin mBGA (refer to Figure 2, “PXA250 Applications Processor” on page 16) • The PXA210 applications processor, 225-pin TPBGA package (refer to Figure 3, “PXA210 Applications Processor” on page 26) 8 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 3.1.1 3.1.1.1 Functional Signal Definitions PXA250 Signal Pin Descriptions Signal definitions for the PXA250 applications processor are described in Table 2, “Pin and Signal Descriptions for the PXA250 Applications Processor” on page 9. The physical characteristics of the PXA250 applications processor are shown in Figure 2, “PXA250 Applications Processor” on page 16. The pinout for the PXA250 applications processor is described in Table 3, “PXA250 256Lead 17x17mm mBGA Pinout — Ballpad Number Order” on page 17. Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 1 of 7) Name Type Description Memory Controller Pins MA[25:0] MD[15:0] MD[31:16] OCZ ICOCZ ICOCZ Memory address bus. This bus signals the address requested for memory accesses. Memory data bus. D[15:0] are used for 16-bit data mode. Memory data bus. D[31:16]: These data bits are used for the PXA250 applications processor 32-bit memories and are not pinned out for the PXA210 applications processor, 16-bit package option. Memory output enable. This signal should be connected to the output enables of memory devices to control their data bus drivers. Memory write enable. Connect this signal should to the write enables of memory devices. SDRAM CS for banks 0 through 3. Connect these signals to the chip select (CS) pins for SDRAM. nSDCS0 is three-stateable nSDCS1-3 are not SDRAM DQM for data bytes 0 through 3. Connect these signals to the data output mask enables (DQM) for SDRAM. SDRAM RAS. Connect this signal should to the row address strobe (RAS) pins for all banks of SDRAM. SDRAM CAS. Connect this signal should to the column address strobe (CAS) pins for all banks of SDRAM. SDRAM and/or Synchronous Static Memory clock enable. Connect SDCKE[0] to the CKE pins of SMROM and SDRAM-timing Synchronous Flash. The memory controller provides control register bits for deassertion of each SDCKE pin. SDRAM and/or Synchronous Static Memory clock enable. SDCKE[1] OC Connect SDCKE[1] to the SDRAM clock enable pins. It is de-asserted (held low) during sleep. SDCKE[1] is always deasserted upon reset. The memory controller provides control register bits for deassertion of each SDCKE pin. nOE nWE nSDCS[3:0] DQM[3:0] nSDRAS nSDCAS OCZ OCZ OCZ OCZ OCZ OCZ SDCKE[0] OC Datasheet 9 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 2 of 7) Name Type Description SDRAM and/or Synchronous Static Memory clocks. Connect SDCLK[0] to the clock (CLK) pins of SMROM and SDRAM-timing Synchronous Flash. SDCLK[1] and SDCLK[2] should be connected to the clock pins of SDRAM in bank pairs 0/1 and 2/3, respectively. They are driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. At reset, all clock pins are free running at the divide by 2 clock speed and may be turned off via free running control register bits in the memory controller. The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin. SDCLK[0] control register assertion bit defaults to on if the boot-time static memory bank 0 is configured for SMROM or SDRAM-timing Synchronous Flash. SDCLK[2:1] control register assertion bits are always deasserted upon reset. 0 and 2 are not three-stateable, SDCLK1 is three-stateable Static chip selects. These signals are chip selects for static memory devices such as ROM and Flash. They are individually programmable in the memory configuration registers. nCS[5:3] may be used with variable data latency variable latency I/O devices. See Note [1] nCS[4]/ GPIO[80] nCS[3]/ GPIO[79] nCS[2]/ GPIO[78] nCS[1]/ GPIO[15] nCS[0] RD/nWR RDY/ GPIO[18] ICOCZ Static chip select 4. SDCLK[2:0] OCZ nCS[5]/ GPIO[33] ICOCZ ICOCZ ICOCZ Static chip select 3. Static chip select 2. ICOCZ ICOCZ OCZ ICOCZ Static chip select 1. Static chip select 0. This is the boot memory chip select. nCS[0] is a dedicated pin. Read/Write for static interface. Intended for use as a steering signal for buffering logic Variable Latency I/O Ready pin (input) See Note [1] PCMCIA/CF Control Pins nPOE/ GPIO[48] nPWE/ GPIO[49] nPIOW/ GPIO[51] nPIOR/ GPIO[50] nPCE[2:1]/ GPIO[53, 52] ICOCZ PCMCIA Output Enable. This PCMCIA signal is an output and performs reads from memory and attribute space. See Note [1] ICOCZ PCMCIA Write Enable. This signal is an output and performs writes to memory and attribute space. See Note [1] ICOCZ PCMCIA I/O Write. This signal is an output and performs write transactions to the PCMCIA I/O space. See Note [1] ICOCZ PCMCIA I/O Read. This signal is an output and performs read transactions from the PCMCIA I/O space. See Note [1] PCMCIA Card Enable. These signals are outputs and select a PCMCIA card. Bit one enables the high byte lane and bit zero enables the low byte lane. See Note [1] ICOCZ 10 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 3 of 7) Name nIOIS16/ GPIO[57] nPWAIT/ GPIO[56] Type Description I/O Select 16. This signal is an input and is an acknowledge from the PCMCIA card that the current address is a valid 16 bit wide I/O address. See Note [1] ICOCZ PCMCIA Wait. This signal is an input and is driven low by the PCMCIA card to extend the length of the transfers to/from applications processor. See Note [1] PCMCIA Socket Select. This signal is an output and is used by external steering logic to route control, address and data signals to one of the two PCMCIA sockets. When PSKTSEL is low, socket zero is selected. When PSKTSEL is high, socket one is selected. This signal has the same timing as an address. See Note [1] PCMCIA Register Select. This signal is an output and indicates that, on a memory transaction, the target address is attribute space. This signal has the same timing as address. See Note [1] LCD Controller Pins L_DD(15:0)/ GPIO[73:58] L_FCLK/ GPIO[74] L_LCLK/ GPIO[75] L_PCLK/ GPIO[76] L_BIAS/ GPIO[77] ICOCZ LCD Controller display data See Note [1] LCD Frame clock See Note [1] LCD Line clock See Note [1] LCD pixel clock See Note [1] AC Bias Drive See Note [1] ICOCZ nPSKTSEL/ GPIO[54] ICOCZ nPREG/ GPIO[55] ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ Full Function UART Pins FFRXD/ GPIO[34] FFTXD/ GPIO[39] FFCTS/ GPIO[35] FFDCD/ GPIO[36] FFDSR/ GPIO[37] FFRI/ GPIO[38] FFDTR/ GPIO[40] FFRTS/ GPIO[41] ICOCZ Full Function UART Receive pin See Note [1] Full Function UART Transmit pin See Note [1] Full Function UART Clear-to-Send pin See Note [1] Full Function UART Data-Carrier-Detect Pin See Note [1] Full Function UART Data-Set-Ready Pin: See Note [1] Full Function UART Ring Indicator Pin See Note [1] Full Function UART Data-Terminal-Ready pin See Note [1] Full Function UART Ready-to-Send pin See Note [1] ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ Datasheet 11 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 4 of 7) Name Type Description Bluetooth UART Pins BTRXD/ GPIO[42] BTTXD/ GPIO[43] BTCTS/ GPIO[44] BTRTS/ GPIO[45] ICOCZ Bluetooth UART Receive pin See Note [1] Bluetooth UART Transmit pin See Note [1] Bluetooth UART Clear-to-Send pin See Note [1] Bluetooth UART Data-Terminal-Ready pin See Note [1] ICOCZ ICOCZ ICOCZ MMC Controller Pins MMCMD MMDAT SSP Pins SSPSCLK/ GPIO[23] SSPSFRM/ GPIO[24] SSPTXD/ GPIO[25] SSPRXD/ GPIO[26] SSPEXTCLK/ GPIO[27] USB Client Pins USB_P USB_N IAOA IAOA USB Client port positive Pin of differential pair. USB Client port negative Pin of differential pair. ICOCZ Synchronous Serial Port Clock (output) See Note [1] Synchronous serial port Frame Signal (output) See Note [1] Synchronous serial port transmit (output) See Note [1] Synchronous serial port receive (input) See Note [1] Synchronous Serial port external clock (input) See Note [1] ICOCZ ICOCZ Multimedia Card Command pin (I/O) Multimedia Card Data Pin (I/O) ICOCZ ICOCZ ICOCZ ICOCZ AC97 Controller Pins BITCLK/ GPIO[28] SDATA_IN0/ GPIO[29] SDATA_IN1/ GPIO[32] SDATA_OUT/ GPIO[30] SYNC/ GPIO[31] nACRESET ICOCZ AC97 Audio Port bit clock (output) See Note [1] AC97 Audio Port data in (input) See Note [1] AC97 Audio Port data in (input) See Note [1] AC97 Audio Port data out (output) See Note [1] AC97 Audio Port sync signal (output) See Note [1] AC97 Audio Port reset signal (output) This pin is a dedicated output. ICOCZ ICOCZ ICOCZ ICOCZ OC 12 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 5 of 7) Name Type Description Standard UART and ICP Pins IRRXD/ GPIO[46] IRTXD/ GPIO[47] ICOCZ IrDA Receive signal (input). See Note [1] IrDA Transmit signal (output). This pin is the transmit pin for both the SIR and FIR functions. See Note [1] ICOCZ I2C Controller Pins I2C clock (Bidirectional) SCL ICOCZ This signal is bidirectional. When it is driving, it functions as an open collector device and requires a pull up resistor. As an input, it expects standard CMOS levels. I2C Data signal (bidirectional). Bidirectional signal. When it is driving, it functions as an open collector device and requires a pull up resistor. As an input, it expects standard CMOS levels. SDA PWM Pins PWM[1:0]/ GPIO[17,16] ICOCZ Pulse Width Modulation channels 0 and 1 (outputs) ICOCZ See Note [1] Dedicated GPIO Pins General Purpose I/O. These two pins are contained in both the PXA250 and PXA210 Applications Processors. They are preconfigured at a hard reset (nRESET) as wakeup sources for both rising and falling edge detects. These GPIOs do not have alternate functions and are intended to be used as the main external sleep wakeup stimulus. GPIO[14:2]) Crystal Pins PXTAL PEXTAL TXTAL TEXTAL IA OA IA OA Input connection for 3.6864 Mhz crystal Output connection for 3.6846 Mhz crystal Input connection for external oscillator Input connection for 32.768 Khz crystal Output connection for 32.768 Khz crystal Input connection for external oscillator ICOCZ General Purpose I/O: These pins are not included in the PXA210 Applications Processor. See Note [1] GPIO[1:0] ICOCZ Datasheet 13 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 6 of 7) Name Miscellaneous Pins Boot programming select pins. These pins are sampled to indicate the type of boot device present per the following table; BOOT_SEL[2:0] 000 001 BOOT_SEL [2:0] IC 010 011 100 101 110 111 Description Asynchronous 32-bit ROM Asynchronous 16-bit ROM Reserved Reserved One 32-bit SMROM One 16 bit SMROM Two 16 bit SMROMs (32 bit bus) Reserved Type Description PWR_EN OCZ Power Enable. Active high output. PWR_EN enables the external power supply. Negating it signals the power supply that the system is going into sleep mode and that the VDD power supply should be removed. Battery Fault. Active low input. nBATT_FAUL T IC Signals the applications processor that the main power source is going away (battery is low or is removed from the system.) The assertion of nBATT_FAULT causes the applications processor to enter Sleep Mode. The device will not recognize a wakeup event while this signal is asserted. VDD Fault. Active low input. nVDD_FAULT IC Signals the applications processor that the main power source is going out of regulation (i.e. shorted card is inserted). nVDD_FAULT causes the device to enter Sleep Mode. nVDD_FAULT is ignored after a wakeup event until the power supply timer completes (approximately 10 ms). Hard reset. Active low input. nRESET is a level sensitive input which starts the processor from a known address. A LOW level causes the current instruction to terminate abnormally, and all on-chip states to be reset. When nRESET is driven HIGH, the processor restarts from address 0. nRESET must remain LOW until the power supply is stable and the internal 3.6864 MHz oscillator has come up to speed. While nRESET is LOW the processor performs idle cycles. Reset Out. Active low output. nRESET IC nRESET_OUT OC This signal is asserted when nRESET is asserted and deasserts after nRESET is negated but before the first instruction fetch. nRESET_OUT is also asserted for “soft” r eset events (sleep, watchdog reset, GPIO reset) JTAG Pins nTRST TDI TDO TMS TCK TEST IC IC OCZ IC IC IC JTAG Test interface reset. If JTAG is used, then you must drive nTRST from low to high either before or at the same time as nRESET If JTAG is not used, then tie nTRST to either nRESET or low. JTAG test interface data input. Note this pin has an internal pullup resistor. JTAG test interface data output. Note this pin does NOT have an internal pullup resistor. JTAG test interface mode select. Note this pin has an internal pullup resistor. JTAG test interface reference Clock. TCK is the reference clock for all transfers on the JTAG test interface. Note this pin has an internal pulldown resistor. Test Mode. You must ground this pin. This pin is for manufacturing purposes only. 14 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 7 of 7) Name TESTCLK Type IC Description Test Clock. This pin should be used for test purposes only. An end user should ground this pin. P ower and Ground Pins VCC VSS PLL_VCC PLL_VSS VCCQ VSSQ VCCN VSSN SUP SUP SUP SUP SUP SUP SUP SUP Positive supply for the applications processor internal Logic. Connect this supply to the low voltage (.85 - 1.3v) supply on the PCB. Ground supply for the applications processor internal logic. Connect these pins to the common ground plane on the PCB. Positive supply for the PLLs and Oscillators. It is recommended that you connect this pin to the common low voltage supply. Ground signal for PLLs. Positive supply for all CMOS I/O, except memory bus and PCMCIA pins. Connect these pins to the common 3.3 volt supply on the PCB. Ground supply for all CMOS I/O except memory bus and PCMCIA pins. Connect these pins to the common ground plane on the PCB. Positive supply for memory bus and PCMCIA pins. Connect these pins to the common 3.3 volt supply on the PCB. Ground supply for memory bus and PCMCIA pins. Connect these pins to the common ground plane on the PCB. Backup battery connection. Connect this pin to the backup battery supply. If a backup battery is not required, then this pin may be connected to the common 3.3 volt supply on the PCB. BATT_VCC SUP NOTE: 1. GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins are disabled to prevent current drain. Datasheet 15 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Figure 2. PXA250 Applications Processor 16 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 1 of 3) Ball # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 VCCN L_DD[13]/GPIO[71] L_DD[12]/GPIO[70] L_DD[11]/GPIO[69] L_DD[9]/GPIO[67] L_DD[7]/GPIO[65] GPIO[11] L_BIAS/GPIO[77] SSPRXD/GPIO[26] SDATA_OUT/GPIO[30] SDA FFDCD/GPIO[36] FFRXD/GPIO[34] FFCTS/GPIO[35] BTCTS/GPIO[44] SDATA_IN1/GPIO[32] DQM[1] DQM[2] L_DD[15]/GPIO[73] GPIO[14] GPIO[13] GPIO[12] L_DD[3]/GPIO[61] L_PCLK/GPIO[76] SSPEXTCLK/GPIO[27] FFRI/GPIO[38] FFDSR/GPIO[37] USB_N BTRXD/GPIO[42] BTRTS/GPIO[45] IRRXD/GPIO[46] MMDAT RDY/GPIO[18] VSSN L_DD[14]/GPIO[72] VSSQ L_DD[8]/GPIO[66] Signal Ball # C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 VCCQ VSSQ USB_P VCCQ VSSQ IRTXD/GPIO[47] VSS SDCLK[2] SDCLK[0] RDnWR VCCN L_DD[10]/GPIO[68] L_DD[5]/GPIO[63] L_DD[1]/GPIO[59] L_LCLK/GPIO[75] SSPTXD/GPIO[25] nACRESET SCL PWM[1]/GPIO[17] BTTXD/GPIO[43] MMCMD VCCQ VSSQ nSDRAS VSSN SDCKE[1] SDCKE[0] L_DD[6]/GPIO[64] L_DD[4]/GPIO[62] L_DD[[0]/GPIO[58] L_FCLK/GPIO[74] SSPSFRM/GPIO[24] SDATA_IN0/GPIO[29] SYNC/GPIO[31] PWM[0]/GPIO[16] FFTXD/GPIO[39] VCCQ Signal Ball # F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 nSDCAS VCCN SDCLK[1] VSSQ GPIO[10] FRTS/GPIO[41] SSPSCLK/GPIO[23] FFDTR/GPIO[40] VCC GPIO[9] BOOT_SEL[2] GPIO[8] VSSQ VSSQ MA[0] VSSN nSDCS[2] nWE nOE nSDCS[1] VCC VSSQ VCC VSSQ TESTCLK TEST BOOT_SEL[1] VCCQ GPIO[7] BOOT_SEL[0] MA[2] MA[1] MD[16] VCCN MD[17] MA[3] VSSQ Signal Datasheet 17 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 2 of 3) Ball # C6 C7 C8 C9 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 VCCQ L_DD[2]/GPIO[60] VSSQ BITCLK/GPIO[28] TCK TMS GPIO[6] TDI TDO MA[7] VSSN MA[6] MD[18] MA[5] MA[4] VCC VSS VSS VSSQ GPIO[5] GPIO[4] nRESET VSSQ PLL_VCC PLL_VSS MA[8] MA[9] MD[19] VCCN MA[10] MA[11] VSSQ VCC VSSQ VCC nRESET_OUT nBATT_FAULT nVDD_FAULT Signal Ball # E15 E16 F1 F2 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 VSSQ VSSQ nSDCS[0] nSDCS[3] VCC GPIO[0] PWR_EN GPIO[1] GPIO[2] VSSQ TEXTAL TXTAL MA[14] MD[21] MA[15] VCCN MD[1] MD[6] MD[7] DQM[0] MD[8] MD[15] BATT_VCC GPIO[22] nPREG/GPIO[55] VCCN VSSN nIOIS16/GPIO[57] MD[22] VSSN MA[16] MD[0] VCCN MD[4] VCCN nCS[0] VCCN MD[13] Signal Ball # H8 H9 H10 H11 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 VSS VSS VCC nTRST MD[24] MD26] MD[27] nCS[2]/GPIO[78] MD[29] MD[12] MD[31] nPOE/GPIO[48] nPCE[1]/GPIO[52] VSSN nPSKTSEL/GPIO[54] MA[18] VSSN MA[20] VSSN MA[22] VSSN MD[25] VSSN MD[10] VSSN MD[30] VSSN nCS[4]/GPIO[80] VSSN nPIOW/GPIO[51] nPCE[2]/GPIO[53] VSS VCCN MD[23] MA[21] MA[24] MD[3] MD[5] Signal 18 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 3 of 3) Ball # K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 GPIO[3] PXTAL PEXTAL MA[12] VSSN MA[13] MD[20] MD[2] VCC DQM[3] MD[28] Signal Ball # N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 VCCN DREQ[0]/GPIO[20] VCCN DREQ[1]/GPIO[19] GPIO[21] nPWAIT/GPIO[56] MA[17] MA[19] VCCN MA[25] MA[23] Signal Ball # T8 T9 T10 T11 T12 T13 T14 T15 T16 Signal nCS[1]/GPIO[15] nCS[3]/GPIO[79] MD[9] MD[11] MD[14] nCS[5]/GPIO[33] nPWE/GPIO[49] nPIOR/GPIO[50] VCCN 3.1.1.2 PXA210 Signal Pin Descriptions Signal definitions for the PXA210 applications processor are described in Table 4. The physical characteristics of the PXA210 applications processor are shown in Figure 3, “PXA210 Applications Processor” on page 26. The pinout for the PXA210 applications processor is described in Table 5, “PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order” on page 27. Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 1 of 7) Pin Name Type Signal Descriptions Memory Controller Pins MA[25:0] MD[15:0] nOE nWE nSDCS[1:0] OCZ ICOCZ OCZ OCZ OCZ Memory address bus. (output) Signals the address requested for memory accesses. Memory data bus. (input/output) Lower 16 bits of the data bus. Memory output enable. (output) Connect to the output enables of memory devices to control data bus drivers. Memory write enable. (output) Connect to the write enables of memory devices. SDRAM CS for banks 1 and 0. (output) Connect to the chip select (CS) pins for SDRAM. For the PXA210 applications processor nSDCS0 can be Hi-Z, nSDCS1 cannot. SDRAM DQM for data bytes 1 and 0. (output) Connect to the data output mask enables (DQM) for SDRAM. SDRAM RAS. (output) Connect to the row address strobe (RAS) pins for all banks of SDRAM. SDRAM CAS. (output) Connect to the column address strobe (CAS) pins for all banks of SDRAM. SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to the CKE pins of SMROM and SDRAM-timing Synchronous Flash. The memory controller provides control register bits for deassertion. DQM[1:0] nSDRAS nSDCAS OCZ OCZ OCZ SDCKE[0] OC Datasheet 19 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 2 of 7) Pin Name Type Signal Descriptions SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to the clock enable pins of SDRAM. It is deasserted during sleep. SDCKE[1] is always deasserted upon reset. The memory controller provides control register bits for deassertion. SDRAM and/or Synchronous Static Memory clocks. (output) Connect to the clock (CLK) pins of SMROM and SDRAM-timing Synchronous Flash. Connect SDCLK[1] to the clock pins of SDRAM in bank pairs 0/1. It is driven by either the internal memory controller clock or the internal memory controller clock divided by 2. At reset, all clock pins are free running at the divide by 2 clock speed and may be turned off via free running control register bits in the memory controller. The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin. SDCLK[0] control register assertion bit defaults to on if the boot-time static memory bank 0 is configured for SMROM or SDRAMtiming Synchronous Flash. SDCLK[1] control register assertion bit is always deasserted on reset. SDCLK[1] can be Hi-Z, SDCLK[0] cannot. SDCKE[1] OC SDCLK[0] OC SDCLK[1] OCZ nCS[5]/ GPIO[33] nCS[4]/ GPIO[80] nCS[3]/ GPIO[79] nCS[2]/ GPIO[78] nCS[1]/ GPIO[15] nPWE/ GPIO[49] nCS[0] RD/nWR RDY/ GPIO[18] L_DD[8]/ GPIO[66] ICOCZ ICOCZ Static chip selects. (output) Chip selects to static memory devices such as ROM and Flash. Individually programmable in the memory configuration registers. nCS[5:3] can be used with variable latency I/O devices. ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ OCZ ICOCZ VLIO write enable (output). Used as the write enable signal for Variable Latency I/O. Static chip select 0. (output) Chip select for the boot memory. nCS[0] is a dedicated pin. Read/Write for static interface. (output) Signals that the current transaction is a read or write. Variable Latency I/O Ready pin. ( input) Notifies the memory controller when an external bus device is ready to transfer data. LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. Memory Controller alternate bus master request. (input) Allows an external device to request the system bus from the Memory Controller. LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. Memory Controller grant. (output) Notifies an external device that it has been granted the system bus. ICOCZ L_DD[15]/ GPIO[73] ICOCZ LCD Controller Pins L_DD(7:0)/ GPIO[65:58] L_DD[8]/ GPIO[66] ICOCZ LCD display data. (outputs) Transfers pixel information from the LCD Controller to the external LCD panel. LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. Memory Controller alternate bus master request. (input) Allows an external device to request the system bus from the Memory Controller. ICOCZ 20 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 3 of 7) Pin Name L_DD[9]/ GPIO[67] L_DD[10]/ GPIO[68] L_DD[11]/ GPIO[69] L_DD[12]/ GPIO[70] L_DD[13]/ GPIO[71] L_DD[14]/ GPIO[72] Type Signal Descriptions LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. MMC chip select 0. ( output) Chip select 0 for the MMC Controller. ICOCZ LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. MMC chip select 1. ( output) Chip select 1 for the MMC Controller. ICOCZ LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. MMC clock. (output) Clock for the MMC Controller. ICOCZ LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. RTC clock. (output) Real time clock 1 Hz tick. ICOCZ LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. ICOCZ LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. 32 kHz clock. (output) Output from the 32 kHz oscillator. LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. Memory Controller grant. (output) Notifies an external device it has been granted the system bus. LCD frame clock. (output) Indicates the start of a new frame. Also referred to as Vsync. LCD line clock. (output) Indicates the start of a new line. Also referred to as Hsync. LCD pixel clock. (output) Clocks valid pixel data into the LCD’s line shift buffer. AC bias drive. (output) Notifies the panel to change the polarity for some passive LCD panel. For TFT panels, this signal indicates valid pixel data. ICOCZ L_DD[15]/ GPIO[73] L_FCLK/ GPIO[74] L_LCLK/ GPIO[75] L_PCLK/ GPIO[76] L_BIAS/ GPIO[77] ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ Full Function UART Pins FFRXD/ GPIO[34] FFTXD/ GPIO[39] ICOCZ ICOCZ Full Function UART Receive. (input) MMC chip select 0. ( output) Chip select 0 for the MMC Controller. Full Function UART Transmit. (output) MMC chip select 1. ( output) Chip select 1 for the MMC Controller. Bluetooth UART Pins BTRXD/ GPIO[42] BTTXD/ GPIO[43] BTCTS/ GPIO[44] BTRTS/ GPIO[45] ICOCZ Bluetooth UART Receive. (input) ICOCZ ICOCZ Bluetooth UART Transmit. ( output) Bluetooth UART Clear-to-Send. (input) ICOCZ Bluetooth UART Data-Terminal-Ready. ( output) Datasheet 21 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 4 of 7) Pin Name Type Signal Descriptions Standard UART and ICP Pins IRRXD/ GPIO[46] IRTXD/ GPIO[47] ICOCZ IrDA receive signal. (input) Receive pin for the FIR function. Standard UART receive. (input) IrDA transmit signal. (output) Transmit pin for the Standard UART, SIR and FIR functions. Standard UART transmit. (output) ICOCZ MMC Controller Pins MMCMD MMDAT GPIO[53] L_DD[9]/ GPIO[67] L_DD[10]/ GPIO[68] L_DD[11]/ GPIO[69] FFRXD/ GPIO[34] FFTXD/ GPIO[39] SSP Pins SSPSCLK/ GPIO[23] SSPSFRM/ GPIO[24] SSPTXD/ GPIO[25] SSPRXD/ GPIO[26] SSPEXTCLK/ GPIO[27] USB Client Pins USB_P USB_N IAOAZ IAOAZ USB Client Positive. ( bidirectional) USB Client Negative pin. (bidirectional) ICOCZ Synchronous Serial Port Clock. (output) ICOCZ ICOCZ ICOCZ ICOCZ Multimedia Card Command. (bidirectional) Multimedia Card Data. ( bidirectional) MMC clock. (output) Clock signal for the MMC Controller. LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. MMC chip select 0. (output) Chip select 0 for the MMC Controller. ICOCZ LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. MMC chip select 1. (output) Chip select 1 for the MMC Controller. LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. MMC clock. (output) Clock for the MMC Controller. Full Function UART Receive. ( input) MMC chip select 0. (output) Chip select 0 for the MMC Controller. Full Function UART Transmit. (output) MMC chip select 1. (output) Chip select 1 for the MMC Controller. ICOCZ ICOCZ ICOCZ ICOCZ Synchronous Serial Port Frame. (output) ICOCZ ICOCZ Synchronous Serial Port Transmit. (output) Synchronous Serial Port Receive. (input) ICOCZ Synchronous Serial Port External Clock. (input) 22 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 5 of 7) Pin Name Type 2 Signal Descriptions AC97 Controller and I S Controller Pins AC97 Audio Port bit clock. (input) AC97 clock is generated by Codec 0 and fed into the PXA210 applications processor and Codec 1. BITCLK/ GPIO[28] AC97 Audio Port bit clock. (output) AC97 clock is generated by the PXA210 applications processor. I2S bit clock. (input) I2S clock is generated externally and fed into PXA210 applications processor. I2S bit clock. ( output) I2S clock is generated by the PXA210 applications processor. SDATA_IN0/ GPIO[29] SDATA_IN1/ GPIO[32] SDATA_OUT/ GPIO[30] SYNC/ GPIO[31] nACRESET ICOCZ AC97 Audio Port data in. (input) Input line for Codec 0. I2S data in. (input) Input line for the I2S Controller. AC97 Audio Port data in. (input) Input line for Codec 1. I2S system clock. (output) System clock from I2S Controller. AC97 Audio Port data out. (output) Output from the PXA210 to Codecs 0 and 1. I2S data out. (output) Output line for the I2S Controller. AC97 Audio Port sync signal. (output) Frame sync signal for the AC97 Controller. I2S sync. (output) Frame sync signal for the I2S Controller. OC AC97 Audio Port reset signal. (output) ICOCZ ICOCZ ICOCZ ICOCZ I2C Controller Pins SCL SDA PWM Pins PWM[1:0]/ GPIO[17:16] GPIO Pins GPIO[1:0] GPIO[57:48] ICOCZ ICOCZ General Purpose I/O. Wakeup sources on both rising and falling edges on nRESET. General Purpose I/O. Wakeup sources on both rising and falling edges on nRESET. ICOCZ Pulse Width Modulation channels 0 and 1. (outputs) ICOCZ ICOCZ I2C clock. (bidirectional) I2C data. (bidirectional). Crystal and Clock Pins PXTAL PEXTAL TXTAL TEXTAL L_DD[12]/ GPIO[70] L_DD[13]/ GPIO[71] L_DD[14]/ GPIO[72] IA OA IA OA ICOCZ 3.6864 Mhz crystal input. 3.6864 Mhz crystal output. 32.768 khz crystal input. 32.768 khz crystal output. LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. RTC clock. (output) Real time clock 1 Hz tick. ICOCZ LCD display data. (output) Transfers the pixel information from the LCD Controller to the external LCD panel. 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. ICOCZ LCD display data. ( output) Transfers pixel information from the LCD Controller to the external LCD panel. 32 kHz clock. (output) Output from the 32 kHz oscillator. Datasheet 23 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 6 of 7) Pin Name Type Signal Descriptions Miscellaneous Pins BOOT_SEL [2:0] PWR_EN IC OC Boot select pins. (input) Indicates type of boot device. Power Enable for the power supply. ( output) When negated, it signals the power supply to remove power because the system is entering Sleep Mode. Main Battery Fault. (input) Signals that main battery is low or removed. Assertion causes the PXA210 applications processor to enter Sleep Mode or force an Imprecise Data Exception, which cannot be masked. The PXA210 applications processor will not recognize a wakeup event while this signal is asserted. VDD Fault. ( input) Signals that the main power source is going out of regulation. nVDD_FAULT causes the PXA210 applications processor to enter Sleep Mode or force an Imprecise Data Exception, which cannot be masked. nVDD_FAULT is ignored after a wakeup event until the power supply timer completes (approximately 10 ms). Hard reset. (input) Level sensitive input used to start the processor from a known address. Assertion causes the current instruction to terminate abnormally and causes a reset. When nRESET is driven high, the processor starts execution from address 0. nRESET must remain low until the power supply is stable and the internal 3.6864 MHz oscillator has stabilized. Reset Out. (output) Asserted when nRESET is asserted and deasserts after nRESET is deasserted but before the first instruction fetch. nRESET_OUT is also asserted for “ soft” reset events: sleep, watchdog reset, or GPIO reset. nBATT_FAULT IC nVDD_FAULT IC nRESET IC nRESET_OUT OC JTAG and Test Pins JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used, drive nTRST from low to high either before or at the same time as nRESET. If JTAG is not used, nTRST must be either tied to nRESET or tied low. Intel recommends that a JTAG/Debug port be added to all systems for debug and download. See Chapter 9 in the “Intel® P XA250 and PXA210 Applications Processor Design Guide” for details. JTAG test data input. (input) Data from the JTAG controller is sent to the PXA210 using this pin. This pin has an internal pull-up resistor. JTAG test data output. (output) Data from the PXA210 applications processor is returned to the JTAG controller using this pin. JTAG test mode select. ( input) Selects the test mode required from the JTAG controller. This pin has an internal pull-up resistor. JTAG test clock. (input) Clock for all transfers on the JTAG test interface. Test Mode. (input) Reserved. Must be grounded. Test Clock. (input) Reserved. Must be grounded. nTRST IC TDI TDO TMS TCK TEST TESTCLK IC OCZ IC IC IC IC Power and Ground Pins VCC VSS PLL_VCC PLL_VSS VCCQ SUP SUP SUP SUP SUP Positive supply for internal logic. M ust be connected to the low voltage (.85 1.3v) supply on the PCB. Ground supply for internal logic. Must be connected to the common ground plane on the PCB. Positive supply for PLLs and oscillators. M ust be connected to a separate quiet supply plane on the PCB but may be connected to the common low voltage supply. Ground signal for PLLs. Positive supply for all CMOS I/O except memory bus. Must be connected to the common 3.3 V supply on the PCB. 24 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 7 of 7) Pin Name VSSQ VCCN VSSN Type SUP SUP SUP Signal Descriptions Ground supply for all CMOS I/O except memory bus. M ust be connected to the common ground plane on the PCB. Positive supply for memory bus. Must be connected to the common 3.3 V or 2.5 V supply on the PCB. Ground supply for memory bus and some GPIO pins. Must be connected to the common ground plane on the PCB. Backup battery supply. Connect to the backup battery supply. If a backup battery is not required then this pin may be connected to the common 3.3 V supply on the PCB. BATT_VCC SUP Datasheet 25 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Figure 3. PXA210 Applications Processor 26 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 1 of 3) Ball # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 C7 DQM[1] L_DD[14]/GPIO[72] L_DD[10]/GPIO[68] VSSQ L_DD[6]/GPIO[64] L_DD[2]/GPIO[60] L_LCLK/GPIO[75] SSPSCLK/GPIO[23] SSPEXTCLK/GPIO[27] nACRESET PWM[1]/GPIO[17] VSSQ FFRXD/GPIO[34] BTCTS/GPIO[44] IRRXD/GPIO[46] RDY/GPIO[18] VSSN L_DD[13]/GPIO[71] L_DD[9]/GPIO[67] VSSQ L_DD[3]/GPIO[61] L_PCLK/GPIO[76] VSSQ BITCLK/GPIO[28] SDA VSSQ USB_N BTRTS/GPIO[45] IRTXD/GPIO[47] MMDAT SDCKE[1] SDCKE[0] VCCN L_DD[12]/GPIO[70] VCCQ L_DD[4]/GPIO[62] L_BIAS/GPIO[77] Signal Ball # C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 F1 F2 F3 Signal BTTXD/GPIO[43] VSSQ VSS VCCQ VCC VSSQ SDCLK[1] L_DD[15]/GPIO[73] VCC L_DD[5]/GPIO[63] L_DD[0]/GPIO[58] SSPSFRM/GPIO[24] SDATA_OUT/GPIO[30] SCL SDATA_IN1/GPIO[32] BOOT_SEL[1] VSSQ VSSQ VSSQ nSDCAS VCCN VSSN SDCLK[0] L_DD[11]/GPIO[69] L_DD[7]/GPIO[65] L_DD[1]/GPIO[59] SSPTXD/GPIO[25] SYNC/GPIO[31] VCCQ MMCMD VCCQ VSSQ VSSQ BOOT_SEL[2] VSSN NSDCS[0] NSDRAS Ball # F8 F9 F10 F11 F12 F13 F14 F15 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 Signal SSPRXD/GPIO[26] VCC FFTXD/GPIO[39] VCC VSSQ TESTCLK BOOT_SEL[0] TEST MA[0] nOE nWE VCCN VSSN RDnWR VSS VSS VSS BTRXD/GPIO[42] nTRST TDI TCK TMS TDO VCCN VSSN MA[2] MA[1] VCC VSSQ VSS VSS VSS VSSQ VCC VSSQ VCC PLL_VCC Datasheet 27 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 2 of 3) Ball # C8 C9 C10 C11 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 L1 L2 L3 L4 L5 L6 L7 VCCQ SDATA_IN0/GPIO[29] PWM[0]/GPIO[16] USB_P MA[4] MA[3] VSSQ VSS VSS VSS VSSQ nRESET nRESET_OUT PWR_EN nVDD_FAULT nBATT_FAULT MA[8] MA[9] MA[10] MA[7] VCCN VCC VSSQ VCC VSSQ VCC GPIO[1] TEXTAL TXTAL PEXTAL PXTAL VSSN VCCN MA[12] MA[13] MA[11] VSSQ MD[2] Signal Ball # F4 F5 F6 F7 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 Signal NSDCS[1] VCC L_DD[8]/GPIO[66] L_FCLK/GPIO[74] GPIO[0] MA[14] MA[15] VCCN MA[16] VCCN VSSN MD[3] MD[7] nCS[1]/GPIO[15] MD[10] MD[13] GPIO[48] GPIO[52] VSSN GPIO[56] VSSN MA[18] VSS MA[22] MA[24] VCCN VCC VSSN DQM[0] VCCN MD[12] VSSN nCS[5]/GPIO[33] GPIO[53] VCCN MA[17] VSSN VCCN Ball # H15 J1 J2 J3 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Signal PLL_VSS MA[5] MA[6] VSSN VCCN MD[15] VCCN GPIO[50] VSSQ MA[19] MA[20] MA[21] MA[25] MD[1] VCCN MD[5] nCS[0] nCS[3]/GPIO[79] MD[9] VSSN MD[14] nCS[4]/GPIO[80] nPWE/GPIO[49] GPIO[51] 28 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 3 of 3) Ball # L8 L9 L10 L11 L12 L13 L14 MD[6] VSSN MD[11] BATT_VCC GPIO[54] GPIO[55] GPIO[57] Signal Ball # P4 P5 P6 P7 P8 P9 P10 MA[23] MD[0] VSSN MD[4] VCCN nCS[2]/GPIO[78] MD[8] Signal Ball # Signal 3.2 Table 6. Package Power Ratings JA and Maximum Power Ratings Processor PXA250 PXA210 JA Max Power 1.4W 888W 33 C /w 44 C /w 4.0 4.1 Electrical Specifications Absolute Maximum Ratings This section provide the Absolute Maximum ratings for the applications processors. Do not exceed these parameters. If you do the part may be permanently damaged. Operation at Absolute Maximum Ratings is not guaranteed. Table 7. Absolute Maximum Ratings (Sheet 1 of 2) Symbol TS VSS_O VCC_O VCC_HV VCC_LV Storage Temperature Offset Voltage between any two VSS pins (VSS, VSSQ, VSSN) Offset Voltage between any of the following pins: VCCQ and VCCN Voltage Applied to High Voltage Supplies (VCCQ, VCCN, BATT_VCC) Voltage Applied to Low Voltage Supplies (VCC, PLL_VCC) Voltage Applied to non-Supply pins except XTAL pins Description Min -40 -0.3 -0.3 VSS-0.3 VSS-0.3 Max 125 0.3 0.3 VSS+4.0 VSS+1.65 max of VCCQ+0.3, VSS+4.0 Units deg C V V V V VIP VSS-0.3 V Datasheet 29 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 7. Absolute Maximum Ratings (Sheet 2 of 2) Symbol VIP_X Description Voltage Applied to XTAL pins (PXTAL, PEXTAL, TXTAL, TEXTAL) Maximum ESD stress voltage, Human Body Model; Any pin to any supply pin, either polarity, or Any pin to all nonsupply pins together, either polarity. Three stresses maximum. Maximum DC Input Current (Electrical Overstress) for any non-supply pin Min VSS-0.3 Max max of VCC+0.3, VSS+1.65 Units V VESD 2000 V IEOS 5 mA 4.2 Operating Conditions This section shows voltage, frequency, and temperature specifications for the applications processor for four different ranges (shown in Table 8, “Voltage, Temperature, and Frequency Electrical Specifications”.) The temperature specification for each range is constant; the frequency range is dependent on the operation voltage. Note: The parameters in Table 8 are preliminary and subject to change. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 1 of 2) Symbol tA tA VVSS VVCCQ VVCCN VBATT Description Ambient Temperature - Extended Temp Ambient Temperature - Nominal Temp VSS, VSSN, VSSQ Voltage VCCQ Voltage VCCN Voltage BATT_VCC Voltage Min -40 0 -0.3 3.0 2.375 2.2 Typical 0 3.3 2.5/3.3 3.0 Max 85 70 0.3 3.6 3.6 3.8 Units °C °C V V V V Table 8. Low Voltage Range (PXA250 and PXA210) VVCC_L fTURBO_L fSDRAM_L VCC, PLL_VCC Voltage, Low Range Turbo Mode Frequency, Low Range External Synchronous Memory Frequency, Low Range 0.765 99.5 50 0.85 0.935 132.7 99.5 V MHz MHz Medium Voltage Range (PXA250 and PXA210) VVCC_M fTURBO_M fSDRAM_M VCC, PLL_VCC Voltage, Mid Range Turbo Mode Frequency, Mid Range External Synchronous Memory Frequency, Mid Range 0.90 99.5 50 1.00 1.10 199.1 99.5 V MHz MHz High Voltage Range (PXA250) VVCC_H fTURBO_H fSDRAM_H VCC, PLL_VCC Voltage, High Range Turbo Mode Frequency, High Range External Synchronous Memory Frequency, High Range 0.99 99.5 50 1.10 1.21 298.7 99.5 V MHz MHz 30 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 8. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 2 of 2) Symbol Description Min Typical Max Units Peak Voltage Range (PXA250) VVCC_P fTURBO_P fSDRAM_P VCC, PLL_VCC Voltage, Peak Range Turbo Mode Frequency, Peak Range External Synchronous Memory Frequency, Peak Range 1.17 99.5 50 1.30 1.43 398.2 99.5 V MHz MHz 4.3 Targeted DC Specifications The DC Characteristics for each pin include input sense levels and output drive levels and currents. These parameters can be used to determine maximum DC loading, and also to determine maximum transition times for a given load. The DC Operating Conditions for the High- and Low-Strength Input, Output, and I/O pins are shown in Table 9, “Standard Input, Output, and I/O Pin DC Operating Conditions”. All DC specification values are valid for the entire temperature range of the device. Table 9. Standard Input, Output, and I/O Pin DC Operating Conditions Symbol Input DC Operating Conditions VIH VIL IIN Input High Voltage, all standard input and I/O pins Input Low Voltage, all standard input and I/O pins Input Leakage, all standard input and IO pins 0.8*VCCQ VSS VCCQ 0.2*VCCQ 10 V V A Description Min Typical Max Units Output DC Operating Conditions VOH VOL IOH_H IOH_L IOL_H IOL_L Output High Voltage, all standard output and I/O pins Output Low Voltage, all standard output and I/O pins Output High Current, all standard, highstrength output and I/O pins (VO=VOH) Output High Current, all standard, lowstrength output and I/O pins (VO=VOH) Output Low Current, all standard, highstrength output and I/O pins (VO=VOH) Output Low Current, all standard, lowstrength output and I/O pins (VO=VOH) VCCQ-0.6 VSS -10 -3 10 3 VCCQ VSS+0.4 V V mA mA mA mA Datasheet 31 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification 4.4 Targeted AC Specifications All the non-analog input, output, and I/O pins on the applications processor can be divided into one of two categories: 1. High Strength Input, Output, and I/O pins: • • • • • • • • • • nCS[5:1] (GP 33, 80, 79, 78, 15 respectively), nCS[0] MD[31:0], MA[25:0] DQM[3:0] nOE, nWE, nSDRAS, nSDCAS, nSDCS[3:0] SDCLK[2:0], SDCKE[1:0] RDnWR, RDY (GP[18]) nPWE, nPOE pins (GP[49:48]) MMCLK (GP[53]), MMCMD, MMDAT TDO nACRESET 2. Low Strength Input, Output, and I/O pins - all remaining non-supply pins A pin’s AC Characteristics include input and output capacitance. These determine loading for external drivers or other load analysis. The AC Characteristics also include a de-rating factor, which indicates how much faster or slower the AC timings get with different loads. The AC Operating Conditions for the high- and low-strength input, output, and I/O pins are shown in Table 10, “Standard Input, Output, and I/O Pin AC Operating Conditions”. All AC specification values are valid for entire temperature range of the device. Table 10. Standard Input, Output, and I/O Pin AC Operating Conditions S ymbol CIN COUT_H Description Input Capacitance, all standard input and IO pins Output Capacitance, all standard highstrength output and IO pins Output de-rating, falling edge on all standard, high-strength output and I/O pins, from 50pF load. Output de-rating, rising edge on all standard, high-strength output and I/O pins, from 50pF load. 251 Min Typical Max 10 501 Units pF pF tdF_H ns/pF tdR_H ns/pF NOTE: AC Specifications guaranteed for loads in this range. All testing is done at 50pF 32 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 4.5 Oscillator Electrical Specifications The applications processor contains two oscillators: a 32.768 kHz oscillator and a 3.6864 MHz oscillator. Each is for a specific crystal. When choosing a crystal, match the crystal parameters as closely as possible. 4.5.1 32.768 kHz Oscillator Specifications The 32.768 kHz Oscillator is connected between the TXTAL (amplifier input) and TEXTAL (amplified output). The 32.768 kHz specifications are shown in Table 11, “32.768 kHz Oscillator Specifications”. Table 11. 32.768 kHz Oscillator Specifications Symbol Description Min Typical Max Units Crystal Specifications - Typical is FOX NC38 FXT LMT CMT RMT COT CLT Crystal Frequency, TXTAL/TEXTAL Motional Inductance, TXTAL/TEXTAL Motional Capacitance, TXTAL/TEXTAL Motional Resistance, TXTAL/TEXTAL Shunt Capacitance TXTAL to TEXTAL Load Capacitance TXTAL/TEXTAL 6 32.768 6827.81 3.455 16 1.6 12.5 35 kHz H fF k pF pF Amplifier Specifications VIH_X VIL_X IIN_XT CIN_XT tS_XT Input High Voltage, TXTAL Input Low Voltage, TXTAL Input Leakage, TXTAL Input Capacitance, TXTAL/TEXTAL Stabilization Time 2 18 0.8*VCC VSS VCC 0.2*VCC 1 25 10 V V A pF s Board Specifications RP_XT CP_XT COP_XT Parasitic Resistance, TXTAL/TEXTAL to any node Parasitic Capacitance, TXTAL/TEXTAL, total Parasitic Shunt Capacitance, TXTAL to TEXTAL 20 5 0.4 M pF pF To drive the 32.768 kHz crystal pins from an external source: • Drive the TEXTAL pin with a digital signal that has a low level near 0 volts and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 volt per 1 µs. The maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1 mA. • Float the TXTAL pin or drive it complementary to the TEXTAL pin, with the same voltage level, slew rate, and input current restrictions. Datasheet 33 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification 4.5.2 3.6864 MHz Oscillator Specifications The 3.6864 MHz Oscillator is connected between the PXTAL (amplifier input) and PEXTAL (amplified output). The 3.6864 MHz specifications are shown in Table 12, “3.6864 MHz Oscillator Specifications”. Table 12. 3.6864 MHz Oscillator Specifications S ymbol Description Min Typical Max Units Crystal Specifications - Typical is FOX HC49S FXP LMP CMP RMP COP CLP Crystal Frequency, PXTAL/PEXTAL Motional Inductance, PXTAL/PEXTAL Motional Capacitance, PXTAL/PEXTAL Motional Resistance, PXTAL/PEXTAL Shunt Capacitance PXTAL to PEXTAL Load Capacitance PXTAL/PEXTAL 50 3.6864 0.50593 3.68488 99.3 1.7 20 200 MHz H fF W pF pF Amplifier Specifications VIH_X VIL_X IIN_XP CIN_XP tS_XP Input High Voltage, PXTAL Input Low Voltage, PXTAL Input Leakage, PXTAL Input Capacitance, PXTAL/PEXTAL Stabilization Time 17.8 40 0.8*VCC VSS VCC 0.2*VCC 10 50 67.8 V V A pF ms Board Specifications RP_XP CP_XP COP_XP Parasitic Resistance, PXTAL/PEXTAL to any node Parasitic Capacitance, PXTAL/PEXTAL, total Parasitic Shunt Capacitance, PXTAL to PEXTAL 20 5 0.4 M pF pF To drive the 3.6864 MHz crystal pins from an external source: • Drive the PEXTAL pin with a digital signal with a low level near 0 volts and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 volt / 100 ns. The maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1 mA. • Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system, and it is therefore not recommended. 34 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 4.6 Reset and Power AC Timing Specifications The applications processor asserts the nRESET_OUT pin in one of several different modes: • • • • • Power On Hardware Reset Watchdog Reset GPIO Reset Sleep Mode The following sections give the timing and specifications for the entry and exit of these modes. 4.6.1 Power On Timing The External Voltage Regulator and other power-on devices must provide the applications processor with a specific sequence of power and resets to ensure proper operation. This sequence is shown in Figure 4, “Power-On Reset Timing” on page 36, and detailed in Table 13, “Power-On Timing Specifications” on page 36. On the applications processor, it is important that the power supplies be powered-up in a certain order to avoid high current situations. The required order is: 1. BATT_VCC 2. VCCQ 3. VCCN 4. VCC and PLL_VCC The supply in step 3 may be powered at the same time as those in step 2, however, VCCN should not be powered before VCCQ. Datasheet 35 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Note: If Hardware Reset is entered during Sleep Mode, follow the proper power-supply stabilization times and nRESET timing requirements indicated in Table 13. Figure 4. Power-On Reset Timing tR_BA TT BATT_VCC t D_VCCQ tR_VCCQ tR_VCC t D_VCC N VCCQ VCCN N tR_VCC t D_VCC VCC tD_NTRST nTRST JTAG PINS nRESET t D_JT tD_NRESET t D_OUT Note: nBA T_F nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is T AULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or the PXA250 applications processor enters Sleep Mode. deassertedor the Cotulla enters Sleep Mode AG Table 13. Power-On Timing Specifications S ymbol tR_BATT tR_VCCQ tR_VCC tD_VCCQ tD_VCC tD_NTRST tD_JTAG tD_NRESET tD_OUT Description BATT_VCC Rise / Stabilization time VCCQ, VCCN Rise / Stabilization time VCC, PLL_VCC Rise / Stabilization time Delay between BATT_VCC at voltage and before VCCQ and VCCN applied Delay from VCCQ, VCCN at voltage and before VCC, PLL_VCC applied Delay between VCC, PLL_VCC stable and nTRST deasserted Delay between nTRST deasserted and JTAG pins active, with nRESET asserted Delay between VCC, PLL_VCC stable and nRESET deasserted Delay between nRESET deasserted and nRESET_OUT deasserted Min 0.01 0.01 0.01 0 0 50 0.03 50 18.1 18.2 — Typical Max 100 100 10 Units ms ms ms ms ms ms ms ms ms 4.6.2 Hardware Reset Timing The timing sequences shown in Hardware Reset Timing for hardware reset assumes stable power supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings indicated in Section 4.6.1, “Power On Timing” on page 35. 36 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Figure 5. Hardware Reset Timing nRESET nRESET_OUT tDHW_OUT_A t DHW_NRESET tDHW_OUT Note: nBA TT_FAULT and nVDD_F AULT must be high before Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted is or the Cotulla will enter Sleep Mode deasserted or the PXA250 applications processor enters Sleep Mode. Table 14. Hardware Reset Timing Specifications S ymbol tDHW_NRESET tDHW_OUT_A tDHW_OUT Description Minimum assertion time of nRESET Delay between nRESET Asserted and nRESET_OUT Asserted Delay between nRESET deasserted and nRESET_OUT deasserted Min 0.001 0 18.1 0.001 18.2 Typical Max Units ms ms ms 4.6.3 Watchdog Reset Timing Watchdog Reset is an internally generated reset and therefore has no external pin dependencies. The nRESETOUT pin is the only indicator of Watchdog Reset, and it stays asserted for tDHW_OUT. Refer to Figure 5, “Hardware Reset Timing” on page 37. 4.6.4 GPIO Reset Timing GPIO Reset is generated externally, and the source is reconfigured as a standard GPIO as soon as the reset propagates internally. The clocks module is not reset by GPIO Reset, so the timing varies based on the frequency of clock selected and if the Clocks and Power Manager is in the Frequency Change Sequence when GPIO Reset is asserted (see Section 4.5.1, “32.768 kHz Oscillator Specifications” on page 33.) Figure 6, “GPIO Reset Timing” on page 37 shows the possible timing of GPIO Reset. Figure 6. GPIO Reset Timing t GP[1] nRESET_OUT t A_GP[1] t DHW_OUT_A DHW_OUT Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted or the application processor will enter Sleep Mode Datasheet 37 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 15. GPIO Reset Timing Specifications Symbol tA_GP[1] Description Minimum assert time of GP[1]1 in 3.6864MHz input clock cycles Delay between GP[1] Asserted and nRESET_OUT Asserted in 3.6864MHz input clock cycles Delay between nRESET_OUT asserted and nRESET_OUT deasserted, Run or Turbo Mode2 Delay between nRESET_OUT asserted and nRESET_OUT deasserted, during Frequency Change Sequence3 Min 4 Typical Max Units cycles tDHW_OUT_A 6 8 cycles tDHW_OUT 5 28 s tDHW_OUT_F 5 380 s NOTES: 1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check the state of GP[1] before configuring as a Reset to ensure no spurious reset is generated. 2. Time is 512*N Processor Clock Cycles plus up to 4 cycles of the 3.6864MHz input clock. 3. Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the assertion of GPIO Reset. The Lock Detector has a maximum time of 350µs plus synchronization. 4.6.5 Sleep Mode Timing Sleep Mode is internally asserted, it and asserts the nRESET_OUT and PWR_EN signals. The sequence indicated in Figure 7, “Sleep Mode Timing” on page 38 and detailed in Figure 16, “Sleep Mode Timing Specifications” on page 39 is the required timing parameters for Sleep Mode. Figure 7. Sleep Mode Timing tA_GP[x] GP[x] PWR_EN VCC nVDD_FAULT nRESET_OUT tD_F A UL T tD_PWR_F t D_PWR_R tDSM_VCC t DSM_OUT Note: nBA TT_FAULT must be high or the PXA250 applications processor Note: nBATT_FAULT must be high or Cotulla will not exit Sleep Mode will not exit Sleep Mode. 38 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 16. Sleep Mode Timing Specifications Symbol tA_GP[x} tD_PWR_F tD_PWR_R tDSM_VCC tD_FAULT tDSM_OUT tDSM_OUT_O Description Assert Time of GPIO Wake up Source (x=[15:0]) Delay from nRESET_OUT asserted to PWR_EN deasserted Delay between GP[x] asserted to PWR_EN asserted Delay between PWR_EN asserted and VCC stable Delay between PWR_EN asserted and nVDD_FAULT deasserted Delay between PWR_EN asserted and nRESET_OUT deasserted, OPDE Set Delay between PWR_EN asserted and nRESET_OUT deasserted, OPDE Clear 28.0 10.35 Min 91.6 61 30.5 91.6 122.1 10 10 80 10.5 Typical Max Units s s s ms ms ms ms 4.7 Memory Bus and PCMCIA AC Specifications This section gives the timing information for these types of memory: • SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes (Table 17, “SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications” on page 39) • Variable Latency I/O (Table 18, “Variable Latency I/O Interface AC Specifications” on page 40) • Card Interface (PCMCIA or Compact Flash) (Table 19, “Card Interface (PCMCIA or Compact Flash) AC Specifications” on page 41) • Synchronous Memories (Table 20, “Synchronous Memory Interface AC Specifications1” on page 42) Table 17. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (Sheet 1 of 2) MEMCLK Frequency (MHz) Symbol Description 99.5 tromAS tromAH tromASW tromAHW tromCES tromCEH tromDS MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) asserted MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) deasserted MA(25:0) setup to nWE asserted MA(25:0) hold after nWE deasserted nCS setup to nWE asserted nCS hold after nWE deasserted MD(31:0), DQM(3:0) write data setup to nWE asserted 10 10 30 10 20 10 10 118.0 8.5 8.5 25.5 8.5 17 8.5 8.5 132.7 7.5 7.5 22.5 7.5 15 7.5 7.5 147.5 6.8 6.8 20.4 6.8 13.6 6.8 6.8 165.9 6 6 18 6 12 6 6 Units, Notes ns, 1 ns, 1 ns, 3 ns, 1 ns, 2 ns, 1 ns, 1 Datasheet 39 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 17. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (Sheet 2 of 2) MEMCLK Frequency (MHz) Symbol Description 99.5 tromDSWH tromDH tromNWE MD(31:0), DQM(3:0) write data setup to nWE deasserted MD(31:0), DQM(3:0) write data hold after nWE deasserted nWE high time between beats of write data 20 10 20 118.0 17 8.5 17 132.7 15 7.5 15 147.5 13.6 6.8 13.6 165.9 12 6 12 Units, Notes ns, 2 ns, 1 ns, 2 NOTES: 1. This number represents 1 MEMCLK period 2. This number represents 2 MEMCLK periods 3. This number represents 3 MEMCLK periods Table 18. Variable Latency I/O Interface AC Specifications MEMCLK Frequency (MHz) Symbol tvlioAS tvlioASRW tvlioAH tvlioCES tvlioCEH tvlioDSW tvlioDSWH tvlioDHW tvlioDHR tvlioRDYH tvlioNPWE Description 99.5 MA(25:0) setup to nCS asserted MA(25:0) setup to nOE or nPWE asserted MA(25:0) hold after nOE or nPWE deasserted nCS setup to nOE or nPWE asserted nCS hold after nOE or nPWE deasserted MD(31:0), DQM(3:0) write data setup to nPWE asserted MD(31:0), DQM(3:0) write data setup to nPWE deasserted MD(31:0), DQM(3:0) hold after nPWE deasserted MD(31:0) read data hold after nOE deasserted RDY hold after nOE, nPWE deasserted nPWE, nOE high time between beats of write or read data 10 10 10 20 10 10 20 10 0 0 20 118.0 8.5 8.5 8.5 17 8.5 8.5 17 8.5 0 0 17 132.7 7.5 7.5 7.5 15 7.5 7.5 15 7.5 0 0 15 147.5 6.8 6.8 6.8 13.6 6.8 6.8 13.6 6.8 0 0 13.6 165.9 6 6 6 12 6 6 12 6 0 0 12 Units, Notes ns, 1 ns, 1 ns, 1 ns, 2 ns, 1 ns, 1 ns, 2 ns, 1 ns ns ns, 2 NOTES: 1. This number represents 1 MEMCLK period 2. This number represents 2 MEMCLK periods 40 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 19. Card Interface (PCMCIA or Compact Flash) AC Specifications MEMCLK Frequency (MHz) Symbol Description 99.5 tcardAS MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or nPIOR asserted MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or nPIOR deasserted MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR deasserted nPWE, nPOE, nPIOW, or nPIOR command assertion 20 118.0 17 132.7 15 147.5 13.6 165.9 12 Units, Notes ns, 1 tcardAH 10 8.5 7.5 6.8 6 ns, 1 tcardDS tcardDH tcardCMD 10 10 30 8.5 8.5 25.5 7.5 7.5 22.5 6.8 6.8 20.4 6 6 18 ns, 1 ns, 1 ns, 1 NOTE: These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers. Datasheet 41 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Table 20. Synchronous Memory Interface AC Specifications1 Symbol Description MIN MAX Units, Notes SDRAM / SMROM / SDRAM-Timing Synchronous Flash (Synchronous) tsynCLK tsynCMD tsynRCD tsynCAS tsynSDOS SDCLK period nSDCAS, nSDRAS, nWE, nSDCS assert time nSDRAS to nSDCAS assert time nSDCAS to nSDCAS assert time MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise MD(31:0) read data input setup time from SDCLK(2:0) rise MD(31:0) read data input hold time from SDCLK(2:0) rise 10 1 1 2 3.8 20 ns, 2 sdclk sdclk sdclk ns, 3 tsynSDOH tsynSDIS tsynDIH 3.6 0.5 1.5 ns, 3 ns ns Fast Flash (Synchronous READS only) tffCLK tffAS tffCES tffADV tffOS tffCEH SDCLK period MA(25:0) setup to nSDCAS (as nADV) asserted nCS setup to nSDCAS (as nADV) asserted nSDCAS (as nADV) pulse width nSDCAS (as nADV) deassertion to nOE assertion nOE deassertion to nCS deassertion 15 0.5 0.5 1 3 4 20 ns, 4 sdclk sdclk sdclk sdclk sdclk NOTES: 1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK. 2. SDCLK for SDRAM, SMROM, and SDRAM-timing Synchronous Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5MHz at the fastest. 3. This number represents 1/2 SDCLK period. 4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz MEMCLK at its fastest. 4.8 Peripheral Module AC Specifications This section describes the AC Specifications for these peripheral units: • LCD • SSP 42 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 4.8.1 LCD Module AC Timing Figure 8 describes the LCD timing parameters. The LCD pin timing specifications are referenced to the pixel clock (L_PCLK). Values for the parameters are given in Table 21. Figure 8. LCD AC Timing Definitions L_PCLK Tpclkdv L_LDD[7:0] (rise) Tpclkdv L_LDD[7:0] (fall) L_LCLK Tpclklv Tpclkbv L_BIAS L_FCLK Tpclkfv A4775-01 Table 21. LCD AC Timing Specifications Symbol Tpclkdv Tpclklv Tpclkfv Tpclkbv Description L_PCLK rise/fall to L_LDD driven valid L_PCLK fall to L_LCLK driven valid L_PCLK fall to L_LFCLK driven valid L_PCLK rise to L_BIAS driven valid Min Max 14 14 14 14 Units ns ns ns ns Notes 1 2 2 2 NOTES: 1. You can program the LCD data pins to be driven on either the rising or falling edge of the pixel clock (L_PCLK). 2. These LCD signals can, at times, transition when L_PCLK is not clocking (between frames). At this time, they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK pin. 4.8.2 SSP Module AC Timing Figure 9, “SSP AC Timing Definitions” on page 44 describes the SSP timing parameters. The SSP pin timing specifications are referenced to SCLK_C. Values for the parameters are given in Table 22, “SSP AC Timing Specifications” on page 44. Datasheet 43 PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification Figure 9. SSP AC Timing Definitions SCLK_C Tsfmv SFRM_C Tsfmv TXD_C Trxds Trxdh RXD_C A4774-01 Table 22. SSP AC Timing Specifications Symbol Tsfmv Trxds Trxdh Tsfmv Description SCLK_C rise to SFRM_C driven valid RXD_C valid to SCLK_C fall (input setup) S CLK_C fall to RXD_C invalid (input hold) SCLK_C rise to TXD_C valid 11 0 22 Min Max 21 Units ns ns ns ns Notes 4.8.3 Boundary Scan Test Signal Timings Boundary scan test signal timing is shown in Table 23, “Boundary Scan Test Signal Timing”. Table 23. Boundary Scan Test Signal Timing (Sheet 1 of 2) Symbol TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSIS2 TBSIH2 TBSOV1 TOF1 TOV12 Parameter TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Input Setup to TCK TDI, TMS Input Hold from TCK TDI, TMS Input Setup to TCK nTRST Input Hold from TCK nTRST TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay 4.0 6.0 25.0 3.0 1.5 1.1 1.5 6.9 5.4 6.9 Min 0.0 15.0 15.0 5.0 5.0 Max 33.33 Units MHz ns ns ns ns ns ns ns ns ns ns ns Relative to falling edge of TCK Relative to falling edge of TCK Relative to falling edge of TCK Measured at 1.5 V Measured at 1.5 V 0.8 V to 2.0 V 2.0 V to 0.8 V Notes 44 Datasheet Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210 Table 23. Boundary Scan Test Signal Timing (Sheet 2 of 2) Symbol TOF2 TIS10 TIH8 Parameter All Outputs (Non-Test) Float Delay Input Setup to TCK All Inputs (Non-Test) Input Hold from TCK All Inputs (Non-Test) Min 1.1 4.0 6.0 Max 5.4 Units ns ns ns Notes Relative to falling edge of TCK 4.9 AC Test Conditions The AC specifications in Section 4.4, “Targeted AC Specifications” on page 32 are tested with a 50 pF load indicated in Figure 10. Figure 10. AC Test Load Output Ball CL = 50pF CL Datasheet 45