Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence
Datasheet
—on 65 nm Process in the 775-land LGA Package supporting Intel® 64 architecture and Intel® Virtualization Technology±
August 2007
Document Number: 315592-005
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Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details.
Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
±
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Intel, Pentium, Itanium, Xeon, Intel SpeedStep, andand the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.. *Other names and brands may be claimed as the property of others. Copyright © 2006–2007 Intel Corporation.
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Datasheet
Contents
1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Terminology ............................................................................ 10 1.2 References ....................................................................................................... 11 Electrical Specifications ........................................................................................... 13 2.1 Power and Ground Lands.................................................................................... 13 2.2 Decoupling Guidelines ........................................................................................ 13 2.2.1 VCC Decoupling ..................................................................................... 13 2.2.2 VTT Decoupling ...................................................................................... 13 2.2.3 FSB Decoupling...................................................................................... 14 2.3 Voltage Identification ......................................................................................... 14 2.4 Reserved, Unused, and TESTHI Signals ................................................................ 16 2.5 Voltage and Current Specification ........................................................................ 17 2.5.1 Absolute Maximum and Minimum Ratings .................................................. 17 2.5.2 DC Voltage and Current Specification ........................................................ 18 2.5.3 VCC Overshoot ...................................................................................... 21 2.5.4 Die Voltage Validation ............................................................................. 21 2.6 Signaling Specifications...................................................................................... 22 2.6.1 FSB Signal Groups.................................................................................. 22 2.6.2 CMOS and Open Drain Signals ................................................................. 24 2.6.3 Processor DC Specifications ..................................................................... 24 2.6.3.1 GTL+ Front Side Bus Specifications ............................................. 26 2.7 Clock Specifications ........................................................................................... 26 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 26 2.7.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 27 2.7.3 Phase Lock Loop (PLL) and Filter .............................................................. 27 2.7.4 BCLK[1:0] Specifications ......................................................................... 28 Package Mechanical Specifications .......................................................................... 31 3.1 Package Mechanical Drawing............................................................................... 31 3.2 Processor Component Keep-Out Zones ................................................................. 35 3.3 Package Loading Specifications ........................................................................... 35 3.4 Package Handling Guidelines............................................................................... 35 3.5 Package Insertion Specifications.......................................................................... 36 3.6 Processor Mass Specification ............................................................................... 36 3.7 Processor Materials............................................................................................ 36 3.8 Processor Markings............................................................................................ 36 3.9 Processor Land Coordinates ................................................................................ 38 Land Listing and Signal Descriptions ....................................................................... 39 4.1 Processor Land Assignments ............................................................................... 39 4.2 Alphabetical Signals Reference ............................................................................ 62 Thermal Specifications and Design Considerations .................................................. 71 5.1 Processor Thermal Specifications ......................................................................... 71 5.1.1 Thermal Specifications ............................................................................ 71 5.1.2 Thermal Metrology ................................................................................. 76 5.2 Processor Thermal Features ................................................................................ 76 5.2.1 Thermal Monitor..................................................................................... 76 5.2.2 Thermal Monitor 2 .................................................................................. 77 5.2.3 On-Demand Mode .................................................................................. 78 5.2.4 PROCHOT# Signal .................................................................................. 79
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5.3
5.2.5 THERMTRIP# Signal ................................................................................79 Platform Environment Control Interface (PECI) ......................................................80 5.3.1 Introduction ...........................................................................................80 5.3.1.1 TCONTROL and TCC Activation on PECI-Based Systems.....................80 5.3.2 PECI Specifications .................................................................................81 5.3.2.1 PECI Device Address..................................................................81 5.3.2.2 PECI Command Support .............................................................81 5.3.2.3 PECI Fault Handling Requirements ...............................................81 5.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support...................81
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Features ..................................................................................................................83 6.1 Power-On Configuration Options ..........................................................................83 6.2 Clock Control and Low Power States .....................................................................83 6.2.1 Normal State .........................................................................................84 6.2.2 HALT and Extended HALT Powerdown States ..............................................84 6.2.2.1 HALT Powerdown State ..............................................................84 6.2.2.2 Extended HALT Powerdown State ................................................85 6.2.3 Stop Grant State ....................................................................................85 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State...........................................................................86 6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................86 6.2.4.2 Extended HALT Snoop State .......................................................86 Boxed Processor Specifications ................................................................................87 7.1 Mechanical Specifications ....................................................................................88 7.1.1 Boxed Processor Cooling Solution Dimensions.............................................88 7.1.2 Boxed Processor Fan Heatsink Weight .......................................................90 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....90 7.2 Electrical Requirements ......................................................................................90 7.2.1 Fan Heatsink Power Supply ......................................................................90 7.3 Thermal Specifications........................................................................................92 7.3.1 Boxed Processor Cooling Requirements......................................................92 7.3.2 Fan Speed Control Operation (Intel® Core™2 Extreme processors only) .........94 7.3.3 Fan Speed Control Operation (Intel® Core™2 Quad processor) .....................94 Debug Tools Specifications ......................................................................................97 8.1 Logic Analyzer Interface (LAI) .............................................................................97 8.1.1 Mechanical Considerations .......................................................................97 8.1.2 Electrical Considerations ..........................................................................97
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Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VCC Static and Transient Tolerance ............................................................................. 20 VCC Overshoot Example Waveform ............................................................................. 21 Differential Clock Waveform ...................................................................................... 29 Differential Clock Crosspoint Specification ................................................................... 30 Differential Measurements......................................................................................... 30 Processor Package Assembly Sketch ........................................................................... 31 Processor Package Drawing Sheet 1 of 3 ..................................................................... 32 Processor Package Drawing Sheet 2 of 3 ..................................................................... 33 Processor Package Drawing Sheet 3 of 3 ..................................................................... 34 Processor Top-Side Markings Example for 1066 MHz Processors ..................................... 36 Processor Top-Side Markings Example for 1333 MHz Processors ..................................... 37 Processor Land Coordinates and Quadrants (Top View) ................................................. 38 land-out Diagram (Top View – Left Side) ..................................................................... 40 land-out Diagram (Top View – Right Side) ................................................................... 41 Thermal Profile for 130 W Processors .......................................................................... 73 Thermal Profile for 105 W Processors .......................................................................... 74 Thermal Profile 95 W Processors ................................................................................ 75 Case Temperature (TC) Measurement Location ............................................................ 76 Thermal Monitor 2 Frequency and Voltage Ordering ...................................................... 78 Conceptual Fan Control on PECI-Based Platforms ......................................................... 80 Processor Low Power State Machine ........................................................................... 84 Mechanical Representation of the Boxed Processor ....................................................... 87 Space Requirements for the Boxed Processor (Side View).............................................. 88 Space Requirements for the Boxed Processor (Top View)............................................... 89 Space Requirements for the Boxed Processor (Overall View) .......................................... 89 Boxed Processor Fan Heatsink Power Cable Connector Description .................................. 91 Baseboard Power Header Placement Relative to Processor Socket ................................... 92 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)................... 93 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................... 93 Boxed Processor Fan Heatsink Set Points..................................................................... 95
Datasheet
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Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 References ..............................................................................................................11 Voltage Identification Definition ..................................................................................15 Absolute Maximum and Minimum Ratings ....................................................................17 Voltage and Current Specifications..............................................................................18 VCC Static and Transient Tolerance .............................................................................19 VCC Overshoot Specifications......................................................................................21 FSB Signal Groups ....................................................................................................22 Signal Characteristics................................................................................................23 Signal Reference Voltages .........................................................................................23 GTL+ Signal Group DC Specifications ..........................................................................24 Open Drain and TAP Output Signal Group DC Specifications ...........................................24 CMOS Signal Group DC Specifications..........................................................................25 PECI DC Electrical Limits ...........................................................................................25 GTL+ Bus Voltage Definitions .....................................................................................26 Core Frequency to FSB Multiplier Configuration.............................................................26 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................27 Front Side Bus Differential BCLK Specifications .............................................................28 FSB Differential Clock Specifications (1066 MHz FSB) ....................................................28 FSB Differential Clock Specifications (1333 MHz FSB) ....................................................29 Processor Loading Specifications.................................................................................35 Package Handling Guidelines......................................................................................35 Processor Materials ...................................................................................................36 Alphabetical Land Assignments...................................................................................42 Numerical Land Assignment .......................................................................................52 Signal Description.....................................................................................................62 Processor Thermal Specifications ................................................................................72 Thermal Profile for 130 W Processors ..........................................................................73 Thermal Profile for 105 W Processors ..........................................................................74 Thermal Profile 95 W Processors .................................................................................75 GetTemp0() and GetTemp1() Error Codes....................................................................81 Power-On Configuration Option Signals .......................................................................83 Fan Heatsink Power and Signal Specifications ...............................................................91 Fan Heatsink Power and Signal Specifications ...............................................................95
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Datasheet
Revision History
Revision Number -001 • • • • • • • • • Initial release
Description
Date November 2006
-002
Added specifications for the Intel Core™2 Quad Processor Q6600 Updated Table 8, “Signal Characteristics”. Updated VTT_SEL description in Table 24. Updated Table 29, “Fan Heatsink Power and Signal Specifications”. Added specifications for the Intel® Core™2 Quad Processor Q6700 and Intel® Core™2 Extreme quad-core processor QX6850 Added Intel® Core™2 Quad Processor Q6600 for 775_VR_CONFIG_05A Added Intel
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®
January 2007
-003 -003 -004 -005
July 2007 July 2007 July 2007 August 2007
Core™2 Extreme quad-core processor QX6850
Added Intel® Core™2 Extreme quad-core processor QX6800
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Datasheet
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Intel® Core™2 Extreme Quad-Core Processor QX6000 and Intel® Core™2 Quad Processor Q6000 Sequence Features
• Available at 3.00 GHz (Intel® Core™2 Extreme Quad-Core Processor QX6850 only) • Available at 2.66 GHz (Intel® Core™2 Extreme Quad-Core Processor QX6700 and Intel® Core™2 Quad Processor Q6700 only) • Available at 2.40 GHz (Intel® Core™2 Quad Processor Q6600 only) • Available at 2.93 GHz (Intel® Core™2 Extreme Quad-Core Processor QX6800 only) • Enhanced Intel Speedstep® Technology • Supports Intel® 64Φ architecture • Supports Intel® Virtualization Technology • Supports Execute Disable Bit capability • FSB frequency at 1066 MHz (Intel® Core™2 Extreme Quad-Core Processor QX6700, QX6800 and Intel® Core™2 Quad Processor Q6700 and Q6600 only) • FSB frequency at 1333 MHz (Intel® Core™2 Extreme Quad-Core Processor QX6850 only) • Binary compatible with applications running on previous members of the Intel microprocessor line • Advance Dynamic Execution • Very deep out-of-order execution • Enhanced branch prediction • Optimized for 32-bit applications running on advanced 32-bit operating systems • Four 32-KB Level 1 data caches • Two 4 MB Level 2 caches • Intel® Advanced Digital Media Boost • Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance • Power Management capabilities • System Management mode • Multiple low-power states • 8-way cache associativity provides improved cache hit rate on load/store operations • 775-land Package
The Intel Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments. Intel® 64Φ architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep® technology, allows tradeoffs to be made between performance and power consumption. The Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. The Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence support Intel® Virtualization Technology. Virtualization Technology provides siliconbased functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve on software-only solutions.
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Datasheet
Introduction
1
Introduction
The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence are the first desktop quad-core processors that combine the performance and power efficiencies of four low-power microarchitecture cores to enable a new level of multi-tasking, multi-media, and gaming experiences. They are 64-bit processors that maintain compatibility with IA-32 software. The processors use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plug into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket. The processors are based on 65 nm process technology.
Note:
In this document the Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence are referred to simply as “processor.” In this document the Intel® Core™2 quad-core processor Q6000 sequence refers to the Intel® Core™2 quad processor Q6600 and Q6700. The Intel® Core™2 Extreme quadcore processor QX6000 sequence refers to the Intel® Core™2 Extreme quad-core processors QX6700, QX6800, and QX6850. The processor supports all the existing Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). The processor supports several advanced technologies including Execute Disable Bit, Intel® 64 architecture, and Intel® Virtualization Technology (VT). The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel® Pentium® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "doubleclocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s. The processor uses some of the infrastructure already enabled by the 775_VR_CONFIG_05 platforms including heatsink, heatsink retention mechanism, and socket. Supported platforms may need to be refreshed to ensure the correct voltage regulation (VRD11) and PECI support is enabled. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. The processor includes an address bus power-down capability that removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.
Note:
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Datasheet
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Introduction
“Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.
1.1.1
Processor Terminology
Commonly used terms are explained here for clarification: • Intel® Core™2 Extreme quad-core processor QX6000 sequence — Quad core processor in the FC-LGA6 package with a 2x4 MB L2 cache. • Intel® Core™2 quad processor Q6000 sequence — Quad core processor in the FC-LGA6 package with a 2x4 MB L2 cache. • Processor — For this document, the term processor is the generic form of the Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence. The processor is a single package that contains one or more execution units. • Keep-out zone — The area on or near the processor that system design can not utilize. • Processor core — Processor core die with integrated L2 cache. • LGA775 socket — The processor mates with the system board through a surface mount, 775-land, LGA socket. • Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. • Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket. • FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. • Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. • Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied. • Execute Disable Bit — The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel® Architecture Software Developer's Manual for more detailed information. • Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http://www.intel.com/technology/intel64/index.htm.
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Introduction
• Enhanced Intel Technology SpeedStep® Technology — Enhanced Intel Technology SpeedStep® Technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support). • Intel® Virtualization Technology (Intel® VT) — Intel Virtualization Technology provides silicon-based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve upon software-only solutions. Because this virtualization hardware provides a new architecture upon which the operating system can run directly, it removes the need for binary translation. Thus, it helps eliminate associated performance overhead and vastly simplifies the design of the VMM, in turn allowing VMMs to be written to common standards and to be more robust. See the Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture for more details.
1.2
References
Material and concepts available in the following documents may be beneficial when reading this document.
Table 1.
References
Document Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update Intel® Core™2 Extreme Quad-Core Processor and Intel® Core™2 Quad Processor Thermal and Mechanical Design Guidelines Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket Balanced Technology Extended (BTX) System Design Guide Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture LGA775 Socket Mechanical Design Guide Intel® 64 and IA-32 Architecture Software Developer’s Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ Intel® Location http://www.intel.com/design/ processor/specupdt/ 315593.htm http://www.intel.com/design/ processor/designex/ 315594.htm http://www.intel.com/design/ processor/applnots/ 313214.htm www.formfactors.org http://www.intel.com/ technology/computing/ vptech/index.htm http://intel.com/design/ Pentium4/guides/ 302666.htm
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Introduction
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Datasheet
Electrical Specifications
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Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.
2.1
Power and Ground Lands
The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands. The signals are denoted as VTT, which provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 4.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4. Failure to do so can result in timing violations or reduced lifetime of the component.
2.2.1
VCC Decoupling
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket.
2.2.2
VTT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.
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Electrical Specifications
2.2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins (see Chapter 2.5.3 for VCC overshoot specifications). Refer to Table 12 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 4. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 4. Refer to the Intel® Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT State). The processor uses six voltage identification signals, VID[7:0], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 are strapped to VSS on the processor package. VID0 and VID7 must be connected to the VR controller for compatibility with future processors. The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 4 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 5 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands. The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 4 and Table 5. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further details.
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Electrical Specifications
Table 2.
Voltage Identification Definition
VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 OFF
VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250
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Electrical Specifications
2.4
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands. In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 7 for details on GTL+ signals that do not include on-die termination. Unused active high inputs, should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (RTT). For details see Table 14. TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. All TESTHI[13,11:10,7:0] lands should be individually connected to VTT via a pull-up resistor which matches the nominal trace impedance. The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group: • TESTHI[1:0] • TESTHI[7:2] • TESTHI10 – cannot be grouped with other TESTHI signals • TESTHI11 – cannot be grouped with other TESTHI signals • TESTHI13 – cannot be grouped with other TESTHI signals However, use of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13,11:10,7:0] lands should have a resistance value within ±20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.
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2.5
2.5.1
Voltage and Current Specification
Absolute Maximum and Minimum Ratings
Table 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.
Table 3.
Absolute Maximum and Minimum Ratings
Symbol VCC VTT TC TSTORAGE NOTES: Parameter Core voltage with respect to VSS FSB termination voltage with respect to VSS Processor case temperature Processor storage temperature Min –0.3 –0.3 See Chapter 5 –40 Max 1.55 1.55 See Chapter 5 85 Unit V V °C °C Notes1,2 3, 4, 5
1. For functional operation, all processor electrical, signal quality, mechanical and thermal 2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the 3. Storage temperature is applicable to storage conditions only. In this scenario, the processor
specifications must be satisfied. processor.
must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, Refer to the processor case temperature specifications. 4. This rating applies to the processor and does not include any tray or packaging. 5. Failure to adhere to this specification can affect the long term reliability of the processor.
Datasheet
17
Electrical Specifications
2.5.2
Table 4.
Symbol VID Range
DC Voltage and Current Specification
Voltage and Current Specifications
Parameter VID Processor Number QX6850 VCC for 775_VR_CONFIG_05 3.00 GHz 2.93 GHz 2.66 GHz 2.66 GHz 2.40 GHz — - 5% ICC for 775_VR_CONFIG_05B 3.00 GHz 2.93 GHz 2.66 GHz 2.40 GHz ICC for 775_VR_CONFIG_05A 2.66 GHz 2.40 GHz — 1.14 — 1.20 115 115 ICC 1.26 A V
10 11, 12
Min 0.8500
Typ —
Max 1.5
Unit V
Notes1,
3
2
VCC
QX6800 QX6700 Q6700 Q6600
Refer to Table 5 and Figure 1
V
4, 5, 6
VCC_BOOT VCCPLL
Default VCC voltage for initial power up PLL VCC Processor Number QX6850 QX6800 QX6700 Q66007 Processor Number Q6700 Q66009
1.10 1.50
— + 5%
V
—
—
125 125 125 115
A
8
ICC
8
ITCC VTT VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT ICC_VCCPLL ICC_GTLREF
ICC TCC active FSB termination voltage (DC + AC specifications) DC Current that may be drawn from VTT_OUT_LEFT and VTT_OUT_RIGHT per pin ICC for VTT supply before VCC stable ICC for VTT supply after VCC stable ICC for PLL land ICC for GTLREF
—
—
580 8.0 7.0 130 200
mA
— — —
— — -—
A mA μA
13
NOTES: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. 3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT State). 4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information. 5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. 6. Refer to Table 5 and Figure 1 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. 7. These processors have CPUID = 06F7h
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8. ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1 for details. 10. The maximum instantaneous current the processor will draw while the thermal control circuit is active (as 11. VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured 12. Baseboard bandwidth is limited to 20 MHz.
9. These Processors have CPUID = 06FBh
indicated by the assertion of PROCHOT#) is the same as the maximum ICC for the processor.
at the land.
13.This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested.
Table 5.
VCC Static and Transient Tolerance
Voltage Deviation from VID Setting (V)1, ICC (A) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 78 85 90 95 100 105 110 115 120 125 NOTES: Maximum Voltage 1.30 mΩ 0.000 -0.007 -0.013 -0.020 -0.026 -0.033 -0.039 -0.046 -0.052 -0.059 -0.065 -0.072 -0.078 -0.085 -0.091 -0.098 -0.101 -0.111 -0.117 -0.124 -0.130 -0.137 -0.143 -0.150 -0.156 -0.163 Typical Voltage 1.38 mΩ -0.019 -0.026 -0.033 -0.040 -0.047 -0.053 -0.060 -0.067 -0.074 -0.081 -0.088 -0.095 -0.102 -0.108 -0.115 -0.122 -0.126 -0.136 -0.143 -0.150 -0.157 -0.163 -0.170 -0.177 -0.184 -0.191
2, 3, 4
Minimum Voltage 1.45 mΩ -0.038 -0.045 -0.053 -0.060 -0.067 -0.074 -0.082 -0.089 -0.096 -0.103 -0.111 -0.118 -0.125 -0.132 -0.140 -0.147 -0.151 -0.161 -0.169 -0.176 -0.183 -0.190 -0.198 -0.205 -0.212 -0.219
1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.5.3. 2. This table is intended to aid in reading discrete points on Figure 1. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE
lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification is required to ensure reliable processor operation.
Datasheet
19
Electrical Specifications
Figure 1.
VCC Static and Transient Tolerance
Icc [A] 0 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 VID - 0.100 Vcc [V] Vcc Typical VID - 0.113 VID - 0.125 VID - 0.138 VID - 0.150 VID - 0.163 VID - 0.175 VID - 0.188 VID - 0.200 VID - 0.213 VID - 0.225 Vcc Minimum Vcc Maximum 10 20 30 40 50 60 70 80 90 100 110 120
NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.5.3. 2. This loadline specification shows the deviation from the VID set point. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.
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2.5.3
VCC Overshoot
The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 6.
VCC Overshoot Specifications
Symbol VOS_MAX TOS_MAX Parameter Magnitude of VCC overshoot above VID Time duration of VCC overshoot above VID Min — — Max 50 25 Unit mV μs Figure 2 2 Notes
1 1
NOTES: 1. Adherence to these specifications is required to ensure reliable processor operation.
Figure 2.
VCC Overshoot Example Waveform
Example Overshoot Waveform
VID + 0.050
VOS
Voltage [V]
VID - 0.000
TOS
0 5 10 15 20 25
Time [us]
TOS: Overshoot time above VID VOS: Overshoot above VID
NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID.
2.5.4
Die Voltage Validation
Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit.
Datasheet
21
Electrical Specifications
2.6
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families. The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.
2.6.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[3:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 7 identifies which signals are common clock, source synchronous, and asynchronous.
Table 7.
FSB Signal Groups (Sheet 1 of 2)
Signal Group GTL+ Common Clock Input GTL+ Common Clock I/O Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK# Signals REQ[4:0]#, A[16:3]# GTL+ Source Synchronous I/O Synchronous to assoc. strobe A[35:17]#
3 3
Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
GTL+ Strobes
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
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Table 7.
FSB Signal Groups (Sheet 2 of 2)
Signal Group CMOS Open Drain Output Open Drain Input/Output FSB Clock Clock Type Signals1 A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:], VID[7:0] FERR#/PBE#, IERR#, THERMTRIP#, TDO PROCHOT#4 BCLK[1:0], ITP_CLK[1:0]2 VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[3:0], COMP[8,3:0], RESERVED, TESTHI[13,11:10,7:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Power/Other
NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details. 4. PROCHOT# signal type is open drain output and CMOS input.
.
Table 8.
Signal Characteristics
Signals with RTT A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY# Open Drain Signals1 THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BPMb[3:0]#, BR0#, TDO, FCx
1. Signals that do not have RTT, nor are actively driven to their high-voltage level.
Signals with No RTT A20M#, BCLK[1:0], BSEL[2:0], COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SMI#, STPCLK#, TESTHI[13,11:10,7:0], VID[7:0], GTLREF[3:0], TCK, TDI, TMS, TRST#, MSID[1:0], VTT_SEL
NOTES:
.
Table 9.
Signal Reference Voltages
GTLREF BPM[5:0]#, BPMb[3:0]#, RESET#, BNR#, HIT#, HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY# NOTES: VTT/2 A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1, TMS1, TRST#1
1. These signals also have hysteresis added to the reference voltage. See Table 11 for more
information.
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Electrical Specifications
2.6.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/ deasserted for at least four BCLKs for the processor to recognize the proper signal state. See Section 2.6.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states.
2.6.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.
Table 10.
GTL+ Signal Group DC Specifications
Symbol VIL VIH VOH IOL ILI ILO RON Parameter Input Low Voltage Input High Voltage Output High Voltage Output Low Current Input Leakage Current Output Leakage Current Buffer On Resistance Min -0.10 GTLREF + 0.10 VTT – 0.10 N/A N/A N/A 10 Max GTLREF – 0.10 VTT + 0.10 VTT VTT_MAX/ [(RTT_MIN)+(2*RON_MIN)] ± 200 ± 200 13 Unit V V V A µA µA Ω Notes1
2, 3 3, 4, 5 3, 5
6 7
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. The VTT referred to in these specifications is the instantaneous VTT. 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VTT. 6. Leakage to VSS with land held at VTT. 7. Leakage to VTT with land held at 300 mV.
Table 11.
Open Drain and TAP Output Signal Group DC Specifications
Symbol VOL VOH IOL ILO
1. 2. 3. 4.
Parameter Output Low Voltage Output High Voltage Output Low Current Output Leakage Current
Min 0 VTT – 0.05 16 N/A
Max 0.20 VTT + 0.05 50 ± 200
Unit V V mA µA
Notes1 2 3 4
NOTES: Unless otherwise noted, all specifications in this table apply to all processor frequencies. Measured at VTT * 0.2. For Vin between 0 and VOH.
VOH is determined by the value of the external pull-up resister to VTT.
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Table 12.
CMOS Signal Group DC Specifications
Symbol VIL VIH VOL VOH IOL IOH ILI ILO NOTES: Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Input Leakage Current Output Leakage Current Min -0.10 VTT * 0.70 -0.10 0.90 * VTT 1.70 1.70 N/A N/A Max VTT * 0.30 VTT + 0.10 VTT * 0.10 VTT + 0.10 4.70 4.70 ± 100 ± 100 Unit V V V V mA mA µA µA Notes1
2, 3 3, 4, 5 3 3, 5,6 3, 7 3, 7 8 9
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low 3. The VTT referred to in these specifications refers to instantaneous VTT. 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high 5. 6. 7. 8. 9.
value.
value. VIH and VOH may experience excursions above VTT. All outputs are open drain. IOL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT. Leakage to VSS with land held at VTT. Leakage to VTT with land held at 300 mV
Table 13.
PECI DC Electrical Limits
Symbol Vin Vhysteresis Vn Vp Isource Isink Ileak+ IleakCbus Vnoise Definition and Conditions Input Voltage Range Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source (VOH = 0.75 * VTT) Low level output sink (VOL = 0.25 * VTT) High impedance state leakage to VTT High impedance leakage to GND Bus capacitance Signal noise immunity above 300 MHz Min -0.30 0.1 * VTT 0.275 * VTT 0.550 * VTT -6.0 0.5 N/A N/A — 0.1 * VTT Max VTT — 0.500 * VTT 0.725 * VTT N/A 1.0 50 10 10 — Units V V V V mA mA µA µA pF Vp-p 2 2 3 Notes
NOTE: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer to Table 4 for VTT specifications. 2. The leakage specification applies to powered devices on the PECI bus. 3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
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25
Electrical Specifications
2.6.3.1
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits.
Table 14.
GTL+ Bus Voltage Definitions
Symbol GTLREF_PU GTLREF_PD RTT COMP[3:0] COMP8 NOTES: Parameter GTLREF pull-up resistor GTLREF pull-down resistor Termination Resistance COMP Resistance COMP Resistance Min 124 * 0.99 210 * 0.99 45 49.40 24.65 Typ 124 210 50 49.90 24.90 Max 124 * 1.01 210 * 1.01 55 50.40 25.15 Units Ω Ω Ω Ω Ω Notes1
2 2 3 4 4
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLEREF land). Refer to the applicable platform design guide for implementation details. 3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver. 4. COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and
COMP8 resistors are to VSS.
2.7
2.7.1
Clock Specifications
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative.
Table 15.
Core Frequency to FSB Multiplier Configuration
Multiplication of System Core Frequency to FSB Frequency 1/6 1/7 1/8 1/9 1/10 1/11 1/12 NOTES: Core Frequency (266 MHz BCLK/ 1066 MHz FSB) 1.60 GHz 1.87 GHz 2.13 GHz 2.40 GHz 2.66 GHz 2.93 GHz 3.20 GHz Core Frequency (333 MHz BCLK/ 1333 MHz FSB) 2.00 GHz 2.33 GHz 2.66 GHz 3.00 GHz 3.33 GHz 3.66 GHz 4.00 GHz Notes1, 2
1. Individual processors operate only at or below the rated frequency. 2. Listed frequencies are not necessarily committed production frequencies.
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2.7.2
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Intel® Core™2 Extreme Quad-Core processor QX6800, QX6700 and Intel® Core™2 Quad processors Q6600 and Q6700 operate at a 1066 MHz FSB frequency (selected by a 266 MHz BCLK[1:0] frequency). The Intel® Core™2 Extreme Quad-Core processor QX6850 operates at 1333 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency.
Table 16.
BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2 L L L L H H H H BSEL1 L L H H H H L L BSEL0 L H H L L H H L FSB Frequency 266 MHz RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 333 MHz
2.7.3
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 4 for DC specifications.
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27
Electrical Specifications
2.7.4
Table 17.
BCLK[1:0] Specifications
Front Side Bus Differential BCLK Specifications
Symbol VL VH VCROSS(abs) ΔVCROSS VOS VUS VSWING NOTES: Parameter Input Low Voltage Input High Voltage Absolute Crossing Point Range of Crossing Points Overshoot Undershoot Differential Output Swing Min -0.30 N/A 0.300 N/A N/A -0.300 0.300 Typ N/A N/A N/A N/A N/A N/A N/A Max N/A 1.15 0.550 0.140 1.4 N/A N/A Unit V V V V V V V Figure 3 3 3, 4 3, 4 3 3 5 Notes1
2 2 3, 4, 5
6 6 7
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. "Steady state" voltage, not including overshoot or undershoot. 3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 4. The
equals the falling edge of BCLK1. crossing point must meet the absolute and relative crossing point specifications simultaneously 5. VHavg is the statistical average of the VH measured by the oscilloscope. 6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage. 7. Measurement taken from differential waveform.
.
Table 18.
FSB Differential Clock Specifications (1066 MHz FSB)
T# Parameter BCLK[1:0] Frequency T1: BCLK[1:0] Period T2: BCLK[1:0] Period Stability T5: BCLK[1:0] Rise and Fall Slew Rate T6: Slew Rate Matching NOTES: Min 265.307 3.74963 — 2.5 N/A Nom — — — — N/A Max 266.746 3.76922 150 8 20 Unit MHz ns ps V/nS % 3 3 5 Figure Notes1
2 3 4 5 6
1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies 2. Duty Cycle (High time/Period) must be between 40 and 60%. 3. The period specified here is the average period. A given period may vary from this specification
based on a 266 MHz BCLK[1:0].
as governed by the period stability specification (T2). Min period specification is based on -300 PPM deviation from a 3.75 ns period. Max period specification is based on the summation of +300 PPM deviation from a 3.75 ns period and a +0.5% maximum variance due to spread spectrum clocking. 4. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 5. Measurement taken from differential waveform. 6. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
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Datasheet
Electrical Specifications
Table 19.
FSB Differential Clock Specifications (1333 MHz FSB)
T# Parameter BCLK[1:0] Frequency T1: BCLK[1:0] Period T2: BCLK[1:0] Period Stability T5: BCLK[1:0] Rise and Fall Slew Rate T6: Slew Rate Matching NOTES: Min 331.635 2.99972 — 2.5 N/A Nom — — — — N/A Max 333.364 3.01536 150 8 20 Unit MHz ns ps V/nS % Figure 3 3 5 Notes1
2 3 4, 5 6 7
1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies 2. Duty Cycle (High time/Period) must be between 40 and 60%. 3. The period specified here is the average period. A given period may vary from this specification
based on a 333 MHz BCLK[1:0].
4. 5. 6. 7.
as governed by the period stability specification (T2). Min period specification is based on -300 PPM deviation from a 3 ns period. Max period specification is based on the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance due to spread spectrum clocking. For the clock jitter specification, refer to the CK505 Clock Synthesizer/Driver Specification. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. Measurement taken from differential waveform. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Slew rate matching is a single ended measurement.
Figure 3.
Differential Clock Waveform
CLK 0
VCROSS median VCROSS CLK 1
CROSS Median + 75 mV
V
VCROSS Max 500 mV
VCROSS
VCROSS Min 300 mV High Time Period Low Time
median
Median - 75 mV
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29
Electrical Specifications
Figure 4.
Differential Clock Crosspoint Specification
650 600
Crossing Point (mV)
550 500 450 400 350 300 250 200
550 mV 550 + 0.5 (VHavg - 700)
300 + 0.5 (VHavg - 700)
300 mV
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Figure 5.
Differential Measurements
Sl ew_ ris e +150 mV 0.0 V -150 mV V_swin g
Slew _fal l +1 50 mV 0.0 V - 150 mV
D iff
§§
30
Datasheet
Package Mechanical Specifications
3
Package Mechanical Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 6 shows a sketch of the processor package components and how they are assembled together. Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket. The package components shown in Figure 6 include the following: • Integrated Heat Spreader (IHS) • Thermal Interface Material (TIM) • Processor core (die) • Package substrate • Capacitors
Figure 6.
Processor Package Assembly Sketch
Core (die) IHS Substrate TIM
Capacitors LGA775 Socket System Board
NOTE: 1. Socket and motherboard are included for reference and are not part of processor package.
3.1
Package Mechanical Drawing
The package mechanical drawings are shown in Figure 7 and Figure 8. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: • Package reference with tolerances (total height, length, width, etc.) • IHS parallelism and tilt • Land dimensions • Top-side and back-side component keep-out dimensions • Reference datums • All drawing dimensions are in mm [in]. • Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines.
Datasheet
31
Package Mechanical Specifications
Figure 7.
Processor Package Drawing Sheet 1 of 3
32
Datasheet
Package Mechanical Specifications
Figure 8.
Processor Package Drawing Sheet 2 of 3
Datasheet
33
Package Mechanical Specifications
Figure 9.
Processor Package Drawing Sheet 3 of 3
34
Datasheet
Package Mechanical Specifications
3.2
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 7 and Figure 8 for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.
3.3
Package Loading Specifications
Table 20 provides dynamic and static load specifications for the processor package. These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions.
.
Table 20.
Processor Loading Specifications
Parameter Static Dynamic NOTES: Minimum 80 N [17 lbf] — Maximum 311 N [70 lbf] 756 N [170 lbf] Notes
1, 2, 3 1, 3, 4
1. These specifications apply to uniform compressive loading in a direction normal to the 2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also 3. These specifications are based on limited testing for design characterization. Loading limits are 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
processor IHS.
provide the minimum specified load on the processor package.
for the package only and do not include the limits of the processor socket. requirement.
3.4
Package Handling Guidelines
Table 21 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.
Table 21.
Package Handling Guidelines
Parameter Shear Tensile Torque NOTES: Maximum Recommended 311 N [70 lbf] 111 N [25 lbf] 3.95 N-m [35 lbf-in] Notes
1, 2 2, 3 2, 4
1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface. 2. These guidelines are based on limited testing for design characterization. 3. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS 4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the
surface.
IHS top surface.
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35
Package Mechanical Specifications
3.5
Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide.
3.6
Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package.
3.7
Table 22.
Processor Materials
Table 22 lists some of the package components and associated materials. Processor Materials
Component Integrated Heat Spreader (IHS) Substrate Substrate Lands Material Nickel Plated Copper Fiber Reinforced Resin Gold Plated Copper
3.8
Processor Markings
Figure 10 shows the topside markings on the processor. This diagram is to aid in the identification of the processor.
Figure 10.
Processor Top-Side Markings Example for 1066 MHz Processors
INTEL M ©'05 QX6700 INTEL® CORE™2 EXTREME SLxxx [COO] 2.66GHZ/8M/1066/05B [FPO] e4
ATPO S/N
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Datasheet
Package Mechanical Specifications
Figure 11.
Processor Top-Side Markings Example for 1333 MHz Processors
INTEL M ©'05 QX6850 INTEL® CORE™2 EXTREME SLxxx [COO] 3.00GHZ/8M/1333/05B [FPO] e4
ATPO S/N
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37
Package Mechanical Specifications
3.9
.
Processor Land Coordinates
Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands.
Figure 12.
Processor Land Coordinates and Quadrants (Top View)
VCC / VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
Preliminary Socket 775 Quadrants Top View
Address/ Common Clock/ Async
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VTT / Clocks
Data
§§
38
Datasheet
Land Listing and Signal Descriptions
4
Land Listing and Signal Descriptions
This chapter provides the processor land assignment and signal descriptions.
4.1
Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown in Figure 13 and Figure 14. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 is a listing of all processor lands ordered alphabetically by land (signal) name. Table 24 is also a listing of all processor lands; the ordering is by land number.
Datasheet
39
Land Listing and Signal Descriptions
Figure 13.
30 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A VTT VTT VTT VTT 30 VCC VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC BSEL1 BSEL2
land-out Diagram (Top View – Left Side)
29 VCC VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC FC15 BSEL0 RSVD FC26 VTT VTT VTT VTT 29 28 VSS VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS BCLK1 27 VSS VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS 26 VCC VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS 25 VCC VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS 24 VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS 23 VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VSS D47# VSS D45# D46# VSS D63# D62# 22 VCC VSS D44# D43# D42# VSS D58# D59# VSS 21 VCC VSS VCC VSS VCC VSS D35# D38# D39# VSS D54# D57# VSS 18 FC34 VSS D36# D37# VSS D49# DSTBP3# VSS D56# 17 FC31 FC33 D32# VSS D34# RSVD VSS D55# DSTBN3# 16 VCC FC32 D31# D30# D33# VSS D51# D53# VSS 15 22 VCC VCC VCC VCC VCC VCC VCC VCC VCC 21 VCC VCC VCC VCC VCC VCC VCC VCC VCC 20 VSS VSS VSS VSS VSS VSS VSS VSS VSS 19 VCC VCC VCC VCC VCC VCC VCC VCC VCC 18 VCC VCC VCC VCC VCC VCC VCC VCC VCC 17 VSS VSS VSS VSS VSS VSS VSS VSS VSS 16 VSS VSS VSS VSS VSS VSS VSS VSS VSS 15 VCC VCC VCC VCC VCC VCC VCC VCC VCC
TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# RSVD RSVD VCCPLL VCCIO PLL VSSA VCCA 23
DSTBN2# DSTBP2# D41# VSS D48# DBI3# VSS RSVD 20 VSS D40# DBI2# VSS D60# D61# 19
BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 VSS VTT VTT VTT VTT 28 VSS VTT VTT VTT VTT 27 VSS VTT VTT VTT VTT 26 VSS VTT VTT VTT VTT 25 FC10 VSS VSS VSS FC23 24
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Datasheet
Land Listing and Signal Descriptions
Figure 14.
14 VCC VCC VCC VCC VCC VCC VCC VCC VCC 13 VSS VSS VSS VSS VSS VSS VSS VSS VSS
land-out Diagram (Top View – Right Side)
12 VCC VCC VCC VCC VCC VCC VCC VCC VCC 11 VCC VCC VCC VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS 9 VCC VCC VCC VCC VCC VCC VCC VCC VCC 8 VCC VCC VCC VCC VCC VCC VCC VCC SKTOCC# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 7 6 5 4 VSS_ SENSE VSS VID5 VID4 VSS A32# A30# A28# RSVD VSS RSVD A26# A21# A20# VSS A15# A13# A11# A8# VSS RSVD A7# A6# REQ0# VSS FC35 BPMb2# VSS HITM# HIT# VSS D0# D2# 4 3 VCC_ SENSE VID2 2 VSS VID0 1 VSS VSS FC25 FC24 BPM1# VSS TRST# TDO TCK TDI TMS VSS VTT_OUT_ RIGHT FC0 MSID0 MSID1 TDO_M COMP1 COMP3 TESTHI11 PWRGOOD VSS LINT1 LINT0 VTT_OUT_ LEFT GTLREF0 BPMb0# AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H VID_SEL VSS_MB_ VCC_MB_ ECT REGULATION REGULATION VID7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DEFER# VSS RSVD D20# VSS D6# D7# 7 FC40 VID3 FC8 A35# VSS A29# VSS RSVD A22# VSS A17# VSS A19# A18# VSS A10# VSS ADSTB0# A4# VSS REQ2# VSS REQ3# REQ4# VSS RSVD FC21 RSVD VSS D3# D5# VSS 6 VID6 VID1 VSS A34# A33# A31# A27# VSS ADSTB1# A25# A24# A23# VSS A16# A14# A12# A9# VSS RSVD RSVD A5# A3# VSS REQ1# TESTHI10 PECI RS1# FC20 VSS D1# VSS D4# 5
VRDSEL PROCHOT# ITP_CLK0 ITP_CLK1 VSS BPM5# VSS FC18 FC36 VSS FC37 VSS FC17 TESTHI1 VSS FC30 VSS FERR#/ PBE# INIT# VSS STPCLK# VSS A20M# FC22 VSS BPMb3# BR0# TRDY# VSS LOCK# RS0# RS2# 3 VSS BPM0# RSVD BPM3# BPM4# VSS BPM2# DBR# IERR# FC39 VSS TDI_M RSVD FC29 FC4 VSS SMI# IGNNE# THERMTRI P# TESTHI13 VSS FC3 GTLREF1 COMP2 GTLREF3 VSS ADS# BNR# DBSY# VSS 2
VCC VSS D29# D28# VSS RSVD D52# VSS D50# 14
VCC VSS D27# VSS D26# D25# VSS COMP8 COMP0 13
VCC VSS DSTBN1# D24# DSTBP1# VSS D14# D13# VSS 12
VCC VSS DBI1# D23# VSS D15# D11# VSS D9# 11
VCC VSS GTLRE F2 VSS D21# D22# VSS D10# D8# 10
VCC VSS D16# D18# D19# VSS BPMb1# DSTBP0# VSS 9
VCC VSS BPRI# D17# VSS D12# DSTBN0# VSS DBI0# 8
G F E
RSVD DRDY# VSS
D C B A
1
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41
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
L5 P6 M5 L4 M4 R4 T5 U6 T4 U5 U4 V5 V4 W5 AB6 W6 Y6 Y4 AA4 AD6 AA5 AB5 AC5 AB4 AF5 AF4 AG6 AG4 AG5 AH4 AH5 AJ5 AJ6 K3 D2 R6 AD5 F28 G28 Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch CMOS
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
C2 AJ2 AJ1 AD2 AG2 AF2 AG3 G1 C9 G4 G3 G8 F3 G29 H30 G30 A13 T1 G2 R1 B13 B4 C5 A4 C6 A5 B6 B7 A7 A10 A11 B10 C11 D8 B12 C12 D11 G9 F8
Land Name
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# A20M# ADS# ADSTB0# ADSTB1# BCLK0 BCLK1
Direction
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input
Land Name
BNR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPMb0# BPMb1# BPMb2# BPMb3# BPRI# BR0# BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 COMP8 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17#
Direction
Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Common Clock Input
Common Clock Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Output Output Output Input Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Common Clock Input/Output Source Synch Source Synch Clock Clock Input/Output Input/Output Input Input
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Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
F9 E9 D7 E10 D10 F11 F12 D13 E13 G13 F14 G14 F15 G15 G16 E15 E16 G18 G17 F17 F18 E18 E19 F20 E21 F21 G21 E22 D22 G22 D20 D17 A14 C15 C14 B15 C18 B16 A17 Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
B18 C21 B21 B19 A19 A22 B22 A8 G11 D19 C20 AC2 B2 G7 C1 C8 G12 G20 A16 B9 E12 G19 C17 Y1 J2 E24 H29 Y3 AE3 E5 F6 J3 A24 AK1 AL1 E29 U2 U3 J16 Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Power/Other
Land Name
D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56#
Direction
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Land Name
D57# D58# D59# D60# D61# D62# D63# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# DEFER# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FC0 FC3 FC10 FC15 FC17 FC18 FC20 FC21 FC22 FC23 FC24 FC25 FC26 FC29 FC30 FC31
Direction
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output
Common Clock Input/Output Common Clock Input
Common Clock Input/Output Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
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Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
H15 H16 J17 H4 AD3 AB3 AA2 T2 AM6 AK6 R3 H1 H2 G10 F2 D4 E4 AB2 N2 P3 AK3 AJ3 K1 L1 C3 W1 V1 G5 AL2 N1 K4 J5 M6 K6 J6 A20 AC4 AE4 AE6 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Power/Other Power/Other Power/Other Power/Other Output Input Input Input Input
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
AH2 D1 D14 D16 E23 E6 E7 F23 F29 G6 N4 N5 P5 V2 G23 B3 F5 A3 AE8 P2 M3 AE1 AD1 W2 AF1 U1 F26 W3 H5 P1 L2 F25 G25 G27 G26 G24 F24 M2 AC1 Common Clock Common Clock Common Clock Common Clock Power/Other Asynch CMOS Asynch CMOS TAP TAP Power/Other TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS TAP Input Input Input Input Output Input Input Input Input Input Output Output Input Input Input Input Input Input Input Input Input Input Input Output Input
Land Name
FC32 FC33 FC34 FC35 FC36 FC37 FC39 FC4 FC40 FC8 FERR#/PBE# GTLREF0 GTLREF1 GTLREF2 GTLREF3 HIT# HITM# IERR# IGNNE# INIT# ITP_CLK0 ITP_CLK1 LINT0 LINT1 LOCK# MSID0 MSID1 PECI PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED
Direction
Land Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET# RS0# RS1# RS2# SKTOCC# SMI# STPCLK# TCK TDI TDI_M TDO TDO_M TESTHI0 TESTHI1 TESTHI10 TESTHI11 TESTHI13 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 THERMTRIP# TMS
Direction
Common Clock Input/Output Common Clock Input/Output Asynch CMOS Asynch CMOS Asynch CMOS TAP TAP Asynch CMOS Asynch CMOS Output Input Input Input Input Input Input
Common Clock Input/Output Power/Other Power/Other Power/Other Asynch CMOS Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Output Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output
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Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
E3 AG1 AA8 AB8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD8 AE11 AE12 AE14 AE15 AE18 AE19 AE21 AE22 AE23 AE9 AF11 AF12 AF14 AF15 AF18 AF19 AF21 Common Clock TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
AF22 AF8 AF9 AG11 AG12 AG14 AG15 AG18 AG19 AG21 AG22 AG25 AG26 AG27 AG28 AG29 AG30 AG8 AG9 AH11 AH12 AH14 AH15 AH18 AH19 AH21 AH22 AH25 AH26 AH27 AH28 AH29 AH30 AH8 AH9 AJ11 AJ12 AJ14 AJ15 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Land Name
TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Direction
Input Input
Land Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Direction
Datasheet
45
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
AJ18 AJ19 AJ21 AJ22 AJ25 AJ26 AJ8 AJ9 AK11 AK12 AK14 AK15 AK18 AK19 AK21 AK22 AK25 AK26 AK8 AK9 AL11 AL12 AL14 AL15 AL18 AL19 AL21 AL22 AL25 AL26 AL29 AL30 AL8 AL9 AM11 AM12 AM14 AM15 AM18 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
AM19 AM21 AM22 AM25 AM26 AM29 AM30 AM8 AM9 AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 AN25 AN26 AN29 AN30 AN8 AN9 J10 J11 J12 J13 J14 J15 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Land Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Direction
Land Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Direction
46
Datasheet
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
J28 J29 J30 J8 J9 K23 K24 K25 K26 K27 K28 K29 K30 K8 L8 M23 M24 M25 M26 M27 M28 M29 M30 M8 N23 N24 N25 N26 N27 N28 N29 N30 N8 P8 R8 T23 T24 T25 T26 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
T27 T28 T29 T30 T8 U23 U24 U25 U26 U27 U28 U29 U30 U8 V8 W23 W24 W25 W26 W27 W28 W29 W30 W8 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y8 AN5 AN3 A23 C23 D23 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output
Land Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Direction
Land Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_MB_ REGULATION VCC_SENSE VCCA VCCIOPLL VCCPLL
Direction
Datasheet
47
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
AN7 AM2 AL5 AM3 AL6 AK4 AL4 AM5 AM7 AL3 A12 A15 A18 A2 A21 A6 A9 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA6 AA7 AB1 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB7 AC3 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
AC6 AC7 AD4 AD7 AE10 AE13 AE16 AE17 AE2 AE20 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE5 AE7 AF10 AF13 AF16 AF17 AF20 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF6 AF7 AG10 AG13 AG16 AG17 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Land Name
VID_SELECT VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VRDSEL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Direction
Output Output Output Output Output Output Output Output Output
Land Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Direction
48
Datasheet
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
AG20 AG23 AG24 AG7 AH1 AH10 AH13 AH16 AH17 AH20 AH23 AH24 AH3 AH6 AH7 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23 AJ24 AJ27 AJ28 AJ29 AJ30 AJ4 AJ7 AK10 AK13 AK16 AK17 AK2 AK20 AK23 AK24 AK27 AK28 AK29 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
AK30 AK5 AK7 AL10 AL13 AL16 AL17 AL20 AL23 AL24 AL27 AL28 AL7 AM1 AM10 AM13 AM16 AM17 AM20 AM23 AM24 AM27 AM28 AM4 AN1 AN10 AN13 AN16 AN17 AN2 AN20 AN23 AN24 AN27 AN28 B1 B11 B14 B17 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Land Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Direction
Land Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Direction
Datasheet
49
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
B20 B24 B5 B8 C10 C13 C16 C19 C22 C24 C4 C7 D12 D15 D18 D21 D24 D3 D5 D6 D9 E11 E14 E17 E2 E20 E25 E26 E27 E28 E8 F10 F13 F16 F19 F22 F4 F7 H10 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
H11 H12 H13 H14 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H3 H6 H7 H8 H9 J4 J7 K2 K5 K7 L23 L24 L25 L26 L27 L28 L29 L3 L30 L6 L7 M1 M7 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Land Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Direction
Land Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Direction
50
Datasheet
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
N3 N6 N7 P23 P24 P25 P26 P27 P28 P29 P30 P4 P7 R2 R23 R24 R25 R26 R27 R28 R29 R30 R5 R7 T3 T6 T7 U7 V23 V24 V25 V26 V27 V28 V29 V3 V30 V6 V7 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table 23.
Alphabetical Land Assignments
Land Signal # Buffer Type
W4 W7 Y2 Y5 Y7 AN6 AN4 B23 A25 A26 A27 A28 A29 A30 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30 J1 AA1 F27 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output
Land Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Direction
Land Name
VSS VSS VSS VSS VSS VSS_MB_ REGULATION VSS_SENSE VSSA VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT_OUT_ LEFT VTT_OUT_ RIGHT VTT_SEL
Direction
Datasheet
51
Land Listing and Signal Descriptions
Table 24.
Land # A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
Numerical Land Assignment
Signal Buffer Type Power/Other Common Clock Input Direction
Table 24.
Land # B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 Input B22 B23 B24 B25 B26 B27 B28 B29
Numerical Land Assignment
Signal Buffer Type Power/Other Source Synch Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Common Clock Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Input/Output Input Direction
Land Name VSS RS2# D02# D04# VSS D07# DBI0# VSS D08# D09# VSS COMP0 D50# VSS DSTBN3# D56# VSS D61# RESERVED VSS D62# VCCA FC23 VTT VTT VTT VTT VTT VTT VSS DBSY# RS0# D00# VSS D05# D06# VSS DSTBP0# D10#
Land Name VSS D13# COMP8 VSS D53# D55# VSS D57# D60# VSS D59# D63# VSSA VSS VTT VTT VTT VTT VTT VTT DRDY# BNR# LOCK# VSS D01# D03# VSS DSTBN0# BPMb1# VSS D11# D14# VSS D52# D51# VSS DSTBP3# D54# VSS
Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other
Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output
Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input
B30 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output
52
Datasheet
Land Listing and Signal Descriptions
Table 24.
Land # C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28
Numerical Land Assignment
Signal Buffer Type Direction
Table 24.
Land # D29 D30 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Common Clock Input Direction
Land Name DBI3# D58# VSS VCCIOPLL VSS VTT VTT VTT VTT VTT VTT RESERVED ADS# VSS HIT# VSS VSS D20# D12# VSS D22# D15# VSS D25# RESERVED VSS RESERVED D49# VSS DBI2# D48# VSS D46# VCCPLL VSS VTT VTT VTT VTT
Land Name VTT VTT VSS TRDY# HITM# FC20 RESERVED RESERVED VSS D19# D21# VSS DSTBP1# D26# VSS D33# D34# VSS D39# D40# VSS D42# D45# RESERVED FC10 VSS VSS VSS VSS FC26 GTLREF3 BR0# VSS RS1# FC21 VSS D17# D18# VSS
Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Common Clock Input/Output Power/Other
Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output
Common Clock Input/Output Power/Other Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output
E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input
Power/Other
E25 E26
Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
E27 E28 E29 F2 F3 F4 F5 F6 F7 F8 F9 F10
Common Clock Input/Output Power/Other Common Clock Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Input
Datasheet
53
Land Listing and Signal Descriptions
Table 24.
Land # F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20
Numerical Land Assignment
Signal Buffer Type Direction
Table 24.
Land # G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 H1 H2 H3
Numerical Land Assignment
Signal Buffer Type Direction
Land Name D23# D24# VSS D28# D30# VSS D37# D38# VSS D41# D43# VSS RESERVED TESTHI7 TESTHI2 TESTHI0 VTT_SEL BCLK0 RESERVED BPMb0# COMP2 BPMb3# BPMb2# PECI RESERVED DEFER# BPRI# D16# GTLREF2 DBI1# DSTBN1# D27# D29# D31# D32# D36# D35# DSTBP2# DSTBN2#
Land Name D44# D47# RESET# TESTHI6 TESTHI3 TESTHI5 TESTHI4 BCLK1 BSEL0 BSEL2 GTLREF0 GTLREF1 VSS FC35 TESTHI10 VSS VSS VSS VSS VSS VSS VSS VSS VSS FC32 FC33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FC15
Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other
Source Synch Input/Output Source Synch Input/Output Common Clock Power/Other Power/Other Power/Other Power/Other Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input Input Input Input Output Output Input Input
Power/Other Power/Other Power/Other Power/Other Clock
Input Input Input Output Input
H4 H5 H6 H7 H8 H9
Common Clock Input/Output Power/Other Input
H10 H11 H12 H13 H14 H15
Common Clock Input/Output Common Clock Input/Output Power/Other Input/Output
Common Clock Common Clock
Input Input
H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29
Source Synch Input/Output Power/Other Input
Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output
54
Datasheet
Land Listing and Signal Descriptions
Table 24.
Land # H30 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K7 K8
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Power/Other Asynch CMOS Input Input Direction Output Output
Table 24.
Land # K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 L8 L23 L24 L25 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M7 M8 M23 M24 M25 M26 M27 M28 M29
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Asynch CMOS Output Input Input Input Direction
Land Name BSEL1 VTT_OUT_LEFT FC3 FC22 VSS REQ1# REQ4# VSS VCC VCC VCC VCC VCC VCC VCC VCC FC31 FC34 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC LINT0 VSS A20M# REQ0# VSS REQ3# VSS VCC
Land Name VCC VCC VCC VCC VCC VCC VCC VCC LINT1 TESTHI13 VSS A06# A03# VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS THERMTRIP# STPCLK# A07# A05# REQ2# VSS VCC VCC VCC VCC VCC VCC VCC VCC
Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other
Datasheet
55
Land Listing and Signal Descriptions
Table 24.
Land # M30 N1 N2 N3 N4 N5 N6 N7 N8 N23 N24 N25 N26 N27 N28 N29 N30 P1 P2 P3 P4 P5 P6 P7 P8 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 R3 R4 R5 R6
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Asynch CMOS Power/Other Input Input Direction
Table 24.
Land # R7 R8 R23 R24 R25 R26
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Direction
Land Name VCC PWRGOOD IGNNE# VSS RESERVED RESERVED VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TESTHI11 SMI# INIT# VSS RESERVED A04# VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS COMP3 VSS FERR#/PBE# A08# VSS ADSTB0#
Land Name VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS COMP1 FC4 VSS A11# A09# VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TDO_M FC29 FC30 A13# A12# A10# VSS VCC VCC VCC VCC VCC VCC
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Asynch CMOS Power/Other Input Input Input
R27 R28 R29 R30 T1 T2 T3 T4 T5 T6 T7 T8 T23 T24 T25 T26
Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Output Input
T27 T28 T29 T30 U1 U2 U3 U4 U5 U6 U7 U8 U23 U24 U25 U26 U27
Source Synch Input/Output Power/Other Source Synch Input/Output
56
Datasheet
Land Listing and Signal Descriptions
Table 24.
Land # U28 U29 U30 V1 V2 V3 V4 V5 V6 V7 V8 V23 V24 V25 V26 V27 V28 V29 V30 W1 W2 W3 W4 W5 W6 W7 W8 W23 W24 W25 W26 W27 W28 W29 W30 Y1 Y2 Y3 Y4
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Output Direction
Table 24.
Land # Y5 Y6 Y7 Y8 Y23
Numerical Land Assignment
Signal Buffer Type Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Power/Other Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Direction
Land Name VCC VCC VCC MSID1 RESERVED VSS A15# A14# VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS MSID0 TDI_M TESTHI1 VSS A16# A18# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC FC0 VSS FC17 A20#
Land Name VSS A19# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VTT_OUT_ RIGHT FC39 VSS A21# A23# VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS IERR# FC37 A26# A24# A17# VSS VCC VSS VSS VSS
Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Output Input Input
Y24 Y25 Y26 Y27 Y28 Y29 Y30 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB23 AB24 AB25
Datasheet
57
Land Listing and Signal Descriptions
Table 24.
Land # AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AE1 AE2
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Input Output Direction
Table 24.
Land # AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11
Numerical Land Assignment
Signal Buffer Type Power/Other Direction
Land Name VSS VSS VSS VSS VSS TMS DBR# VSS RESERVED A25# VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TDI BPM2# FC36 VSS ADSTB1# A22# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TCK VSS
Land Name FC18 RESERVED VSS RESERVED VSS SKTOCC# VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS TDO BPM4# VSS A28# A27# VSS VSS VCC VCC VSS VCC
Power/Other
C Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Output Output
Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Input
AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9
Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Input
Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
AF10 AF11
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Table 24.
Land # AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Input Direction
Table 24.
Land # AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Land Name VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS TRST# BPM3# BPM5# A30# A31# A29# VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS
Land Name VCC VCC VSS VSS VCC VCC VCC VCC VCC VCC VSS RESERVED VSS A32# A33# VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VCC VCC VCC
Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Common Clock Input/Output Common Clock Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
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Land Listing and Signal Descriptions
Table 24.
Land # AH30 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8
Numerical Land Assignment
Signal Buffer Type Power/Other Common Clock Input/Output Common Clock Input/Output TAP Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Input Direction
Table 24.
Land # AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Direction
Land Name VCC BPM1# BPM0# ITP_CLK1 VSS A34# A35# VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS FC24 VSS ITP_CLK0 VID4 VSS FC8 VSS VCC
Land Name VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS FC25 PROCHOT# VRDSEL VID5 VID1 VID3 VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS
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Table 24.
Land # AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Direction
Table 24.
Land # AM27 AM28 AM29 AM30 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30
Numerical Land Assignment
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Direction
Land Name VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VID0 VID2 VSS VID6 FC40 VID7 VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC
Land Name VSS VSS VCC VCC VSS VSS VCC_SENSE VSS_SENSE VCC_MB_ REGULATION VSS_MB_ REGULATION VID_SELECT VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC
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Land Listing and Signal Descriptions
4.2
Table 25.
Alphabetical Signals Reference
Signal Description (Sheet 1 of 9)
Name Type Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See Section 6.1 for more details. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. Input/ Output ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the ADS# activation to begin protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB0# ADSTB1#
A[35:3]#
Input/ Output
A20M#
Input
ADS#
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
BNR#
Input/ Output
BNR# (Block Next Request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.
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Table 25.
Signal Description (Sheet 2 of 9)
Name Type Description BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# and BPMb[3:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[3:0]# are associated with core 0. BPMb[3:0]# are associated with core 1. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. These signals do not have on-die termination. Refer to Section 2.5.2 for termination requirements. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to Section 2.7.2. COMP[3:0] and COMP8 must be terminated to VSS on the system board using precision resistors.
BPM[5:0]# BPMb[3:0]#
Input/ Output
BPRI#
Input
BR0#
Input/ Output
BSEL[2:0]
Output
COMP8 COMP[3:0]
Analog
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Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 3 of 9)
Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#. Quad-Pumped Signal Groups D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DBI# 0 1 2 3
Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. DBI[3:0]# Input/ Output DBI[3:0] Assignment To Data Bus Bus Signal DBI3# DBI2# DBI1# DBI0# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]#
DBR#
Output
DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins/lands on all processor FSB agents.
DBSY#
Input/ Output
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Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 4 of 9)
Name Type Description DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#. Signals DSTBN[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobe DSTBN0# DSTBN1# DSTBN2# DSTBN3#
DEFER#
Input
DRDY#
Input/ Output
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# FCx Other Associated Strobe DSTBP0# DSTBP1# DSTBP2# DSTBP3#
FC signals are signals that are available for compatibility with other processors. FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/ PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. GTLREF[3:0] determine the signal reference level for GTL+ input signals. GTLREF is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.
FERR#/PBE#
Output
GTLREF[3:0]
Input
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Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 5 of 9)
Name HIT# HITM# Type Input/ Output Input/ Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination. Refer to Section 2.5.2 for termination requirements. IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands of all processor FSB agents. ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these signals as LINT[1:0] is the default configuration.
IERR#
Output
IGNNE#
Input
INIT#
Input
ITP_CLK[1:0]
Input
LINT[1:0]
Input
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Table 25.
Signal Description (Sheet 6 of 9)
Name Type Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# de-asserted. This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock. PECI is a proprietary one-wire bus interface. See Section 5.3 for details. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system de-asserts PROCHOT#. See Section 5.2.4 for more details. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# Input/ Output REQ[4:0]# (Request Command) must connect the appropriate pins/ lands of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1. This signal does not have on-die termination and must be terminated on the system board. RESERVED All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors.
LOCK#
Input/ Output
PECI
Input/ Output
PROCHOT#
Input/ Output
PWRGOOD
Input
RESET#
Input
Datasheet
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Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 7 of 9)
Name Type Description RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents. SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the de-assertion of RESET#, the processor will tri-state its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop Grant state. The processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop Grant state. When STPCLK# is de-asserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI and TDI_M (Test Data In) transfer serial test data into the processor cores. TDI and TDI_M provide the serial input needed for JTAG specification support. TDI connects to core 0. TDI_M connects to core 1. TDO and TDO_M (Test Data Out) transfer serial test data out of the processor cores. TDO and TDI_M provide the serial output needed for JTAG specification support. TDO connects to core 1. TDO_M connects to core 0. TESTHI[13,11:10,7:0] must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a resistor for proper processor operation. See Section 2.4 for more details.
RS[2:0]#
Input
SKTOCC#
Output
SMI#
Input
STPCLK#
Input
TCK
Input
TDI, TDI_M
Input
TDO, TDO_M
Output
TESTHI[13, 11:10,7:0]
Input
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Table 25.
Signal Description (Sheet 8 of 9)
Name Type Description In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid) and is disabled on de-assertion of PWRGOOD (if VTT or VCC are not valid, THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains latched until PWRGOOD, VTT, or VCC is de-asserted. While the de-assertion of the PWRGOOD, VTT, or VCC will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid). TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[7:0] pins. VCCPLL provides isolated power for internal processor FSB PLLs. VCC_SENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure voltage near the silicon with little noise. This land is provided as a voltage regulator feedback sense point for VCC. It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. VID[7:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See Table 2 for definitions of these signals. The VR must supply the voltage that is requested by the signals, or disable itself. This land is tied high on the processor package and is used by the VR to choose the proper VID table. Refer to the Voltage RegulatorDown (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information.
THERMTRIP#
Output
TMS TRDY# TRST# VCC VCCPLL VCC_SENSE
Input Input Input Input Input Output
VCC_MB_ REGULATION
Output
VID[7:0]
Output
VID_SELECT
Output
Datasheet
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Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 9 of 9)
Name VRDSEL VSS VSSA VSS_SENSE Type Input Input Input Output Description This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to VSS. VSS are the ground pins for the processor and should be connected to the system ground plane. VSSA is the isolated ground for internal PLLs. VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. This land is provided as a voltage regulator feedback sense point for VSS. It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. Miscellaneous voltage supply. Output VTT_OUT_RIGHT VTT_SEL Output The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to VTT on the motherboard. The VTT_SEL signal is used to select the correct VTT voltage level for the processor. This land is connected internally in the package to VTT.
VSS_MB_ REGULATION VTT VTT_OUT_LEFT
Output
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5
5.1
Thermal Specifications and Design Considerations
Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
Note:
The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on the boxed processor.
5.1.1
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (TC) specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 26. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in Section 5.3.1.1. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
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The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to Section 5.2. In all cases the Thermal Monitor and Thermal Monitor 2 feature must be enabled for the processor to remain within specification. Table 26. Processor Thermal Specifications
Thermal Core Design Frequency Power (W) (GHz) 3.00 2.93 2.66 2.66 130 130 130 95 Extended HALT Power (W)1 37 37 50 24 775_VR_CONF IG_05A 775_VR_CONF IG_05B 775_VR_CONF IG_05A 775_VR_CONF IG_05B 775_VR_ Minimum CONFIG_05A TC (°C) 2 /B Guidance 5 5 5 5 Maximum TC (°C) See Table 27, Figure 15 See Table 29, Figure 17 See Table 28, Figure 16 See Table 29, Figure 17 Notes
Processor Number QX6850 QX6800 QX6700 Q6700
3, 4
3, 4
Q6600
2.40
105
50
5
3, 4, 5
Q6600 NOTES:
2.40
95
24
5
3, 4, 6
1. Specification is at 50 °C TC and typical voltage loadline.
2. 775_VR_CONFIG_05B guidelines provide a design target for meeting future thermal requirements. 3. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate. 4. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the maximum TC will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table for the allowed combinations of power and TC. 5. These processors have CPUID = 06F7h 6. These processors have CPUID = 06FBh
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Table 27.
Thermal Profile for 130 W Processors
Power (W) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Maximum Tc (°C) 42.4 42.7 43.1 43.4 43.8 44.1 44.4 44.8 45.1 45.5 45.8 46.1 46.5 46.8 47.2 47.5 47.8 Power (W) 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Maximum Tc (°C) 48.2 48.5 48.9 49.2 49.5 49.9 50.2 50.6 50.9 51.2 51.6 51.9 52.3 53.1 52.9 53.3 53.6 Power (W) 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Maximum Tc (°C) 54.0 54.3 54.6 55.0 55.3 57.7 56.0 56.3 56.7 57.0 57.4 57.7 58.0 58.4 58.7 59.1 59.4 Power (W) 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 Maximum Tc (°C) 59.7 60.1 60.4 60.8 61.1 61.4 61.8 62.1 62.5 62.8 63.1 63.5 63.8 64.1 64.5
Figure 15.
Thermal Profile for 130 W Processors
65.0
60.0
55.0 Tcase (C)
y = 0.17x + 42.4
50.0
45.0
40.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Power (W)
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Table 28.
Thermal Profile for 105 W Processors
Power (W) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 Maximum Tc (°C) 43.3 43.7 44.0 44.4 44.7 45.1 45.5 45.7 46.1 46.4 46.9 47.3 47.6 48.0 Power (W) 28 30 32 34 36 38 40 42 44 46 48 50 52 54 Maximum Tc (°C) 48.3 48.7 49.1 49.4 49.8 50.1 50.5 50.9 51.2 51.6 51.9 52.3 52.7 53.0 Power (W) 56 58 60 62 64 66 68 70 72 74 76 78 80 82 Maximum Tc (°C) 53.4 53.8 54.1 54.5 54.9 55.2 55.4 55.9 56.3 56.7 57.0 57.4 57.7 58.1 Power (W) 84 86 88 90 92 94 96 98 100 102 104 105 Maximum Tc (°C) 58.4 58.8 59.1 59.5 59.9 60.3 60.6 60.9 61.3 61.7 62.0 62.2
Figure 16.
Thermal Profile for 105 W Processors
65.0
60.0
55.0 Tcase (C)
y = 0.18x + 43.3
50.0
45.0
40.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Power (W)
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Table 29.
Thermal Profile 95 W Processors
Power (W) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 Maximum Tc (°C) 44.4 45.0 45.5 46.1 46.6 47.2 47.8 48.3 48.9 49.4 50.0 50.6 51.1 51.7 Power (W) 28 30 32 34 36 38 40 42 44 46 48 50 52 54 Maximum Tc (°C) 52.2 52.8 53.4 53.9 54.5 55.0 55.6 56.2 56.7 57.3 57.8 58.4 59.0 59.5 Power (W) 56 58 60 62 64 66 68 70 72 74 76 78 80 82 Maximum Tc (°C) 60.1 60.6 61.2 61.8 62.3 62.9 63.4 64.0 64.6 65.1 65.7 66.2 66.8 67.4 Power (W) 84 86 88 90 92 94 95 Maximum Tc (°C) 67.9 68.5 69.0 69.6 70.2 70.7 71.0
Figure 17.
Thermal Profile 95 W Processors
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5.1.2
Thermal Metrology
The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 18 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
Figure 18.
Case Temperature (TC) Measurement Location
Measure TC at this point (geometric center of the package)
37.5 mm
37.5 mm
5.2
5.2.1
Processor Thermal Features
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will not be off for more than 3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An
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under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.
5.2.2
Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor. When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple utilized by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID is that specified in Table 4. These parameters represent normal system operation. The second operating point consists of both a lower operating frequency and voltage. When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see Table 4). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 19 for an illustration of this ordering.
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Figure 19.
Thermal Monitor 2 Frequency and Voltage Ordering
TTM2 fMAX fTM2 VID VIDTM2
Temperature
Frequency
VID
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.
5.2.3
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature. The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features. On-Demand mode is intended as a means to reduce system level power consumption. Systems utilizing the Clovertown processor s must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/ 12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the OnDemand mode.
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5.2.4
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#. PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi-directional PROCHOT# feature.
5.2.5
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage (VCC) must be removed within the timeframe defined in Table 10.
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5.3
5.3.1
Platform Environment Control Interface (PECI)
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire; thus, alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI interface on the processor is disabled by default and must be enabled through BIOS.
5.3.1.1
TCONTROL and TCC Activation on PECI-Based Systems
Fan speed control solutions based on PECI use a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative. Thermal management algorithms should use the relative temperature value delivered over PECI in conjunction with the TCONTROL MSR value to control or optimize fan speeds. Figure 20 shows a conceptual fan control diagram using PECI temperatures. The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the temperature approaches TCC activation, the PECI value approaches zero. TCC activates at a PECI count of zero.
.
Figure 20.
Conceptual Fan Control on PECI-Based Platforms
TCONTROL Setting
TCC Activation Temperature Max PECI = 0
Fan Speed (RPM) Min PECI = -20
PECI = -10
Temperature Note: Not intended to depict actual implementation
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5.3.2
5.3.2.1
PECI Specifications
PECI Device Address
The socket 0 PECI register resides at address 30h and socket 1 resides at 31h. Note that each address also supports two domains (Domain 0 and Domain 1). For more information on PECI domains, refer to the Platform Environment Control Interface Specification.
5.3.2.2
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes.
5.3.2.3
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is known to be unresponsive. Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI. To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the Host controller should take action to protect the system from possible damaging states. It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive GetTemp0()s or GetTemp1()s or for a one second time interval. The host controller may also implement an alert to software in the event of a critical or continuous fault condition.
5.3.2.4
PECI GetTemp0() and GetTemp1() Error Code Support
The error codes supported for the processor GetTemp0() and GetTemp1() commands are listed in Table 30.
Table 30.
GetTemp0() and GetTemp1() Error Codes
Error Code 8000h 8002h General sensor error Sensor is operational, but has detected a temperature below its operational range (underflow). Description
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6.1
Features
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 31. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.
Table 31.
Power-On Configuration Option Signals
Configuration Option Output tristate Execute BIST Disable dynamic bus parking Symmetric agent arbitration ID RESERVED Signal1,2,3 SMI# A3# A25# BR0# A[8:5]#, A[24:11]#, A[35:26]#
NOTES: 1. Asserting this signal during RESET# will select the corresponding option. 2. Address signals not identified in this table as configuration options should not be asserted during RESET#. 3. Disabling of any of the cores within the processor must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the package.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 21 for a visual representation of the processor low power states.
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Figure 21.
Processor Low Power State Machine
HALT or MWAIT Instruction and HALT Bus Cycle Generated Normal State - Normal Execution INIT#, BINIT#, INTR, NMI, SMI#, RESET#, FSB interrupts
Extended HALT or HALT State - BCLK running - Snoops and interrupts allowed
STPCLK# Asserted
STPCLK# De-asserted
STPCLK# Asserted
Snoop Event Occurs STPCLK# De-asserted
Snoop Event Serviced
Extended HALT Snoop or HALT Snoop State - BCLK running - Service Snoops to cahces Stop Grant State - BCLK running - Snoops and interrupts allowed Snoop Event Occurs Snoop Event Serviced Stop Grant Snoop State - BCLK running - Service Snoops to cahces
SleepStateFigure
6.2.1
Normal State
This is the normal operating state for the processor.
6.2.2
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. The Extended HALT state is a lower power state as compared to the Stop Grant State. If Extended HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the sections below for details about the HALT and Extended HALT states.
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information.
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The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS. When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. Not all processors are capable of supporting Extended HALT State. More details on which processor frequencies will support this feature will be provided in future releases of the Intel® Core™2 Extreme Quad-Core Processor QX6700 and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update when available. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID. While in Extended HALT state, the processor will process bus snoops. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will first transition the VID to the original value and then change the bus ratio back to the original value.
6.2.3
Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. The processor will issue two Stop Grant Acknowledge special bus cycles, once for each die. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state. All processor cores will enter the Stop Grant state once the STPCLK# pin is asserted. Additionally, all processor cores must be in the Stop Grant state before the deassertion of STPCLK#. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4). While in the Stop Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop Grant state, the processor will process a FSB snoop.
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6.2.4
Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State
The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop State and Extended HALT Snoop State.
6.2.4.1
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop Grant state or HALT Power Down state, as appropriate.
6.2.4.2
Extended HALT Snoop State
The Extended HALT Snoop State is the default Snoop State when the Extended HALT state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state. While in the Extended HALT Snoop State, snoops are handled the same way as in the HALT Snoop State. After the snoop is serviced the processor will return to the Extended HALT state.
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7
Boxed Processor Specifications
The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor. This chapter is particularly important for OEMs that manufacture baseboards for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. Figure 22 shows a mechanical representation of a boxed processor.
Note:
Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). Mechanical Representation of the Boxed Processor
Figure 22.
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
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7.1
7.1.1
Mechanical Specifications
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 22 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 23 (Side View), and Figure 24 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 28 and Figure 29. Note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning.
Figure 23.
Space Requirements for the Boxed Processor (Side View)
95.0 [3.74]
81.3 [3.2]
10.0 [0.39]
25.0 [0.98]
Boxed Proc SideView
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Figure 24.
Space Requirements for the Boxed Processor (Top View)
NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Figure 25.
Space Requirements for the Boxed Processor (Overall View)
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7.1.2
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 550 grams. Refer to Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements.
7.1.3
Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly.
7.2
7.2.1
Electrical Requirements
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 26. Baseboards must provide a matched power header to support the boxed processor. Table 32 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL. The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 27 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket.
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Figure 26.
Boxed Processor Fan Heatsink Power Cable Connector Description
Pin 1 2 3 4
Signal GND +12 V SENSE CONTROL
Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard.
1234
Table 32.
Fan Heatsink Power and Signal Specifications
Description +12 V: 12 volt fan power supply IC: - Maximum fan steady-state current draw - Average fan steady-state current draw - Maximum fan start-up current draw - Fan start-up current draw maximum duration SENSE: SENSE frequency CONTROL NOTES: — — — — 1.2 0.5 2.2 1.0 — — — — A A A Second pulses per fan revolution Hz Min 11.4 Typ 12 Max 12.6 Unit V Notes -
— 21
2 25
— 28
1
2, 3
1. Baseboard should pull this pin up to 5 V with a resistor. 2. Open drain type, pulse width modulated. 3. Fan will have pull-up resistor to 4.75 V maximum of 5.25 V.
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Figure 27.
Baseboard Power Header Placement Relative to Processor Socket
7.3
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the boxed processor.
7.3.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is in Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 26) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 28 and Figure 29 illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 39 ºC. Again, meeting the processor's temperature specification is the responsibility of the system integrator.
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Figure 28.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)
Figure 29.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)
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7.3.2
Fan Speed Control Operation (Intel® Core™2 Extreme processors only)
The boxed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control over fan speed. The fan speed can be controlled by hardware and software from the motherboard. This is accomplished by varying the duty cycle of the Control signal on the 4th pin (see Table 32). The motherboard must have a 4-pin fan header and must be designed with a fan speed controller with PWM output and Digital Thermometer measurement capabilities. For more information on specific motherboard requirements for 4-wire based fan speed control refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). The Internal chassis temperature should be kept below 39 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the fan for the boxed processor. See Table 32 for specific requirements.
7.3.3
Fan Speed Control Operation (Intel® Core™2 Quad processor)
If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point. These set points, represented in Figure 30 and Table 33, can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 38 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to Table 32 for the specific requirements.
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Figure 30.
Boxed Processor Fan Heatsink Set Points
Higher Set Point Highest Noise Level
Increasing Fan Speed & Noise
Lower Set Point Lowest Noise Level
X
Y
Z
Internal Chassis Temperature (Degrees C)
Table 33.
Fan Heatsink Power and Signal Specifications
Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds. Recommended maximum internal chassis temperature for worst-case operating environment. When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed. Notes
X ≤ 30
1
Y = 35
-
Z ≥ 39 NOTES:
-
1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (CONTROL see Table 32) and remote thermal diode measurement capability the boxed processor will operate as follows: As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage. The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by more accurate measurement of processor die temperature through the processor's Digital Thermal Sensors (DTS) and PECI. Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures.
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Boxed Processor Specifications
If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
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Debug Tools Specifications
8
8.1
Debug Tools Specifications
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a r system that can make use of an LAI: mechanical and electrical.
8.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
8.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides.
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