T7100

Intel® Core™2 Duo Processors and Intel® Core™2 Extreme Processors for Platforms Based on Mobile Intel® 965 Express Chipset Family Datasheet January 2008 Document Number: 316745-005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Enhanced Intel SpeedStep® Technology for specified units of this processor available Q2/06. See the Processor Spec Finder at http:// processorfinder.intel.com or contact your Intel representative for more information. Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. This device is protected by U.S. patent numbers 5,315,448 and 6,516,132, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel® 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. Intel, Pentium, Intel Core, Intel Core 2, Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007 - 2008, Intel Corporation. All rights reserved. 2 Datasheet Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 Low Power Features ................................................................................................ 11 2.1 Clock Control and Low Power States .................................................................... 11 2.1.1 Core Low Power State Descriptions ........................................................... 13 2.1.2 Package Low Power State Descriptions ...................................................... 15 2.2 Enhanced Intel SpeedStep® Technology .............................................................. 18 2.2.1 Dynamic FSB Frequency Switching ........................................................... 19 2.2.2 Intel® Dynamic Acceleration Technology ................................................... 19 2.3 Extended Low Power States ................................................................................ 19 2.4 FSB Low Power Enhancements ............................................................................ 20 2.5 VID-x .............................................................................................................. 21 2.6 Processor Power Status Indicator (PSI-2) Signal .................................................... 21 Electrical Specifications ........................................................................................... 23 3.1 Power and Ground Pins ...................................................................................... 23 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................... 23 3.3 Voltage Identification ......................................................................................... 23 3.4 Catastrophic Thermal Protection .......................................................................... 26 3.5 Reserved and Unused Pins.................................................................................. 26 3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 27 3.7 FSB Signal Groups............................................................................................. 27 3.8 CMOS Signals ................................................................................................... 29 3.9 Maximum Ratings.............................................................................................. 29 3.10 Processor DC Specifications ................................................................................ 30 Package Mechanical Specifications and Pin Information .......................................... 41 4.1 Package Mechanical Specifications ....................................................................... 41 4.2 Processor Pinout and Pin List .............................................................................. 49 4.3 Alphabetical Signals Reference ............................................................................ 69 Thermal Specifications and Design Considerations .................................................. 77 5.1 Thermal Specifications ....................................................................................... 80 5.1.1 Thermal Diode ....................................................................................... 81 5.1.2 Thermal Diode Offset .............................................................................. 83 5.1.3 Intel® Thermal Monitor........................................................................... 84 5.1.4 Digital Thermal Sensor............................................................................ 86 5.1.5 Out of Specification Detection .................................................................. 87 5.1.6 PROCHOT# Signal Pin ............................................................................. 87 2 3 4 5 Datasheet 3 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 Core Low Power States..............................................................................................12 Package Low Power States.........................................................................................13 Active VCC and ICC Loadline Intel Core 2 Duo Processors - Standard Voltage, Low Voltage and Ultra Low Voltage and Intel Core 2 Extreme Processors | (PSI# Not Asserted) .................................................................................................36 Deeper Sleep VCC and ICC Loadline Intel Core 2 Duo Processors Standard Voltage and Intel Core 2 Extreme Processors (PSI# Asserted)...........................37 Deeper Sleep VCC and ICC Loadline Intel Core 2 Duo Processor Low Voltage and Ultra Low Voltage (PSI# Asserted) ......................................................38 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) .................42 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) .................43 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ........................................44 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ........................................45 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2).................46 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2).................47 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ........................................48 2-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ........................................49 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Coordination of Core Low Power States at the Package Level ..........................................13 Voltage Identification Definition ..................................................................................23 BSEL[2:0] Encoding for BCLK Frequency......................................................................27 FSB Pin Groups ........................................................................................................28 Processor Absolute Maximum Ratings..........................................................................29 Voltage and Current Specifications for the Intel Core 2 Duo Processors Standard Voltage......................................................................................................30 Voltage and Current Specifications for the Intel Core 2 Duo Processors Low Voltage.............................................................................................................32 Voltage and Current Specifications for the Intel Core 2 Duo -Ultra Low Voltage Processors ...................................................................................................33 Voltage and Current Specifications for the Intel Core 2 Extreme Processors ......................34 FSB Differential BCLK Specifications ............................................................................38 AGTL+ Signal Group DC Specifications ........................................................................39 CMOS Signal Group DC Specifications..........................................................................40 Open Drain Signal Group DC Specifications ..................................................................40 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 1 of 2) ..........................................................................................................50 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of 2) ..........................................................................................................51 Pin Listing by Pin Name .............................................................................................53 Pin Listing by Pin Number ..........................................................................................60 Signal Description.....................................................................................................69 Power Specifications for the Intel Core 2 Duo Processor - Standard Voltage ......................77 Power Specifications for the Intel Core 2 Duo Processor - Low Voltage .............................78 Power Specifications for the Intel Core 2 Duo Processor - Ultra Low Voltage .....................79 Power Specifications for the Intel Core 2 Extreme Processor ...........................................80 Thermal Diode Interface ............................................................................................81 Thermal Diode Parameters Using Diode Model ..............................................................82 Thermal Diode Parameters Using Transistor Model ........................................................83 Thermal Diode ntrim and Diode Correction Toffset ........................................................84 4 Datasheet Revision History Document Number 316745 Revision Number -001 • Initial Release • Updates — Chapter 1 added Intel® Core™2 Duo processor - Ultra Low Voltage information — Chapter 3 added Table 8 with Intel Core 2 Duo processor Ultra Low Voltage U7600 and U7500 specifications — Chapter 3 updated Figure 3 and 5 with Intel Core 2 Duo processor - Ultra Low Voltage information — Chapter 5 added Table 19 with Intel Core 2 Duo processor -Ultra Low Voltage U7600 and U7500 specifications • Updates — Chapter 1 added Intel® Core™2 Extreme processor — Chapter 3 added Table 9 with Intel Core 2 Extreme processor X7800 specifications — Chapter 3 updated Figure 3 and 4 with Intel Core 2 Extreme processor information — Chapter 5 added Table 20 with Intel Core 2 Extreme processor X7800 specifications — Corrected the pin diagram for 4-MB Micro-FCPGA and 2-MB Micro-FCPGA Processor Package Drawings • Updates 316745 -004 — Chapter 3 added Intel Core 2 Extreme processor X7900 and Low Voltage processor L7700 specifications — Chapter 5 added Intel Core 2 Extreme processor X7900 and Low Voltage processor L7700 specifications • Updates 316745 -005 — Chapter 3 added Table 8 with Intel Core 2 Duo processor Ultra Low Voltage U7700 specifications — Chapter 5 added Table 21 with Intel Core 2 Duo processor -Ultra Low Voltage U7700 specifications January 2007 August 2007 Description Date May 2007 316745 -002 June 2007 316745 -003 July 2007 Datasheet 5 6 Datasheet Introduction 1 Introduction The Intel® Core™2 Duo processor on 65-nm process technology is the next generation high-performance, low-power processor based on the Intel® Core™ microarchitecture. The Intel Core 2 Duo processor supports the Mobile Intel® 965 Express Chipset and Intel® 82801HBM ICH8M Controller Hub Based Systems. This document contains electrical, mechanical and thermal specifications for the following processors: • Intel Core 2 Duo processor - Standard Voltage • Intel Core 2 Duo processor - Low Voltage • Intel Core 2 Duo processor - Ultra Low Voltage • Intel Core 2 Extreme processor Note: In this document, the Intel Core 2 Duo and Intel Core 2 Extreme processors are referred to as the processor and Mobile Intel® 965 Express Chipset family is referred to as the (G)MCH. The following list provides some of the key features on this processor: • Dual core processor for mobile with enhanced performance • Intel architecture with Intel® Wide Dynamic Execution • L1 Cache to Cache (C2C) transfer • On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each core • On-die, up to 4-MB second level shared cache with advanced transfer cache architecture • Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3) • 800-MHz Source-Synchronous Front Side Bus (FSB) for Intel Core 2 Extreme processors, Intel Core 2 Duo standard and low voltage processors. 533-MHz FSB for Intel Core 2 Duo ultra low voltage processors • Advanced power management features including Enhanced Intel SpeedStep® Technology and Dynamic FSB frequency switching. • Intel Enhanced Deeper Sleep state with P_LVL5 I/O support • Digital Thermal Sensor (DTS) • Intel® 64 Technology • Enhanced Intel® Virtualization Technology • Intel® Dynamic Acceleration Technology • Enhanced Multi Threaded Thermal Management (EMTTM) • PSI2 functionality • Standard voltage processors are offered in Micro-FCPGA and Micro-FCBGA packaging. Low voltage and Ultra low voltage processors are offered in MicroFCBGA packaging only. Intel Core 2 Extreme processors are offered in Micro-FCPGA packaging only. • Execute Disable Bit support for enhanced security Datasheet 7 Introduction 1.1 Terminology Term Definition A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Refers to the interface between the processor and system core logic (also known as the chipset components). Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors. Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. Technology that provides power management capabilities to laptops. Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core. 64-bit memory extensions to the IA-32 architecture. Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Thermal Design Power The processor core power supply The processor ground # Front Side Bus (FSB) AGTL+ Storage Conditions Enhanced Intel SpeedStep® Technology Processor Core Intel® 64 Technology Intel® Virtualization Technology TDP VCC VSS 8 Datasheet Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document Intel® Core™ 2 Duo Processors For Intel® Centrino® Duo Processor Technology Specification Update Mobile Intel® 965 Express Chipset Family Datasheet Mobile Intel® 965 Express Chipset Family Specification Update Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Datasheet Document Number1,2 314079 316273 316274 See http:// www.intel.com/design/ chipsets/datashts/ 313056.htm See http:// www.intel.com/design/ chipsets/specupdt/ 313057.htm See http:// www.intel.com/design/ pentium4/manuals/ index_new.htm See http:// developer.intel.com/ design/processor/ specupdt/252046.htm 253665 253666 253667 253668 253669 Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Specification Update Intel® 64 and IA-32 Architectures Software Developer’s Manual Intel® 64 and IA-32 Architectures Software Developer's Manuals Documentation Change Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide NOTES: 1. Contact your local Intel representative for the latest revision of this document. § Datasheet 9 Introduction 10 Datasheet Low Power Features 2 2.1 Low Power Features Clock Control and Low Power States The processor supports low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states. When both cores coincide in a common core low power state, the central power management logic ensures that the entire processor enters the respective package low power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4, or P_LVL5) I/O read to the chipset. The processor implements two software interfaces for requesting low power states: MWAIT instruction extensions with sub-state hints or P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The P_LVLx I/O monitor address does not need to be set up before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through the Model Specific Register (MSR). If a core encounters a chipset break event while STPCLK# is asserted, then it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the processor should return to the Normal state. Figure 1 shows the core low power states and Figure 2 shows the package low power states. Table 1 maps the core low power states to the package low power states. Datasheet 11 Low Power Features Figure 1. Core Low Power States Stop Grant STPCLK# asserted STPCLK# de-asserted STPCLK# de-asserted STPCLK# asserted C1/ MWAIT STPCLK# de-asserted STPCLK# asserted Core state break MWAIT(C1) C1/Auto Halt HLT instruction Halt break C0 Core State break P_LVL4 or ø P_LVL5 or MWAIT(C4) P_LVL2 or MWAIT(C2) Core state break Core P_LVL3 or state MWAIT(C3) break C4 †‡ C2 † C3 † halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) † — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ — Core C4 state supports the package level Intel Enhanced Deeper Sleep state . Ø — P_LVL5 read is issued once the L2 cache is reduced to zero. 12 Datasheet Low Power Features Figure 2. Package Low Power States STPCLK# asserted SLP# asserted DPSLP# asserted DPRSTP# asserted Normal STPCLK# deasserted Stop Grant SLP# deasserted Sleep DPSLP# deasserted Deep Sleep DPRSTP# deasserted Deeper † Sleep Snoop Snoop serviced occurs Stop Grant Snoop † — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state. Table 1. Coordination of Core Low Power States at the Package Level Package State Core0 State C0 C11 C2 C3 C0 Normal Normal Normal Normal C11 Normal Normal Normal Normal Core1 State C2 Normal Normal Stop-Grant Stop-Grant C3 Normal Normal Stop Grant Deep Sleep C4 Normal Normal Stop Grant Deep Sleep Deeper Sleep / Intel® Enhanced Deeper Sleep C4 Normal Normal Stop-Grant Deep Sleep NOTES: 1. AutoHALT or MWAIT/C1. 2.1.1 2.1.1.1 Core Low Power State Descriptions Core C0 State This is the normal operating state for cores in the processor. 2.1.1.2 Core C1/AutoHALT Powerdown State C1/AutoHALT is a low power state entered when a core executes the HALT instruction. The processor transitions to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# causes the processor to immediately initialize itself. Datasheet 13 Low Power Features A System Management Interrupt (SMI) handler returns execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT state. While in AutoHALT Powerdown state, the dual core processor processes bus snoops and snoops from the other core. The processor enters a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT Powerdown state. 2.1.1.3 Core C1/MWAIT Powerdown State C1/MWAIT is a low power state entered when the processor core executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information. 2.1.1.4 Core C2 State Individual cores of the dual core processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor does not issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in the C2 state, the dual core processor processes bus snoops and snoops from the other core. The processor enters a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the C2 state. 2.1.1.5 Core C3 State Individual cores of the dual core processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual core processor accesses cacheable memory. The processor core transitions to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# causes the processor to immediately initialize itself. 2.1.1.6 Core C4 State Individual cores of the dual core processor can enter the C4 state by initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core behavior in the C4 state is nearly identical to the behavior in the C3 state. The only difference is that if both processor cores are in C4, then the central power management logic requests that the entire processor enter the Deeper Sleep package low power state (see Section 2.1.2.6). To enable the package level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software programmable MSR. Refer to Section 2.1.2.6 for further details on Intel Enhanced Deeper Sleep state. 14 Datasheet Low Power Features 2.1.2 2.1.2.1 Package Low Power State Descriptions Normal State This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state. 2.1.2.2 Stop-Grant State When the STPCLK# pin is asserted by the chipset, each core of the dual core processor enters the Stop-Grant state within 20-bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low power state. When the STPCLK# pin is deasserted, each core returns to its previous core low power state. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted after the deassertion of SLP#. While in Stop-Grant state, the processor services snoops and latch interrupts delivered on the FSB. The processor latches SMI#, INIT# and LINT[1:0] interrupts and services only one of each upon return to the Normal state. The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# asserts if there is any pending interrupt or Monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear causes assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor should return to the Normal state. A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) occurs with the assertion of the SLP# signal. 2.1.2.3 Stop-Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor stays in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor returns to the StopGrant state once the snoop has been serviced or the interrupt has been latched. 2.1.2.4 Sleep State The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Datasheet 15 Low Power Features In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state causes unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state results in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active, then the processor resets itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur. 2.1.2.5 Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform-level power savings. BCLK stop/restart timings on appropriate chipset based platforms with the CK505 clock chip are as follows: • Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep. • Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it does not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state results in unpredictable behavior. 2.1.2.6 Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels. One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.2 for further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state. In response to entering Deeper Sleep, the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins. 16 Datasheet Low Power Features Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point. 2.1.2.6.1 Intel Enhanced Deeper Sleep State Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends powersaving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters Intel Enhanced Deeper Sleep state: • The last core entering C4 causes the package to issue a P_LVL4 IO Read. • Every concurrent package C4 entry reduces the L2 Cache a certain number of cache ways, after which another P_LVL4 IO Read is issued to the chipset. By default, half the cache is flushed per concurrent C4 entry. • Once the cache is flushed, P_LVL4 IO Reads continue to be issued. • The processor drives the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID[6:0] pins. At this point, snoops to the L2 are still serviced, which reduces the amount of time the processor can reside at the Intel Enhanced Deeper Sleep state core voltage. To improve the Intel Enhanced Deeper Sleep state residency, the (G)MCH features P_LVL5 IO Read support. When enabled, the CPU issues a P_LVL5 IO read, once the L2 cache is flushed. The P_LVL5 IO read triggers a special chipset sequence to notify the chipset to redirect all FSB traffic, except APIC messages, to memory instead of L2 cache. Therefore, the processor remains at the Intel Enhanced Deeper Sleep state core voltage for a longer period of time. 2.1.2.6.2 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions: • The second core is already in C4 and the Intel Enhanced Deeper Sleep state is enabled (as specified in Section 2.1.1.6). • The C0 timer, which tracks continuous residency in the Normal package state, has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed. • The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold. If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold, then L2 cache expansion is requested. If the ratio is zero, then the ratio is not taken into account for Dynamic Cache Sizing decisions. Upon STPCLK# deassertion, the first core exiting Intel Enhanced Deeper Sleep state expands the L2 cache to two ways and invalidate previously disabled cache ways. If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 is shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not the one currently entering the interrupt routine) requests the C1, C2, or C3 states, then all of L2 expands upon the next interrupt event. L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled the processor does not enter Intel Enhanced Deeper Sleep state because the L2 cache remains valid and in full size. Datasheet 17 Low Power Features 2.2 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power. • Voltage and frequency selection is software-controlled by writing to processor MSRs: — If the target frequency is higher than the current frequency, Vcc is ramped up in steps by placing new values on the VID pins, and the PLL then locks to the new frequency. — If the target frequency is lower than the current frequency, the PLL locks to the new frequency, and the VCC is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress the new transition is deferred until the previous transition completes. • The processor controls voltage ramp rates internally to ensure glitch-free transitions. • Low transition latency and large number of transitions possible per second: — Processor core (including L2 cache) is unavailable for up to 10 ms during the frequency transition. — The bus protocol (BNR# mechanism) is used to block snooping. • Improved Intel® Thermal Monitor mode: — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency and voltage specified in a software-programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up-transition to the previous frequency and voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system-level thermal management. • Enhanced thermal management features: — Digital Thermal Sensor and Out of Specification detection — Intel Thermal Monitor 1 in addition to Intel Thermal Monitor 2 in case of unsuccessful Intel Thermal Monitor 2 transition. — Dual core thermal management synchronization. Each core in the dual processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage, then the processor transitions to the requested common frequency and voltage. If the two cores have different frequency and voltage requests, then the processor takes the highest of the two frequencies and voltages as the resolved request, and transition to that frequency and voltage. The processor also supports Dynamic FSB Frequency Switching and Intel® Dynamic Acceleration Technology mode on select SKUS. The operating system can take advantage of these features and request a lower operating point called SuperLFM (due to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic Acceleration Technology mode. 18 Datasheet Low Power Features 2.2.1 Dynamic FSB Frequency Switching Dynamic FSB frequency switching effectively reduces the internal bus clock frequency in half to further decrease the minimum processor operating frequency from the Enhanced Intel SpeedStep Technology performance states and achieve the Super Low Frequency Mode (SuperLFM). This feature is supported at FSB frequencies of 800-MHz and does not entail a change in the external bus signal (BCLK) frequency. Instead, both the processor and (G)MCH internally lower their BCLK reference frequency to 50% of the externally visible frequency. Both the processor and (G)MCH maintain a virtual BCLK signal (“VBCLK”) that is aligned to the external BCLK but at half the frequency. After a downward shift, it would appear externally as if the bus is running with a 100-MHz base clock in all aspects, except that the actual external BCLK remains at 200 MHz. The transition into SuperLFM, a “down-shift”, is done following a handshake between the processor and (G)MCH. A similar handshake is used to indicate an “upshift”, a change back to normal operating mode. 2.2.2 Intel® Dynamic Acceleration Technology The processor supports Intel Dynamic Acceleration Technology mode on select platforms. The Intel Dynamic Acceleration Technology mode feature allows one core of the processor to temporarily operate at a higher frequency point when the other core is inactive and the operating system requests increased performance. This higher frequency is called the opportunistic frequency and the maximum rated operating frequency is the guaranteed frequency. Note: Intel Core 2 Extreme processors do not support Intel Dynamic Acceleration mode. Intel Dynamic Acceleration Technology mode enabling requires: • Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state. • Enhanced Multi-Threaded Thermal Management (EMTTM). • Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via BIOS. When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be active under certain internal conditions. In such a scenario the processor may draw a Instantaneous current (ICC_CORE_INST) for a short duration of tINST; however, the average ICC current is lesser than or equal to ICCDES current specification. Please refer to the Processor DC Specifications section for more details. 2.3 Extended Low Power States Extended low power states (CxE) optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state. Instead of directly transitioning into the package low power state, the extended package low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low power state, control returns to the software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in low power states. Note: Long-term reliability cannot be assured unless all the Extended Low Power states are enabled. Datasheet 19 Low Power Features The processor implements two software interfaces for requesting extended package low power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring MSR bits to automatically promote package low power states to extended package low power states. Extended Stop-Grant and Extended Deeper Sleep must be enabled via the BIOS for the processor to remain within specification. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor. As processor technology changes, enabling the extended low power states becomes increasingly crucial when building computer systems. Maintaining the proper BIOS configuration is key to reliable, long-term system operation. Not complying with this guideline may affect the long-term reliability of the processor. Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states. Extended Deeper Sleep state configuration lowers core voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, automatically transitions to the lowest operating voltage and frequency to reduce snoop service latency. The transition to the lowest operating point or back to the original software requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases. 2.4 FSB Low Power Enhancements The processor incorporates FSB low power enhancements: • Dynamic FSB Power Down • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On Die Termination disabling • Low VCCP (I/O termination voltage) The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane, independent of the core voltage, enabling low I/O switching power at all times. 2.5 VID-x The processor implements the VID-x feature when in Intel Dynamic Acceleration Technology mode. VID-x provides the ability for the processor to request core voltage level reductions greater than one VID tick. The quantity of VID ticks to be reduced depends on the specific performance state in which the processor is running. This improved voltage regulator efficiency during periods of reduced power 20 Datasheet Low Power Features consumption allows for leakage current reduction, which results in platform power savings and extended battery life. There is no platform-level change required to support this feature as long as the VR vendor supports the VID-x feature. 2.6 Processor Power Status Indicator (PSI-2) Signal The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous mobile processors. PSI-2 functionality improves overall voltage regulator efficiency over a wide power range based on the C-state and P-state of the two cores. The combined C-state and P-state of both cores are used to dynamically predict processor power. PSI-2 functionality is expanded further to support three processor states: • Both cores are in idle state • Only one core is in active state • Both cores are in active state § Datasheet 21 Low Power Features 22 Datasheet Electrical Specifications 3 3.1 Electrical Specifications Power and Ground Pins For clean, on-chip power distribution, the processor has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor uses a differential clocking implementation. 3.3 Voltage Identification The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 refers to a high-voltage level and a 0 refers to low-voltage level. Table 2. Voltage Identification Definition (Sheet 1 of 4) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 Datasheet 23 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 4) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID4 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID3 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCC (V) 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 24 Datasheet Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 4) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 VID3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 Datasheet 25 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 4 of 4) VID6 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 1 1 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 3.4 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough that the processor cannot be protected in all conditions without power removal to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. THERMTRIP# functionality is not guaranteed if the PWRGOOD signal is not asserted. 3.5 Reserved and Unused Pins All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) may result in component malfunction or incompatibility with future processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected. The TEST1 and TEST2 pins must have a stuffing option of separate pull-down resistors to VSS. For the purpose of testability, route the TEST3 and TEST5 signals through a groundreferenced Zo = 55-Ω trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. 26 Datasheet Electrical Specifications 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3. Table 3. BSEL[2:0] Encoding for BCLK Frequency BSEL[2] L L L L H H H H BSEL[1] L L H H H H L L BSEL[0] L H H L L H H L BCLK Frequency RESERVED 133 MHz RESERVED 200 MHz RESERVED RESERVED RESERVED RESERVED 3.7 FSB Signal Groups The FSB signals have been combined into groups by buffer type in the following sections. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus, two sets of timing parameters need to be specified. One set is for common clock signals, which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals, which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous. Datasheet 27 Electrical Specifications Table 4. FSB Pin Groups Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3, DPWR# Signal Group AGTL+ Common Clock Input AGTL+ Common Clock I/O Signals REQ[4:0]#, A[16:3]# A[35:17]# AGTL+ Source Synchronous I/O Synchronous to assoc. strobe D[15:0]#, DINV0# D[31:16]#, DINV1# D[47:32]#, DINV2# D[63:48]#, DINV3# AGTL+ Strobes CMOS Input Open Drain Output Open Drain I/O CMOS Output CMOS Input Open Drain Output FSB Clock Power/Other Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK Clock Associated Strobe ADSTB[0]# ADSTB[1]# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, IERR#, THERMTRIP# PROCHOT#4 PSI#, VID[6:0], BSEL[2:0] TCK, TDI, TMS, TRST# TDO BCLK[1:0] COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, VCC, VCCA, VCCP, VCC_SENSE, VSS, VSS_SENSE NOTES: 1. Refer to Chapter 4 for signal descriptions and termination requirements. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. BPM[2:1]# and PRDY# are AGTL+ output only signals. 4. PROCHOT# signal type is open drain output and CMOS input. 5. On die termination differs from other AGTL+ signals. 28 Datasheet Electrical Specifications 3.8 CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs in order for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups. 3.9 Maximum Ratings Table 5 specifies absolute maximum and minimum ratings. If the processor stays within functional operation limits, functionality and long-term reliability can be expected. Caution: At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. Precautions should always be taken to avoid high static voltages or electric fields. Processor Absolute Maximum Ratings Symbol TSTORAGE VCC VinAGTL+ VinAsynch_CMOS Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS CMOS buffer DC input voltage with respect to VSS Min -40 -0.3 -0.1 -0.1 Max 85 1.55 1.55 1.55 Unit °C V V V Notes1 2, 3, 4 Caution: Table 5. NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits does not affect the long term reliability of the device. For functional operation, please refer to the processor case temperature specifications. 3. This rating applies to the processor and does not include any tray or packaging. 4. Failure to adhere to this specification can affect the long term reliability of the processor. Datasheet 29 Electrical Specifications 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Table 6 through Table 8 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Super Low Frequency Mode (SuperLFM) refer to the highest and lowest core operating frequencies supported on the processor. Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the processor are at Tjunction = 100°C. Care should be taken to read all notes associated with each parameter. c Table 6. Symbol VCCDAM VCCHFM VCCLFM VCCSLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for the Intel Core 2 Duo Processors Standard Voltage (Sheet 1 of 2) Parameter VCC in Intel® Dynamic Acceleration Technology Mode VCC at High Frequency Mode (HFM) VCC at Low Frequency Mode (LFM) VCC at Super Low Frequency Mode (SuperLFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep VCC at Intel® Enhanced Deeper Sleep Voltage Standard Voltage Processor ICC Recommended Design Target Standard Voltage ICC for the Processor Processor Number T7800 T7700 T7500 T7300 T7250 T7100 Core Frequency/Voltage 2.6 2.4 2.2 2.0 2.0 1.8 1.2 0.8 GHz GHz GHz GHz GHz GHz GHz GHz & & & & & & & & VCCHFM VCCHFM VCCHFM VCCHFM VCCHFM VCCHFM VCCLFM VCCSLFM 41 41 41 41 41 41 30.1 25.5 27.9 17.0 27.4 16.8 3, 4, 5, 12, 13 3, 4, 5, 12, 13 A 3, 4, 5, 12, 13 3, 4, 5, 12, 14 1.00 1.425 0.6000 0.5500 Min 1.0375 1.0375 0.8500 0.7500 1.20 1.05 1.5 1.10 1.575 0.8000 0.7500 44 Typ Max 1.3500 1.3000 1.0500 0.9500 Unit V V V V V V V V V A 1, 2 1, 2, 8 6 Notes 1, 2 1, 2 1, 2, 8 1, 2 2 ICC IAH, ISGNT ICC Auto-Halt & Stop-Grant HFM SuperLFM ICC Sleep HFM SuperLFM A 3, 4, 12 ISLP A 3, 4, 12 30 Datasheet Electrical Specifications Table 6. Symbol IDSLP IDPRSLP IDC4 dICC/DT ICCA ICCP Voltage and Current Specifications for the Intel Core 2 Duo Processors Standard Voltage (Sheet 2 of 2) Parameter ICC Deep Sleep HFM SuperLFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at Processor Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable Min Typ Max 25.0 16.0 11.5 9.4 600 130 4.5 2.5 Unit A A A A/µs mA A A 10 11 Notes 3, 4, 12 3, 4 3, 4 7, 9 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing in such a way that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the nominal VCC. 5. 800-MHz FSB supported 6. Instantaneous current ICC_CORE_INST of 55 A has to be sustained for short time (tINST) of 10 µs. Average current is less than maximum specified ICCDES. VR OCP threshold should be high enough to support current levels described herein. 7. Measured at the bulk capacitors on the motherboard. 8. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor is lesser than or equal to 350 mV. 9. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 10. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 11. This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high. 12. Processor ICC requirements in Intel Dynamic Acceleration Technology mode is lesser than ICC in HFM. 13. 4-M L2 cache. 14. 2-M L2 cache. Datasheet 31 Electrical Specifications Table 7. Symbol VCCDAM VCCHFM VCCLFM VCCSLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for the Intel Core 2 Duo Processors - Low Voltage Parameter VCC in Intel® Dynamic Acceleration Technology Mode VCC at High Frequency Mode (HFM) VCC at Low Frequency Mode (LFM) VCC at Super Low Frequency Mode (SuperLFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep VCC at Intel® Enhanced Deeper Sleep Voltage Low Voltage Processor ICC Recommended Design Target Low Voltage ICC for the Processor Processor Number Core Frequency/Voltage 1.8 1.6 1.4 1.2 0.8 GHz GHz GHz GHz GHz & & & & & VCCHFM VCCHFM VCCHFM VCCLFM VCCSLFM 23 23 23 21 14.2 11.7 8.3 11.4 8.1 10.0 7.3 6.3 4.7 600 130 4.5 2.5 1.00 1.425 0.6000 0.5500 Min 0.9000 0.9000 0.9000 0.7500 1.20 1.05 1.5 1.10 1.575 0.8000 0.7000 23 Typ Max 1.3000 1.2000 1.0500 0.9500 Unit V V V V V V V V V A 1, 2 1, 2, 13 6 Notes 1, 2 1, 2 1, 2, 13 1, 2 2 ICC L7700 L7500 L7300 A 3, 4, 5, 8, 12 IAH, ISGNT ICC Auto-Halt & Stop-Grant HFM SuperLFM ICC Sleep HFM SuperLFM ICC Deep Sleep HFM SuperLFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at Processor Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable A 3, 4, 12 ISLP A 3, 4, 12 IDSLP IDPRSLP IDC4 dICC/DT ICCA ICCP A A A A/µs mA A A 3, 4, 12 3, 4 3, 4 7, 9 10 11 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 32 Datasheet Electrical Specifications 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. Specified at 100°C Tj. Specified at the nominal VCC. 800-MHz FSB supported. Instantaneous current ICC_CORE_INST of 30 A has to be sustained for short time (tINST) of 10 µs. Average current is less than maximum specified ICCDES. VR OCP threshold should be high enough to support current levels described herein. Measured at the bulk capacitors on the motherboard. 4-M L2 cache. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high. Processor ICC requirements in Intel Dynamic Acceleration Technology mode is lesser than Icc in HFM. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor is lesser than or equal to 350 mV. Table 8. Symbol VCCDAM VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for the Intel Core 2 Duo -Ultra Low Voltage Processors (Sheet 1 of 2) Parameter VCC in Intel® Dynamic Acceleration Mode VCC at High Frequency Mode (HFM) VCC at Low Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep VCC at Intel® Enhanced Deeper Sleep voltage Ultra Low Voltage Processor ICC Recommended Design Target Ultra Low Voltage ICC for the Processor Processor Number Core Frequency/Voltage 1.33 1.20 1.06 0.80 GHz GHz GHz GHz & & & & VCCHFM VCCHFM VCCHFM VCCLFM 16 16 16 13.8 7.4 6.5 7.2 6.3 6.2 5.7 4.9 3, 4, 5, 8, 12, 14 1.00 1.425 0.6000 0.5500 Min 0.8000 0.8000 0.7500 1.20 1.05 1.5 1.10 1.575 0.8000 0.7500 17 Typ Max 1.2000 0.9750 0.9500 Unit V V V V V V V V A 1, 2 1, 2, 13 6 Notes 1, 2 1, 2 1, 2, 13 2 ICC U7700 U7600 U7500 A IAH, ISGNT ICC Auto-Halt & Stop-Grant HFM LFM ICC Sleep HFM LFM ICC Deep Sleep HFM LFM ICC Deeper Sleep A 3, 4, 12 ISLP A 3, 4, 12 IDSLP IDPRSLP A A 3, 4, 12 3, 4 Datasheet 33 Electrical Specifications Table 8. Symbol IDC4 dICC/DT ICCA ICCP Voltage and Current Specifications for the Intel Core 2 Duo -Ultra Low Voltage Processors (Sheet 2 of 2) Parameter ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at Processor Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable Min Typ Max 4.0 600 130 4.5 2.5 Unit A A/µs mA A A 10 11 Notes 3, 4 7, 9 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the nominal VCC. 5. 533-MHz FSB supported. 6. Instantaneous current ICC_CORE_INST of 21 A has to be sustained for short time (tINST) of 10 µs. Average current is less than maximum specified ICCDES. VR OCP threshold should be high enough to support current levels described herein. 7. Measured at the bulk capacitors on the motherboard. 8. 2-M L2 cache. 9. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 10. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 11. This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high. 12. Processor ICC requirements in Intel Dynamic Acceleration Technology mode is lesser than ICC in HFM. 13. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor is lesser than or equal to 350 mV. 14. Dynamic FSB Frequency Switching not supported. Table 9. Symbol VCCHFM VCCLFM VCCSLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for the Intel Core 2 Extreme Processors (Sheet 1 of 2) Parameter VCC at High Frequency Mode (HFM) VCC at Low Frequency Mode (LFM) VCC at Super Low Frequency Mode (SuperLFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep VCC at Intel® Enhanced Deeper Sleep Voltage Extreme Processor ICC Recommended Design Target 1.00 1.425 0.7000 0.6500 Min 1.1000 1.0000 0.9000 1.20 1.05 1.5 1.10 1.575 0.9000 0.8500 55 Typ Max 1.3750 1.1000 1.1000 Unit V V V V V V V V A 1, 2 1, 2, 7 Notes 1, 2 1, 2, 7 1, 2 2 34 Datasheet Electrical Specifications Table 9. Symbol Voltage and Current Specifications for the Intel Core 2 Extreme Processors (Sheet 2 of 2) Parameter Extreme Processor ICC for the Processor Processor Number Core Frequency/Voltage 2.80 2.60 1.20 0.80 GHz GHz GHz GHz & & & & VCCHFM VCCHFM VCCLFM VCCSLFM 55 55 37 29 29.8 21.6 29.1 21.4 26.6 20.6 14.7 13.5 600 130 4.5 2.5 Min Typ Max Unit Notes ICC X7900 X7800 A 3, 4, 5, 11, 12 IAH, ISGNT ICC Auto-Halt & Stop-Grant HFM SuperLFM ICC Sleep HFM SuperLFM ICC Deep Sleep HFM SuperLFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at Processor Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable A 3, 4 ISLP A 3, 4 IDSLP IDPRSLP IDC4 dICC/DT ICCA ICCP A A A A/µs mA A A 3, 4 3, 4 3, 4 6, 8 9 10 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the nominal VCC. 5. 800-MHz FSB Supported 6. Measured at the bulk capacitors on the motherboard. 7. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor is lesser than or equal to 350 mV. 8. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 9. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 10. This is a steady-state Icc current specification, which is applicable when both VCCP and VCC_CORE are high. 11. 4-M L2 cache. 12. Intel Dynamic Acceleration Technology not supported. Datasheet 35 Electrical Specifications Figure 3. Active VCC and ICC Loadline Intel Core 2 Duo Processors - Standard Voltage, Low Voltage and Ultra Low Voltage and Intel Core 2 Extreme Processors (PSI# Not Asserted) VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} VCC-CORE nom {HFM|LFM} 10mV= RIPPLE VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ 0 N o t e 1 / V C C - C O R E S e t P o i n t E r r o r T o l e r a n c e is p e r b e lo w : ICC-CORE max {HFM|LFM} ICC-CORE [A] Tolerance VCC-CORE VID Voltage Range --------------- -------------------------------------------------------+ /-1.5% VCC-CORE > 0.7500V +/-11.5m V 0.75000V < VCC-CORE < 0.5000V 36 Datasheet Electrical Specifications Figure 4. Deeper Sleep VCC and ICC Loadline Intel Core 2 Duo Processors - Standard Voltage and Intel Core 2 Extreme Processors (PSI# Asserted) VCC-CORE[V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {Deeper Sleep} VCC-CORE, DC max {Deeper Sleep} VCC-CORE nom {Deeper Sleep} 13mV= RIPPLE for PSI# Asserted VCC-CORE, DC min {Deeper Sleep} VCC-CORE min {Deeper Sleep} +/-VCC-CORE Tolerance = VR St. Pt. Error1/ 0 Note 1/ Deeper Sleep V Tolerance - PSI# Ripple -----------------------------+/-[(VID*1.5%) - 3 mV] +/-(11.5 mV - 3 mV) +/- (25 mV - 3 mV) CC-CORE ICC-CORE max {Deeper Sleep} Set Point Error Tolerance is per below: ICC-CORE [A] V CC-CORE VID Voltage Range -------------------------------------------------------V CC-CORE > 0.7500V 0.5000V 0.4125V < V CC-CORE < 0.7500V < V CC-CORE < 0.5000V NOTE: Deeper Sleep mode tolerance depends on VID value. Datasheet 37 Electrical Specifications Figure 5. Deeper Sleep VCC and ICC Loadline Intel Core 2 Duo Processor - Low Voltage and Ultra Low Voltage (PSI# Asserted) NOTE: Deeper Sleep mode tolerance depends on VID value. Table 10. FSB Differential BCLK Specifications Symbol VCROSS ΔVCROSS VSWING ILI Cpad Parameter Crossing Voltage Range of Crossing Points Differential Output Swing Input Leakage Current Pad Capacitance 300 -5 0.95 1.2 +5 1.45 Min 0.3 Typ Max 0.55 140 Unit V mV mV µA pF Notes1 2, 7, 8 2, 7, 5 6 3 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. For Vin between 0 V and VIH. 4. Cpad includes die capacitance only. No package parasitics are included. 5. ΔVCROSS is defined as the total variation of all crossing voltages as defined in Note 2. 6. Measurement taken from differential waveform. 7. Measurement taken from single-ended waveform. 8. Only applies to the differential rising edge (Clock rising and Clock# falling). 38 Datasheet Electrical Specifications Table 11. AGTL+ Signal Group DC Specifications Symbol VCCP GTLREF RCOMP RODT VIH VIL VOH RTT RON ILI Cpad Parameter I/O Voltage Reference Voltage Compensation Resistor Termination Resistor Input High Voltage Input Low Voltage Output High Voltage Termination Resistance Buffer On Resistance Input Leakage Current Pad Capacitance 1.6 2.1 GTLREF+0.10 -0.10 VCCP-0.10 50 22 27.23 Min 1.00 Typ 1.05 2/3 VCCP 27.5 55 VCCP 0 VCCP 55 25 VCCP+0.10 GTLREF-0.10 VCCP 61 28 ±100 2.55 27.78 Max 1.10 Unit V V 6 10 11 3,6 2,4 6 Notes1 Ω Ω V V Ω Ω µA pF 7 5 8 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that is interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that is interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull-down driver resistance. Measured at 0.31*VCCP. RON (min) = 0.4*RTT, RON (typ) = 0.455*RTT, RON (max) = 0.51*RTT. RTT typical value of 55 Ω is used for RON typ/ min/max calculations. 6. GTLREF should be generated from VCCP with a 1%-tolerance resistor divider. The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VCCP. RTT is connected to VCCP on die. 8. Specified with on die RTT and RON turned off. Vin between 0 and VCCP. 9. Cpad includes die capacitance only. No package parasitics are included. 10. This is the external resistor on the comp pins. 11. On die termination resistance measured at 0.33*VCCP. Datasheet 39 Electrical Specifications Table 12. CMOS Signal Group DC Specifications Symbol VCCP VIH VIL VOH VOL IOH IOL ILI Cpad1 Cpad2 Parameter I/O Voltage Input High Voltage Input Low Voltage CMOS Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current Pad Capacitance Pad Capacitance for CMOS Input 1.6 0.95 2.1 1.2 Min 1.00 0.7*VCCP -0.10 0.9*VCCP -0.10 1.5 1.5 Typ 1.05 VCCP 0.00 VCCP 0 Max 1.10 VCCP+0.1 0.3*VCCP VCCP+0.1 0.1*VCCP 4.1 4.1 ±100 2.55 1.45 Unit V V V V V mA mA µA pF 2 2 2 2 5 4 6 7 3 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VCCP referred to in these specifications refers to instantaneous VCCP. 3. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included. 4. Measured at 0.1*VCCP. 5. Measured at 0.9*VCCP. 6. For Vin between 0 V and VCCP. Measured when the driver is tristated. 7. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are included. Table 13. Open Drain Signal Group DC Specifications Symbol VOH VOL IOL ILO Cpad Parameter Output High Voltage Output Low Voltage Output Low Current Output Leakage Current Pad Capacitance 1.9 2.2 Min VCCP-5% 0 16 Typ VCCP Max VCCP+5% 0.20 50 ±200 2.45 Unit V V mA µA pF 2 4 5 Notes1 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2 V. 3. VOH is determined by value of the external pull-up resistor to VCCP. 4. For Vin between 0 V and VOH. 5. Cpad includes die capacitance only. No package parasitics are included. § 40 Datasheet Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information Package Mechanical Specifications The processor is available in 4-MB and 2-MB, 478-pin Micro-FCPGA packages as well as 4-MB and 2-MB, 479-ball Micro-FCBGA packages. The package mechanical dimensions, keep-out zones, processor mass specifications, and package loading specifications are shown in Figure 6 through Figure 13. The mechanical package pressure specifications are in a direction normal to the surface of the processor. This requirement is to protect the processor die from fracture risk due to uneven die pressure distribution under tilt, stack-up tolerances and other similar conditions. These specifications assume that a mechanical attach is designed specifically to load one type of processor. Intel also specifies that 15-lbf load limit should not be exceeded on any of Intel’s BGA packages so as to not impact solder joint reliability after reflow. This load limit ensures that impact to the package solder joints due to transient bend, shock, or tensile loading is minimized. The 15-lbf metric should be used in parallel with the 689-kPa (100 psi) pressure limit as long as neither limits are exceeded. Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for the thermal or mechanical solution. Please refer to the Santa Rosa Platform Mechanical Design Guide for more details. 4.1 Caution: The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors are electrically conductive so care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors and possibly damage the device or render it inactive. For E-step based processors refer the 4-MB and Fused 2-MB package drawings. For Mstep based processors refer to the 2-MB package drawings. Note: Datasheet 41 Package Mechanical Specifications and Pin Information Figure 6. h 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) B B1 H1 G1 C2 B2 H2 G2 C1 A J2 J1 Bottom View Top View 478 Pins A Front View Side View Underfill Package Substrate 0.37 MAX Die SYMBOL MILLIMETERS MIN MAX COMMENTS F2 0.65 MAX F3 2.03±0.08 C 0.65 MAX P Detail A Scale 20 B1 34.95 35.05 B2 34.95 35.05 C1 10.5 C2 13.8 F2 0.89 F3 1.903 2.163 G1 31.75 BASIC G2 31.75 BASIC H1 15.875 BASIC H2 15.875 BASIC J1 1.27 BASIC J2 1.27 BASIC P 0.255 0.355 P DIE 689 kPa W 6g Keying Pins ø0.356 M C A B ø0.254 M C A1, B1 42 Datasheet Package Mechanical Specifications and Pin Information Figure 7. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) 4X 7.00 4X 7.00 Edge Keep Out Zone 4X 4X 5.00 Corner Keep Out Zone 4X Side View Top View ø0.305±0.25 ø0.406 M C A B ø0.254 M C 13.97 6.985 1.625 1.625 13.97 6.985 1.5 Max Allowable Component Height Bottom View Datasheet 43 Package Mechanical Specifications and Pin Information Figure 8. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) B B1 H1 G1 C2 B2 H2 G2 C1 A J2 J1 Bottom View Top View 478 Pins A Front View Side View Underfill Package Substrate 0.37 MAX Die SYMBOL MILLIMETERS MIN MAX COMMENTS F2 0.65 MAX F3 2.03±0.08 C 0.65 MAX P Detail A Scale 20 B1 34.95 35.05 B2 34.95 35.05 C1 10 C2 10.3 F2 0.89 F3 1.823 2.063 G1 31.75 BASIC G2 31.75 BASIC H1 15.875 BASIC H2 15.875 BASIC J1 1.27 BASIC J2 1.27 BASIC P 0.255 0.355 P DIE 689 kPa W 6g Keying Pins ø0.356 M C A B ø0.254 M C A1, B1 44 Datasheet Package Mechanical Specifications and Pin Information Figure 9. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) 4X 7.00 4X 7.00 Edge Keep Out Zone 4X 4X 5.00 Corner Keep Out Zone 4X Side View Top View ø0.305±0.25 ø0.406 M C A B ø0.254 M C 13.97 6.985 1.625 1.625 13.97 6.985 1.5 Max Allowable Component Height Bottom View Datasheet 45 Package Mechanical Specifications and Pin Information Figure 10. 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. B B1 B H1 G1 C2 B2 H2 J2 C1 J1 G2 Top View A Bottom View 479 Balls M A Front View Detail B Scale 50 Side View Die SYMBOL B1 B2 C1 C2 F2 F3 G1 G2 H1 H2 J1 J2 M N P DIE W MILLIMETERS 34.95 35.05 34.95 35.05 10.5 13.8 0.89 1.903 2.163 31.75 BASIC 31.75 BASIC 15.875 BASIC 15.875 BASIC 1.27 BASIC 1.27 BASIC 0.61 0.69 0.6 0.8 689 kPa 6g MIN MAX COMMENTS Package Substrate Underfill F2 F3 C N Detail A Scale 20 0.203 ø0.203 L C A B ø0.071 L 46 Datasheet Package Mechanical Specifications and Pin Information Figure 11. 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) 4X 7.00 4X 7.00 Edge Keep Out Zone 4X 4X 5.00 Top View 13.97 6.985 Corner Keep Out Zone 4X Side View 1.625 1.625 13.97 6.985 0.55 Max Allowable Component Height Bottom View Datasheet 47 Package Mechanical Specifications and Pin Information Figure 12. 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. B B1 B H1 G1 C2 B2 H2 J2 C1 J1 G2 Top View A Bottom View 479 Balls M A Front View Detail B Scale 50 Side View Die SYMBOL B1 B2 C1 C2 F2 F3 G1 G2 H1 H2 J1 J2 M N P DIE W MILLIMETERS 34.95 34.95 MIN 35.05 35.05 MAX COMMENTS Package Substrate Underfill F2 F3 C N Detail A Scale 20 0.203 10 10.3 0.89 1.903 2.163 31.75 BASIC 31.75 BASIC 15.875 BASIC 15.875 BASIC 1.27 BASIC 1.27 BASIC 0.61 0.69 0.6 0.8 689 kPa 6g ø0.203 L C A B ø0.071 L 48 Datasheet Package Mechanical Specifications and Pin Information Figure 13. 2-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) 4X 7.00 4X 7.00 Edge Keep Out Zone 4X 4X 5.00 Top View 13.97 6.985 Corner Keep Out Zone 4X Side View 1.625 1.625 13.97 6.985 0.55 Max Allowable Component Height Bottom View 4.2 Processor Pinout and Pin List Table 14 shows the top view pinout of the Intel Core 2 Duo mobile processor. The pin list, arranged in two different formats, is shown in the following pages. Datasheet 49 Package Mechanical Specifications and Pin Information Table 14. 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF RESET# VSS DBSY# BR0# VSS ADS# A[9]# VSS REQ[4]# ADSTB[0 ]# VSS A[15]# A[16]# VSS A[23]# ADSTB[1 ]# VSS COMP[3] COMP[2] VSS PREQ# BPM[2]# VSS TEST5 1 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 1 of 2) 2 VSS RSVD VSS RSVD BNR# VSS TRDY# REQ[1] # VSS REQ[2] # A[13]# VSS A[8]# A[12]# VSS RSVD A[30]# VSS A[27]# A[17]# VSS A[34]# PRDY# VSS VID[6] VSS 2 3 SMI# INIT# RSVD RSVD VSS RS[0]# RS[2]# VSS REQ[3] # REQ[0] # VSS A[7]# A[10]# VSS A[19]# A[26]# VSS RSVD A[32]# VSS A[35]# TDO VSS BPM[1] # VID[4] VID[5] 3 4 VSS LINT1 IGNNE # VSS HITM# RS[1]# VSS LOCK# A[3]# VSS A[5]# RSVD VSS A[14]# A[24]# VSS A[21]# A[31]# VSS A[29]# A[33]# VSS BPM[3] # BPM[0] # VSS VID[3] 4 5 FERR# DPSLP# VSS STPCLK # DPRSTP # VSS BPRI# DEFER# VSS A[6]# A[4]# VSS RSVD A[11]# VSS A[25]# A[18]# VSS A[28]# A[22]# VSS TMS TCK VSS VID[2] VID[1] 5 6 A20M# VSS LINT0 PWRGO OD VSS RSVD HIT# VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP A[20]# VSS TDI TRST# VSS VID[0] PSI# VSS 6 VCC VCC VCC VCC VSS SENSE VCC SENSE 7 VSS VSS VSS VSS VSS VSS 8 VCC VCC VCC VCC VCC VCC 9 VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS 11 VCC VCC VCC VCC VCC VCC 12 VCC VSS VCC VSS VCC VSS 13 7 VCC VCC THERM TRIP# SLP# VCC VCC 8 VSS VSS VSS VSS VSS VSS 9 VCC VCC VCC VCC VCC VCC 10 VCC VCC VCC VCC VCC VCC 11 VSS VSS VSS VSS VSS VSS 12 VCC VCC VCC VCC VCC VCC 13 VCC VSS VCC VSS VCC VSS A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 50 Datasheet Package Mechanical Specifications and Pin Information Table 15. 14 A B C D E F G H J K L M N P R T U V W Y AA AB AC A D AE AF VSS VCC VSS VCC VSS VCC 14 VCC VCC VCC VCC VCC VCC 15 VSS VCC VSS VCC VSS VCC 15 VCC VCC VCC VCC VCC VCC The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of 2) 16 VSS VSS VSS VSS VSS VSS 17 VCC VCC VCC VCC VCC VCC 18 VCC VCC VCC VCC VCC VCC 19 VSS VSS VSS VSS VSS VSS 20 VCC VCC DBR# IERR# VCC VCC 21 BCLK[1] VSS BSEL[2] PROCHO T# VSS DRDY# VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VSS VSS VSS VSS VSS VSS 16 VCC VCC VCC VCC VCC VCC 17 VCC VCC VCC VCC VCC VCC 18 VSS VSS VSS VSS VSS VSS 19 VCC VCC DINV[3 ]# D[54]# VCC VCC 20 D[50]# D[52]# VSS D[59]# D[58]# VSS 21 22 BCLK[0] BSEL[0] VSS RSVD D[0]# VSS D[3]# D[12]# VSS D[14]# D[22]# VSS D[16]# D[26]# VSS D[37]# DINV[2]# VSS D[41]# D[32]# VSS D[51]# D[60]# VSS D[55]# D[62]# 22 23 VSS BSEL[1] TEST1 VSS D[7]# D[4]# VSS D[15]# D[11]# VSS D[20]# D[23]# VSS D[25]# D[19]# VSS D[39]# D[36]# VSS D[42]# D[45]# VSS D[63]# D[61]# VSS D[56]# 23 24 THRMDA VSS TEST3 DPWR# VSS D[1]# D[9]# VSS D[10]# D[8]# VSS D[21]# DINV[1]# VSS D[28]# D[27]# VSS D[34]# D[43]# VSS D[46]# D[33]# VSS D[49]# D[48]# DSTBP[3] # 24 25 VSS THRMDC VSS TEST2 D[6]# VSS D[5]# DINV[0]# VSS D[17]# D[29]# VSS D[31]# D[24]# VSS D[30]# D[38]# VSS D[44]# D[40]# VSS D[47]# D[57]# VSS DSTBN[3] # VSS 25 26 TEST6 VCCA VCCA VSS D[2]# D[13]# VSS DSTBP[ 0]# DSTBN[ 0]# VSS DSTBN[ 1]# DSTBP[ 1]# VSS D[18]# COMP[0 ] VSS COMP[1 ] D[35]# VSS DSTBN[ 2]# DSTBP[ 2]# VSS D[53]# GTLREF VSS TEST4 26 A B C D E F G H J K L M N P R T U V W Y A A A B AC A D AE AF Datasheet 51 Package Mechanical Specifications and Pin Information This page is intentionally left blank. 52 Datasheet Package Mechanical Specifications and Pin Information Table 16. Table 16. Pin Listing by Pin Name (Sheet 1 of 16) Pin Number J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U1 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Pin Listing by Pin Name (Sheet 2 of 16) Pin Number R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 A6 H1 M1 V1 A22 A21 E2 AD4 AD3 AD1 AC4 G5 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Source Synch Source Synch Bus Clock Bus Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input Input Input/ Output Input/ Output Output Output Input/ Output Input Pin Name A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# A20M# ADS# ADSTB[0]# ADSTB[1]# BCLK[0] BCLK[1] BNR# BPM[0]# BPM[1]# BPM[2]# BPM[3]# BPRI# Pin Name A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# Datasheet 53 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 3 of 16) Pin Number F1 B22 B23 C21 R26 U26 AA1 Y1 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 Signal Buffer Type Common Clock CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Output Output Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 16. Pin Listing by Pin Name (Sheet 4 of 16) Pin Number H23 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 Y22 AB24 V24 V26 V23 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Pin Name BR0# BSEL[0] BSEL[1] BSEL[2] COMP[0] COMP[1] COMP[2] COMP[3] D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# Pin Name D[15]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# D[32]# D[33]# D[34]# D[35]# D[36]# 54 Datasheet Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 5 of 16) Pin Number T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 16. Pin Listing by Pin Name (Sheet 6 of 16) Pin Number AD21 AC22 AD23 AF22 AC23 C20 E1 H5 H25 N24 U22 AC20 E5 B5 D24 F21 J26 L26 Y26 AE25 H26 M26 AA26 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch CMOS CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Pin Name D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# Pin Name D[59]# D[60]# D[61]# D[62]# D[63]# DBR# DBSY# DEFER# DINV[0]# DINV[1]# DINV[2]# DINV[3]# DPRSTP# DPSLP# DPWR# DRDY# DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DSTBP[0]# DSTBP[1]# DSTBP[2]# Datasheet 55 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 7 of 16) Pin Number AF24 A5 AD26 G6 E4 D20 C4 B3 C6 B4 H4 AC2 AC1 D21 AE6 D6 K3 H2 K2 J3 L1 C1 F3 F4 G3 B2 C3 D2 D3 D22 Signal Buffer Type Source Synch Open Drain Power/Other Common Clock Common Clock Open Drain CMOS CMOS CMOS CMOS Common Clock Common Clock Common Clock Open Drain CMOS CMOS Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Common Clock Common Clock Common Clock Reserved Reserved Reserved Reserved Reserved Direction Input/ Output Output Input Input/ Output Input/ Output Output Input Input Input Input Input/ Output Output Input Input/ Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input Input Table 16. Pin Listing by Pin Name (Sheet 8 of 16) Pin Number F6 M4 N5 T2 V3 D7 A3 D5 AC5 AA6 AB3 C23 D25 C24 AF26 AF1 A26 C7 A24 B25 AB5 G2 AB6 A7 A9 A10 A12 A13 A15 A17 A18 A20 AA7 AA9 AA10 AA12 Signal Buffer Type Reserved Reserved Reserved Reserved Reserved CMOS CMOS CMOS CMOS CMOS Open Drain Test Test Test Test Test Test Open Drain Power/Other Power/Other CMOS Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Output Input Input Input Input Input Output Direction Pin Name DSTBP[3]# FERR# GTLREF HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# PRDY# PREQ# PROCHOT# PSI# PWRGOOD REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# RESET# RS[0]# RS[1]# RS[2]# RSVD RSVD RSVD RSVD RSVD Pin Name RSVD RSVD RSVD RSVD RSVD SLP# SMI# STPCLK# TCK TDI TDO TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 THERMTRIP # THRMDA THRMDC TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 56 Datasheet Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 9 of 16) Pin Number AA13 AA15 AA17 AA18 AA20 AB7 AB9 AB10 AB12 AB14 AB15 AB17 AB18 AB20 AC7 AC9 AC10 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 16. Pin Listing by Pin Name (Sheet 10 of 16) Pin Number AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Datasheet 57 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 11 of 16) Pin Number E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 B26 C26 G21 J6 J21 K6 K21 M6 M21 N6 N21 R6 R21 T6 T21 V6 V21 W21 AF7 AD6 AF5 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Output Output Direction Table 16. Pin Listing by Pin Name (Sheet 12 of 16) Pin Number AE5 AF4 AE3 AF3 AE2 A2 A4 A8 A11 A14 A16 A19 A23 A25 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 Signal Buffer Type CMOS CMOS CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output Output Output Output Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCSENSE VID[0] VID[1] Pin Name VID[2] VID[3] VID[4] VID[5] VID[6] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 58 Datasheet Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 13 of 16) Pin Number AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF25 B6 B8 B11 B13 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 16. Pin Listing by Pin Name (Sheet 14 of 16) Pin Number B16 B19 B21 B24 C2 C5 C8 C11 C14 C16 C19 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F2 F5 F8 F11 F13 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Datasheet 59 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 15 of 16) Pin Number F16 F19 F22 F25 G1 G4 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 P6 P21 P24 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 16. Pin Listing by Pin Name (Sheet 16 of 16) Pin Number R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AE7 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Direction Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE Table 17. Pin Listing by Pin Number (Sheet 1 of 17) Pin Number A2 A3 A4 A5 A6 A7 Signal Buffer Type Power/Other CMOS Power/Other Open Drain CMOS Power/Other Output Input Input Direction Pin Name VSS SMI# VSS FERR# A20M# VCC 60 Datasheet Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 2 of 17) Pin Number A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Bus Clock Bus Clock Power/Other Power/Other Power/Other Test Power/Other Power/Other Source Synch Source Synch Power/Other CMOS Power/Other Power/other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input/ Output Input/ Output Input/ Output Input Input Direction Table 17. Pin Listing by Pin Number (Sheet 3 of 17) Pin Number AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Open Drain Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/ Output Input Input Input/ Output Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Name VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THRMDA VSS TEST6 COMP[2] VSS A[35]# A[33]# VSS TDI VCC VSS VCC VCC VSS VCC VCC VSS VCC Pin Name VSS VCC VCC VSS VCC D[50]# VSS D[45]# D[46]# VSS DSTBP[2]# VSS A[34]# TDO VSS TMS TRST# VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC D[52]# Datasheet 61 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 4 of 17) Pin Number AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 Signal Buffer Type Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input Output Input/ Output Input/ Output Direction Input/ Output Table 17. Pin Listing by Pin Number (Sheet 5 of 17) Pin Number AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 Signal Buffer Type Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other CMOS CMOS Power/Other Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Output Output Input/ Output Direction Input/ Output Output Pin Name D[51]# VSS D[33]# D[47]# VSS PREQ# PRDY# VSS BPM[3]# TCK VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS DINV[3]# VSS D[60]# D[63]# VSS D[57]# Pin Name D[53]# BPM[2]# VSS BPM[1]# BPM[0]# VSS VID[0] VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS D[54]# D[59]# VSS D[61]# D[49]# VSS GTLREF VSS VID[6] VID[4] VSS 62 Datasheet Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 6 of 17) Pin Number AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 Signal Buffer Type CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Test Power/Other CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Output Output Output Table 17. Pin Listing by Pin Number (Sheet 7 of 17) Pin Number AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Power/Other Test Reserved CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input/ Output Input/ Output Input/ Output Direction Pin Name VID[2] PSI# VSSSENSE VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC D[58]# D[55]# VSS D[48]# DSTBN[3]# VSS TEST5 VSS VID[5] VID[3] VID[1] VSS VCCSENSE VSS VCC VCC VSS VCC Pin Name VSS VCC VCC VSS VCC VCC VSS VCC VSS D[62]# D[56]# DSTBP[3]# VSS TEST4 RSVD INIT# LINT1 DPSLP# VSS VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS Datasheet 63 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 8 of 17) Pin Number B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 Signal Buffer Type CMOS CMOS Power/Other Power/Other Power/Other Common Clock Power/Other Reserved CMOS Power/Other CMOS Open Drain Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Power/Other Test Test Power/Other Power/Other Power/Other Reserved Reserved Power/Other Output Output Input Output Input Input Direction Output Output Table 17. Pin Listing by Pin Number (Sheet 9 of 17) Pin Number D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 Signal Buffer Type CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain Open Drain Reserved Power/Other Common Clock Test Power/Other Common Clock Common Clock Power/Other Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/ Output Input Input/ Output Input/ Output Input/ Output Output Input/ Output Direction Input Input Input Pin Name BSEL[0] BSEL[1] VSS THRMDC VCCA RESET# VSS RSVD IGNNE# VSS LINT0 THERMTRIP # VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS DBR# BSEL[2] VSS TEST1 TEST3 VSS VCCA VSS RSVD RSVD VSS Pin Name STPCLK# PWRGOOD SLP# VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS IERR# PROCHOT# RSVD VSS DPWR# TEST2 VSS DBSY# BNR# VSS HITM# DPRSTP# VSS VCC VSS VCC VCC VSS 64 Datasheet Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 10 of 17) Pin Number E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 17. Pin Listing by Pin Number (Sheet 11 of 17) Pin Number F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 Signal Buffer Type Power/Other Power/Other Power/Other Common Clock Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Common Clock Common Clock Power/Other Common Clock Common Clock Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Common Clock Common Clock Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input Input Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Name VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS D[0]# D[7]# VSS D[6]# D[2]# BR0# VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC Pin Name VCC VSS VCC DRDY# VSS D[4]# D[1]# VSS D[13]# VSS TRDY# RS[2]# VSS BPRI# HIT# VCCP D[3]# VSS D[9]# D[5]# VSS ADS# REQ[1]# VSS LOCK# DEFER# Datasheet 65 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 12 of 17) Pin Number H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K21 K22 Signal Buffer Type Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 17. Pin Listing by Pin Number (Sheet 13 of 17) Pin Number K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M21 M22 M23 M24 M25 Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Reserved Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Name VSS VSS D[12]# D[15]# VSS DINV[0]# DSTBP[0]# A[9]# VSS REQ[3]# A[3]# VSS VCCP VCCP VSS D[11]# D[10]# VSS DSTBN[0]# VSS REQ[2]# REQ[0]# VSS A[6]# VCCP VCCP D[14]# Pin Name VSS D[8]# D[17]# VSS REQ[4]# A[13]# VSS A[5]# A[4]# VSS VSS D[22]# D[20]# VSS D[29]# DSTBN[1]# ADSTB[0]# VSS A[7]# RSVD VSS VCCP VCCP VSS D[23]# D[21]# VSS 66 Datasheet Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 14 of 17) Pin Number M26 N1 N2 N3 N4 N5 N6 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P21 P22 P23 P24 P25 P26 R1 Signal Buffer Type Source Synch Power/Other Source Synch Source Synch Power/Other Reserved Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Table 17. Pin Listing by Pin Number (Sheet 15 of 17) Pin Number R2 R3 R4 R5 R6 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Reserved Source Synch Power/Other Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Name DSTBP[1]# VSS A[8]# A[10]# VSS RSVD VCCP VCCP D[16]# VSS DINV[1]# D[31]# VSS A[15]# A[12]# VSS A[14]# A[11]# VSS VSS D[26]# D[25]# VSS D[24]# D[18]# A[16]# Pin Name VSS A[19]# A[24]# VSS VCCP VCCP VSS D[19]# D[28]# VSS COMP[0] VSS RSVD A[26]# VSS A[25]# VCCP VCCP D[37]# VSS D[27]# D[30]# VSS A[23]# A[30]# VSS A[21]# Datasheet 67 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 16 of 17) Pin Number U5 U6 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 Signal Buffer Type Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Power/Other Reserved Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Table 17. Pin Listing by Pin Number (Sheet 17 of 17) Pin Number W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Y24 Y25 Y26 Signal Buffer Type Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Pin Name A[18]# VSS VSS DINV[2]# D[39]# VSS D[38]# COMP[1] ADSTB[1]# VSS RSVD A[31]# VSS VCCP VCCP VSS D[36]# D[34]# VSS D[35]# VSS A[27]# A[32]# VSS A[28]# A[20]# VCCP Pin Name D[41]# VSS D[43]# D[44]# VSS COMP[3] A[17]# VSS A[29]# A[22]# VSS VSS D[32]# D[42]# VSS D[40]# DSTBN[2]# 68 Datasheet Package Mechanical Specifications and Pin Information 4.3 Table 18. Name Alphabetical Signals Reference Signal Description (Sheet 1 of 7) Type Description A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/ write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. Input/ Output ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. A[35:3]# Input/ Output A20M# Input ADS# ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB[0]# ADSTB[1]# BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all processor FSB agents.This includes debug or performance monitoring tools. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. The arbitration is done between processor (Symmetric Agent) and (G)MCH (High Priority Agent). BNR# Input/ Output Output Input/ Output BPM[2:1]# BPM[3,0]# BPRI# Input BR0# Input/ Output Datasheet 69 Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 2 of 7) Type Description BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and are driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals corresponds to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups BSEL[2:0] Output COMP[3:0] Analog D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DINV# 0 1 2 3 Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no-connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both FSB agents. DBR# Output DBSY# Input/ Output DEFER# Input 70 Datasheet Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 3 of 7) Type Description DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent inverts the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment To Data Bus DINV[3:0]# Input/ Output Bus Signal DINV[3]# DINV[2]# DINV[1]# DINV[0]# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]# DPRSTP# Input DPRSTP# when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state. In order to return to the Deep Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the Intel 82801HBM ICH8M I/O Controller Hub based chipset. DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the Intel 82801HBM ICH8M chipset. DPWR# is a control signal used by the chipset to reduce power on the processor data bus input buffers. The processor drives this pin during dynamic FSB frequency switching. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DPSLP# Input DPWR# Input/ Output DRDY# Input/ Output DSTBN[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# Datasheet 71 Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 4 of 7) Type Description FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating point when the processor detects an unmasked floatingpoint error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it remains asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active also causes an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volumes 3A and 3B of the Intel® 64 and IA-32 Architectures Software Developer’s Manual and the Intel® Processor Identification and CPUID Instruction application note. FERR#/PBE# Output GTLREF HIT# HITM# Input Input/ Output Input/ Output GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor keeps IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST) IERR# Output IGNNE# Input INIT# Input 72 Datasheet Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 5 of 7) Type Description LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Intel® Pentium® processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it waits until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. Probe Request signal used by debug tools to request debug operation of the processor. As an output, PROCHOT# (Processor Hot) goes active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system activates the TCC, if enabled. The TCC remains active until the system deasserts PROCHOT#. By default PROCHOT# is configured as an output. The processor must be enabled via the BIOS for PROCHOT# to be configured as bidirectional. This signal may require voltage translation on the motherboard. Processor Power Status Indicator signal. This signal is asserted when the processor is in both in the Normal state (HFM to LFM) and in lower power states (Deep Sleep and Deeper Sleep). PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal remains low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. LINT[1:0] Input LOCK# Input/ Output PRDY# PREQ# Output Input PROCHOT# Input/ Output PSI# Output PWRGOOD Input REQ[4:0]# Input/ Output REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. Datasheet 73 Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 6 of 7) Type Description Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents deasserts their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. There is a 55-Ω (nominal) on die pull-up resistor on this signal. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state does not recognize snoops or interrupts. The processor recognizes only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor exits the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enters System Management Mode (SMM). An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler. If an SMI# is asserted during the deassertion of RESET#, then the processor tristates its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TEST1 and TEST2 must have a stuffing option of separate pulldown resistors to VSS. For the purpose of testability, route the TEST3 and TEST5 signals through a ground-referenced Zo=55 ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. Thermal Diode Anode. Thermal Diode Cathode. RESET# Input RS[2:0]# Input Reserved /No Connect RSVD SLP# Input SMI# Input STPCLK# Input TCK TDI TDO TEST1, TEST2, TEST3, TEST4, TEST5, TEST6 THRMDA THRMDC Input Input Output Input Other Other 74 Datasheet Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 7 of 7) Type Description The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor stops all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Processor core power supply. Processor core ground node. VCCA provides isolated power for the internal processor core PLL’s. Processor I/O Power Supply. VCC_SENSE together with VSS_SENSE are voltage feedback signals to Intel MVP-6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense voltage near the silicon with little noise. VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike some previous generations of processors, these are CMOS signals that are driven by the processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSS_SENSE together with VCC_SENSE are voltage feedback signals to Intel MVP-6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense ground near the silicon with little noise. THERMTRIP# Output TMS TRDY# Input Input TRST# VCC VSS VCCA VCCP VCC_SENSE Input Input Input Input Input Output VID[6:0] Output VSS_SENSE Output § Datasheet 75 Package Mechanical Specifications and Pin Information 76 Datasheet Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. The system/processor thermal solution should be designed so that the processor remains within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 19 through Table 20. Caution: Table 19. Symbol Operating the processor outside these limits may result in permanent damage to the processor and potentially other components in the system. Power Specifications for the Intel Core 2 Duo Processor - Standard Voltage Processor Number T7800 T7700 T7500 T7300 T7250 T7100 Core Frequency & Voltage 2.6 GHz & HFM VCC 2.4 GHz & HFM VCC 2.2 GHz & HFM VCC 2.0 GHz & HFM VCC 2.0 GHz & HFM VCC 1.8 GHz & HFM VCC 1.2 GHZ & LFM VCC 0.80 GHZ & SuperLFM VCC Thermal Design Power 35 35 35 35 35 35 25 12 Min Typ Max 13.5 6.9 12.9 6.7 7.7 4.3 2.0 1.2 0 100 W W °C 2, 8 2, 8 3, 4 W 2, 5, 8 W 2, 5, 7 Unit W 2, 5, 7 W 1, 4, 5, 6, 9 1, 4, 5, 6, 9 1, 4, 5, 6, 9 1, 4, 5, 6, 10 Unit Notes TDP Symbol PAH, PSGNT at HFM VCC at SuperLFM VCC Sleep Power PSLP at HFM VCC at SuperLFM VCC Deep Sleep Power PDSLP PDPRSLP PDC4 TJ at HFM VCC at SuperLFM VCC Deeper Sleep Power Parameter Auto Halt, Stop Grant Power Intel® Enhanced Deeper Sleep Power Junction Temperature NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. Datasheet 77 Thermal Specifications and Design Considerations 5. 6. 7. 8. 9. 10. Processor TDP requirements in Intel Dynamic Acceleration Technology mode is lesser than TDP in HFM. At Tj of 100oC At Tj of 50oC At Tj of 35oC 4-M L2 cache 2-M L2 cache Table 20. Symbol Power Specifications for the Intel Core 2 Duo Processor - Low Voltage Processor Number L7700 L7500 Core Frequency & Voltage 1.8 GHz & HFM VCC 1.6 GHz & HFM VCC 1.4 GHz & HFM VCC 1.2 GHZ & LFM VCC 0.80 GHZ & SuperLFM VCC Thermal Design Power 17 17 17 16.1 10.0 Min Typ Max 5.6 3.9 5.3 3.6 2.8 2.3 1.3 0.8 0 100 W W °C 2, 8 2, 8 3, 4 W 2, 5, 8 W 2, 5, 7 Unit W 2, 5, 7 W 1, 4, 5, 6, 9 Unit Notes TDP L7300 Symbol PAH, PSGNT at HFM VCC at SuperLFM VCC Sleep Power PSLP at HFM VCC at SuperLFM VCC Deep Sleep Power PDSLP PDPRSLP PDC4 TJ at HFM VCC at SuperLFM VCC Deeper Sleep Power Parameter Auto Halt, Stop Grant Power Intel® Enhanced Deeper Sleep Power Junction Temperature NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. Processor TDP requirements in Intel Dynamic Acceleration Technology mode is lesser than TDP in HFM. 6. At Tj of 100oC. 7. At Tj of 50oC. 8. At Tj of 35oC. 9. 4-M L2 cache. 78 Datasheet Thermal Specifications and Design Considerations Table 21. Symbol Power Specifications for the Intel Core 2 Duo Processor - Ultra Low Voltage Processor Number U7700 U7600 U7500 Core Frequency & Voltage 1.33 GHz & HFM VCC 1.20 GHz & HFM VCC 1.06 GHz & HFM VCC 0.80 GHZ & LFM VCC Parameter Auto Halt, Stop Grant Power at HFM VCC at LFM VCC Sleep Power at HFM VCC at LFM VCC Deep Sleep Power 3.1 2.6 3.0 2.5 1.5 1.3 1.0 0.7 0 100 W W °C 2, 8 2, 8 3, 4 W 2, 5, 8 W 2, 5, 7 W 2, 5, 7 Min Thermal Design Power 10 10 10 9.2 Typ Max Unit W 1, 4, 5, 6, 9 Unit Notes TDP Symbol PAH, PSGNT PSLP PDSLP PDPRSLP PDC4 TJ at HFM VCC at LFM VCC Deeper Sleep Power Intel Enhanced Deeper Sleep Power Junction Temperature NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. Processor TDP requirements in Intel Dynamic Acceleration Technology mode is lesser than TDP in HFM. 6. At Tj of 100oC. 7. At Tj of 50oC. 8. At Tj of 35oC. 9. 2-M L2 cache. Datasheet 79 Thermal Specifications and Design Considerations Table 22. Symbol Power Specifications for the Intel Core 2 Extreme Processor Processor Number X7900 X7800 Core Frequency & Voltage 2.8 GHz & HFM VCC 2.6 GHz & HFM VCC 1.2 GHZ & LFM VCC 0.80 GHZ & SuperLFM VCCc Parameter Auto Halt, Stop Grant Power at HFM VCC at SuperLFM VCC Sleep Power at HFM VCC at SuperLFM VCC Deep Sleep Power 15.7 9.3 15.0 9.1 9.5 6.0 3.0 2.5 0 100 W W °C 2, 8 2, 8 3, 4 W 2, 5, 8 W 2, 5, 7 W 2, 5, 7 Min Thermal Design Power 44 44 35 27 Typ Max Unit W 1, 4, 5, 6, 9 Unit Notes TDP Symbol PAH, PSGNT PSLP PDSLP PDPRSLP PDC4 TJ at HFM VCC at SuperLFM VCC Deeper Sleep Power Intel Enhanced Deeper Sleep Power Junction Temperature NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. Intel Dynamic Acceleration mode is not supported. 6. At Tj of 100°C. 7. At Tj of 50oC. 8. At Tj of 35°C. 9. 4-M L2 cache. 5.1 Thermal Specifications The processor incorporates three methods of monitoring die temperature: • Thermal Diode • Intel Thermal Monitor • Digital Thermal Sensor 80 Datasheet Thermal Specifications and Design Considerations 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to ground. The thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor MSR and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage recommendation when the PROCHOT# signal is not asserted. The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals does not reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time-based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change. Offset between the thermal diode-based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of the thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the processor Model Specific Register (MSR). Table 23 to Table 26 provide the diode interface and specifications. The diode model parameters apply to the traditional thermal sensors that use the diode equation to determine the processor temperature. Transistor model parameters have been added to support thermal sensors that use the transistor equation method. The Transistor model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. Contact your external sensor supplier for recommendations. The thermal diode is separate from the Intel Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor. Table 23. Thermal Diode Interface Signal Name THERMDA THERMDC Pin/Ball Number A24 A25 Signal Description Thermal diode anode Thermal diode cathode Datasheet 81 Thermal Specifications and Design Considerations Table 24. Thermal Diode Parameters Using Diode Model Symbol IFW n RT Parameter Forward Bias Current Diode Ideality Factor Series Resistance Min 5 1.000 2.79 1.009 4.52 Typ Max 200 1.050 6.24 Ω Unit µA Notes 1 2, 3, 4 2, 3, 5 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. Characterized across a temperature range of 50-100°C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW = IS * (e qV /nkT D –1) 5. where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature. RT, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N] where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic charge. 82 Datasheet Thermal Specifications and Design Considerations Table 25. Thermal Diode Parameters Using Transistor Model Symbol IFW IE nQ Beta RT Series Resistance Parameter Forward Bias Current Emitter Current Transistor Ideality Min 5 5 0.997 0.3 2.79 4.52 1.001 Typ Max 200 200 1.005 0.760 6.24 Ω Unit μA μA Notes 1,2 1 3,4,5 3,4 3,6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 24. 3. Characterized across a temperature range of 50-100°C. 4. Not 100% tested. Specified by design characterization. 5. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current: IC = IS * ( e qV BE /n kT Q –1) 6. where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin). The series resistance, RT, provided in the Diode Model Table (Table 24) can be used for more accurate readings as needed. When calculating a temperature based on the thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 24. In most sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode, the ideality value (also called ntrim) is 1.000. Given that most diodes are not perfect, the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. If the processor diode ideality deviates from that of the ntrim, each calculated temperature offsets by a fixed amount. This temperature offset can be calculated with the equation: Terror(nf) = Tmeasured * (1 - nactual/ntrim) where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing device. 5.1.2 Thermal Diode Offset In order to improve the accuracy of the diode-based temperature measurements, a temperature offset value (specified as Toffset) is programmed in the processor MSR which contains thermal diode characterization data. During manufacturing each processor thermal diode is evaluated for its behavior relative to the theoretical diode. Using the equation above, the temperature error created by the difference ntrim and the actual ideality of the particular processor is calculated. Datasheet 83 Thermal Specifications and Design Considerations If the ntrim value used to calculate the Toffset differs from the ntrim value used to in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the ntrim as defined in the temperature sensor manufacturer’s datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 26. Table 26. Thermal Diode ntrim and Diode Correction Toffset Symbol ntrim Parameter Diode Ideality used to calculate Toffset Value 1.01 5.1.3 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An underdesigned thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic mode and on-demand mode. If both modes are activated, automatic mode takes precedence. There are two automatic modes called Intel Thermal Monitor 1 and Intel Thermal Monitor 2. These modes are selected by writing values to the MSRs of the processor. After automatic mode is enabled, the TCC activates only when the internal die temperature reaches the maximum allowed value for operation. When Intel Thermal Monitor 1 is enabled and a high temperature situation exists, the clocks modulates by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and decreases linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance decreases by the same amount as the duty cycle when the TCC is active. When Intel Thermal Monitor 2 is enabled and a high temperature situation exists, the processor performs an Enhanced Intel SpeedStep Technology transition to the LFM. When the processor temperature drops below the critical level, the processor makes an Enhanced Intel SpeedStep Technology transition to the last requested operating point. The processor also supports Enhanced Multi Threaded Thermal Monitoring (EMTTM). 84 Datasheet Thermal Specifications and Design Considerations EMTTM is a processor feature that enhances Intel Thermal Monitor 2 with a processor throttling algorithm known as Adaptive Intel Thermal Monitor 2. Adaptive Intel Thermal Monitor 2 transitions to intermediate operating points, rather than directly to the LFM, once the processor has reached its thermal limit and subsequently searches for the highest possible operating point. Please ensure this feature is enabled and supported in the BIOS. Also with EMTTM enabled, the operating system can request the processor to throttling to any point between Intel Dynamic Acceleration Technology frequency and SuperLFM frequency as long as these features are enabled in the BIOS and supported by the processor. The Intel Thermal Monitor automatic mode and Enhanced Multi Threaded Thermal Monitoring must be enabled through BIOS for the processor to be operating within specifications. Note: Intel Thermal Monitor 1, Intel Thermal Monitor 2 and EMTTM features are collectively referred to as Adaptive Thermal Monitoring features. Intel recommends Intel Thermal Monitor 1 and 2 be enabled on the processors. Intel Thermal Monitor 1 and 2 can co-exist within the processor. If both Intel Thermal Monitor 1 and 2 bits are enabled in the auto-throttle MSR, Intel Thermal Monitor 2 takes precedence over Intel Thermal Monitor 1. However, if Force Intel Thermal Monitor 1 over Intel Thermal Monitor 2 is enabled in MSRs via BIOS and Intel Thermal Monitor 2 is not sufficient to cool the processor below the maximum operating temperature, then Intel Thermal Monitor 1 also activates to help cool down the processor. If a processor load based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when a Intel Thermal Monitor 2 period is active, there are two possible results: 1. If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is higher than the Intel Thermal Monitor 2 transition-based target frequency, the processor load-based transition deferrs until the Intel Thermal Monitor 2 event has been completed. 2. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the Intel Thermal Monitor 2 transition-based target frequency, the processor transitions to the processor load-based Enhanced Intel SpeedStep Technology target frequency point. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC activates immediately independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode takes precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. PROCHOT# is not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states, hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor Datasheet 85 Thermal Specifications and Design Considerations junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3. In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification. 5.1.4 Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor (DTS) that can be read via an MSR (no I/O interface). Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor. The DTS is only valid while the processor is in the normal operating state (the Normal package level low power state). Unlike traditional thermal devices, the DTS will output a temperature relative to the maximum supported operating temperature of the processor (TJ,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ,max. Catastrophic temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The DTS-relative temperature readout corresponds to the Intel Thermal Monitor 1/Intel Thermal Monitor 2 trigger point. When the DTS indicates maximum processor core temperature has been reached, the Intel Thermal Monitor 1 or 2 hardware thermal control mechanism will activate. The DTS and Intel Thermal Monitor 1/Intel Thermal Monitor 2 temperature may not correspond to the thermal diode reading because the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach, and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications. Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual for specific register and programming details. 86 Datasheet Thermal Specifications and Design Considerations 5.1.5 Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s Intel Thermal Monitor 1 or 2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt. 5.1.6 PROCHOT# Signal Pin An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If Intel Thermal Monitor 1 or 2 is enabled, then the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual for specific register and programming details. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from overheating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. Only a single PROCHOT# pin exists at a package level of the processor. When either core's thermal sensor trips, the PROCHOT# signal will be driven by the processor package. If only Intel Thermal Monitor 1 is enabled, PROCHOT# will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated. If Intel Thermal Monitor 2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed Intel Thermal Monitor 2 performance state. It is important to note that Intel recommends both Intel Thermal Monitor 1 and 2 to be enabled. When PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is enabled on both cores, then both processor cores will have their core clocks modulated. If Intel Thermal Monitor 2 is enabled on both cores, then both processor cores will enter the lowest programmed Intel Thermal Monitor 2 performance state. It should be noted that Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2, enabled via BIOS, does not have any effect on external PROCHOT#. If PROCHOT# is driven by an external agent when Intel Thermal Monitor 1, Intel Thermal Monitor 2, and Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2 are all enabled, then the processor will still apply only Intel Thermal Monitor 2. PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. § Datasheet 87