U1400

Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process Datasheet January 2007 Document Number: 309221-006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Core™ Duo processor and the Intel® Core™ Solo processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel Core Duo, Intel Core Solo, Pentium, Intel SpeedStep, MMX and the Intel logo are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006 - 2007, Intel Corporation. All rights reserved. 2 Datasheet Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 9 1.2 References ......................................................................................................... 9 Low Power Features ................................................................................................ 11 2.1 Clock Control and Low Power States .................................................................... 11 2.1.1 Core Low-Power States ........................................................................... 13 2.1.1.1 C0 State .................................................................................. 13 2.1.1.2 C1/AutoHALT Powerdown State .................................................. 13 2.1.1.3 C1/MWAIT Powerdown State ...................................................... 13 2.1.1.4 Core C2 State........................................................................... 13 2.1.1.5 Core C3 State........................................................................... 14 2.1.1.6 Core C4 State........................................................................... 14 2.1.2 Package Low Power States ...................................................................... 14 2.1.2.1 Normal State............................................................................ 14 2.1.2.2 Stop-Grant State ...................................................................... 14 2.1.2.3 Stop Grant Snoop State ............................................................. 15 2.1.2.4 Sleep State .............................................................................. 15 2.1.2.5 Deep Sleep State ...................................................................... 16 2.1.2.6 Deeper Sleep State ................................................................... 16 2.2 Enhanced Intel SpeedStep® Technology .............................................................. 17 2.3 Extended Low Power States ................................................................................ 18 2.4 FSB Low Power Enhancements ............................................................................ 19 2.5 Processor Power Status Indicator (PSI#) Signal..................................................... 19 Electrical Specifications ........................................................................................... 21 3.1 Power and Ground Pins ...................................................................................... 21 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................... 21 3.3 Voltage Identification ......................................................................................... 21 3.4 Catastrophic Thermal Protection .......................................................................... 24 3.5 Signal Terminations and Unused Pins ................................................................... 25 3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 25 3.7 FSB Signal Groups............................................................................................. 25 3.8 CMOS Signals ................................................................................................... 27 3.9 Maximum Ratings.............................................................................................. 27 3.10 Processor DC Specifications ................................................................................ 28 Package Mechanical Specifications and Pin Information .......................................... 41 4.1 Package Mechanical Specifications ....................................................................... 41 4.1.1 Package Mechanical Drawings .................................................................. 41 4.1.2 Processor Component Keep-Out Zones ...................................................... 46 4.1.3 Package Loading Specifications ................................................................ 46 4.1.4 Processor Mass Specifications .................................................................. 46 4.2 Processor Pinout and Pin List .............................................................................. 47 4.3 Alphabetical Signals Reference ............................................................................ 49 Thermal Specifications and Design Considerations .................................................. 79 5.1 Thermal Specifications ....................................................................................... 85 5.1.1 Thermal Diode ....................................................................................... 85 5.1.2 Thermal Diode Offset .............................................................................. 87 5.1.3 Intel® Thermal Monitor........................................................................... 87 5.1.4 Digital Thermal Sensor (DTS)................................................................... 89 5.1.5 Out of Specification Detection .................................................................. 90 2 3 4 5 Datasheet 3 5.1.6 PROCHOT# Signal Pin .............................................................................90 Figures 1 2 3 4 5 6 7 8 9 10 Package-Level Low Power States ................................................................................12 Core Low Power States..............................................................................................12 Active VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and Intel Core Solo Processor SV ......................................................................................35 Deeper Sleep VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and Intel Core Solo Processor SV ......................................................................................36 Active VCC and ICC Loadline for Intel Core Solo Processor ULV .......................................37 Deeper Sleep VCC and ICC Loadline for Intel Core Solo Processor ULV ..............................38 Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................................................42 Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................................................43 Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ................................................44 Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ...............................................45 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Coordination of Core-Level Low Power States at the Package Level .................................11 Voltage Identification Definition ..................................................................................21 BSEL[2:0] Encoding for BCLK Frequency......................................................................25 FSB Pin Groups ........................................................................................................26 Processor DC Absolute Maximum Ratings.....................................................................27 Voltage and Current Specifications for Intel Core Duo Processor SV (Standard Voltage) .....28 Voltage and Current Specifications for Intel Core Solo Processor SV (Standard Voltage) .....30 Voltage and Current Specifications for Intel Core Duo Processor LV (Low Voltage) .............31 Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage (ULV) ........32 Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra Low Voltage) ...33 FSB Differential BCLK Specifications ............................................................................39 AGTL+ Signal Group DC Specifications ........................................................................39 CMOS Signal Group DC Specifications..........................................................................40 Open Drain Signal Group DC Specifications ..................................................................40 The Coordinates of the Processor Pins as Viewed from the Top of the Package ..................47 The Coordinates of the Processor Pins as Viewed from the Top of the Package .................48 Signal Description.....................................................................................................49 Pin Listing by Pin Name .............................................................................................59 Pin Listing by Pin Number ..........................................................................................69 Power Specifications for the Intel Core Duo Processor SV (Standard Voltage) ...................80 Power Specifications for the Intel Core Solo Processor SV (Standard Voltage) ...................81 Power Specifications for the Intel Core Duo Processor LV (Low Voltage) ...........................82 Power Specifications for the Intel Core Duo Processor, Ultra Low Voltage (ULV) ................83 Power Specifications for the Intel Core Solo Processor ULV (Ultra Low Voltage) .................84 Thermal Diode Interface ............................................................................................85 Thermal Diode Parameters using Diode Mode ...............................................................86 Thermal Diode Parameters using Transistor Mode .........................................................86 Thermal Diode ntrim and Diode Correction Toffset..........................................................87 4 Datasheet Revision History Revision -001 Initial Release • • • • -002 Added references to ULV processor throughout the document Replaced references to the terminology Deep C4 voltage with Intel® Enhanced Deeper Sleep Voltage throughout the document. Replaced references to Enhanced Low Power states with CxE Low Power States Section 3.10 — Included Table 10 Voltage and Current Specifications for Intel Core Solo Processor ULV — Included Figure 5 Active VCC and ICC Load Line for Intel Core Solo Processor ULV — Included Figure 6 Deeper Sleep VCC and ICC Load Line for Intel Core Solo Processor ULV Chapter 5 — Included Table 24 Power Specifications for the Intel Core Solo Processor ULV (Ultra Low Voltage) Added Intel® Core™ Duo Processor T2300E and Intel® Core™ Solo Processor T1400 specifications. Added references to Intel Core Duo Processor, Ultra Low Voltage (ULV) throughout the document CxE low power states now also referred to as Extended Low Power States Section 3.10 — Updated Table 6 - Added Icc spec for T2700 — Included Table 9 Voltage and Current Specifications Intel Core Duo Processor, Ultra Low Voltage (ULV) Chapter 5 — Updated Table 20 - Added TDP for T2700 — Included Table 23 - Power Specification for Intel Core Duo Processor Ultra Low Voltage (ULV) In Chapter 3: — Added L2500 processor specifications to Table 8. — Added U2400 processor specifications to Table 9. In Chapter 5: — Added L2500 processor power specifications to Table 22. — Added U2400 processor power specifications to Table 23. In Chapter 3: — Added U1500 processor specifications to Table 10. In Chapter 5: — Added U1500 processor power specifications to Table 24. Description Date January 2006 April 2006 • -003 • • • • May 2006 -004 • June 2006 • -005 • September 2006 • -006 • January 2007 § Datasheet 5 6 Datasheet Introduction 1 Introduction The Intel® CoreTM Duo processor and the Intel® CoreTM Solo processor are built on Intel’s next generation 65 nanometer process technology with copper interconnect. The Intel Core Solo processor refers to a single core processor and the Intel Core Duo processor refers to a dual core processor. This document provides specifications for all Intel Core Duo processor and Intel Core Solo processor in standard voltage (SV), low voltage (LV) and ultra low voltage (ULV) products. Note: All instances of the “processor” in this document refer to the Intel Core Duo processor and Intel Core Solo processor with 2-MB L2 cache, unless specified otherwise. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number for details. The following list provides some of the key features on this processor: • First dual core processor for mobile • Supports Intel® Architecture with Dynamic Execution • On-die, primary 32-KB instruction cache and 32-KB write-back data cache • On-die, 2-MB second level cache with Advanced Transfer Cache Architecture • Data Prefetch Logic • Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3) • The Intel Core Duo processor and Intel Core Solo processor standard voltage and low voltage processors are offered at 667-MHz FSB • The Intel Core Duo processor and Intel Core Solo processor ultra low voltage are offered at 533-MHz FSB • Advanced power management features including Enhanced Intel SpeedStep® Technology • Digital thermal sensor (DTS) • The Intel Core Duo processor and Intel Core Solo processor standard voltage are offered in both the Micro-FCPGA and the Micro-FCBGA packages • Intel Core Duo processor low voltage is offered only in the Micro-FCBGA package • The Intel Core Duo processor and Intel Core Solo processor ultra low voltage are offered only in Micro-FCBGA package • Execute Disable Bit support for enhanced security • Intel® Virtualization Technology • Intel® Enhanced Deeper Sleep and Dynamic Cache Sizing The processor maintains support for MMX™ technology, Streaming SIMD instructions, and full compatibility with IA-32 software. The processor features on-die, 32-KB, Level 1 instruction and data caches and a 2-MB level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before the L1 cache requests occurs, resulting in reduced bus cycle penalties. The processor includes the Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, the Writer Order Buffer depth is enhanced to help with the write-back latency performance. Datasheet 7 Introduction In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new instructions which extend the capabilities of Intel processor technology further. These new instructions are called Streaming SIMD Extensions 3 (SSE3). 3D graphics and other entertainment applications, such as gaming, will have the opportunity to take advantage of these new instructions as platforms with the processor and SSE3 become available in the market place. The processor’s FSB utilizes a split-transaction, deferred reply protocol. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock. The 4X data bus can deliver data four times per bus clock and is referred as “quad-pumped” or 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and the 2X address bus provide a data bus bandwidth of up to 5.33 GB/second. The FSB uses Advanced Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling technology with low power enhancements. The processor features Enhanced Intel SpeedStep Technology, which enables real-time dynamic switching between multiple voltage and frequency points. The processor features the Auto Halt, Stop Grant, Deep Sleep, and Deeper Sleep low power C-states. The processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket. The processor supports the Execute Disable Bit capability. This feature, combined with a support operating system, allows memory to be marked as executable or non executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® Architecture Software Developer's Manual for more detailed information. Intel Virtualization Technology is a set of hardware enhancements to Intel server and client systems that combined with the appropriate software, will enable enhanced virtualization robustness and performance for both enterprise and consumer uses. Intel Virtualization Technology forms the foundation of Intel technologies focused on improved virtualization, safer computing, and system stability. For client systems, Intel Virtualization Technology’s hardware-based isolation helps provide the foundation for highly available and more secure client virtualization partitions. 8 Datasheet Introduction 1.1 Terminology Term Definition A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Refers to the interface between the processor and system core logic (also known as the chipset components). Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors. # Front Side Bus (FSB) AGTL+ 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Chipset references in this document are to the Mobile Intel® 945 Express Chipset family unless specified otherwise. Document Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process Specification Update Mobile Intel® 945 Express Chipset Family Datasheet Mobile Intel® 945 Express Chipset Family Specification Update Intel® I/O Controller Hub 7 (ICH7) Family Datasheet Intel® I/O Controller Hub 7 (ICH7) Family Specification Update Intel® Architecture Software Developer's Manual Volume 1 Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide AP-485, Intel® Processor Identification and CPUID Instruction Application Note 253665 253666 253667 253668 253669 241618 Document Number 309222 309219 309220 307013 307014 § Datasheet 9 Introduction 10 Datasheet Low Power Features 2 2.1 Low Power Features Clock Control and Low Power States The Intel Core Duo processor and Intel Core Solo processor support low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states. Refer to Figure 2 for a visual representation of the core low power states for the Intel Core Duo processor and Intel Core Solo processor. When both cores coincide in a common core low power state, the central power management logic ensures the Intel Core Duo processor enters the respective package low power state by initiating a P_LVLx (P_LVL2, P_LVL3, and P_LVL4) I/O read to the Mobile Intel 945 Express Chipset family. Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep, Deep Sleep, and Deeper Sleep. Refer Figure 1 for a visual representation of the package low-power states for the Intel Core Duo processor and Intel Core Solo processor and to Table 1 for a mapping of core low power states to package low power states. The processor implements two software interfaces for requesting low power states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The monitor address does not need to be setup before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured in a software programmable MSR. When software running on a core requests the C4 state, that core enters the core C4 state, which is identical to the core C3 state. When both cores have requested C4 then the Intel Core Duo processor will enter the Deeper Sleep state. If a core encounters a chipset break event while STPCLK# is asserted, then it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the Intel Core Duo processor should return to the Normal state. Same mechanism is also applicable for the Intel Core Solo processor. Table 1. Coordination of Core-Level Low Power States at the Package Level Single Core Normal Normal Stop Grant Deep Sleep Dual Core: Core1 State C0 Normal Normal Normal Normal C11 Normal Normal Normal Normal C2 Normal Normal Stop Grant Stop Grant C3 Normal Normal Stop Grant Deep Sleep C4 Normal Normal Stop Grant Deep Sleep Deeper Sleep / Intel® Enhanced Deeper Sleep Resolved Package State C0 Core0 / Functional Core State C1† C2 C3 C4 Deeper Sleep Normal Normal Stop Grant Deep Sleep NOTE: 1. AutoHALT or MWAIT/C1. Datasheet 11 Low Power Features Figure 1. Package-Level Low Power States STPCLK# asserted SLP# asserted DPSLP# asserted DPRSTP# asserted Normal STPCLK# de-asserted Stop Grant SLP# de-asserted Sleep DPSLP# de-asserted Deep Sleep DPRSTP# de-asserted Deeper † Sleep Snoop serviced Snoop occurs Stop Grant Snoop † — Deeper Sleep includes the Deeper Sleep and the Intel Enhanced Deeper Sleep state. Figure 2. Core Low Power States Stop Grant STPCLK# asserted STPCLK# de-asserted STPCLK# de-asserted STPCLK# asserted C1/ MWAIT STPCLK# de-asserted STPCLK# asserted Core state break MWAIT(C1) C1/Auto Halt HLT instruction Halt break C0 Core State break P_LVL4 or MWAIT(C4) P_LVL2 or MWAIT(C2) Core state break Core P_LVL3 or state MWAIT(C3) break C4 †‡ C2 † C3 † halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) † — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ — Core C4 state supports the package level Intel Enhanced Deeper sleepstate. 12 Datasheet Low Power Features 2.1.1 2.1.1.1 Core Low-Power States C0 State This is the normal operating state for the Intel Core Duo processor and Intel Core Solo processor. 2.1.1.2 C1/AutoHALT Powerdown State C1/AutoHALT is a low power state entered when the processor core executes the HALT instruction. The processor core will transition to the C0 state upon the occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® Architecture Software Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can generate an STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Powerdown state, the dual core processor will process bus snoops and snoops from the other core, and the single core processor will process only the bus snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the AutoHALT Powerdown state. 2.1.1.3 C1/MWAIT Powerdown State MWAIT is a low power state entered when the processor core executes the MWAIT instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the Intel® Architecture Software Developer's Manual, Volumes 2A/2B: Instruction Set Reference, for more information. 2.1.1.4 Core C2 State Individual cores of the Intel Core Duo processor and Intel Core Solo processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in C2 state, the dual core processor will process bus snoops and snoops from the other core, and the single core processor will process only the bus snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the C2 state. Datasheet 13 Low Power Features 2.1.1.5 Core C3 State Core C3 state is a very low power state the processor core can enter while maintaining context. Individual cores of the Intel Core Duo processor and Intel Core Solo processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual core processor accesses cacheable memory. The processor core will transition to the C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself. 2.1.1.6 Core C4 State Individual cores of the Intel Core Duo processor and Intel Core Solo processor can enter the C4 state by initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core behavior in the C4 state is identical to the behavior in the C3 state. The only difference is that if both processor cores are in C4, then the central power management logic will request that the entire dual core processor enter the Deeper Sleep package low power state (see Section 2.1.2.5). The single core processor would be put into the Deeper Sleep State in C4 state if the low power state coordination logic is enabled. To enable the package level Intel Enhanced Deeper Sleep Low Voltage, Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software programmable MSR. 2.1.2 Package Low Power States The package level low power states are applicable for the Intel Core Duo processor as well as the Intel Core Solo processor. The package level low power states are described in Section 2.1.2.1 through Section Section 2.1.2.6. 2.1.2.1 Normal State This is the normal operating state for the processor. The processor enters the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state. 2.1.2.2 Stop-Grant State When the STPCLK# pin is asserted, each core of the Intel Core Duo processor and Intel Core Solo processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current lowpower state. When the STPCLK# pin is deasserted, each core returns to its previous core low power state. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. 14 Datasheet Low Power Features RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 450 µs prior to RESET# deassertion. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#. While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state. The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire dual core processor should return to the Normal state. A transition to the Stop Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) will occur with the assertion of the SLP# signal. 2.1.2.3 Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor will return to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched. 2.1.2.4 Sleep State The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 2.1.2.5.) While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur. Datasheet 15 Low Power Features 2.1.2.5 Deep Sleep State Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset-based platforms with the CK410M clock chip are as follows: • Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep. • Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. 2.1.2.6 Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but reduces core voltage to one of two lower levels. One lower core voltage level is achieved by entering the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper Sleep state of Deeper Sleep state. The Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.2 for further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state. In response to entering Deeper Sleep, the processor will drive the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins. Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point. 2.1.2.6.1 Intel Enhanced Deeper Sleep State Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power saving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters Intel Enhanced Deeper Sleep state: • The last core entering C4 issues a P_LVL4 I/O read or an MWAIT(C4) instruction and then progressively reduces the L2 cache to zero. • The processor drives the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID[6:0] pins. 16 Datasheet Low Power Features 2.1.2.6.2 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions: • The second core is already in C4 and the Intel Enhanced Deeper Sleep state is enabled (as specified in Section 2.1.2.6.1). • The C0 timer, which tracks continuous residency in the Normal package state, has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed. • The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold. If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing decisions. Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways. If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not the one currently entering the interrupt routine) requests the C1, C2, or C3 states, then the whole L2 will be expanded when the next INTR event would occur. L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled, then the processor does not enter the Intel Enhanced Deeper Sleep state since the L2 cache remains valid and in full size. 2.2 Enhanced Intel SpeedStep® Technology Intel Core Duo processor and Intel Core Solo processor feature Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage/frequency operating points provide optimal performance at the lowest power. • Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model Specific Registers). — If the target frequency is higher than the current frequency, VCC is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency. — If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition completes. • The processor controls voltage ramp rates internally to ensure glitch free transitions. • Low transition latency and large number of transitions possible per second. — Processor core (including L2 cache) is unavailable for up to 10 μs during the frequency transition Datasheet 17 Low Power Features — The bus protocol (BNR# mechanism) is used to block snooping • Improved Intel® Thermal Monitor mode. — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency/ voltage specified in a software programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency/voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management. • Enhanced thermal management features. — Digital thermal sensor and thermal interrupts — TM1 in addition to TM2 in case of non successful TM2 transition. — dual core thermal management synchronization. Each core in the Intel Core Duo processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage then the Intel Core Duo processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests then the Intel Core Duo processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage. 2.3 Extended Low Power States The Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state. Instead of directly transitioning into the package low power states, the extended low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the package low power states. The processor implements two software interfaces for requesting extended low power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring a software programmable MSR bit to automatically promote package low power states to extended low power states. Note: C2E and C4E must be enabled via the BIOS for the processor to remain within specification. Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states. C4E is an exception to this rule when the Hard C4E configuration is enabled in a software programmable MSR bit. This C4E low power state configuration will lower core voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency. The transition to the lowest operating point or back to the original software requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state 18 Datasheet Low Power Features entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases. 2.4 FSB Low Power Enhancements The processor incorporates FSB low power enhancements: • Dynamic FSB Power Down • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On Die Termination disabling • Low VCCP (I/O termination voltage) The Intel Core Duo processor and Intel Core Solo processor incorporate the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times. 2.5 Processor Power Status Indicator (PSI#) Signal The Intel Core Duo processor and Intel Core Solo processor incorporate the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and improved battery life. The algorithm that the Intel Core Duo processor and Intel Core Solo processor use for determining when to assert PSI# is different from the algorithm used in previous Intel® Pentium® M processors. § Datasheet 19 Low Power Features 20 Datasheet Electrical Specifications 3 3.1 Electrical Specifications Power and Ground Pins For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please contact your Intel representative for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Intel Core Duo processor and Intel Core Solo processors’ core frequency is a multiple of the BCLK[1:0] frequency. The processor uses a differential clocking implementation. 3.3 Voltage Identification The processor uses seven voltage identification pins, VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to lowvoltage level. Table 2. Voltage Identification Definition (Sheet 1 of 4) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 Datasheet 21 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 4) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 22 Datasheet Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 4) VID6 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 VID2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 Datasheet 23 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 4 of 4) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 3.4 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. 24 Datasheet Electrical Specifications 3.5 Signal Terminations and Unused Pins All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected. The TEST1 pin must have a stuffing option connection to VSS. The TEST2 pin must have a 51 Ω ±5%, pull-down resistor to VSS. 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the Mobile Intel 945 Express Chipset family on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3: Table 3. BSEL[2:0] Encoding for BCLK Frequency BSEL[2] L L L L BSEL[1] L L H H BSEL[0] L H L H BCLK Frequency RESERVED 133 MHz RESERVED 166 MHz 3.7 FSB Signal Groups In order to simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous. Datasheet 25 Electrical Specifications Table 4. FSB Pin Groups Signal Group Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3 Signals REQ[4:0]#, A[16:3]# A[31:17]# Synchronous to Assoc. Strobe Associated Strobe ADSTB[0]# ADSTB[1]# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# AGTL+ Common Clock Input AGTL+ Common Clock I/O AGTL+ Source Synchronous I/O D[15:0]#, DINV0# D[31:16]#, DINV1# D[47:32]#, DINV2# D[63:48]#, DINV3# AGTL+ Strobes CMOS Input Open Drain Output Open Drain I/O CMOS Output CMOS Input Open Drain Output FSB Clock Power/Other Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK Clock ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, IERR#, THERMTRIP# PROCHOT#4 PSI#, VID[6:0], BSEL[2:0] TCK, TDI, TMS, TRST# TDO BCLK[1:0] COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, VCC, VCCA, VCCP, VCCSENSE, VSS, VSSSENSE NOTES: 1. Refer to Table 17 for signal descriptions and termination requirements. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. BPM[2:1]# and PRDY# are AGTL+ output only signals. 4. PROCHOT# signal type is open drain output and CMOS input. 26 Datasheet Electrical Specifications 3.8 CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups. 3.9 Maximum Ratings Table 5 specifies absolute maximum and minimum ratings. Only within specified operation limits, can functionality and long-term reliability be expected. At condition outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from electro static discharge, precautions should always be taken to avoid high static voltages or electric fields. Table 5. Symbol TSTORAGE VCC VinAGTL+ VinAsynch_CMOS Processor DC Absolute Maximum Ratings Parameter Processor Storage Temperature Any Processor Supply Voltage with Respect to VSS AGTL+ Buffer DC Input Voltage with Respect to VSS CMOS Buffer DC iNput Voltage with Respect to VSS Min -40 -0.3 -0.3 -0.3 Max 85 1.6 1.6 1.6 Unit °C V V V Notes 2 1 1, 2 1, 2 NOTES: 1. This rating applies to any processor pin. 2. Contact Intel for storage requirements in excess of one year. Datasheet 27 Electrical Specifications 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 12. DC specifications for the CMOS group are listed in Table 13. Table 6 through Table 14 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on the processor. Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the processor are at Tjunction = 100°C. Care should be taken to read all notes associated with each parameter. Table 6. Symbol VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for Intel Core Duo Processor SV (Standard Voltage) (Sheet 1 of 2) Parameter VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep Voltage VCC at Intel Enhanced Deeper Sleep Voltage ICC for Intel® Core™ Duo Processor SV Recommended Design Target ICC for Intel Core Duo Processor SV Processor Number T2700 T2600 T2500 T2400 T2300 T2300E N/A Core Frequency/Voltage 2.33 GHz and HFM VCC 2.16 GHz and HFM VCC 2.00 GHz and HFM VCC 1.83 GHz and HFM VCC 1.66 GHz and HFM VCC 1.66 GHz and HFM VCC 1 GHz and LFM VCC 34 34 34 34 34 34 15.5 12.5 23.3 12.4 23.2 A 3,4 A 3,4 A 3,12,13 0.997 1.425 0.55 0.50 Min 1.1625 0.7625 1.20 1.05 1.5 1.102 1.575 0.85 0.80 36 Typ Max 1.3 1.0 Unit V V V V V V V A 1, 2, 12 1, 2 5 Notes 1, 2 1, 2 2, 8 2 ICC IAH, ISGNT ICC Auto-Halt & Stop-Grant LFM HFM ICC Sleep LFM HFM ISLP 28 Datasheet Electrical Specifications Table 6. Symbol Voltage and Current Specifications for Intel Core Duo Processor SV (Standard Voltage) (Sheet 2 of 2) Parameter ICC Deep Sleep LFM HFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable Min Typ Max 11.8 20.9 7.6 6.7 600 120 6.0 2.5 A A A/µs mA A A 10 9 3, 4 4 6, 7 Unit A Notes 3, 4 IDSLP IDPRSLP IDC4 dICC/DT ICCA ICCP NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or C1E). 2. The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the VID voltage. 5. The ICCDES(max) specification of 36 A comprehends only Intel Core Duo processor SV HFM frequencies. Platforms should be designed to 44 A to be compatible with next generation processor. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Measured at the bulk capacitors on the motherboard. 8. VCC, boot tolerance is shown in Figure 3. 9. This is a steady-state ICCP current specification, which is applicable when both VCCP and VCC core are high. 10. This is a power-up peak current specification, which is applicable when VCCP is high and VCC core is low. 11. Specified at the nominal VCC. 12. If a given Operating Systems C-State model is not based on the use of MWAIT or I/O Redirection, the processor Deeper Sleep VID will be same as LFM VID. 13. T2300E does not support Intel Virtualization Technology. Datasheet 29 Electrical Specifications Table 7. Symbol VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for Intel Core Solo Processor SV (Standard Voltage) Parameter VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep Voltage VCC at Intel Enhanced Deeper Sleep Voltage ICC for Intel® Core™ Solo Processor SV ICC for Intel Core Solo Processor SV Processor Number T1400 T1300 N/A Core Frequency/Voltage 1.83 GHz and HFM VCC 1.66 GHz and HFM VCC 1 GHz and LFM VCC 12.5 23.3 12.4 23.2 11.8 20.9 7.6 6.7 600 120 6.0 2.5 A A A/µs mA A A 10 9 3,4 4 6, 7 A 3,4 A 3,4 A 3,4 34 15.5 A 3,11 0.997 1.425 0.55 0.50 Min 1.1625 0.7625 1.20 1.05 1.5 1.102 1.575 0.85 0.80 36 Typ Max 1.3 1.0 Unit V V V V V V V A 1, 2, 12 1, 2 5 Notes 1, 2 1, 2 2, 8 2 ICC IAH, ISGNT ICC Auto-Halt & Stop-Grant LFM HFM ICC Sleep LFM HFM ICC Deep Sleep ISLP IDSLP IDPRSLP IDC4 dICC/DT ICCA ICCP LFM HFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before Vcc Stable ICC for VCCP Supply after Vcc Stable NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or C1E). 2. The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the VID voltage. 5. The ICCDES(max) specification of 36 A comprehends only Intel Core Solo processor SV HFM frequencies. 30 Datasheet Electrical Specifications 6. 7. 8. 9. 10. 11. 12. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. Measured at the bulk capacitors on the motherboard. VCC, boot tolerance is shown in Figure 3. This is a steady-state Iccp current specification, which is applicable when both VCCP and Vcc core are high. This is a power-up peak current specification, which is applicable when VCCP is high and Vcc core is low. Specified at the nominal VCC. If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the processor Deeper Sleep VID will be same as LFM VID. Table 8. Symbol VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for Intel Core Duo Processor LV (Low Voltage) Parameter VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep Voltage VCC at Intel® Enhanced Deeper Sleep Voltage ICC for Intel® Core™ Duo Processor LV Icc for Intel Core Duo Processor LV Processor Number Core Frequency/Voltage 1.83 GHz and HFM VCC 1.66 GHz and HFM VCC 1.50 GHz and HFM VCC 1 GHz and LFM VCC 19 19 19 15.5 12.5 13.5 12.4 13.3 11.8 12.0 7.6 6.7 600 120 6.0 2.5 A A A/µs mA A A 10 9 3,4 4 6, 7 A 3,4 A 3,4 A 3,4 A 3,11 0.997 1.425 0.55 0.50 Min 1.0000 0.7625 1.20 1.05 1.5 1.102 1.575 0.85 0.80 19 Typ Max 1.2125 1.0000 Unit V V V V V V V A 1, 2, 12 1, 2 5 Notes 1, 2, 3 1, 2, 3 2, 8 2 ICC L2500 L2400 L2300 N/A IAH, ISGNT ICC Auto-Halt & Stop-Grant LFM HFM ICC Sleep LFM HFM ICC Deep Sleep ISLP IDSLP IDPRSLP IDC4 dICC/DT ICCA ICCP LFM HFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable Datasheet 31 Electrical Specifications NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or C1E). 2. The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the VID voltage. 5. The ICCDES(max) specification of 19 A comprehends only Intel Core Duo processor LV HFM frequencies. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Measured at the bulk capacitors on the motherboard. 8. VCC, boot tolerance is shown in Figure 3. 9. This is a steady-state Iccp current specification, which is applicable when both VCCP and VCC core are high. 10. This is a power-up peak current specification, which is applicable when VCCP is high and VCC core is low. 11. Specified at the nominal VCC. 12. If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the processor Deeper Sleep VID will be same as LFM VID. Table 9. Symbol VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage (ULV) (Sheet 1 of 2) Parameter VCC at Highest Frequency Mode (HFM) VCCat Lowest Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep voltage VCC at Intel® Enhanced Deeper Sleep Voltage ICC for Intel® Core™ Duo Processor ULV Icc for Intel Core Duo Processor ULV Processor Number U2500 U2400 N/A Core Frequency/Voltage 1.20 GHz and HFM VCC 1.06 GHz and HFM VCC 800 MHz and LFM VCC 13.9 13.9 10.5 5.4 6.4 5.3 6.3 4.8 5.4 3.6 A 4 A 3,4 A 3,4 A 3,4 A 3, 12 0.997 1.425 0.55 0.5 Min 0.85 0.8 1.20 1.05 1.5 1.102 1.575 0.85 0.8 14 Typ Max 1.1 1.0 Unit V V V V V V V A 5 1, 2, 13 Notes 1, 2 1, 2 2, 7, 9 2 ICC IAH, ISGNT ICC Auto-Halt & Stop-Grant LFM HFM ICC Sleep LFM HFM ICC Deep Sleep ISLP IDSLP IDPRSLP LFM HFM ICC Deeper Sleep 32 Datasheet Electrical Specifications Table 9. Symbol IDC4 dICC/DT ICCA ICCP Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage (ULV) (Sheet 2 of 2) Parameter ICCC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP supply after VCC Stable Min Typ Max 3.3 600 120 6.0 2.5 Unit A A/µs mA A A 11 10 Notes 4 6, 8 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or C1E). 2. The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the VID voltage. 5. The ICCDES(max) specification of 14A comprehends Intel Core Duo processor ultra low voltage HFM frequencies. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Reserved. 8. Measured at the bulk capacitors on the motherboard. 9. VCC, boot tolerance is shown in Figure 3. 10. This is a steady-state Iccp current specification, which is applicable when both VCCP and VCC_CORE are high. 11. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 12. Specified at the nominal VCC. 13. If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the processor Deeper Sleep VID will be same as LFM VID. Table 10. Symbol VCCHFM VCCLFM VCC,BOOT VCCP VCCA VCCDPRSLP VCCDC4 ICCDES Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra Low Voltage) (Sheet 1 of 2) Parameter VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) Default VCC Voltage for Initial Power Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep Voltage VCC at Intel Enhanced Deeper Sleep Voltage ICC for Intel® Core™ Solo Processor ULV 0.997 1.425 0.55 0.50 Min 0.85 0.8 1.20 1.05 1.5 1.102 1.575 0.85 0.80 8 Typ Max 1.1 1.0 Unit V V V V V V V A 1, 2, 12 1, 2 5 Notes 1, 2 1, 2 2, 8 2 Datasheet 33 Electrical Specifications Table 10. Symbol Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra Low Voltage) (Sheet 2 of 2) Parameter ICC for Intel Core Solo Processor ULV Processor Number Core Frequency/Voltage 1.33 GHz and HFM VCC 1.20 GHz and HFM VCC 1.06 GHz and HFM VCC 800 MHz and LFM VCC 8 8 8 6.4 3.9 4.6 3.8 4.5 3.3 3.6 2.4 2.3 600 120 6.0 2.5 A A A/µs mA A A 10 9 3,4 4 6, 7 A 3,4 A 3,4 A 3,4 A 3,11 Min Typ Max Unit Notes ICC U1500 U1400 U1300 N/A IAH, ISGNT ICC Auto-Halt & Stop-Grant LFM HFM ICC Sleep LFM HFM ICC Deep Sleep ISLP IDSLP IDPRSLP IDC4 dICC/DT ICCA ICCP LFM HFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep VCC Power Supply Current Slew Rate at CPU Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or C1E). 2. The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100°C Tj. 4. Specified at the VID voltage. 5. This specification comprehends Intel Core Duo processor ULV processor HFM frequencies. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 7. Measured at the bulk capacitors on the motherboard. 8. Vcc, boot tolerance is shown in Figure 5. 9. This is a steady-state ICCP current specification, which is applicable when both VCCP and VCC_CORE are high. 10. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 11. Specified at the nominal VCC. 12. If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the processor Deeper Sleep VID will be same as LFM VID. 34 Datasheet Electrical Specifications Figure 3. Active VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and Intel Core Solo Processor SV VCC [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC max {HFM|LFM} VCC, DC max {HFM|LFM} VCC nom {HFM|LFM} 10mV= RIPPLE VCC, DC min {HFM|LFM} VCC min {HFM|LFM} +/-VCC nom * 1.5% = VR St. Pt. Error 1/ 0 Note 1/ VCC Set Point Error Tolerance is per below: Tolerance --------------+/-1.5% +/-11.5mV ICC [A] ICC max {HFM|LFM} VCC A ctive Mode VID Code Range -------------------------------------------------------VCC > 0 .7500V (VID 0111100). VCC < 0.7500V (VID 0111100) Datasheet 35 Electrical Specifications Figure 4. Deeper Sleep VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and Intel Core Solo Processor SV VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {Deeper Sleep} VCC-CORE, DC max {Deeper Sleep} VCC-CORE nom {Deeper Sleep} 13mV= RIPPLE for PSI# Asserted VCC-CORE, DC min {Deeper Sleep} VCC-CORE min {Deeper Sleep} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ ICC-CORE [A] ICC-CORE max {Deeper Sleep} 0 Tolerance - PSI# Ripple -----------------------------+/-[(VID*1.5%) - 3 mV] +/-(11.5 mV - 3 mV) +/- (25 mV - 3 mV) Note 1/ Deeper Sleep V CC-CORE Set Point Error Tolerance is per below : VCC-CORE VID Voltage Range -------------------------------------------------------VCC-CORE > 0.7500V 0.7500V < VCC-CORE < 0.5000 V 0.5000V < VCC-CORE < 0.4125 V NOTE: For low voltage, if PSI# is not asserted, then the 13-mV ripple allowance becomes 10 mV. 36 Datasheet Electrical Specifications Figure 5. Active VCC and ICC Loadline for Intel Core Solo Processor ULV VCC-CORE [V] Slope = -5.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ 0 Note 1/ VCC-CORE Set Point Error Tolerance is per below: ICC-CORE max {HFM|LFM} Tolerance VCC-CORE VID Voltage Range --------------- -------------------------------------------------------+/-1.5% VCC-CORE > 0.7500V +/-11.5mV 0.75000V < VCC-CORE < 0.5000V Datasheet 37 Electrical Specifications Figure 6. Deeper Sleep VCC and ICC Loadline for Intel Core Solo Processor ULV VCC-CORE[V] Slope = -5.1 m at package V/A VccSense, VssSense pins. Differential Rem Sense required. ote VCC-CORE m {Deeper Sleep} ax ax VCC-CORE, DC m {Deeper Sleep} VCC-CORE nom {Deeper Sleep} 10 m RIPPLE V= in VCC-CORE, DC m {Deeper Sleep} VCC-CORE m {Deeper Sleep} in +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ 0 Tolerance -----------------------------+/- (VID*1.5%) +/- 11.5 mV +/- 25 mV ICC-CORE m ax {Deeper Sleep} ICC-CORE [A] Note 1/ Deeper Sleep VCC-CORE Set Point Error Tolerance is per below: VCC-CORE VID Voltage Range -------------------------------------------------------VCC-CORE > 0.7500V 0.7500V < VCC-CORE < 0.5000V 0.5000V < VCC-CORE < 0.4125V 38 Datasheet Electrical Specifications Table 11. Symbol VIL VIH VCROSS ΔVCROSS VTH ILI Cpad FSB Differential BCLK Specifications Parameter Input Low Voltage Input High Voltage Crossing Voltage Range of Crossing Points Threshold Region Input Leakage Current Pad Capacitance 0.95 1.2 VCROSS -0.100 0.660 0.25 Min Typ 0 0.710 0.35 0.85 0.55 0.14 VCROSS+0.100 ± 100 1.45 Max Unit V V V V V µA pF 2 6 3 4 5 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis. 4. For Vin between 0 V and VIH. 5. Cpad includes die capacitance only. No package parasitics are included. 6. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2. Table 12. Symbol VCCP GTLREF VIH VIL VOH RTT RON ILI Cpad AGTL+ Signal Group DC Specifications Parameter I/O Voltage Reference Voltage Input High Voltage Input Low Voltage Output High Voltage Termination Resistance Buffer on Resistance Input Leakage Current Pad Capacitance 1.8 2.3 50 22.3 GTLREF+0.1 -0.1 0 VCCP 55 25.5 61 28.7 ± 100 2.75 Min 0.997 Typ 1.05 2/3 VCCP VCCP+0.1 GTLREF-0.1 Max 1.102 Unit V V V V 6 3,6 2,4 6 Notes1 Ω Ω µA pF 7,10 5 8 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull-down driver resistance. 6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. Tolerance of resistor divider decides the tolerance of GTLREF. The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. 8. Specified with on die RTT and RON are turned off. 9. Cpad includes die capacitance only. No package parasitics are included. 10. This spec applies to all AGTL+ signals except for PREQ#. RTT for PREQ# is between 1.5 kΩ to 6.0 kΩ. Datasheet 39 Electrical Specifications . Table 13. Symbol VCCP VIL VIH VOL VOH IOL IOH ILI Cpad1 Cpad2 CMOS Signal Group DC Specifications Parameter I/O Voltage Input Low Voltage CMOS Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Input Leakage Current Pad Capacitance Pad Capacitance for CMOS Input 1.8 0.95 2.3 1.2 Min 1.0 -0.1 0.7 -0.1 0.9 1.3 1.3 Typ 1.05 0.0 1.05 0 VCCP Max 1.10 0.33 1.20 0.11 1.20 4.1 4.1 ±100 2.75 1.45 Unit V V V V V mA mA µA pF pF 2, 3 2 2 2 4 5 6 7 8 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VCCP referred to in these specifications refers to instantaneous VCCP. 3. Reserved. 4. Measured at 0.1*VCCP. 5. Measured at 0.9*VCCP. 6. For Vin between 0 V and VCCP. Measured when the driver is tristated. 7. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#,PWRGOOD. No package parasitics are included. 8. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included. Table 14. Symbol VOH VOL IOL ILeak Cpad Open Drain Signal Group DC Specifications Parameter Output High Voltage Output Low Voltage Output Low Current Output Leakage Current Pad Capacitance 1.8 2.3 Min 1.0 0 11.40 Typ 1.05 Max 1.10 0.20 50 ±200 2.75 Unit V V mA µA pF 2 4 5 Notes1 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2*VCCP. 3. VOH is determined by value of the external pullup resistor to VCCP. Please contact your Intel representative for details. 4. For Vin between 0 V and VOH. 5. Cpad includes die capacitance only. No package parasitics are included. § 40 Datasheet Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information Package Mechanical Specifications The Intel Core Duo processor and Intel Core Solo processor are available in 478-pin Micro-FCPGA and 479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 7 through Figure 10. Table 15 (two sheets) shows a top-view of package pin-out with their functionalities. 4.1 Warning: The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors are electrically conductive, care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors, and possibly damage the device or render it inactive. 4.1.1 Package Mechanical Drawings Different views showing all pertinent dimensions of the Micro-FCPGA package are shown in Figure 7 and continued in Figure 8. Views and pertinent dimensions for MicroFCBGA package are shown in Figure 9 and continued in Figure 10. Datasheet 41 Package Mechanical Specifications and Pin Information Figure 7. Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) 42 Datasheet Package Mechanical Specifications and Pin Information Figure 8. Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) Datasheet 43 Package Mechanical Specifications and Pin Information Figure 9. Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) 44 Datasheet Package Mechanical Specifications and Pin Information Figure 10. Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) Datasheet 45 Package Mechanical Specifications and Pin Information 4.1.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted in the keepout areas. The location and quantity of the capacitors may change, but will remain within the component keep-in. See Figure 7 and Figure 9 for keep-out zones. 4.1.3 Package Loading Specifications Maximum mechanical package loading specifications are given in Figure 7 and Figure 9. These specifications are static compressive loading in the direction normal to the processor. This maximum load limit should not be exceeded during shipping conditions, standard use condition, or by thermal solution. In addition, there are additional load limitations against transient bend, shock, and tensile loading. These limitations are more platform specific, and should be obtained by contacting your field support. Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. 4.1.4 Processor Mass Specifications The typical mass of the processor is given in Figure 7 and Figure 9. This mass includes all the components that are included in the package. 46 Datasheet Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Table 15 shows the top view pinout of the processor. The pin list arranged in two different formats is shown in the following pages. Table 15. 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF RESET# RSVD VSS DBSY# BR0# VSS ADS# A[9]# VSS A[13]# A[7]# VSS A[15]# A[16]# VSS COMP[2] COMP[3] VSS A[31]# RSVD VSS PREQ# BPM[2]# VSS RSVD 1 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 1 of 2) 2 3 SMI# RSVD VSS RSVD BNR# VSS TRDY# REQ[1] # VSS REQ[2] # ADSTB[ 0]# VSS A[8]# A[12]# VSS RSVD A[23]# VSS A[30]# A[17]# VSS RSVD PRDY# VSS VID[6] VID[5] 2 INIT# RSVD RSVD VSS RS[0]# RS[2]# VSS REQ[3] # REQ[0] # VSS A[5]# A[10]# VSS A[19]# A[26]# VSS RSVD A[27]# VSS RSVD TDO VSS BPM[1] # VID[4] VSS 3 4 VSS LINT1 IGNNE # VSS HITM# RS[1]# VSS LOCK# A[3]# VSS A[4]# RSVD VSS A[14]# A[24]# VSS A[21]# ADSTB [1]# VSS A[29]# RSVD VSS BPM[3] # BPM[0] # VSS VID[3] 4 5 FERR# DPSLP# VSS STPCLK # DPRSTP # VSS BPRI# DEFER# VSS A[6]# REQ[4] # VSS RSVD A[11]# VSS A[25]# A[18]# VSS A[28]# A[22]# VSS TMS TCK VSS VID[2] VID[1] 5 6 A20M# VSS LINT0 PWRGO OD VSS RSVD HIT# VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP A[20]# VSS TDI TRST# VSS VID[0] PSI# VSS 6 VCC VCC VCC VCC VSS SENSE VCC SENSE 7 VSS VSS VSS VSS VSS VSS 8 VCC VCC VCC VCC VCC VCC 9 VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS 11 VCC VCC VCC VCC VCC VCC 12 VCC VSS VCC VSS VCC VSS 13 7 VCC VCC THERM TRIP# SLP# VCC VCC 8 VSS VSS VSS VSS VSS VSS 9 VCC VCC VCC VCC VCC VCC 10 VCC VCC VCC VCC VCC VCC 11 VSS VSS VSS VSS VSS VSS 12 VCC VCC VCC VCC VCC VCC 13 VCC VSS VCC VSS VCC VSS A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Datasheet 47 Package Mechanical Specifications and Pin Information Table 16. 14 A B C D E F G H J K L M N P R T U V W Y AA AB AC A D AE AF VSS VCC VSS VCC VSS VCC 14 VCC VCC VCC VCC VCC VCC 15 VSS VCC VSS VCC VSS VCC 15 VCC VCC VCC VCC VCC VCC The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of 2) 16 VSS VSS VSS VSS VSS VSS 17 VCC VCC VCC VCC VCC VCC 18 VCC VCC VCC VCC VCC VCC 19 VSS VSS VSS VSS VSS VSS 20 VCC VCC DBR# IERR# VCC VCC 21 BCLK[1] VSS BSEL[2] PROC HOT# VSS DRDY# VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VSS VSS VSS VSS VSS VSS 16 VCC VCC VCC VCC VCC VCC 17 VCC VCC VCC VCC VCC VCC 18 VSS VSS VSS VSS VSS VSS 19 VCC VCC DINV[3 ]# D[54]# VCC VCC 20 D[51]# D[52]# VSS D[59]# D[58]# VSS 21 22 BCLK[0] BSEL[0] VSS RSVD D[0]# VSS DSTBP[0]# D[3]# VSS D[14]# D[21]# VSS D[16]# D[25]# VSS RSVD D[39]# VSS D[41]# D[45]# VSS D[50]# D[48]# VSS D[55]# D[62]# 22 23 VSS BSEL[1] RSVD VSS D[7]# D[4]# VSS DSTBN[0]# D[11]# VSS D[22]# D[23]# VSS D[26]# D[19]# VSS D[37]# DINV[2]# VSS D[42]# D[32]# VSS D[49]# DSTBN[3]# VSS D[56]# 23 24 THRMDA VSS RSVD DPWR# VSS D[1]# D[9]# VSS D[10]# D[8]# VSS DSTBN[1]# D[31]# VSS D[28]# D[27]# VSS D[34]# DSTBN[2]# VSS D[47]# D[33]# VSS D[57]# DSTBP[3]# VSS 24 25 THRMDC RSVD VSS TEST2 D[6]# VSS D[5]# D[15]# VSS D[17]# D[20]# VSS DSTBP[1]# D[24]# VSS D[30]# D[38]# VSS D[36]# DSTBP[2]# VSS D[40]# D[53]# VSS D[60]# D[61]# 25 26 VSS VCCA TEST1 VSS D[2]# D[13]# VSS D[12]# DINV[0 ]# VSS D[29]# DINV[1 ]# VSS D[18]# COMP [0] VSS COMP [1] D[35]# VSS D[44]# D[43]# VSS D[46]# GTLREF VSS D[63]# 26 A B C D E F G H J K L M N P R T U V W Y A A A B AC A D AE AF 48 Datasheet Package Mechanical Specifications and Pin Information 4.3 Table 17. Alphabetical Signals Reference Signal Description (Sheet 1 of 9) Name Type Description A[31:3]# (Address) define a 232-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel® Core™ Duo processor and the Intel® Core™ Solo processor FSB. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[31:17]# Associated Strobe ADSTB[0]# ADSTB[1]# A[31:3]# Input/ Output A20M# Input ADS# Input/ Output BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BNR# Input/ Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. Datasheet 49 Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 2 of 9) Name Type Description BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all processor FSB agents.This includes debug or performance monitoring tools. Please contact your Intel representative for more detailed information. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. The arbitration is done between the processor (Symmetric Agent) and the Mobile Intel® 945 Express Chipset family (High Priority Agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The processor operates at 667-MHz or 533-MHz system bus frequency (166-MHz or 133-MHz BCLK[1:0] frequency, respectively). COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Please contact your Intel representative for more implementation details. BPM[2:1]# BPM[3,0]# Output Input/ Output BPRI# Input BR0# Input/ Output BSEL[2:0] Output COMP[3:0] Analog 50 Datasheet Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DINV# 0 1 2 3 Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/ Output agent. This signal must connect the appropriate pins of both FSB agents. DBR# Output DBSY# Input/ Output DEFER# Input Datasheet 51 Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 4 of 9) Name Type Description DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment to Data Bus DINV[3:0]# Input/ Output Bus Signal DINV[3]# DINV[2]# DINV[1]# DINV[0]# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]# DPRSTP# Input DPRSTP# when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state. In order to return to the Deep Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the Intel® ICH7M chipset. DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the ICH7M chipset. DPWR# is a control signal from the Mobile Intel 945 Express Chipset family used to reduce power on the processor data bus input buffers. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DPSLP# Input DPWR# Input DRDY# Input/ Output DSTBN[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# 52 Datasheet Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 5 of 9) Name Type Description FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volume 3 of the Intel ® Architecture Software Developer’s Manual and AP-485, Intel ® Processor Identification and CPUID Instruction Application Note. For termination requirements please contact your Intel representative. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. Please contact your Intel representative for more information regarding GTLREF implementation. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. For termination requirements please contact your Intel representative. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. FERR#/PBE# Output GTLREF Input HIT# HITM# Input/ Output Input/ Output IERR# Output IGNNE# Input Datasheet 53 Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 6 of 9) Name Type Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). For termination requirements please contact your Intel representative. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. Please contact your Intel representative for more implementation details. Probe Request signal used by debug tools to request debug operation of the processor. Please contact your Intel representative for more implementation details. INIT# Input LINT[1:0] Input LOCK# Input/ Output PRDY# Output PREQ# Input 54 Datasheet Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 7 of 9) Name Type Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system deasserts PROCHOT#. By default PROCHOT# is configured as an output only. Bidirectional PROCHOT# must be enabled via the BIOS. For termination requirements please contact your Intel representative. This signal may require voltage translation on the motherboard. Please contact your Intel representative for more details. Processor Power Status Indicator signal. This signal is asserted when the processor is in a normal state (HFM and LFM) and lower state (Deep Sleep and Deeper Sleep). Please contact your Intel representative for more details on the PSI# signal. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. For termination requirements please contact your Intel representative. Input/ Output REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. For termination requirements please contact your Intel representative and implementation details. There is a 55 Ω (nominal) on die pull-up resistor on this signal. RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please contact your Intel representative for more details. PROCHOT# Input/ Output PSI# Output PWRGOOD Input REQ[4:0]# RESET# Input RSVD Reserved /No Connect Datasheet 55 Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 8 of 9) Name Type Description SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to StopGrant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). Please contact your Intel representative for termination requirements and implementation details. TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. Please contact your Intel representative for termination requirements and implementation details. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Please contact your Intel representative for termination requirements and implementation details. TEST1 must have a stuffing option of separate pull-down resistor to VSS. Please contact your Intel representative for more detailed information. TEST2 must have a 51 Ω ±5% pull-down resistor to VSS. Please contact your Intel representative for more details. Thermal Diode Anode. Thermal Diode Cathode. SLP# Input SMI# Input STPCLK# Input TCK Input TDI Input TDO Output TEST1 Input TEST2 THERMDA THERMDC Input Other Other 56 Datasheet Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 9 of 9) Name Type Description The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. For termination requirements please contact your Intel representative. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Please contact your Intel representative for termination requirements and implementation details. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. Please contact your Intel representative for termination requirements and implementation details. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Please contact your Intel representative for termination requirements and implementation details. Processor core power supply. VCCA provides isolated power for the internal processor core PLL’s. Please contact your Intel representative for complete implementation details. Processor I/O Power Supply. VCCSENSE together with VSSSENSE are voltage feedback signals to IMVP6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense voltage near the silicon with little noise. Please contact your Intel Representative for more information regarding termination and routing recommendations. VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike some previous generations of processors, these are CMOS signals that are driven by the Intel Core Duo processor and Intel Core Solo processor. The voltage supply for these pins must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSSSENSE together with VCCSENSE are voltage feedback signals to Intel® MVP6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense ground near the silicon with little noise. Please contact your Intel Representative for more information regarding termination and routing recommendations. THERMTRIP# Output TMS Input TRDY# Input TRST# Input VCC VCCA VCCP Input Input Input VCCSENSE Output VID[6:0] Output VSSSENSE Output § Datasheet 57 Package Mechanical Specifications and Pin Information 58 Datasheet Package Mechanical Specifications and Pin Information Table 18. Table 18. Pin Name Pin Listing by Pin Name Pin Number Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 A6 H1 L2 V4 A22 A21 E2 AD4 AD3 AD1 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Source Synch Source Synch Bus Clock Bus Clock Common Clock Common Clock Common Clock Common Clock Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input Input Input/ Output Input/ Output Output Output Pin Listing by Pin Name Pin Number J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Pin Name A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A20M# ADS# ADSTB[0] # ADSTB[1] # BCLK[0] BCLK[1] BNR# BPM[0]# BPM[1]# BPM[2]# A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# Datasheet 59 Package Mechanical Specifications and Pin Information Table 18. Pin Name Pin Listing by Pin Name Pin Number AC4 G5 F1 B22 B23 C21 R26 U26 U1 V1 E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 Signal Buffer Type Common Clock Common Clock Common Clock CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input Input/ Output Output Output Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 18. Pin Name Pin Listing by Pin Name Pin Number J24 J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output BPM[3]# BPRI# BR0# BSEL[0] BSEL[1] BSEL[2] COMP[0] COMP[1] COMP[2] COMP[3] D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# 60 Datasheet Package Mechanical Specifications and Pin Information Table 18. Pin Name Pin Listing by Pin Name Pin Number L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Table 18. Pin Name Pin Listing by Pin Name Pin Number AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 C20 E1 H5 J26 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Common Clock Source Synch Direction Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Output Input/ Output Input Input/ Output D[29]# D[30]# D[31]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DBR# DBSY# DEFER# DINV[0]# Datasheet 61 Package Mechanical Specifications and Pin Information Table 18. Pin Name Pin Listing by Pin Name Pin Number M26 V23 AC20 E5 B5 D24 F21 H23 M24 W24 AD23 G22 N25 Y25 AE24 A5 AD26 G6 E4 D20 C4 B3 Signal Buffer Type Source Synch Source Synch Source Synch CMOS CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Open Drain Power/Other Common Clock Common Clock Open Drain CMOS CMOS Direction Input/ Output Input/ Output Input/ Output Input Input Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Output Input Input/ Output Input/ Output Output Input Input Table 18. Pin Name LINT0 LINT1 LOCK# PRDY# PREQ# PROCHOT # PSI# PWRGOOD REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# RESET# RS[0]# RS[1]# RS[2]# RSVD RSVD RSVD RSVD RSVD RSVD Pin Listing by Pin Name Pin Number C6 B4 H4 AC2 AC1 D21 AE6 D6 K3 H2 K2 J3 L5 B1 F3 F4 G3 D2 F6 D3 C1 AF1 D22 Signal Buffer Type CMOS CMOS Common Clock Common Clock Common Clock Open Drain CMOS CMOS Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Common Clock Common Clock Common Clock Reserved Reserved Reserved Reserved Reserved Reserved Direction Input Input Input/ Output Output Input Input/ Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input Input DINV[1]# DINV[2]# DINV[3]# DPRSTP# DPSLP# DPWR# DRDY# DSTBN[0] # DSTBN[1] # DSTBN[2] # DSTBN[3] # DSTBP[0] # DSTBP[1] # DSTBP[2] # DSTBP[3] # FERR# GTLREF HIT# HITM# IERR# IGNNE# INIT# 62 Datasheet Package Mechanical Specifications and Pin Information Table 18. Pin Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SLP# SMI# STPCLK# TCK TDI TDO TEST1 TEST2 THERMDA THERMDC THERMTRI P# TMS TRDY# TRST# VCC Pin Listing by Pin Name Pin Number C23 C24 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25 D7 A3 D5 AC5 AA6 AB3 C26 D25 A24 A25 C7 AB5 G2 AB6 AB20 Signal Buffer Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CMOS CMOS CMOS CMOS CMOS Open Drain Test Test Power/Other Power/Other Open Drain CMOS Common Clock CMOS Power/Other Output Input Input Input Input Input Input Input Input Output Direction Table 18. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Listing by Pin Name Pin Number AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17 AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 63 Package Mechanical Specifications and Pin Information Table 18. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Listing by Pin Name Pin Number AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 18. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Listing by Pin Name Pin Number C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 64 Datasheet Package Mechanical Specifications and Pin Information Table 18. Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCSENSE VID[0] VID[1] VID[2] Pin Listing by Pin Name Pin Number C9 F10 F9 E10 E9 B7 A7 F7 E7 B26 K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21 AF7 AD6 AF5 AE5 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS CMOS Output Output Output Direction Table 18. Pin Name VID[3] VID[4] VID[5] VID[6] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number AF4 AE3 AF2 AE2 AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 Signal Buffer Type CMOS CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output Output Output Datasheet 65 Package Mechanical Specifications and Pin Information Table 18. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 18. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1 K1 J2 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 66 Datasheet Package Mechanical Specifications and Pin Information Table 18. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 18. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing by Pin Name Pin Number B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 67 Package Mechanical Specifications and Pin Information Table 18. Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE Pin Listing by Pin Name Pin Number L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21 AE7 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Direction 68 Datasheet Package Mechanical Specifications and Pin Information Table 19. Table 19. Pin Number A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 Pin Listing by Pin Number Pin Name VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC D[51]# VSS D[32]# D[47]# VSS D[43]# VSS RSVD TDO VSS TMS TRST# VCC VSS Signal Buffer Type Power/Other Power/other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Reserved Open Drain Power/Other CMOS CMOS Power/Other Power/Other Input Input Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Pin Listing by Pin Number Pin Name SMI# VSS FERR# A20M# VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THERMDA THERMDC VSS RSVD VSS RSVD RSVD VSS TDI Signal Buffer Type CMOS Power/Other Open Drain CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Bus Clock Bus Clock Power/Other Power/Other Power/Other Power/Other Reserved Power/Other Reserved Reserved Power/Other CMOS Input Input Input Output Input Direction Input Pin Number AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 Datasheet 69 Package Mechanical Specifications and Pin Information Table 19. Pin Number AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 Pin Listing by Pin Number Pin Name VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC D[52]# D[50]# VSS D[33]# D[40]# VSS PREQ# PRDY# VSS BPM[3]# TCK VSS VCC VSS VCC Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Input/ Output Input Input Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 19. Pin Number AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 Pin Listing by Pin Number Pin Name VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS DINV[3]# VSS D[48]# D[49]# VSS D[53]# D[46]# BPM[2]# VSS BPM[1]# BPM[0]# VSS VID[0] VCC VSS VCC Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other CMOS Power/Other Power/Other Power/Other Output Output Input/ Output Input/ Output Input/ Output Output Input/ Output Input/ Output Input/ Output Direction 70 Datasheet Package Mechanical Specifications and Pin Information Table 19. Pin Number AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 Pin Listing by Pin Number Pin Name VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS D[54]# D[59]# VSS DSTBN[3] # D[57]# VSS GTLREF VSS VID[6] VID[4] VSS VID[2] PSI# VSSSENSE VSS VCC VCC VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other CMOS CMOS Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 19. Pin Number AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 Pin Listing by Pin Number Pin Name VCC VCC VSS VCC VSS VCC VCC VSS VCC D[58]# D[55]# VSS DSTBP[3] # D[60]# VSS RSVD VID[5] VSS VID[3] VID[1] VSS VCCSENSE VSS VCC VCC VSS VCC VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Reserved CMOS Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Datasheet 71 Package Mechanical Specifications and Pin Information Table 19. Pin Number AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 Pin Listing by Pin Number Pin Name VCC VCC VSS VCC VCC VSS VCC VSS D[62]# D[56]# VSS D[61]# D[63]# RESET# RSVD INIT# LINT1 DPSLP# VSS VCC VSS VCC VCC VSS VCC VSS VCC VCC Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Common Clock Reserved CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input/ Output Input/ Output Input Input/ Output Input/ Output Direction Table 19. Pin Number B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 Pin Listing by Pin Number Pin Name VSS VCC VCC VSS VCC VSS BSEL[0] BSEL[1] VSS RSVD VCCA RSVD VSS RSVD IGNNE# VSS LINT0 THERMTRI P# VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Power/Other Reserved Power/Other Reserved Power/Other Reserved CMOS Power/Other CMOS Open Drain Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Input Output Output Direction 72 Datasheet Package Mechanical Specifications and Pin Information Table 19. Pin Number C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 Pin Listing by Pin Number Pin Name DBR# BSEL[2] VSS RSVD RSVD VSS TEST1 VSS RSVD RSVD VSS STPCLK# PWRGOOD SLP# VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS IERR# PROCHOT # RSVD VSS Signal Buffer Type CMOS CMOS Power/Other Reserved Reserved Power/Other Test Power/Other Reserved Reserved Power/Other CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain Open Drain Reserved Power/Other Output Input/ Output Input Input Input Direction Output Output Table 19. Pin Number D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 Pin Listing by Pin Number Pin Name Signal Buffer Type Common Clock Test Power/Other Common Clock Common Clock Power/Other Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Direction DPWR# TEST2 VSS DBSY# BNR# VSS HITM# DPRSTP# VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS D[0]# D[7]# VSS Input Datasheet 73 Package Mechanical Specifications and Pin Information Table 19. Pin Number E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 Pin Listing by Pin Number Pin Name Signal Buffer Type Source Synch Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output Input/ Output Table 19. Pin Number F25 F26 G1 G2 G3 Pin Listing by Pin Number Pin Name VSS D[13]# VSS TRDY# RS[2]# VSS BPRI# HIT# VCCP DSTBP[0] # VSS D[9]# D[5]# VSS ADS# REQ[1]# VSS LOCK# DEFER# VSS VSS D[3]# DSTBN[0] # Signal Buffer Type Power/Other Source Synch Power/Other Common Clock Common Clock Power/Other Common Clock Common Clock Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Common Clock Common Clock Power/Other Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input Input Input/ Output Direction D[6]# D[2]# BR0# VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC DRDY# VSS D[4]# D[1]# Input G4 Input G5 G6 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 74 Datasheet Package Mechanical Specifications and Pin Information Table 19. Pin Number H24 H25 H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K21 K22 K23 Pin Listing by Pin Number Pin Name VSS D[15]# D[12]# A[9]# VSS REQ[3]# A[3]# VSS VCCP VCCP VSS D[11]# D[10]# VSS DINV[0]# VSS REQ[2]# REQ[0]# VSS A[6]# VCCP VCCP D[14]# VSS Signal Buffer Type Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 19. Pin Number K24 K25 K26 L1 L2 L3 L4 L5 L6 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M21 M22 Pin Listing by Pin Number Pin Name Signal Buffer Type Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Reserved Power/Other Power/Other Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output D[8]# D[17]# VSS A[13]# ADSTB[0] # VSS A[4]# REQ[4]# VSS VSS D[21]# D[22]# VSS D[20]# D[29]# A[7]# VSS A[5]# RSVD VSS VCCP VCCP VSS Datasheet 75 Package Mechanical Specifications and Pin Information Table 19. Pin Number M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P21 Pin Listing by Pin Number Pin Name Signal Buffer Type Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Reserved Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output Table 19. Pin Number P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T21 Pin Listing by Pin Number Pin Name Signal Buffer Type Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Reserved Source Synch Power/Other Source Synch Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output D[23]# DSTBN[1] # VSS DINV[1]# VSS A[8]# A[10]# VSS RSVD VCCP VCCP D[16]# VSS D[31]# DSTBP[1] # VSS A[15]# A[12]# VSS A[14]# A[11]# VSS VSS D[25]# D[26]# VSS D[24]# D[18]# A[16]# VSS A[19]# A[24]# VSS VCCP VCCP VSS D[19]# D[28]# VSS COMP[0] VSS RSVD A[26]# VSS A[25]# VCCP VCCP 76 Datasheet Package Mechanical Specifications and Pin Information Table 19. Pin Number T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V21 Pin Listing by Pin Number Pin Name RSVD VSS D[27]# D[30]# VSS COMP[2] A[23]# VSS A[21]# A[18]# VSS VSS D[39]# D[37]# VSS D[38]# COMP[1] COMP[3] VSS RSVD ADSTB[1] # VSS VCCP VCCP Signal Buffer Type Reserved Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Reserved Source Synch Power/Other Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Table 19. Pin Number V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Pin Listing by Pin Number Pin Name VSS DINV[2]# D[34]# VSS D[35]# VSS A[30]# A[27]# VSS A[28]# A[20]# VCCP D[41]# VSS DSTBN[2] # D[36]# VSS A[31]# A[17]# VSS A[29]# A[22]# VSS Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Datasheet 77 Package Mechanical Specifications and Pin Information Table 19. Pin Number Y21 Y22 Y23 Y24 Y25 Y26 Pin Listing by Pin Number Pin Name VSS D[45]# D[42]# VSS DSTBP[2] # D[44]# Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Direction 78 Datasheet Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor via a heat pipe or direct die attachment. A secondary fan or air from the processor fan may also be used to cool other platform components or to lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 20 to Table 22. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. The maximum junction temperature is defined by an activation of the processor Intel Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 20 to Table 22. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification. Datasheet 79 Thermal Specifications and Design Considerations Table 20. Power Specifications for the Intel Core Duo Processor SV (Standard Voltage) Symbol Processor Number T2700 T2600 T2500 TDP T2400 T2300 T2300E N/A Symbol PAH, PSGNT at HFM VCC at LFM VCC Sleep Power PSLP at HFM VCC at LFM VCC Deep Sleep Power PDSLP at HFM VCC at LFM VCC PDPRSLP PDC4 TJ Deeper Sleep Power Intel® Enhanced Deeper Sleep Power Junction Temperature 0 10.5 3.4 2.2 1.8 100 W W °C W 15.5 4.7 W Core Frequency & Voltage 2.33 GHz & HFM VCC 2.16 GHz & HFM VCC 2.00 GHz & HFM VCC 1.83 GHz & HFM VCC 1.66 GHz & HFM VCC 1.66 GHz & HFM VCC 1.00 GHz & LFM VCC Parameter Auto Halt, Stop Grant Power 15.8 4.8 W Min Thermal Design Power 31 31 31 31 31 31 13.1 Typ Max Unit Notes At 50°C Note 2 At 50°C Note 2 At 35°C Note 2 At 35°C Note 2 At 35°C Note 2 Notes 3, 4 W At 100°C Notes 1, 4, 5 Unit Notes NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specification. 5. T2300E does not support Intel Virtualization Technology. 80 Datasheet Thermal Specifications and Design Considerations Table 21. Power Specifications for the Intel Core Solo Processor SV (Standard Voltage) Symbol Processor Number T1400 TDP Symbol PAH, PSGNT at HFM VCC at LFM VCC Sleep Power PSLP at HFM VCC at LFM VCC Deep Sleep Power PDSLP at HFM VCC at LFM VCC PDPRSLP PDC4 TJ Deeper Sleep Power Intel® Enhanced Deeper Sleep Power Junction Temperature 0 10.5 3.4 2.2 1.8 100 W W °C W 15.5 4.7 W T1300 N/A Core Frequency & Voltage 1.83 GHz & HFM VCC 1.66 GHz & HFM VCC 1.00 GHz & LFM VCC Parameter Auto Halt, Stop Grant Power 15.8 4.8 W Min Thermal Design Power 27 27 13.1 Typ Max Unit W Unit Notes At 100°C Notes 1, 4 Notes At 50°C Note 2 At 50°C Note 2 At 35°C Note 2 At 35°C Note 2 At 35°C Note 2 Notes 3, 4 NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specification. Datasheet 81 Thermal Specifications and Design Considerations Table 22. Power Specifications for the Intel Core Duo Processor LV (Low Voltage) Symbol Processor Number L2500 TDP L2400 L2300 N/A Symbol PAH, PSGNT at HFM VCC at LFM VCC Sleep Power PSLP at HFM VCC at LFM VCC Deep Sleep Power PDSLP at HFM VCC at LFM VCC PDPRSLP PDC4 TJ Deeper Sleep Power Intel® Enhanced Deeper Sleep Power Junction Temperature 0 5.7 3.4 2.2 1.8 100 W W °C W 5.8 4.7 W Core Frequency & Voltage 1.83 GHz & HFM VCC 1.66 GHz & HFM VCC 1.50 GHz & HFM VCC 1.00 GHz & LFM VCC Parameter Auto Halt, Stop Grant Power 6.0 4.8 W Min Thermal Design Power 15 15 15 13.1 Typ Max Unit Notes At 50°C Note 2 At 50°C Note 2 At 35°C Note 2 At 35°C Note 2 At 35°C Note 2 Notes 3, 4 W At 100°C Notes 1, 4 Unit Notes NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specification. 82 Datasheet Thermal Specifications and Design Considerations Table 23. Power Specifications for the Intel Core Duo Processor, Ultra Low Voltage (ULV) Symbol Processor Number U2500 TDP Symbol PAH, PSGNT at HFM VCC at LFM VCC Sleep Power PSLP at HFM VCC at LFM VCC Deep Sleep Power PDSLP at HFM VCC at LFM VCC PDPRSLP PDC4 TJ Deeper Sleep Power Intel® Enhanced Deeper Sleep Power Junction Temperature 0 2.2 1.8 1.3 1.1 100 W W °C W 3.6 2.5 W U2400 N/A Core Frequency & Voltage 1.20 GHz & HFM VCC 1.06 GHz & HFM VCC 800 MHz & LFM VCC Parameter Auto Halt, Stop Grant Power 3.7 2.6 W Min Thermal Design Power 9 9 7.5 Typ Max Unit W Unit Notes At 100°C Notes1, 4 Notes At 50°C Note 2 At 50°C Note 2 At 35°C Note 2 At 35°C Note 2 At 35°C Note 2 Notes 3, 4 NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specification. Datasheet 83 Thermal Specifications and Design Considerations Table 24. Power Specifications for the Intel Core Solo Processor ULV (Ultra Low Voltage) Symbol Processor Number U1500 TDP U1400 U1300 Core Frequency & Voltage 1.33 GHz and HFM VCC 1.20 GHz and HFM VCC1.06 GHz and LFM VCC 800 MHz and LFM VCC Symbol PAH, PSGNT at HFM VCC at LFM VCC Sleep Power PSLP at HFM VCC at LFM VCC Deep Sleep Power PDSLP at HFM VCC at LFM VCC PDPRSLP PDC4 TJ Deeper Sleep Power Intel® Enhanced Deeper Sleep Power Junction Temperature 0 1.5 1.2 0.7 0.6 100 W W °C W 2.9 2.1 W Parameter Auto Halt, Stop Grant Power 3.0 2.2 W Min Thermal Design Power 5.5 5.5 5.5 5 Typ Max Unit Notes At 50°C Note 2 At 50°C Note 2 At 35°C Note 2 At 35°C Note 2 At 35°C Note 2 Notes 3, 4 W At 100°C Notes 1, 4 Unit Notes NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specification. 84 Datasheet Thermal Specifications and Design Considerations 5.1 Thermal Specifications The processor incorporates three methods of monitoring die temperature, the digital thermal sensor (DTS), Intel Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1.3) must be used to determine when the maximum specified processor junction temperature has been reached. 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to Ground. The thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor Model Specific Register (MSR) and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage recommendation when the PROCHOT# signal is not asserted. Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change. Offset between the thermal diode-based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the processor Model Specific Register (MSR). Table 25, Table 26, Table 27, and Table 28 provide the diode interface and specifications. Two different sets of diode parameters are listed in Table 26 and Table 27. The Diode Model parameters (Table 26) apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature. Transistor Model parameters (Table 27) have been added to support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. Please contact your external thermal sensor supplier for their recommendation. This thermal diode is separate from the Intel Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor. Table 25. Thermal Diode Interface Signal Name THERMDA THERMDC Pin/Ball Number A24 A25 Signal Description Thermal diode anode Thermal diode cathode Datasheet 85 Thermal Specifications and Design Considerations Table 26. Thermal Diode Parameters using Diode Mode Symbol IFW n RT Parameter Forward Bias Current Diode Ideality Factor Series Resistance Min 5 1.000 2.79 Typ 1.009 4.52 Max 200 1.050 6.24 Unit µA Ω Notes 1 2, 3, 4 2, 3, 5 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. Characterized across a temperature range of 50 - 100°C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW = IS * (e qVD/nkT –1) 5. where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature. RT, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N] where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic charge. Table 27. Thermal Diode Parameters using Transistor Mode Symbol IFW IE nQ Beta RT Series Resistance Parameter Forward Bias Current Emitter Current Transistor Ideality Min 5 5 0.997 0.3 2.79 4.52 1.001 Typ Max 200 200 1.005 0.760 6.24 Ω Unit µA µA 3, 4, 5 3, 4 3, 6 Notes 1, 2 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 25. 3. Characterized across a temperature range of 50 - 100°C. 4. Not 100% tested. Specified by design characterization. 5. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current: IC = IS * (e qVBE/nQkT –1) Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin). The series resistance, RT, provided in the Diode Model Table (Table 26) can be used for more accurate readings as needed. 6. 86 Datasheet Thermal Specifications and Design Considerations When calculating a temperature based on thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although some are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 25. In most temperature sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode the ideality value (also called ntrim) will be 1.000. Given that most diodes are not perfect, the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. If the processors diode ideality deviates from that of ntrim, each calculated temperature will be offset by a fixed amount. This temperature offset can be calculated with the equation: Terror(nf) = Tmeasured X (1 - nactual/ntrim) Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing device. 5.1.2 Thermal Diode Offset In order to improve the accuracy of diode based temperature measurements, a temperature offset value (specified as Toffset) will be programmed into a processor Model Specific Register (MSR) which will contain thermal diode characterization data. During manufacturing each processors thermal diode will be evaluated for its behavior relative to a theoretical diode. Using the equation above, the temperature error created by the difference between ntrim and the actual ideality of the particular processor will be calculated. If the ntrim value used to calculate Toffset differs from the ntrim value used in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the actual ntrim as defined in the temperature sensor manufacturers' datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in the table below Table 28. Thermal Diode ntrim and Diode Correction Toffset Symbol ntrim Parameter Diode ideality used to calculate Toffset Value 1.01 5.1.3 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An underdesigned thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. Datasheet 87 Thermal Specifications and Design Considerations The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and on-demand mode. If both modes are activated, Automatic mode takes precedence. Note: The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal Monitor 2 (TM2). These modes are selected by writing values to the Model Specific Registers (MSRs) of the processor. After Automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. Likewise, when Intel Thermal Monitor 2 is enabled, and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep Technology transition to a lower operating point. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in the auto-throttle MSR, TM2 will take precedence over TM1. However, if TM2 is not sufficient to cool the processor below the maximum operating temperature then TM1 will also activate to help cool down the processor. Intel recommends Intel Thermal Monitor 1 and Intel Thermal Monitor 2 be enabled on the Intel Core Duo processor and Intel Core Solo processor. If a processor load-based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when an Intel Thermal Monitor 2 period is active, there are two possible results: 1. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is higher than the Intel Thermal Monitor 2 transition-based target frequency, the processor load-based transition will be deferred until the Intel Thermal Monitor 2 event has been completed. 2. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the Intel Thermal Monitor 2 transition-based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep Technology target frequency point. When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a noncritical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, 88 Datasheet Thermal Specifications and Design Considerations if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three model specific registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3. 5.1.4 Digital Thermal Sensor (DTS) The processor also contains an on-die DTS that can be read via a MSR (no I/O interface). In a dual core implementation of the Intel Core Duo processor, each core will have a unique DTS whose temperature is accessible via processor MSR. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor. The DTS is only valid while the processor is in the normal operating state (C0 state). Unlike traditional thermal devices, the DTS will output a temperature relative to the maximum supported operating temperature of the processor (TJ,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the digital thermal sensor MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The DTS relative temperature readout corresponds to the Intel Thermal Monitor (TM1/ TM2) trigger point. When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism will activate. The DTS and TM1/TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical Datasheet 89 Thermal Specifications and Design Considerations and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. 5.1.5 Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s TM1 or TM2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt. 5.1.6 PROCHOT# Signal Pin An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled (note that the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. In a dual core implementation, only a single PROCHOT# pin exists at a package level. When either core's thermal sensor trips, PROCHOT# signal will be driven by the processor package. If only TM1 is enabled, PROCHOT# will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated. If TM2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed TM2 performance state. Note: It is important to note that Intel recommends both TM1 and TM2 be enabled. When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores, then both processor cores will have their core clocks modulated. If TM2 is enabled on both cores, then both processor core will enter the lowest programmed TM2 performance state. One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very 90 Datasheet Thermal Specifications and Design Considerations short periods of time when running the most power intensive applications. An underdesigned thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. § Datasheet 91