WGCE5037SL9FV882558

CE5037 Digital Satellite Tuner with RF Bypass Data Sheet Features • • • • • • • • • Direct conversion tuner for quadrature down conversion from L-band to Zero IF Symbol rate 1-45 MS/s High sensitivity < -83 dBm at 27.5 MS/s Code rate 7/8 Independent RF AGC and baseband gain control Fifth order baseband filters with bandwidth adjustable from 6 to 43 MHz Fully integrated alignment-free low phase noise local oscillator Selectable RF Bypass Low power consumption 0.5W at 3.3V. 28 pin 5x5 mm QFN Package Ordering Information WGCE5037 882557 28 Pin QFN* Trays WGCE5037 S L9FV 882558 28 Pin QFN* Tape & Reel *Pb Free Matte Tin January 2007 -10 ° C to +85 ° C Description The CE5037 is a fully integrated direct conversion tuner for digital satellite receiver systems. It provides excellent immunity to composite undesired channels. The device also contains a RF Bypass for connecting to a second receiver module. The CE5037 is simple to use, requiring no alignment or tuning algorithms and uses a minimum number of external components. The device is programmable via a I2C compatible bus. The CE5037 is qualified for DVB-S2 8PSK receiver applications A complete reference design (CE9542) is available using CE6313 demodulator. Applications • • • DVB-S PayTV satellite receivers DSS satellite receivers DVB-S2 8PSK satellite receivers RF AGC CE5037 I RF Input Q Bypass Output Quadrature I2C Control VCO PLL Loop Filter Crystal Figure 1 - Basic Block Diagram 1 Intel Corporation Order Number: D55745-002 Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007 Intel Corporation. All rights reserved. CE6313 QPSK Demodulator CE5037 Table of Contents Data Sheet 1.0 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Local Oscillator Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 Register Map and Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 RF Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Base Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 Local Oscillator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 General Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 DVB-S2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Baseband Filter Bandwidth Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.0 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.0 Typical Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2 Intel Corporation CE5037 Data Sheet SLEEP IOUT VccBB SDA P0 XCAP XTAL VccDIG VccCP PUMP SCL QOUT QOUT RFAGC N/C RFIN N/C RFIN N/C VccRF1 RFBYPASS VccRF2 CE5037 1 PAD/REF Vvar LOTEST VccVCO VccLO IOUT Ground - Package Paddle Figure 2 - Pin Diagram Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name Vvar PAD/REF VccVCO VccLO LOTEST VccRF2 VccRF1 N/C RFIN N/C RFIN N/C RFAGC Description LO Tuning Voltage Vvar Reference Ground / Continuity Test VCO Supply LO Supply LO Test pin - do not connect RF Supply RF Supply Not connected RF Input Not connected RF Complementary Input Not connected RF Gain control input Pin # 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name QOUT QOUT VccBB IOUT IOUT SLEEP SCL SDA P0 XCAP XTAL VccDIG VccCP PUMP Description Q Channel baseband output Q Channel baseband output Baseband Supply I Channel baseband output I Channel baseband output Hardware power down input I2C Clock I2C Data General purpose switching output Crystal oscillator feedback Crystal oscillator crystal input Digital Supply Varactor Tuning Supply PLL charge pump output RFBYPASS RF Bypass output Table 1 - Pin Names Note: Ground contact is via underside of package. Pin 2 is connected to ground internally. 3 Intel Corporation CE5037 Data Sheet BF BANDWIDTH ADJUST VccBB QOUT VccFE1 VccFE2 FILTER QOUT RFAGC DC CORRECTION DC CORRECTION RFIN RFIN FILTER 10dB switched gain (RFG) RFBYPASS IOUT IOUT 90 deg 0 deg PHASE SPLITTER VccLO LOTEST Vvar PAD/REF VccVCO (PADDLE) LOCK DETECT VCO BANK 15 BIT PROGRAMMABLE DIVIDER Fpd CHARGE PUMP VccCP PUMP VccDIG Fcomp SDA SCL I2C BUS INTERFACE PORT INTERFACE P0 SLEEP XTAL XCAP REF OSC REFERENCE DIVIDER Figure 3 - Detailed Block Diagram 4 Intel Corporation CE5037 1.0 1.1 Data Sheet Circuit Description Functional Description The CE5037 is a single chip wide band direct conversion tuner with integral RF bypass optimised for digital satellite receiver systems. It provides excellent signal handling capability in the presence of high composite signal levels. The device offers a highly integrated solution for a satellite tuner incorporating a low phase noise PLL frequency synthesizer, the quadrature down converter, a fully integrated local oscillator, and programmable baseband channel filters. A minimal number of additional peripheral components are required. The crystal reference source can be also used as the reference for the demodulator. An I2C compatible bus interface controls all of the tuner functionality. The CE5037 contains both hardware and software power down modes. 1.2 1.2.1 Signal Path RF Input The tuner RF input signal at a frequency of 950 – 2150 MHz is fed to the CE5037 RF input pre-amplifier stage. The signal handling is designed such that no tracking filter is required to offer immunity to input signal composite overload. The RF input amplifier feeds an AGC stage, which provides RF gain control. There is additional gain adjustment in the baseband section. The total AGC gain range will guarantee an operating dynamic range of –92 to –10 dBm. The RF AGC in the CE5037 is divided into two stages. The first stage is a continually variable gain control stage, and provides the main system AGC set under control of the analogue AGC signal generated by the demodulator section. The second stage is a programmable gain stage to reduce RF gain by 10 dB. This would normally be used when an external LNA is being used to improve system sensitivity. The analogue RF AGC is optimised for S/N and S/I performance across the full dynamic range. Typical RF AGC characteristic and variation of IIP3, IIP2 and NF are shown in Section 8 - Typical Performance Curves. The output of the AGC stage is coupled to the quadrature mixer where the RF signal is mixed with quadrature local oscillator signals generated by the on-board local oscillator. 1.2.2 Baseband The outputs of the quadrature down converter are passed through the baseband filters followed by a programmable baseband gain stage. The baseband paths are DC coupled. An integrated DC correction loop prevents saturation due to local oscillator self-mixing in the converter section. No external components are required for dc correction. The baseband filters are 5th order Chebychev and provide excellent matching in both amplitude and phase between the I and Q channels. The filters are fully programmable for 3 dB bandwidths from 6 MHz to 43 MHz. The recommended filter bandwidth is related to the required symbol rate by the following equation. − 3dBFilterBandwidth fc = SymbolRate × 1.35 2 × 0.8 This equation makes no allowance for LNB tuning offset at low symbol rates < 10 MS/s. 5 Intel Corporation CE5037 Data Sheet The baseband filter uses an automatic tuning algorithm to calibrate the filter bandwidth to the programmed requirement. This removes any variation due to operating conditions and process variations. The automatic tuning algorithm uses a frequency locked loop, which locks the filter bandwidth to a reference frequency derived from the crystal reference input frequency. Further details are provided in the programming section. The filters are followed by a programmable gain stage. This provides twelve 1.5 dB gain steps. These can be used for optimising performance at different symbol rates and for adjusting the output level in applications not using CE6313. The differential outputs of each channel stage are designed for low impedance drive capability and low intermodulation. The device can also be used in single-ended applications with unused outputs. 1.2.3 RF Bypass The CE5037 provides a single ended bypass function, which can be used for driving a second receiver module. The electrical characteristics of the RF input are unchanged whether the RF bypass is enabled or disabled. The RF Bypass powers up in the enabled state and can also operate with the remainder of the device in power down modes. 1.3 1.3.1 Local Oscillator Generation On Chip VCO The local oscillator on the CE5037 is fully integrated. It consists of three independently selectable oscillator stages with sub bands. The three oscillators and sub-bands are designed to provide optimum phase noise performance over the required tuning range of 950 to 2150 MHz, over operating conditions and process variations. The local oscillators operate at a harmonic of the required local oscillator frequency and are divided down to the required LO frequency. The required divider ratio is automatically selected by the local oscillator control logic. The oscillators are fully controlled by an on-chip automatic tuning algorithm. The user simply programs the required LO frequency. The control logic automatically selects the required VCO and sub band to give optimum performance. VCO settling time is minimized as different tuning algorithms are used, depending on the magnitude of the LO frequency change required. This choice of algorithm is also automatic and does not require user intervention. The oscillator control logic tracks any changes in operating conditions and will retune the VCO if necessary, however hysteresis is built into this function to avoid unnecessary switching. All oscillator components are included on the chip including the VCO varactor. An external loop filter is required as part of the PLL frequency synthesizer. 1.3.2 PLL Frequency Synthesizer The fully integrated PLL frequency synthesizer section controls the LO frequency. The only external requirements are crystal reference and simple second order loop filter. The PLL can be operated up to comparison frequencies of 2 MHz enabling a wide loop bandwidth for maximizing the close in phase noise performance. The local oscillator input signal is multiplexed from the active oscillator to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier provides the input to a 15-bit fully programmable divider with MN+A architecture incorporating a dual modulus 16/17 prescaler. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider, which is programmable into 1 of 15 ratios. 6 Intel Corporation CE5037 Data Sheet The output of the phase detector feeds a charge pump which combined with an external loop filter integrates the current pulses to control the varactor voltage. The charge pump current is automatically varied by the VCO control logic to compensate for VCO gain variations that are dependent on selected sub band. The varactor control voltage is externally coupled to the oscillator section through the input pin Vvar. 1.4 I2C Interface All programming for the CE5037 is controlled by an I2C data bus and is compatible with 3V3 standard mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is logic ‘0’, and read mode if it is logic ‘1’. The I2C address is fixed at C0 (Write)/C1(Read) in hex format. The CE5037 contains 16 control registers. These registers are read/write registers. These registers are addressed as sub-addresses on the I2C bus. Registers can be addressed as random access single write/read or random access sequential write and read as shown below. Random Access Single Write Stop Start Device W A Address Register Address N A Register Data N A Stop Random Access Sequential Write Stop Start Device W A Address Register Address N A Register Data N A Register Data N+1 ... Register Data N+M A Stop Stop Random Access Single Read Stop Start Device W A Address Register Address N A Start Device Address R A Register Data N N Stop Random Access Sequential Read Stop Start Device W A Address Register Address N A Start Device Address R A Register Data N A ... Register Data N+M N Stop W A N Write bit Acknowledge Bit Not Acknowledge A SLEEP pin is provided. This powers down all sections of the chip including the crystal oscillator and I2C interface. The RF bypass function will be operational in this mode providing it has been previously enabled through the I2C interface. 7 Intel Corporation CE5037 2.0 Register Map and Programming Data Sheet The register map is arranged as 16 byte-wide read/write registers grouped by functional block. The registers may be written to and read-back from either sequentially (for lowest overhead) or specifically (for maximum flexibility). A significant number of bits are used for test and evaluation purposes only and are fixed at logic ‘0’ or ‘1’. The correct programming for these test bits is shown in the table below. It is essential that these values are programmed for correct operation. When the contents of the registers are read back the value of some bits may have changed from their programmed value. This is due to the internal automatic control which can update registers. Any changes can be ignored. Read only bits are marked with an asterisk (*). Any data written to these bits will be ignored. Registers are set to default settings on applying power. These conditions are shown below and in the applicable tables. Register 0 1 2 3 4 5 6 7 8 9 A B C D E F PLL PLL PLL PLL RF Front End Base Band Base Band Base Band Local Oscillator Local Oscillator Local Oscillator Local Oscillator Local Oscillator Local Oscillator Local Oscillator General Block PLF 27 0 X* X* BF7 0 BLF* FLF* 1 1 X* 1 X* X* PD 214 26 0 1 1 BF6 LF BG3 0 0 1 X* 1 X* X* CLR 213 25 C1 0 1 BF5 SF BG2 1 1 1 1 0 X* 1 P0 Function 212 24 C0 0 0 BF4 BR4 BG1 0 0 1 1 1 1 1 0 211 23 R3 0 1 BF3 BR3 BG0 0 0 0 1 0 0 0 X* 210 22 R2 0 1 BF2 BR2 0 0 0 0 0 0 0 0 X* 29 21 R1 0 LEN BF1 BR1 0 0 1 0 0 0 0 0 X* 28 20 R0 0 RFG BF0 BR0 0 0 0 1 0 0 0 0 X* Table 2 - Register Map X* denotes a read only test bit 8 Intel Corporation CE5037 2.1 PLL Registers Data Sheet There are four registers that control the PLL: Bit Field 7 6:0 Name PLF 2[14:8] Default 0 Type R R/W PLL Lock Flag MSB bits of LO Divider register Description Table 3 - Register 0 The PLF bit is the PLL lock detect circuit output. The PLF bit is set after 64 consecutive comparison cycles in lock. A chip-wide reset initializes the lock detect output to 0. The 2[14:8] bits are the MSB bits of the LO Divider divide value. Bit Field 7:0 Name 2[7:0] Default 0 Type R/W Table 4 - Register 1 Description LSB bits of LO Divider register The 2[7:0] bits are the LSB bits of the LO Divider divide value. The division ratio of the LO divider is fully programmable to integer values within the range of 240 to 32767. Note that when the LO Divider divide value is to be changed, the new value is not actually presented to the LO Divider until all of the 15-bit control word 2[14:0] has been programmed. Register 0 and 1 must be therefore be programmed (in any order) before the LO divider is updated even if the only data change is in one of the registers. Bit Field 7:6 5:4 3:0 Name C[1:0] R[3:0] Default 0 0 0 Type R/W R/W R/W Test modes Charge pump current Reference divider ratio Description Table 5 - Register 2 The C[1:0] bits set the programmed charge pump current C[1] 0 0 1 1 C[0] 0 1 0 1 . Typ 400 550 750 1000 Units uA uA uA uA Table 6 - Charge Pump Currents The charge pump current is automatically increased to the next setting dependent on the VCO sub band that has been selected by the VCO tuning algorithm. This is to compensate for changes in VCO gain and so provide consistent PLL performance across all sub bands. Programming the highest charge pump value will not allow the value to be incremented, therefore this value should not be programmed. The value read back for the charge pump current is the actual value in use for the selected sub band. 9 Intel Corporation CE5037 Data Sheet The R[3:0] bits select the Reference Divider divide ratio. The ratio selected is not a simple binary power-of-two value but through a lookup table, see Table 7- PLL Reference Divider Ratios. Division Ratio 2 4 8 16 32 64 128 256 3 5 10 20 40 80 160 320 R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 7 - PLL Reference Divider Ratios Bit Field 7:0 Name - Default 0X40 Type R/W Test Modes Description Table 8 - Register 3 This register controls test modes within the PLL. This should be programmed with the default settings. 2.2 RF Control Register A single register controls RF programmability. Bit Field 7 6:2 1 0 Name LEN RFG Default 11011 1 0 Type R R/W R/W R/W Test Modes Test Modes Bypass Enable RF Gain Adjust Description Table 9 - Register 4 10 Intel Corporation CE5037 Data Sheet The LEN bit enables the RFBYPASS output. With this bit set, the RF Bypass is active even if ‘software’ or ‘hardware’ power down has been selected. The RFG bit controls the gain of the second section of RF gain control. With this bit set, the RF gain is reduced by 10dB. This setting would normally used when an external LNA is being used. 2.3 Base Band Registers There are three registers that control the Base Band: Bit Field 7:0 Name BF[7:0] Default 0X3C Type R/W Description Base Band Filter Cut-Off Frequency Table 10 - Register 5 The bits BF[7:0] control the bandwidth of the baseband filter. An automatic adjustment routine synchronizes the filter bandwidth to a reference frequency derived from the crystal. Bit Field 7 6 5 4:0 Name LF SF BR[4:0] Default 0 0 0 1000 Type R/W R/W R/W R/W Test Mode Baseband Filter Adjust Disable Baseband Filter Adjust Disable Base Band Reference Division Ratio Description Table 11 - Register 6 The LF and SF bits disable the baseband filter adjustment. It is recommended that these bits are set after programming the filter bandwidth to prevent interactions within the circuit. These bits must be reset to enable the baseband filter bandwidth to be reprogrammed. The BR[4:0] bits set the crystal reference divide ratio. This effectively determines the resolution setting of the baseband filters. The baseband filter settings (BF[7:0]) can be calculated from the following equation. BF[7 : 0] = (Filter bandwidth (MHz) * 5.088 * BR[4 : 0]) −1 CrystalFrequency (MHz) See Section 3 Applications Information, for a typical programming example. BR[4:0] = 0 is invalid Bit Field 7 6:3 2:0 Name BLF BG[3:0] Default 0111 000 Type R R/W R/W Description Base Band Lock Flag Base Band Gain Select Test Modes Table 12 - Register 7 The BLF bit indicates that the baseband adjustment has completed and locked. The control bits BG[3:0] define the gain of the Base Band post-filter amplifier. The following table shows the gain note this is relative gain. The 1.5 dB gain steps enable the baseband output level to be adjusted and optimise gain distribution for different symbol rates. 11 Intel Corporation CE5037 BG[3] 0 0 0 0 0 0 0 0 1 1 1 1 BG[2] 0 0 0 0 1 1 1 1 0 0 0 0 BG[1] 0 0 1 1 0 0 1 1 0 0 1 1 BG[0] 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB) 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 Data Sheet Table 13 - BG[3:0] Control of Base Band Post Filter Gain 2.4 Local Oscillator Registers There are seven registers that control the Local Oscillator: These are used primarily for test and evaluation by Intel Corporation. Although VCO’s can be manually programmed, the user is recommended to use the default automatic settings as these provide optimum performance. Bit Field 7 6:0 Name FLF Default 0X20 Type R R/W Full Lock Flag Test Modes Description Table 14 - Register 8 The FLF bit is the VCO tuning controller lock output and is set when PLL is locked and the automatic VCO tuning is optimised and complete. Register 9 to Register E are for test modes only. It is however important that these registers are programmed with the values shown. 12 Intel Corporation CE5037 Bit Field 7:0 Name Default 0XA2 Type R/W Test Modes Description Data Sheet Table 15 - Register 9 Bit Field 7:0 Name Default 0XF1 Type R/W Test Modes Description Table 16 - Register A Bit Field 7:6 5:0 Name Default 0X38 Type R R/W Description Test Modes (read only) Test Modes Table 17 - Register B Bit Field 7:0 Name - Default 0XD0 Type R/W Test Modes Description Table 18 - Register C Bit Field 7:5 4:0 Name Default 0X10 Type R R/W Description Test Modes (read only) Test Modes Table 19 - Register D Bit Field 7:6 5:0 Name Default 0X30 Type R R/W Description Test Modes (read only) Test Modes Table 20 - Register E 13 Intel Corporation CE5037 2.5 General Control Register Data Sheet This register controls powerdown and general control functions: Bit Field 7 6 5 4 3:0 Name PD CLR P0 Default 1 0 0 0 Type R/W R/W R/W R/W R Power Down Clear and reset logic Port 0 control Test Mode Test Modes (Read only) Description Table 21 - Register F The PD bit is the ‘software’ power down control. When this bit is set to 1, all the analogue blocks are powered down with the exception of the Crystal Oscillator. The I2C interface will remain active and can still be used to enable the RF Bypass. Setting the SLEEP input pin high also invokes ‘software’ power down with the addition of powering down the Crystal Oscillator to produce ‘hardware’ power down. The RF Bypass will remain active if it has been previously programmed on the I2C bus. Note that in ‘hardware’ power down, the I2C interface does not operate. The CLR bit re-triggers the power-on-reset function. This resets all register values to their power-on reset default value. The CLR bit is itself cleared. Note that the chip-wide reset will reset the I2C Interface and the current write sequence used to set this bit will not be acknowledged. The P0 bit controls the state of the output port according to Table 22. P0 0 1 Output Port State Off, high impedance On, current sinking Table 22 - Output Port States 14 Intel Corporation 3.0 SL EEP +3V 3_D +3V3_D C2 8 C31 100 nF 100nF 100 nF 100 nF C3 2 C3 3 C3 4 100 nF C3 56p F R8 470R XTAL X1 10.111MHz R9 C5 100 K +3V 3_D C2 5 Vcore +3V 3_D R11 22K 10n F TP 11 R10 36K +3V 3_A C1 1 47p F Applications Information LOOP F ILTER C4 56p F TP 1 R1 NF 2 R1 47K 3 +3V 3_D C1 0 220 nF 55 39 5 R2 8K2 TP 12 R3 10n F 8K2 Vd d Vd d Vd d Vd d CVd d CVd d CVd d 28 26 25 27 24 23 22 C6 10n F R14 100 R R5 100 K 16 OscMod e R15 100 R DA TA2 14 CLK2 15 C7 220 pF 19 20 XTI XTO Digital R17 4k7 +3V 3_D C1 2 10p F C1 3 10p F SCL SLE EP IOUT IOUTB +3V 3_A 17 16 15 R2 3 1K R2 4 1K2 PA D C1 22p F C2 NF R6 C1 7 22p F C1 8 NF 51R R1 51R 8 C14 C21 22p F C4 5 NF 100nF VccBB QO UTB QO UT Pad dle 18 R1 51R 9 C4 8 22p F C5 1 NF 24 25 29 30 41 R2 5 100 R 19 R2 51R 0 20 DA TA2 CL K2 21 R16 4k7 C9 22p F Ana e logu Digital P0 ADDR4 ADDR3 ADDR2 ADDR1 CLK +3V3_D CVd d CVd d CVd d CVd d CVd d CVd d DATA 27 34 32 22 59 50 44 17 12 7 38 37 36 35 PUMP VccDIG 2 PA D/RE F XTALCAP Vva r VccCP 1 XTAL SDA MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 48 49 52 53 56 57 60 61 R2 1 33R MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 CE5037 15 U3 CE5037 C2 6 10nF C2 7 10nF C2 9 10nF C3 0 10nF 3 U1 I in I in Q in Q in AG C Digital Ana e logu +3V3_A VccVCO 4 VccLO CE6313 R2 2 33R C2 4 10u F 5 LO TEST Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Te st Vc cFE 1 nc RF IN nc RF INB nc SK1 +3V 3_A RF AGC 58 54 51 45 40 21 18 13 8 6 33 31 28 26 23 8 9 10 11 12 13 14 1nF L3 BLM18RK102 SN1D +3V3_D Vco re C47 220nF C3 5 C3 6 nF 100nF 100 C3 7 C3 8 C3 9 100 nF 100 nF 100 nF C4 0 C4 1 C4 2 C43 C44 100 nF 100 nF 100 nF 100nF 100nF RFin 950-2150MHz 75 Ohms C5 7 100 pF C4 6 220 nF C1 5 220nF C2 0 100 pF C5 8 1pF C2 3 10n F SK2 C1 9 L1 4.7 nH 47p F Figure 4 - Typical Application with CE6313 Demodulator MOVAL BK ERR MO STRT MOCLK IRQ DATA1 CL K1 Sle ep Sta tus Re set DiS EqC0 DiS EqC1 DiS EqC2 47 63 46 62 43 11 10 9 64 1 4 3 2 VL NBRF D1 BAR63-03W 42 Intel Corporation TP 17 C16 220 nF C22 100pF 6 RFBYPA SS MOVAL BKERR MOSTRT MOCLK IRQ DA TA1 CLK1 SLEEP STATUS RESET DISEQC0 DISEQC1 DISEQC2 7 VccFE2 C8 Data Sheet CE5037 3.1 General Design Guidelines Data Sheet Figure 4 shows a typical application using a CE6313 as a demodulator. This is available as a reference design (CE9542) from Intel Corporation. The design uses a standard two layer board. All components are mounted on the upper surface with the lower surface as a ground plane. The RF input requires a coupling capacitor and series inductor for optimum matching. The RF bypass output requires a coupling capacitor. Good decoupling should be used - these components should be mounted as close to the device as practicable. All ground contact to the CE5037 is to the ground ‘paddle’ on the underside of the package. This must be soldered fully to the board to achieve best thermal and electrical contact. It is recommended that an array of vias (4 x 4) is used to achieve good contact to the ground plane underneath the device A common crystal reference can be used for the tuner and demodulator. The crystal oscillator capacitors are optimised for a 10.111 MHz reference. Sensitivity is optimised by minimizing interaction from digital signal activity in the demodulator. This is achieved by filtering in the agc control, and filter networks in the baseband I and Q signals between the demodulator and CE5037. These networks should be mounted as close to the CE5037 as possible. The typical performance from the reference design is shown in the table below: Parameter Sensitivity C/N 27.5MS/s rate 7/8 2e-4 post Viterbi BER C/N 2MS/s rate 7/8 2e-4 post Viterbi BER Interference Rejection Ratio 27.5 MS/s rate 7/8. Interferers at -25 dBm Typ. -83 8.3 8.1 8.1 8.2 8.0 8.0 32 35 45 35 Units dBm dB dB dB dB dB dB dB dB dB dB Notes QEF 27.5MS/s rate 7/8 No added noise Input = -69 dBm -45 dBm -23 dBm Input = -81dBm -45 dBm -23 dBm N+1 N+4 N+10 2 Interferers at -25dBm Table 23 - Typical Performance using CE5037 and CE6313 Further information is provided in CE9542 user guides. The CE5037 can also be used with other demodulators. If the demodulator has a single-ended input then the CE5037 can be used with a single-ended outputs ie IOUT and QOUT. The unused outputs should be loaded with an equivalent load to the demodulator input to maintain a good balanced configuration. The optimum output level for the demodulator can be achieved by adjusting the post filter baseband gain. 3.2 DVB-S2 Applications The excellent performance of the CE5037 makes the device also suitable for the higher level modulation schemes (8PSK) used for DVB-S2. In the critical areas of quadrature accuracy and phase noise, typical performance is shown in the following table. 16 Intel Corporation CE5037 Parameter Quadrature Amplitude Matching Quadrature Phase Matching Integrated Phase Noise LO = 950MHz Integrated Phase Noise LO = 1500MHz Integrated Phase Noise LO = 2150MHz Value < 0.5 dB