5962-0625601QXC

® 5962-0625601QXC, 5962-0625602QXC Data Sheet October 17, 2007 FN6491.1 1.4GHz Current Feedback Amplifiers with Enable The 5962-0625601QXC and 5962-0625602QXC are fully DSCC SMD compliant parts and the SMD data sheets are available on the DSCC website (http://www.dscc.dla.mil/ programs/specfind/default.asp). The 5962-0625601QXC is electrically equivalent to the EL5166, the 5962-0625602QXC is electrically equivalent to the EL5167. Reference equivalent “EL” data sheet for additional information. The amplifiers are of the current feedback variety and exhibit a very high bandwidth of 1.4GHz at AV = +1 and 800MHz at AV = +2. This makes these amplifiers ideal for today's high speed video and monitor applications, as well as a number of RF and IF frequency designs. With a supply current of just 12mA and the ability to run from a single supply voltage from 5V to 12V, these amplifiers offer very high performance for little power consumption. The 5962-0625601QXC also incorporates an enable and disable function to reduce the supply current to 13µA typical per amplifier. Allowing the CE pin to float or applying a low logic level will enable the amplifier. Features • Gain-of-1 bandwidth = 1.4GHz/gain-of-2 bandwidth = 800MHz • 6000V/µs slew rate • Single and dual supply operation from 5V to 12V • Low noise = 1.5nV/√Hz • 12mA supply current • Fast enable/disable (5962-0625601QXC only) Applications • Video amplifiers • Cable drivers • RGB amplifiers • Test equipment • Instrumentation • Current to voltage converters Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # 5962-0625601QXC 06256 01QXC 5962-0625602QXC 06256 02QXC 10 Ld Flat Pack K10.A 10 Ld Flat Pack K10.A NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pinouts 5962-0625601QXC (10 LD FLAT PACK) TOP VIEW 1 2 3 4 5 NC ININ+ VSNC NC NC CE VS+ OUT 10 9 8 7 6 1 2 3 4 5 5962-0625602QXC (10 LD FLAT PACK) TOP VIEW NC ININ+ VSNC NC NC NC VS+ OUT 10 9 8 7 6 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 5962-0625601QXC, 5962-0625602QXC Absolute Maximum Ratings (TA = +25°C) Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 12.6V Slewrate between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 20mA I into VIN+, VIN-, Enable Pins . . . . . . . . . . . . . . . . . . . . . . . . . ±4mA Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) Flat Pack Package (Notes 1, 2) . . . . . . 165 60 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . .-55°C to +125°C Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144mW CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER AC PERFORMANCE BW -3dB Bandwidth VS+ = +5V, VS- = -5V, RF = 392Ω for AV = 1, RF = 250Ω for AV = 2, RL = 150Ω, TA = +25°C Unless Otherwise Specified. CONDITIONS MIN TYP MAX UNIT DESCRIPTION AV = +1 AV = +2 1400 800 100 6000 8 1.7 19 50 MHz MHz MHz V/µs ns nV/√Hz pA/√Hz pA/√Hz % ° BW1 SR tS eN iNiN+ dG dP 0.1dB Bandwidth Slew Rate 0.1% Settling Time Input Voltage Noise IN- Input Current Noise IN+ Input Current Noise Differential Gain Error (Note 3) Differential Phase Error (Note 3) AV = +2 VO = -2.5V to +2.5V, AV = +2 VOUT = -2.5V to +2.5V, AV = -1 AV = +2 AV = +2 0.01 0.03 INPUT CHARACTERISTICS CIN Input Capacitance 1.5 pF ENABLE (5962-0625601QXC ONLY) tEN tDIS NOTE: 3. Standard NTSC test, AC signal amplitude = 286mV, f = 3.58MHz. Enable Time Disable Time 170 1.25 ns µs 2 FN6491.1 October 17, 2007 5962-0625601QXC, 5962-0625602QXC Pin Descriptions 5962-0625601QXCIS (10 Ld FLAT PACK) 1, 5, 9, 10 2 5962-0625602QXCIS (10 ld FLAT PACK) 1, 5, 8 , 9 ,10 2 Pin Name NC INFunction Not connected Inverting input VS+ Equivalent Circuit IN+ IN- VSCIRCUIT 1 3 4 6 3 4 6 IN+ VSOUT Non-inverting input Negative supply Output (See circuit 1) VS+ OUT VSCIRCUIT 2 7 8 7 VS+ CE Positive supply Chip enable VS+ CE VSCIRCUIT 3 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 3 FN6491.1 October 17, 2007 5962-0625601QXC, 5962-0625602QXC Ceramic Metal Seal Flatpack Packages (Flatpack) K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B) e -Ab PIN NO. 1 ID AREA E1 0.004 M H A-B S DS 0.036 M -B- 10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A A D INCHES SYMBOL A b b1 MIN 0.045 0.015 0.015 0.004 0.004 0.240 0.125 0.030 0.008 0.250 0.026 0.005 10 MAX 0.115 0.022 0.019 0.009 0.006 0.290 0.260 0.280 0.015 0.370 0.045 0.0015 MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 6.10 3.18 0.76 1.27 BSC 0.20 6.35 0.66 0.13 10 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 7.37 6.60 7.11 NOTES 3 3 7 2 8 6 Rev. 0 3/07 S1 H A-B S DS c c1 D E E1 E2 E3 e k L Q S1 M N Q A -C- E C -D-H- L E3 E2 E3 LEAD FINISH L SEATING AND BASE PLANE 0.050 BSC c1 BASE METAL b1 M M (b) SECTION A-A (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 4 FN6491.1 October 17, 2007