68HC68T1M

® CDP68HC68T1 Data Sheet March 17, 2006 FN1547.7 CMOS Serial Real-Time Clock With RAM and Power Sense/Control The CDP68HC68T1 Real-Time Clock provides a time/calendar function, a 32 byte static RAM, and a 3 wire Serial Peripheral Interface (SPI Bus). The primary function of the clock is to divide down a frequency input that can be supplied by the on-board oscillator in conjunction with an external crystal or by an external clock source. The internal oscillator can operate with a 32kHz, 1MHz, 2MHz, or 4MHz crystal. An external clock source with a 32kHz, 1MHz, 2MHz, 4MHz, 50Hz or 60Hz frequency can be used to drive the CDP68HC68T1. The time registers hold seconds, minutes, and hours, while the calendar registers hold day-of-week, date, month, and year information. The data is stored in BCD format. In addition, 12 or 24 hour operation can be selected. In 12 hour mode, an AM/PM indicator is provided. The T1 has a programmable output which can provide one of seven outputs for use elsewhere in the system. Computer handshaking is controlled with a “wired-OR” interrupt output. The interrupt can be programmed to provide a signal as the result of: 1) an alarm programmed to occur at a predetermined combination of seconds, minutes, and hours; 2) one of 15 periodic interrupts ranging from sub-second to once per day frequency; 3) a power fail detect. The PSE output and the VSYS input are used for external power control. The CPUR output is available to reset the processor under power-down conditions. CPUR is enabled under software control and can also be activated via the CDP68HC68T1’s watchdog. If enabled, the watchdog requires a periodic toggle of the CE pin without a serial transfer. Features • SPI (Serial Peripheral Interface) • Full Clock Features - Seconds, Minutes, Hours (12/24, AM/PM), Day of Week, Date, Month, Year (0-99), Automatic Leap Year • 32 Word x 8-Bit RAM • Seconds, Minutes, Hours Alarm • Automatic Power Loss Detection • Low Minimum Standby (Timekeeping) Voltage . . . . . 2.2V • Selectable Crystal or 50/60Hz Line Input • Buffered Clock Output • Battery Input Pin that Powers Oscillator and also Connects to VDD Pin When Power Fails • Three Independent Interrupt Modes - Alarm - Periodic - Power-Down Sense • Pb-Free Plus Anneal Available (RoHS Compliant) Pinouts CDP68HC68T1 (PDIP, SOIC) TOP VIEW CLKOUT CPUR INT SCK MOSI MISO CE VSS 1 2 3 4 5 6 7 8 16 VDD 15 XTAL OUT 14 XTAL IN 13 VBATT 12 VSYS 11 LINE 10 POR 9 PSE CLK OUT CPUR INT NC SCK MOSI MISO CE VSS CDP68HC68T1 (SOIC) TOP VIEW 1 2 3 4 5 6 7 8 9 20 VDD 19 XTAL OUT 18 XTAL IN 17 NC 16 VBATT 15 VSYS 14 NC 13 NC 12 LINE 11 POR PSE 10 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1997. Copyright Intersil Americas Inc. 2001, 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Ordering Information PART NUMBER CDP68HC68T1E CDP68HC68T1EZ (Note) CDP68HC68T1M* CDP68HC68T1MZ* (Note) CDP68HC68T1M2* PART MARKING CDP68HC68T1E TEMP RANGE (°C) PKG PACKAGE DWG. # E16.3 -40 to 85 16 Ld PDIP CDP68HC68T1EZ -40 to 85 16 Ld PDIP** E16.3 (Pb-free) 68HC68T1M 68HC68T1MZ HC68T1M2 -40 to 85 20 Ld SOIC -40 to 85 20 Ld SOIC (Pb-free) -40 to 85 16 Ld SOIC -40 to 85 16 Ld SOIC (Pb-free) M20.3 M20.3 M16.3 M16.3 CDP68HC68T1M2Z* HC68T1M2Z (Note) *Add “96” suffix for taoe and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. Pin number references throughout this specification refer to the 16 lead PDIP/SOIC. See pinouts for cross reference. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN1547.7 March 17, 2006 Absolute Maximum Ratings Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V Current Drain Per Input Pin Excluding VDD and VSS, I . . . . . . 10mA Current Drain Per Output Pin, I . . . . . . . . . . . . . . . . . . . . . . . . 40mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) 16 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 20 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range (TSTG). . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC, Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +6.0V Standby (Timekeeping) Voltage . . . . . . . . . . . . . . . . . +2.2V to +6.0V Temperature Range CDP68HC68T1E (PDIP Package) . . . . . . . . . . . . . .-40°C to 85°C CDP68HC68T1M/M2 (SOIC Packages) . . . . . . . . .-40°C to 85°C Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . .(0.7 x VDD) to VDD Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0V to (0.3 x VDD) Serial Clock Frequency (fSCK). . . . . . . . . . . . . . . . . . +3.0V to +6.0V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Static Electrical Specifications At TA = -40°C to +85°C, VDD = VBATT = 5V ±5%, except as noted. CDP68HC68T1 PARAMETER Quiescent Device CurrentIDD Output Voltage High LevelVOH Output Voltage Low LevelVOL Output Voltage High LevelVOH Output Voltage Low LevelVOL Input Leakage CurrentIIN Three-State Output Leakage CurrentIOUT Operating Current (Note 3) (ID + IB) VDD = VB = 5V Crystal Operation 32kHz 1MHz 2MHz 4MHz Pin 14 External Clock (Squarewave) (Note 3) (ID + IB) VDD = VS = 5V 32kHz 1MHz 2MHz 4MHz Standby Current (Note 3)IB V S = 3V Crystal Operation 32kHz 1MHz 2MHz 4MHz Operating Current (Note 3) VDD = 5V, VB = 3V Crystal Operation IOH = -1.6mA, VDD = 4.5V IOL = 1.6mA, VDD = 4.5V IOH ≤ 10µA, VDD = 4.5V IOL ≤ 10µA, VDD = 4.5V CONDITIONS MIN 3.7 - (NOTE 2) TYP 1 0.08 0.5 0.7 1 0.02 0.1 0.2 0.4 20 200 300 500 ID IB 15 0.15 0.25 0.4 MAX 10 0.4 0.1 ±1 ±10 0.01 0.6 0.84 1.2 0.024 0.12 0.24 0.5 25 250 360 600 ID 30 0.1 0.18 0.36 IS 20 0.18 0.3 0.5 UNITS µA V 4.4 - - µA mA µA mA 32kHz 1MHz 2MHz 4MHz - 25 0.08 0.15 0.3 3 FN1547.7 March 17, 2006 Static Electrical Specifications At TA = -40°C to +85°C, VDD = VBATT = 5V ±5%, except as noted. (Continued) CDP68HC68T1 PARAMETER Standby Current (Note 3)IB VB = 2.2V Crystal Operation Input Capacitance CIN Maximum Rise and Fall Timestr, tf (Except XTAL Input and POR Pin 10) Input Voltage (Line Input Pin Only, Power Sense Mode) VSYS > VBVT (For VB Not Internally Connected to VDD) Power-On Reset (POR) Pulse Width NOTES: 2. Typical values are for TA = 25°C and nominal VDD. 3. Clock out (Pin 1) disabled, outputs open circuited. No serial access cycles. CONDITIONS 32kHz MIN (NOTE 2) TYP 10 MAX 12 UNITS µA VIN = 0, TA = 25°C 0 100 10 1.0 75 2 2 12 - pF µs V V ns 4 FN1547.7 March 17, 2006 Functional Block Diagram CE FREEZE CIRCUIT AM - PM AND HOUR LOGIC CALENDAR LOGIC LINE 50/60Hz XTAL IN XTAL OUT OSCILLATOR PRESCALE SECOND MINUTE HOUR DAY/DAY OF WEEK MONTH 5 FN1547.7 March 17, 2006 VBATT PRESCALE SELECT CLOCK OUT INT VDD VSS CLOCK AND INT LOGIC CLOCK SELECT CLOCK CONTROL REGISTER INTERRUPT CONTROL REGISTER COMPARATOR SECOND LATCH MINUTE LATCH 8-BIT DATA BUS YEAR HOUR LATCH LINE VSYS POR PSE CPUR SCK MISO MOSI SERIAL INTERFACE POWER SENSE CONTROL INT STATUS REGISTER 32 X 8 RAM FIGURE 1. REAL TIME CLOCK FUNCTIONAL DIAGRAM 0 $00 32 33 34 SECONDS MINUTES HOURS DAY OF WEEK DATE MONTH YEARS NOT USED SEC ALARM MIN ALARM HRS ALARM NOT USED NOT USED NOT USED NOT USED NOT USED STATUS REGISTER CONTROL REGISTER INTERRUPT CONTROL REGISTER R, W R, W R, W R, W R, W R, W R, W $20 $21 $22 $23 $24 $25 $26 $27 32 RAM LOCATIONS 35 36 37 31 32 CLOCK/CALENDAR 50 51 $1F $20 38 39 40 41 W W W $28 $29 $2A $2B $2C $2D $2E $2F $32 $33 42 43 44 45 13 BYTES UNUSED 46 47 48 R R, W R, W $30 $31 $32 63 85 R = READABLE TEST MODE W = WRITABLE $3F $55 49 50 FIGURE 2. ADDRESS MAP TABLE 1. CLOCK/CALENDAR AND ALARM DATA MODES ADDRESS LOCATION (H) 20 21 22 Seconds Minutes Hours 12 Hour Mode (Note 5) Hours 24 Hour Mode 23 24 25 26 28 29 2A Day of the Week (Sunday = 1) Day of the Month (Date) Month Jan = 1, Dec = 12 Years Alarm Seconds Alarm Minutes Alarm Hours (Note 6) 12 Hour Mode Alarm Hours 24 Hour Mode NOTES: 4. Example: 3:49:18, Tuesday. Oct. 29,1985. 5. Most significant Bit, D7, is “0” for 24 hours, and “1” for 12 hour mode. Data Bit D5 is “1” for P.M. and ‘0” for A.M. in 12 hour mode. 6. Alarm hours. Data Bit D5 is “1” for P.M. and “0” for A.M. in 12 hour mode. Data Bits D7 and D6 are DON’T CARE. FUNCTION DECIMAL RANGE 0-59 0-59 1-12 BCD DATA RANGE 00-59 00-59 81-92 (AM) A1-B2 (PM) 00-23 01-07 01-31 01-12 00-99 00-59 00-59 01-12 (AM) 21-32 (PM) 00-23 (NOTE 4) BCD DATE EXAMPLE 18 49 A3 0-23 1-7 1-31 1-12 0-99 0-59 0-59 1-12 0-23 15 03 29 10 85 18 49 23 15 6 FN1547.7 March 17, 2006 Programmers Model - Clock Registers HEX ADDRESS DB7 TENS 0-5 20 TENS 0-5 21 12 HR 24 X X PM/AM TENS 0-2 UNITS 0-9 DB7, 1 = 12 HR., 0 = 24 HR. DB = 1 PM, 0 = AM HOURS (01-12 OR 00-23 DAY OF WK (01-07) SUNDAY = 1 01-28 29 30 31 UNITS 0-9 UNITS 0-9 WRITE/READ REGISTERS DB0 SECONDS (00-59) NAME MINUTES (00-59) 22 23 X X X X UNITS 1-7 24 TENS 0-3 UNITS 0-9 DATE DAY OF MONTH 25 TENS 0-1 UNITS 0-9 MONTH (01-12) JAN = 1 DEC = 12 26 7 TENS 0-9 UNITS 0-9 YEARS (00-99) 31 6 5 4 3 2 1 0 CONTROL 7 32 6 5 4 3 2 1 0 INTERRUPT WRITE ONLY REGISTERS ALARM SECONDS (00-59) ALARM MINUTES (00-59) ALARM HOURS (01-12 OR 00-23) PLUS AM/PM IN 12 HR. MODE PM = 1, AM = 0 28 29 X TENS 0-5 TENS 0-5 PM/AM TENS 0-2 UNITS 0-9 UNITS 0-9 2A X UNITS 0-9 READ ONLY REGISTERS 30 7 6 5 4 3 2 1 0 STATUS 7 D7 RAM DATA BYTE 6 D6 5 D5 BIT 4 3 D3 2 D2 1 D1 D0 0 D4 HEX ADDRESS 00-1F NOTE: X = Don’t care writes, X = 0 when read. 7 FN1547.7 March 17, 2006 Functional Description The SPI real-time clock consists of a clock/calendar and a 32 x 8 RAM. Communications is established via the SPI (Serial Peripheral Interface) bus. In addition to the clock/calendar data from seconds to years, and system flexibility provided by the 32-byte RAM, the clock features computer handshaking with an interrupt output and a separate squarewave clock output that can be one of 7 different frequencies. An alarm circuit is available that compares the alarm latches with the seconds, minutes and hours time counters and activates the interrupt output when they are equal. The clock is specifically designed to aid in power-down/up applications and offers several pins to aid the designer of battery backup systems. years information. Data in the counters is in BCD format. The hours counter utilizes BCD for hour data plus bits for 12/24 hour and AM/PM. The 7 time counters are accessed serially at addresses 20H through 26H. (See Table 1). RAM The real-time clock also has a static 32 x 8 RAM that is located at addresses 00-1FH. Transmitting the address/control word with bit-5 low selects RAM access. Bits 0 through 4 select the RAM location. Alarm The alarm is set by accessing the three alarm latches and loading the required data. The alarm latches consist of seconds, minutes and hours registers. When their outputs equal the values in the seconds, minutes and hours time counters, an interrupt is generated. The interrupt output will go low if the alarm bit in the Interrupt Control Register is set high. The alarm interrupt bit in the Status Register is set when the interrupt occurs (see Pin Functions, INT Pin). To preclude a false interrupt when loading the time counters, the alarm interrupt bit should be set low in the Interrupt Control Register. This procedure is not required when the alarm time is set. Mode Select The voltage level that is present at the VSYS input pin at the end of power-on-reset selects the device to be in the single supply or battery backup mode. Single-Supply Mode If VSYS is a logic high when power-on-reset is completed, CLK OUT, PSE and CPUR will be enabled and the device will be completely operational. CPUR will be placed low if the logic level at the VSYS pin goes low. If the output signals CLK OUT, PSE and CPUR are disabled due to a powerdown instruction, VSYS brought to a logic low and then to a logic high will re-enable these outputs. An example of the single-supply mode is where only one supply is available and VDD , VBATT and VSYS are tied together to the supply. Watchdog Function (See Figure 6) When bit 7 in the Interrupt Control Register is set high, the Clock’s CE (chip enable) pin must be toggled at a regular interval without a serial data transfer. If the CE is not toggled, the clock will supply a CPU reset pulse and bit 6 in the Status Register will be set. Typical service and reset times are listed below. 50Hz MIN Service Time Reset Time 20 MAX 10ms 40ms 60Hz MIN 16.7 MAX 8.3ms 33.3ms XTAL MIN 15.6 MAX 7.8ms 31.3ms Battery Backup Mode If VSYS is a logic low at the end of power-on-reset, CLK OUT, PSE and CPUR will be disabled (CLK OUT, PSE and CPUR low). This condition will be held until VSYS rises to a threshold (about 1.0V) above VBATT. The outputs CLK OUT, PSE and CPUR will then be enabled and the device will be operational. If VSYS falls below a threshold above VBATT the outputs CLK OUT, PSE and CPUR will be disabled. An example of battery backup operation occurs if VSYS is tied to VDD and VDD is not connected to a supply when a battery is connected to the VBATT pin. (See Pin Functions, VBATT for Battery Backup Operation.) Clock Out The value in the 3 least significant bits of the Clock Control Register selects one of seven possible output frequencies. (See Clock Control Register). This squarewave signal is available at the CLK OUT pin. When Power-Down operation is initiated, the output is set low. Clock/Calendar (See Figures 1 and 2) The clock/calendar portion of this device consists of a long string of counters that is toggled by a 1Hz input. The 1Hz input is generated by a prescaler driven by an on-board oscillator that utilizes one of four possible external crystals or that can be driven by an external clock source. The 1Hz trigger to the counters can also be supplied by a 50Hz or 60Hz input source that is connected to the LINE input pin. The time counters offer seconds, minutes and hours data in 12 hour or 24 hour format. An AM/PM indicator is available that once set, toggles every 12 hours. The calendar counters consist of day (day of week), date (day of month), month and 8 Control Registers and Status Registers The operation of the Real-Time Clock is controlled by the Clock Control and Interrupt Control Registers. Both registers are Read-Write Registers. Another register, the Status Register, is available to indicate the operating conditions. The Status Register is a Read only Register. Power Control Power control is composed of two operations, Power Sense and Power Down/Up. Two pins are involved in power sensing, the LINE input pin and the INT output pin. Two additional pins are utilized during power-down/up operation. They are the PSE (Power Supply Enable) output pin and VSYS input pin. FN1547.7 March 17, 2006 XTAL IN INT XTAL OUT VDD 0V LINE CPU CDP68HC05C16B INT VDD REAL-TIME CLOCK CDP68HC68T1 I STATUS REGISTER FIGURE 3. POWER-SENSING FUNCTIONAL DIAGRAM FROM SYSTEM POWER TO SYSTEM POWER CONTROL POWER UP PSE POWER SENSE OR ALARM CIRCUIT PERIODIC INTERRUPT SIGNAL SERIAL INTERFACE MOSI REAL-TIME CLOCK CDP68HC68T1 VSYS I INTERRUPT CONTROL REGISTER PSE CLK OUT CPUR MISO MOSI CPUR CLK OUT OSC RESET SERIAL INTERFACE REAL-TIME CLOCK CDP68HC68T1 INT MISO CPU CDP68HC05C4B FIGURE 4. POWER-DOWN FUNCTIONAL DIAGRAM FIGURE 5. POWER-UP FUNCTIONAL DIAGRAM (INITIATED BY INTERRUPT SIGNAL Power Sensing (See Figure 3) When Power Sensing is enabled (Bit 5 = 1 in Interrupt Control Register), AC transitions are sensed at the LINE input pin. Threshold detectors determine when transitions cease. After a delay of 2.68ms to 4.64ms, plus the external input circuit RC time constant, an interrupt is generated and a bit is set in the Status Register. This bit can then be sampled to see if system power has turned back on. See PIN FUNCTIONS, LINE PIN. The power-sense circuitry operates by sensing the level of the voltage presented at the line input pin. This voltage is centered around VDD and as long as it is either plus or minus a threshold (about 1V) from VDD a power-sense failure will not be indicated. With an AC signal present, remaining in this VDD window longer than a minimum of 2.68ms will activate the power-sense circuit. The larger the amplitude of the AC signal, the less time it spends in the VDD window, and the less likely a power failure will be detected. A 60Hz, 10VP-P sinewave voltage is an applicable signal to present at the LINE input pin to setup the power sense function. Power Down (See Figure 4) Power down is a processor-directed operation. A bit is set in the Interrupt Control Register to initiate operation. 3 pins are affected. The PSE (Power Supply Enable) output, normally high, is placed low. The CLK OUT is placed low. The CPUR output, connected to the processors reset input is also placed low. In addition, the Serial Interface is disabled. Power Up (See Figures 5 and 6) Two conditions will terminate the Power-Down mode. The first condition (See Figure 5) requires an interrupt. The interrupt can be generated by the alarm circuit, the programmable periodic interrupt signal, or the power sense circuit. The second condition that releases Power Down occurs when the level on the VSYS pin rises about 1.0V above the level at the VBATT input, after previously falling to the level of VBATT (See Figure 6) in the Battery Backup Mode or VSYS falls to logic low and returns high in the Single Supply Mode. FN1547.7 March 17, 2006 9 CE A positive chip-enable input. A low level at this input holds the serial interface logic in a reset state. This pin is also used for the watchdog function. VBATT VSYS PSE CPUR CLK OUT MISO VSS The negative power-supply pin that is connected to ground. PSE Power-supply enable output pin. This pin is used to control power to the system. The pin is set high when: 1. VSYS rises above the VBATT voltage after VSYS was placed low by a system failure. 2. 2An interrupt occurs. 3. A power-on reset (if VSYS is a logic high). The PSE pin is set low by writing a high into bit 6 (powerdown bit) in the Interrupt Control Register. SERIAL INTERFACE REAL-TIME CLOCK CDP68HC68T1 MOSI FIGURE 6. POWER-UP FUNCTIONAL DIAGRAM (INITIATED BY A RISE IN VOLTAGE ON THE “VSYS” PIN) CLK OUT Clock output pin. One of seven frequencies can be selected (or this output can be set low) by the levels of the three LSB’s in the Clock-Control Register. If a frequency is selected, it will toggle with a 50% duty cycle except 2Hz in the 50Hz time base mode. (Ex, if 1Hz is selected, the output will be high for 500ms and low for the same period). During power-down operation (bit 6 in Interrupt Control Register set to “1”), the clock-output pin will be set low. POR Power-on reset. A Schmitt-trigger input that generates a power-on internal reset signal using an external R-C network. Both control registers and frequency dividers for the oscillator and line input are reset. The Status Register is reset except for the first time up bit (B4), which is set. Single supply or battery backup operation is selected at the end of POR. CPUR CPU reset output pin. This pin functions as an N-Channel only, open-drain output and requires an external pull-up resistor. LINE This input is used for two functions. When not used it should be connected to VDD via a 10kΩ resistor. The first function utilizes the input signal as the frequency source for the timekeeping counters. This function is selected by setting bit 6 in the Clock Control Register. The second function enables the line input to sense a power failure. Threshold detectors operating above and below VDD sense an AC voltage loss. Bit 5 must be set to “1” in the Interrupt Control Register and crystal or external clock source operation is required. Bit 6 in the Clock Control Register must be low to select XTAL operation. INT Interrupt output pin. This output is driven from a single NFET pulldown transistor and must be tied to an external pull-up resistor. The output is activated to a low level when: 1. Power-sense operation is selected (B5 = 1 in Interrupt Control Register) and a power failure occurs. 2. A previously set alarm time occurs. The alarm bit in the Status Register and interrupt-out signal are delayed 30.5µs when 32kHz operation is selected and 15.3µs for 2MHz and 7.6µs for 4MHz. 3. A previously selected periodic interrupt signal activates. The Status Register must be read to set the Interrupt output high after the selected periodic interval occurs. This is also true when conditions 1 and 2 activate the interrupt. If power down had been previously selected, the interrupt will also reset the power-down functions. Oscillator Circuit The CDP68HC68T1 has an on-board 150K resistor that is switched in series with its internal inverter when 32kHz is selected via the Clock Control Register. Note: When first powered up the series resistor is not part of the oscillator circuit. (The CDP68HC68T1 sets up for a 4MHz oscillator). SCK, MOSI, MISO See Serial Peripheral Interface (SPI) section in this data sheet. 10 FN1547.7 March 17, 2006 R (NOTE 8) XTAL IN 22M T1 XTAL OUT 5 - 30pF C1 LlNE-XTAL When this bit is set high, clock operation will use the 50 or 60-cycle input present at the LINE input pin. When the bit is low, the crystal input will generate the 1Hz time update. CRYSTAL XTAL Select One of 4 possible crystals is selected by value in these two bits: 0 = 4.194304MHz 2 = 1.048576MHz 3 = 32,768Hz C2 10 - 40pF NOTES: 7. All frequencies recommended oscillator circuit. C1, C2 values crystal dependent. 8. R used for 32KHz operation only. 100K - 300K range as specified by crystal manufacturer. FIGURE 7. OSCILLATOR CIRCUIT 1 = 2.097152MHz 50-60Hz 50Hz is selected as the line input frequency when this bit is set high. A low will select 60Hz. The power-sense bit in the Interrupt Control Register must be set low for line frequency operation. VSYS This input is connected to the system voltage. After the CPU initiates power down by setting bit 6 in the Interrupt Control Register to “1”, the level on this pin will terminate power down if it rises about 1.0V above the level at the VBATT input pin after previously falling below VBATT +1.0V. When power down is terminated, the PSE pin will return high and the Clock Output will be enabled. The CPUR output pin will also return high. The logic level present at this pin at the end of POR determines the CDP68HC68T1’s operating mode. Clock Out The three bits specify one of the 7 frequencies to be used as the squarewave clock output: 0 = XTAL 1 = XTAL/2 2 = XTAL/4 3 = XTAL/8 4 = Disable (low output) 5 = 1Hz 6 = 2Hz 7 = 50Hz or 60Hz XTAL Operation = 64Hz VBATT The oscillator power source. The positive terminal of the battery should be connected to this pin. When the level on the VSYS pin falls below VBATT +1.0V, the VBATT pin will be internally connected to the VDD pin. When the voltage on VSYS rises a threshold above (1.0V) the voltage on VBATT, the connection from VBATT to the VDD pin is opened. When the “LINE” input is used as the frequency source, VBATT may be tied to VDD or VSS . The “XTAL IN” pin must be at VSS if VBATT is at VSS . If VBATT is connected to VDD , the “XTAL IN” pin can be tied to VSS or VDD . All bits are reset by a power-on reset. Therefore, the XTAL is selected as the clock output at this time. Interrupt Control Register Watchdog When this bit is set high, the watchdog operation will be enabled. This function requires the CPU to toggle the CE pin periodically without a serial-transfer requirement. In the event this does not occur, a CPU reset will be issued. Status Register must be read before re-enabling watchdog. Power Down A high in this location will initiate a power down. A CPU reset will occur, the CLK OUT and PSE output pins will be set low and the serial interface will be disabled. XTAL IN, XTAL OUT These pins are connected to a 32,768Hz. 1.048576MHz, 2.097152MHz or 4.194304MHz crystal. If an external clock is used, it should be connected to “XTAL IN” with ‘XTAL OUT” left open. Power Sense This bit is used to enable the line input pin to sense a power failure. It is set high for this function. When power sense is selected, the input to the 50Hz to 60Hz prescaler is disconnected. Therefore, crystal operation is required when power sense is enabled. An interrupt is generated when a power failure is sensed and the power sense and Interrupt True bit in the Status Register are set. When power sense is activated, a “0” must be written to this location followed by a “1” to re-enable power sense. VDD The positive power-supply pin. Clock Control Register START-STOP A high written into this bit will enable the counter stages of the clock circuitry. A low will hold all bits reset in the divider chain from 32Hz to 1Hz. A clock out selected by bits 0, 1 and 2 will not be affected by the stop function except the 1Hz and 2Hz outputs. 11 FN1547.7 March 17, 2006 Alarm The output of the alarm comparator is enabled when this bit is set high. When a comparison occurs between the seconds, minutes and hours time and alarm counters, the interrupt output is activated. When loading the time counters, this bit should be set low to avoid a false interrupt. This is not CLOCK CONTROL REGISTER (Write/Read) - Address 31H D7 START D6 LINE D5 XTAL SEL STOP XTAL 1 D4 XTAL SEL 0 required when loading the alarm counters. See Pin Functions, INT for explanation of alarm delay. Periodic Select The value in these 4 bits will select the frequency of the periodic output. (See Table 2). D3 50Hz D2 CLK OUT D1 CLK OUT D0 CLK OUT 60Hz 2 1 0 INTERRUPT CONTROL REGISTER (Write/Read) - Address 32H D7 WATCHDOG D6 POWER DOWN D5 POWER SENSE D4 ALARM D3 D2 D1 D0 PERIODIC SELECT NOTE: All bits are reset by power-on reset. TABLE 2. PERIODIC INTERRUPT OUTPUT PERIODIC INTERRUPT OUTPUT FREQUENCY Disable 2048Hz 1024Hz 512Hz 256Hz 128Hz 64Hz 50 or 60Hz 7 8 9 10 11 12 13 14 15 32Hz 16Hz 8Hz 4Hz 2Hz 1Hz Minute Hour Day X X X X X X X X X X X X X X X X X X X X X FREQUENCY TIME BASE XTAL LINE D0 - D3 VALUE 0 1 2 3 4 5 6 12 FN1547.7 March 17, 2006 STATUS REGISTER (Read Only) - Address 30H D7 0 D6 WATCHDOG D5 TEST MODE D4 FIRST TIME UP D3 INTERRUPT TRUE D2 POWER SENSE INTERRUPT D1 ALARM INTERRUPT D0 CLOCK INTERRUPT TRUTH TABLE SIGNAL MODE DISABLE RESET WRITE CE L H SCK (Note 9) INPUT DISABLED CPOL = 1 MOSI INPUT DISABLED DATA BIT LATCH MISO HIGH Z HIGH Z CPOL = 0 READ H CPOL = 1 X NEXT DATA BIT SHIFTED OUT (Note 10) CPOL = 0 NOTES: 9. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer’s Control Register. 10. MISO remains at a high Z until 8-bits of data are ready to be shifted out during a READ. It remains at a high Z during the entire WRITE cycle. WATCHDOG If this bit is set high, the watchdog circuit has detected a CPU failure. Pin Signal Description SCK (Serial Clock Input, Note 11) This input causes serial data to be latched from the MOSI input and shifted out on the MISO output. TEST MODE When this bit is set high, the device is in the TEST MODE. MOSI (Master Out/Slave In, Note 11) Data bytes are shifted in at this pin, most significant bit (MSB) first. FIRST-TIME UP Power-on reset sets this bit high. This signifies that data in the RAM and Clock is not valid and should be initialized. MISO (Master In/Slave Out) Data bytes are shifted out at this pin, most significant bit (MSB) first. INTERRUPT TRUE A high in this bit signifies that one of the three interrupts (Power Sense, Alarm, and Clock) is valid. CE (Chip Enable, Note 12) A positive chip-enable input. A low level at this input holds the serial interface logic in a reset state, and disables the output driver at the MISO pin. NOTES: 11. These inputs will retain their previous state if the line driving them goes into a High-Z state. 12. The CE input has as internal pull down device, if the input is in a low state before going to High Z, the input can be left in a High Z. POWER-SENSE INTERRUPT This bit set high signifies that the power-sense circuit has generated an interrupt. ALARM INTERRUPT When the seconds, minutes and hours time and alarm counter are equal, this bit will be set high. Status Register must be read before loading Interrupt Control Register for valid alarm indication after alarm activates. CLOCK INTERRUPT A periodic interrupt will set this bit high. All bits are reset by a power-on reset except the “FIRSTTIME UP” which is set. All bits except the power-sense bit are reset after a read of this register. 13 FN1547.7 March 17, 2006 Functional Description The Serial Peripheral Interface (SPI) utilized by the CDP68HC68T1 is a serial synchronous bus for address and data transfers. The clock, which is generated by the microcomputer is active only during address and data transfers. In systems using the CDP68HC05C4 or CDP68HC05D2, the inactive clock polarity is determined by the CPOL bit in the microcomputer’s Control Register. A unique feature of the CDP68HC68T1 is that it automatically determines the level of the inactive clock by sampling SCK when CE becomes active (see Figure 8). Input data (MOSI) is latched internally on the internal strobe edge and output data (MISO) is shifted out on the shift edge, as defined by Figure 8. There is one clock for each data bit transferred (address, as well as data bits are transferred in groups of 8). CE CPOL = 1 SCK INTERNAL SHIFT STROBE Address And Data Format There are three types of serial transfer: 1. Address Control - Figure 9. 2. READ or WRITE Data - Figure 10. 3. Watchdog Reset (actually a non-transfer) Figure 11. The Address/Control and Data bytes are shifted MSB first, Into the serial data input (MOSI) and out of the serial data output (MISO). Any transfer of data requires an Address/Control byte to specify a Write or Read operation and to select a Clock or RAM location, followed by one or more bytes of data. Data is transferred out of MISO for a Read and into MOSI for a Write operation. Address/Control Byte - Figure 9 It is always the first byte received after CE goes true. To transmit a new address, CE must first go false and then true again. Bit 5 is used to select between Clock and RAM locations. CE CPOL = 0 SCK SHIFT INTERNAL STROBE MOSI MSB MSB -1 NOTE: “CPOL” is a bit that is set in the microcomputer’s Control Register. FIGURE 8. SERIAL RAM CLOCK (SCK) AS A FUNCTION OF MCU CLOCK POLARITY (CPOL) BIT 7 W/R 6 0 A0-A4 CLK RAM 0 W/R 5 CLK RAM 4 A4 3 A3 2 A2 1 A1 0 A0 04 5 6 7 Selects 5-Bit HEX Address of RAM or specifies Clock Register. Most Significant Address Bit. If equal to “1”, A0 through A4 selects a Clock Register. If equal to “0”, A0 through A4 selects one of 32 RAM locations. Must be set to ”0” when not in Test Mode 7W/R W/R = “1” initiates one or more WRITE cycles.W/R = “0”, initiates one or more READ cycles. CE SCK (NOTE) MOSI W/R 0 CLOCK RAM A4 A3 A2 A1 A0 NOTE: SCK can be either polarity. FIGURE 9. ADDRESS/CONTROL BYTE-TRANSFER WAVEFORMS 14 FN1547.7 March 17, 2006 Read/Write Data (See Figure 10) Read/Write data follows the Address/Control byte. BIT 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 CE SCK (NOTE) MOSI D7 D6 D5 D4 D3 D2 D1 D0 MISO D7 D6 D5 D4 D3 D2 D1 D0 NOTE: SCK can be either polarity. FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS Watchdog Reset (See Figure 11) When watchdog operation is selected, CE must be toggled periodically or a CPU reset will be outputted. SERVICE TIME CE SCK CPUR SERVICE TIME Address And Data Data transfers can occur one byte at a time (Figure 12) or in a multibyte burst mode (Figure 13). After the Real-Time Clock enabled, an Address/Control word is sent to set the CLOCK or RAM and select the type of operation (i.e., Read or Write). For a single-byte Read or Write, one byte is transferred to or from the Clock Register or RAM location specified in the Address/Control byte and the Real-Time Clock is then disabled. Write cycle causes the latched Clock Register or RAM address to automatically increment. Incrementing continues after each transfer until the device is disabled. After incrementing to 1FH the address will “wrap” to 00H and continue. Therefore, when the RAM is selected the address will “wrap” to 00H and when the clock is selected the address will “wrap” 20H. FIGURE 11. WATCHDOG OPERATION WAVEFORMS 15 FN1547.7 March 17, 2006 CE SCK WRITE MOSI ADDRESS BYTE WRITE DATA MOSI ADDRESS BYTE READ MISO READ DATA FIGURE 12. SINGLE-BYTE TRANSFER WAVEFORMS CE SCK WRITE MOSI ADDRESS BYTE DATA BYTE DATA BYTE DATA BYTE MOSI READ ADDRESS BYTE MISO DATA BYTE DATA BYTE W/R ADDRESS DATA BYTE +1 DATA BYTE + (n-1) DATA BYTE DATA BYTE FIGURE 13. MULTIPLE-BYTE TRANSFER WAVEFORMS 16 FN1547.7 March 17, 2006 Dynamic Electrical Specifications Bus Timing VDD ±10%, VSS = 0VDC, TA = 40°C to 85°C LIMITS (ALL TYPES) VDD = 3.3V VDD = 5V MIN 100 125 200 200 100 100 200 MAX 100 100 100 100 100 UNITS ns ns ns ns ns ns ns ns ns ns ns ns IDENT. NO 1 2 3 4 5 7 8 11 12 A B C PARAMETER Chip Enable Setup TimetEVCV Chip Enable After Clock Hold TimetCVEX Clock Width HightWH Clock Width LowtWL Data In to Clock Setup TimetDVCV Clock to Data Propagation DelaytCVDV Chip Disable to Output High ZtEXQZ Output Rise Timetr Output Fall Timetf Data in After Clock Hold TimetCVDX Clock to Data Out ActivetCVQX Clock Recovery TimetREC MIN 200 250 400 400 200 200 200 MAX 200 200 200 200 200 - 17 FN1547.7 March 17, 2006 Timing Diagrams 5 MOSI W/R A6 A0 A 5 D7O D6O D1N DON CE I SCK 4 3 C 2 FIGURE 14. WRITE-CYCLE TIMING WAVEFORMS 5 MOSI W/R A6 A0 A 8 MISO D7O 7 CE I SCK 4 3 C D6O DIN 11 12 DON 8 2 FIGURE 15. READ-CYCLE TIMING WAVEFORMS System Diagrams AC LINE BRIDGE REGULATOR VDD POR INT VSYS LINE CDP68HC68T1 VBATT VDD IRQ VDD CDP68HC05C8B XTAL IN CPUR CE SCK MOSI MISO RESET PORT SCK MOSI MISO NOTE: Example of a system in which power is always on. Clock circuit driven by line input frequency. FIGURE 16. POWER-ON ALWAYS SYSTEM DIAGRAM 18 FN1547.7 March 17, 2006 System Diagrams AC LINE (Continued) BRIDGE GENERATOR VBATT VDD POR VSYS VDD INT CDP68HC68T1 LINE CPUR CLK OUT CE MISO VDD MOSI SCK VDD IRQ CDP68HC05C8B RESET OSC 1 PORT (e.g., PCO) MISO MOSI SCK NOTE: Example of a system in which the power is controlled by an external source. The LINE input pin can sense when the switch opens by use of the POWER-SENSE INTERRUPT. The CDP68HC68T1 crystal drives the clock input to the CPU using the CLK OUT pin. On power down when VSYS < VBATT + 1.0V. VBATT will power the CDP68HC68T1. A threshold detect activates a P-Channel switch, connecting VBATT to VDD . VBATT always supplies power to the oscillator, keeping voltage frequency variation to a minimum. FIGURE 17. EXTERNALLY CONTROLLED POWER SYSTEM DIAGRAM A Procedure for Power-Down Operation might consist of the following: 1. Set power sense operation by writing bit 5 high in the Interrupt Control Register. 2. When an interrupt occurs, the CPU reads the Status Register to determine the interrupt source. 3. Sensing a power failure, the CPU does the necessary housekeeping to prepare for shutdown. 4. The CPU reads the Status Register again after several milliseconds to determine validity of power failure. 5. The CPU sets power-down bit 6 and disables all interrupts in the Interrupt Control Register when power down is verified. This causes the CPU reset and clock out to be held low and disconnects the serial interface. 6. When power returns and VSYS rises above VBATT, power down is terminated. The CPU reset is released and serial communication is established. 19 FN1547.7 March 17, 2006 System Diagrams AC LINE (Continued) (EPS) ENABLED POWER SUPPLY NC 0.1 REGULATOR 0.047 R CHARGE 100k POR VBATT VDD VSYS VDD 1k PSE 22M XTAL CPUR VDD RESET CDP68HC05C4B IRQ OSC1 PORT 3 SPI VSS LINE 20k RTC VDD INT CLK OUT CE VSS SPI FIGURE 18. EXAMPLE OF A SYSTEM WITH A BATTERY BACKUP 20 FN1547.7 March 17, 2006 System Diagrams (Continued) CLOCK BUTTON ENABLED POWER IGNITION 5V REG + LINE VBATT POR PSE XTAL 2MHz CPUR T1 CDP68HC05C4B CLK OUT OSC1 RESET VDD VSYS VDD PORT 12V - INT SPI VSS CE 3 IRQ SPI PORT VSS Example of an automotive system. The VSYS and LINE inputs can be used to sense the ignition turning on and off. An external switch is included to activate the system without turning on the ignition. Also, the CMOS CPU is not powered down with the system VDD , but is held in a low power reset mode during power down. When restoring power the CDP68HC68T1 will enable the CLK OUT pin and set the PSE and CPUR high. Important Application Note: Those units with a code of 6PG have delayed alarm interrupts of 8.3ms regardless of CDP68HC68T1’s operating frequency. (See Pin Functions, INT.) In addition, reading the Status Register before delayed alarm activates will disable alarm signal. FIGURE 19. AUTOMOTIVE SYSTEM DIAGRAM 21 FN1547.7 March 17, 2006 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 -C- A2 B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 22 FN1547.7 March 17, 2006 Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45° 0.25(0.010) M BM M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 10.00 0.25 0.40 16 8° 0° 8° MAX 2.65 0.30 0.51 0.32 10.50 7.60 10.65 0.75 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914 0.394 0.010 0.016 16 0° MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992 0.419 0.029 0.050 A1 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 23 FN1547.7 March 17, 2006 Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45° 0.25(0.010) M BM M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.35 0.23 12.60 7.40 10.00 0.25 0.40 20 8° 0° 8° MAX 2.65 0.30 0.49 0.32 13.00 7.60 10.65 0.75 1.27 NOTES 9 3 4 5 6 7 Rev. 2 6/05 MIN 0.0926 0.0040 0.014 0.0091 0.4961 0.2914 0.394 0.010 0.016 20 0° MAX 0.1043 0.0118 0.019 0.0125 0.5118 0.2992 0.419 0.029 0.050 A1 B C D E e H C e B 0.25(0.010) M C AM BS α A1 0.10(0.004) 0.050 BSC 1.27 BSC h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 FN1547.7 March 17, 2006