7242IPAZ

® ICM7242 Data Sheet February 9, 2007 FN2866.4 Long Range Fixed Timer The ICM7242 is a CMOS timer/counter circuit consisting of an RC oscillator followed by an 8-bit binary counter. It will replace the 2242 in most applications, with a significant reduction in the number of external components. Three outputs are provided. They are the oscillator output, and buffered outputs from the first and eighth counters. Features • Replaces the 2242 in Most Applications • Timing From Microseconds to Days • Cascadable • Monostable or Astable Operation • Wide Supply Voltage Range . . . . . . . . . . . . . . . 2V to 16V • Low Supply Current . . . . . . . . . . . . . . . . . . . . 115µA at 5V PACKAGE 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) PKG. DWG. # E8.3 E8.3 M8.15 VDD 1 2 3 4 8 7 6 5 TB I/O RC TRIGGER RESET Ordering Information PART TEMP. PART NUMBER MARKING RANGE (°C) ICM7242IPA ICM7242IPAZ (See Note) 7242 IPA 7242 IPAZ -25 to +85 -25 to +85 0 to +70 -25 to +85 • Pb-Free Plus Anneal Available (RoHS Compliant) Pinout ICM7242 (8 LD PDIP, SOIC) TOP VIEW ICM7242CBAZ* 7242 CBAZ ICM7242IBAZ* 7242 IBAZ M8.15 ÷2 OUT ÷128/256 OUT VSS *Add “-T” suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1996, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICM7242 Functional Block Diagram R1 50k CL + R2 86k R S R Q Q CL Q S S Q CL S Q CL Q S Q CL Q S Q CL Q S Q Q + 7 RC R3 50k - Q CL Q S Q CL Q S Q Q 1 VDD 4 VSS 8 TB I/O 5 RESET 6 2 3 TRIGGER ÷2 OUT ÷128/256 OUTPUT 2 FN2866.4 February 9, 2007 ICM7242 Absolute Maximum Ratings Supply Voltage (VDD to VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Input Voltage (Note 1) Terminals (Pins 5, 6, 7, 8). . . . . . . . . . (VSS -0.3V) to (VDD +0.3V) Continuous Output Current (Each Output). . . . . . . . . . . . . . . . 50mA Thermal Information Thermal Resistance (Typical, Note2) θJA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range ICM7242I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C ICM7242C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same supply be applied to the device before its supply is established and, that in multiple supply systems, the supply to the ICM7242 be turned on first. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Guaranteed Supply Voltage Supply Current VDD = 5V, TA = +25°C, R = 10kΩ, C = 0.1µF, VSS = 0V, Unless Otherwise Specified SYMBOL VDD IDD Reset Operating, R = 10kΩ, C = 0.1µF Operating, R = 1MΩ, C = 0.1µF TB Inhibited, RC Connected to VSS TEST CONDITIONS MIN 2 Δf/Δt VOTB Independent of RC Components ISOURCE = 100µA ISINK = 1.0mA VDD = 2V VDD = 5V VDD = 15V 50% Duty Cycle Input with Peak to Peak Voltages Equal to VDD and VSS Counter/Divider Mode 2 TYP 125 340 220 225 5 250 3.5 0.40 1.6 3.5 1.3 2.7 10 1 6 13 MAX 16 800 600 25 2.0 4.5 2.0 4.0 UNITS V µA µA µA µA % ppm/°C V V µA V V V V µA MHz MHz MHz Timing Accuracy RC Oscillator Frequency Temperature Drift Time Base Output Voltage Time Base Output Leakage Current Trigger Input Voltage ITBLK VTRIG RC = Ground VDD = 5V VDD = 15V Reset Input Voltage VRST VDD = 5V VDD = 15V Trigger/Reset Input Current Max Count Toggle Rate ITRIG, IRST fT Output Saturation Voltage Output Sourcing Current MIN Timing Capacitor (Note 3) Timing Resistor Range (Note 3) NOTE: 3. For design only, not tested. VSAT ISOURCE CT RT All Outputs Except TB Output VDD = 5V, IOUT = 3.2mA VDD = 5V Terminals 2 and 3, VOUT = 1V 10 0.22 300 - 0.4 22M V µA pF Ω VDD = 2 - 16V 1k 3 FN2866.4 February 9, 2007 ICM7242 Test Circuit VDD 1 ÷21 (RC/2) OUTPUT ÷28 (RC/256) OUTPUT 2 3 4 8 7 6 5 RESET TRIGGER TIME BASE PERIOD = 1.0RC; 1s = 1MΩ x 1µF C R TIME BASE INPUT/OUTPUT VDD NOTE: 4. ÷21 and ÷28 outputs are inverters and have active pullups. Application Information Operating Considerations Shorting the RC terminal or output terminals to VDD may exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages). There is a limitation of 50pF maximum loading on the TB I/O terminal if the timebase is being used to drive the counter section. If higher value loading is used, the counter sections may miscount. For greatest accuracy, use timing component values shown in Figure 8. For highest frequency operation it will be desirable to use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200kHz. The timing capacitor should be connected between the RC pin and the positive supply rail, VDD , as shown in Figure 1. When system power is turned off, any charge remaining on the capacitor will be discharged to ground through a large internal diode between the RC node and VSS. Do NOT reference the timing capacitor to ground, since there is no high current path in this direction to safely discharge the capacitor when power is turned off. The discharge current from such a configuration could potentially damage the device. When driving the counter section from an external clock, the optimum drive waveform is a square wave with an amplitude equal to the supply voltage. If the clock is a very slow ramp triangular, sine wave, etc., it will be necessary to “square up” the waveform; this can be done by using two CMOS inverters in series, operating from the same supply voltage as the ICM7242. The ICM7242 is a non-programmable timer whose principal applications will be very low frequency oscillators and long range timers; it makes a much better low frequency oscillator/timer than a 555 or ICM7555, because of the onchip 8-bit counter. Also, devices can be cascaded to produce extremely low frequency signals. Because outputs will not be ANDed, output inverters are used instead of open drain N-Channel transistors, and the 4 external resistors used for the 2242 will not be required for the ICM7242. The ICM7242 will, however, plug into a socket for the 2242 having these resistors. The timing diagram for the ICM7242 is shown in Figure 1. Assuming that the device is in the RESET mode, which occurs on power up or after a positive signal on the RESET terminal (if TRIGGER is low), a positive edge on the trigger input signal will initiate normal operation. The discharge transistor turns on, discharging the timing capacitor C, and all the flip-flops in the counter chain change states. Thus, the outputs on terminals 2 and 3 change from high to low states. After 128 negative timebase edges, the ÷28 output returns to the high state. TRIGGER INPUT (TERMINAL 6) TIMEBASE INPUT (TERMINAL 8) ÷2 OUTPUT (TERMINAL 2) ÷128/256 OUTPUT (TERMINAL 3) (ASTABLE OR “FREE RUN” MODE) ÷128/256 OUTPUT (TERMINAL 3) (MONOSTABLE OR “ONE SHOT” MODE) 128RC 128RC 128RC FIGURE 1. TIMING DIAGRAMS OF OUTPUT WAVEFORMS FOR THE ICM7242 (COMPARE WITH FIGURE 5) VDD 1 fIN/2 OUTPUTS fIN/256 2 3 4 8 7 6 VDD 5 fIN >3/4 (V+)