7650SCPDZ

® ICL7650S Data Sheet April 12, 2007 FN2920.10 2MHz, Super Chopper-Stabilized Operational Amplifier The ICL7650S Super Chopper-Stabilized Amplifier offers exceptionally low input offset voltage and is extremely stable with respect to time and temperature. It is a direct replacement for the industry-standard ICL7650 offering improved input offset voltage, lower input offset voltage temperature coefficient, reduced input bias current, and wider common mode voltage range. All improvements are highlighted in bold italics in the Electrical Characteristics section. Critical parameters are guaranteed over the entire commercial temperature range. Intersil’s unique CMOS chopper-stabilized amplifier circuitry is user-transparent, virtually eliminating the traditional chopper amplifier problems of intermodulation effects, chopping spikes, and overrange lockup. The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling amplifier, nulled by alternate clock phases. Two external capacitors are required to store the correcting potentials on the two amplifier nulling inputs; these are the only external components necessary. The clock oscillator and all the other control circuitry is entirely self-contained. However the 14 lead version includes a provision for the use of an external clock, if required for a particular application. In addition, the ICL7650S is internally compensated for unity-gain operation. Features • Guaranteed Max Input Offset Voltage for All Temperature Ranges • Low Long-Term and Temperature Drifts of Input Offset Voltage • Guaranteed Max Input Bias Current . . . . . . . . . . . . .10pA • Extremely Wide Common Mode Voltage Range. . . . . . . . . . . . . . . . . . . . . . . +3.5V to -5V • Reduced Supply Current . . . . . . . . . . . . . . . . . . . . . . 2mA • Guaranteed Minimum Output Source/Sink Current • Extremely High Gain . . . . . . . . . . . . . . . . . . . . . . . .150dB • Extremely High CMRR and PSRR . . . . . . . . . . . . . .140dB • High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V/μs • Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2MHz • Unity-Gain Compensated • Clamp Circuit to Avoid Overload Recovery Problems and Allow Comparator Use • Extremely Low Chopping Spikes at Input and Output • Improved, Direct Replacement for Industry-Standard ICL7650 and other Second-Source Parts • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER ICL7650SCBA-1 ICL7650SCBA-1T ICL7650SCBA-1Z (Note) ICL7650SCBA-1ZT (Note) ICL7650SCPA-1 ICL7650SCPA-1Z (Note) ICL7650SCPD ICL7650SCPDZ PART MARKING 7650S CBA-1 7650S CBA-1 7650S CBA-1Z 7650S CBA-1Z 7650S CPA-1 7650S CPA-1Z ICL7650SCPD 7650SCPDZ TEMP. RANGE (°C) 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 PACKAGE 8 Ld SOIC PKG. DWG. # M8.15 8 Ld SOIC (Tape and Reel) M8.15 8 Ld SOIC M8.15 8 Ld SOIC (Tape and Reel) M8.15 8 Ld PDIP 8 Ld PDIP* (Pb-free) 14 Ld PDIP 14 Ld PDIP* (Pb-free) E8.3 E8.3 E14.3 E14.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL7650S Pinouts ICL7650S (8 LD PDIP, SOIC) TOP VIEW CEXTA -IN +IN V1 2 3 4 8 CEXTB V+ OUTPUT CRETN + - 7 6 5 ICL7650S (14 PDIP) TOP VIEW CEXTB 1 CEXTA 2 NC (GUARD) 3 -IN 4 +IN 5 NC (GUARD) 6 V- 7 14 INT/EXT 13 EXT CLK IN 12 INT CLK OUT - 11 V+ 10 OUTPUT 9 OUT CLAMP 8 CRETN + Functional Diagram INT/EXT EXT CLK IN CLK OUT OSC. A A B C INTERNAL BIAS +IN -IN A A + MAIN EXT CLK IN A = CLK OUT P A OUTPUT B N CLAMP B CEXTA CEXTB C - NULL + C CAP RETURN 2 FN2920.10 April 12, 2007 Absolute Maximum Ratings Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +0.3) to (V- -0.3) Voltage on Oscillator Control Pins . . . . . . . . . . . . . . . . . . . . V+ to VDuration of Output Short Circuit. . . . . . . . . . . . . . . . . . . . . Indefinite Current to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA While Operating (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .100μA Thermal Information Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W) 8 Lead PDIP Package* . . . . . . . . . . . . 110 N/A 14 Lead PDIP Package . . . . . . . . . . . . 90 N/A 8 Lead SOIC Package . . . . . . . . . . . . . 160 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . -55°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range ICL7650SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Limiting input current to 100μA is recommended to avoid latchup problems. Typically 1mA is safe, however this is not guaranteed. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Input Offset Voltage (Note 3) VSUPPLY = ±5V. See Test Circuit, Unless Otherwise Specified SYMBOL VOS ΔVOS/ΔT ΔVOS/ΔT IBIAS IOS RIN AVOL VOUT CMVR RL = 10kΩ, VO = ±4V RL = 10kΩ RL = 100kΩ TEST CONDITIONS TEMP. (°C) +25 0 to +70 MIN 135 130 ±4.7 -5 -5 120 120 120 4.5 TYP ±0.7 ±1 0.02 100 4 5 8 10 1012 150 ±4.85 ±4.95 -5.2 to +4 140 140 2 0.01 2 2.5 0.2 20 2 MAX ±5 ±8 10 20 20 40 3.5 3.5 16 3 3.2 UNITS μV μV μV/°C nV/√month pA pA pA pA Ω dB dB V V V V dB dB dB μVP-P pA/√Hz MHz V/μs μs % V mA mA Average Temperature Coefficient of Input Offset Voltage (Note 3) Change in Input Offset with Time Input Bias Current |I(+)|, |I(-)| 0 to +70 +25 +25 0 to +70 Input Offset Current |I(-), |I(+)| +25 0 to +70 Input Resistance Large Signal Voltage Gain (Note 3) +25 +25 0 to +70 Output Voltage Swing (Note 4) +25 +25 +25 0 to +70 Common Mode Voltage Range (Note 3) Common Mode Rejection Ratio (Note 3) Power Supply Rejection Ratio Input Noise Voltage Input Noise Current Gain Bandwidth Product Slew Rate Rise Time Overshoot Operating Supply Range Supply Current CMRR CMVR = -5V to +3.5V VS = ±3V to ±8V RS = 100Ω, f = DC to 10Hz f = 10Hz CL = 50pF, RL = 10kΩ +25 0 to +70 PSRR eN iN GBWP SR tR OS V+ to VISUPP +25 +25 +25 +25 +25 +25 +25 +25 No Load +25 0 to +70 3 FN2920.10 April 12, 2007 Electrical Specifications PARAMETER Output Source Current VSUPPLY = ±5V. See Test Circuit, Unless Otherwise Specified (Continued) SYMBOL IO SOURCE IO SINK fCH Pins 13 and 14 Open RL = 100kΩ -4V ≤ VOUT ≤ +4V TEST CONDITIONS TEMP. (°C) +25 0 to +70 MIN 2.9 2.3 25 20 120 25 TYP 4.5 30 250 70 0.001 MAX 375 5 10 UNITS mA mA mA mA Hz μA nA nA Output Sink Current +25 0 to +70 Internal Chopping Frequency Clamp ON Current (Note 5) Clamp OFF Current (Note 5) +25 +25 +25 0 to +70 NOTES: 3. These parameters are guaranteed by design and characterization, but not tested at temperature extremes because thermocouple effects prevent precise measurement of these voltages in automatic test equipment. 4. OUTPUT CLAMP not connected. See typical characteristic curves for output swing vs clamp current characteristics. 5. See OUTPUT CLAMP under detailed description. 6. All significant improvements over the industry-standard ICL7650 are highlighted in bold italics. Test Circuit R2 1MΩ R1 1MΩ INTERMODULATION Previous chopper-stabilized amplifiers have suffered from intermodulation effects between the chopper frequency and input signals. These arise because the finite AC gain of the amplifier necessitates a small AC signal at the input. This is seen by the zeroing circuit as an error signal, which is chopped and fed back, thus injecting sum and difference frequencies and causing disturbances to the gain and phase vs frequency characteristics near the chopping frequency. These effects are substantially reduced in the ICL7650S by feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current, in such a way as to cancel that portion of the input signal due to finite AC gain. Since that is the major error contribution to the ICL7650S, the intermodulation and gain/phase disturbances are held to very low values, and can generally be ignored. CAPACITOR CONNECTION The null/storage capacitors should be connected to the CEXTA and CEXTB pins, with a common connection to the CRETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting load current IR drops into the capacitive circuitry. The outside foil, where available, should be connected to CRETN. OUTPUT CLAMP The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing junction, a current path between this point and the OUTPUT pin occurs just before the device output saturates. Thus uncontrolled input differentials are avoided, together with the consequent charge buildup on the correction-storage capacitors. The output swing is slightly reduced. ICL7650S + C 0.1μF C CR 0.1μF OUTPUT Application Information Detailed Description AMPLIFIER The functional diagram shows the major elements of the ICL7650S. There are two amplifiers, the main amplifier, and the nulling amplifier. Both have offset-null capability. The main amplifier is connected continuously from the input to the output, while the nulling amplifier, under the control of the chopping oscillator and clock circuit, alternately nulls itself and the main amplifier. The nulling connections, which are MOSFET gates, are inherently high impedance, and two external capacitors provide the required storage of the nulling potentials and the necessary nulling-loop time constants. The nulling arrangement operates over the full common-mode and power-supply ranges, and is also independent of the output level, thus giving exceptionally high CMRR, PSRR, and AVOL. Careful balancing of the input switches, and the inherent balance of the input circuit, minimizes chopper frequency charge injection at the input terminals, and also the feed forward-type injection into the compensation capacitor, which is the main cause of output spikes in this type of circuit. 4 FN2920.10 April 12, 2007 CLOCK The ICL7650S has an internal oscillator, giving a chopping frequency of 200Hz, available at the CLOCK OUT pin on the 14 pin devices. Provision has also been made for the use of an external clock in these parts. The INT/EXT pin has an internal pull-up and may be left open for normal operation, but to utilize an external clock this pin must be tied to V- to disable the internal clock. The external clock signal may then be applied to the EXT CLOCK IN pin. An internal divide-by-two provides the desired 50% input switching duty cycle. Since the capacitors are charged only when EXT CLOCK IN is high, a 50% to 80% positive duty cycle is recommended, especially for higher frequencies. The external clock can swing between V+ and V-. The logic threshold will be at about 2.5V below V+. Note also that a signal of about 400 Hz, with a 70% duty cycle, will be present at the EXT CLOCK IN pin with INT/EXT high or open. This is the internal clock signal before being fed to the divider. In those applications where a strobe signal is available, an alternate approach to avoid capacitor misbalancing during overload can be used. If a strobe signal is connected to EXT CLK IN so that it is low during the time that the overload signal is applied to the amplifier, neither capacitor will be charged. Since the leakage at the capacitor pins is quite low at room temperature, the typical amplifier will drift less than 10μV/s, and relatively long measurements can be made with little change in offset. COMPONENT SELECTION The two required capacitors, CEXTA and CEXTB, have optimum values depending on the clock or chopping frequency. For the preset internal clock, the correct value is 0.1μF, and to maintain the same relationship between the chopping frequency and the nulling time constant this value should be scaled approximately in proportion if an external clock is used. A high quality film type capacitor such as mylar is preferred, although a ceramic or other lower-grade capacitor may prove suitable in many applications. For quickest settling on initial turn-on, low dielectric absorption capacitors (such as polypropylene) should be used. With ceramic capacitors, several seconds may be required to settle to 1μV. STATIC PROTECTION All device pins are static-protected by the use of input diodes. However, strong static fields and discharges should be avoided, as they can cause degraded diode junction characteristics, which may result in increased input-leakage currents. LATCHUP AVOIDANCE Junction-isolated CMOS circuits inherently include a parasitic 4-layer (PNPN) structure which has characteristics similar to an SCR. Under certain circumstances this junction may be triggered into a low-impedance state, resulting in excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails should be applied to any pin. In general, the amplifier supplies must be established either at 5 the same time or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to under 1mA to avoid latchup, even under fault conditions. OUTPUT STAGE/LOAD DRIVING The output circuit is a high-impedance type (approximately 18kΩ), and therefore with loads less than this value, the chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to load resistance. For example, the open-loop gain will be 17dB lower with a 1kΩ load than with a 10kΩ load. If the amplifier is used strictly for DC, this lower gain is of little consequence, since the DC gain is typically greater than 120dB even with a 1kΩ load. However, for wideband applications, the best frequency response will be achieved with a load resistor of 10kΩ or higher. This will result in a smooth 6dB/octave response from 0.1Hz to 2MHz, with phase shifts of less than 10° in the transition region where the main amplifier takes over from the null amplifier. THERMO-ELECTRIC EFFECTS The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in thermocouple junctions of dissimilar metals, alloys, silicon, etc. Unless all junctions are at the same temperature, thermoelectric voltages typically around 0.1μV/°C, but up to tens of mV/°C for some materials, will be generated. In order to realize the extremely low offset voltages that the chopper amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components should be enclosed to eliminate air movement, especially that caused by power-dissipating elements in the system. Low thermoelectric-efficient connections should be used where possible and power supply voltages and power dissipation should be kept to a minimum. High-impedance loads are preferable, and good separation from surrounding heat-dissipating elements is advisable. GUARDING Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents of the ICL7650S. Boards must be thoroughly cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination. Even with properly cleaned and coated boards, leakage currents may cause trouble, particularly since the input pins are adjacent to pins that are at supply potentials. This leakage can be significantly reduced by using guarding to lower the voltage difference between the inputs and adjacent metal runs. The guard, which is a conductive ring surrounding the inputs, is connected to a low impedance point that is at approximately the same voltage as the inputs. Leakage currents from high-voltage pins are then absorbed by the guard. FN2920.10 April 12, 2007 INPUT R1 + R2 OUTPUT INPUT + OUTPUT FIGURE 1A. INVERTING AMPLIFIER R2 FIGURE 1B. FOLLOWER + R1 INPUT OUTPUT R1 R2 NOTE: --------------------R1 + R2 SHOULD BE LOW IMPEDANCE FOR OPTIMUM GUARDING FIGURE 1C. NON-INVERTING AMPLIFIER FIGURE 1. CONNECTION OF INPUT GUARDS PIN COMPATIBILITY The basic pinout of the 8-pin device corresponds, where possible, to that of the industry standard 8-pin devices, the LM741, LM101, etc. The null-storing external capacitors are connected to pins 1 and 8, usually used for offset null or compensation capacitors, or simply not connected. In the case of the OP-05 and OP-07 devices, the replacement of the offset-null pot, connected between pins 1 and 8 and V+, by two capacitors from those pins to pin 5, will provide easy compatibility. As for the LM108, replacement of the compensation capacitor between pins 1 and 8 by the two capacitors to pin 5 is all that is necessary. The same operation, with the removal of any connection to pin 5, will suffice for the LM101, μA748, and similar parts. The 14-pin device pinout corresponds most closely to that of the LM108 device, owing to the provision of “NC” pins for guarding between the input and all other pins. Since this device does not use any of the extra pins, and has no provision for offset-nulling, but requires a compensation capacitor, some changes will be required in layout to convert it to the ICL7650S. as shown in Figure 4, to enable the full output capabilities of the LM741 (or any other standard device) to be combined with the input capabilities of the ICL7650S. The pair form a composite device, so loop gain stability, when the feedback network is added, should be watched carefully. 0.1μF C INPUT + C 7650S R 0.1μF - OUTPUT R2 R1 CLAMP R3 R3 + (R1||R2) ≥ 100kΩ For Full Clamp Effect NOTE: R1||R2 indicates the parallel combination of R1 and R2. FIGURE 2. NON INVERTING AMPLIFIER WITH OPTIONAL CLAMP Typical Applications Clearly the applications of the ICL7650S will mirror those of other op amps. Anywhere that the performance of a circuit can be significantly improved by a reduction of input-offset voltage and bias current, the ICL7650S is the logical choice. Basic non-inverting and inverting amplifier circuits are shown in Figures 2 and 3. Both circuits can use the output clamping circuit to enhance the overload recovery performance. The only limitations on the replacement of other op amps by the ICL7650S are the supply voltage (±8V Max) and the output drive capability (10kΩ load for full swing). Even these limitations can be overcome using a simple booster circuit, 6 Figure 5 shows the use of the clamp circuit to advantage in a zero-offset comparator. The usual problems in using a chopper stabilized amplifier in this application are avoided, since the clamp circuit forces the inverting input to follow the input signal. The threshold input must tolerate the output clamp current ≈ VlN/R without disturbing other portions of the system. The pin configuration of the 14 pin dual in-line package is designed to facilitate guarding, since the pins adjacent to the inputs are not used (this is different from the standard 741 and 101A pin configuration, but corresponds to that of the LM108). FN2920.10 April 12, 2007 R2 R1 INPUT CLAMP IN OUTPUT -7.5V 0.1μF 0.1μF CLAMP + 7650S +7.5V + 741 +15V OUT -15V 0.1μF 10kΩ 10kΩ 7650S + C R C - - 0.1μF (R1||R2) ≥ 100kΩ For Full Clamp Effect NOTE: R1||R2 indicates the parallel combination of R1 and R2. FIGURE 3. INVERTING AMPLIFIER WITH (OPTIONAL) CLAMP FIGURE 4. USING 741 TO BOOST OUTPUT DRIVE CAPACITY 0.1μF C VIN + C 7650S R 0.1μF CLAMP R VOUT 200kΩ - 2MΩ VTH FIGURE 5. LOW OFFSET COMPARATOR VREF (+15V) RREF IREF 16 13 V+ R5 2kΩ 12 ICL7650S + IIN 2 VIN RIN 1 33kΩ 5 33kΩ 4 Q1 Q2 R3 A1 + - + A2 - VOUT 10 ICL8048 GROUND 150pF C1 7 GAIN 15 R1 15.9kΩ 680Ω (LOW T.C.) R2 1kΩ R0 10kΩ NOTE: For further Applications Assistance, see AN053. FIGURE 6. ICL8048 OFFSET NULLED BY ICL7650S Normal logarithmic amplifiers are limited in dynamic range in the voltage-input mode by their input-offset voltage. The built-in temperature compensation and convenience features of the ICL8048 can be extended to a voltage-input dynamic range of close to 6 decades by using the ICL7650S to offset-null the ICL8048, as shown in Figure 6. The same concept can also be used with such devices as the HA2500 or HA2600 families of op amps to add very low offset voltage capability to their very high slew rates and bandwidths. Note that these circuits will also have their DC gains, CMRR, and PSRR enhanced. 7 FN2920.10 April 12, 2007 Typical Performance Curves 3 3 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 2 2 1 1 0 4 6 8 10 12 14 16 TOTAL SUPPLY VOLTAGE (V) 0 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 8. SUPPLY CURRENT vs AMBIENT TEMPERATURE 8 MAXIMUM OUTPUT CURRENT (mA) COMMON MODE VOLTAGE LIMIT 6 4 2 0 -10 -20 -30 2 4 6 8 10 12 14 16 TOTAL SUPPLY VOLTAGE (V) 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE (±V) 6 7 8 POSITIVE LIMIT NEGATIVE LIMIT FIGURE 9. MAXIMUM OUTPUT CURRENT vs SUPPLY VOLTAGE FIGURE 10. COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE CLOCK RIPPLE DUE TO LEAKAGE CURRENT AT CAP PINS (μVP-P REFERRED TO INPUT) 4 10Hz NOISE VOLTAGE (μVP-P) 150 100 BROADBAND NOISE (AV = 1000) 10 0.1μF 3 2 1.0μF 1 1 0.1 25 50 75 100 TEMPERATURE (oC) 125 0 10 100 1k CHOPPING FREQUENCY - CLOCK OUT (Hz) 10k FIGURE 11. CLOCK RIPPLE REFERRED TO THE INPUT vs TEMPERATURE FIGURE 12. 10Hz NOISE VOLTAGE vs CHOPPING FREQUENCY 8 FN2920.10 April 12, 2007 Typical Performance Curves 3 INPUT OFFSET VOLTAGE CHANGE (μV) (Continued) 8 2 OFFSET VOLTAGE (μV) 6 1 0 4 -1 -2 2 -3 4 6 8 10 12 14 16 TOTAL SUPPLY VOLTAGE (V) 0 10 100 1k 10k CHOPPING FREQUENCY - CLOCK OUT (Hz) FIGURE 13. INPUT OFFSET VOLTAGE CHANGE vs SUPPLY VOLTAGE FIGURE 14. INPUT OFFSET VOLTAGE vs CHOPPING FREQUENCY 160 140 OPEN LOOP GAIN (dB) 120 RL = 10kΩ CEXT = 0.1μF 50 70 PHASE SHIFT (°) OUTPUT (mV) 20mV/DIV. 1ms/DIV. 20 0 20 100 90 80 110 60 130 40 20 0.01 1 2 3 4 5 6 7 8 9 0.1 1 TIME (ms) 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 15. OUTPUT WITH ZERO INPUT; GAIN = 1000; BALANCED SOURCE IMPEDANCE = 10kΩ FIGURE 16. OPEN LOOP GAIN AND PHASE SHIFT vs FREQUENCY 9 FN2920.10 April 12, 2007 Typical Performance Curves (Continued) 160 140 OPEN LOOP GAIN (dB) 120 OUTPUT VOLTAGE (V) RL = 10kΩ CEXT = 1μF 50 PHASE SHIFT (°) 70 2 1 0 -1 -2 CLOCK OUT LOW CLOCK OUT HIGH 100 90 80 110 60 130 40 0 20 0.01 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 0.5 1.0 1.5 TIME (μs) 2.0 2.5 NOTE: The two different responses correspond to the two phases of the clock. FIGURE 18. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (NOTE) 100μA N-CHANNEL CLAMP CURRENT 2.0 FIGURE 17. OPEN LOOP GAIN AND PHASE SHIFT vs FREQUENCY 2 OUTPUT VOLTAGE (V) 10μA 1 μA 100nA 10nA 1nA 100pA 10pA 1pA 0.8 0.6 0.4 0.2 0 1 0 CLOCK OUT HIGH -1 CLOCK OUT LOW -2 0 0.5 1.0 TIME (μS) 1.5 NOTE: The two different responses correspond to the two phases of the clock. FIGURE 19. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (NOTE) 100μA P-CHANNEL CLAMP CURRENT 10μA 1 μA 100nA 10nA 1nA 100pA 10pA 1pA -0.8 -0.6 -0.4 OUTPUT VOLTAGE (ΔV+) -0.2 OUTPUT VOLTAGE (ΔV-) FIGURE 20. N-CHANNEL CLAMP CURRENT vs OUTPUT VOLTAGE 0 FIGURE 21. P-CHANNEL CLAMP CURRENT vs OUTPUT VOLTAGE 10 FN2920.10 April 12, 2007 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E eA eC C -C- e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 11 FN2920.10 April 12, 2007 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 -C- A2 B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 12 FN2920.10 April 12, 2007 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8° 0° 8° MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0° MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 A1 B C D E e C α µ A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS H h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN2920.10 April 12, 2007