7667CPAZ

® ICL7667 Data Sheet April 4, 2006 FN2853.5 Dual Power MOSFET Driver The ICL7667 is a dual monolithic high-speed driver designed to convert TTL level signals into high current outputs at voltages up to 15V. Its high speed and current output enable it to drive large capacitive loads with high slew rates and low propagation delays. With an output voltage swing only millivolts less than the supply voltage and a maximum supply voltage of 15V, the ICL7667 is well suited for driving power MOSFETs in high frequency switched-mode power converters. The ICL7667’s high current outputs minimize power losses in the power MOSFETs by rapidly charging and discharging the gate capacitance. The ICL7667’s inputs are TTL compatible and can be directly driven by common pulse-width modulation control ICs. Features • Fast Rise and Fall Times - 30ns with 1000pF Load • Wide Supply Voltage Range - VCC = 4.5V to 15V • Low Power Consumption - 4mW with Inputs Low - 20mW with Inputs High • TTL/CMOS Input Compatible Power Driver - ROUT = 7Ω Typ • Direct Interface with Common PWM Control ICs • Pin Equivalent to DS0026/DS0056; TSC426 • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER ICL7667CBA ICL7667CBA-T ICL7667CBAZA (Note) PART MARKING 7667CBA 7667CBA 7667CBAZ TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE PKG. DWG. # Applications • Switching Power Supplies • DC/DC Converters • Motor Controllers 8 Ld SOIC (N) M8.15 8 Ld SOIC (N) M8.15 Tape and Reel 8 Ld SOIC (N) M8.15 (Pb-free) 8 Ld SOIC (N) M8.15 Tape and Reel (Pb-free) 8 Ld PDIP 8 Ld PDIP* (Pb-free) E8.3 E8.3 Pinout ICL7667 (PDIP, SOIC) TOP VIEW ICL7667CBAZA-T 7667CBAZ (Note) ICL7667CPA ICL7667CPAZ (Note) 7667CPA 7667CPAZ 0 to 70 0 to 70 N/C IN A VIN B 1 2 3 4 8 7 6 5 N/C OUT A V+ OUT B *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Diagram VCC ≈ 2mA OUT IN 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL7667 Absolute Maximum Ratings Supply Voltage V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3V to V+ +0.3V Package Dissipation, TA 25oC. . . . . . . . . . . . . . . . . . . . . . . .500mW Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC(oC/W) PDIP Package* . . . . . . . . . . . . . . . . . . 150 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 170 N/A Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Temperature Range ICL7667C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC ICL7667M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications ICL7667C, M TA = 25oC PARAMETER DC SPECIFICATIONS Logic 1 Input Voltage Logic 1 Input Voltage Logic 0 Input Voltage Logic 0 Input Voltage Input Current Output Voltage High Output Voltage Low Output Resistance Output Resistance Power Supply Current Power Supply Current VIH VIH VIL VIL IIL VOH VOL ROUT ROUT ICC ICC VCC = 4.5V VCC = 15V VCC = 4.5V VCC = 15V VCC = 15V, VIN = 0V and 15V VCC = 4.5V and 15V VCC = 4.5V and 15V VIN = VIL, IOUT = -10mA, VCC = 15V VIN = VIH, IOUT = 10mA, VCC = 15V VCC = 15V, VIN = 3V both inputs VCC = 15V, VIN = 0V both inputs 2.0 2.0 -0.1 VCC -0.05 VCC 0 7 8 5 150 0.8 0.8 0.1 0.05 10 12 7 400 2.0 2.0 -0.1 VCC -0.1 VCC 0.5 0.5 0.1 0.1 12 13 8 400 V V V V µA V V Ω Ω mA µA SYMBOL TEST CONDITIONS MIN TYP MAX ICL7667M -55oC ≤ TA ≤ 125oC MIN TYP MAX UNITS SWITCHING SPECIFICATIONS Delay Time Rise Time Fall Time Delay Time TD2 TR TF TD1 Figure 3 Figure 3 Figure 3 Figure 3 35 20 20 20 50 30 30 30 60 40 40 40 ns ns ns ns NOTE: All typical values have been characterized but are not tested. 2 FN2853.5 April 4, 2006 ICL7667 Test Circuits V- = 15V +5V 90% + 4.7µF INPUT ICL7667 INPUT RISE AND FALL TIMES ≤ 10ns OUTPUT 0V 10% 10% INPUT 0.1µF 10% ≈0.4V OUTPUT CL = 1000pF 15V TD1 tf 90% TD2 tr 90% Typical Performance Curves 1µs VCC = 15V 100 90 80 100 tr AND tf , (ns) tRISE TD1 AND TD2, (ns) 70 60 50 40 30 20 10 1 10 100 1000 CL (pF) 10K 100K 0 -55 0 25 70 TEMPERATURE (oC) 125 TD1 TD2 CL = 1nF VCC = 15V 10 tFALL FIGURE 1. RISE AND FALL TIMES vs CL 50 30 FIGURE 2. TD1, TD2 vs TEMPERATURE VCC = 15V 40 tr AND tf , (ns) tr AND tf 10 CL = 1nF VCC = 15V 20 ICC (mA) 30 20kHz 200kHz 3.0 10 0 -55 0 25 70 125 TEMPERATURE (oC) 1 10 100 1K CL (pF) 10K 100K FIGURE 3. tr , tf vs TEMPERATURE FIGURE 4. ICC vs CL 3 FN2853.5 April 4, 2006 ICL7667 Typical Performance Curves (Continued) 100 100 ICC (mA) ICC (mA) VCC = 15V 10 10 VCC = 15V VCC = 5V 1 1 VCC = 5V CL = 10pF 100k 1M 10M 100µA 10K 100K CL = 1nF 1M 10M 100mA 10k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. ICC vs FREQUENCY 50 50 FIGURE 6. NO LOAD ICC vs FREQUENCY 40 40 tD1 AND tf , (ns) tr AND tD2 , (ns) 30 tf 20 tD1 10 CL = 1nF 0 5 30 tr = TD2 20 10 CL = 10pF 0 5 10 15 10 VCC (V) 15 VCC (V) FIGURE 7. DELAY AND FALL TIMES vs VCC FIGURE 8. RISE TIME vs VCC Detailed Description The ICL7667 is a dual high-power CMOS inverter whose inputs respond to TTL levels while the outputs can swing as high as 15V. Its high output current enables it to rapidly charge and discharge the gate capacitance of power MOSFETs, minimizing the switching losses in switchmode power supplies. Since the output stage is CMOS, the output will swing to within millivolts of both ground and VCC without any external parts or extra power supplies as required by the DS0026/56 family. Although most specifications are at VCC = 15V, the propagation delays and specifications are almost independent of VCC . In addition to power MOS drivers, the ICL7667 is well suited for other applications such as bus, control signal, and clock drivers on large memory of microprocessor boards, where the load capacitance is large and low propagation delays are required. Other potential applications include peripheral power drivers and charge-pump voltage inverters. 4 Input Stage The input stage is a large N-Channel FET with a P-channel constant-current source. This circuit has a threshold of about 1.5V, relatively independent of the VCC voltage. This means that the inputs will be directly compatible with TTL over the entire 4.5V - 15V VCC range. Being CMOS, the inputs draw less than 1µA of current over the entire input voltage range of ground to VCC. The quiescent current or no load supply current of the ICL7667 is affected by the input voltage, going to nearly zero when the inputs are at the 0 logic level and rising to 7mA maximum when both inputs are at the 1 logic level. A small amount of hysteresis, about 50mV to 100mV at the input, is generated by positive feedback around the second stage. Output Stage The ICL7667 output is a high-power CMOS inverter, swinging between ground and VCC. At VCC = 15V, the output impedance of the inverter is typically 7Ω . The high FN2853.5 April 4, 2006 ICL7667 peak current capability of the ICL7667 enables it to drive a 1000pF load with a rise time of only 40ns. Because the output stage impedance is very low, up to 300mA will flow through the series N-Channel and P-channel output devices (from VCC to ground) during output transitions. This crossover current is responsible for a significant portion of the internal power dissipation of the ICL7667 at high frequencies. It can be minimized by keeping the rise and fall times of the input to the ICL7667 below 1µs. 7. Output stage I2R power loss The sum of the above must stay within the specified limits for reliable operation. As noted above, the input inverter current is input voltage dependent, with an ICC of 0.1mA maximum with a logic 0 input and 6mA maximum with a logic 1 input. The output stage crowbar current is the current that flows through the series N-Channel and P-channel devices that form the output. This current, about 300mA, occurs only during output transitions. Caution: The inputs should never be allowed to remain between VIL and VIH since this could leave the output stage in a high current mode, rapidly leading to destruction of the device. If only one of the drivers is being used, be sure to tie the unused input to a ground. NEVER leave an input floating. The average supply current drawn by the output stage is frequency dependent, as can be seen in ICC vs Frequency graph in the Typical Characteristics Graphs. The output stage I2R power dissipation is nothing more than the product of the output current times the voltage drop across the output device. In addition to the current drawn by any resistive load, there will be an output current due to the charging and discharging of the load capacitance. In most high frequency circuits the current used to charge and discharge capacitance dominates, and the power dissipation is approximately PAC = CVCC2f where C = Load Capacitance, f = Frequency In cases where the load is a power MOSFET and the gate drive requirement are described in terms of gate charge, the ICL7667 power dissipation will be PAC = QGVCCf where QG = Charge required to switch the gate, in Coulombs, f = Frequency. Application Notes Although the ICL7667 is simply a dual level-shifting inverter, there are several areas to which careful attention must be paid. Grounding Since the input and the high current output current paths both include the ground pin, it is very important to minimize and common impedance in the ground return. Since the ICL7667 is an inverter, any common impedance will generate negative feedback, and will degrade the delay, rise and fall times. Use a ground plane if possible, or use separate ground returns for the input and output circuits. To minimize any common inductance in the ground return, separate the input and output circuit ground returns as close to the ICL7667 as is possible. Bypassing The rapid charging and discharging of the load capacitance requires very high current spikes from the power supplies. A parallel combination of capacitors that has a low impedance over a wide frequency range should be used. A 4.7µF tantalum capacitor in parallel with a low inductance 0.1µF capacitor is usually sufficient bypassing. Output Damping Ringing is a common problem in any circuit with very fast rise or fall times. Such ringing will be aggravated by long inductive lines with capacitive loads. Techniques to reduce ringing include: 1. Reduce inductance by making printed circuit board traces as short as possible. 2. Reduce inductance by using a ground plane or by closely coupling the output lines to their return paths. 3. Use a 10Ω to 30Ω resistor in series with the output of the ICL7667. Although this reduces ringing, it will also slightly increase the rise and fall times. 4. Use good bypassing techniques to prevent supply voltage ringing. Power MOS Driver Circuits Power MOS Driver Requirements Because it has a very high peak current output, the ICL7667 the at driving the gate of power MOS devices. The high current output is important since it minimizes the time the power MOS device is in the linear region. Figure 9 is a typical curve of charge vs gate voltage for a power MOSFET. The flat region is caused by the Miller capacitance, where the drain-to-gate capacitance is multiplied by the voltage gain of the FET. This increase in capacitance occurs while the power MOSFET is in the linear region and is dissipating significant amounts of power. The very high current output of the ICL7667 is able to rapidly overcome this high capacitance and quickly turns the MOSFET fully on or off. Power Dissipation The power dissipation of the ICL7667 has three main components: 5. Input inverter current loss 6. Output stage crossover current loss 5 FN2853.5 April 4, 2006 ICL7667 Transformer Coupled Drive of MOSFETs 18 16 GATE TO SOURCE VOLTAGE 14 12 10 8 6 4 2 0 -2 0 2 4 6 8 10 12 14 16 18 GATE CHARGE - QG (NANO-COULOMBS) 20 212pF 680pF VDD = 200V 630pF VDD = 375V ID = 1A VDD = 50V Transformers are often used for isolation between the logic and control section and the power section of a switching regulator. The high output drive capability of the ICL7667 enables it to directly drive such transformers. Figure 11 shows a typical transformer coupled drive circuit. PWM ICs with either active high or active low output can be used in this circuit, since any inversion required can be obtained by reversing the windings on the secondaries. Buffered Drivers for Multiple MOSFETs In very high power applications which use a group of MOSFETs in parallel, the input capacitance may be very large and it can be difficult to charge and discharge quickly. Figure 13 shows a circuit which works very well with very large capacitance loads. When the input of the driver is zero, Q1 is held in conduction by the lower half of the ICL7667 and Q2 is clamped off by Q1. When the input goes positive, Q1 is turned off and a current pulse is applied to the gate of Q2 by the upper half of the ICL7667 through the transformer, T1. After about 20ns, T1 saturates and Q2 is held on by its own CGS and the bootstrap circuit of C1, D1 and R1. This bootstrap circuit may not be needed at frequencies greater than 10kHz since the input capacitance of Q2 discharges slowly. FIGURE 9. MOSFET GATE DYNAMIC CHARACTERISTICS Direct Drive of MOSFETs Figure 11 shows interfaces between the ICL7667 and typical switching regulator ICs. Note that unlike the DS0026, the ICL7667 does not need a dropping resistor and speedup capacitor between it and the regulator IC. The ICL7667, with its high slew rate and high voltage drive can directly drive the gate of the MOSFET. The SG1527 IC is the same as the SG1525 IC, except that the outputs are inverted. This inversion is needed since ICL7667 is an inverting buffer. 15V +165VDC +VC A +V IRF730 SG1527 B GND ICL7667 IRF730 -V FIGURE 10A. 15V +165VDC +VC C1 E1 TL494 C2 E2 GND +15V 1K -V ICL7667 IRF730 1K +V IRF730 VOUT FIGURE 10B. FIGURE 10. DIRECT DRIVE OF MOSFET GATES 6 FN2853.5 April 4, 2006 ICL7667 18V CA CB VIN EA 470 +V 1 µF +165V IRF730 0V ICL7667 1 µF CA1524 EB 470 IRF730 -165V -V VOUT FIGURE 11. TRANSFORMER COUPLED DRIVE CIRCUIT V+ 0.1µF + 4.7µF R1 10k IN914 D1 4.7µF 0.1µF Q2 1/2 ICL7667 2200pF FF10 IRFF120 1000pF C1 0V - 5V INPUT FROM PWM IC 5FF10 1/2 ICL7667 ZL IRFF120 Q1 FIGURE 12. VERY HIGH SPEED DRIVER -4 f = 10kHz -6 -8 VOUT (V) SLOPE = 60Ω -10 -12 1kHz - 250kHz SQUARE WAVE IN TTL LEVELS + 1/2 ICL7667 IN4001 -13.5V IN4001 47µF + -14 +15V 10µF 5 20 40 60 IOUT (mA) 80 100 FIGURE 13A. FIGURE 13B. OUTPUT CURRENT vs OUTPUT VOLTAGE FIGURE 13. VOLTAGE INVERTER 7 FN2853.5 April 4, 2006 ICL7667 Other Applications Relay and Lamp Drivers The ICL7667 is suitable for converting low power TTL or CMOS signals into high current, high voltage outputs for relays, lamps and other loads. Unlike many other level translator/driver ICs, the ICL7667 will both source and sink current. The continuous output current is limited to 200mA by the I2R power dissipation in the output FETs. Clock Driver Some microprocessors (such as the CDP68HC05 families) use a clock signal to control the various LSI peripherals of the family. The ICL7667s combination of low propagation delay, high current drive capability and wide voltage swing make it attractive for this application. Although the ICL7667 is primarily intended for driving power MOSFET gates at 15V, the ICL7667 also works well as a 5V high-speed buffer. Unlike standard 4000 series CMOS, the ICL7667 uses short channel length FETs and the ICL7667 is only slightly slower at 5V than at 15V. +15V 1kHz - 250kHz SQUARE WAVE IN TTL LEVELS + 1/2 ICL7667 IN4001 + 47µF +15 IN4001 28.5V 10µF Charge Pump or Voltage Inverters and Doublers The low output impedance and wide VCC range of the ICL7667 make it well suited for charge pump circuits. Figure 13A shows a typical charge pump voltage inverter circuit and a typical performance curve. A common use of this circuit is to provide a low current negative supply for analog circuitry or RS232 drivers. With an input voltage of +15V, this circuit will deliver 20mA at -12.6V. By increasing the size of the capacitors, the current capability can be increased and the voltage loss decreased. The practical range of the input frequency is 500Hz to 250kHz. As the frequency goes up, the charge pump capacitors can be made smaller, but the internal losses in the ICL7667 will rise, reducing the circuit efficiency. Figure 14, a voltage doubler, is very similar in both circuitry and performance. A potential use of Figure 13 would be to supply the higher voltage needed for EEPROM or EPROM programming. FIGURE 14. VOLTAGE DOUBLER All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN2853.5 April 4, 2006